eaw/SharpMZ
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Initial commit

Browse Source
This commit is contained in:
Philip Smart
2019-10-25 17:16:34 +01:00
commit 4a64af4a00
252 changed files with 134777 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

333
README.md Normal file
View File

@@ -0,0 +1,333 @@
# Sharp MZ Series Personal and Business Computer Emulation
Written by Philip Smart, 2018 for the Terasic DE10 Nano board under the MiSTer framework.
This project aims to provide full emulation (along with extensions) of the Sharp MZ Series Computers.
The following emulations have been written
- MZ80K
- MZ80C
- MZ1200
- MZ80A
- MZ700
and the following are under development:
- MZ800
- MZ80B
- MZ2000
The current emulations provide:
- 48K RAM for MZ80K,C,1200,A
- 64K RAM for MZ700
- Hardware Tape Read/Write with selectable 1x - 32x Fast Mode
- Turbo Mode 1x - 32x (ie. 112MHz for MZ700)
- Programmable Character Generator (PCG-8000/PCG-1200)
- 40x25, 80x25 Mono and Colour Display Modes
- 320x200, 640x200 8 Colour Bit addressed Graphics
- Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type.
- i8253 mono audio
### Enhancements in test/under development:
- Floppy Disk Drive/Controller 5.25"
- Quick Disk Controller
- Dual digital Joystick Input (MZ700)
### Known Issues
- Tape Write isn’t working correctly, I made some structural changes resulting in it no longer working, so this needs to be resolved.
- Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A.
- HDMI needs to be re-enabled in the design.
- The Aspect Ratio/Scandoubler options aren’t working on the VGA output.
## Installation
1. Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide
2. Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:-
scp SharpMZ_MiSTer/releases/SharpMZ_\<date\>.rbf root@\<de10 ip address\>/media/fat/SharpMZ.rbf
Target name can be anything you like ending with .rbf
3. Make a SharpMZ directory on the SD card, ie:
ssh root@\<de10 ip address\>
mkdir /media/fat/SharpMZ
4. Copy any Rom Files, MZF Tape Files, DSK files across to the new directory, ie:
scp \*.mzf root@\<de10 ip address\>:/media/fat/SharpMZ/
5. Start the MiSTer menu (ie. press the DE10 reset button if it is not showing).
6. Select the SharpMZ core (or whatever name you called it).
7. The emulator will boot into an MZ80K model with the SP-1002 monitor.
8. Press F12 to change the configuration, select Save Config to store it.
## Detail
### Design Summary
The idea of this design is to keep the emulation as independent of the HPS as possible (so it works standalone), only needing the HPS to set control registers,
read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
### Menu System
The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the display parameters, debugging and access to the MiSTer control menu.
### Tape Storage
In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved on to Floppy/Quick Disks.
This menu controls the hardware CMT unit and has the following choices:
- Load direct to RAM
This option allows you to load an MZF format tape file (ie. 128 bytes header + code) directly into RAM. It uses the Load Address and Size stored in the header in order to correctly locate the code and also stores the header in the Cassette Work area at 10F0H. After load is completed and warm reset is made, the details of the tape are displayed on-screen. In order to run the loaded program, simply issue the correct monitor command, ie. J1200 (Jump to 1200H where 1200H is shown as the Execution Address in the tape summary).
- Queue Tape
A real cassette has 1 or more programs stored on it sequentially. The emulation cache only stores 1 full program so this is a mechanism to line up multiple programs and they will be fed into the emulation cache as it becomes empty, thus simulating a real cassette.
Selecting this option presents you with a directory listing of all MZF files. Choose one per selection and it will be added to the Queue. The programs queued will be displayed on the menu.
- Clear Queue
This option allows you to purge all queue entries.
- Save Tape
This option allows you to save a program to the MiSTer SD card which is in the emulation cache. Normally the emulation would have written a program/data to tape (ie. via the BASIC ‘SAVE’ command) which in reality is stored in the emulation cache.
The tape is saved under the name given in the emulation save command (ie. in BASIC ‘SAVE “myfile”’ would result in a file called myfile.mzf being saved).
- Auto Save Tape
This option allows you to auto save the emulation cache. Ie. when an emulation save completes, a flag is raised which is seen by the MiSTer program and the emulation cache is saved to SD under the name given in the emulation.
- Tape Buttons
This option allows you to set the active Tape buttons, ie. Play, Record or Auto. Auto is a hardware mechanism to detect if the emulation is reading or writing to tape and process accordingly.
- Fast Tape Load
This option allows you to set the speed of the tape drive. On the original machines, the tape runs at 1200baud which is quite slow, so use of this option is recommended.
You can select one of: "Off", "2x", "4x", "8x", "16x", "32x"
Selecting “Off” runs the tape drive at the original speed.
### Machine
The emulation emulates several Sharp MZ computers and this menu allows you to make selections accordingly.
- Machine Model
This option allows you to choose which Sharp MZ computer is emulated. Currently the choices are:
"MZ80K", "MZ80C", "MZ1200", "MZ80A", "MZ700" with "MZ800", "MZ80B", "MZ2000" in the pipeline.
- CPU Speed
This option allows you to set the speed at which the emulation runs. Generally speaking, higher speeds can be beneficial in non-graphics based applications although some games benefit from a small speed boost. The choices are:
- MZ80K/C/1200/A => "2MHz", "4MHz", "8MHz", "16MHz", "32MHz", "64MHz"
- MZ700 => "3.5MHz", "7MHz", "14MHz", "28MHz", "56MHz", "112MHz"
- Audio Source
This option allows you to choose what is played through the audio output. The choices are:
- Sound => The mono audio generated by the emulation output on L/R channels.
- Tape => The CMT signals as sound, Playback on Right channel, Record on Left channel. In theory you should be able to connect the right channel to an external tape drive and record to physical tape.
- Audio Volume
This option allows you to set the output volume. There are 16 possible steps from Min .. Max.
- Audio Mute
This option allows you to Mute the output.
- Rom Management
The emulation comes with the Monitor, Character Generator and Key Mapping Roms built-in for each machine emulated. This option selects a sub-menu which allows you to upload non-standard Roms when the emulation is started (ie. the Core is selected).
- Machine Model
This option allows you to select the emulated Sharp MZ computer to which the custom rom images will affect. The choices are:
"MZ80K", "MZ80C", "MZ1200", "MZ80A", "MZ700" with "MZ800", "MZ80B", "MZ2000" in the pipeline.
- User ROM
On some machine models (ie. MZ80A) there exists a socket to place a User ROM, which will have control passed to it should the first byte be 0 and non-writeable. Although this option only exists on certain models, it is a nice to have feature it is available for all machine models.
This option allows you to enable or disable the User ROM (NB. If you enable this option, it only enables hardware select, you still need to upload a ROM which has the first byte set to 0).
- Floppy Disk ROM
A Floppy Disk drive was an expansion option for the Sharp MZ computers, and with the advent of the MZ700, a Quick Disk drive was also an option. These options typically held control software in a ROM at location F000H. This option allows you to enable this feature, albeit you still need to upload a ROM.
- Enable Custom Rom
This section allows you to enable custom Roms and select the image which will be uploaded. For each Rom, you can enable or disable. If enabled, you can choose the required file. The Roms which can be customized are:
- Monitor (40x25)
- Monitor (80x25)
- Char Generator
- Key Mapping
- User Rom
- Floppy Disk
The Monitor Rom is a special case. Most of the Personal Sharp MZ Computers were only able to display 40x25 characters so the Rom hardcodes these parameters. Some people required wider screens for use with CPM, so hardware modifications were made to create an 80x25 display. The emulation is capable of both modes but in order to run correctly, a different Monitor Rom for 80x25 display is needed.
### Display
The display on the Sharp MZ computers was originally quite simplistic. In order to cater for enhancements made in each model and by external vendors, the emulation has several configurable parameters which are grouped under this menu.
- Display Type
This option allows you to select the display used. Normally, when a machine model is chosen, it defaults to the original display, this option allows you to override the default. The choices are:
"Mono 40x25", "Mono 80x25 ", "Colour 40x25", "Colour 80x25"
- Video
An extension to the original design was the addition of a graphics frame buffer. It is possible to blend the original display video with the graphics frame buffer. This option allows you to enable or disable the original display video (ie. if you only want graphics).
- Graphics
There were various add-on boards made available in order to display bit addressable pixel graphics. This is my extension to the original design and as I gather information on other add-on boards, I will adapt the hardware interface so it accommodates these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
- VRAM CPU Wait
I deviated from the original design by adding a pixel based display buffer. During the Vertical Blanking period, I expand the character based VRAM and Attribute RAM into pixels and store them in the display buffer (a double buffer technique). This consequently means that no snow/tearing will occur if the CPU accesses the VRAM/Attribute RAM during the visible display period. The original design added software waits (MZ80K) and hardware CPU wait states (MZ80A/700) to eliminate snow/tearing and due to the addition of double buffering, this is no longer needed. You can thus disable the wait states with this option and gain some speed or enable them to keep compatibility.
- PCG Mode
All of the Sharp MZ computers used character generators which were hard coded in a ROM. External vendors offered add-ons to allow for a Programmable Character Generator based in RAM. This option enables the Programmable Character Generator which is compatible with the HAL PCG-8000/PCG-1200 add-ons.
- Aspect Ratio
This option is a MiSTer framework extension which converts the Aspect Ratio from 4:3 to 16:9. It doesn’t work at the moment with VGA output but should work on HDMI. Use this option to choose the desired format.
- Scandoubler
This option is a MiSTer framework extension which doubles the scan lines to widen/improve the image of older computer displays. It doesn’t work correctly with VGA output at the moment but should work on HDMI.
The choices are: "None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%"
### System
This is the MiSTer main control menu which allows you to select a core, map keys etc.
### Debugging
As you cannot easily get out a trusty Oscilloscope or write breakpoint/debug messages with an FPGA, I’ve added a debugging mode which can be used at any time without affecting the emulation (unless you choose a debug frequency in which case the emulation will run at the selected frequency).
Basically, the 8 LED’s on the main DE10 main board can display a selectable set of signals, either in auto mode (move from set to set after a fixed period) or a static set. The sample rate of the signals displayed on the LED’s is selectable from the Z80 CPU frequency down to 1Hz. You can also attach an oscilloscope onto the LED’s and thus see the waveform if a simple flicker is not sufficient. In addition, you can slow the CPU frequency down in steps from 1MHz to 1/10Hz so you have a good chance of seeing what is happening internally.
This debugging addition is also a great method of understanding the internals of a computer and seeing the Z80 in action.
To use the debug mode, press F12 to enter the MiSTer menu, then select Debug and you are offered the following choices:
- Select Memory Bank
This option allows you to select one of the memory banks so it can be written to a local (DE10 SD Card) file.
- SysROM = System ROM. This is the complete concatenated set of Monitor ROM’s for all the emulations.
- SysRAM = System RAM. This is the 64K Main RAM.
- KeyMap = Key Mapping ROM. This is the complete concatenated set of Key Mapping’s for all the emulations.
- VRAM = Video RAM. This is the 2K Video RAM concatenated with the 2K Attribute RAM.
- CMTHDR = Cassette Header. This is the 128 byte memory holding the last loaded or saved tape header.
- CMTDATA = Cassette Data. This is the 64K memory holding the last loaded or saved tape data.
- CGROM = Character Generator ROM. This is the complete concatenated set of CGROM’s for all the emulations.
- CGRAM = Character Generator RAM. This is the 2K contents of the Programmable Character Generator RAM.
- All = This is the complete memory set as one file.
- Dump To <memory bank name>
Dump the selected memory bank. The system will show the file name used for the dump.
- Debug Mode
Select to Enable or Disable
- CPU Frequency
Select the CPU Frequency which can be one of:
"CPU/CMT", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz"
- Debug LEDS
Select to Enable or Disable
- Sample Freq
This is the sampling frequency used to sample the displayed signals. It can be one of:
"CPU/CMT", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz"
- Signal Block
This is the signal block for display. It can be one of:
- T80 => CPU Address/Data Bus and associated signals.
- I/O => Video, Keyboard and Select signals.
- IOCTL => External I/O Control. Address/Data and Select signals.
- Config => Register configuration signals.
- MZ80C I => 5 sets of signals relating to the MZ80K/C/1200/A/700/800.
- MZ80C II => An additional 5 sets of signals.
- MZ80B I => 5 sets of signals relating to the MZ80B/MZ2000.
- MZ80B II => An additional 5 sets of signals.
- Bank
This is the Bank within the Block to be displayed on the LED’s. It can be one of:
- T80 => "Auto", "A7-0", "A15-8", "DI", "Signals"
- I/O => "Auto", "Video", "PS2Key", "Signals"
- IOCTL => "Auto", "A23-16", "A15-8", "A7-0", "Signals"
- Config => "Auto", "Config 1", "Config 2", "Config 3", "Config 4", "Config 5"
- MZ80C I => "Auto", "CS 1", "CS 2", "CS 3", "INT/RE", "Clk"
- MZ80C II => "Auto", "CMT 1", "CMT 2", "CMT 3"
- MZ80B I => Not yet defined.
- MZ80B II => Not yet defined.
### Graphics Frame Buffer
An addition to the original design is a 640x200/320x200 8 colour Graphics frame buffer. There were many additions to the Sharp MZ series to allow graphics (ie. MZ80B comes with standard mono graphics) display and as I don’t have detailed information of these to date, I designed my own extension with the intention of adding hardware abstraction layers at a later date to add compatibility to external vendor add-ons.
This frame buffer is made up of 3x16K RAM blocks, 1 per colour with a resolution of 640x200 which matches the output display buffer bit for bit. If the display is working at 40x25 characters then the resolution is 320x200, otherwise for 80x25 it is 640x200.
The RAM for the Graphics frame buffer can be switched into the main CPU address range C000H – FFFFH by programmable registers, 1 bank at a time (ie. Red, Green, Blue banks). This allows for direct CPU addressable pixels to be read and/or written. Each pixel is stored in groups of 8 (1 byte in RAM) scanning from right to left per byte, left to right per row, top to bottom. Ie. if the Red bank is mapped into CPU address space, the byte at C000H represents pixels 7 - 0 of 320/640 (X) at pixel 0 of 200 (Y). Thus 01H written to C000H would set Pixel 7 (X) on Row 0 (Y). This applies for Green and Blue banks when mapped into CPU address space.
In order to speed up display, there is a Colour Write register, so that a write to the graphics RAM will update all 3 banks at the same time.
The programmable registers are as follows:
*Switching Graphics RAM Bank into ZPU CPU Address Range*
- Graphics Bank Switch Set Register: I/O Address: E8H (232 decimal)
Switches in 1 of the 16Kb Graphics RAM pages (of the 3 pages) to C000 - FFFF. The bank which is switched in is set in the Control Register by bits 1/0 for Read operations and 3/2 for Write operations. This bank switch overrides all MZ80A/MZ700 page switching functions.
- Graphics Bank Switch Reset Register: I/O Address: E9H (233 decimal)
Switches out the Graphics RAM and returns to previous state.
*Control Register: I/O Address: EAH (234 decimal)*
- Bit 1:0
Read mode (00=Red Bank, 01=Green Bank, 10=Blue Bank, 11=Not used). Select which bank to be read when enabled in CPU address space.
- Bit 3:2
Write mode (00=Red Bank, 01=Green Bank, 10=Blue Bank, 11=Indirect). Select which bank to be written to when enabled in CPU address space.
- Bit 4
VRAM Output. 0=Enable, 1=Disable. Output Character RAM to the display.
- Bit 5
GRAM Output. 0=Enable, 1=Disable. Output Graphics RAM to the display.
- Bit 7:6
Blend Operator (00=OR ,01=AND, 10=NAND, 11=XOR). Operator to blend Character display with Graphics Display.
*Red Colour Writer Register: I/O Address: EBH (235 decimal)*
- Bit 0 Pixel 7 Set to Red during indirect write.
- Bit 1 Pixel 6
- Bit 2 Pixel 5
- Bit 3 Pixel 4
- Bit 4 Pixel 3
- Bit 5 Pixel 2
- Bit 6 Pixel 1
- Bit 7 Pixel 0 Set to Red during indirect write.
*Green Colour Writer Register: I/O Address: ECH (236 decimal)*
- Bit 0 Pixel 7 Set to Green during indirect write.
- Bit 1 Pixel 6
- Bit 2 Pixel 5
- Bit 3 Pixel 4
- Bit 4 Pixel 3
- Bit 5 Pixel 2
- Bit 6 Pixel 1
- Bit 7 Pixel 0 Set to Green during indirect write.
*Blue Colour Writer Register: I/O Address: EDH (237 decimal)*
- Bit 0 Pixel 7 Set to Blue during indirect write.
- Bit 1 Pixel 6
- Bit 2 Pixel 5
- Bit 3 Pixel 4
- Bit 4 Pixel 3
- Bit 5 Pixel 2
- Bit 6 Pixel 1
- Bit 7 Pixel 0 Set to Blue during indirect write.
For Indirect mode (Control Register bits 3/2 set to 11), a write to the Graphics RAM when mapped into CPU address space C000H – FFFFH will see the byte masked by the Red Colour Writer Register and written to the Red Bank with the same operation for Green and Blue. This allows rapid setting of a colour across the 3 banks.
## Credits
My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab and his excellent work.
Also credit to Sorgelig for his hard work in creating the MiSTer framework and design of some excellent hardware add-ons. The MiSTer framework makes it significantly easier to design/port emulations.
## Links
The Sharp MZ Series Computers were not as wide spread as Commodore, Atari or Sinclair but they had a dedicated following. Given their open design it was very easy to modify and extend applications such as the BASIC interpreters and likewise easy to add hardware extension. As such, a look round the web finds some very comprehensive User Groups with invaluable resources. If you need manuals, programs, information then please look (for starters) at the following sites:
- https://original.sharpmz.org/
- https://www.sharpmz.no/
- https://mz-80a.com
- http://www.sharpusersclub.org/
- http://www.scav.cz/uvod.htm (use chrome to auto translate Czech)

579
bridge.vhd Normal file
View File

@@ -0,0 +1,579 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: bridge.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series compatible logic IO Control.
--
-- This module is the IO control layer which provides io services to the emulation,
-- which at time of writing can come from the DE10 Nano HPS or the soft-core STORM
-- or NEO430 microcontroller.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.config_pkg.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity bridge is
port(
-------------------- Clock Input ----------------------------
clkmaster : in std_logic; -- Master Clock(50MHz)
clksys : out std_logic; -- System clock.
clkvid : out std_logic; -- Pixel base clock of video.
-------------------- Reset ----------------------------
cold_reset : in std_logic;
warm_reset : in std_logic;
-------------------- main_leds ----------------------------
main_leds : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
ps2_key : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
vga_hb_o : out std_logic; -- VGA Horizontal Blank
vga_vb_o : out std_logic; -- VGA Vertical Blank
vga_hs_o : out std_logic; -- VGA H_SYNC
vga_vs_o : out std_logic; -- VGA V_SYNC
vga_r_o : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
vga_g_o : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
vga_b_o : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
audio_l_o : out std_logic;
audio_r_o : out std_logic;
uart_rx : in std_logic;
uart_tx : out std_logic;
sd_sck : out std_logic;
sd_mosi : out std_logic;
sd_miso : in std_logic;
sd_cs : out std_logic;
sd_cd : out std_logic;
-------------------- HPS Interface ------------------------------
ioctl_download : in std_logic; -- HPS Downloading to FPGA.
ioctl_upload : in std_logic; -- HPS Uploading from FPGA.
ioctl_clk : in std_logic; -- HPS I/O Clock.
ioctl_wr : in std_logic; -- HPS Write Enable to FPGA.
ioctl_rd : in std_logic; -- HPS Read Enable from FPGA.
ioctl_addr : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
ioctl_dout : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
ioctl_din : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS.
);
end bridge;
architecture rtl of bridge is
--
-- Signals.
--
signal CON_CLKMASTER : std_logic;
signal CON_CLKSYS : std_logic;
signal CON_CLKVID : std_logic;
signal CON_CLKIOP : std_logic;
signal CON_COLD_RESET : std_logic;
signal CON_WARM_RESET : std_logic;
signal CON_MAIN_LEDS : std_logic_vector(7 downto 0);
signal CON_PS2_KEY : std_logic_vector(10 downto 0);
signal CON_VGA_HB_O : std_logic;
signal CON_VGA_VB_O : std_logic;
signal CON_VGA_HS_O : std_logic;
signal CON_VGA_VS_O : std_logic;
signal CON_VGA_R_O : std_logic_vector(7 downto 0);
signal CON_VGA_G_O : std_logic_vector(7 downto 0);
signal CON_VGA_B_O : std_logic_vector(7 downto 0);
signal CON_AUDIO_L_O : std_logic;
signal CON_AUDIO_R_O : std_logic;
signal CON_IOCTL_DOWNLOAD : std_logic;
signal CON_IOCTL_UPLOAD : std_logic;
signal CON_IOCTL_CLK : std_logic;
signal CON_IOCTL_WR : std_logic;
signal CON_IOCTL_RD : std_logic;
signal CON_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal CON_IOCTL_DOUT : std_logic_vector(31 downto 0);
signal CON_IOCTL_DIN : std_logic_vector(31 downto 0);
--
-- IO Processor Signals.
--
signal IOP_IOCTL_DOWNLOAD : std_logic;
signal IOP_IOCTL_UPLOAD : std_logic;
signal IOP_IOCTL_CLK : std_logic;
signal IOP_IOCTL_WR : std_logic;
signal IOP_IOCTL_RD : std_logic;
signal IOP_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal IOP_IOCTL_DOUT : std_logic_vector(31 downto 0);
signal IOP_IOCTL_DIN : std_logic_vector(31 downto 0);
signal IOP_IOCTL_SENSE : std_logic;
signal IOP_IOCTL_SELECT : std_logic;
--
--
--
signal CON_UART_TX : std_logic;
signal CON_UART_RX : std_logic;
signal CON_SPI_SCLK : std_logic;
signal CON_SPI_MOSI : std_logic;
signal CON_SPI_MISO : std_logic;
signal CON_SPI_CS : std_logic_vector(7 downto 0);
--
-- Components
--
component sharpmz
port (
-------------------- Clock Input ----------------------------
CLKMASTER : in std_logic; -- Master Clock(50MHz)
CLKSYS : out std_logic; -- System clock.
CLKVID : out std_logic; -- Pixel base clock of video.
CLKIOP : out std_logic; -- IO processor clock.
-------------------- Reset ----------------------------
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
-------------------- main_leds ----------------------------
MAIN_LEDS : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
VGA_HB_O : out std_logic; -- VGA Horizontal Blank
VGA_VB_O : out std_logic; -- VGA Vertical Blank
VGA_HS_O : out std_logic; -- VGA H_SYNC
VGA_VS_O : out std_logic; -- VGA V_SYNC
VGA_R_O : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
VGA_G_O : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
VGA_B_O : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
AUDIO_L_O : out std_logic;
AUDIO_R_O : out std_logic;
-------------------- HPS Interface ------------------------------
IOCTL_DOWNLOAD : in std_logic; -- Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- Uploading from FPGA.
IOCTL_CLK : in std_logic; -- I/O Clock.
IOCTL_WR : in std_logic; -- Write Enable to FPGA.
IOCTL_RD : in std_logic; -- Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0) -- Data to be read into HPS.
);
end component;
component STORM_SoC
port (
-- Global Control --
CLK_I : in std_logic;
RST_I : in std_logic;
-- General purpose (debug) UART --
UART0_RXD_I : in std_logic;
UART0_TXD_O : out std_logic;
-- System Control --
START_I : in std_logic; -- low active
BOOT_CONFIG_I : in std_logic_vector(03 downto 0); -- low active
LED_BAR_O : out std_logic_vector(07 downto 0);
-- GP Input Pins --
GP_INPUT_I : in std_logic_vector(07 downto 0);
-- GP Output Pins --
GP_OUTPUT_O : out std_logic_vector(07 downto 0);
-- I²C Port --
I2C_SCL_IO : inout std_logic;
I2C_SDA_IO : inout std_logic;
-- SPI Port 0 [3 devices] --
SPI_P0_CLK_O : out std_logic;
SPI_P0_MISO_I : in std_logic;
SPI_P0_MOSI_O : out std_logic;
SPI_P0_CS_O : out std_logic_vector(02 downto 0);
-- SPI Port 1 [3 devices] --
SPI_P1_CLK_O : out std_logic;
SPI_P1_MISO_I : in std_logic;
SPI_P1_MOSI_O : out std_logic;
SPI_P1_CS_O : out std_logic_vector(02 downto 0);
-- SPI Port 2 [2 devices] --
SPI_P2_CLK_O : out std_logic;
SPI_P2_MISO_I : in std_logic;
SPI_P2_MOSI_O : out std_logic;
SPI_P2_CS_O : out std_logic_vector(01 downto 0);
-- PWM Port 0 --
-- PWM0_PORT_O : out std_logic_vector(07 downto 0)
-- IOCTL Bus --
IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA.
IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA.
IOCTL_CLK : out std_logic; -- I/O Clock.
IOCTL_WR : out std_logic; -- Write Enable to FPGA.
IOCTL_RD : out std_logic; -- Read Enable from FPGA.
IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus.
IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus.
IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
IOCTL_DIN : in std_logic_vector(31 downto 0) -- Data to be read into HPS.
-- -- SDRAM Interface --
-- SDRAM_CLK_O : out std_logic;
-- SDRAM_CSN_O : out std_logic;
-- SDRAM_CKE_O : out std_logic;
-- SDRAM_RASN_O : out std_logic;
-- SDRAM_CASN_O : out std_logic;
-- SDRAM_WEN_O : out std_logic;
-- SDRAM_DQM_O : out std_logic_vector(01 downto 0);
-- SDRAM_BA_O : out std_logic_vector(01 downto 0);
-- SDRAM_ADR_O : out std_logic_vector(11 downto 0);
-- SDRAM_DAT_IO : inout std_logic_vector(15 downto 0)
);
end component;
component neo430
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := false;-- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := true; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- gpio --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(02 downto 0); -- pwm channels
-- serial com --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- IOCTL Bus --
ioctl_download : out std_logic; -- Downloading to FPGA.
ioctl_upload : out std_logic; -- Uploading from FPGA.
ioctl_clk : out std_logic; -- I/O Clock.
ioctl_wr : out std_logic; -- Write Enable to FPGA.
ioctl_rd : out std_logic; -- Read Enable from FPGA.
ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus.
ioctl_select : out std_logic; -- Enable CFU control over ioctl bus.
ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
ioctl_dout : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
ioctl_din : in std_logic_vector(31 downto 0); -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_dat_i : in std_logic_vector(31 downto 0); -- read data
wb_dat_o : out std_logic_vector(31 downto 0); -- write data
wb_we_o : out std_logic; -- read/write
wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_logic; -- strobe
wb_cyc_o : out std_logic; -- valid cycle
wb_ack_i : in std_logic; -- transfer acknowledge
-- interrupts --
irq_i : in std_logic; -- external interrupt request line
irq_ack_o : out std_logic -- external interrupt request acknowledge
);
end component;
begin
--
-- Instantiation
--
SHARPMZ_0 : sharpmz
port map (
-------------------- Clock Input ----------------------------
CLKMASTER => CON_CLKMASTER, -- Master Clock(50MHz)
CLKSYS => CON_CLKSYS, -- System clock.
CLKVID => CON_CLKVID, -- Pixel base clock of video.
CLKIOP => CON_CLKIOP, -- IO Processor Clock.
-------------------- ----------------------------
COLD_RESET => CON_COLD_RESET,
WARM_RESET => CON_WARM_RESET,
-------------------- ----------------------------
MAIN_LEDS => CON_MAIN_LEDS, -- main_leds Green[7:0]
-------------------- ----------------------------
PS2_KEY => CON_PS2_KEY, -- PS2 Key data.
-------------------- ----------------------------
VGA_HB_O => CON_VGA_HB_O, -- VGA Horizontal Blank
VGA_VB_O => CON_VGA_VB_O, -- VGA Vertical Blank
VGA_HS_O => CON_VGA_HS_O, -- VGA H_SYNC
VGA_VS_O => CON_VGA_VS_O, -- VGA V_SYNC
VGA_R_O => CON_VGA_R_O, -- VGA Red[3:0], [7:4] = 0
VGA_G_O => CON_VGA_G_O, -- VGA Green[3:0]
VGA_B_O => CON_VGA_B_O, -- VGA Blue[3:0]
-------------------- ------------------------------
AUDIO_L_O => CON_AUDIO_L_O,
AUDIO_R_O => CON_AUDIO_R_O,
-------------------- ------------------------------
IOCTL_DOWNLOAD => CON_IOCTL_DOWNLOAD, -- Downloading to FPGA.
IOCTL_UPLOAD => CON_IOCTL_UPLOAD, -- Uploading from FPGA.
IOCTL_CLK => CON_IOCTL_CLK, -- I/O Clock.
IOCTL_WR => CON_IOCTL_WR, -- Write Enable to FPGA.
IOCTL_RD => CON_IOCTL_RD, -- Read Enable from FPGA.
IOCTL_ADDR => CON_IOCTL_ADDR, -- Address in FPGA to write into.
IOCTL_DOUT => CON_IOCTL_DOUT, -- Data to be written into FPGA.
IOCTL_DIN => CON_IOCTL_DIN -- Data to be read into HPS.
);
-- If enabled, instantiate the local STORM IO processor to provide IO and user interface services.
--
STORM_ENABLED: if STORM_ENABLE = 1 generate
STORM_0: STORM_SoC
port map (
-- Global Control --
CLK_I => CON_CLKIOP, -- global clock, rising edge
RST_I => (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
-- General purpose (debug) UART --
UART0_RXD_I => CON_UART_RX,
UART0_TXD_O => CON_UART_TX,
-- System Control --
START_I => '1',
BOOT_CONFIG_I => "0000",
LED_BAR_O => open,
-- GP Input Pins --
GP_INPUT_I => x"FF",
-- GP Output Pins --
GP_OUTPUT_O => open,
-- I²C Port --
I2C_SCL_IO => open,
I2C_SDA_IO => open,
-- SPI Port 0 [3 devices] --
SPI_P0_CLK_O => CON_SPI_SCLK,
SPI_P0_MISO_I => CON_SPI_MISO,
SPI_P0_MOSI_O => CON_SPI_MOSI,
SPI_P0_CS_O => CON_SPI_CS(2 downto 0),
-- SPI Port 1 [3 devices] --
SPI_P1_CLK_O => open,
SPI_P1_MISO_I => '0',
SPI_P1_MOSI_O => open,
SPI_P1_CS_O => open,
-- SPI Port 2 [2 devices] --
SPI_P2_CLK_O => open,
SPI_P2_MISO_I => '0',
SPI_P2_MOSI_O => open,
SPI_P2_CS_O => open,
-- PWM Port 0 --
-- PWM0_PORT_O => open
-- IOCTL Bus --
IOCTL_DOWNLOAD => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
IOCTL_UPLOAD => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
IOCTL_CLK => IOP_IOCTL_CLK, -- I/O Clock.
IOCTL_WR => IOP_IOCTL_WR, -- Write Enable to FPGA.
IOCTL_RD => IOP_IOCTL_RD, -- Read Enable from FPGA.
IOCTL_SENSE => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
IOCTL_SELECT => IOP_IOCTL_SELECT, -- Enable IOP control over ioctl bus.
IOCTL_ADDR => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
IOCTL_DOUT => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
IOCTL_DIN => IOP_IOCTL_DIN -- Data to be read into HPS.
-- -- SDRAM Interface --
-- SDRAM_CLK_O => open,
-- SDRAM_CSN_O => open,
-- SDRAM_CKE_O => open,
-- SDRAM_RASN_O => open,
-- SDRAM_CASN_O => open,
-- SDRAM_WEN_O => open,
-- SDRAM_DQM_O => open,
-- SDRAM_BA_O => open,
-- SDRAM_ADR_O => open,
-- SDRAM_DAT_IO => open
);
end generate;
-- If enabled, instantiate the local IO processor to provide IO and user interface services.
--
NEO430_ENABLED: if NEO_ENABLE = 1 generate
NEO430_0 : neo430
generic map (
-- general configuration --
CLOCK_SPEED => 64000000, -- main clock in Hz
IMEM_SIZE => 48*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => 12*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => x"0000", -- custom user code
-- module configuration --
DADD_USE => true, -- implement DADD instruction? (default=true)
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => false, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WDT? (default=true)
GPIO_USE => true, -- implement GPIO unit? (default=true)
TIMER_USE => true, -- implement timer? (default=true)
UART_USE => true, -- implement UART? (default=true)
CRC_USE => false, -- implement CRC unit? (default=true)
CFU_USE => false, -- implement custom functions unit? (default=false)
PWM_USE => true, -- implement PWM controller?
TWI_USE => false, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE => true, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => CON_CLKIOP, -- global clock, rising edge
rst_i => not (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
-- gpio --
gpio_o => open, -- parallel output
gpio_i => X"0000", -- parallel input
-- pwm channels --
pwm_o => open, -- pwm channels
-- serial com --
uart_txd_o => CON_UART_TX, -- UART send data
uart_rxd_i => CON_UART_RX, -- UART receive data
spi_sclk_o => CON_SPI_SCLK, -- serial clock line
spi_mosi_o => CON_SPI_MOSI, -- serial data line out
spi_miso_i => CON_SPI_MISO, -- serial data line in
spi_cs_o => CON_SPI_CS, -- SPI CS 0..7
twi_sda_io => open, -- twi serial data line
twi_scl_io => open, -- twi serial clock line
-- IOCTL Bus --
ioctl_download => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
ioctl_upload => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
ioctl_clk => IOP_IOCTL_CLK, -- I/O Clock.
ioctl_wr => IOP_IOCTL_WR, -- Write Enable to FPGA.
ioctl_rd => IOP_IOCTL_RD, -- Read Enable from FPGA.
ioctl_sense => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
ioctl_select => IOP_IOCTL_SELECT, -- Enable CFU control over ioctl bus.
ioctl_addr => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
ioctl_dout => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
ioctl_din => IOP_IOCTL_DIN, -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o => open, -- address
wb_dat_i => (others => '0'), -- read data
wb_dat_o => open, -- write data
wb_we_o => open, -- read/write
wb_sel_o => open, -- byte enable
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- interrupts --
irq_i => '0', -- external interrupt request line
irq_ack_o => open -- external interrupt request acknowledge
);
end generate;
-- If the IO Processor is disabled, set the signals to inactive.
--
IOP_DISABLED: if NEO_ENABLE = 0 and STORM_ENABLE = 0 generate
IOP_IOCTL_DOWNLOAD <= '0';
IOP_IOCTL_UPLOAD <= '0';
IOP_IOCTL_CLK <= '0';
IOP_IOCTL_WR <= '0';
IOP_IOCTL_RD <= '0';
IOP_IOCTL_ADDR <= (others => '0');
IOP_IOCTL_DOUT <= (others => '0');
--IOP_IOCTL_DIN => open;
--IOP_IOCTL_SENSE => open;
IOP_IOCTL_SELECT <= '0';
end generate;
-- Assign signals from the emu onto local wires.
--
CON_CLKMASTER <= clkmaster;
clksys <= CON_CLKSYS;
clkvid <= CON_CLKVID;
CON_COLD_RESET <= cold_reset;
CON_WARM_RESET <= warm_reset;
main_leds <= CON_MAIN_LEDS;
CON_PS2_KEY <= ps2_key;
vga_hb_o <= CON_VGA_HB_O;
vga_vb_o <= CON_VGA_VB_O;
vga_hs_o <= CON_VGA_HS_O;
vga_vs_o <= CON_VGA_VS_O;
vga_r_o <= CON_VGA_R_O;
vga_g_o <= CON_VGA_G_O;
vga_b_o <= CON_VGA_B_O;
audio_l_o <= CON_AUDIO_L_O;
audio_r_o <= CON_AUDIO_R_O;
uart_tx <= CON_UART_TX;
CON_UART_RX <= uart_rx;
sd_sck <= CON_SPI_SCLK;
sd_mosi <= CON_SPI_MOSI;
CON_SPI_MISO <= sd_miso;
sd_cs <= CON_SPI_CS(0);
--
-- Multiplexer, default IO control to the HPS unless the IOP is enabled and selects.
-- The IOP first senses to ensure there is no activity on the bus, then takes control
--
CON_IOCTL_DOWNLOAD <= ioctl_download when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_DOWNLOAD;
CON_IOCTL_UPLOAD <= ioctl_upload when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_UPLOAD;
CON_IOCTL_CLK <= ioctl_clk when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_CLK;
CON_IOCTL_WR <= ioctl_wr when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_WR;
CON_IOCTL_RD <= ioctl_rd when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_RD;
CON_IOCTL_ADDR <= ioctl_addr when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_ADDR;
CON_IOCTL_DOUT <= X"0000" & ioctl_dout when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_DOUT;
ioctl_din <= CON_IOCTL_DIN(15 downto 0) when IOP_IOCTL_SELECT = '0'
else
(others => '0');
IOP_IOCTL_DIN <= CON_IOCTL_DIN when IOP_IOCTL_SELECT = '1'
else
(others => '0');
IOP_IOCTL_SENSE <= ioctl_download or ioctl_upload or ioctl_wr or ioctl_rd;
end rtl;

2
build_id.v Normal file
View File

@@ -0,0 +1,2 @@
`define BUILD_DATE "190107"
`define BUILD_TIME "222840"

118
c5_pin_model_dump.txt Normal file
View File

@@ -0,0 +1,118 @@
io_4iomodule_c5_index: 55gpio_index: 2
io_4iomodule_c5_index: 54gpio_index: 465
io_4iomodule_c5_index: 33gpio_index: 6
io_4iomodule_c5_index: 51gpio_index: 461
io_4iomodule_c5_index: 27gpio_index: 10
io_4iomodule_c5_index: 57gpio_index: 457
io_4iomodule_c5_index: 34gpio_index: 14
io_4iomodule_c5_index: 28gpio_index: 453
io_4iomodule_c5_index: 26gpio_index: 19
io_4iomodule_c5_index: 47gpio_index: 449
io_4iomodule_c5_index: 29gpio_index: 22
io_4iomodule_c5_index: 3gpio_index: 445
io_4iomodule_c5_index: 16gpio_index: 27
io_4iomodule_c5_index: 6gpio_index: 441
io_4iomodule_c5_index: 50gpio_index: 30
io_4iomodule_c5_index: 35gpio_index: 437
io_4iomodule_c5_index: 7gpio_index: 35
io_4iomodule_c5_index: 53gpio_index: 433
io_4iomodule_c5_index: 12gpio_index: 38
io_4iomodule_c5_index: 1gpio_index: 429
io_4iomodule_c5_index: 22gpio_index: 43
io_4iomodule_c5_index: 8gpio_index: 425
io_4iomodule_c5_index: 20gpio_index: 46
io_4iomodule_c5_index: 30gpio_index: 421
io_4iomodule_c5_index: 2gpio_index: 51
io_4iomodule_c5_index: 31gpio_index: 417
io_4iomodule_c5_index: 39gpio_index: 54
io_4iomodule_c5_index: 18gpio_index: 413
io_4iomodule_c5_index: 10gpio_index: 59
io_4iomodule_c5_index: 42gpio_index: 409
io_4iomodule_c5_index: 5gpio_index: 62
io_4iomodule_c5_index: 24gpio_index: 405
io_4iomodule_c5_index: 37gpio_index: 67
io_4iomodule_c5_index: 13gpio_index: 401
io_4iomodule_c5_index: 0gpio_index: 70
io_4iomodule_c5_index: 44gpio_index: 397
io_4iomodule_c5_index: 38gpio_index: 75
io_4iomodule_c5_index: 52gpio_index: 393
io_4iomodule_c5_index: 32gpio_index: 78
io_4iomodule_c5_index: 56gpio_index: 389
io_4iomodule_a_index: 13gpio_index: 385
io_4iomodule_c5_index: 4gpio_index: 83
io_4iomodule_c5_index: 23gpio_index: 86
io_4iomodule_a_index: 15gpio_index: 381
io_4iomodule_a_index: 8gpio_index: 377
io_4iomodule_c5_index: 46gpio_index: 91
io_4iomodule_a_index: 5gpio_index: 373
io_4iomodule_a_index: 11gpio_index: 369
io_4iomodule_c5_index: 41gpio_index: 94
io_4iomodule_a_index: 3gpio_index: 365
io_4iomodule_c5_index: 25gpio_index: 99
io_4iomodule_a_index: 7gpio_index: 361
io_4iomodule_c5_index: 9gpio_index: 102
io_4iomodule_a_index: 0gpio_index: 357
io_4iomodule_c5_index: 14gpio_index: 107
io_4iomodule_a_index: 12gpio_index: 353
io_4iomodule_c5_index: 45gpio_index: 110
io_4iomodule_c5_index: 17gpio_index: 115
io_4iomodule_a_index: 4gpio_index: 349
io_4iomodule_c5_index: 36gpio_index: 118
io_4iomodule_a_index: 10gpio_index: 345
io_4iomodule_a_index: 16gpio_index: 341
io_4iomodule_c5_index: 15gpio_index: 123
io_4iomodule_a_index: 14gpio_index: 337
io_4iomodule_c5_index: 43gpio_index: 126
io_4iomodule_c5_index: 19gpio_index: 131
io_4iomodule_a_index: 1gpio_index: 333
io_4iomodule_c5_index: 59gpio_index: 134
io_4iomodule_a_index: 2gpio_index: 329
io_4iomodule_a_index: 9gpio_index: 325
io_4iomodule_c5_index: 48gpio_index: 139
io_4iomodule_a_index: 6gpio_index: 321
io_4iomodule_a_index: 17gpio_index: 317
io_4iomodule_c5_index: 40gpio_index: 142
io_4iomodule_c5_index: 11gpio_index: 147
io_4iomodule_c5_index: 58gpio_index: 150
io_4iomodule_c5_index: 21gpio_index: 155
io_4iomodule_c5_index: 49gpio_index: 158
io_4iomodule_h_c5_index: 0gpio_index: 161
io_4iomodule_h_c5_index: 6gpio_index: 165
io_4iomodule_h_c5_index: 10gpio_index: 169
io_4iomodule_h_c5_index: 3gpio_index: 173
io_4iomodule_h_c5_index: 8gpio_index: 176
io_4iomodule_h_c5_index: 11gpio_index: 180
io_4iomodule_h_c5_index: 7gpio_index: 184
io_4iomodule_h_c5_index: 5gpio_index: 188
io_4iomodule_h_c5_index: 1gpio_index: 192
io_4iomodule_h_c5_index: 2gpio_index: 196
io_4iomodule_h_c5_index: 9gpio_index: 200
io_4iomodule_h_c5_index: 4gpio_index: 204
io_4iomodule_h_index: 15gpio_index: 208
io_4iomodule_h_index: 1gpio_index: 212
io_4iomodule_h_index: 3gpio_index: 216
io_4iomodule_h_index: 2gpio_index: 220
io_4iomodule_h_index: 11gpio_index: 224
io_4iomodule_vref_h_index: 1gpio_index: 228
io_4iomodule_h_index: 20gpio_index: 231
io_4iomodule_h_index: 8gpio_index: 235
io_4iomodule_h_index: 6gpio_index: 239
io_4iomodule_h_index: 10gpio_index: 243
io_4iomodule_h_index: 23gpio_index: 247
io_4iomodule_h_index: 7gpio_index: 251
io_4iomodule_h_index: 22gpio_index: 255
io_4iomodule_h_index: 5gpio_index: 259
io_4iomodule_h_index: 24gpio_index: 263
io_4iomodule_h_index: 0gpio_index: 267
io_4iomodule_h_index: 13gpio_index: 271
io_4iomodule_h_index: 21gpio_index: 275
io_4iomodule_h_index: 16gpio_index: 279
io_4iomodule_vref_h_index: 0gpio_index: 283
io_4iomodule_h_index: 12gpio_index: 286
io_4iomodule_h_index: 4gpio_index: 290
io_4iomodule_h_index: 19gpio_index: 294
io_4iomodule_h_index: 18gpio_index: 298
io_4iomodule_h_index: 17gpio_index: 302
io_4iomodule_h_index: 25gpio_index: 306
io_4iomodule_h_index: 14gpio_index: 310
io_4iomodule_h_index: 9gpio_index: 314

38
clean.bat Normal file
View File

@@ -0,0 +1,38 @@
@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del *.cdf
del *.rpt
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

37
clean.sh Normal file
View File

@@ -0,0 +1,37 @@
#!/bin/bash -x
rm -f *.bak
rm -f *.orig
rm -f *.rej
rm -f *~
rm -fr db
rm -fr incremental_db
rm -fr output_files
rm -fr simulation
rm -fr greybox_tmp
rm -fr hc_output
rm -fr .qsys_edit
rm -fr hps_isw_handoff
rm -fr sys\.qsys_edit
rm -fr sys\vip
#rm build_id.v
rm -f c5_pin_model_dump.txt
rm -f PLLJ_PLLSPE_INFO.txt
rm -f *.qws
rm -f *.ppf
rm -f *.ddb
rm -f *.csv
rm -f *.cmp
rm -f *.sip
rm -f *.spd
rm -f *.bsf
rm -f *.f
rm -f *.sopcinfo
rm -f *.xml
rm -f *.cdf
rm -f *.rpt
rm -f new_rtl_netlist
rm -f old_rtl_netlist
rm -f asm/*.obj
rm -f asm/*.sym
(cd ../Main_MiSTer; make clean)

2
common/.qsys_edit/filters.xml Normal file
View File

@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<filters version="17.1" />

2440
common/.qsys_edit/pll.xml Normal file
View File

File diff suppressed because it is too large Load Diff

34
common/.qsys_edit/pll_schematic.nlv Normal file
View File

@@ -0,0 +1,34 @@
# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
preplace inst pll.pll_0 -pg 1 -lvl 2 -y 170
preplace inst pll.pll_1 -pg 1 -lvl 3 -y 170
preplace inst pll.pll_2 -pg 1 -lvl 2 -y 370
preplace inst pll.clk_0 -pg 1 -lvl 1 -y 260
preplace inst pll -pg 1 -lvl 1 -y 40 -regy -20
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_2_outclk3,(MASTER)pll_2.outclk3) 1 2 2 NJ 440 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_0_outclk4,(MASTER)pll_0.outclk4) 1 2 2 NJ 120 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.pll_2_refclk,(SLAVE)pll_2.refclk) 1 0 2 NJ 400 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll_1.reset,(SLAVE)pll.pll_1_reset) 1 0 3 NJ 250 NJ 360 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk2,(MASTER)pll.pll_0_outclk2) 1 2 2 NJ 80 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_2_outclk2,(MASTER)pll_2.outclk2) 1 2 2 NJ 420 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk6,(MASTER)pll.pll_0_outclk6) 1 2 2 NJ 160 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk5,(MASTER)pll.pll_0_outclk5) 1 2 2 NJ 140 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll_1.refclk,(SLAVE)pll.pll_1_refclk) 1 0 3 NJ 160 NJ 160 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk1,(MASTER)pll.pll_1_outclk1) 1 3 1 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)clk_0.clk_in,(SLAVE)pll.clk) 1 0 1 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_2.outclk1,(MASTER)pll.pll_2_outclk1) 1 2 2 NJ 400 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_1_outclk2,(MASTER)pll_1.outclk2) 1 3 1 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_0_outclk3,(MASTER)pll_0.outclk3) 1 2 2 NJ 100 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk3,(MASTER)pll.pll_1_outclk3) 1 3 1 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_2.outclk4,(MASTER)pll.pll_2_outclk4) 1 2 2 NJ 460 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_0_outclk1,(MASTER)pll_0.outclk1) 1 2 2 NJ 60 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk0,(MASTER)pll.pll_0_outclk0) 1 2 2 NJ 40 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk4,(MASTER)pll.pll_1_outclk4) 1 3 1 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_2.outclk0,(MASTER)pll.pll_2_outclk0) 1 2 2 NJ 380 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll_0.refclk,(SLAVE)pll.pll_0_refclk) 1 0 2 NJ 210 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.pll_2_reset,(SLAVE)pll_2.reset) 1 0 2 NJ 420 NJ
preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk0,(MASTER)pll.pll_1_outclk0) 1 3 1 NJ
preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.pll_0_reset,(SLAVE)pll_0.reset) 1 0 2 NJ 230 NJ
levelinfo -pg 1 0 90 970
levelinfo -hier pll 100 130 370 730 860

13
common/.qsys_edit/preferences.xml Normal file
View File

@@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="319" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Library,Project" />
<window width="1988" height="1246" x="4127" y="162" />
<generation synthesis="VHDL" path="pll" />
</preferences>

1094
common/T80/T80.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

194
common/T80/T8080se.vhd Normal file
View File

@@ -0,0 +1,194 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

371
common/T80/T80_ALU.vhd Normal file
View File

@@ -0,0 +1,371 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

2029
common/T80/T80_MCode.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

220
common/T80/T80_Pack.vhd Normal file
View File

@@ -0,0 +1,220 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

114
common/T80/T80_Reg.vhd Normal file
View File

@@ -0,0 +1,114 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

176
common/T80/T80_RegX.vhd Normal file
View File

@@ -0,0 +1,176 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;

262
common/T80/T80a.vhd Normal file
View File

@@ -0,0 +1,262 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

192
common/T80/T80se.vhd Normal file
View File

@@ -0,0 +1,192 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

179
common/T80/T80sed.vhd Normal file
View File

@@ -0,0 +1,179 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

1
common/cgrom.dump Executable file
View File

File diff suppressed because one or more lines are too long

61
common/clk_div.vhd Normal file
View File

@@ -0,0 +1,61 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: clk_div.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: A basic frequency divider module.
-- This module takes an input frequency and divides it based on a provided divider.
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_div is
GENERIC (
divider : natural
);
PORT (
clk_in : in std_logic;
reset : in std_logic;
clk_out : out std_logic
);
end clk_div;
architecture Behavioral of clk_div is
signal temporal: std_logic;
signal counter : integer range 0 to divider-1 := 0;
begin
process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = divider-1) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;

794
common/clkgen.vhd Normal file
View File

@@ -0,0 +1,794 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: clkgen.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: A programmable Clock Generate module using division.
--
-- This module is the heart of the emulator, providing all required frequencies
-- from a given input clock (ie. DE10 Nano 50MHz).
--
-- Based on input control signals from the MCTRL block, it changes the core frequencies
-- according to requirements and adjusts delays (such as memory) accordingly.
--
-- The module also has debugging logic to create debug frequencies (in the FPGA, static
-- is quite possible). The debug frequencies can range from CPU down to 1/10 Hz.
--
-- Note: Generally on FPGA's you try to minimise clocks generated by division, this is
-- due to following:-
-- o The fpga may need to have the routing to bring a clock signal from a register
-- output into a clock net.
-- o Clock nets are a limited resource, some fpga's can clock flip flops off normal
-- nets but doing this is likely to affect timing behaviour.
-- o You may need to add constraints to tell the timing analyser the clock details in
-- order to get proper timing behaviour/analysis.
-- o There may be substantial phase-skew between the original clock and the generated
-- clock.
-- o To ensure the clock is clean it should come directly from a register output, not
-- from combinatorial logic.
--
-- This module has been written with the above in mind and on the Cyclone SE it works fine.
-- Basically it uses Clock Enables on the Master clock to minimise skew. Only core frequencies
-- that cannot be clock enabled remain.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
-- October 2018- Updated and seperated so that debug code can be removed at compile time.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
package clkgen_pkg is
-- Clock bus, various clocks on a single bus construct.
--
subtype CLKBUS_WIDTH is integer range 8 downto 0;
-- Indexes to the various clocks on the bus.
--
constant CKMASTER : integer := 0;
constant CKSOUND : integer := 1; -- Sound clock.
constant CKRTC : integer := 2; -- RTC clock.
constant CKENVIDEO : integer := 3; -- Video clock enable.
constant CKVIDEO : integer := 4; -- Video clock.
constant CKIOP : integer := 5;
constant CKENCPU : integer := 6; -- CPU clock enable.
constant CKENLEDS : integer := 7; -- LEDS display clock enable.
constant CKENPERIPH : integer := 8; -- Peripheral clock enable.
end clkgen_pkg;
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use pkgs.config_pkg.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity clkgen is
Port (
RST : in std_logic; -- Reset
-- Clocks
CKBASE : in std_logic; -- Base system main clock.
CLKBUS : out std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by this module.
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- Debug modes.
DEBUG : in std_logic_vector(DEBUG_WIDTH)
);
end clkgen;
architecture RTL of clkgen is
--
-- Selectable output Clocks
--
signal PLLLOCKED1 : std_logic;
signal PLLLOCKED2 : std_logic;
signal PLLLOCKED3 : std_logic;
signal CK448Mi : std_logic; -- 448MHz
signal CK112Mi : std_logic; -- 112MHz
signal CK64Mi : std_logic; -- 64MHz
signal CK56M750i : std_logic; -- 56MHz
signal CK32Mi : std_logic; -- 32MHz
signal CK31M5i : std_logic; -- 31.5MHz
signal CK28M375i : std_logic; -- 28MHz
signal CK25M175i : std_logic; -- 25.175MHz
signal CK17M734i : std_logic; -- 17.7MHz
signal CK16Mi : std_logic; -- 16MHz
signal CK14M1875i : std_logic; -- 14MHz
signal CK8M8672i : std_logic; -- 8.8MHz
signal CK8Mi : std_logic; -- 8MHz
signal CK7M709i : std_logic; -- 7MHz
signal CK4Mi : std_logic; -- 4MHz
signal CK3M546875i : std_logic; -- 3.5MHz
signal CK2Mi : std_logic; -- 2MHz
signal CK1Mi : std_logic; -- 1MHz
signal CK895Ki : std_logic; -- 895KHz Sound frequency.
signal CK100Ki : std_logic; -- Debug frequency.
signal CK31500i : std_logic; -- Clock base frequency,
signal CK31250i : std_logic; -- Clock base frequency.
signal CK15611i : std_logic; -- Clock base frequency.
signal CK10Ki : std_logic; -- 10KHz debug CPU frequency.
signal CK5Ki : std_logic; -- 5KHz debug CPU frequency.
signal CK1Ki : std_logic; -- 1KHz debug CPU frequency.
signal CK500i : std_logic; -- 500Hz debug CPU frequency.
signal CK100i : std_logic; -- 100Hz debug CPU frequency.
signal CK50i : std_logic; -- 50Hz debug CPU frequency.
signal CK10i : std_logic; -- 10Hz debug CPU frequency.
signal CK5i : std_logic; -- 5Hz debug CPU frequency.
signal CK2i : std_logic; -- 2Hz debug CPU frequency.
signal CK1i : std_logic; -- 1Hz debug CPU frequency.
signal CK0_5i : std_logic; -- 0.5Hz debug CPU frequency.
signal CK0_2i : std_logic; -- 0.2Hz debug CPU frequency.
signal CK0_1i : std_logic; -- 0.1Hz debug CPU frequency.
signal CKSOUNDi : std_logic; -- Sound clock 50/50 Duty cycle.
signal CKRTCi : std_logic; -- RTC clock 50/50 Duty cycle.
signal CKVIDEOi : std_logic; -- Video clock 50/50 Duty cycle.
signal CKIOPi : std_logic; -- IO Processor clock.
--
-- Enable signals for target clocks.
--
signal CKENCPUi : std_logic;
signal CKENLEDSi : std_logic;
signal CKENVIDEOi : std_logic;
signal CKENPERi : std_logic;
--
-- Clock edge detection for creating clock enables.
--
signal CPUEDGE : std_logic_vector(1 downto 0);
signal LEDSEDGE : std_logic_vector(1 downto 0);
signal VIDEOEDGE : std_logic_vector(1 downto 0);
signal PEREDGE : std_logic_vector(1 downto 0);
--
-- Components
--
component pll_pll_0 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
outclk_2 : out std_logic; -- clk
outclk_3 : out std_logic; -- clk
outclk_4 : out std_logic; -- clk
outclk_5 : out std_logic; -- clk
outclk_6 : out std_logic; -- clk
outclk_7 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll_pll_0;
component pll_pll_1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
outclk_2 : out std_logic; -- clk
outclk_3 : out std_logic; -- clk
outclk_4 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll_pll_1;
component pll_pll_2 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
outclk_2 : out std_logic; -- clk
outclk_3 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll_pll_2;
begin
PLLMAIN01 : pll_pll_0
port map (
refclk => CKBASE, -- Reference clock
rst => RST, -- Reset
outclk_0 => CK448Mi, -- 448MHz
outclk_1 => CK112Mi, -- 112MHz
outclk_2 => CK64Mi, -- 64MHz
outclk_3 => CK32Mi, -- 328MHz
outclk_4 => CK16Mi, -- 16MHz
outclk_5 => CK8Mi, -- 8MHz
outclk_6 => CK4Mi, -- 4MHz
outclk_7 => CK2Mi, -- 2MHz
locked => PLLLOCKED1 -- PLL locked.
);
PLLMAIN02 : pll_pll_1
port map (
refclk => CK448Mi, -- Reference clock
rst => RST, -- Reset
outclk_0 => CK56M750i, -- 56.750MHz
outclk_1 => CK28M375i, -- 28.375MHz
outclk_2 => CK14M1875i, -- 14.1875MHz
outclk_3 => CK7M709i, -- 7.709MHz
outclk_4 => CK3M546875i, -- 3.546875MHz
locked => PLLLOCKED2 -- PLL locked.
);
PLLMAIN03 : pll_pll_2
port map (
refclk => CK448Mi, -- Reference clock
rst => RST, -- Reset
outclk_0 => CK31M5i, -- 31.5MHz
outclk_1 => CK25M175i, -- 25.175MHz
outclk_2 => CK17M734i, -- 17.734MHz
outclk_3 => CK8M8672i, -- 8.8672MHz
locked => PLLLOCKED3 -- PLL locked.
);
--
-- Clock Generator - Basic divide circuit for higher end frequencies.
--
process (RST, PLLLOCKED1, PLLLOCKED2, PLLLOCKED3, CK2Mi)
--
-- Divide by counters to create the various Clock enable signals.
--
variable counter1Mi : unsigned(0 downto 0); -- Binary divider to create 1Mi clock.
variable counter895Ki : unsigned(0 downto 0); -- Binary divider to create 895Ki clock.
variable counter100Ki : unsigned(4 downto 0); -- Binary divider to create 100Ki clock.
variable counter31500i : unsigned(5 downto 0); -- Binary divider to create 31500i clock.
variable counter31250i : unsigned(5 downto 0); -- Binary divider to create 31250i clock.
variable counter15611i : unsigned(6 downto 0); -- Binary divider to create 15611i clock.
variable counter10Ki : unsigned(7 downto 0); -- Binary divider to create 10Ki clock.
variable counter5Ki : unsigned(8 downto 0); -- Binary divider to create 5Ki clock.
variable counter1Ki : unsigned(10 downto 0); -- Binary divider to create 1Ki clock.
variable counter500i : unsigned(11 downto 0); -- Binary divider to create 500i clock.
variable counter100i : unsigned(14 downto 0); -- Binary divider to create 100i clock.
variable counter50i : unsigned(15 downto 0); -- Binary divider to create 50i clock.
variable counter10i : unsigned(17 downto 0); -- Binary divider to create 10i clock.
variable counter5i : unsigned(18 downto 0); -- Binary divider to create 5i clock.
variable counter2i : unsigned(29 downto 0); -- Binary divider to create 1i clock.
variable counter1i : unsigned(20 downto 0); -- Binary divider to create 1i clock.
variable counter0_5i : unsigned(21 downto 0); -- Binary divider to create 0_5i clock.
variable counter0_2i : unsigned(23 downto 0); -- Binary divider to create 0_2i clock.
variable counter0_1i : unsigned(24 downto 0); -- Binary divider to create 0_1i clock.
begin
if RST = '1' or PLLLOCKED1 = '0' or PLLLOCKED2 = '0' or PLLLOCKED3 = '0' then
counter1Mi := (others => '0');
counter895Ki := (others => '0');
counter100Ki := (others => '0');
counter31500i := (others => '0');
counter31250i := (others => '0');
counter15611i := (others => '0');
counter10Ki := (others => '0');
counter5Ki := (others => '0');
counter1Ki := (others => '0');
counter500i := (others => '0');
counter100i := (others => '0');
counter50i := (others => '0');
counter10i := (others => '0');
counter5i := (others => '0');
counter2i := (others => '0');
counter1i := (others => '0');
counter0_5i := (others => '0');
counter0_2i := (others => '0');
counter0_1i := (others => '0');
CK1Mi <= '0';
CK895Ki <= '0';
CK100Ki <= '0';
CK31500i <= '0';
CK31250i <= '0';
CK15611i <= '0';
CK10Ki <= '0';
CK5Ki <= '0';
CK1Ki <= '0';
CK500i <= '0';
CK100i <= '0';
CK50i <= '0';
CK10i <= '0';
CK5i <= '0';
CK2i <= '0';
CK1i <= '0';
CK0_5i <= '0';
CK0_2i <= '0';
CK0_1i <= '0';
--
-- CKSOUNDi <= '0';
CKRTCi <= '0';
elsif rising_edge(CK2Mi) then
-- 1000000Hz
if counter1Mi = 0 or counter1Mi = 1 then
CK1Mi <= not CK1Mi;
if counter1Mi = 1 then
counter1Mi := (others => '0');
else
counter1Mi := counter1Mi + 1;
end if;
else
counter1Mi := counter1Mi + 1;
end if;
-- 895000Hz
if counter895Ki = 0 or counter895Ki = 1 then
CK895Ki <= not CK895Ki;
if counter895Ki = 1 then
counter895Ki := (others => '0');
else
counter895Ki := counter895Ki + 1;
end if;
else
counter895Ki := counter895Ki + 1;
end if;
-- 100000Hz
if counter100Ki = 9 or counter100Ki = 19 then
CK100Ki <= not CK100Ki;
if counter100Ki = 19 then
counter100Ki := (others => '0');
else
counter100Ki := counter100Ki + 1;
end if;
else
counter100Ki := counter100Ki + 1;
end if;
-- 31500Hz
if counter31500i = 30 or counter31500i = 62 then
CK31500i <= not CK31500i;
if CONFIG(RTCSPEED) = "00" then
CKRTCi <= not CKRTCi;
end if;
if counter31500i = 62 then
counter31500i := (others => '0');
else
counter31500i := counter31500i + 1;
end if;
else
counter31500i := counter31500i + 1;
end if;
-- 31250Hz
if counter31250i = 31 or counter31250i = 63 then
CK31250i <= not CK31250i;
if CONFIG(RTCSPEED) = "01" then
CKRTCi <= not CKRTCi;
end if;
if counter31250i = 63 then
counter31250i := (others => '0');
else
counter31250i := counter31250i + 1;
end if;
else
counter31250i := counter31250i + 1;
end if;
-- 15611Hz
if counter15611i = 63 or counter15611i = 127 then
CK15611i <= not CK15611i;
if CONFIG(RTCSPEED) = "10" then
CKRTCi <= not CKRTCi;
end if;
if counter15611i = 127 then
counter15611i := (others => '0');
else
counter15611i := counter15611i + 1;
end if;
else
counter15611i := counter15611i + 1;
end if;
-- 10000Hz
if counter10Ki = 99 or counter10Ki = 199 then
CK10Ki <= not CK10Ki;
if counter10Ki = 199 then
counter10Ki := (others => '0');
else
counter10Ki := counter10Ki + 1;
end if;
else
counter10Ki := counter10Ki + 1;
end if;
-- 5000Hz
if counter5Ki = 199 or counter5Ki = 399 then
CK5Ki <= not CK5Ki;
if counter5Ki = 399 then
counter5Ki := (others => '0');
else
counter5Ki := counter5Ki + 1;
end if;
else
counter5Ki := counter5Ki + 1;
end if;
-- 1000Hz
if counter1Ki = 999 or counter1Ki = 1999 then
CK1Ki <= not CK1Ki;
if counter1Ki = 1999 then
counter1Ki := (others => '0');
else
counter1Ki := counter1Ki + 1;
end if;
else
counter1Ki := counter1Ki + 1;
end if;
-- 500Hz
if counter500i = 1999 or counter500i = 3999 then
CK500i <= not CK500i;
if counter500i = 3999 then
counter500i := (others => '0');
else
counter500i := counter500i + 1;
end if;
else
counter500i := counter500i + 1;
end if;
-- 100Hz
if counter100i = 9999 or counter100i = 19999 then
CK100i <= not CK100i;
if counter100i = 19999 then
counter100i := (others => '0');
else
counter100i := counter100i + 1;
end if;
else
counter100i := counter100i + 1;
end if;
-- 50Hz
if counter50i = 19999 or counter50i = 39999 then
CK50i <= not CK50i;
if counter50i = 39999 then
counter50i := (others => '0');
else
counter50i := counter50i + 1;
end if;
else
counter50i := counter50i + 1;
end if;
-- 10Hz
if counter10i = 99999 or counter10i = 199999 then
CK10i <= not CK10i;
if counter10i = 199999 then
counter10i := (others => '0');
else
counter10i := counter10i + 1;
end if;
else
counter10i := counter10i + 1;
end if;
-- 5Hz
if counter5i = 199999 or counter5i = 399999 then
CK5i <= not CK5i;
if counter5i = 399999 then
counter5i := (others => '0');
else
counter5i := counter5i + 1;
end if;
else
counter5i := counter5i + 1;
end if;
-- 2Hz
if counter2i = 499999 or counter2i = 999999 then
CK2i <= not CK2i;
if counter2i = 999999 then
counter2i := (others => '0');
else
counter2i := counter2i + 1;
end if;
else
counter2i := counter2i + 1;
end if;
-- 1Hz
if counter1i = 999999 or counter1i = 1999999 then
CK1i <= not CK1i;
if counter1i = 1999999 then
counter1i := (others => '0');
else
counter1i := counter1i + 1;
end if;
else
counter1i := counter1i + 1;
end if;
-- 0.5Hz
if counter0_5i = 1999999 or counter0_5i = 3999999 then
CK0_5i <= not CK0_5i;
if counter0_5i = 3999999 then
counter0_5i := (others => '0');
else
counter0_5i := counter0_5i + 1;
end if;
else
counter0_5i := counter0_5i + 1;
end if;
-- 0.2Hz
if counter0_2i = 4999999 or counter0_2i = 9999999 then
CK0_2i <= not CK0_2i;
if counter0_2i = 9999999 then
counter0_2i := (others => '0');
else
counter0_2i := counter0_2i + 1;
end if;
else
counter0_2i := counter0_2i + 1;
end if;
-- 0.1Hz
if counter0_1i = 9999999 or counter0_1i = 19999999 then
CK0_1i <= not CK0_1i;
if counter0_1i = 19999999 then
counter0_1i := (others => '0');
else
counter0_1i := counter0_1i + 1;
end if;
else
counter0_1i := counter0_1i + 1;
end if;
end if;
end process;
-- Process the clocks according to the user selections and assign.
--
process (RST, PLLLOCKED1, PLLLOCKED2, PLLLOCKED3, CK112Mi)
begin
if RST = '1' or PLLLOCKED1 = '0' or PLLLOCKED2 = '0' or PLLLOCKED3 = '0' then
CKENCPUi <= '0';
CKENLEDSi <= '0';
CKENPERi <= '0';
CPUEDGE <= "00";
LEDSEDGE <= "00";
VIDEOEDGE <= "00";
CKVIDEOi <= '0';
PEREDGE <= "00";
elsif rising_edge(CK112Mi) then
-- Once the rising edge of the CPU clock is detected, enable the CPU Clock Enable signal
-- which is used to enable the master clock onto the logic.
CPUEDGE(0) <= CPUEDGE(1);
CKENCPUi <= '0';
if CPUEDGE = "10" then
CKENCPUi <= '1';
end if;
-- Once the rising edge of the LED clock is detected, enable the LED Clock Enable signal
-- which is used to enable the master clock onto the LED logic.
LEDSEDGE(0) <= LEDSEDGE(1);
CKENLEDSi <= '0';
if LEDSEDGE = "10" then
CKENLEDSi <= '1';
end if;
-- Once the rising edge of the Video clock is detected, enable the LED Clock Enable signal
-- which is used to enable the master clock onto the Video logic.
VIDEOEDGE(0) <= VIDEOEDGE(1);
CKENVIDEOi <= '0';
if VIDEOEDGE = "10" then
CKENVIDEOi <= '1';
end if;
-- Form the video frequency enable signal according to the user selection.
--
case CONFIG(VIDSPEED) is
when "000" => -- 8MHz
VIDEOEDGE(1) <= CK8Mi;
when "001" => -- 16MHz
VIDEOEDGE(1) <= CK16Mi;
when "010" => -- 8.8672375MHz
VIDEOEDGE(1) <= CK8M8672i;
when "011" => -- 17.734475MHz
VIDEOEDGE(1) <= CK17M734i;
when "100" => -- 25.175MHz - Standard VGA 640x480 mode.
VIDEOEDGE(1) <= CK25M175i;
when "101" => -- 8MHz
VIDEOEDGE(1) <= CK25M175i;
when "110" => -- 1368x768 VGA mode.
VIDEOEDGE(1) <= CK31M5i;
when "111" => -- Pixel clock for 1024x768 VGA mode. Should be 65Mhz.
VIDEOEDGE(1) <= CK25M175i;
end case;
-- The video clock is multiplexed with the correct frequency chosen for the video
-- mode. The actual clock is sent to the video module rather than an enable as skew
-- is less of an issue.
--
case CONFIG(VIDSPEED) is
when "000" => -- 8MHz
CKVIDEOi <= CK8Mi;
when "001" => -- 16MHz
CKVIDEOi <= CK16Mi;
when "010" => -- 8.8672375MHz
CKVIDEOi <= CK8M8672i;
when "011" => -- 17.734475MHz
CKVIDEOi <= CK17M734i;
when "100" => -- 25.175MHz - Standard VGA 640x480@60Hz mode.
CKVIDEOi <= CK25M175i;
when "101" => -- 25.175MHz - Standard VGA 640x480@60Hz mode.
CKVIDEOi <= CK25M175i;
when "110" => -- 640x480@75Hz mode.
CKVIDEOi <= CK31M5i;
when "111" => -- 25.175MHz - Standard VGA 640x480@60Hz mode.
CKVIDEOi <= CK25M175i;
end case;
-- The sound clock is multiplexed with the correct frequency according to model.
--
case CONFIG(SNDSPEED) is
when "01" =>
CKSOUNDi <= CK895Ki;
when "00" | "10" | "11" =>
CKSOUNDi <= CK2Mi;
end case;
-- Once the rising edge of the Peripherals clock is detected, enable the Peripheral Clock Enable signal
-- which is used to enable the master clock onto the Peripheral logic.
PEREDGE(0) <= PEREDGE(1);
CKENPERi <= '0';
if PEREDGE = "10" then
CKENPERi <= '1';
end if;
-- If debugging has been enabled and the debug cpu frequency set to a valid value, change cpu clock accordingly.
if DEBUG_ENABLE = 0 or DEBUG(ENABLED) = '0' or DEBUG(CPUFREQ) = "0000" then
-- The CPU speed is configured by the CMT register and CMT state or the CPU register. Select the right
-- frequency and form the clock by flipping on the right flip flag.
--
case CONFIG(CPUSPEED) is
when "0001" => -- 3.546875MHz
CPUEDGE(1) <= CK3M546875i;
when "0010" => -- 4MHz
CPUEDGE(1) <= CK4Mi;
when "0011" => -- 7.709MHz
CPUEDGE(1) <= CK7M709i;
when "0100" => -- 8MHz
CPUEDGE(1) <= CK8Mi;
when "0101" => -- 14.1875MHz
CPUEDGE(1) <= CK14M1875i;
when "0110" => -- 16MHz
CPUEDGE(1) <= CK16Mi;
when "0111" => -- 28.375MHz
CPUEDGE(1) <= CK28M375i;
when "1000" => -- 32MHz
CPUEDGE(1) <= CK32Mi;
when "1001" => -- 56.750MHz
CPUEDGE(1) <= CK56M750i;
when "1010" => -- 64MHz
CPUEDGE(1) <= CK64Mi;
-- Unallocated frequencies, use default.
when "0000" | "1011" | "1100" | "1101" | "1110" | "1111" => -- 2MHz
CPUEDGE(1) <= CK2Mi;
end case;
else
case DEBUG(CPUFREQ) is
when "0000" => -- Use normal cpu frequency, so this choice shouldnt be selected.
CPUEDGE(1) <= CK2Mi;
when "0001" => -- 1MHz
CPUEDGE(1) <= CK1Mi;
when "0010" => -- 100KHz
CPUEDGE(1) <= CK100Ki;
when "0011" => -- 10KHz
CPUEDGE(1) <= CK10Ki;
when "0100" => -- 5KHz
CPUEDGE(1) <= CK5Ki;
when "0101" => -- 1KHz
CPUEDGE(1) <= CK1Ki;
when "0110" => -- 500Hz
CPUEDGE(1) <= CK500i;
when "0111" => -- 100Hz
CPUEDGE(1) <= CK100i;
when "1000" => -- 50Hz
CPUEDGE(1) <= CK50i;
when "1001" => -- 10Hz
CPUEDGE(1) <= CK10i;
when "1010" => -- 5Hz
CPUEDGE(1) <= CK5i;
when "1011" => -- 2Hz
CPUEDGE(1) <= CK2i;
when "1100" => -- 1Hz
CPUEDGE(1) <= CK1i;
when "1101" => -- 0.5Hz
CPUEDGE(1) <= CK0_5i;
when "1110" => -- 0.2Hz
CPUEDGE(1) <= CK0_2i;
when "1111" => -- 0.1Hz
CPUEDGE(1) <= CK0_1i;
end case;
end if;
-- Sampling frequency of signals, typically used to drive LED outputs but could easily be read by an oscilloscope.
--
case DEBUG(SMPFREQ) is
when "0000" => -- Use normal cpu frequency.
LEDSEDGE(1) <= CPUEDGE(1);
when "0001" => -- 1MHz
LEDSEDGE(1) <= CK1Mi;
when "0010" => -- 100KHz
LEDSEDGE(1) <= CK100Ki;
when "0011" => -- 10KHz
LEDSEDGE(1) <= CK10Ki;
when "0100" => -- 5KHz
LEDSEDGE(1) <= CK5Ki;
when "0101" => -- 1KHz
LEDSEDGE(1) <= CK1Ki;
when "0110" => -- 500Hz
LEDSEDGE(1) <= CK500i;
when "0111" => -- 100Hz
LEDSEDGE(1) <= CK100i;
when "1000" => -- 50Hz
LEDSEDGE(1) <= CK50i;
when "1001" => -- 10Hz
LEDSEDGE(1) <= CK10i;
when "1010" => -- 5Hz
LEDSEDGE(1) <= CK5i;
when "1011" => -- 2Hz
LEDSEDGE(1) <= CK2i;
when "1100" => -- 1Hz
LEDSEDGE(1) <= CK1i;
when "1101" => -- 0.5Hz
LEDSEDGE(1) <= CK0_5i;
when "1110" => -- 0.2Hz
LEDSEDGE(1) <= CK0_2i;
when "1111" => -- 0.1Hz
LEDSEDGE(1) <= CK0_1i;
end case;
-- Form the RTC frequency enable signal according to the user selection.
--
case CONFIG(PERSPEED) is
when "00" => -- 2MHz
PEREDGE(1) <= CK2Mi;
when "01" | "10" | "11" => -- 2MHz
PEREDGE(1) <= CK2Mi;
end case;
end if;
end process;
-- Assign necessary clocks and enables.
--
CLKBUS(CKMASTER) <= CK112Mi;
CLKBUS(CKSOUND) <= CKSOUNDi; -- Sound base clock, 50/50 duty cycle.
CLKBUS(CKRTC) <= CKRTCi; -- RTC base clock, 50/50 duty cycle.
CLKBUS(CKENVIDEO) <= CKENVIDEOi; -- Enable signal for video base clock.
CLKBUS(CKVIDEO) <= CKVIDEOi; -- Clock signal for video base clock.
CLKBUS(CKENCPU) <= CKENCPUi; -- Enable signal for CPU base clock.
CLKBUS(CKENLEDS) <= CKENLEDSi; -- Enable signal for LEDS base clock.
CLKBUS(CKENPERIPH) <= CKENPERi; -- Enable signal for Peripheral base clock.
CLKBUS(CKIOP) <= CK64Mi;
end RTL;

1615
common/cmt.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

34
common/config_pkg.vhd Normal file
View File

@@ -0,0 +1,34 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: config_pkg.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series compilation configuration parameters.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: September 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
package config_pkg is
constant DEBUG_ENABLE : integer := 1; -- Enable debug logic,
constant NEO_ENABLE : integer := 0; -- Enable local NEO430 IO processor,
constant STORM_ENABLE : integer := 1; -- Enable local STORM IO processor,
end config_pkg;

169
common/dpram.vhd Normal file
View File

@@ -0,0 +1,169 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: dpram.vhd
-- Created: July 2018
-- Author(s): Altera/Intel - refactored by Philip Smart
-- Description: Dual Port RAM as provided by Altera in the Megafunctions suite.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
widthad_b : natural;
width_b : natural := 8;
-- clock_en_a : string := "NORMAL";
-- clock_en_b : string := "NORMAL";
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
clock_a : IN STD_LOGIC;
clocken_a : IN STD_LOGIC := '1';
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
clock_b : IN STD_LOGIC;
clocken_b : IN STD_LOGIC := '1';
address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
wren_b : IN STD_LOGIC := '1';
q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
clocken0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
clock1 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
wren_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_b-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_b,
operation_mode => "BIDIR_DUAL_PORT",
--operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_b,
width_a => width_a,
width_b => width_b,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clock0 => clock_a,
clocken0 => clocken_a,
address_a => address_a,
data_a => data_a,
wren_a => wren_a,
q_a => sub_wire0,
clock1 => clock_b,
clocken1 => clocken_b,
address_b => address_b,
wren_b => wren_b,
data_b => data_b,
q_b => sub_wire1
);
END SYN;

160
common/dprom.vhd Normal file
View File

@@ -0,0 +1,160 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: dprom.vhd
-- Created: July 2018
-- Author(s): Altera/Intel - refactored by Philip Smart
-- Description: Dual Port ROM as provided by Altera in the Megafunctions suite.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_b : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_b : IN STD_LOGIC;
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dprom;
ARCHITECTURE SYN OF dprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock1 : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
--operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
clock0 => clock_a,
data_a => data_a,
wren_a => wren_a,
q_a => sub_wire0,
address_b => address_b,
clock1 => clock_b,
data_b => data_b,
wren_b => wren_b,
q_b => sub_wire1
);
END SYN;

65
common/functions.vhd Normal file
View File

@@ -0,0 +1,65 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: functions.vhd
-- Created: October 2018
-- Author(s): Philip Smart
-- Description: Collection of re-usable functions for the SharpMZ Project.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: October 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
package functions_pkg is
-- Function to reverse the order of the bits in a standard logic vector.
-- ie. 1010 becomes 0101
function reverse_vector(slv:std_logic_vector) return std_logic_vector;
-- Function to convert an integer (0 or 1) into std_logic.
--
function to_std_logic(i : in integer) return std_logic;
end functions_pkg;
package body functions_pkg is
function reverse_vector(slv:std_logic_vector) return std_logic_vector is
variable target : std_logic_vector(slv'high downto slv'low);
begin
for idx in slv'high downto slv'low loop
target(idx) := slv(slv'low + (slv'high-idx));
end loop;
return target;
end reverse_vector;
function to_std_logic(i : in integer) return std_logic is
begin
if i = 0 then
return '0';
end if;
return '1';
end function;
end functions_pkg;

214
common/i8254/i8254.vhd Normal file
View File

@@ -0,0 +1,214 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: i8254.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series i8254 Timer
-- This module emulates the Intel i8254 Programmable Interval Timer.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial write.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i8254 is
Port (
RST : in std_logic;
CLK : in std_logic;
ENA : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
WR_n : in std_logic;
RD_n : in std_logic;
--
CLK0 : in std_logic;
GATE0 : in std_logic;
OUT0 : out std_logic;
CLK1 : in std_logic;
GATE1 : in std_logic;
OUT1 : out std_logic;
CLK2 : in std_logic;
GATE2 : in std_logic;
OUT2 : out std_logic
);
end i8254;
architecture Behavioral of i8254 is
signal WREN : std_logic;
signal RDEN : std_logic;
signal WRCTRLEN : std_logic;
signal WR0 : std_logic;
signal WR1 : std_logic;
signal WR2 : std_logic;
signal RD0 : std_logic;
signal RD1 : std_logic;
signal RD2 : std_logic;
signal DO0 : std_logic_vector(7 downto 0);
signal DO1 : std_logic_vector(7 downto 0);
signal DO2 : std_logic_vector(7 downto 0);
signal LDO0 : std_logic_vector(7 downto 0);
signal LDO1 : std_logic_vector(7 downto 0);
signal LDO2 : std_logic_vector(7 downto 0);
signal READDATA_NEXT : std_logic_vector(7 downto 0);
signal CTRLM0 : std_logic;
signal CTRLM1 : std_logic;
signal CTRLM2 : std_logic;
signal LATCNT0 : std_logic;
signal LATCNT1 : std_logic;
signal LATCNT2 : std_logic;
signal LATSTS0 : std_logic;
signal LATSTS1 : std_logic;
signal LATSTS2 : std_logic;
component i8254_counter
Port (
CLK : in std_logic;
RESET : in std_logic;
--
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
WRITE : in std_logic;
READ : in std_logic;
CTRL_MODE_EN : in std_logic;
LATCH_COUNT_EN : in std_logic;
LATCH_STATUS_EN : in std_logic;
--
CTR_CLK : in std_logic;
CTR_GATE : in std_logic;
CTR_OUT : out std_logic
);
end component;
begin
-- Create signals to select a given register for read or write.
--
WREN <= '1' when ENA = '1' and CS_n = '0' and WR_n = '0'
else '0';
RDEN <= '1' when ENA = '1' and CS_n = '0' and RD_n = '0'
else '0';
WRCTRLEN <= '1' when WREN = '1' and A = "11"
else '0';
WR0 <= '1' when WREN = '1' and A = "00"
else '0';
WR1 <= '1' when WREN = '1' and A = "01"
else '0';
WR2 <= '1' when WREN = '1' and A = "10"
else '0';
RD0 <= '1' when RDEN = '1' and A = "00"
else '0';
RD1 <= '1' when RDEN = '1' and A = "01"
else '0';
RD2 <= '1' when RDEN = '1' and A = "10"
else '0';
-- Create signals to enable setting of a command, a count value or latching status per counter.
--
CTRLM0 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "00" and DI(5 downto 4) /= "00"
else '0';
CTRLM1 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "01" and DI(5 downto 4) /= "00"
else '0';
CTRLM2 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "10" and DI(5 downto 4) /= "00"
else '0';
LATCNT0 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "00" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(1) = '1'))
else '0';
LATCNT1 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "01" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(2) = '1'))
else '0';
LATCNT2 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "10" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(3) = '1'))
else '0';
LATSTS0 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(1) = '1'
else '0';
LATSTS1 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(2) = '1'
else '0';
LATSTS2 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(3) = '1'
else '0';
-- Assign the counter whose address is active. Not permissible to read back control register.
--
DO <= DO0 when A = "00"
else
DO1 when A = "01"
else
DO2 when A = "10"
else
(others => '0');
-- Instantiate the 3 counters within the 8254.
--
CTR0 : i8254_counter port map (
CLK => CLK,
RESET => RST,
--
DATA_IN => DI,
DATA_OUT => DO0,
WRITE => WR0,
READ => RD0,
CTRL_MODE_EN => CTRLM0,
LATCH_COUNT_EN => LATCNT0,
LATCH_STATUS_EN => LATSTS0,
--
CTR_CLK => CLK0,
CTR_GATE => GATE0,
CTR_OUT => OUT0
);
CTR1 : i8254_counter port map (
CLK => CLK,
RESET => RST,
--
DATA_IN => DI,
DATA_OUT => DO1,
WRITE => WR1,
READ => RD1,
CTRL_MODE_EN => CTRLM1,
LATCH_COUNT_EN => LATCNT1,
LATCH_STATUS_EN => LATSTS1,
--
CTR_CLK => CLK1,
CTR_GATE => GATE1,
CTR_OUT => OUT1
);
CTR2 : i8254_counter port map (
CLK => CLK,
RESET => RST,
--
DATA_IN => DI,
DATA_OUT => DO2,
WRITE => WR2,
READ => RD2,
CTRL_MODE_EN => CTRLM2,
LATCH_COUNT_EN => LATCNT2,
LATCH_STATUS_EN => LATSTS2,
--
CTR_CLK => CLK2,
CTR_GATE => GATE2,
CTR_OUT => OUT2
);
end Behavioral;

523
common/i8254/i8254_counter.vhd Normal file
View File

@@ -0,0 +1,523 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: i8254_counter.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series i8254 Timer
-- This module emulates the Intel i8254 Programmable Interval Timer.
--
-- Credits: Based on Verilog pit_counter by Aleksander Osman, 2014.
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial write.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i8254_counter is
Port (
CLK : in std_logic;
RESET : in std_logic;
--
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
WRITE : in std_logic;
READ : in std_logic;
CTRL_MODE_EN : in std_logic;
LATCH_COUNT_EN : in std_logic;
LATCH_STATUS_EN : in std_logic;
--
CTR_CLK : in std_logic;
CTR_GATE : in std_logic;
CTR_OUT : out std_logic
);
end i8254_counter;
architecture Behavioral of i8254_counter is
subtype LSB is integer range 7 downto 0;
subtype MSB is integer range 15 downto 8;
signal MODE : std_logic_vector(2 downto 0);
signal RW_MODE : std_logic_vector(1 downto 0);
signal BCD : std_logic;
signal REGISTER_IN : std_logic_vector(15 downto 0);
signal REGISTER_OUT : std_logic_vector(15 downto 0);
signal REGISTER_OUT_LATCHED : std_logic;
signal NULL_COUNTER : std_logic;
signal MSB_WRITE : std_logic;
signal MSB_READ : std_logic;
signal STATUS : std_logic_vector(7 downto 0);
signal STATUS_LATCHED : std_logic;
--
signal CLOCK_LAST : std_logic;
signal CLOCK_PULSE : std_logic;
signal GATE_LAST : std_logic;
signal GATE_SAMPLED : std_logic;
signal TRIGGER : std_logic;
signal TRIGGER_SAMPLED : std_logic;
signal WRITTEN : std_logic;
signal LOADED : std_logic;
signal CTR_OUTi : std_logic;
--
signal MODE0 : std_logic;
signal MODE1 : std_logic;
signal MODE2 : std_logic;
signal MODE3 : std_logic;
signal MODE4 : std_logic;
signal MODE5 : std_logic;
signal LOAD : std_logic;
signal LOAD_MODE0 : std_logic;
signal LOAD_MODE1 : std_logic;
signal LOAD_MODE2 : std_logic;
signal LOAD_MODE3 : std_logic;
signal LOAD_MODE4 : std_logic;
signal LOAD_MODE5 : std_logic;
signal LOAD_EVEN : std_logic;
signal ENABLE_MODE0 : std_logic;
signal ENABLE_MODE1 : std_logic;
signal ENABLE_MODE2 : std_logic;
signal ENABLE_MODE3 : std_logic;
signal ENABLE_MODE4 : std_logic;
signal ENABLE_MODE5 : std_logic;
signal ENABLE_DOUBLE : std_logic;
signal ENABLE : std_logic;
signal BCD_DIGIT_1 : std_logic_vector(3 downto 0);
signal BCD_DIGIT_2 : std_logic_vector(3 downto 0);
signal BCD_DIGIT_3 : std_logic_vector(3 downto 0);
signal COUNTER_MINUS_1 : std_logic_vector(15 downto 0);
signal COUNTER_MINUS_2 : std_logic_vector(15 downto 0);
signal COUNTER : std_logic_vector(15 downto 0);
begin
-- Control register settings. A write to the control register sets up the mode of this counter, wether it
-- uses BCD or 16 bit binary and how the data is accessed, ie. LSB, MSB or both.
--
process(RESET, CLK)
begin
if RESET = '1' then
MODE <= "010";
BCD <= '0';
RW_MODE <= "01";
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
MODE <= DATA_IN(3 downto 1);
BCD <= DATA_IN(0);
RW_MODE <= DATA_IN(5 downto 4);
end if;
end if;
end process;
-- Staging counter loading. Depending on the mode, the byte is stored in the LSB, NSB or according to the write flag
-- for 16 bit mode. The staging counter is used to load the main counter.
--
process(RESET, CLK)
begin
if RESET = '1' then
REGISTER_IN <= (others => '0');
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
REGISTER_IN <= (others => '0');
elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '0' then
REGISTER_IN(LSB) <= DATA_IN;
elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '1' then
REGISTER_IN(MSB) <= DATA_IN;
elsif WRITE = '1' and RW_MODE = "01" then
REGISTER_IN(LSB) <= DATA_IN;
elsif WRITE = '1' and RW_MODE = "10" then
REGISTER_IN(MSB) <= DATA_IN;
end if;
end if;
end process;
-- Store the counter contents on every clock until a latch request is made, then we suspend storing
-- until data is read.
--
process(RESET, CLK)
begin
if RESET = '1' then
REGISTER_OUT <= (others => '0');
elsif CLK'event and CLK = '1' then
-- Store each clock cycle, stop on the clock between LATCH going active and REGISTER_OUT_LATCHED going active.
--
if LATCH_COUNT_EN = '1' and REGISTER_OUT_LATCHED = '0' then
REGISTER_OUT <= COUNTER(15 downto 0);
elsif REGISTER_OUT_LATCHED = '0' then
REGISTER_OUT <= COUNTER(15 downto 0);
end if;
end if;
end process;
-- Set the output latched signal if LATCH_COUNT_EN goes high, this will stop the storing of the counter until
-- output latch is cleared, which can be done by a control register access or a 1/2 byte read depending on mode.
--
process(RESET, CLK)
begin
if RESET = '1' then
REGISTER_OUT_LATCHED <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
REGISTER_OUT_LATCHED <= '0';
elsif LATCH_COUNT_EN = '1' then
REGISTER_OUT_LATCHED <= '1';
elsif (READ = '1' and (RW_MODE /= "11" or MSB_READ = '1')) then
REGISTER_OUT_LATCHED <= '0';
end if;
end if;
end process;
-- Status flag null count - indicates if the counter can be read (0) or it is being loaded (1).
--
process(RESET, CLK)
begin
if RESET = '1' then
NULL_COUNTER <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
NULL_COUNTER <= '1';
elsif (WRITE = '1' and (RW_MODE /= "11" or MSB_WRITE = '1')) then
NULL_COUNTER <= '1';
elsif LOAD = '1' then
NULL_COUNTER <= '0';
end if;
end if;
end process;
-- Double byte handling for 16 bit load and fetch. An access to the control register resets the flag,
-- but on each write or read it gets toggled. The flag indicates wether the LSB(0) or MSB(1) is being read or writted.
--
process(RESET, CLK)
begin
if RESET = '1' then
MSB_WRITE <= '0';
MSB_READ <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
MSB_WRITE <= '0';
MSB_READ <= '0';
elsif WRITE = '1' and RW_MODE = "11" then
MSB_WRITE <= not MSB_WRITE;
elsif READ = '1' and RW_MODE = "11" then
MSB_READ <= not MSB_READ;
end if;
end if;
end process;
-- Status register, contains the Output pin value, the state on the counter being read (1 = can be read) and the programmed
-- mode of the counter. The current values are latched during the clock between the LATCH_STATUS_EN going active and the latched
-- signal going active.
--
process(RESET, CLK)
begin
if RESET = '1' then
STATUS <= (others => '0');
elsif CLK'event and CLK = '1' then
if LATCH_STATUS_EN = '1' and STATUS_LATCHED = '0' then
STATUS <= CTR_OUTi & NULL_COUNTER & RW_MODE & MODE & BCD;
end if;
end if;
end process;
-- Set the status latch signal if the LATCH_STATUS_EN goes active. Any read or control mode access resets the flag.
--
process(RESET, CLK)
begin
if RESET = '1' then
STATUS_LATCHED <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
STATUS_LATCHED <= '0';
elsif LATCH_STATUS_EN = '1' then
STATUS_LATCHED <= '1';
elsif READ = '1' then
STATUS_LATCHED <= '0';
end if;
end if;
end process;
-- Set the internal counter signals according to the output clock and gate.
--
process(RESET, CLK)
begin
if RESET = '1' then
CLOCK_PULSE <= '0';
CLOCK_LAST <= '0';
GATE_LAST <= '1';
GATE_SAMPLED <= '0';
TRIGGER <= '0';
TRIGGER_SAMPLED <= '0';
elsif CLK'event and CLK = '1' then
CLOCK_LAST <= CTR_CLK;
GATE_LAST <= CTR_GATE;
if CLOCK_LAST = '1' and CTR_CLK = '0' then
CLOCK_PULSE <= '1';
else
CLOCK_PULSE <= '0';
end if;
if CLOCK_LAST = '0' and CTR_CLK = '1' then
GATE_SAMPLED <= CTR_GATE;
TRIGGER_SAMPLED <= TRIGGER;
end if;
if GATE_LAST = '0' and CTR_GATE = '1' then
TRIGGER <= '1';
elsif CLOCK_LAST = '0' and CTR_CLK = '1' then
TRIGGER <= '0';
end if;
end if;
end process;
-- Set the counter output according to programmed mode and events.
--
process(RESET, CLK)
begin
if RESET = '1' then
CTR_OUTi <= '1';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
if MODE0 = '1' then
CTR_OUTi <= '0';
elsif MODE1 = '1' or MODE2 = '1' or MODE3 = '1' or MODE4 = '1' or MODE5 = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE0 = '1' then
if WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '0' then
CTR_OUTi <= '0';
elsif WRITTEN = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE1 = '1' then
if LOAD = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE2 = '1' then
if CTR_GATE = '0' then
CTR_OUTi <= '1';
elsif COUNTER = "0000000000000010" and ENABLE = '1' then
CTR_OUTi <= '0';
elsif LOAD = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE3 = '1' then
if CTR_GATE = '0' then
CTR_OUTi <= '1';
elsif LOAD = '1' and COUNTER = "000000000000010" and CTR_OUTi = '1' and REGISTER_IN(0) = '0' then
CTR_OUTi <= '0';
elsif LOAD = '1' and COUNTER = "000000000000000" and CTR_OUTi = '1' and REGISTER_IN(0) = '1' then
CTR_OUTi <= '0';
elsif LOAD = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE4 = '1' then
if LOAD = '1' then
CTR_OUTi <= '1';
elsif COUNTER = "0000000000000010" and ENABLE = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE5 = '1' then
if COUNTER = "0000000000000010" and ENABLE = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
end if;
end if;
end process;
-- Setup flags to indicate if the counter has been written to or loaded. These flags then determine loading operation
-- of the staging counter into the counter.
--
process(RESET, CLK)
begin
if RESET = '1' then
WRITTEN <= '0';
LOADED <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
WRITTEN <= '0';
elsif WRITE = '1' and RW_MODE /= "11" then
WRITTEN <= '1';
elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '1' then
WRITTEN <= '1';
elsif LOAD = '1' then
WRITTEN <= '0';
end if;
if CTRL_MODE_EN = '1' then
LOADED <= '0';
elsif LOAD = '1' then
LOADED <= '1';
end if;
end if;
end process;
-- Process to present the requested data, according to mode, to the uC. The data is latched for timing delay to allow the uC
-- more time to read the byte.
--
process(RESET, CLK)
begin
if RESET = '1' then
DATA_OUT <= (others => '0');
elsif CLK'event and CLK = '1' then
if STATUS_LATCHED = '1' then
DATA_OUT <= STATUS;
elsif RW_MODE = "11" and MSB_READ = '0' then
DATA_OUT <= REGISTER_OUT(LSB);
elsif RW_MODE = "11" and MSB_READ = '1' then
DATA_OUT <= REGISTER_OUT(MSB);
elsif RW_MODE = "01" then
DATA_OUT <= REGISTER_OUT(LSB);
else
DATA_OUT <= REGISTER_OUT(MSB);
end if;
end if;
end process;
-- Load up the primary counter according to the programmed mode and load signals coming from the uC.
--
process(RESET, CLK)
begin
if RESET = '1' then
COUNTER <= (others => '1');
elsif CLK'event and CLK = '1' then
if LOAD_EVEN = '1' then
COUNTER <= REGISTER_IN(15 downto 1) & '0';
elsif LOAD = '1' then
COUNTER <= REGISTER_IN;
elsif ENABLE_DOUBLE = '1' then
COUNTER <= COUNTER_MINUS_2;
elsif ENABLE = '1' then
COUNTER <= COUNTER_MINUS_1;
end if;
end if;
end process;
-- Quick reference signals to indicate programmed mode.
--
MODE0 <= '1' when MODE = "000"
else '0';
MODE1 <= '1' when MODE = "001"
else '0';
MODE2 <= '1' when MODE(1 downto 0) = "10"
else '0';
MODE3 <= '1' when MODE(1 downto 0) = "11"
else '0';
MODE4 <= '1' when MODE = "100"
else '0';
MODE5 <= '1' when MODE = "101"
else '0';
-- Quick reference signals to indicate a load is required for a given mode.
--
LOAD_MODE0 <= '1' when MODE0 = '1' and WRITTEN = '1'
else '0';
LOAD_MODE1 <= '1' when MODE1 = '1' and WRITTEN = '1' and TRIGGER_SAMPLED = '1'
else '0';
LOAD_MODE2 <= '1' when MODE2 = '1' and (WRITTEN = '1' or TRIGGER_SAMPLED = '1' or (LOADED = '1' and GATE_SAMPLED = '1' and COUNTER = "0000000000000001"))
else '0';
LOAD_MODE3 <= '1' when MODE3 = '1' and (WRITTEN = '1' or TRIGGER_SAMPLED = '1' or (LOADED = '1' and GATE_SAMPLED = '1' and ((COUNTER = "0000000000000010" and (REGISTER_IN(0) = '0' or CTR_OUTi = '0')) or (COUNTER = "0000000000000000" and REGISTER_IN(0) = '1' and CTR_OUTi = '1'))))
else '0';
LOAD_MODE4 <= '1' when MODE4 = '1' and WRITTEN = '1'
else '0';
LOAD_MODE5 <= '1' when MODE5 = '1' and (WRITTEN = '1' or LOADED = '1') and TRIGGER_SAMPLED = '1'
else '0';
-- Quick reference signals to indicate a programmed mode can be enabled and set running.
--
ENABLE_MODE0 <= '1' when MODE0 = '1' and GATE_SAMPLED = '1' and MSB_WRITE = '0'
else '0';
ENABLE_MODE1 <= '1' when MODE1 = '1'
else '0';
ENABLE_MODE2 <= '1' when MODE2 = '1' and GATE_SAMPLED = '1'
else '0';
ENABLE_MODE3 <= '1' when MODE3 = '1' and GATE_SAMPLED = '1'
else '0';
ENABLE_MODE4 <= '1' when MODE4 = '1' and GATE_SAMPLED = '1'
else '0';
ENABLE_MODE5 <= '1' when MODE5 = '1'
else '0';
-- Signals to indicate the type of data to be loaded into the primary counter according to programmed mode.
--
LOAD <= '1' when CLOCK_PULSE = '1' and (LOAD_MODE0 = '1' or LOAD_MODE1 = '1' or LOAD_MODE2 = '1' or LOAD_MODE3 = '1' or LOAD_MODE4 = '1' or LOAD_MODE5 = '1')
else '0';
LOAD_EVEN <= '1' when LOAD = '1' and MODE3 = '1'
else '0';
ENABLE <= '1' when LOAD = '0' and LOADED = '1' and CLOCK_PULSE = '1' and (ENABLE_MODE0 = '1' or ENABLE_MODE1 = '1' or ENABLE_MODE2 = '1' or ENABLE_MODE4 = '1' or ENABLE_MODE5 = '1')
else '0';
ENABLE_DOUBLE<= '1' when LOAD = '0' and LOADED = '1' and CLOCK_PULSE = '1' and ENABLE_MODE3 = '1'
else '0';
-- BCD logic. Calculate each digit to ease the main
BCD_DIGIT_3 <= COUNTER(15 downto 12) - X"1";
BCD_DIGIT_2 <= COUNTER(11 downto 8) - X"1";
BCD_DIGIT_1 <= COUNTER(7 downto 4) - X"1";
-- Count down of the primary counter, 1 clock at a time. If we are in BCD mode, adjust count to reflect the BCD value, otherwise make
-- a normal binary countdown.
--
COUNTER_MINUS_1 <= X"9999" when BCD = '1' and COUNTER = X"0000"
else
BCD_DIGIT_3 & X"999" when BCD = '1' and COUNTER(11 downto 0) = X"000"
else
COUNTER(15 downto 12) & BCD_DIGIT_2 & X"99" when BCD = '1' and COUNTER(7 downto 0) = X"00"
else
COUNTER(15 downto 8) & BCD_DIGIT_1 & X"9" when BCD = '1' and COUNTER(3 downto 0) = X"0"
else
COUNTER - X"0001";
-- Count down evenly. Same as above but we count down 2 clocks at a time.
--
COUNTER_MINUS_2 <= X"9998" when BCD = '1' and COUNTER = X"0000"
else
BCD_DIGIT_3 & X"998" when BCD = '1' and COUNTER(11 downto 0) = X"000"
else
COUNTER(15 downto 12) & BCD_DIGIT_2 & X"98" when BCD = '1' and COUNTER(7 downto 0) = X"00"
else
COUNTER(15 downto 8) & BCD_DIGIT_1 & X"8" when BCD = '1' and COUNTER(3 downto 0) = X"0"
else
COUNTER - X"0002";
-- Counter output.
--
CTR_OUT <= CTR_OUTi;
end Behavioral;

715
common/i8255/i8255.vhd Normal file
View File

@@ -0,0 +1,715 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: i8255.vhd
-- Created: Feb 2007
-- Author(s): MikeJ (fpgaarcade), refactored and adapted for this emulation by Philip Smart
-- Description: Sharp MZ series i8255 PPI
-- This module emulates the Intel i8255 Programmable Peripheral Interface chip.
--
-- Credits:
-- Copyright: (c) MikeJ - Feb 2007
--
-- History: July 2018 - Initial module refactored and updated for this emulation.
--
---------------------------------------------------------------------------------------------------------
--
-- Original copyright notice below:-
--
-- A simulation model of i8255 PIA
-- Copyright (c) MikeJ - Feb 2007
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
---------------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity i8255 is
port (
RESET : in std_logic;
CLK : in std_logic;
ENA : in std_logic; -- (CPU) clk enable
ADDR : in std_logic_vector(1 downto 0); -- A1-A0
DI : in std_logic_vector(7 downto 0); -- D7-D0
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
PA_I : in std_logic_vector(7 downto 0);
PA_O : out std_logic_vector(7 downto 0);
PA_O_OE_n : out std_logic_vector(7 downto 0);
PB_I : in std_logic_vector(7 downto 0);
PB_O : out std_logic_vector(7 downto 0);
PB_O_OE_n : out std_logic_vector(7 downto 0);
PC_I : in std_logic_vector(7 downto 0);
PC_O : out std_logic_vector(7 downto 0);
PC_O_OE_n : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of i8255 is
-- registers
signal BIT_MASK : std_logic_vector(7 downto 0);
signal R_PORTA : std_logic_vector(7 downto 0);
signal R_PORTB : std_logic_vector(7 downto 0);
signal R_PORTC : std_logic_vector(7 downto 0);
signal R_CONTROL : std_logic_vector(7 downto 0);
--
signal PORTA_WE : std_logic;
signal PORTB_WE : std_logic;
signal PORTA_RE : std_logic;
signal PORTB_RE : std_logic;
--
signal PORTA_WE_T1 : std_logic;
signal PORTB_WE_T1 : std_logic;
signal PORTA_RE_T1 : std_logic;
signal PORTB_RE_T1 : std_logic;
--
signal PORTA_WE_RISING : boolean;
signal PORTB_WE_RISING : boolean;
signal PORTA_RE_RISING : boolean;
signal PORTB_RE_RISING : boolean;
--
signal GROUPA_MODE : std_logic_vector(1 downto 0); -- port a/c upper
signal GROUPB_MODE : std_logic; -- port b/c lower
--
signal PORTA_READ : std_logic_vector(7 downto 0);
signal PORTB_READ : std_logic_vector(7 downto 0);
signal PORTC_READ : std_logic_vector(7 downto 0);
signal CONTROL_READ : std_logic_vector(7 downto 0);
signal MODE_CLEAR : std_logic;
--
signal A_INTE1 : std_logic;
signal A_INTE2 : std_logic;
signal B_INTE : std_logic;
--
signal A_INTR : std_logic;
signal A_OBF_L : std_logic;
signal A_IBF : std_logic;
signal A_ACK_L : std_logic;
signal A_STB_L : std_logic;
signal A_ACK_L_T1 : std_logic;
signal A_STB_L_T1 : std_logic;
--
signal B_INTR : std_logic;
signal B_OBF_L : std_logic;
signal B_IBF : std_logic;
signal B_ACK_L : std_logic;
signal B_STB_L : std_logic;
signal B_ACK_L_T1 : std_logic;
signal B_STB_L_T1 : std_logic;
--
signal A_ACK_L_RISING : boolean;
signal A_STB_L_RISING : boolean;
signal B_ACK_L_RISING : boolean;
signal B_STB_L_RISING : boolean;
--
signal PORTA_IPREG : std_logic_vector(7 downto 0);
signal PORTB_IPREG : std_logic_vector(7 downto 0);
begin
--
-- mode 0 - basic input/output
-- mode 1 - strobed input/output
-- mode 2/3 - bi-directional bus
--
-- control word (write)
--
-- D7 mode set flag 1 = active
-- D6..5 GROUPA mode selection (mode 0,1,2)
-- D4 GROUPA porta 1 = input, 0 = output
-- D3 GROUPA portc upper 1 = input, 0 = output
-- D2 GROUPB mode selection (mode 0 ,1)
-- D1 GROUPB portb 1 = input, 0 = output
-- D0 GROUPB portc lower 1 = input, 0 = output
--
-- D7 bit set/reset 0 = active
-- D6..4 x
-- D3..1 bit select
-- d0 1 = set, 0 - reset
--
-- all output registers including status are reset when mode is changed
-- 1. Port A:
-- All Modes: Output data is cleared, input data is not cleared.
-- 2. Port B:
-- Mode 0: Output data is cleared, input data is not cleared.
-- Mode 1 and 2: Both output and input data are cleared.
-- 3. Port C:
-- Mode 0:Output data is cleared, input data is not cleared.
-- Mode 1 and 2: IBF and INTR are cleared and OBF# is set.
-- Outputs in Port C which are not used for handshaking or interrupt signals are cleared.
-- Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled.
P_BIT_MASK : process(DI)
begin
BIT_MASK <= x"01";
case DI(3 downto 1) is
when "000" => BIT_MASK <= x"01";
when "001" => BIT_MASK <= x"02";
when "010" => BIT_MASK <= x"04";
when "011" => BIT_MASK <= x"08";
when "100" => BIT_MASK <= x"10";
when "101" => BIT_MASK <= x"20";
when "110" => BIT_MASK <= x"40";
when "111" => BIT_MASK <= x"80";
when others => null;
end case;
end process;
P_WRITE_REG_RESET : process(RESET, CLK)
variable R_PORTC_masked : std_logic_vector(7 downto 0);
variable R_PORTC_setclr : std_logic_vector(7 downto 0);
begin
if (RESET = '1') then
R_PORTA <= x"00";
R_PORTB <= x"00";
R_PORTC <= x"00";
R_CONTROL <= x"9B"; -- 10011011
MODE_CLEAR <= '1';
elsif CLK'event and CLK = '1' then
R_PORTC_masked := (not BIT_MASK) and R_PORTC;
for i in 0 to 7 loop
R_PORTC_setclr(i) := BIT_MASK(i) and DI(0);
end loop;
if (ENA = '1') then
MODE_CLEAR <= '0';
if (CS_n = '0') and (WR_n = '0') then
case ADDR is
when "00" => R_PORTA<= DI;
when "01" => R_PORTB<= DI;
when "10" => R_PORTC<= DI;
when "11" =>
if (DI(7) = '0') then -- set/clr
R_PORTC <= R_PORTC_masked or R_PORTC_setclr;
else
--MODE_CLEAR <= '1';
--R_PORTA <= x"00";
--R_PORTB <= x"00"; -- clear port b input reg
--R_PORTC <= x"00"; -- clear control sigs
R_CONTROL <= DI; -- load new mode
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
P_DECODE_CONTROL : process(R_CONTROL)
begin
GROUPA_MODE <= R_CONTROL(6 downto 5);
GROUPB_MODE <= R_CONTROL(2);
end process;
P_READ : process(ADDR, PORTA_READ, PORTB_READ, PORTC_READ, CONTROL_READ)
begin
DO <= x"00"; -- default
--if (CS_n = '0') and (RD_n = '0') then -- not required
case ADDR is
when "00" => DO <= PORTA_READ;
when "01" => DO <= PORTB_READ;
when "10" => DO <= PORTC_READ;
when "11" => DO <= CONTROL_READ;
when others => null;
end case;
--end if;
end process;
CONTROL_READ(7) <= '1'; -- always 1
CONTROL_READ(6 downto 0) <= R_CONTROL(6 downto 0);
P_RW_CONTROL : process(CS_n, RD_n, WR_n, ADDR)
begin
PORTA_WE <= '0';
PORTB_WE <= '0';
PORTA_RE <= '0';
PORTB_RE <= '0';
if (CS_n = '0') and (ADDR = "00") then
PORTA_WE <= not WR_n;
PORTA_RE <= not RD_n;
end if;
if (CS_n = '0') and (ADDR = "01") then
PORTB_WE <= not WR_n;
PORTB_RE <= not RD_n;
end if;
end process;
P_RW_CONTROL_REG : process(RESET, CLK)
begin
if RESET = '1' then
PORTA_WE_T1 <= '0';
PORTB_WE_T1 <= '0';
PORTA_RE_T1 <= '0';
PORTB_RE_T1 <= '0';
A_STB_L_T1 <= '0';
A_ACK_L_T1 <= '0';
B_STB_L_T1 <= '0';
B_ACK_L_T1 <= '0';
elsif CLK'event and CLK = '1' then
if (ENA = '1') then
PORTA_WE_T1 <= PORTA_WE;
PORTB_WE_T1 <= PORTB_WE;
PORTA_RE_T1 <= PORTA_RE;
PORTB_RE_T1 <= PORTB_RE;
A_STB_L_T1 <= A_STB_L;
A_ACK_L_T1 <= A_ACK_L;
B_STB_L_T1 <= B_STB_L;
B_ACK_L_T1 <= B_ACK_L;
end if ;
end if;
end process;
PORTA_WE_RISING <= (PORTA_WE = '0') and (PORTA_WE_T1 = '1'); -- falling as inverted
PORTB_WE_RISING <= (PORTB_WE = '0') and (PORTB_WE_T1 = '1'); -- "
PORTA_RE_RISING <= (PORTA_RE = '0') and (PORTA_RE_T1 = '1'); -- falling as inverted
PORTB_RE_RISING <= (PORTB_RE = '0') and (PORTB_RE_T1 = '1'); -- "
--
A_STB_L_RISING <= (A_STB_L = '1') and (A_STB_L_T1 = '0');
A_ACK_L_RISING <= (A_ACK_L = '1') and (A_ACK_L_T1 = '0');
B_STB_L_RISING <= (B_STB_L = '1') and (B_STB_L_T1 = '0');
B_ACK_L_RISING <= (B_ACK_L = '1') and (B_ACK_L_T1 = '0');
--
-- GROUP A
-- in mode 1
--
-- d4=1 (porta = input)
-- pc7,6 io (d3=1 input, d3=0 output)
-- pc5 output A_IBF
-- pc4 input A_STB_L
-- pc3 output A_INTR
--
-- d4=0 (porta = output)
-- pc7 output A_OBF_L
-- pc6 input A_ACK_L
-- pc5,4 io (d3=1 input, d3=0 output)
-- pc3 output A_INTR
--
-- GROUP B
-- in mode 1
-- d1=1 (portb = input)
-- pc2 input B_STB_L
-- pc1 output B_IBF
-- pc0 output B_INTR
--
-- d1=0 (portb = output)
-- pc2 input B_ACK_L
-- pc1 output B_OBF_L
-- pc0 output B_INTR
-- WHEN AN INPUT
--
-- stb_l a low on this input latches input data
-- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L
-- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L
-- inte A controlled by bit/set PC4
-- inte B controlled by bit/set PC2
-- WHEN AN OUTPUT
--
-- obf_l output will go low when cpu has written data
-- ack_l input - a low on this clears obf_l
-- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L
-- inte A controlled by bit/set PC6
-- inte B controlled by bit/set PC2
-- GROUP A
-- in mode 2
--
-- porta = IO
--
-- control bits 2..0 still control groupb/c lower 2..0
--
--
-- PC7 output a_obf
-- PC6 input A_ACK_L
-- PC5 output A_IBF
-- PC4 input A_STB_L
-- PC3 is still interrupt out
P_CONTROL_FLAGS : process(RESET, CLK)
variable we : boolean;
variable set1 : boolean;
variable set2 : boolean;
begin
if (RESET = '1') then
A_OBF_L <= '1';
A_INTE1 <= '0';
A_IBF <= '0';
A_INTE2 <= '0';
A_INTR <= '0';
--
B_INTE <= '0';
B_OBF_L <= '1';
B_IBF <= '0';
B_INTR <= '0';
elsif rising_edge(CLK) then
we := (CS_n = '0') and (WR_n = '0') and (ADDR = "11") and (DI(7) = '0');
if (ENA = '1') then
if (MODE_CLEAR = '1') then
A_OBF_L <= '1';
A_INTE1 <= '0';
A_IBF <= '0';
A_INTE2 <= '0';
A_INTR <= '0';
--
B_INTE <= '0';
B_OBF_L <= '1';
B_IBF <= '0';
B_INTR <= '0';
else
if (BIT_MASK(7) = '1') and we then
A_OBF_L <= DI(0);
else
if PORTA_WE_RISING then
A_OBF_L <= '0';
elsif (A_ACK_L = '0') then
A_OBF_L <= '1';
end if;
end if;
--
if (BIT_MASK(6) = '1') and we then
A_INTE1 <= DI(0);
end if; -- bus set when mode1 & input?
--
if (BIT_MASK(5) = '1') and we then
A_IBF <= DI(0);
else
if PORTA_RE_RISING then
A_IBF <= '0';
elsif (A_STB_L = '0') then
A_IBF <= '1';
end if;
end if;
--
if (BIT_MASK(4) = '1') and we then
A_INTE2 <= DI(0);
end if; -- bus set when mode1 & output?
--
set1 := A_ACK_L_RISING and (A_OBF_L = '1') and (A_INTE1 = '1');
set2 := A_STB_L_RISING and (A_IBF = '1') and (A_INTE2 = '1');
--
if (BIT_MASK(3) = '1') and we then
A_INTR <= DI(0);
else
if (GROUPA_MODE(1) = '1') then
if (PORTA_WE = '1') or (PORTA_RE = '1') then
A_INTR <= '0';
elsif set1 or set2 then
A_INTR <= '1';
end if;
else
if (R_CONTROL(4) = '0') then -- output
if (PORTA_WE = '1') then -- falling ?
A_INTR <= '0';
elsif set1 then
A_INTR <= '1';
end if;
elsif (R_CONTROL(4) = '1') then -- input
if (PORTA_RE = '1') then -- falling ?
A_INTR <= '0';
elsif set2 then
A_INTR <= '1';
end if;
end if;
end if;
end if;
--
if (BIT_MASK(2) = '1') and we then
B_INTE <= DI(0);
end if; -- bus set?
if (BIT_MASK(1) = '1') and we then
B_OBF_L <= DI(0);
else
if (R_CONTROL(1) = '0') then -- output
if PORTB_WE_RISING then
B_OBF_L <= '0';
elsif (B_ACK_L = '0') then
B_OBF_L <= '1';
end if;
else
if PORTB_RE_RISING then
B_IBF <= '0';
elsif (B_STB_L = '0') then
B_IBF <= '1';
end if;
end if;
end if;
if (BIT_MASK(0) = '1') and we then
B_INTR <= DI(0);
else
if (R_CONTROL(1) = '0') then -- output
if (PORTB_WE = '1') then -- falling ?
B_INTR <= '0';
elsif B_ACK_L_RISING and (B_OBF_L = '1') and (B_INTE = '1') then
B_INTR <= '1';
end if;
else
if (PORTB_RE = '1') then -- falling ?
B_INTR <= '0';
elsif B_STB_L_RISING and (B_IBF = '1') and (B_INTE = '1') then
B_INTR <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end process;
P_PORTA : process(R_PORTA, R_CONTROL, GROUPA_MODE, PA_I, PORTA_IPREG, A_ACK_L)
begin
-- D4 GROUPA porta 1 = input, 0 = output
PA_O <= x"FF"; -- if not driven, float high
PA_O_OE_n <= x"FF";
PORTA_READ <= x"00";
if (GROUPA_MODE = "00") then -- simple io
PA_O <= R_CONTROL; -- x"5F"; -- if not driven, float high
if (R_CONTROL(4) = '0') then -- output
PA_O <= R_PORTA;
PA_O_OE_n <= x"00";
end if;
PORTA_READ <= PA_I;
elsif (GROUPA_MODE = "01") then -- strobed
if (R_CONTROL(4) = '0') then -- output
PA_O <= R_PORTA;
PA_O_OE_n <= x"00";
end if;
PORTA_READ <= PORTA_IPREG;
else -- if (GROUPA_MODE(1) = '1') then -- bi dir
if (A_ACK_L = '0') then -- output enable
PA_O <= R_PORTA;
PA_O_OE_n <= x"00";
end if;
PORTA_READ <= PORTA_IPREG; -- latched dat
end if;
end process;
P_PORTB : process(R_PORTB, R_CONTROL, GROUPB_MODE, PB_I, PORTB_IPREG)
begin
PB_O <= x"FF"; -- if not driven, float high
PB_O_OE_n <= x"FF";
PORTB_READ <= x"00";
if (GROUPB_MODE = '0') then -- simple io
if (R_CONTROL(1) = '0') then -- output
PB_O <= R_PORTB;
PB_O_OE_n <= x"00";
end if;
PORTB_READ <= PB_I;
else -- strobed mode
if (R_CONTROL(1) = '0') then -- output
PB_O <= R_PORTB;
PB_O_OE_n <= x"00";
end if;
PORTB_READ <= PORTB_IPREG;
end if;
end process;
P_PORTC_OUT : process(R_PORTC, R_CONTROL, GROUPA_MODE, GROUPB_MODE, A_OBF_L, A_IBF, A_INTR,B_OBF_L, B_IBF, B_INTR)
begin
PC_O <= x"FF"; -- if not driven, float high
PC_O_OE_n <= x"FF";
-- bits 7..4
if (GROUPA_MODE = "00") then -- simple io
if (R_CONTROL(3) = '0') then -- output
PC_O(7 downto 4) <= R_PORTC(7 downto 4);
PC_O_OE_n(7 downto 4) <= x"0";
end if;
elsif (GROUPA_MODE = "01") then -- mode1
if (R_CONTROL(4) = '0') then -- port a output
PC_O(7) <= A_OBF_L;
PC_O_OE_n(7) <= '0';
-- 6 is ack_l input
if (R_CONTROL(3) = '0') then -- port c output
PC_O(5 downto 4) <= R_PORTC(5 downto 4);
PC_O_OE_n(5 downto 4) <= "00";
end if;
else -- port a input
if (R_CONTROL(3) = '0') then -- port c output
PC_O(7 downto 6) <= R_PORTC(7 downto 6);
PC_O_OE_n(7 downto 6) <= "00";
end if;
PC_O(5) <= A_IBF;
PC_O_OE_n(5) <= '0';
-- 4 is stb_l input
end if;
else -- if (GROUPA_MODE(1) = '1') then -- mode2
PC_O(7) <= A_OBF_L;
PC_O_OE_n(7) <= '0';
-- 6 is ack_l input
PC_O(5) <= A_IBF;
PC_O_OE_n(5) <= '0';
-- 4 is stb_l input
end if;
-- bit 3 (controlled by group a)
if (GROUPA_MODE = "00") then -- group a steals this bit
--if (GROUPB_MODE = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this
if (R_CONTROL(0) = '0') then -- ouput (note, groupb control bit)
PC_O(3) <= R_PORTC(3);
PC_O_OE_n(3) <= '0';
end if;
--
else -- stolen
PC_O(3) <= A_INTR;
PC_O_OE_n(3) <= '0';
end if;
-- bits 2..0
if (GROUPB_MODE = '0') then -- simple io
if (R_CONTROL(0) = '0') then -- output
PC_O(2 downto 0) <= R_PORTC(2 downto 0);
PC_O_OE_n(2 downto 0) <= "000";
end if;
else
-- mode 1
-- 2 is input
if (R_CONTROL(1) = '0') then -- output
PC_O(1) <= B_OBF_L;
PC_O_OE_n(1) <= '0';
else -- input
PC_O(1) <= B_IBF;
PC_O_OE_n(1) <= '0';
end if;
PC_O(0) <= B_INTR;
PC_O_OE_n(0) <= '0';
end if;
end process;
P_PORTC_IN : process(R_PORTC, PC_I, R_CONTROL, GROUPA_MODE, GROUPB_MODE, A_IBF, B_OBF_L, A_OBF_L, A_INTE1, A_INTE2, A_INTR, B_INTE, B_IBF, B_INTR)
begin
PORTC_READ <= x"00";
A_STB_L <= '1';
A_ACK_L <= '1';
B_STB_L <= '1';
B_ACK_L <= '1';
if (GROUPA_MODE = "01") then -- mode1 or 2
if (R_CONTROL(4) = '0') then -- port a output
A_ACK_L <= PC_I(6);
else -- port a input
A_STB_L <= PC_I(4);
end if;
elsif (GROUPA_MODE(1) = '1') then -- mode 2
A_ACK_L <= PC_I(6);
A_STB_L <= PC_I(4);
end if;
if (GROUPB_MODE = '1') then
if (R_CONTROL(1) = '0') then -- output
B_ACK_L <= PC_I(2);
else -- input
B_STB_L <= PC_I(2);
end if;
end if;
if (GROUPA_MODE = "00") then -- simple io
PORTC_READ(7 downto 3) <= PC_I(7 downto 3);
elsif (GROUPA_MODE = "01") then
if (R_CONTROL(4) = '0') then -- port a output
PORTC_READ(7 downto 3) <= A_OBF_L & A_INTE1 & PC_I(5 downto 4) & A_INTR;
else -- input
PORTC_READ(7 downto 3) <= PC_I(7 downto 6) & A_IBF & A_INTE2 & A_INTR;
end if;
else -- mode 2
PORTC_READ(7 downto 3) <= A_OBF_L & A_INTE1 & A_IBF & A_INTE2 & A_INTR;
end if;
if (GROUPB_MODE = '0') then -- simple io
PORTC_READ(2 downto 0) <= PC_I(2 downto 0);
else
if (R_CONTROL(1) = '0') then -- output
PORTC_READ(2 downto 0) <= B_INTE & B_OBF_L & B_INTR;
else -- input
PORTC_READ(2 downto 0) <= B_INTE & B_IBF & B_INTR;
end if;
end if;
end process;
P_IPREG : process(RESET, CLK)
begin
if RESET = '1' then
PORTA_IPREG <= (others => '0');
PORTB_IPREG <= (others => '0');
PORTB_IPREG <= (others => '0');
elsif CLK'event and CLK = '1' then
-- pc4 input A_STB_L
-- pc2 input B_STB_L
if (ENA = '1') then
if (A_STB_L = '0') then
PORTA_IPREG <= PA_I;
end if;
if (MODE_CLEAR = '1') then
PORTB_IPREG <= (others => '0');
elsif (B_STB_L = '0') then
PORTB_IPREG <= PB_I;
end if;
end if;
end if;
end process;
end architecture RTL;

319
common/keymatrix.vhd Normal file
View File

@@ -0,0 +1,319 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: keymatrix.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: Keyboard module to convert PS2 key codes into Sharp scan matrix key connections.
-- For each scan output (10 lines) sent by the Sharp, an 8bit response is read in
-- and the bits set indicate keys pressed. This allows for multiple keys to be pressed
-- at the same time. The PS2 scan code is mapped via a rom and the output is used to drive
-- the data in lines of the 8255.
--
-- Credits: Nibbles Lab (c) 2005-2012
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written, originally based on the Nibbles Lab code but
-- rewritten to match the overall design of this emulation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity keymatrix is
Port (
RST_n : in std_logic;
-- i8255
PA : in std_logic_vector(3 downto 0);
PB : out std_logic_vector(7 downto 0);
STALL : in std_logic;
BREAKDETECT : out std_logic;
-- PS/2 Keyboard Data
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- Clock signals used by this module.
CLKBUS : in std_logic_vector(CLKBUS_WIDTH);
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0) -- HPS Data to be read into HPS.
);
end keymatrix;
architecture Behavioral of keymatrix is
--
-- prefix flag
--
signal FLGF0 : std_logic;
signal FLGE0 : std_logic;
--
-- MZ-series matrix registers
--
signal SCAN00 : std_logic_vector(7 downto 0);
signal SCAN01 : std_logic_vector(7 downto 0);
signal SCAN02 : std_logic_vector(7 downto 0);
signal SCAN03 : std_logic_vector(7 downto 0);
signal SCAN04 : std_logic_vector(7 downto 0);
signal SCAN05 : std_logic_vector(7 downto 0);
signal SCAN06 : std_logic_vector(7 downto 0);
signal SCAN07 : std_logic_vector(7 downto 0);
signal SCAN08 : std_logic_vector(7 downto 0);
signal SCAN09 : std_logic_vector(7 downto 0);
signal SCAN10 : std_logic_vector(7 downto 0);
signal SCAN11 : std_logic_vector(7 downto 0);
signal SCAN12 : std_logic_vector(7 downto 0);
signal SCAN13 : std_logic_vector(7 downto 0);
signal SCAN14 : std_logic_vector(7 downto 0);
signal SCANLL : std_logic_vector(7 downto 0);
--
-- Key code exchange table
--
signal MTEN : std_logic_vector(3 downto 0);
signal F_KBDT : std_logic_vector(7 downto 0);
signal MAP_DATA : std_logic_vector(7 downto 0);
signal KEY_BANK : std_logic_vector(2 downto 0);
--
-- HPS access
--
signal IOCTL_KEYMAP_WEN : std_logic;
signal IOCTL_DIN_KEYMAP : std_logic_vector(7 downto 0); -- HPS Data to be read into HPS.
signal KEY_EXTENDED : std_logic;
signal KEY_FLAG : std_logic;
signal KEY_PRESS : std_logic;
signal KEY_VALID : std_logic;
--
-- Components
--
component dprom
GENERIC (
init_file : string;
widthad_a : natural;
width_a : natural
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
-- data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-- wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
-- 0 = MZ80K KEYMAP = 256Bytes -> 0000:00ff 0000 bytes padding
-- 1 = MZ80C KEYMAP = 256Bytes -> 0100:01ff 0000 bytes padding
-- 2 = MZ1200 KEYMAP = 256Bytes -> 0200:02ff 0000 bytes padding
-- 3 = MZ80A KEYMAP = 256Bytes -> 0300:03ff 0000 bytes padding
-- 4 = MZ700 KEYMAP = 256Bytes -> 0400:04ff 0000 bytes padding
-- 5 = MZ80B KEYMAP = 256Bytes -> 0500:05ff 0000 bytes padding
MAP0 : dprom
GENERIC MAP (
--init_file => "./software/mif/key_80k_80b.mif",
init_file => "./software/mif/combined_keymap.mif",
widthad_a => 11,
width_a => 8
)
PORT MAP (
clock_a => CLKBUS(CKMASTER),
address_a => KEY_BANK & F_KBDT,
-- data_a => IOCTL_DOUT(7 DOWNTO 0),
-- wren_a =>
q_a => MAP_DATA,
clock_b => IOCTL_CLK,
address_b => IOCTL_ADDR(10 DOWNTO 0),
data_b => IOCTL_DOUT(7 DOWNTO 0),
wren_b => IOCTL_KEYMAP_WEN,
q_b => IOCTL_DIN_KEYMAP
);
-- Store changes to the key valid flag in a flip flop.
process( CLKBUS(CKMASTER) ) begin
if rising_edge(CLKBUS(CKMASTER)) then
if CLKBUS(CKENCPU) = '1' then
KEY_FLAG <= PS2_KEY(10);
end if;
end if;
end process;
-- Set the key mapping to use according to selected machine.
--
process( RST_n, CLKBUS(CKMASTER) ) begin
if RST_n = '0' then
KEY_BANK <= "000";
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
if CLKBUS(CKENCPU) = '1' then
if CONFIG(MZ80K) = '1' then -- Key map for MZ80K
KEY_BANK <= "000";
elsif CONFIG(MZ80C) = '1' then -- Key map for MZ80C
KEY_BANK <= "001";
elsif CONFIG(MZ1200) = '1' then -- Key map for MZ1200
KEY_BANK <= "010";
elsif CONFIG(MZ80A) = '1' then -- Key map for MZ80A
KEY_BANK <= "011";
elsif CONFIG(MZ700) = '1' then -- Key map for MZ700
KEY_BANK <= "100";
elsif CONFIG(MZ800) = '1' then -- Key map for MZ800
KEY_BANK <= "101";
elsif CONFIG(MZ80B) = '1' then -- Key map for MZ80B
KEY_BANK <= "110";
elsif CONFIG(MZ2000) = '1' then -- Key map for MZ2000
KEY_BANK <= "111";
end if;
end if;
end if;
end process;
--
-- Convert
--
process( RST_n, CLKBUS(CKMASTER) ) begin
if RST_n = '0' then
SCAN00 <= (others=>'0');
SCAN01 <= (others=>'0');
SCAN02 <= (others=>'0');
SCAN03 <= (others=>'0');
SCAN04 <= (others=>'0');
SCAN05 <= (others=>'0');
SCAN06 <= (others=>'0');
SCAN07 <= (others=>'0');
SCAN08 <= (others=>'0');
SCAN09 <= (others=>'0');
SCAN10 <= (others=>'0');
SCAN11 <= (others=>'0');
SCAN12 <= (others=>'0');
SCAN13 <= (others=>'0');
SCAN14 <= (others=>'0');
FLGF0 <= '0';
FLGE0 <= '0';
MTEN <= (others=>'0');
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
if CLKBUS(CKENCPU) = '1' then
MTEN <= MTEN(2 downto 0) & KEY_VALID;
if KEY_VALID='1' then
if(KEY_EXTENDED='1') then
FLGE0 <= '1';
end if;
if(KEY_PRESS='0') then
FLGF0 <= '1';
end if;
if(PS2_KEY(7 downto 0) = X"AA" ) then
F_KBDT <= X"EF";
else
F_KBDT <= FLGE0 & PS2_KEY(6 downto 0); FLGE0<='0';
end if;
end if;
if MTEN(3)='1' then
case MAP_DATA(7 downto 4) is
when "0000" => SCAN00(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0001" => SCAN01(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0010" => SCAN02(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0011" => SCAN03(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0100" => SCAN04(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0101" => SCAN05(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0110" => SCAN06(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0111" => SCAN07(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1000" => SCAN08(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1001" => SCAN09(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1010" => SCAN10(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1011" => SCAN11(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1100" => SCAN12(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1101" => SCAN13(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1110" => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0;
when others => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
end case;
end if;
end if;
end if;
end process;
PA_L : for I in 0 to 7 generate
SCANLL(I) <= SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I) or
SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I) or
SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I);
end generate PA_L;
--
-- response from key access
--
PB <= (not SCANLL) when STALL='0' and CONFIG(MZ_B)='1' else
(not SCAN00) when PA="0000" else
(not SCAN01) when PA="0001" else
(not SCAN02) when PA="0010" else
(not SCAN03) when PA="0011" else
(not SCAN04) when PA="0100" else
(not SCAN05) when PA="0101" else
(not SCAN06) when PA="0110" else
(not SCAN07) when PA="0111" else
(not SCAN08) when PA="1000" else
(not SCAN09) when PA="1001" else
(not SCAN10) when PA="1010" else
(not SCAN11) when PA="1011" else
(not SCAN12) when PA="1100" else
(not SCAN13) when PA="1101" else (others=>'1');
-- Setup key extension signals to use in mapping.
--
KEY_PRESS <= PS2_KEY(9);
KEY_EXTENDED <= PS2_KEY(8);
KEY_VALID <= '1' when KEY_FLAG /= PS2_KEY(10)
else '0';
-- Break detect is connected to SCAN line 3, bit 7. When the strobe is set to 03H and the break key is pressed
-- this signal will go low and detected in the IPL.
BREAKDETECT <= not SCAN03(7);
--
-- HPS access to reload keymap.
--
IOCTL_KEYMAP_WEN <= '1' when IOCTL_ADDR(24 downto 16) = "000100011" and IOCTL_WR = '1'
else '0';
IOCTL_DIN <= X"000000" & IOCTL_DIN_KEYMAP when IOCTL_ADDR(24 downto 16) = "000100011" and IOCTL_RD = '1'
else
(others=>'0');
end Behavioral;

707
common/mctrl.vhd Normal file
View File

@@ -0,0 +1,707 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: mctrl.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Programmable Machine Control logic.
-- This module forms the Programmable control of the emulation along with sync reset
-- management.
-- A set of 16 addressable registers is presented on the external IOCTL interface.
-- Each register controls an aspect of the emulation, such as video mode or cpu speed.
--
-- Reset to all components is managed by this module, taking cold, warm and internally
-- generated reset signals and creating a unified system reset output.
--
-- Please see the docs/SharpMZ_Notes.xlsx spreadsheet for details on these registers
-- and the values they take.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
package mctrl_pkg is
-- Config Bus
--
subtype CONFIG_WIDTH is integer range 70 downto 0;
-- Mode signals indicating type of machine we are emulating.
--
constant MZ80K : integer := 0; -- Machine is an MZ80K
constant MZ80C : integer := 1; -- Machine is an MZ80C
constant MZ1200 : integer := 2; -- Machine is an MZ1200
constant MZ80A : integer := 3; -- Machine is an MZ80A
constant MZ700 : integer := 4; -- Machine is an MZ700
constant MZ800 : integer := 5; -- Machine is an MZ800
constant MZ80B : integer := 6; -- Machine is an MZ80B
constant MZ2000 : integer := 7; -- Machine is an MZ2000
subtype CURRENTMACHINE is integer range 7 downto 0; -- Range of bits to indicate current machine, only 1 bit is set at a time.
constant MZ_KC : integer := 8; -- Machine is an MZ80K/MZ80C Series
constant MZ_A : integer := 9; -- Machine is an MZ1200/MZ80A Series
constant MZ_B : integer := 10; -- Machine is an MZ2000/MZ80B Series
constant MZ_80B : integer := 11; -- Machine is an MZ2000/MZ80B Series
constant MZ_80C : integer := 12; -- Machine is an MZ80K/MZ80C/MZ1200/MZ80A Series
-- Type of display to emulate.
--
constant NORMAL : integer := 13; -- Normal 40 x 25 character monochrome display.
constant NORMAL80 : integer := 14; -- Normal 80 x 25 character monochrome display.
constant COLOUR : integer := 15; -- Colour 40 x 25 character display.
constant COLOUR80 : integer := 16; -- Colour 80 x 25 character display.
subtype VGAMODE is integer range 18 downto 17; -- Output display to 640x400 or 640x480, double up pixels as required.
-- Option Roms Enable (some machines by design dont have them, but this emulation allows them to be enabled if needed).
--
subtype USERROM is integer range 26 downto 19; -- User ROM E800 - EFFF enable per machine.
subtype FDCROM is integer range 34 downto 27; -- FDC ROM F000 - FFFF enable per machine.
subtype GRAMIOADDR is integer range 39 downto 35;
-- Various configurable settings.
--
constant AUDIOSRC : integer := 40; -- Audio source, 0 = sound generator, 1 = tape audio.
subtype TURBO is integer range 43 downto 41; -- 2MHz/4MHz/8MHz/16MHz/32MHz switch (various).
subtype FASTTAPE is integer range 46 downto 44; -- Speed of tape read/write.
subtype BUTTONS is integer range 48 downto 47; -- Various external buttons, such as CMT play/record.
constant PCGRAM : integer := 49; -- PCG ROM(0) or RAM(1) based.
constant VRAMWAIT : integer := 50; -- Insert video wait states on CPU access as per original design.
constant VRAMDISABLE : integer := 51; -- Disable the Video RAM from display output.
constant GRAMDISABLE : integer := 52; -- Disable the graphics RAM from display output.
constant MENUENABLE : integer := 53; -- Enable the OSD menu on display output.
constant STATUSENABLE : integer := 54; -- Enable the OSD menu on display output.
constant BOOT_RESET : integer := 55; -- MZ80B/2000 Boot IPL Reset Enable.
constant CMTASCII_IN : integer := 56; -- Enable CMT conversion of Sharp Ascii <-> Ascii on receipt of data from Sharp.
constant CMTASCII_OUT : integer := 57; -- Enable CMT conversion of Sharp Ascii <-> Ascii on sending data to Sharp.
-- Derivative settings to program the clock generator.
--
subtype CPUSPEED is integer range 61 downto 58; -- Active CPU Speed.
subtype VIDSPEED is integer range 64 downto 62; -- Active Video Speed.
subtype PERSPEED is integer range 66 downto 65; -- Active Peripheral Speed.
subtype RTCSPEED is integer range 68 downto 67; -- Active RTC Speed.
subtype SNDSPEED is integer range 70 downto 69; -- Active Sound Speed.
-- CMT Bus
--
subtype CMT_BUS_OUT_WIDTH is integer range 13 downto 0;
subtype CMT_BUS_IN_WIDTH is integer range 7 downto 0;
-- CMT exported Signals.
--
constant PLAY_READY : integer := 0; -- Tape play back buffer, 0 = empty, 1 = full.
constant PLAYING : integer := 1; -- Tape playback, 0 = stopped, 1 = in progress.
constant RECORD_READY : integer := 2; -- Tape record buffer full, 0 = empty, 1 = full.
constant RECORDING : integer := 3; -- Tape recording, 0 = stopped, 1 = in progress.
constant ACTIVE : integer := 4; -- Tape transfer in progress, 0 = no activity, 1 = activity.
constant SENSE : integer := 5; -- Tape state Sense out.
constant WRITEBIT : integer := 6; -- Write bit to MZ.
constant TAPEREADY : integer := 7; -- Tape is loaded in deck when L = 0.
constant WRITEREADY : integer := 8; -- Write is prohibited when L = 0.
constant APSS_SEEK : integer := 9; -- Start to seek the next program according to APSS_DIR
constant APSS_DIR : integer := 10; -- Direction for APSS Seek, 0 = Rewind, 1 = Forward.
constant APSS_EJECT : integer := 11; -- Eject cassette.
constant APSS_PLAY : integer := 12; -- Play cassette.
constant APSS_STOP : integer := 13; -- Stop playing/rwd/ff of cassette.
-- CMT imported Signals.
--
constant READBIT : integer := 0; -- Receive bit from MZ.
constant REEL_MOTOR : integer := 1; -- APSS Reel Motor on/off.
constant STOP : integer := 2; -- Stop the motor.
constant PLAY : integer := 3; -- Play cassette.
constant SEEK : integer := 4; -- Seek cassette using DIRECTION (L = Rewind, H = FF).
constant DIRECTION : integer := 5; -- Seek direction, L = Rewind, H = Fast Forward.
constant EJECT : integer := 6; -- Eject the cassette.
constant WRITEENABLE : integer := 7; -- Enable writing to cassette.
-- Debug Bus
--
subtype DEBUG_WIDTH is integer range 15 downto 0;
-- Debugging signals.
--
subtype LEDS_BANK is integer range 2 downto 0;
subtype LEDS_SUBBANK is integer range 5 downto 3;
constant LEDS_ON : integer := 6;
constant ENABLED : integer := 7;
subtype SMPFREQ is integer range 11 downto 8;
subtype CPUFREQ is integer range 15 downto 12;
end mctrl_pkg;
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use pkgs.config_pkg.all;
use pkgs.mctrl_pkg.all;
use pkgs.clkgen_pkg.all;
entity mctrl is
Port (
-- Clock signals used by this module.
CLKBUS : in std_logic_vector(CLKBUS_WIDTH);
-- Reset's
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
SYSTEM_RESET : out std_logic;
-- HPS Interface
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0); -- HPS Data to be read into HPS.
-- Different operations modes.
CONFIG : out std_logic_vector(CONFIG_WIDTH);
-- Cassette magnetic tape signals.
CMT_BUS_OUT : in std_logic_vector(CMT_BUS_OUT_WIDTH);
CMT_BUS_IN : in std_logic_vector(CMT_BUS_IN_WIDTH);
-- MZ80B series can dynamically change the video frequency to attain 40/80 character display.
CONFIG_CHAR80 : in std_logic;
-- Debug modes.
DEBUG : out std_logic_vector(DEBUG_WIDTH)
);
end mctrl;
architecture rtl of mctrl is
signal REGISTER_MODEL : std_logic_vector(7 downto 0) := "00000011";
signal REGISTER_DISPLAY : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_DISPLAY2 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_DISPLAY3 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CPU : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_AUDIO : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CMT : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CMT2 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_USERROM : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_FDCROM : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_10 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_11 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_12 : std_logic_vector(7 downto 0) := "00000000";
-- REGISTER_13 is a read only configuration, so no register required.
signal REGISTER_DEBUG : std_logic_vector(7 downto 0) := "00001000";
signal REGISTER_DEBUG2 : std_logic_vector(7 downto 0) := "00000000";
signal delay : integer range 0 to 63;
signal READ_STATUS : std_logic_vector(15 downto 0);
signal RESET_MACHINE : std_logic;
signal CMT_BUS_OUT_LAST : std_logic_vector(CMT_BUS_OUT_WIDTH);
begin
-- Synchronise the register update with the configuration signals according to the CPU clock.
--
process (COLD_RESET, CLKBUS(CKMASTER))
begin
if COLD_RESET = '1' then
CONFIG(CONFIG_WIDTH) <= "00000000000000000000000000000000011000000000000000000000011001000001000";
DEBUG(DEBUG_WIDTH) <= "0000000000000000";
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
if CLKBUS(CKENCPU) = '1' then
if REGISTER_MODEL(2 downto 0) = "000" then
CONFIG(MZ80K) <= '1';
else
CONFIG(MZ80K) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ80C) <= '1';
else
CONFIG(MZ80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" then
CONFIG(MZ1200) <= '1';
else
CONFIG(MZ1200) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ80A) <= '1';
else
CONFIG(MZ80A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(MZ700) <= '1';
else
CONFIG(MZ700) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "101" then
CONFIG(MZ800) <= '1';
else
CONFIG(MZ800) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(MZ80B) <= '1';
else
CONFIG(MZ80B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ2000) <= '1';
else
CONFIG(MZ2000) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "000" or REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ_KC) <= '1';
else
CONFIG(MZ_KC) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" or REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ_A) <= '1';
else
CONFIG(MZ_A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_B) <= '1';
else
CONFIG(MZ_B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(MZ_80C) <= '1';
else
CONFIG(MZ_80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_80B) <= '1';
else
CONFIG(MZ_80B) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "000" then
CONFIG(NORMAL) <= '1';
else
CONFIG(NORMAL) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "001" then
CONFIG(NORMAL80) <= '1';
else
CONFIG(NORMAL80) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "010" then
CONFIG(COLOUR) <= '1';
else
CONFIG(COLOUR) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "011" then
CONFIG(COLOUR80) <= '1';
else
CONFIG(COLOUR80) <= '0';
end if;
-- Convert CPU/CMT and Debug speed selections to actual CPU speed.
-- If debugging enabled and Debug freq not 0, select otherwise CMT if CMT is active, otherwise CPU speed as required.
--
-- Mapping could be made in software or 1-1 with the register, but setting restrictions and mapping in hw preferred, it
-- limits frequencies belonging to a given machine and makes it easier to change the frequency by NIOS or other controller if
-- MiSTer not used.
if CMT_BUS_OUT(ACTIVE) = '1' then
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
end if;
else
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
end if;
end if;
-- Setup the video speed dependent upon model and graphics option. VGA OUT currently
-- forces all pixel clocks to 25.175MHz, otherwise the original pixel clock is chosen.
--
case REGISTER_MODEL(2 downto 0) is
-- MZ80K/C/1200/A
when "000" | "001" | "010" | "011" =>
case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8MHz clock, Mono and Colour.
when "11000" | "11010" | "11100" | "11101" | "11110" | "11111" =>
CONFIG(VIDSPEED) <= "000";
-- 80x25 mode requires 16MHz clock, Mono and Colour.
when "11001" | "11011" =>
CONFIG(VIDSPEED) <= "001";
-- VGA Timing 640x480 @ 60Hz
when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
CONFIG(VIDSPEED) <= "100";
-- VGA Timing 640x480 @ 75Hz
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
CONFIG(VIDSPEED) <= "110";
-- VGA Timing 640x480 @ 85Hz
when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
CONFIG(VIDSPEED) <= "111";
end case;
-- MZ700/MZ800 Models.
when "100" | "101" =>
-- Currently all modes default to one speed!
case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8.8MHz clock, Mono and Colour.
when "11000" | "11010" | "11100" | "11101" | "11110" | "11111" =>
CONFIG(VIDSPEED) <= "010";
-- 80x25 mode requires 17.7MHz clock, Mono and Colour.
when "11001" | "11011" =>
CONFIG(VIDSPEED) <= "011";
-- VGA Timing 640x480 @ 60Hz
when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
CONFIG(VIDSPEED) <= "100";
-- VGA Timing 640x480 @ 75Hz
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
CONFIG(VIDSPEED) <= "110";
-- VGA Timing 640x480 @ 85Hz
when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
CONFIG(VIDSPEED) <= "111";
end case;
-- MZ80B or MZ2200
when "110" | "111" =>
case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
-- 80x25 mode requires 16MHz clock, 40x25 requires 8MHz, switched on the CHAR80 signal.
when "11000" | "11001" | "11010" | "11011" | "11100" | "11101" | "11110" | "11111" =>
if CONFIG_CHAR80 = '1' then
CONFIG(VIDSPEED) <= "001";
else
CONFIG(VIDSPEED) <= "000";
end if;
-- VGA Timing 640x480 @ 60Hz
when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
CONFIG(VIDSPEED) <= "100";
-- VGA Timing 640x480 @ 75Hz
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
CONFIG(VIDSPEED) <= "110";
-- VGA Timing 640x480 @ 85Hz
when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
CONFIG(VIDSPEED) <= "111";
end case;
end case;
-- Setup RTC clock frequency dependent upon model.
if REGISTER_MODEL(2 downto 0) = "110" and REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(RTCSPEED) <= "01";
elsif REGISTER_MODEL(2 downto 0) = "100" or REGISTER_MODEL(2 downto 0) = "101" then
CONFIG(RTCSPEED) <= "10";
else
CONFIG(RTCSPEED) <= "00";
end if;
if REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(SNDSPEED) <= "01";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(SNDSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(SNDSPEED) <= "00";
else
CONFIG(SNDSPEED) <= "00";
end if;
-- Setup the peripheral speed.
if REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(PERSPEED) <= "00";
else
CONFIG(PERSPEED) <= "00";
end if;
CONFIG(GRAMIOADDR) <= REGISTER_DISPLAY2(7 downto 3);
CONFIG(VRAMDISABLE) <= REGISTER_DISPLAY(4);
CONFIG(GRAMDISABLE) <= REGISTER_DISPLAY(5);
CONFIG(VRAMWAIT) <= REGISTER_DISPLAY(6);
CONFIG(PCGRAM) <= REGISTER_DISPLAY(7);
CONFIG(VGAMODE) <= REGISTER_DISPLAY2(1 downto 0);
CONFIG(MENUENABLE) <= REGISTER_DISPLAY3(0);
CONFIG(STATUSENABLE) <= REGISTER_DISPLAY3(1);
CONFIG(TURBO) <= REGISTER_CPU(2 downto 0);
CONFIG(FASTTAPE) <= REGISTER_CMT(2 downto 0);
CONFIG(BUTTONS) <= REGISTER_CMT(4 downto 3);
CONFIG(CMTASCII_IN) <= REGISTER_CMT(5);
CONFIG(CMTASCII_OUT) <= REGISTER_CMT(6);
CONFIG(AUDIOSRC) <= REGISTER_AUDIO(0);
CONFIG(USERROM) <= REGISTER_USERROM;
CONFIG(FDCROM) <= REGISTER_FDCROM;
CONFIG(BOOT_RESET) <= REGISTER_CPU(7);
DEBUG(LEDS_BANK) <= REGISTER_DEBUG(2 downto 0);
DEBUG(LEDS_SUBBANK) <= REGISTER_DEBUG(5 downto 3);
DEBUG(LEDS_ON) <= REGISTER_DEBUG(6);
DEBUG(ENABLED) <= REGISTER_DEBUG(7);
DEBUG(SMPFREQ) <= REGISTER_DEBUG2(3 downto 0);
DEBUG(CPUFREQ) <= REGISTER_DEBUG2(7 downto 4);
end if;
end if;
end process;
-- Machine control is just a set of registers holding latched signals to configure machine components.
-- A write is made on address 100000000000000000000AAAA to read/write the registers, direction is via the
-- RD/WR signals.
-- AAAA specifies which register to read/write.
--
process (COLD_RESET, IOCTL_CLK)
begin
if COLD_RESET = '1' then
REGISTER_MODEL <= "00000011";
REGISTER_DISPLAY <= "00000000";
REGISTER_DISPLAY2<= "00000000";
REGISTER_DISPLAY3<= "00000000";
REGISTER_CPU <= "00000000";
REGISTER_AUDIO <= "00000000";
REGISTER_CMT <= "00000000";
REGISTER_CMT2 <= "00000000";
REGISTER_USERROM <= "00000000";
REGISTER_FDCROM <= "00000000";
REGISTER_10 <= "00000000";
REGISTER_11 <= "00000000";
REGISTER_12 <= "00000000";
REGISTER_DEBUG <= "00000000";
REGISTER_DEBUG2 <= "00000000";
READ_STATUS <= (others => '0');
RESET_MACHINE <= '1';
CMT_BUS_OUT_LAST <= (others => '0');
elsif IOCTL_CLK'event and IOCTL_CLK='1' then
-- Reset a register if it has been read, ready for next status change.
--
if READ_STATUS(6) = '1' then
REGISTER_CMT2 <= (others => '0');
end if;
-- CMT Register 2, for bits 0,2,3 & 4, they set an active bit, then upon read it is reset.
--
if CMT_BUS_OUT(APSS_STOP) /= CMT_BUS_OUT_LAST(APSS_STOP) and CMT_BUS_OUT(APSS_STOP) = '1' then
REGISTER_CMT2(4) <= CMT_BUS_OUT(APSS_STOP);
end if;
--if CMT_BUS_OUT(APSS_PLAY) /= CMT_BUS_OUT_LAST(APSS_PLAY) and CMT_BUS_OUT(APSS_PLAY) = '1' then
REGISTER_CMT2(3) <= CMT_BUS_OUT(APSS_PLAY);
--end if;
if CMT_BUS_OUT(APSS_EJECT) /= CMT_BUS_OUT_LAST(APSS_EJECT) and CMT_BUS_OUT(APSS_EJECT) = '1' then
REGISTER_CMT2(2) <= '1';
end if;
REGISTER_CMT2(1) <= CMT_BUS_OUT(APSS_DIR);
if CMT_BUS_OUT(APSS_SEEK) /= CMT_BUS_OUT_LAST(APSS_SEEK) and CMT_BUS_OUT(APSS_SEEK) = '1' then
REGISTER_CMT2(0) <= '1';
end if;
CMT_BUS_OUT_LAST <= CMT_BUS_OUT;
READ_STATUS <= (others => '0');
-- For reading of registers, if no specific signal is required, just read back the output latch.
--
if IOCTL_ADDR(24) = '1' and IOCTL_RD = '1' then
case IOCTL_ADDR(3 downto 0) is
when "0000" => IOCTL_DIN <= X"000000" & REGISTER_MODEL; READ_STATUS(0) <= '1';
when "0001" => IOCTL_DIN <= X"000000" & REGISTER_DISPLAY; READ_STATUS(1) <= '1';
when "0010" => IOCTL_DIN <= X"000000" & REGISTER_DISPLAY2; READ_STATUS(2) <= '1';
when "0011" => IOCTL_DIN <= X"000000" & REGISTER_DISPLAY3; READ_STATUS(3) <= '1';
when "0100" => IOCTL_DIN <= X"000000" & REGISTER_CPU; READ_STATUS(4) <= '1';
when "0101" => IOCTL_DIN <= X"000000" & REGISTER_AUDIO; READ_STATUS(5) <= '1';
when "0110" => IOCTL_DIN <= X"000000" & CMT_BUS_OUT(7 downto 0); READ_STATUS(6) <= '1';
when "0111" => IOCTL_DIN <= X"000000" & REGISTER_CMT2; READ_STATUS(7) <= '1';
when "1000" => IOCTL_DIN <= X"000000" & REGISTER_USERROM; READ_STATUS(8) <= '1';
when "1001" => IOCTL_DIN <= X"000000" & REGISTER_FDCROM; READ_STATUS(9) <= '1';
when "1010" => IOCTL_DIN <= X"000000" & REGISTER_10; READ_STATUS(10) <= '1';
when "1011" => IOCTL_DIN <= X"000000" & REGISTER_11; READ_STATUS(11) <= '1';
when "1100" => IOCTL_DIN <= X"000000" & REGISTER_12; READ_STATUS(12) <= '1';
when "1101" => IOCTL_DIN <= X"000000" & "000000" & std_logic_vector(to_unsigned(NEO_ENABLE, 1)) & std_logic_vector(to_unsigned(DEBUG_ENABLE, 1));
when "1110" => IOCTL_DIN <= X"000000" & REGISTER_DEBUG; READ_STATUS(14) <= '1';
when "1111" => IOCTL_DIN <= X"000000" & REGISTER_DEBUG2; READ_STATUS(15) <= '1';
end case;
end if;
-- For writing of registers, just assign the input bus to the register.
if IOCTL_ADDR(24) = '1' and IOCTL_WR = '1' then
case IOCTL_ADDR(3 downto 0) is
when "0000" =>
-- Assign the model data to the register and preset the default display hardware.
REGISTER_MODEL <= IOCTL_DOUT(7 downto 0);
case IOCTL_DOUT(2 downto 0) is
when "000" | "001" | "010" | "011" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "000";
when "100" | "101" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "010";
when "110" | "111" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "001";
end case;
RESET_MACHINE <= '1';
when "0001" =>
REGISTER_DISPLAY <= IOCTL_DOUT(7 downto 0);
-- Reset display if the mode changes.
if REGISTER_DISPLAY(2 downto 0) /= IOCTL_DOUT(2 downto 0) then
RESET_MACHINE <= '1';
end if;
when "0010" =>
-- Check the sanity, certain address ranges are blocked by the underlying machine.
--
if IOCTL_DOUT(7 downto 4) /= "1111" and IOCTL_DOUT(7 downto 4) /= "1110" and IOCTL_DOUT(7 downto 4) /= "1101" then
REGISTER_DISPLAY2 <= IOCTL_DOUT(7 downto 0);
end if;
when "0011" => REGISTER_DISPLAY3<= IOCTL_DOUT(7 downto 0);
when "0100" => REGISTER_CPU <= IOCTL_DOUT(7 downto 0);
if REGISTER_CPU(7) = '1' then
RESET_MACHINE<= '1';
end if;
when "0101" => REGISTER_AUDIO <= IOCTL_DOUT(7 downto 0);
when "0110" => REGISTER_CMT <= IOCTL_DOUT(7 downto 0);
when "0111" => REGISTER_CMT2 <= IOCTL_DOUT(7 downto 0);
when "1000" => REGISTER_USERROM <= IOCTL_DOUT(7 downto 0);
when "1001" => REGISTER_FDCROM <= IOCTL_DOUT(7 downto 0);
when "1010" => REGISTER_10 <= IOCTL_DOUT(7 downto 0);
when "1011" => REGISTER_11 <= IOCTL_DOUT(7 downto 0);
when "1100" => REGISTER_12 <= IOCTL_DOUT(7 downto 0);
when "1101" => -- Setup register showing configuration, cannot be changed.
when "1110" => REGISTER_DEBUG <= IOCTL_DOUT(7 downto 0);
when "1111" => REGISTER_DEBUG2 <= IOCTL_DOUT(7 downto 0);
end case;
end if;
-- Only allow reset signal to be active for 1 clock cycle, just enough to trigger a system reset.
--
if RESET_MACHINE = '1' then
RESET_MACHINE <= '0';
end if;
end if;
end process;
-- System reset oneshot, triggered on COLD/WARM reset or a status change.
process (CLKBUS(CKMASTER), COLD_RESET, WARM_RESET, RESET_MACHINE)
begin
if COLD_RESET = '1' or WARM_RESET = '1' or RESET_MACHINE = '1' then
if COLD_RESET = '1' then
delay <= 15;
elsif WARM_RESET = '1' then
delay <= 31;
else
delay <= 31;
end if;
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
if delay /= 0 then
delay <= delay + 1;
elsif delay >= 63 then
delay <= 0;
end if;
end if;
end process;
SYSTEM_RESET <= '1' when delay > 0
else '0';
end rtl;

987
common/pll.qip Normal file
View File

@@ -0,0 +1,987 @@
set_global_assignment -entity "clkgen" -library "pll" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "clkgen" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "clkgen" -library "pll" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "pll" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../pll.sopcinfo"]
set_global_assignment -entity "clkgen" -library "pll" -name SLD_INFO "QSYS_NAME pll HAS_SOPCINFO 1 GENERATION_ID 1544470692"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../pll.cmp"]
set_global_assignment -library "pll" -name SLD_FILE [file join $::quartus(qip_path) "pll.debuginfo"]
set_global_assignment -entity "clkgen" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "clkgen" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "clkgen" -library "pll" -name IP_QSYS_MODE "SYSTEM"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../../pll.qsys"]
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_NAME "cGxs"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "cGxs"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU0NDQ3MDY5Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8y"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MzEuMQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTAy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MzYuMDAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjUuMTc1::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTI2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MzEuNTAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTcuNzM0NDc1::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTc4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MjUuNTY4NjI3IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzU4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MzEuMDk5OTk4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjUuMTc2MTg4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTcuODIxMzQ2IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::OC44NjA4OTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Niw2LDEsMSxmYWxzZSxmYWxzZSxmYWxzZSxmYWxzZSwyNiwyNSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMyLDMxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsNDUsNDQsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw5MCw4OSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDEsMzAsMjAwMCwxNTg2LjA5OTgwMSBNSHosMTY4MTA3MDM2NixnY2xrLGdsYixmYl8xLHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8x"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTYuNzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NDA2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjguMzc1::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::ODEy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTQuMTg3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTYyNA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzI0OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NjQ5Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTYuNzQ4NzY4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjguMzc0Mzg0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTQuMTg3MTkyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::Ny4wOTM1OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::My41NDY3OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NDUsNDUsMTUsMTQsZmFsc2UsZmFsc2UsZmFsc2UsdHJ1ZSw3LDcsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTQsMTQsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMjgsMjgsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNTYsNTYsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTEyLDExMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDc5NC40ODI3NTggTUh6LDEsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8w"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::OA==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::OA==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjU2LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MTIwLjAwMDAwMCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NjQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MzIuNTMzMzI0IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NDg=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::OC4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::OTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::NC4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MTky::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::Mi4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::Mzg0::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MS4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjU1Ljk5OTg3MiBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTA5LjcxNDI1NyBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NjMuOTk5OTgxIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MzEuOTk5OTg5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MTUuOTk5OTk0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::Ny45OTk5OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::My45OTk5OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MS45OTk5OTkgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTUgSGkgRGl2aWRlLEMtQ291bnRlci01IExvdyBEaXZpZGUsQy1Db3VudGVyLTUgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci01IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTUgSW5wdXQgU291cmNlLEMtQ291bnRlci01IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTUgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTYgSGkgRGl2aWRlLEMtQ291bnRlci02IExvdyBEaXZpZGUsQy1Db3VudGVyLTYgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci02IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTYgSW5wdXQgU291cmNlLEMtQ291bnRlci02IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTYgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTcgSGkgRGl2aWRlLEMtQ291bnRlci03IExvdyBEaXZpZGUsQy1Db3VudGVyLTcgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci03IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTcgSW5wdXQgU291cmNlLEMtQ291bnRlci03IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTcgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OCw3LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDIsMSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDQsMywxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDYsNiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMiwxMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyNCwyNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw0OCw0OCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw5Niw5NiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxOTIsMTkyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCw3NjcuOTk5NjcxIE1IeiwxNTQ2MTU5OTY2LGdjbGssZ2xiLGZiXzEscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -library "pll" -name VHDL_FILE [file join $::quartus(qip_path) "clkgen.vhd"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.qip"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.qip"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.qip"]
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_ENV "Qsys"

783
common/pll.qsys Normal file
View File

@@ -0,0 +1,783 @@
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
element pll_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
element pll_1
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element pll_2
{
datum _sortIndex
{
value = "3";
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="5CSEBA6U23I7" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="pll_0_outclk1"
internal="pll_0.outclk1"
type="clock"
dir="start" />
<interface
name="pll_0_outclk2"
internal="pll_0.outclk2"
type="clock"
dir="start" />
<interface
name="pll_0_outclk3"
internal="pll_0.outclk3"
type="clock"
dir="start" />
<interface
name="pll_0_outclk4"
internal="pll_0.outclk4"
type="clock"
dir="start" />
<interface
name="pll_0_outclk5"
internal="pll_0.outclk5"
type="clock"
dir="start" />
<interface
name="pll_0_outclk6"
internal="pll_0.outclk6"
type="clock"
dir="start" />
<interface name="pll_0_refclk" internal="pll_0.refclk" type="clock" dir="end" />
<interface name="pll_0_reset" internal="pll_0.reset" type="reset" dir="end" />
<interface
name="pll_1_outclk0"
internal="pll_1.outclk0"
type="clock"
dir="start" />
<interface
name="pll_1_outclk1"
internal="pll_1.outclk1"
type="clock"
dir="start" />
<interface
name="pll_1_outclk2"
internal="pll_1.outclk2"
type="clock"
dir="start" />
<interface
name="pll_1_outclk3"
internal="pll_1.outclk3"
type="clock"
dir="start" />
<interface
name="pll_1_outclk4"
internal="pll_1.outclk4"
type="clock"
dir="start" />
<interface name="pll_1_reset" internal="pll_1.reset" type="reset" dir="end" />
<interface
name="pll_2_outclk0"
internal="pll_2.outclk0"
type="clock"
dir="start" />
<interface
name="pll_2_outclk1"
internal="pll_2.outclk1"
type="clock"
dir="start" />
<interface
name="pll_2_outclk2"
internal="pll_2.outclk2"
type="clock"
dir="start" />
<interface
name="pll_2_outclk3"
internal="pll_2.outclk3"
type="clock"
dir="start" />
<interface name="pll_2_outclk4" internal="pll_2.outclk4" />
<interface name="pll_2_reset" internal="pll_2.reset" type="reset" dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<module name="clk_0" kind="clock_source" version="17.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module name="pll_0" kind="altera_pll" version="17.1" enabled="1">
<parameter name="debug_print_output" value="false" />
<parameter name="debug_use_rbc_taf_method" value="false" />
<parameter name="device" value="5CSEBA6U23I7" />
<parameter name="device_family" value="Cyclone V" />
<parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_output_clock_frequency0" value="120.000000 MHz" />
<parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency3" value="32.533324 MHz" />
<parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
<parameter name="gui_actual_phase_shift0" value="0" />
<parameter name="gui_actual_phase_shift1" value="0" />
<parameter name="gui_actual_phase_shift10" value="0" />
<parameter name="gui_actual_phase_shift11" value="0" />
<parameter name="gui_actual_phase_shift12" value="0" />
<parameter name="gui_actual_phase_shift13" value="0" />
<parameter name="gui_actual_phase_shift14" value="0" />
<parameter name="gui_actual_phase_shift15" value="0" />
<parameter name="gui_actual_phase_shift16" value="0" />
<parameter name="gui_actual_phase_shift17" value="0" />
<parameter name="gui_actual_phase_shift2" value="0" />
<parameter name="gui_actual_phase_shift3" value="0" />
<parameter name="gui_actual_phase_shift4" value="0" />
<parameter name="gui_actual_phase_shift5" value="0" />
<parameter name="gui_actual_phase_shift6" value="0" />
<parameter name="gui_actual_phase_shift7" value="0" />
<parameter name="gui_actual_phase_shift8" value="0" />
<parameter name="gui_actual_phase_shift9" value="0" />
<parameter name="gui_cascade_counter0" value="false" />
<parameter name="gui_cascade_counter1" value="false" />
<parameter name="gui_cascade_counter10" value="false" />
<parameter name="gui_cascade_counter11" value="false" />
<parameter name="gui_cascade_counter12" value="false" />
<parameter name="gui_cascade_counter13" value="false" />
<parameter name="gui_cascade_counter14" value="false" />
<parameter name="gui_cascade_counter15" value="false" />
<parameter name="gui_cascade_counter16" value="false" />
<parameter name="gui_cascade_counter17" value="false" />
<parameter name="gui_cascade_counter2" value="false" />
<parameter name="gui_cascade_counter3" value="false" />
<parameter name="gui_cascade_counter4" value="false" />
<parameter name="gui_cascade_counter5" value="false" />
<parameter name="gui_cascade_counter6" value="false" />
<parameter name="gui_cascade_counter7" value="false" />
<parameter name="gui_cascade_counter8" value="false" />
<parameter name="gui_cascade_counter9" value="false" />
<parameter name="gui_cascade_outclk_index" value="0" />
<parameter name="gui_channel_spacing" value="0.0" />
<parameter name="gui_clk_bad" value="false" />
<parameter name="gui_device_speed_grade" value="2" />
<parameter name="gui_divide_factor_c0" value="1" />
<parameter name="gui_divide_factor_c1" value="1" />
<parameter name="gui_divide_factor_c10" value="1" />
<parameter name="gui_divide_factor_c11" value="1" />
<parameter name="gui_divide_factor_c12" value="1" />
<parameter name="gui_divide_factor_c13" value="1" />
<parameter name="gui_divide_factor_c14" value="1" />
<parameter name="gui_divide_factor_c15" value="1" />
<parameter name="gui_divide_factor_c16" value="1" />
<parameter name="gui_divide_factor_c17" value="1" />
<parameter name="gui_divide_factor_c2" value="1" />
<parameter name="gui_divide_factor_c3" value="1" />
<parameter name="gui_divide_factor_c4" value="1" />
<parameter name="gui_divide_factor_c5" value="1" />
<parameter name="gui_divide_factor_c6" value="1" />
<parameter name="gui_divide_factor_c7" value="1" />
<parameter name="gui_divide_factor_c8" value="1" />
<parameter name="gui_divide_factor_c9" value="1" />
<parameter name="gui_divide_factor_n" value="1" />
<parameter name="gui_dps_cntr" value="C0" />
<parameter name="gui_dps_dir" value="Positive" />
<parameter name="gui_dps_num" value="1" />
<parameter name="gui_dsm_out_sel" value="1st_order" />
<parameter name="gui_duty_cycle0" value="50" />
<parameter name="gui_duty_cycle1" value="50" />
<parameter name="gui_duty_cycle10" value="50" />
<parameter name="gui_duty_cycle11" value="50" />
<parameter name="gui_duty_cycle12" value="50" />
<parameter name="gui_duty_cycle13" value="50" />
<parameter name="gui_duty_cycle14" value="50" />
<parameter name="gui_duty_cycle15" value="50" />
<parameter name="gui_duty_cycle16" value="50" />
<parameter name="gui_duty_cycle17" value="50" />
<parameter name="gui_duty_cycle2" value="50" />
<parameter name="gui_duty_cycle3" value="50" />
<parameter name="gui_duty_cycle4" value="50" />
<parameter name="gui_duty_cycle5" value="50" />
<parameter name="gui_duty_cycle6" value="50" />
<parameter name="gui_duty_cycle7" value="50" />
<parameter name="gui_duty_cycle8" value="50" />
<parameter name="gui_duty_cycle9" value="50" />
<parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" />
<parameter name="gui_enable_cascade_out" value="false" />
<parameter name="gui_enable_mif_dps" value="false" />
<parameter name="gui_feedback_clock" value="Global Clock" />
<parameter name="gui_frac_multiply_factor" value="1" />
<parameter name="gui_fractional_cout" value="32" />
<parameter name="gui_mif_generate" value="false" />
<parameter name="gui_multiply_factor" value="1" />
<parameter name="gui_number_of_clocks" value="8" />
<parameter name="gui_operation_mode" value="normal" />
<parameter name="gui_output_clock_frequency0" value="256.0" />
<parameter name="gui_output_clock_frequency1" value="112.0" />
<parameter name="gui_output_clock_frequency10" value="100.0" />
<parameter name="gui_output_clock_frequency11" value="100.0" />
<parameter name="gui_output_clock_frequency12" value="100.0" />
<parameter name="gui_output_clock_frequency13" value="100.0" />
<parameter name="gui_output_clock_frequency14" value="100.0" />
<parameter name="gui_output_clock_frequency15" value="100.0" />
<parameter name="gui_output_clock_frequency16" value="100.0" />
<parameter name="gui_output_clock_frequency17" value="100.0" />
<parameter name="gui_output_clock_frequency2" value="64.0" />
<parameter name="gui_output_clock_frequency3" value="32.0" />
<parameter name="gui_output_clock_frequency4" value="16.0" />
<parameter name="gui_output_clock_frequency5" value="8.0" />
<parameter name="gui_output_clock_frequency6" value="4.0" />
<parameter name="gui_output_clock_frequency7" value="2.0" />
<parameter name="gui_output_clock_frequency8" value="1.0" />
<parameter name="gui_output_clock_frequency9" value="100.0" />
<parameter name="gui_phase_shift0" value="0" />
<parameter name="gui_phase_shift1" value="0" />
<parameter name="gui_phase_shift10" value="0" />
<parameter name="gui_phase_shift11" value="0" />
<parameter name="gui_phase_shift12" value="0" />
<parameter name="gui_phase_shift13" value="0" />
<parameter name="gui_phase_shift14" value="0" />
<parameter name="gui_phase_shift15" value="0" />
<parameter name="gui_phase_shift16" value="0" />
<parameter name="gui_phase_shift17" value="0" />
<parameter name="gui_phase_shift2" value="0" />
<parameter name="gui_phase_shift3" value="0" />
<parameter name="gui_phase_shift4" value="0" />
<parameter name="gui_phase_shift5" value="0" />
<parameter name="gui_phase_shift6" value="0" />
<parameter name="gui_phase_shift7" value="0" />
<parameter name="gui_phase_shift8" value="0" />
<parameter name="gui_phase_shift9" value="0" />
<parameter name="gui_phase_shift_deg0" value="0.0" />
<parameter name="gui_phase_shift_deg1" value="0.0" />
<parameter name="gui_phase_shift_deg10" value="0.0" />
<parameter name="gui_phase_shift_deg11" value="0.0" />
<parameter name="gui_phase_shift_deg12" value="0.0" />
<parameter name="gui_phase_shift_deg13" value="0.0" />
<parameter name="gui_phase_shift_deg14" value="0.0" />
<parameter name="gui_phase_shift_deg15" value="0.0" />
<parameter name="gui_phase_shift_deg16" value="0.0" />
<parameter name="gui_phase_shift_deg17" value="0.0" />
<parameter name="gui_phase_shift_deg2" value="0.0" />
<parameter name="gui_phase_shift_deg3" value="0.0" />
<parameter name="gui_phase_shift_deg4" value="0.0" />
<parameter name="gui_phase_shift_deg5" value="0.0" />
<parameter name="gui_phase_shift_deg6" value="0.0" />
<parameter name="gui_phase_shift_deg7" value="0.0" />
<parameter name="gui_phase_shift_deg8" value="0.0" />
<parameter name="gui_phase_shift_deg9" value="0.0" />
<parameter name="gui_phout_division" value="1" />
<parameter name="gui_pll_auto_reset" value="On" />
<parameter name="gui_pll_bandwidth_preset" value="Auto" />
<parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
<parameter name="gui_pll_mode" value="Fractional-N PLL" />
<parameter name="gui_ps_units0" value="ps" />
<parameter name="gui_ps_units1" value="ps" />
<parameter name="gui_ps_units10" value="ps" />
<parameter name="gui_ps_units11" value="ps" />
<parameter name="gui_ps_units12" value="ps" />
<parameter name="gui_ps_units13" value="ps" />
<parameter name="gui_ps_units14" value="ps" />
<parameter name="gui_ps_units15" value="ps" />
<parameter name="gui_ps_units16" value="ps" />
<parameter name="gui_ps_units17" value="ps" />
<parameter name="gui_ps_units2" value="ps" />
<parameter name="gui_ps_units3" value="ps" />
<parameter name="gui_ps_units4" value="ps" />
<parameter name="gui_ps_units5" value="ps" />
<parameter name="gui_ps_units6" value="ps" />
<parameter name="gui_ps_units7" value="ps" />
<parameter name="gui_ps_units8" value="ps" />
<parameter name="gui_ps_units9" value="ps" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_switch" value="false" />
<parameter name="gui_reference_clock_frequency" value="50.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="false" />
</module>
<module name="pll_1" kind="altera_pll" version="17.1" enabled="1">
<parameter name="debug_print_output" value="false" />
<parameter name="debug_use_rbc_taf_method" value="false" />
<parameter name="device" value="5CSEBA6U23I7" />
<parameter name="device_family" value="Cyclone V" />
<parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
<parameter name="gui_actual_phase_shift0" value="0" />
<parameter name="gui_actual_phase_shift1" value="0" />
<parameter name="gui_actual_phase_shift10" value="0" />
<parameter name="gui_actual_phase_shift11" value="0" />
<parameter name="gui_actual_phase_shift12" value="0" />
<parameter name="gui_actual_phase_shift13" value="0" />
<parameter name="gui_actual_phase_shift14" value="0" />
<parameter name="gui_actual_phase_shift15" value="0" />
<parameter name="gui_actual_phase_shift16" value="0" />
<parameter name="gui_actual_phase_shift17" value="0" />
<parameter name="gui_actual_phase_shift2" value="0" />
<parameter name="gui_actual_phase_shift3" value="0" />
<parameter name="gui_actual_phase_shift4" value="0" />
<parameter name="gui_actual_phase_shift5" value="0" />
<parameter name="gui_actual_phase_shift6" value="0" />
<parameter name="gui_actual_phase_shift7" value="0" />
<parameter name="gui_actual_phase_shift8" value="0" />
<parameter name="gui_actual_phase_shift9" value="0" />
<parameter name="gui_cascade_counter0" value="false" />
<parameter name="gui_cascade_counter1" value="false" />
<parameter name="gui_cascade_counter10" value="false" />
<parameter name="gui_cascade_counter11" value="false" />
<parameter name="gui_cascade_counter12" value="false" />
<parameter name="gui_cascade_counter13" value="false" />
<parameter name="gui_cascade_counter14" value="false" />
<parameter name="gui_cascade_counter15" value="false" />
<parameter name="gui_cascade_counter16" value="false" />
<parameter name="gui_cascade_counter17" value="false" />
<parameter name="gui_cascade_counter2" value="false" />
<parameter name="gui_cascade_counter3" value="false" />
<parameter name="gui_cascade_counter4" value="false" />
<parameter name="gui_cascade_counter5" value="false" />
<parameter name="gui_cascade_counter6" value="false" />
<parameter name="gui_cascade_counter7" value="false" />
<parameter name="gui_cascade_counter8" value="false" />
<parameter name="gui_cascade_counter9" value="false" />
<parameter name="gui_cascade_outclk_index" value="0" />
<parameter name="gui_channel_spacing" value="0.0" />
<parameter name="gui_clk_bad" value="false" />
<parameter name="gui_device_speed_grade" value="2" />
<parameter name="gui_divide_factor_c0" value="1" />
<parameter name="gui_divide_factor_c1" value="1" />
<parameter name="gui_divide_factor_c10" value="1" />
<parameter name="gui_divide_factor_c11" value="1" />
<parameter name="gui_divide_factor_c12" value="1" />
<parameter name="gui_divide_factor_c13" value="1" />
<parameter name="gui_divide_factor_c14" value="1" />
<parameter name="gui_divide_factor_c15" value="1" />
<parameter name="gui_divide_factor_c16" value="1" />
<parameter name="gui_divide_factor_c17" value="1" />
<parameter name="gui_divide_factor_c2" value="1" />
<parameter name="gui_divide_factor_c3" value="1" />
<parameter name="gui_divide_factor_c4" value="1" />
<parameter name="gui_divide_factor_c5" value="1" />
<parameter name="gui_divide_factor_c6" value="1" />
<parameter name="gui_divide_factor_c7" value="1" />
<parameter name="gui_divide_factor_c8" value="1" />
<parameter name="gui_divide_factor_c9" value="1" />
<parameter name="gui_divide_factor_n" value="1" />
<parameter name="gui_dps_cntr" value="C0" />
<parameter name="gui_dps_dir" value="Positive" />
<parameter name="gui_dps_num" value="1" />
<parameter name="gui_dsm_out_sel" value="1st_order" />
<parameter name="gui_duty_cycle0" value="50" />
<parameter name="gui_duty_cycle1" value="50" />
<parameter name="gui_duty_cycle10" value="50" />
<parameter name="gui_duty_cycle11" value="50" />
<parameter name="gui_duty_cycle12" value="50" />
<parameter name="gui_duty_cycle13" value="50" />
<parameter name="gui_duty_cycle14" value="50" />
<parameter name="gui_duty_cycle15" value="50" />
<parameter name="gui_duty_cycle16" value="50" />
<parameter name="gui_duty_cycle17" value="50" />
<parameter name="gui_duty_cycle2" value="50" />
<parameter name="gui_duty_cycle3" value="50" />
<parameter name="gui_duty_cycle4" value="50" />
<parameter name="gui_duty_cycle5" value="50" />
<parameter name="gui_duty_cycle6" value="50" />
<parameter name="gui_duty_cycle7" value="50" />
<parameter name="gui_duty_cycle8" value="50" />
<parameter name="gui_duty_cycle9" value="50" />
<parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" />
<parameter name="gui_enable_cascade_out" value="false" />
<parameter name="gui_enable_mif_dps" value="false" />
<parameter name="gui_feedback_clock" value="Global Clock" />
<parameter name="gui_frac_multiply_factor" value="1" />
<parameter name="gui_fractional_cout" value="32" />
<parameter name="gui_mif_generate" value="false" />
<parameter name="gui_multiply_factor" value="1" />
<parameter name="gui_number_of_clocks" value="5" />
<parameter name="gui_operation_mode" value="normal" />
<parameter name="gui_output_clock_frequency0" value="56.75" />
<parameter name="gui_output_clock_frequency1" value="28.375" />
<parameter name="gui_output_clock_frequency10" value="100.0" />
<parameter name="gui_output_clock_frequency11" value="100.0" />
<parameter name="gui_output_clock_frequency12" value="100.0" />
<parameter name="gui_output_clock_frequency13" value="100.0" />
<parameter name="gui_output_clock_frequency14" value="100.0" />
<parameter name="gui_output_clock_frequency15" value="100.0" />
<parameter name="gui_output_clock_frequency16" value="100.0" />
<parameter name="gui_output_clock_frequency17" value="100.0" />
<parameter name="gui_output_clock_frequency2" value="14.1875" />
<parameter name="gui_output_clock_frequency3" value="7.09375" />
<parameter name="gui_output_clock_frequency4" value="3.546875" />
<parameter name="gui_output_clock_frequency5" value="7.09375" />
<parameter name="gui_output_clock_frequency6" value="3.546875" />
<parameter name="gui_output_clock_frequency7" value="3.546875" />
<parameter name="gui_output_clock_frequency8" value="3.546875" />
<parameter name="gui_output_clock_frequency9" value="100.0" />
<parameter name="gui_phase_shift0" value="0" />
<parameter name="gui_phase_shift1" value="0" />
<parameter name="gui_phase_shift10" value="0" />
<parameter name="gui_phase_shift11" value="0" />
<parameter name="gui_phase_shift12" value="0" />
<parameter name="gui_phase_shift13" value="0" />
<parameter name="gui_phase_shift14" value="0" />
<parameter name="gui_phase_shift15" value="0" />
<parameter name="gui_phase_shift16" value="0" />
<parameter name="gui_phase_shift17" value="0" />
<parameter name="gui_phase_shift2" value="0" />
<parameter name="gui_phase_shift3" value="0" />
<parameter name="gui_phase_shift4" value="0" />
<parameter name="gui_phase_shift5" value="0" />
<parameter name="gui_phase_shift6" value="0" />
<parameter name="gui_phase_shift7" value="0" />
<parameter name="gui_phase_shift8" value="0" />
<parameter name="gui_phase_shift9" value="0" />
<parameter name="gui_phase_shift_deg0" value="0.0" />
<parameter name="gui_phase_shift_deg1" value="0.0" />
<parameter name="gui_phase_shift_deg10" value="0.0" />
<parameter name="gui_phase_shift_deg11" value="0.0" />
<parameter name="gui_phase_shift_deg12" value="0.0" />
<parameter name="gui_phase_shift_deg13" value="0.0" />
<parameter name="gui_phase_shift_deg14" value="0.0" />
<parameter name="gui_phase_shift_deg15" value="0.0" />
<parameter name="gui_phase_shift_deg16" value="0.0" />
<parameter name="gui_phase_shift_deg17" value="0.0" />
<parameter name="gui_phase_shift_deg2" value="0.0" />
<parameter name="gui_phase_shift_deg3" value="0.0" />
<parameter name="gui_phase_shift_deg4" value="0.0" />
<parameter name="gui_phase_shift_deg5" value="0.0" />
<parameter name="gui_phase_shift_deg6" value="0.0" />
<parameter name="gui_phase_shift_deg7" value="0.0" />
<parameter name="gui_phase_shift_deg8" value="0.0" />
<parameter name="gui_phase_shift_deg9" value="0.0" />
<parameter name="gui_phout_division" value="1" />
<parameter name="gui_pll_auto_reset" value="On" />
<parameter name="gui_pll_bandwidth_preset" value="Auto" />
<parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
<parameter name="gui_pll_mode" value="Integer-N PLL" />
<parameter name="gui_ps_units0" value="ps" />
<parameter name="gui_ps_units1" value="ps" />
<parameter name="gui_ps_units10" value="ps" />
<parameter name="gui_ps_units11" value="ps" />
<parameter name="gui_ps_units12" value="ps" />
<parameter name="gui_ps_units13" value="ps" />
<parameter name="gui_ps_units14" value="ps" />
<parameter name="gui_ps_units15" value="ps" />
<parameter name="gui_ps_units16" value="ps" />
<parameter name="gui_ps_units17" value="ps" />
<parameter name="gui_ps_units2" value="ps" />
<parameter name="gui_ps_units3" value="ps" />
<parameter name="gui_ps_units4" value="ps" />
<parameter name="gui_ps_units5" value="ps" />
<parameter name="gui_ps_units6" value="ps" />
<parameter name="gui_ps_units7" value="ps" />
<parameter name="gui_ps_units8" value="ps" />
<parameter name="gui_ps_units9" value="ps" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_switch" value="false" />
<parameter name="gui_reference_clock_frequency" value="256.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="false" />
</module>
<module name="pll_2" kind="altera_pll" version="17.1" enabled="1">
<parameter name="debug_print_output" value="false" />
<parameter name="debug_use_rbc_taf_method" value="false" />
<parameter name="device" value="5CSEBA6U23I7" />
<parameter name="device_family" value="Cyclone V" />
<parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_output_clock_frequency0" value="36.000000 MHz" />
<parameter name="gui_actual_output_clock_frequency1" value="31.500000 MHz" />
<parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency2" value="25.568627 MHz" />
<parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
<parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
<parameter name="gui_actual_phase_shift0" value="0" />
<parameter name="gui_actual_phase_shift1" value="0" />
<parameter name="gui_actual_phase_shift10" value="0" />
<parameter name="gui_actual_phase_shift11" value="0" />
<parameter name="gui_actual_phase_shift12" value="0" />
<parameter name="gui_actual_phase_shift13" value="0" />
<parameter name="gui_actual_phase_shift14" value="0" />
<parameter name="gui_actual_phase_shift15" value="0" />
<parameter name="gui_actual_phase_shift16" value="0" />
<parameter name="gui_actual_phase_shift17" value="0" />
<parameter name="gui_actual_phase_shift2" value="0" />
<parameter name="gui_actual_phase_shift3" value="0" />
<parameter name="gui_actual_phase_shift4" value="0" />
<parameter name="gui_actual_phase_shift5" value="0" />
<parameter name="gui_actual_phase_shift6" value="0" />
<parameter name="gui_actual_phase_shift7" value="0" />
<parameter name="gui_actual_phase_shift8" value="0" />
<parameter name="gui_actual_phase_shift9" value="0" />
<parameter name="gui_cascade_counter0" value="false" />
<parameter name="gui_cascade_counter1" value="false" />
<parameter name="gui_cascade_counter10" value="false" />
<parameter name="gui_cascade_counter11" value="false" />
<parameter name="gui_cascade_counter12" value="false" />
<parameter name="gui_cascade_counter13" value="false" />
<parameter name="gui_cascade_counter14" value="false" />
<parameter name="gui_cascade_counter15" value="false" />
<parameter name="gui_cascade_counter16" value="false" />
<parameter name="gui_cascade_counter17" value="false" />
<parameter name="gui_cascade_counter2" value="false" />
<parameter name="gui_cascade_counter3" value="false" />
<parameter name="gui_cascade_counter4" value="false" />
<parameter name="gui_cascade_counter5" value="false" />
<parameter name="gui_cascade_counter6" value="false" />
<parameter name="gui_cascade_counter7" value="false" />
<parameter name="gui_cascade_counter8" value="false" />
<parameter name="gui_cascade_counter9" value="false" />
<parameter name="gui_cascade_outclk_index" value="0" />
<parameter name="gui_channel_spacing" value="0.0" />
<parameter name="gui_clk_bad" value="false" />
<parameter name="gui_device_speed_grade" value="1" />
<parameter name="gui_divide_factor_c0" value="1" />
<parameter name="gui_divide_factor_c1" value="1" />
<parameter name="gui_divide_factor_c10" value="1" />
<parameter name="gui_divide_factor_c11" value="1" />
<parameter name="gui_divide_factor_c12" value="1" />
<parameter name="gui_divide_factor_c13" value="1" />
<parameter name="gui_divide_factor_c14" value="1" />
<parameter name="gui_divide_factor_c15" value="1" />
<parameter name="gui_divide_factor_c16" value="1" />
<parameter name="gui_divide_factor_c17" value="1" />
<parameter name="gui_divide_factor_c2" value="1" />
<parameter name="gui_divide_factor_c3" value="1" />
<parameter name="gui_divide_factor_c4" value="1" />
<parameter name="gui_divide_factor_c5" value="1" />
<parameter name="gui_divide_factor_c6" value="1" />
<parameter name="gui_divide_factor_c7" value="1" />
<parameter name="gui_divide_factor_c8" value="1" />
<parameter name="gui_divide_factor_c9" value="1" />
<parameter name="gui_divide_factor_n" value="1" />
<parameter name="gui_dps_cntr" value="C0" />
<parameter name="gui_dps_dir" value="Positive" />
<parameter name="gui_dps_num" value="1" />
<parameter name="gui_dsm_out_sel" value="1st_order" />
<parameter name="gui_duty_cycle0" value="50" />
<parameter name="gui_duty_cycle1" value="50" />
<parameter name="gui_duty_cycle10" value="50" />
<parameter name="gui_duty_cycle11" value="50" />
<parameter name="gui_duty_cycle12" value="50" />
<parameter name="gui_duty_cycle13" value="50" />
<parameter name="gui_duty_cycle14" value="50" />
<parameter name="gui_duty_cycle15" value="50" />
<parameter name="gui_duty_cycle16" value="50" />
<parameter name="gui_duty_cycle17" value="50" />
<parameter name="gui_duty_cycle2" value="50" />
<parameter name="gui_duty_cycle3" value="50" />
<parameter name="gui_duty_cycle4" value="50" />
<parameter name="gui_duty_cycle5" value="50" />
<parameter name="gui_duty_cycle6" value="50" />
<parameter name="gui_duty_cycle7" value="50" />
<parameter name="gui_duty_cycle8" value="50" />
<parameter name="gui_duty_cycle9" value="50" />
<parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" />
<parameter name="gui_enable_cascade_out" value="false" />
<parameter name="gui_enable_mif_dps" value="false" />
<parameter name="gui_feedback_clock" value="Global Clock" />
<parameter name="gui_frac_multiply_factor" value="1" />
<parameter name="gui_fractional_cout" value="32" />
<parameter name="gui_mif_generate" value="false" />
<parameter name="gui_multiply_factor" value="1" />
<parameter name="gui_number_of_clocks" value="4" />
<parameter name="gui_operation_mode" value="normal" />
<parameter name="gui_output_clock_frequency0" value="31.1" />
<parameter name="gui_output_clock_frequency1" value="25.175" />
<parameter name="gui_output_clock_frequency10" value="100.0" />
<parameter name="gui_output_clock_frequency11" value="100.0" />
<parameter name="gui_output_clock_frequency12" value="100.0" />
<parameter name="gui_output_clock_frequency13" value="100.0" />
<parameter name="gui_output_clock_frequency14" value="100.0" />
<parameter name="gui_output_clock_frequency15" value="100.0" />
<parameter name="gui_output_clock_frequency16" value="100.0" />
<parameter name="gui_output_clock_frequency17" value="100.0" />
<parameter name="gui_output_clock_frequency2" value="17.734475" />
<parameter name="gui_output_clock_frequency3" value="8.867237" />
<parameter name="gui_output_clock_frequency4" value="8.867237" />
<parameter name="gui_output_clock_frequency5" value="100.0" />
<parameter name="gui_output_clock_frequency6" value="100.0" />
<parameter name="gui_output_clock_frequency7" value="100.0" />
<parameter name="gui_output_clock_frequency8" value="100.0" />
<parameter name="gui_output_clock_frequency9" value="100.0" />
<parameter name="gui_phase_shift0" value="0" />
<parameter name="gui_phase_shift1" value="0" />
<parameter name="gui_phase_shift10" value="0" />
<parameter name="gui_phase_shift11" value="0" />
<parameter name="gui_phase_shift12" value="0" />
<parameter name="gui_phase_shift13" value="0" />
<parameter name="gui_phase_shift14" value="0" />
<parameter name="gui_phase_shift15" value="0" />
<parameter name="gui_phase_shift16" value="0" />
<parameter name="gui_phase_shift17" value="0" />
<parameter name="gui_phase_shift2" value="0" />
<parameter name="gui_phase_shift3" value="0" />
<parameter name="gui_phase_shift4" value="0" />
<parameter name="gui_phase_shift5" value="0" />
<parameter name="gui_phase_shift6" value="0" />
<parameter name="gui_phase_shift7" value="0" />
<parameter name="gui_phase_shift8" value="0" />
<parameter name="gui_phase_shift9" value="0" />
<parameter name="gui_phase_shift_deg0" value="0.0" />
<parameter name="gui_phase_shift_deg1" value="0.0" />
<parameter name="gui_phase_shift_deg10" value="0.0" />
<parameter name="gui_phase_shift_deg11" value="0.0" />
<parameter name="gui_phase_shift_deg12" value="0.0" />
<parameter name="gui_phase_shift_deg13" value="0.0" />
<parameter name="gui_phase_shift_deg14" value="0.0" />
<parameter name="gui_phase_shift_deg15" value="0.0" />
<parameter name="gui_phase_shift_deg16" value="0.0" />
<parameter name="gui_phase_shift_deg17" value="0.0" />
<parameter name="gui_phase_shift_deg2" value="0.0" />
<parameter name="gui_phase_shift_deg3" value="0.0" />
<parameter name="gui_phase_shift_deg4" value="0.0" />
<parameter name="gui_phase_shift_deg5" value="0.0" />
<parameter name="gui_phase_shift_deg6" value="0.0" />
<parameter name="gui_phase_shift_deg7" value="0.0" />
<parameter name="gui_phase_shift_deg8" value="0.0" />
<parameter name="gui_phase_shift_deg9" value="0.0" />
<parameter name="gui_phout_division" value="1" />
<parameter name="gui_pll_auto_reset" value="On" />
<parameter name="gui_pll_bandwidth_preset" value="Auto" />
<parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
<parameter name="gui_pll_mode" value="Fractional-N PLL" />
<parameter name="gui_ps_units0" value="ps" />
<parameter name="gui_ps_units1" value="ps" />
<parameter name="gui_ps_units10" value="ps" />
<parameter name="gui_ps_units11" value="ps" />
<parameter name="gui_ps_units12" value="ps" />
<parameter name="gui_ps_units13" value="ps" />
<parameter name="gui_ps_units14" value="ps" />
<parameter name="gui_ps_units15" value="ps" />
<parameter name="gui_ps_units16" value="ps" />
<parameter name="gui_ps_units17" value="ps" />
<parameter name="gui_ps_units2" value="degrees" />
<parameter name="gui_ps_units3" value="ps" />
<parameter name="gui_ps_units4" value="ps" />
<parameter name="gui_ps_units5" value="ps" />
<parameter name="gui_ps_units6" value="ps" />
<parameter name="gui_ps_units7" value="ps" />
<parameter name="gui_ps_units8" value="ps" />
<parameter name="gui_ps_units9" value="ps" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_switch" value="false" />
<parameter name="gui_reference_clock_frequency" value="256.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="false" />
</module>
<connection kind="clock" version="17.1" start="pll_0.outclk0" end="pll_1.refclk" />
<connection kind="clock" version="17.1" start="pll_0.outclk0" end="pll_2.refclk" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

13411
common/pll.sopcinfo Normal file
View File

File diff suppressed because it is too large Load Diff

268
common/pll/pll.bsf Normal file
View File

@@ -0,0 +1,268 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 664)
(text "pll" (rect 122 -1 129 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 648 20 660)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 96 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "pll_0_refclk_clk" (rect 0 0 62 12)(font "Arial" (font_size 8)))
(text "pll_0_refclk_clk" (rect 4 101 100 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 96 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "pll_0_reset_reset" (rect 0 0 69 12)(font "Arial" (font_size 8)))
(text "pll_0_reset_reset" (rect 4 141 106 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 96 152)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "pll_1_reset_reset" (rect 0 0 68 12)(font "Arial" (font_size 8)))
(text "pll_1_reset_reset" (rect 4 181 106 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 96 192)(line_width 1))
)
(port
(pt 0 232)
(input)
(text "pll_2_reset_reset" (rect 0 0 69 12)(font "Arial" (font_size 8)))
(text "pll_2_reset_reset" (rect 4 221 106 232)(font "Arial" (font_size 8)))
(line (pt 0 232)(pt 96 232)(line_width 1))
)
(port
(pt 0 272)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 261 82 272)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 96 272)(line_width 1))
)
(port
(pt 256 72)
(output)
(text "pll_0_outclk1_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
(text "pll_0_outclk1_clk" (rect 172 61 274 72)(font "Arial" (font_size 8)))
(line (pt 256 72)(pt 160 72)(line_width 1))
)
(port
(pt 256 112)
(output)
(text "pll_0_outclk2_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_0_outclk2_clk" (rect 170 101 272 112)(font "Arial" (font_size 8)))
(line (pt 256 112)(pt 160 112)(line_width 1))
)
(port
(pt 256 152)
(output)
(text "pll_0_outclk3_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_0_outclk3_clk" (rect 170 141 272 152)(font "Arial" (font_size 8)))
(line (pt 256 152)(pt 160 152)(line_width 1))
)
(port
(pt 256 192)
(output)
(text "pll_0_outclk4_clk" (rect 0 0 68 12)(font "Arial" (font_size 8)))
(text "pll_0_outclk4_clk" (rect 170 181 272 192)(font "Arial" (font_size 8)))
(line (pt 256 192)(pt 160 192)(line_width 1))
)
(port
(pt 256 232)
(output)
(text "pll_0_outclk5_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_0_outclk5_clk" (rect 170 221 272 232)(font "Arial" (font_size 8)))
(line (pt 256 232)(pt 160 232)(line_width 1))
)
(port
(pt 256 272)
(output)
(text "pll_0_outclk6_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_0_outclk6_clk" (rect 170 261 272 272)(font "Arial" (font_size 8)))
(line (pt 256 272)(pt 160 272)(line_width 1))
)
(port
(pt 256 312)
(output)
(text "pll_1_outclk0_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
(text "pll_1_outclk0_clk" (rect 172 301 274 312)(font "Arial" (font_size 8)))
(line (pt 256 312)(pt 160 312)(line_width 1))
)
(port
(pt 256 352)
(output)
(text "pll_1_outclk1_clk" (rect 0 0 64 12)(font "Arial" (font_size 8)))
(text "pll_1_outclk1_clk" (rect 174 341 276 352)(font "Arial" (font_size 8)))
(line (pt 256 352)(pt 160 352)(line_width 1))
)
(port
(pt 256 392)
(output)
(text "pll_1_outclk2_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
(text "pll_1_outclk2_clk" (rect 172 381 274 392)(font "Arial" (font_size 8)))
(line (pt 256 392)(pt 160 392)(line_width 1))
)
(port
(pt 256 432)
(output)
(text "pll_1_outclk3_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
(text "pll_1_outclk3_clk" (rect 172 421 274 432)(font "Arial" (font_size 8)))
(line (pt 256 432)(pt 160 432)(line_width 1))
)
(port
(pt 256 472)
(output)
(text "pll_1_outclk4_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_1_outclk4_clk" (rect 172 461 274 472)(font "Arial" (font_size 8)))
(line (pt 256 472)(pt 160 472)(line_width 1))
)
(port
(pt 256 512)
(output)
(text "pll_2_outclk0_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_2_outclk0_clk" (rect 170 501 272 512)(font "Arial" (font_size 8)))
(line (pt 256 512)(pt 160 512)(line_width 1))
)
(port
(pt 256 552)
(output)
(text "pll_2_outclk1_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
(text "pll_2_outclk1_clk" (rect 172 541 274 552)(font "Arial" (font_size 8)))
(line (pt 256 552)(pt 160 552)(line_width 1))
)
(port
(pt 256 592)
(output)
(text "pll_2_outclk2_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_2_outclk2_clk" (rect 170 581 272 592)(font "Arial" (font_size 8)))
(line (pt 256 592)(pt 160 592)(line_width 1))
)
(port
(pt 256 632)
(output)
(text "pll_2_outclk3_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "pll_2_outclk3_clk" (rect 170 621 272 632)(font "Arial" (font_size 8)))
(line (pt 256 632)(pt 160 632)(line_width 1))
)
(drawing
(text "clk" (rect 81 43 180 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 101 67 220 144)(font "Arial" (color 0 0 0)))
(text "pll_0_outclk1" (rect 161 43 400 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 67 308 144)(font "Arial" (color 0 0 0)))
(text "pll_0_outclk2" (rect 161 83 400 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 107 308 224)(font "Arial" (color 0 0 0)))
(text "pll_0_outclk3" (rect 161 123 400 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 147 308 304)(font "Arial" (color 0 0 0)))
(text "pll_0_outclk4" (rect 161 163 400 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 187 308 384)(font "Arial" (color 0 0 0)))
(text "pll_0_outclk5" (rect 161 203 400 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 227 308 464)(font "Arial" (color 0 0 0)))
(text "pll_0_outclk6" (rect 161 243 400 499)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 267 308 544)(font "Arial" (color 0 0 0)))
(text "pll_0_refclk" (rect 28 83 128 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 101 107 220 224)(font "Arial" (color 0 0 0)))
(text "pll_0_reset" (rect 31 123 128 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 101 147 232 304)(font "Arial" (color 0 0 0)))
(text "pll_1_outclk0" (rect 161 283 400 579)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 307 308 624)(font "Arial" (color 0 0 0)))
(text "pll_1_outclk1" (rect 161 323 400 659)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 347 308 704)(font "Arial" (color 0 0 0)))
(text "pll_1_outclk2" (rect 161 363 400 739)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 387 308 784)(font "Arial" (color 0 0 0)))
(text "pll_1_outclk3" (rect 161 403 400 819)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 427 308 864)(font "Arial" (color 0 0 0)))
(text "pll_1_outclk4" (rect 161 443 400 899)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 467 308 944)(font "Arial" (color 0 0 0)))
(text "pll_1_reset" (rect 33 163 132 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 101 187 232 384)(font "Arial" (color 0 0 0)))
(text "pll_2_outclk0" (rect 161 483 400 979)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 507 308 1024)(font "Arial" (color 0 0 0)))
(text "pll_2_outclk1" (rect 161 523 400 1059)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 547 308 1104)(font "Arial" (color 0 0 0)))
(text "pll_2_outclk2" (rect 161 563 400 1139)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 587 308 1184)(font "Arial" (color 0 0 0)))
(text "pll_2_outclk3" (rect 161 603 400 1219)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 145 627 308 1264)(font "Arial" (color 0 0 0)))
(text "pll_2_reset" (rect 31 203 128 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 101 227 232 464)(font "Arial" (color 0 0 0)))
(text "reset" (rect 67 243 164 499)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 101 267 244 544)(font "Arial" (color 0 0 0)))
(text " pll " (rect 244 648 518 1306)(font "Arial" ))
(line (pt 96 32)(pt 160 32)(line_width 1))
(line (pt 160 32)(pt 160 648)(line_width 1))
(line (pt 96 648)(pt 160 648)(line_width 1))
(line (pt 96 32)(pt 96 648)(line_width 1))
(line (pt 97 52)(pt 97 76)(line_width 1))
(line (pt 98 52)(pt 98 76)(line_width 1))
(line (pt 159 52)(pt 159 76)(line_width 1))
(line (pt 158 52)(pt 158 76)(line_width 1))
(line (pt 159 92)(pt 159 116)(line_width 1))
(line (pt 158 92)(pt 158 116)(line_width 1))
(line (pt 159 132)(pt 159 156)(line_width 1))
(line (pt 158 132)(pt 158 156)(line_width 1))
(line (pt 159 172)(pt 159 196)(line_width 1))
(line (pt 158 172)(pt 158 196)(line_width 1))
(line (pt 159 212)(pt 159 236)(line_width 1))
(line (pt 158 212)(pt 158 236)(line_width 1))
(line (pt 159 252)(pt 159 276)(line_width 1))
(line (pt 158 252)(pt 158 276)(line_width 1))
(line (pt 97 92)(pt 97 116)(line_width 1))
(line (pt 98 92)(pt 98 116)(line_width 1))
(line (pt 97 132)(pt 97 156)(line_width 1))
(line (pt 98 132)(pt 98 156)(line_width 1))
(line (pt 159 292)(pt 159 316)(line_width 1))
(line (pt 158 292)(pt 158 316)(line_width 1))
(line (pt 159 332)(pt 159 356)(line_width 1))
(line (pt 158 332)(pt 158 356)(line_width 1))
(line (pt 159 372)(pt 159 396)(line_width 1))
(line (pt 158 372)(pt 158 396)(line_width 1))
(line (pt 159 412)(pt 159 436)(line_width 1))
(line (pt 158 412)(pt 158 436)(line_width 1))
(line (pt 159 452)(pt 159 476)(line_width 1))
(line (pt 158 452)(pt 158 476)(line_width 1))
(line (pt 97 172)(pt 97 196)(line_width 1))
(line (pt 98 172)(pt 98 196)(line_width 1))
(line (pt 159 492)(pt 159 516)(line_width 1))
(line (pt 158 492)(pt 158 516)(line_width 1))
(line (pt 159 532)(pt 159 556)(line_width 1))
(line (pt 158 532)(pt 158 556)(line_width 1))
(line (pt 159 572)(pt 159 596)(line_width 1))
(line (pt 158 572)(pt 158 596)(line_width 1))
(line (pt 159 612)(pt 159 636)(line_width 1))
(line (pt 158 612)(pt 158 636)(line_width 1))
(line (pt 97 212)(pt 97 236)(line_width 1))
(line (pt 98 212)(pt 98 236)(line_width 1))
(line (pt 97 252)(pt 97 276)(line_width 1))
(line (pt 98 252)(pt 98 276)(line_width 1))
(line (pt 0 0)(pt 256 0)(line_width 1))
(line (pt 256 0)(pt 256 664)(line_width 1))
(line (pt 0 664)(pt 256 664)(line_width 1))
(line (pt 0 0)(pt 0 664)(line_width 1))
)
)

26
common/pll/pll.cmp Normal file
View File

@@ -0,0 +1,26 @@
component pll is
port (
clk_clk : in std_logic := 'X'; -- clk
pll_0_outclk1_clk : out std_logic; -- clk
pll_0_outclk2_clk : out std_logic; -- clk
pll_0_outclk3_clk : out std_logic; -- clk
pll_0_outclk4_clk : out std_logic; -- clk
pll_0_outclk5_clk : out std_logic; -- clk
pll_0_outclk6_clk : out std_logic; -- clk
pll_0_refclk_clk : in std_logic := 'X'; -- clk
pll_0_reset_reset : in std_logic := 'X'; -- reset
pll_1_outclk0_clk : out std_logic; -- clk
pll_1_outclk1_clk : out std_logic; -- clk
pll_1_outclk2_clk : out std_logic; -- clk
pll_1_outclk3_clk : out std_logic; -- clk
pll_1_outclk4_clk : out std_logic; -- clk
pll_1_reset_reset : in std_logic := 'X'; -- reset
pll_2_outclk0_clk : out std_logic; -- clk
pll_2_outclk1_clk : out std_logic; -- clk
pll_2_outclk2_clk : out std_logic; -- clk
pll_2_outclk3_clk : out std_logic; -- clk
pll_2_reset_reset : in std_logic := 'X'; -- reset
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component pll;

5938
common/pll/pll.html Normal file
View File

File diff suppressed because it is too large Load Diff

2212
common/pll/pll.xml Normal file
View File

File diff suppressed because one or more lines are too long

46
common/pll/pll_bb.v Normal file
View File

@@ -0,0 +1,46 @@
module pll (
clk_clk,
pll_0_outclk1_clk,
pll_0_outclk2_clk,
pll_0_outclk3_clk,
pll_0_outclk4_clk,
pll_0_outclk5_clk,
pll_0_outclk6_clk,
pll_0_refclk_clk,
pll_0_reset_reset,
pll_1_outclk0_clk,
pll_1_outclk1_clk,
pll_1_outclk2_clk,
pll_1_outclk3_clk,
pll_1_outclk4_clk,
pll_1_reset_reset,
pll_2_outclk0_clk,
pll_2_outclk1_clk,
pll_2_outclk2_clk,
pll_2_outclk3_clk,
pll_2_reset_reset,
reset_reset_n);
input clk_clk;
output pll_0_outclk1_clk;
output pll_0_outclk2_clk;
output pll_0_outclk3_clk;
output pll_0_outclk4_clk;
output pll_0_outclk5_clk;
output pll_0_outclk6_clk;
input pll_0_refclk_clk;
input pll_0_reset_reset;
output pll_1_outclk0_clk;
output pll_1_outclk1_clk;
output pll_1_outclk2_clk;
output pll_1_outclk3_clk;
output pll_1_outclk4_clk;
input pll_1_reset_reset;
output pll_2_outclk0_clk;
output pll_2_outclk1_clk;
output pll_2_outclk2_clk;
output pll_2_outclk3_clk;
input pll_2_reset_reset;
input reset_reset_n;
endmodule

54
common/pll/pll_generation.rpt Normal file
View File

@@ -0,0 +1,54 @@
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --block-symbol-file --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll --family="Cyclone V" --part=5CSEBA6U23I7
Progress: Loading common/pll.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 17.1]
Progress: Parameterizing module clk_0
Progress: Adding pll_0 [altera_pll 17.1]
Progress: Parameterizing module pll_0
Progress: Adding pll_1 [altera_pll 17.1]
Progress: Parameterizing module pll_1
Progress: Adding pll_2 [altera_pll 17.1]
Progress: Parameterizing module pll_2
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --synthesis=VHDL --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll/synthesis --family="Cyclone V" --part=5CSEBA6U23I7
Progress: Loading common/pll.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 17.1]
Progress: Parameterizing module clk_0
Progress: Adding pll_0 [altera_pll 17.1]
Progress: Parameterizing module pll_0
Progress: Adding pll_1 [altera_pll 17.1]
Progress: Parameterizing module pll_1
Progress: Adding pll_2 [altera_pll 17.1]
Progress: Parameterizing module pll_2
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
Info: pll: Generating pll "pll" for QUARTUS_SYNTH
Info: pll_0: "pll" instantiated altera_pll "pll_0"
Info: pll_1: "pll" instantiated altera_pll "pll_1"
Info: pll_2: "pll" instantiated altera_pll "pll_2"
Info: pll: Done "pll" with 4 modules, 7 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

54
common/pll/pll_generation_previous.rpt Normal file
View File

@@ -0,0 +1,54 @@
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --block-symbol-file --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll --family="Cyclone V" --part=5CSEBA6U23I7
Progress: Loading common/pll.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 17.1]
Progress: Parameterizing module clk_0
Progress: Adding pll_0 [altera_pll 17.1]
Progress: Parameterizing module pll_0
Progress: Adding pll_1 [altera_pll 17.1]
Progress: Parameterizing module pll_1
Progress: Adding pll_2 [altera_pll 17.1]
Progress: Parameterizing module pll_2
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --synthesis=VHDL --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll/synthesis --family="Cyclone V" --part=5CSEBA6U23I7
Progress: Loading common/pll.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 17.1]
Progress: Parameterizing module clk_0
Progress: Adding pll_0 [altera_pll 17.1]
Progress: Parameterizing module pll_0
Progress: Adding pll_1 [altera_pll 17.1]
Progress: Parameterizing module pll_1
Progress: Adding pll_2 [altera_pll 17.1]
Progress: Parameterizing module pll_2
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
Info: pll: Generating pll "pll" for QUARTUS_SYNTH
Info: pll_0: "pll" instantiated altera_pll "pll_0"
Info: pll_1: "pll" instantiated altera_pll "pll_1"
Info: pll_2: "pll" instantiated altera_pll "pll_2"
Info: pll: Done "pll" with 4 modules, 7 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

24
common/pll/pll_inst.v Normal file
View File

@@ -0,0 +1,24 @@
pll u0 (
.clk_clk (<connected-to-clk_clk>), // clk.clk
.pll_0_outclk1_clk (<connected-to-pll_0_outclk1_clk>), // pll_0_outclk1.clk
.pll_0_outclk2_clk (<connected-to-pll_0_outclk2_clk>), // pll_0_outclk2.clk
.pll_0_outclk3_clk (<connected-to-pll_0_outclk3_clk>), // pll_0_outclk3.clk
.pll_0_outclk4_clk (<connected-to-pll_0_outclk4_clk>), // pll_0_outclk4.clk
.pll_0_outclk5_clk (<connected-to-pll_0_outclk5_clk>), // pll_0_outclk5.clk
.pll_0_outclk6_clk (<connected-to-pll_0_outclk6_clk>), // pll_0_outclk6.clk
.pll_0_refclk_clk (<connected-to-pll_0_refclk_clk>), // pll_0_refclk.clk
.pll_0_reset_reset (<connected-to-pll_0_reset_reset>), // pll_0_reset.reset
.pll_1_outclk0_clk (<connected-to-pll_1_outclk0_clk>), // pll_1_outclk0.clk
.pll_1_outclk1_clk (<connected-to-pll_1_outclk1_clk>), // pll_1_outclk1.clk
.pll_1_outclk2_clk (<connected-to-pll_1_outclk2_clk>), // pll_1_outclk2.clk
.pll_1_outclk3_clk (<connected-to-pll_1_outclk3_clk>), // pll_1_outclk3.clk
.pll_1_outclk4_clk (<connected-to-pll_1_outclk4_clk>), // pll_1_outclk4.clk
.pll_1_reset_reset (<connected-to-pll_1_reset_reset>), // pll_1_reset.reset
.pll_2_outclk0_clk (<connected-to-pll_2_outclk0_clk>), // pll_2_outclk0.clk
.pll_2_outclk1_clk (<connected-to-pll_2_outclk1_clk>), // pll_2_outclk1.clk
.pll_2_outclk2_clk (<connected-to-pll_2_outclk2_clk>), // pll_2_outclk2.clk
.pll_2_outclk3_clk (<connected-to-pll_2_outclk3_clk>), // pll_2_outclk3.clk
.pll_2_reset_reset (<connected-to-pll_2_reset_reset>), // pll_2_reset.reset
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
);

51
common/pll/pll_inst.vhd Normal file
View File

@@ -0,0 +1,51 @@
component pll is
port (
clk_clk : in std_logic := 'X'; -- clk
pll_0_outclk1_clk : out std_logic; -- clk
pll_0_outclk2_clk : out std_logic; -- clk
pll_0_outclk3_clk : out std_logic; -- clk
pll_0_outclk4_clk : out std_logic; -- clk
pll_0_outclk5_clk : out std_logic; -- clk
pll_0_outclk6_clk : out std_logic; -- clk
pll_0_refclk_clk : in std_logic := 'X'; -- clk
pll_0_reset_reset : in std_logic := 'X'; -- reset
pll_1_outclk0_clk : out std_logic; -- clk
pll_1_outclk1_clk : out std_logic; -- clk
pll_1_outclk2_clk : out std_logic; -- clk
pll_1_outclk3_clk : out std_logic; -- clk
pll_1_outclk4_clk : out std_logic; -- clk
pll_1_reset_reset : in std_logic := 'X'; -- reset
pll_2_outclk0_clk : out std_logic; -- clk
pll_2_outclk1_clk : out std_logic; -- clk
pll_2_outclk2_clk : out std_logic; -- clk
pll_2_outclk3_clk : out std_logic; -- clk
pll_2_reset_reset : in std_logic := 'X'; -- reset
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component pll;
u0 : component pll
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pll_0_outclk1_clk => CONNECTED_TO_pll_0_outclk1_clk, -- pll_0_outclk1.clk
pll_0_outclk2_clk => CONNECTED_TO_pll_0_outclk2_clk, -- pll_0_outclk2.clk
pll_0_outclk3_clk => CONNECTED_TO_pll_0_outclk3_clk, -- pll_0_outclk3.clk
pll_0_outclk4_clk => CONNECTED_TO_pll_0_outclk4_clk, -- pll_0_outclk4.clk
pll_0_outclk5_clk => CONNECTED_TO_pll_0_outclk5_clk, -- pll_0_outclk5.clk
pll_0_outclk6_clk => CONNECTED_TO_pll_0_outclk6_clk, -- pll_0_outclk6.clk
pll_0_refclk_clk => CONNECTED_TO_pll_0_refclk_clk, -- pll_0_refclk.clk
pll_0_reset_reset => CONNECTED_TO_pll_0_reset_reset, -- pll_0_reset.reset
pll_1_outclk0_clk => CONNECTED_TO_pll_1_outclk0_clk, -- pll_1_outclk0.clk
pll_1_outclk1_clk => CONNECTED_TO_pll_1_outclk1_clk, -- pll_1_outclk1.clk
pll_1_outclk2_clk => CONNECTED_TO_pll_1_outclk2_clk, -- pll_1_outclk2.clk
pll_1_outclk3_clk => CONNECTED_TO_pll_1_outclk3_clk, -- pll_1_outclk3.clk
pll_1_outclk4_clk => CONNECTED_TO_pll_1_outclk4_clk, -- pll_1_outclk4.clk
pll_1_reset_reset => CONNECTED_TO_pll_1_reset_reset, -- pll_1_reset.reset
pll_2_outclk0_clk => CONNECTED_TO_pll_2_outclk0_clk, -- pll_2_outclk0.clk
pll_2_outclk1_clk => CONNECTED_TO_pll_2_outclk1_clk, -- pll_2_outclk1.clk
pll_2_outclk2_clk => CONNECTED_TO_pll_2_outclk2_clk, -- pll_2_outclk2.clk
pll_2_outclk3_clk => CONNECTED_TO_pll_2_outclk3_clk, -- pll_2_outclk3.clk
pll_2_reset_reset => CONNECTED_TO_pll_2_reset_reset, -- pll_2_reset.reset
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);

13433
common/pll/synthesis/pll.debuginfo Normal file
View File

File diff suppressed because it is too large Load Diff

987
common/pll/synthesis/pll.qip Normal file
View File

@@ -0,0 +1,987 @@
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "pll" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../pll.sopcinfo"]
set_global_assignment -entity "pll" -library "pll" -name SLD_INFO "QSYS_NAME pll HAS_SOPCINFO 1 GENERATION_ID 1544470692"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../pll.cmp"]
set_global_assignment -library "pll" -name SLD_FILE [file join $::quartus(qip_path) "pll.debuginfo"]
set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "SYSTEM"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../../pll.qsys"]
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "cGxs"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU0NDQ3MDY5Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8y"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MzEuMQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTAy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MzYuMDAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjUuMTc1::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTI2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MzEuNTAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTcuNzM0NDc1::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTc4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MjUuNTY4NjI3IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzU4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MzEuMDk5OTk4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjUuMTc2MTg4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTcuODIxMzQ2IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::OC44NjA4OTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Niw2LDEsMSxmYWxzZSxmYWxzZSxmYWxzZSxmYWxzZSwyNiwyNSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMyLDMxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsNDUsNDQsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw5MCw4OSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDEsMzAsMjAwMCwxNTg2LjA5OTgwMSBNSHosMTY4MTA3MDM2NixnY2xrLGdsYixmYl8xLHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8x"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTYuNzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NDA2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjguMzc1::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::ODEy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTQuMTg3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTYyNA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzI0OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NjQ5Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTYuNzQ4NzY4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjguMzc0Mzg0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTQuMTg3MTkyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::Ny4wOTM1OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::My41NDY3OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NDUsNDUsMTUsMTQsZmFsc2UsZmFsc2UsZmFsc2UsdHJ1ZSw3LDcsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTQsMTQsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMjgsMjgsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNTYsNTYsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTEyLDExMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDc5NC40ODI3NTggTUh6LDEsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8w"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::OA==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::OA==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjU2LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MTIwLjAwMDAwMCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NjQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MzIuNTMzMzI0IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NDg=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::OC4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::OTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::NC4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MTky::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::Mi4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::Mzg0::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MS4w::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjU1Ljk5OTg3MiBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTA5LjcxNDI1NyBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NjMuOTk5OTgxIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MzEuOTk5OTg5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MTUuOTk5OTk0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::Ny45OTk5OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::My45OTk5OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MS45OTk5OTkgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTUgSGkgRGl2aWRlLEMtQ291bnRlci01IExvdyBEaXZpZGUsQy1Db3VudGVyLTUgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci01IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTUgSW5wdXQgU291cmNlLEMtQ291bnRlci01IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTUgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTYgSGkgRGl2aWRlLEMtQ291bnRlci02IExvdyBEaXZpZGUsQy1Db3VudGVyLTYgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci02IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTYgSW5wdXQgU291cmNlLEMtQ291bnRlci02IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTYgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTcgSGkgRGl2aWRlLEMtQ291bnRlci03IExvdyBEaXZpZGUsQy1Db3VudGVyLTcgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci03IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTcgSW5wdXQgU291cmNlLEMtQ291bnRlci03IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTcgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OCw3LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDIsMSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDQsMywxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDYsNiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMiwxMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyNCwyNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw0OCw0OCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw5Niw5NiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxOTIsMTkyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCw3NjcuOTk5NjcxIE1IeiwxNTQ2MTU5OTY2LGdjbGssZ2xiLGZiXzEscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -library "pll" -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.qip"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.qip"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.qip"]
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_ENV "Qsys"

119
common/pll/synthesis/pll.vhd Normal file
View File

@@ -0,0 +1,119 @@
-- pll.vhd
-- Generated using ACDS version 17.1 593
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pll is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pll_0_outclk1_clk : out std_logic; -- pll_0_outclk1.clk
pll_0_outclk2_clk : out std_logic; -- pll_0_outclk2.clk
pll_0_outclk3_clk : out std_logic; -- pll_0_outclk3.clk
pll_0_outclk4_clk : out std_logic; -- pll_0_outclk4.clk
pll_0_outclk5_clk : out std_logic; -- pll_0_outclk5.clk
pll_0_outclk6_clk : out std_logic; -- pll_0_outclk6.clk
pll_0_refclk_clk : in std_logic := '0'; -- pll_0_refclk.clk
pll_0_reset_reset : in std_logic := '0'; -- pll_0_reset.reset
pll_1_outclk0_clk : out std_logic; -- pll_1_outclk0.clk
pll_1_outclk1_clk : out std_logic; -- pll_1_outclk1.clk
pll_1_outclk2_clk : out std_logic; -- pll_1_outclk2.clk
pll_1_outclk3_clk : out std_logic; -- pll_1_outclk3.clk
pll_1_outclk4_clk : out std_logic; -- pll_1_outclk4.clk
pll_1_reset_reset : in std_logic := '0'; -- pll_1_reset.reset
pll_2_outclk0_clk : out std_logic; -- pll_2_outclk0.clk
pll_2_outclk1_clk : out std_logic; -- pll_2_outclk1.clk
pll_2_outclk2_clk : out std_logic; -- pll_2_outclk2.clk
pll_2_outclk3_clk : out std_logic; -- pll_2_outclk3.clk
pll_2_reset_reset : in std_logic := '0'; -- pll_2_reset.reset
reset_reset_n : in std_logic := '0' -- reset.reset_n
);
end entity pll;
architecture rtl of pll is
component pll_pll_0 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
outclk_2 : out std_logic; -- clk
outclk_3 : out std_logic; -- clk
outclk_4 : out std_logic; -- clk
outclk_5 : out std_logic; -- clk
outclk_6 : out std_logic; -- clk
outclk_7 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll_pll_0;
component pll_pll_1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
outclk_2 : out std_logic; -- clk
outclk_3 : out std_logic; -- clk
outclk_4 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll_pll_1;
component pll_pll_2 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
outclk_2 : out std_logic; -- clk
outclk_3 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll_pll_2;
signal pll_0_outclk0_clk : std_logic; -- pll_0:outclk_0 -> [pll_1:refclk, pll_2:refclk]
begin
pll_0 : component pll_pll_0
port map (
refclk => pll_0_refclk_clk, -- refclk.clk
rst => pll_0_reset_reset, -- reset.reset
outclk_0 => pll_0_outclk0_clk, -- outclk0.clk
outclk_1 => pll_0_outclk1_clk, -- outclk1.clk
outclk_2 => pll_0_outclk2_clk, -- outclk2.clk
outclk_3 => pll_0_outclk3_clk, -- outclk3.clk
outclk_4 => pll_0_outclk4_clk, -- outclk4.clk
outclk_5 => pll_0_outclk5_clk, -- outclk5.clk
outclk_6 => pll_0_outclk6_clk, -- outclk6.clk
outclk_7 => open, -- outclk7.clk
locked => open -- (terminated)
);
pll_1 : component pll_pll_1
port map (
refclk => pll_0_outclk0_clk, -- refclk.clk
rst => pll_1_reset_reset, -- reset.reset
outclk_0 => pll_1_outclk0_clk, -- outclk0.clk
outclk_1 => pll_1_outclk1_clk, -- outclk1.clk
outclk_2 => pll_1_outclk2_clk, -- outclk2.clk
outclk_3 => pll_1_outclk3_clk, -- outclk3.clk
outclk_4 => pll_1_outclk4_clk, -- outclk4.clk
locked => open -- (terminated)
);
pll_2 : component pll_pll_2
port map (
refclk => pll_0_outclk0_clk, -- refclk.clk
rst => pll_2_reset_reset, -- reset.reset
outclk_0 => pll_2_outclk0_clk, -- outclk0.clk
outclk_1 => pll_2_outclk1_clk, -- outclk1.clk
outclk_2 => pll_2_outclk2_clk, -- outclk2.clk
outclk_3 => pll_2_outclk3_clk, -- outclk3.clk
locked => open -- (terminated)
);
end architecture rtl; -- of pll

4
common/pll/synthesis/submodules/pll_pll_0.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"

108
common/pll/synthesis/submodules/pll_pll_0.v Normal file
View File

@@ -0,0 +1,108 @@
`timescale 1ns/10ps
module pll_pll_0(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'outclk4'
output wire outclk_4,
// interface 'outclk5'
output wire outclk_5,
// interface 'outclk6'
output wire outclk_6,
// interface 'outclk7'
output wire outclk_7,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(8),
.output_clock_frequency0("255.999872 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("109.714257 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("63.999981 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("31.999989 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("15.999994 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("7.999996 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("3.999998 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("1.999999 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_7, outclk_6, outclk_5, outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

4
common/pll/synthesis/submodules/pll_pll_1.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"

99
common/pll/synthesis/submodules/pll_pll_1.v Normal file
View File

@@ -0,0 +1,99 @@
`timescale 1ns/10ps
module pll_pll_1(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'outclk4'
output wire outclk_4,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("256.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(5),
.output_clock_frequency0("56.748768 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("28.374384 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("14.187192 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("7.093596 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("3.546798 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

4
common/pll/synthesis/submodules/pll_pll_2.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"

96
common/pll/synthesis/submodules/pll_pll_2.v Normal file
View File

@@ -0,0 +1,96 @@
`timescale 1ns/10ps
module pll_pll_2(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("256.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(4),
.output_clock_frequency0("31.099998 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("25.176188 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("17.821346 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("8.860892 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

172
common/spi_master.vhd Normal file
View File

@@ -0,0 +1,172 @@
--------------------------------------------------------------------------------
--
-- FileName: spi_master.vhd
-- Dependencies: none
-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 7/23/2010 Scott Larson
-- Initial Public Release
-- Version 1.1 4/11/2013 Scott Larson
-- Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY spi_master IS
GENERIC(
slaves : INTEGER := 4; --number of spi slaves
d_width : INTEGER := 2); --data bus width
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
enable : IN STD_LOGIC; --initiate transaction
cpol : IN STD_LOGIC; --spi clock polarity
cpha : IN STD_LOGIC; --spi clock phase
cont : IN STD_LOGIC; --continuous mode command
clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
addr : IN INTEGER; --address of slave
tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
miso : IN STD_LOGIC; --master in, slave out
sclk : BUFFER STD_LOGIC; --spi clock
ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
mosi : OUT STD_LOGIC; --master out, slave in
busy : OUT STD_LOGIC; --busy / data ready signal
rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
END spi_master;
ARCHITECTURE logic OF spi_master IS
TYPE machine IS(ready, execute); --state machine data type
SIGNAL state : machine; --current state
SIGNAL slave : INTEGER; --slave selected for current transaction
SIGNAL clk_ratio : INTEGER; --current clk_div
SIGNAL count : INTEGER; --counter to trigger sclk from system clock
SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1; --count spi clock toggles
SIGNAL assert_data : STD_LOGIC; --'1' is tx sclk toggle, '0' is rx sclk toggle
SIGNAL continue : STD_LOGIC; --flag to continue transaction
SIGNAL rx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
SIGNAL tx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2; --last rx data bit location
BEGIN
PROCESS(clock, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset system
busy <= '1'; --set busy signal
ss_n <= (OTHERS => '1'); --deassert all slave select lines
mosi <= '0'; --set master out to high impedance
rx_data <= (OTHERS => '0'); --clear receive data port
state <= ready; --go to ready state when reset is exited
ELSIF(clock'EVENT AND clock = '1') THEN
CASE state IS --state machine
WHEN ready =>
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave select outputs high
mosi <= '0'; --set mosi output high impedance
continue <= '0'; --clear continue flag
--user input to initiate transaction
IF(enable = '1') THEN
busy <= '1'; --set busy signal
IF(addr < slaves) THEN --check for valid slave address
slave <= addr; --clock in current slave selection if valid
ELSE
slave <= 0; --set to first slave if not valid
END IF;
IF(clk_div = 0) THEN --check for valid spi speed
clk_ratio <= 1; --set to maximum speed if zero
count <= 1; --initiate system-to-spi clock counter
ELSE
clk_ratio <= clk_div; --set to input selection if valid
count <= clk_div; --initiate system-to-spi clock counter
END IF;
sclk <= cpol; --set spi clock polarity
assert_data <= NOT cpha; --set spi clock phase
tx_buffer <= tx_data; --clock in data for transmit into buffer
clk_toggles <= 0; --initiate clock toggle counter
last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
state <= execute; --proceed to execute state
ELSE
state <= ready; --remain in ready state
END IF;
WHEN execute =>
busy <= '1'; --set busy signal
ss_n(slave) <= '0'; --set proper slave select output
--system clock to sclk ratio is met
IF(count = clk_ratio) THEN
count <= 1; --reset system-to-spi clock counter
assert_data <= NOT assert_data; --switch transmit/receive indicator
IF(clk_toggles = d_width*2 + 1) THEN
clk_toggles <= 0; --reset spi clock toggles counter
ELSE
clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
END IF;
--spi clock toggle needed
IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN
sclk <= NOT sclk; --toggle spi clock
END IF;
--receive spi clock toggle
IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN
rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
END IF;
--transmit spi clock toggle
IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN
mosi <= tx_buffer(d_width-1); --clock out data bit
tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
END IF;
--last data receive, but continue
IF(clk_toggles = last_bit_rx AND cont = '1') THEN
tx_buffer <= tx_data; --reload transmit buffer
clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
continue <= '1'; --set continue flag
END IF;
--normal end of transaction, but continue
IF(continue = '1') THEN
continue <= '0'; --clear continue flag
busy <= '0'; --clock out signal that first receive data is ready
rx_data <= rx_buffer; --clock out received data to output port
END IF;
--end of transaction
IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave selects high
mosi <= '0'; --set mosi output high impedance
rx_data <= rx_buffer; --clock out received data to output port
state <= ready; --return to ready state
ELSE --not end of transaction
state <= execute; --remain in execute state
END IF;
ELSE --system clock to sclk ratio not met
count <= count + 1; --increment counter
state <= execute; --remain in execute state
END IF;
END CASE;
END IF;
END PROCESS;
END logic;

4
common/submodules/pll_pll_0.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"

108
common/submodules/pll_pll_0.v Normal file
View File

@@ -0,0 +1,108 @@
`timescale 1ns/10ps
module pll_pll_0(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'outclk4'
output wire outclk_4,
// interface 'outclk5'
output wire outclk_5,
// interface 'outclk6'
output wire outclk_6,
// interface 'outclk7'
output wire outclk_7,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(8),
.output_clock_frequency0("255.999872 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("109.714257 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("63.999981 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("31.999989 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("15.999994 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("7.999996 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("3.999998 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("1.999999 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_7, outclk_6, outclk_5, outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

4
common/submodules/pll_pll_1.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"

99
common/submodules/pll_pll_1.v Normal file
View File

@@ -0,0 +1,99 @@
`timescale 1ns/10ps
module pll_pll_1(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'outclk4'
output wire outclk_4,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("256.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(5),
.output_clock_frequency0("56.748768 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("28.374384 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("14.187192 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("7.093596 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("3.546798 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

4
common/submodules/pll_pll_2.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"

96
common/submodules/pll_pll_2.v Normal file
View File

@@ -0,0 +1,96 @@
`timescale 1ns/10ps
module pll_pll_2(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("256.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(4),
.output_clock_frequency0("31.099998 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("25.176188 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("17.821346 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("8.860892 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

BIN
common/sysrom.dump Executable file
View File

Binary file not shown.

1976
common/video.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

1981
common/video.vhd.sav Normal file
View File

File diff suppressed because it is too large Load Diff

125
common/z8420/Interrupt.vhd Normal file
View File

@@ -0,0 +1,125 @@
--
-- Interrupt.vhd
--
-- Z80 Daisy-Chain Interrupt Logic for FPGA
--
-- Nibbles Lab. 2013-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Interrupt is
Port (
-- System Signal
RESET : in std_logic;
-- CPU Signals
DI : in std_logic_vector(7 downto 0);
IORQ_n : in std_logic; -- same as Z80
RD_n : in std_logic; -- same as Z80
M1_n : in std_logic; -- same as Z80
IEI : in std_logic; -- same as Z80
IEO : out std_logic; -- same as Z80
INTO_n : out std_logic;
-- Control Signals
VECTEN : out std_logic;
INTI : in std_logic;
INTEN : in std_logic
);
end Interrupt;
architecture Behavioral of Interrupt is
-----------------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------------
signal IREQ : std_logic;
signal IRES : std_logic;
signal INTR : std_logic;
signal IAUTH : std_logic;
signal AUTHRES : std_logic;
signal IED1 : std_logic;
signal IED2 : std_logic;
signal ICB : std_logic;
signal I4D : std_logic;
signal FETCH : std_logic;
signal INTA : std_logic;
signal IENB : std_logic;
signal iINT : std_logic;
signal iIEO : std_logic;
begin
--
-- External signals
--
INTO_n <= iINT;
IEO <= iIEO;
--
-- Internal signals
--
iINT <= '0' when IEI='1' and IREQ='1' and IAUTH='0' else '1';
iIEO <= not (((not IED1) and IREQ) or IAUTH or (not IEI));
INTA <= ((not M1_n) and (not IORQ_n) and IEI);
AUTHRES <= RESET or (IEI and IED2 and I4D);
FETCH <= M1_n or RD_n;
IRES <= RESET or INTA;
INTR <= M1_n and (INTI and INTEN);
VECTEN <= '1' when INTA='1' and IEI='1' and IAUTH='1' else '0';
--
-- Keep Interrupt Request
--
process( IRES, INTR ) begin
if IRES='1' then
IREQ <= '0';
elsif INTR'event and INTR='1' then
IREQ <= '1';
end if;
end process;
--
-- Interrupt Authentication
--
process( AUTHRES, INTA ) begin
if AUTHRES='1' then
IAUTH <= '0';
elsif INTA'event and INTA='1' then
IAUTH <= IREQ;
end if;
end process;
--
-- Fetch 'RETI'
--
process( RESET, FETCH ) begin
if RESET='1' then
IED1 <= '0';
IED2 <= '0';
ICB <= '0';
I4D <= '0';
elsif FETCH'event and FETCH='1' then
IED2 <= IED1;
if DI=X"ED" and ICB='0' then
IED1 <= '1';
else
IED1 <= '0';
end if;
if DI=X"CB" then
ICB <= '1';
else
ICB <= '0';
end if;
if DI=X"4D" then
I4D <= IEI;
else
I4D <= '0';
end if;
end if;
end process;
end Behavioral;

246
common/z8420/z8420.vhd Normal file
View File

@@ -0,0 +1,246 @@
--
-- z8420.vhd
--
-- Zilog Z80PIO partiality compatible module
-- for MZ-80B on FPGA
--
-- Port A : Output, mode 0 only
-- Port B : Input, mode 0 only
--
-- Nibbles Lab. 2005-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity z8420 is
Port (
-- System
RST_n : in std_logic; -- Only Power On Reset
-- Z80 Bus Signals
CLK : in std_logic;
ENA : in std_logic;
BASEL : in std_logic;
CDSEL : in std_logic;
CE : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
IORQ_n : in std_logic;
M1_n : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
IEI : in std_logic;
IEO : out std_logic;
INT_n : out std_logic;
-- Port
A : out std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0)
);
end z8420;
architecture Behavioral of z8420 is
--
-- Port Selecter
--
signal SELAD : std_logic;
signal SELBD : std_logic;
signal SELAC : std_logic;
signal SELBC : std_logic;
--
-- Port Register
--
signal AREG : std_logic_vector(7 downto 0); -- Output Register (Port A)
signal DIRA : std_logic_vector(7 downto 0); -- Data Direction (Port A)
signal DDWA : std_logic; -- Prepare for Data Direction (Port A)
signal IMWA : std_logic_vector(7 downto 0); -- Interrupt Mask Word (Port A)
signal MFA : std_logic; -- Mask Follows (Port A)
signal VECTA : std_logic_vector(7 downto 0); -- Interrupt Vector (Port A)
signal MODEA : std_logic_vector(1 downto 0); -- Mode Word (Port A)
signal HLA : std_logic; -- High/Low (Port A)
signal AOA : std_logic; -- AND/OR (Port A)
signal DIRB : std_logic_vector(7 downto 0); -- Data Direction (Port B)
signal DDWB : std_logic; -- Prepare for Data Direction (Port B)
signal IMWB : std_logic_vector(7 downto 0); -- Interrupt Mask Word (Port B)
signal MFB : std_logic; -- Mask Follows (Port B)
signal VECTB : std_logic_vector(7 downto 0); -- Interrupt Vector (Port B)
signal MODEB : std_logic_vector(1 downto 0); -- Mode Word (Port B)
signal HLB : std_logic; -- High/Low (Port B)
signal AOB : std_logic; -- AND/OR (Port B)
--
-- Interrupt
--
--signal VECTENA : std_logic;
signal EIA : std_logic; -- Interrupt Enable (Port A)
--signal MINTA : std_logic_vector(7 downto 0);
--signal INTA : std_logic;
signal VECTENB : std_logic;
signal EIB : std_logic; -- Interrupt Enable (Port B)
signal MINTB : std_logic_vector(7 downto 0);
signal INTB : std_logic;
--
-- Components
--
component Interrupt is
Port (
-- System Signal
RESET : in std_logic;
-- CPU Signals
DI : in std_logic_vector(7 downto 0);
IORQ_n : in std_logic; -- same as Z80
RD_n : in std_logic; -- same as Z80
M1_n : in std_logic; -- same as Z80
IEI : in std_logic; -- same as Z80
IEO : out std_logic; -- same as Z80
INTO_n : out std_logic;
-- Control Signals
VECTEN : out std_logic;
INTI : in std_logic;
INTEN : in std_logic
);
end component;
begin
--
-- Instantiation
--
-- INT0 : Interrupt port map (
-- -- System Signal
-- RESET => RST_n,
-- -- CPU Signals
-- IORQ_n => IORQ_n,
-- RD_n => RD_n,
-- M1_n => M1_n,
-- IEI => IEI,
-- IEO => IEO,
-- INTO_n => INTA_n,
-- -- Control Signals
-- VECTEN => VECTENA,
-- INTI => INTA,
-- INTEN => EIA
-- );
INT1 : Interrupt port map (
-- System Signal
RESET => RST_n,
-- CPU Signals
DI => DI,
IORQ_n => IORQ_n,
RD_n => RD_n,
M1_n => M1_n,
IEI => IEI,
IEO => IEO,
INTO_n => INT_n, --INTB_n,
-- Control Signals
VECTEN => VECTENB,
INTI => INTB,
INTEN => EIB
);
--
-- Port select for Output
--
SELAD <= '1' when BASEL='0' and CDSEL='0' else '0';
SELBD <= '1' when BASEL='1' and CDSEL='0' else '0';
SELAC <= '1' when BASEL='0' and CDSEL='1' else '0';
SELBC <= '1' when BASEL='1' and CDSEL='1' else '0';
--
-- Output
--
process( RST_n, CLK, ENA ) begin
if RST_n='0' then
AREG <= (others=>'0');
MODEA <= "01";
DDWA <= '0';
MFA <= '0';
EIA <= '0';
-- B<=(others=>'0');
MODEB <= "01";
DDWB <= '0';
MFB <= '0';
EIB <= '0';
elsif CLK'event and CLK='0' then
if ENA = '1' then
if CE='0' and WR_n='0' then
if SELAD='1' then
AREG <=DI;
end if;
-- if SELBD='1' then
-- B<=DI;
-- end if;
if SELAC='1' then
if DDWA='1' then
DIRA <=DI;
DDWA <='0';
elsif MFA='1' then
IMWA <=DI;
MFA <='0';
elsif DI(0)='0' then
VECTA <=DI;
elsif DI(3 downto 0)="1111" then
MODEA <=DI(7 downto 6);
DDWA <=DI(7) and DI(6);
elsif DI(3 downto 0)="0111" then
MFA <=DI(4);
HLA <=DI(5);
AOA <=DI(6);
EIA <=DI(7);
elsif DI(3 downto 0)="0011" then
EIA <=DI(7);
end if;
end if;
if SELBC='1' then
if DDWB='1' then
DIRB <=DI;
DDWB <='0';
elsif MFB='1' then
IMWB <=DI;
MFB <='0';
elsif DI(0)='0' then
VECTB <=DI;
elsif DI(3 downto 0)="1111" then
MODEB <=DI(7 downto 6);
DDWB <=DI(7) and DI(6);
elsif DI(3 downto 0)="0111" then
MFB <=DI(4);
HLB <=DI(5);
AOB <=DI(6);
EIB <=DI(7);
elsif DI(3 downto 0)="0011" then
EIB <=DI(7);
end if;
end if;
end if;
end if;
end if;
end process;
A<=AREG;
--
-- Input select
--
DO<=AREG when RD_n='0' and CE='0' and SELAD='1' else
B when RD_n='0' and CE='0' and SELBD='1' else
-- VECTA when VECTENA='1' else
VECTB when VECTENB='1' else (others=>'0');
--
-- Interrupt select
--
INTMASK : for I in 0 to 7 generate
-- MINTA(I)<=(A(I) xnor HLA) and (not IMWA(I)) when AOA='0' else
-- (A(I) xnor HLA) or IMWA(I);
MINTB(I)<=(B(I) xnor HLB) and (not IMWB(I)) when AOB='0' else
(B(I) xnor HLB) or IMWB(I);
end generate INTMASK;
-- INTA<=MINTA(7) or MINTA(6) or MINTA(5) or MINTA(4) or MINTA(3) or MINTA(2) or MINTA(1) or MINTA(0) when AOA='0' else
-- MINTA(7) and MINTA(6) and MINTA(5) and MINTA(4) and MINTA(3) and MINTA(2) and MINTA(1) and MINTA(0);
INTB<=MINTB(7) or MINTB(6) or MINTB(5) or MINTB(4) or MINTB(3) or MINTB(2) or MINTB(1) or MINTB(0) when AOB='0' else
MINTB(7) and MINTB(6) and MINTB(5) and MINTB(4) and MINTB(3) and MINTB(2) and MINTB(1) and MINTB(0);
end Behavioral;

356
emu.sv Normal file
View File

@@ -0,0 +1,356 @@
//=======================================================================================================
//
// Name: emu.sv
// Created: June 2018
// Author(s): Philip Smart
// Description: Sharp MZ series compatible logic.
//
// This module is the main bridge between the emulator (sharpmz.vhd) and the MiSTer
// framework (hps_io.v/sys_top.v).
//
// Copyright: (C) 2018 Sorgelig
// (C) 2018 Philip Smart <philip.smart@net2net.org>
//
// History: June 2018 - Initial creation.
//
//=======================================================================================================
// This source file is free software: you can redistribute it and-or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//=======================================================================================================
module emu
(
//Master input clocks
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [44:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
output [7:0] VIDEO_ARX,
output [7:0] VIDEO_ARY,
// These video signals are defined in sys_top.v, via the video_mixer we output the video from the emulator onto these
// signals, which then get passed as follows:
// emu -> video_mixer -> vga_osd -> vga_out
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
output [7:0] LED_MB,
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
// input TAPE_IN,
// SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
// ,output SDRAM_CLK,
// output SDRAM_CKE,
// output [12:0] SDRAM_A,
// output [1:0] SDRAM_BA,
// inout [15:0] SDRAM_DQ,
// output SDRAM_DQML,
// output SDRAM_DQMH,
// output SDRAM_nCS,
// output SDRAM_nCAS,
// output SDRAM_nRAS,
// output SDRAM_nWE
input UART_RX,
output UART_TX
);
//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
assign LED_USER = ioctl_download;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3;
wire [2:0] scale = status[4:2];
// Menu is handled in the MiSTer c++ program.
//
`include "build_id.v"
localparam CONF_STR =
{
"SHARP MZ SERIES;;",
"J,Fire;",
"V,v1.02.",`BUILD_DATE
};
///////////////// CLOCKS ////////////////////////
wire clk_sys;
///////////////// HPS ///////////////////////////
wire [31:0] status;
wire [1:0] buttons;
wire [10:0] ps2_key;
wire [24:0] ps2_mouse;
wire ioctl_download;
wire ioctl_upload;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire ioctl_rd;
wire [24:0] ioctl_addr;
wire [15:0] ioctl_dout;
wire [15:0] ioctl_din;
wire forced_scandoubler;
hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str(CONF_STR),
.buttons(buttons),
.status(status),
.forced_scandoubler(forced_scandoubler),
.ioctl_download(ioctl_download),
.ioctl_upload(ioctl_upload),
.ioctl_index(ioctl_index),
.ioctl_wr(ioctl_wr),
.ioctl_rd(ioctl_rd),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_din(ioctl_din),
.ioctl_wait(0),
.sd_conf(0),
.sd_ack_conf(),
//.ps2_kbd_led_use(0),
//.ps2_kbd_led_status(0),
.ps2_key(ps2_key),
.ps2_mouse(ps2_mouse)
// unused
//.joystick_0(),
//.joystick_1(),
//.new_vmode(),
//.img_mounted(),
//.img_readonly(),
//.img_size(),
//.sd_lba(),
//.sd_rd(),
//.sd_wr(),
//.sd_ack(),
//.sd_buff_addr(),
//.sd_buff_dout(),
//.sd_buff_din(),
//.sd_buff_wr(),
//.ps2_kbd_clk_out(),
//.ps2_kbd_data_out(),
//.ps2_kbd_clk_in(),
//.ps2_kbd_data_in(),
//.ps2_mouse_clk_out(),
//.ps2_mouse_data_out(),
//.ps2_mouse_data_in(),
//.ps2_mouse_clk_in(),
//.joystick_analog_0(),
//.joystick_analog_1(),
//.RTC(),
//.TIMESTAMP()
);
///////////////// RESET /////////////////////////
//wire reset = RESET | status[0] | buttons[1] | status[6] | ioctl_download;
wire reset = RESET;
wire warm_reset = status[0] | buttons[1]; //| ioctl_download;
//////////////// Machine ////////////////////////
wire [7:0] audio_l_emu;
wire [7:0] audio_r_emu;
assign AUDIO_L = {audio_l_emu,8'd0};
assign AUDIO_R = {audio_r_emu,8'd0};
assign AUDIO_S = 1;
assign AUDIO_MIX = 0;
wire clk_video_in;
wire [7:0] R_emu;
wire [7:0] G_emu;
wire [7:0] B_emu;
wire hblank_emu;
wire vblank_emu;
wire hsync_emu;
wire vsync_emu;
bridge sharp_mz
(
// Clocks Input to Emulator.
.clkmaster(CLK_50M),
// System clock.
.clksys(clk_sys),
// Clocks output by the emulator.
.clkvid(clk_video_in),
// Reset
.cold_reset(reset),
.warm_reset(warm_reset),
// LED on MB
.main_leds(LED_MB),
// PS2 via USB.
.ps2_key(ps2_key),
// VGA on IO daughter card.
.vga_hb_o(hblank_emu),
.vga_vb_o(vblank_emu),
.vga_hs_o(hsync_emu),
.vga_vs_o(vsync_emu),
.vga_r_o(R_emu),
.vga_g_o(G_emu),
.vga_b_o(B_emu),
// AUDIO on IO daughter card.
.audio_l_o(audio_l_emu),
.audio_r_o(audio_r_emu),
.uart_rx(UART_RX),
.uart_tx(UART_TX),
.sd_sck(SD_SCK),
.sd_mosi(SD_MOSI),
.sd_miso(SD_MISO),
.sd_cs(SD_CS),
.sd_cd(SD_CD),
// HPS Interface
.ioctl_download(ioctl_download), // HPS Downloading to FPGA.
.ioctl_upload(ioctl_upload), // HPS Uploading from FPGA.
.ioctl_clk(clk_sys), // HPS I/O Clock.
.ioctl_wr(ioctl_wr), // HPS Write Enable to FPGA.
.ioctl_rd(ioctl_rd), // HPS Read Enable from FPGA.
.ioctl_addr(ioctl_addr), // HPS Address in FPGA to write into.
.ioctl_dout(ioctl_dout), // HPS Data to be written into FPGA.
.ioctl_din(ioctl_din) // HPS Data to be read into HPS.
);
// If ce_pix is same as pixel clock, uncomment below and remove CE_PIXEL from .ce_pix_out below.
//
//assign CE_PIXEL=1;
//assign CLK_VIDEO = clk_sys;
assign CLK_VIDEO = clk_video_in;
assign CE_PIXEL = clk_video_in;
assign VGA_R = R_emu;
assign VGA_G = G_emu;
assign VGA_B = B_emu;
assign VGA_VS = vsync_emu;
assign VGA_HS = hsync_emu;
assign VGA_DE = ~(vblank_emu | hblank_emu);
//video_mixer #(.HALF_DEPTH(0)) video_mixer
//video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer
//(
// .clk_sys(clk_sys),
// .ce_pix(clk_video_in), // Video pixel clock from core.
// //.ce_pix_out(CE_PIXEL),
//
// .scanlines({scale == 4, scale == 3, scale == 2}),
// .scandoubler(scale || forced_scandoubler),
// .hq2x(scale==1),
//
// .mono(0),
//
// // Input signals into the mixer, originating from the emulator.
// .R(R_emu),
// .G(G_emu),
// .B(B_emu),
//
// // Positive pulses.
// .HSync(hsync_emu),
// .VSync(vsync_emu),
// .HBlank(hblank_emu),
// .VBlank(vblank_emu),
//
// .VGA_R(VGA_R),
// .VGA_G(VGA_G),
// .VGA_B(VGA_B),
// .VGA_VS(VGA_VS),
// .VGA_HS(VGA_HS),
// .VGA_DE(VGA_DE)
//
// // Outputs of the mixer are bound to the VGA_x signals defined in the sys_top module and passed into this module as parameters.
// // These signals then feed the vga_osd -> vga_out modules in systop.v
//);
// Uncomment below and comment out video_mixer to pass original signal to sys_top.v.
// To output original signal, edit sys_top.v and comment out vga_osd and vga_out, uncomment the assign statements.
//
//assign VGA_R = R_emu;
//assign VGA_G = G_emu;
//assign VGA_B = B_emu;
//assign VGA_HS = hsync_emu;
//assign VGA_VS = vsync_emu;
//assign VGA_DE = ~(vblank_emu | hblank_emu);
endmodule

451
ioctl.vhd.sav Normal file
View File

@@ -0,0 +1,451 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: ioctl.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series compatible logic IO Control.
--
-- This module is the IO control layer which provides io services to the emulation,
-- which at time of writing can come from the DE10 Nano HPS or the soft-core NEO430
-- microcontroller.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.config_pkg.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity ioctl is
port(
-------------------- Clock Input ----------------------------
clkmaster : in std_logic; -- Master Clock(50MHz)
clksys : out std_logic; -- System clock.
clkvid : out std_logic; -- Pixel base clock of video.
-------------------- Reset ----------------------------
cold_reset : in std_logic;
warm_reset : in std_logic;
-------------------- main_leds ----------------------------
main_leds : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
ps2_key : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
vga_hb_o : out std_logic; -- VGA Horizontal Blank
vga_vb_o : out std_logic; -- VGA Vertical Blank
vga_hs_o : out std_logic; -- VGA H_SYNC
vga_vs_o : out std_logic; -- VGA V_SYNC
vga_r_o : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
vga_g_o : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
vga_b_o : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
audio_l_o : out std_logic;
audio_r_o : out std_logic;
uart_rx : in std_logic;
uart_tx : out std_logic;
sd_sck : out std_logic;
sd_mosi : out std_logic;
sd_miso : in std_logic;
sd_cs : out std_logic;
sd_cd : out std_logic;
-------------------- HPS Interface ------------------------------
ioctl_download : in std_logic; -- HPS Downloading to FPGA.
ioctl_upload : in std_logic; -- HPS Uploading from FPGA.
ioctl_clk : in std_logic; -- HPS I/O Clock.
ioctl_wr : in std_logic; -- HPS Write Enable to FPGA.
ioctl_rd : in std_logic; -- HPS Read Enable from FPGA.
ioctl_addr : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
ioctl_dout : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
ioctl_din : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS.
);
end ioctl;
architecture rtl of ioctl is
--
-- Signals.
--
signal CON_CLKMASTER : std_logic;
signal CON_CLKSYS : std_logic;
signal CON_CLKVID : std_logic;
signal CON_CLKNEO : std_logic;
signal CON_COLD_RESET : std_logic;
signal CON_WARM_RESET : std_logic;
signal CON_MAIN_LEDS : std_logic_vector(7 downto 0);
signal CON_PS2_KEY : std_logic_vector(10 downto 0);
signal CON_VGA_HB_O : std_logic;
signal CON_VGA_VB_O : std_logic;
signal CON_VGA_HS_O : std_logic;
signal CON_VGA_VS_O : std_logic;
signal CON_VGA_R_O : std_logic_vector(7 downto 0);
signal CON_VGA_G_O : std_logic_vector(7 downto 0);
signal CON_VGA_B_O : std_logic_vector(7 downto 0);
signal CON_AUDIO_L_O : std_logic;
signal CON_AUDIO_R_O : std_logic;
signal CON_IOCTL_DOWNLOAD : std_logic;
signal CON_IOCTL_UPLOAD : std_logic;
signal CON_IOCTL_CLK : std_logic;
signal CON_IOCTL_WR : std_logic;
signal CON_IOCTL_RD : std_logic;
signal CON_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal CON_IOCTL_DOUT : std_logic_vector(15 downto 0);
signal CON_IOCTL_DIN : std_logic_vector(15 downto 0);
--
-- NEO430 Signals.
--
signal NEO_IOCTL_DOWNLOAD : std_logic;
signal NEO_IOCTL_UPLOAD : std_logic;
signal NEO_IOCTL_CLK : std_logic;
signal NEO_IOCTL_WR : std_logic;
signal NEO_IOCTL_RD : std_logic;
signal NEO_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal NEO_IOCTL_DOUT : std_logic_vector(15 downto 0);
signal NEO_IOCTL_DIN : std_logic_vector(15 downto 0);
signal NEO_IOCTL_SENSE : std_logic;
signal NEO_IOCTL_SELECT : std_logic;
--
--
--
signal CON_UART_TX : std_logic;
signal CON_UART_RX : std_logic;
signal CON_SPI_SCLK : std_logic;
signal CON_SPI_MOSI : std_logic;
signal CON_SPI_MISO : std_logic;
signal CON_SPI_CS : std_logic_vector(7 downto 0);
--
-- HPS Control.
--
signal MZ_IOCTL_DOWNLOAD : std_logic;
signal MZ_IOCTL_UPLOAD : std_logic;
signal MZ_IOCTL_CLK : std_logic;
signal MZ_IOCTL_WR : std_logic;
signal MZ_IOCTL_RD : std_logic;
signal MZ_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal MZ_IOCTL_DOUT : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_SYSROM : std_logic_vector(7 downto 0);
signal MZ_IOCTL_DIN_SYSRAM : std_logic_vector(7 downto 0);
signal MZ_IOCTL_DIN_VIDEO : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_MZ80C : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_MZ80B : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_MCTRL : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_CMT : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_KEY : std_logic_vector(15 downto 0);
signal MZ_IOCTL_WENROM : std_logic;
signal MZ_IOCTL_WENRAM : std_logic;
signal MZ_IOCTL_RENROM : std_logic;
signal MZ_IOCTL_RENRAM : std_logic;
--
-- Components
--
component sharpmz
port (
-------------------- Clock Input ----------------------------
CLKMASTER : in std_logic; -- Master Clock(50MHz)
CLKSYS : out std_logic; -- System clock.
CLKVID : out std_logic; -- Pixel base clock of video.
CLKNEO : out std_logic; -- Neo processor clock.
-------------------- Reset ----------------------------
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
-------------------- main_leds ----------------------------
MAIN_LEDS : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
VGA_HB_O : out std_logic; -- VGA Horizontal Blank
VGA_VB_O : out std_logic; -- VGA Vertical Blank
VGA_HS_O : out std_logic; -- VGA H_SYNC
VGA_VS_O : out std_logic; -- VGA V_SYNC
VGA_R_O : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
VGA_G_O : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
VGA_B_O : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
AUDIO_L_O : out std_logic;
AUDIO_R_O : out std_logic;
-------------------- HPS Interface ------------------------------
IOCTL_DOWNLOAD : in std_logic; -- Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- Uploading from FPGA.
IOCTL_CLK : in std_logic; -- I/O Clock.
IOCTL_WR : in std_logic; -- Write Enable to FPGA.
IOCTL_RD : in std_logic; -- Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0) -- Data to be read into HPS.
);
end component;
component neo430
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := false;-- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := false;-- implement CRC unit? (default=true)
CFU_USE : boolean := true; -- implement custom functions unit? (default=false)
PWM_USE : boolean := false;-- implement PWM controller?
TWI_USE : boolean := false;-- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- gpio --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(02 downto 0); -- pwm channels
-- serial com --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- IOCTL Bus --
ioctl_download : out std_logic; -- Downloading to FPGA.
ioctl_upload : out std_logic; -- Uploading from FPGA.
ioctl_clk : out std_logic; -- I/O Clock.
ioctl_wr : out std_logic; -- Write Enable to FPGA.
ioctl_rd : out std_logic; -- Read Enable from FPGA.
ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus.
ioctl_select : out std_logic; -- Enable CFU control over ioctl bus.
ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
ioctl_dout : out std_logic_vector(15 downto 0); -- Data to be written into FPGA.
ioctl_din : in std_logic_vector(15 downto 0); -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_dat_i : in std_logic_vector(31 downto 0); -- read data
wb_dat_o : out std_logic_vector(31 downto 0); -- write data
wb_we_o : out std_logic; -- read/write
wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_logic; -- strobe
wb_cyc_o : out std_logic; -- valid cycle
wb_ack_i : in std_logic; -- transfer acknowledge
-- interrupts --
irq_i : in std_logic; -- external interrupt request line
irq_ack_o : out std_logic -- external interrupt request acknowledge
);
end component;
begin
--
-- Instantiation
--
SHARPMZ_0 : sharpmz
port map (
-------------------- Clock Input ----------------------------
CLKMASTER => CON_CLKMASTER, -- Master Clock(50MHz)
CLKSYS => CON_CLKSYS, -- System clock.
CLKVID => CON_CLKVID, -- Pixel base clock of video.
CLKNEO => CON_CLKNEO, -- Neo Clock.
-------------------- ----------------------------
COLD_RESET => CON_COLD_RESET,
WARM_RESET => CON_WARM_RESET,
-------------------- ----------------------------
MAIN_LEDS => CON_MAIN_LEDS, -- main_leds Green[7:0]
-------------------- ----------------------------
PS2_KEY => CON_PS2_KEY, -- PS2 Key data.
-------------------- ----------------------------
VGA_HB_O => CON_VGA_HB_O, -- VGA Horizontal Blank
VGA_VB_O => CON_VGA_VB_O, -- VGA Vertical Blank
VGA_HS_O => CON_VGA_HS_O, -- VGA H_SYNC
VGA_VS_O => CON_VGA_VS_O, -- VGA V_SYNC
VGA_R_O => CON_VGA_R_O, -- VGA Red[3:0], [7:4] = 0
VGA_G_O => CON_VGA_G_O, -- VGA Green[3:0]
VGA_B_O => CON_VGA_B_O, -- VGA Blue[3:0]
-------------------- ------------------------------
AUDIO_L_O => CON_AUDIO_L_O,
AUDIO_R_O => CON_AUDIO_R_O,
-------------------- ------------------------------
IOCTL_DOWNLOAD => CON_IOCTL_DOWNLOAD, -- Downloading to FPGA.
IOCTL_UPLOAD => CON_IOCTL_UPLOAD, -- Uploading from FPGA.
IOCTL_CLK => CON_IOCTL_CLK, -- I/O Clock.
IOCTL_WR => CON_IOCTL_WR, -- Write Enable to FPGA.
IOCTL_RD => CON_IOCTL_RD, -- Read Enable from FPGA.
IOCTL_ADDR => CON_IOCTL_ADDR, -- Address in FPGA to write into.
IOCTL_DOUT => CON_IOCTL_DOUT, -- Data to be written into FPGA.
IOCTL_DIN => CON_IOCTL_DIN -- Data to be read into HPS.
);
-- If enabled, instantiate the local IO processor to provide IO and user interface services.
--
NEO430_ENABLE: if NEO_ENABLE = 1 generate
NEO430_0 : neo430
generic map (
-- general configuration --
CLOCK_SPEED => 64000000, -- main clock in Hz
IMEM_SIZE => 48*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => 12*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => x"0000", -- custom user code
-- module configuration --
DADD_USE => true, -- implement DADD instruction? (default=true)
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => false, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WDT? (default=true)
GPIO_USE => true, -- implement GPIO unit? (default=true)
TIMER_USE => true, -- implement timer? (default=true)
UART_USE => true, -- implement UART? (default=true)
CRC_USE => true, -- implement CRC unit? (default=true)
CFU_USE => true, -- implement custom functions unit? (default=false)
PWM_USE => true, -- implement PWM controller?
TWI_USE => true, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE => true, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => CON_CLKNEO, -- global clock, rising edge
rst_i => not (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async, low-active
-- gpio --
gpio_o => open, -- parallel output
gpio_i => X"0000", -- parallel input
-- pwm channels --
pwm_o => open, -- pwm channels
-- serial com --
uart_txd_o => CON_UART_TX, -- UART send data
uart_rxd_i => CON_UART_RX, -- UART receive data
spi_sclk_o => CON_SPI_SCLK, -- serial clock line
spi_mosi_o => CON_SPI_MOSI, -- serial data line out
spi_miso_i => CON_SPI_MISO, -- serial data line in
spi_cs_o => CON_SPI_CS, -- SPI CS 0..7
twi_sda_io => 'H', -- twi serial data line
twi_scl_io => 'H', -- twi serial clock line
-- IOCTL Bus --
ioctl_download => NEO_IOCTL_DOWNLOAD, -- Downloading to FPGA.
ioctl_upload => NEO_IOCTL_UPLOAD, -- Uploading from FPGA.
ioctl_clk => NEO_IOCTL_CLK, -- I/O Clock.
ioctl_wr => NEO_IOCTL_WR, -- Write Enable to FPGA.
ioctl_rd => NEO_IOCTL_RD, -- Read Enable from FPGA.
ioctl_sense => NEO_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
ioctl_select => NEO_IOCTL_SELECT, -- Enable CFU control over ioctl bus.
ioctl_addr => NEO_IOCTL_ADDR, -- Address in FPGA to write into.
ioctl_dout => NEO_IOCTL_DOUT, -- Data to be written into FPGA.
ioctl_din => NEO_IOCTL_DIN, -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o => open, -- address
wb_dat_i => (others => '0'), -- read data
wb_dat_o => open, -- write data
wb_we_o => open, -- read/write
wb_sel_o => open, -- byte enable
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- interrupts --
irq_i => '0', -- external interrupt request line
irq_ack_o => open -- external interrupt request acknowledge
);
end generate;
-- If the Neo430 IO Processor is disabled, set the signals to inactive.
--
NEO430_DISABLE: if NEO_ENABLE = 0 generate
NEO_IOCTL_DOWNLOAD <= '0';
NEO_IOCTL_UPLOAD <= '0';
NEO_IOCTL_CLK <= '0';
NEO_IOCTL_WR <= '0';
NEO_IOCTL_RD <= '0';
NEO_IOCTL_ADDR <= (others => '0');
NEO_IOCTL_DOUT <= (others => '0');
--NEO_IOCTL_DIN => open;
--NEO_IOCTL_SENSE => open;
NEO_IOCTL_SELECT <= '0';
end generate;
-- Assign signals from the emu onto local wires.
--
CON_CLKMASTER <= clkmaster;
clksys <= CON_CLKSYS;
clkvid <= CON_CLKVID;
CON_COLD_RESET <= cold_reset;
CON_WARM_RESET <= warm_reset;
main_leds <= CON_MAIN_LEDS;
CON_PS2_KEY <= ps2_key;
vga_hb_o <= CON_VGA_HB_O;
vga_vb_o <= CON_VGA_VB_O;
vga_hs_o <= CON_VGA_HS_O;
vga_vs_o <= CON_VGA_VS_O;
vga_r_o <= CON_VGA_R_O;
vga_g_o <= CON_VGA_G_O;
vga_b_o <= CON_VGA_B_O;
audio_l_o <= CON_AUDIO_L_O;
audio_r_o <= CON_AUDIO_R_O;
uart_tx <= CON_UART_TX;
CON_UART_RX <= uart_rx;
sd_sck <= CON_SPI_SCLK;
sd_mosi <= CON_SPI_MOSI;
CON_SPI_MISO <= sd_miso;
sd_cs <= CON_SPI_CS(0);
--
-- Multiplexer, default IO control to the HPS unless the NEO is enabled and selects.
-- The NEO430 first senses to ensure there is no activity on the bus, then takes control
--
CON_IOCTL_DOWNLOAD <= ioctl_download when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_DOWNLOAD;
CON_IOCTL_UPLOAD <= ioctl_upload when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_UPLOAD;
CON_IOCTL_CLK <= ioctl_clk when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_CLK;
CON_IOCTL_WR <= ioctl_wr when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_WR;
CON_IOCTL_RD <= ioctl_rd when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_RD;
CON_IOCTL_ADDR <= ioctl_addr when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_ADDR;
CON_IOCTL_DOUT <= ioctl_dout when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_DOUT;
ioctl_din <= CON_IOCTL_DIN when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_DIN;
NEO_IOCTL_SENSE <= ioctl_download or ioctl_upload or ioctl_wr or ioctl_rd;
end rtl;

451
ioctl_neo430.vhd Normal file
View File

@@ -0,0 +1,451 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: ioctl.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series compatible logic IO Control.
--
-- This module is the IO control layer which provides io services to the emulation,
-- which at time of writing can come from the DE10 Nano HPS or the soft-core NEO430
-- microcontroller.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.config_pkg.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity ioctl is
port(
-------------------- Clock Input ----------------------------
clkmaster : in std_logic; -- Master Clock(50MHz)
clksys : out std_logic; -- System clock.
clkvid : out std_logic; -- Pixel base clock of video.
-------------------- Reset ----------------------------
cold_reset : in std_logic;
warm_reset : in std_logic;
-------------------- main_leds ----------------------------
main_leds : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
ps2_key : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
vga_hb_o : out std_logic; -- VGA Horizontal Blank
vga_vb_o : out std_logic; -- VGA Vertical Blank
vga_hs_o : out std_logic; -- VGA H_SYNC
vga_vs_o : out std_logic; -- VGA V_SYNC
vga_r_o : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
vga_g_o : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
vga_b_o : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
audio_l_o : out std_logic;
audio_r_o : out std_logic;
uart_rx : in std_logic;
uart_tx : out std_logic;
sd_sck : out std_logic;
sd_mosi : out std_logic;
sd_miso : in std_logic;
sd_cs : out std_logic;
sd_cd : out std_logic;
-------------------- HPS Interface ------------------------------
ioctl_download : in std_logic; -- HPS Downloading to FPGA.
ioctl_upload : in std_logic; -- HPS Uploading from FPGA.
ioctl_clk : in std_logic; -- HPS I/O Clock.
ioctl_wr : in std_logic; -- HPS Write Enable to FPGA.
ioctl_rd : in std_logic; -- HPS Read Enable from FPGA.
ioctl_addr : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
ioctl_dout : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
ioctl_din : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS.
);
end ioctl;
architecture rtl of ioctl is
--
-- Signals.
--
signal CON_CLKMASTER : std_logic;
signal CON_CLKSYS : std_logic;
signal CON_CLKVID : std_logic;
signal CON_CLKNEO : std_logic;
signal CON_COLD_RESET : std_logic;
signal CON_WARM_RESET : std_logic;
signal CON_MAIN_LEDS : std_logic_vector(7 downto 0);
signal CON_PS2_KEY : std_logic_vector(10 downto 0);
signal CON_VGA_HB_O : std_logic;
signal CON_VGA_VB_O : std_logic;
signal CON_VGA_HS_O : std_logic;
signal CON_VGA_VS_O : std_logic;
signal CON_VGA_R_O : std_logic_vector(7 downto 0);
signal CON_VGA_G_O : std_logic_vector(7 downto 0);
signal CON_VGA_B_O : std_logic_vector(7 downto 0);
signal CON_AUDIO_L_O : std_logic;
signal CON_AUDIO_R_O : std_logic;
signal CON_IOCTL_DOWNLOAD : std_logic;
signal CON_IOCTL_UPLOAD : std_logic;
signal CON_IOCTL_CLK : std_logic;
signal CON_IOCTL_WR : std_logic;
signal CON_IOCTL_RD : std_logic;
signal CON_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal CON_IOCTL_DOUT : std_logic_vector(15 downto 0);
signal CON_IOCTL_DIN : std_logic_vector(15 downto 0);
--
-- NEO430 Signals.
--
signal NEO_IOCTL_DOWNLOAD : std_logic;
signal NEO_IOCTL_UPLOAD : std_logic;
signal NEO_IOCTL_CLK : std_logic;
signal NEO_IOCTL_WR : std_logic;
signal NEO_IOCTL_RD : std_logic;
signal NEO_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal NEO_IOCTL_DOUT : std_logic_vector(15 downto 0);
signal NEO_IOCTL_DIN : std_logic_vector(15 downto 0);
signal NEO_IOCTL_SENSE : std_logic;
signal NEO_IOCTL_SELECT : std_logic;
--
--
--
signal CON_UART_TX : std_logic;
signal CON_UART_RX : std_logic;
signal CON_SPI_SCLK : std_logic;
signal CON_SPI_MOSI : std_logic;
signal CON_SPI_MISO : std_logic;
signal CON_SPI_CS : std_logic_vector(7 downto 0);
--
-- HPS Control.
--
signal MZ_IOCTL_DOWNLOAD : std_logic;
signal MZ_IOCTL_UPLOAD : std_logic;
signal MZ_IOCTL_CLK : std_logic;
signal MZ_IOCTL_WR : std_logic;
signal MZ_IOCTL_RD : std_logic;
signal MZ_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal MZ_IOCTL_DOUT : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_SYSROM : std_logic_vector(7 downto 0);
signal MZ_IOCTL_DIN_SYSRAM : std_logic_vector(7 downto 0);
signal MZ_IOCTL_DIN_VIDEO : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_MZ80C : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_MZ80B : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_MCTRL : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_CMT : std_logic_vector(15 downto 0);
signal MZ_IOCTL_DIN_KEY : std_logic_vector(15 downto 0);
signal MZ_IOCTL_WENROM : std_logic;
signal MZ_IOCTL_WENRAM : std_logic;
signal MZ_IOCTL_RENROM : std_logic;
signal MZ_IOCTL_RENRAM : std_logic;
--
-- Components
--
component sharpmz
port (
-------------------- Clock Input ----------------------------
CLKMASTER : in std_logic; -- Master Clock(50MHz)
CLKSYS : out std_logic; -- System clock.
CLKVID : out std_logic; -- Pixel base clock of video.
CLKNEO : out std_logic; -- Neo processor clock.
-------------------- Reset ----------------------------
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
-------------------- main_leds ----------------------------
MAIN_LEDS : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
VGA_HB_O : out std_logic; -- VGA Horizontal Blank
VGA_VB_O : out std_logic; -- VGA Vertical Blank
VGA_HS_O : out std_logic; -- VGA H_SYNC
VGA_VS_O : out std_logic; -- VGA V_SYNC
VGA_R_O : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
VGA_G_O : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
VGA_B_O : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
AUDIO_L_O : out std_logic;
AUDIO_R_O : out std_logic;
-------------------- HPS Interface ------------------------------
IOCTL_DOWNLOAD : in std_logic; -- Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- Uploading from FPGA.
IOCTL_CLK : in std_logic; -- I/O Clock.
IOCTL_WR : in std_logic; -- Write Enable to FPGA.
IOCTL_RD : in std_logic; -- Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0) -- Data to be read into HPS.
);
end component;
component neo430
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := false;-- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := true; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- gpio --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(02 downto 0); -- pwm channels
-- serial com --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- IOCTL Bus --
ioctl_download : out std_logic; -- Downloading to FPGA.
ioctl_upload : out std_logic; -- Uploading from FPGA.
ioctl_clk : out std_logic; -- I/O Clock.
ioctl_wr : out std_logic; -- Write Enable to FPGA.
ioctl_rd : out std_logic; -- Read Enable from FPGA.
ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus.
ioctl_select : out std_logic; -- Enable CFU control over ioctl bus.
ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
ioctl_dout : out std_logic_vector(15 downto 0); -- Data to be written into FPGA.
ioctl_din : in std_logic_vector(15 downto 0); -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_dat_i : in std_logic_vector(31 downto 0); -- read data
wb_dat_o : out std_logic_vector(31 downto 0); -- write data
wb_we_o : out std_logic; -- read/write
wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_logic; -- strobe
wb_cyc_o : out std_logic; -- valid cycle
wb_ack_i : in std_logic; -- transfer acknowledge
-- interrupts --
irq_i : in std_logic; -- external interrupt request line
irq_ack_o : out std_logic -- external interrupt request acknowledge
);
end component;
begin
--
-- Instantiation
--
SHARPMZ_0 : sharpmz
port map (
-------------------- Clock Input ----------------------------
CLKMASTER => CON_CLKMASTER, -- Master Clock(50MHz)
CLKSYS => CON_CLKSYS, -- System clock.
CLKVID => CON_CLKVID, -- Pixel base clock of video.
CLKNEO => CON_CLKNEO, -- Neo Clock.
-------------------- ----------------------------
COLD_RESET => CON_COLD_RESET,
WARM_RESET => CON_WARM_RESET,
-------------------- ----------------------------
MAIN_LEDS => CON_MAIN_LEDS, -- main_leds Green[7:0]
-------------------- ----------------------------
PS2_KEY => CON_PS2_KEY, -- PS2 Key data.
-------------------- ----------------------------
VGA_HB_O => CON_VGA_HB_O, -- VGA Horizontal Blank
VGA_VB_O => CON_VGA_VB_O, -- VGA Vertical Blank
VGA_HS_O => CON_VGA_HS_O, -- VGA H_SYNC
VGA_VS_O => CON_VGA_VS_O, -- VGA V_SYNC
VGA_R_O => CON_VGA_R_O, -- VGA Red[3:0], [7:4] = 0
VGA_G_O => CON_VGA_G_O, -- VGA Green[3:0]
VGA_B_O => CON_VGA_B_O, -- VGA Blue[3:0]
-------------------- ------------------------------
AUDIO_L_O => CON_AUDIO_L_O,
AUDIO_R_O => CON_AUDIO_R_O,
-------------------- ------------------------------
IOCTL_DOWNLOAD => CON_IOCTL_DOWNLOAD, -- Downloading to FPGA.
IOCTL_UPLOAD => CON_IOCTL_UPLOAD, -- Uploading from FPGA.
IOCTL_CLK => CON_IOCTL_CLK, -- I/O Clock.
IOCTL_WR => CON_IOCTL_WR, -- Write Enable to FPGA.
IOCTL_RD => CON_IOCTL_RD, -- Read Enable from FPGA.
IOCTL_ADDR => CON_IOCTL_ADDR, -- Address in FPGA to write into.
IOCTL_DOUT => CON_IOCTL_DOUT, -- Data to be written into FPGA.
IOCTL_DIN => CON_IOCTL_DIN -- Data to be read into HPS.
);
-- If enabled, instantiate the local IO processor to provide IO and user interface services.
--
NEO430_ENABLE: if NEO_ENABLE = 1 generate
NEO430_0 : neo430
generic map (
-- general configuration --
CLOCK_SPEED => 64000000, -- main clock in Hz
IMEM_SIZE => 48*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => 12*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => x"0000", -- custom user code
-- module configuration --
DADD_USE => true, -- implement DADD instruction? (default=true)
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => false, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WDT? (default=true)
GPIO_USE => true, -- implement GPIO unit? (default=true)
TIMER_USE => true, -- implement timer? (default=true)
UART_USE => true, -- implement UART? (default=true)
CRC_USE => false, -- implement CRC unit? (default=true)
CFU_USE => false, -- implement custom functions unit? (default=false)
PWM_USE => true, -- implement PWM controller?
TWI_USE => false, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE => true, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => CON_CLKNEO, -- global clock, rising edge
rst_i => not (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async, low-active
-- gpio --
gpio_o => open, -- parallel output
gpio_i => X"0000", -- parallel input
-- pwm channels --
pwm_o => open, -- pwm channels
-- serial com --
uart_txd_o => CON_UART_TX, -- UART send data
uart_rxd_i => CON_UART_RX, -- UART receive data
spi_sclk_o => CON_SPI_SCLK, -- serial clock line
spi_mosi_o => CON_SPI_MOSI, -- serial data line out
spi_miso_i => CON_SPI_MISO, -- serial data line in
spi_cs_o => CON_SPI_CS, -- SPI CS 0..7
twi_sda_io => open, -- twi serial data line
twi_scl_io => open, -- twi serial clock line
-- IOCTL Bus --
ioctl_download => NEO_IOCTL_DOWNLOAD, -- Downloading to FPGA.
ioctl_upload => NEO_IOCTL_UPLOAD, -- Uploading from FPGA.
ioctl_clk => NEO_IOCTL_CLK, -- I/O Clock.
ioctl_wr => NEO_IOCTL_WR, -- Write Enable to FPGA.
ioctl_rd => NEO_IOCTL_RD, -- Read Enable from FPGA.
ioctl_sense => NEO_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
ioctl_select => NEO_IOCTL_SELECT, -- Enable CFU control over ioctl bus.
ioctl_addr => NEO_IOCTL_ADDR, -- Address in FPGA to write into.
ioctl_dout => NEO_IOCTL_DOUT, -- Data to be written into FPGA.
ioctl_din => NEO_IOCTL_DIN, -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o => open, -- address
wb_dat_i => (others => '0'), -- read data
wb_dat_o => open, -- write data
wb_we_o => open, -- read/write
wb_sel_o => open, -- byte enable
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- interrupts --
irq_i => '0', -- external interrupt request line
irq_ack_o => open -- external interrupt request acknowledge
);
end generate;
-- If the Neo430 IO Processor is disabled, set the signals to inactive.
--
NEO430_DISABLE: if NEO_ENABLE = 0 generate
NEO_IOCTL_DOWNLOAD <= '0';
NEO_IOCTL_UPLOAD <= '0';
NEO_IOCTL_CLK <= '0';
NEO_IOCTL_WR <= '0';
NEO_IOCTL_RD <= '0';
NEO_IOCTL_ADDR <= (others => '0');
NEO_IOCTL_DOUT <= (others => '0');
--NEO_IOCTL_DIN => open;
--NEO_IOCTL_SENSE => open;
NEO_IOCTL_SELECT <= '0';
end generate;
-- Assign signals from the emu onto local wires.
--
CON_CLKMASTER <= clkmaster;
clksys <= CON_CLKSYS;
clkvid <= CON_CLKVID;
CON_COLD_RESET <= cold_reset;
CON_WARM_RESET <= warm_reset;
main_leds <= CON_MAIN_LEDS;
CON_PS2_KEY <= ps2_key;
vga_hb_o <= CON_VGA_HB_O;
vga_vb_o <= CON_VGA_VB_O;
vga_hs_o <= CON_VGA_HS_O;
vga_vs_o <= CON_VGA_VS_O;
vga_r_o <= CON_VGA_R_O;
vga_g_o <= CON_VGA_G_O;
vga_b_o <= CON_VGA_B_O;
audio_l_o <= CON_AUDIO_L_O;
audio_r_o <= CON_AUDIO_R_O;
uart_tx <= CON_UART_TX;
CON_UART_RX <= uart_rx;
sd_sck <= CON_SPI_SCLK;
sd_mosi <= CON_SPI_MOSI;
CON_SPI_MISO <= sd_miso;
sd_cs <= CON_SPI_CS(0);
--
-- Multiplexer, default IO control to the HPS unless the NEO is enabled and selects.
-- The NEO430 first senses to ensure there is no activity on the bus, then takes control
--
CON_IOCTL_DOWNLOAD <= ioctl_download when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_DOWNLOAD;
CON_IOCTL_UPLOAD <= ioctl_upload when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_UPLOAD;
CON_IOCTL_CLK <= ioctl_clk when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_CLK;
CON_IOCTL_WR <= ioctl_wr when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_WR;
CON_IOCTL_RD <= ioctl_rd when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_RD;
CON_IOCTL_ADDR <= ioctl_addr when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_ADDR;
CON_IOCTL_DOUT <= ioctl_dout when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_DOUT;
ioctl_din <= CON_IOCTL_DIN when NEO_IOCTL_SELECT = '0'
else
NEO_IOCTL_DIN;
NEO_IOCTL_SENSE <= ioctl_download or ioctl_upload or ioctl_wr or ioctl_rd;
end rtl;

13
jtag.cdf Normal file
View File

@@ -0,0 +1,13 @@
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23I7) Path("output_files/") File("sharpmz-lite.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1392
jtag_uart_0.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

47
memory_hw.tcl Normal file
View File

@@ -0,0 +1,47 @@
# TCL File Generated by Component Editor 17.0
# Mon Jun 11 22:55:14 BST 2018
# DO NOT MODIFY
#
# memory "memory" v1.0
# 2018.06.11.22:55:14
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module memory
#
set_module_property DESCRIPTION ""
set_module_property NAME memory
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME memory
set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
#
# parameters
#
#
# display items
#

294
mz80b/cmt.vhd Normal file
View File

@@ -0,0 +1,294 @@
--
-- cmt.vhd
--
-- Sharp PWM Tape I/F and Pseudo-CMT module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2013-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cmt is
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Tape action interrupt
-- Z80 Bus
ZCLK : in std_logic;
-- ZA8 : in std_logic_vector(7 downto 0);
-- ZIWR_x : in std_logic;
-- ZDI : in std_logic_vector(7 downto 0);
-- ZDO : out std_logic_vector(7 downto 0);
-- Tape signals
T_END : out std_logic; -- Sense CMT(Motor on/off)
OPEN_x : in std_logic; -- Open
PLAY_x : in std_logic; -- Play
STOP_x : in std_logic; -- Stop
FF_x : in std_logic; -- Fast Foward
REW_x : in std_logic; -- Rewind
APSS_x : in std_logic; -- APSS
FFREW : in std_logic; -- FF/REW mode
FMOTOR : in std_logic; -- FF/REW start
FLATCH : in std_logic; -- FF/REW latch
WREADY : out std_logic; -- Write enable
TREADY : out std_logic; -- Tape exist
-- EXIN : in std_logic; -- CMT IN from I/O board
RDATA : out std_logic; -- to 8255
-- Status Signal
SCLK : in std_logic; -- Slow Clock(31.25kHz)
MZMODE : in std_logic; -- Hardware Mode
DMODE : in std_logic -- Display Mode
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end cmt;
architecture RTL of cmt is
--
-- Status
--
signal RPLBUF : std_logic_vector(2 downto 0);
signal REG_PL : std_logic;
signal RSTBUF : std_logic_vector(2 downto 0);
signal REJBUF : std_logic_vector(2 downto 0);
signal REG_EJ : std_logic;
signal RREBUF : std_logic_vector(2 downto 0);
signal REG_RE : std_logic;
signal RFFBUF : std_logic_vector(2 downto 0);
signal REG_FF : std_logic;
signal RASBUF : std_logic_vector(2 downto 0);
signal REG_AS : std_logic;
signal RLTBUF : std_logic_vector(2 downto 0);
signal RFMBUF : std_logic_vector(2 downto 0);
signal REG_RE_M : std_logic;
signal REG_FF_M : std_logic;
signal TAPE : std_logic;
signal WP : std_logic;
signal MOTOR : std_logic;
signal PBIT : std_logic;
signal RBYTE : std_logic_vector(15 downto 0);
signal PON : std_logic;
signal APSS : std_logic;
signal FA : std_logic;
--
-- Pulse Generator
--
signal POUT : std_logic;
signal PCNT : std_logic_vector(10 downto 0);
signal PBUSY : std_logic;
signal PEXT : std_logic_vector(4 downto 0);
----
---- Filters
----
--signal CNT3 : std_logic_vector(1 downto 0);
--signal PL_BTN : std_logic_vector(1 downto 0);
--signal ST_BTN : std_logic_vector(1 downto 0);
--signal T_BTN : std_logic;
----
---- Divider
----
--signal DIV : std_logic_vector(13 downto 0);
----
---- Registers for Z80
----
--signal MADR : std_logic_vector(15 downto 0);
--signal MBYTE : std_logic_vector(15 downto 0);
--signal MCMD : std_logic_vector(7 downto 0);
--signal STAT : std_logic_vector(7 downto 0);
--
-- Components
--
begin
--
-- HPS Bus
--
process( RST_n, CLK ) begin
if RST_n='0' then
WP <='0';
MOTOR <='0';
TAPE <='0';
REG_PL <='0';
REG_EJ <='0';
REG_FF <='0';
REG_RE <='0';
REG_AS <='0';
REG_FF_M <='0';
REG_RE_M <='0';
PBIT <='0';
PON <='0';
FA <='0';
PEXT <=(others=>'0');
elsif CLK'event and CLK='1' then
-- Edge Sense
if MZMODE='0' then
RPLBUF<=RPLBUF(1 downto 0)&PLAY_x; -- MZ-80B
else
RPLBUF <= RPLBUF(1 downto 0)&(not PLAY_x); -- MZ-2000
end if;
if RPLBUF(2 downto 1)="01" then
REG_PL <= TAPE;
REG_AS <= '0';
end if;
if MZMODE='0' then
RSTBUF <= RSTBUF(1 downto 0)&STOP_x; -- MZ-80B
else
RSTBUF <= RSTBUF(1 downto 0)&(not STOP_x); -- MZ-2000
end if;
if RSTBUF(2 downto 1)="01" then
MOTOR <= '0';
REG_AS <= '0';
REG_FF <= '0';
REG_RE <= '0';
end if;
REJBUF<=REJBUF(1 downto 0)&(not OPEN_x);
if REJBUF(2 downto 1)="01" then
REG_EJ <= '1';
TAPE <= '0';
REG_AS <= '0';
REG_FF <= '0';
REG_RE <= '0';
end if;
if MZMODE='0' then -- MZ-80B
RLTBUF <= RLTBUF(1 downto 0)&FLATCH;
if RLTBUF(2 downto 1)="01" then
REG_RE_M <= not FFREW;
REG_FF_M <= FFREW;
end if;
RFMBUF<=RFMBUF(1 downto 0)&FMOTOR;
if RFMBUF(2 downto 1)="01" then
REG_RE <= REG_RE_M and TAPE;
REG_FF <= REG_FF_M and TAPE;
REG_AS <= TAPE;
end if;
else -- MZ-2000
RREBUF<=RREBUF(1 downto 0)&(not REW_x);
if RREBUF(2 downto 1)="01" then
REG_RE <= TAPE;
end if;
RFFBUF<=RFFBUF(1 downto 0)&(not FF_x);
if RFFBUF(2 downto 1)="01" then
REG_FF <= TAPE;
end if;
RASBUF<=RASBUF(1 downto 0)&(not APSS_x);
if RASBUF(2 downto 1)="01" then
REG_AS <= TAPE;
end if;
end if;
-- Register
if IOCTL_RD='1' and IOCTL_WR='1' then
if IOCTL_ADDR=X"0010" and PBUSY='0' then -- MZ_CMT_POUT
PBIT <= IOCTL_DOUT(0);
PEXT <= "11111";
else
PEXT <= PEXT(3 downto 0)&'0';
end if;
if IOCTL_ADDR=X"0011" then -- MZ_CMT_STATUS
REG_AS <= REG_AS and (not IOCTL_DOUT(4));
REG_RE <= REG_RE and (not IOCTL_DOUT(3));
REG_FF <= REG_FF and (not IOCTL_DOUT(2));
REG_PL <= REG_PL and (not IOCTL_DOUT(1));
REG_EJ <= REG_EJ and (not IOCTL_DOUT(0));
end if;
if IOCTL_ADDR=X"0012" then -- MZ_CMT_COUNT
RBYTE(7 downto 0) <= IOCTL_DOUT;
end if;
if IOCTL_ADDR=X"0013" then -- MZ_CMT_COUNTH
RBYTE(15 downto 8) <= IOCTL_DOUT;
end if;
if IOCTL_ADDR=X"0014" then -- MZ_CMT_CTRL
FA <= IOCTL_DOUT(4);
PON <= IOCTL_DOUT(3);
WP <= IOCTL_DOUT(2);
MOTOR <= IOCTL_DOUT(1);
TAPE <= IOCTL_DOUT(0);
end if;
else
PEXT <= PEXT(3 downto 0)&'0';
end if;
end if;
end process;
IOCTL_DIN <= "0000000"&PBUSY when IOCTL_RD='1' and IOCTL_ADDR=X"0010" else -- MZ_CMT_POUT
"000"&REG_AS&REG_RE&REG_FF&REG_PL&REG_EJ when IOCTL_RD='1' and IOCTL_ADDR=X"0011" else -- MZ_CMT_STATUS
"000"&FA&PON&WP&MOTOR&TAPE when IOCTL_RD='1' and IOCTL_ADDR=X"0014" else -- MZ_CMT_CTRL
"00000000";
APSS <= REG_AS or FA;
INTO <= REG_PL or REG_EJ or REG_RE or REG_FF;
WREADY <= not WP;
TREADY <= not TAPE;
T_END <= not MOTOR;
RDATA <= POUT or PON;
--
-- PWM pulse generate
--
process( RST_n, ZCLK ) begin
if RST_n='0' then
POUT <='0';
PBUSY <='0';
PCNT <=(others=>'0');
elsif ZCLK'event and ZCLK='1' then
if PEXT(4)='1' then
if PBIT='0' then
PCNT <= "01010011011"; --667
else
PCNT <= "10100110100"; --1332
end if;
POUT <= '1';
PBUSY <= '1';
else
if POUT='1' and PCNT=0 then
if PBIT='0' then
PCNT <= "01010011000"; --664
else
PCNT <= "10100110110"; --1334
end if;
POUT <= '0';
elsif POUT='0' and PCNT=0 then
PBUSY <= '0';
else
PCNT <= PCNT-'1';
end if;
end if;
end if;
end process;
-- --
-- -- MZ-80B Action for Quick Access
-- --
-- process( reset, ZCLK ) begin
-- if reset='1' then
-- MADR<=(others=>'0');
-- MBYTE<=(others=>'0');
-- MCMD<=(others=>'0');
-- interrupt<='1';
-- elsif ZCLK'event and ZCLK='0' then
-- if ZIWR_x='0' and ZA8(7 downto 3)="10001" then
-- case ZA8(2 downto 0) is
-- when "000" => MADR(7 downto 0)<=ZDI; interrupt<='1';
-- when "001" => MADR(15 downto 8)<=ZDI; interrupt<='1';
-- when "010" => MBYTE(7 downto 0)<=ZDI; interrupt<='1';
-- when "011" => MBYTE(15 downto 8)<=ZDI; interrupt<='1';
-- when others => MCMD<=ZDI; interrupt<=not(ZDI(7) or ZDI(6) or ZDI(5) or ZDI(4) or ZDI(3) or ZDI(2) or ZDI(1) or ZDI(0));
-- end case;
-- end if;
-- end if;
-- end process;
-- ZDO<=STAT;
end RTL;

647
mz80b/fd55b.vhd Normal file
View File

@@ -0,0 +1,647 @@
--
-- fd55b.vhd
--
-- Floppy Disk Drive Emulation module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014-2015
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fd55b is
generic
(
DS_SW : std_logic_vector(4 downto 1) := "1111";
REG_ADDR : std_logic_vector(15 downto 0) := "0000000000000000"
);
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Step Pulse interrupt
-- FD signals
FCLK : in std_logic;
DS_n : in std_logic_vector(4 downto 1); -- Drive Select
HS : in std_logic; -- Head Select
MOTOR_n : in std_logic; -- Motor On
INDEX_n : out std_logic; -- Index Hole Detect
TRACK00 : out std_logic; -- Track 0
WPRT_n : out std_logic; -- Write Protect
STEP_n : in std_logic; -- Head Step In/Out
DIREC : in std_logic; -- Head Step Direction
WG_n : in std_logic; -- Write Gate
DTCLK : out std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Write Data
FDO : out std_logic_vector(7 downto 0); -- Read Data
-- Buffer RAM I/F
BCS_n : out std_logic; -- RAM Request
BADR : out std_logic_vector(22 downto 0); -- RAM Address
BWR_n : out std_logic; -- RAM Write Signal
BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end fd55b;
architecture RTL of fd55b is
--
-- Signals
--
signal DS : std_logic; -- Drive Select
signal HS_n : std_logic; -- Side One Select
signal DIV : std_logic_vector(6 downto 0); -- Divider
signal SS : std_logic; -- ROM Address multiplexer
signal PC : std_logic_vector(4 downto 0); -- ROM Address
signal OP : std_logic_vector(7 downto 0); -- OP code
signal ROMOUT : std_logic_vector(31 downto 0); -- ROM Data
signal TRACK : std_logic_vector(5 downto 0); -- Track Number
signal MF : std_logic; -- Modify Flag
signal PHASE : std_logic; -- Phase of Process
signal SSIZE : std_logic_vector(3 downto 0); -- Sector Size
signal FDOi : std_logic_vector(7 downto 0); -- Output Data(internal)
signal WP : std_logic; -- Write Protect Flag
signal DISK : std_logic; -- Disk Exist
signal D88 : std_logic; -- D88 flag(more 16bytes)
signal RSTBUF : std_logic_vector(2 downto 0); -- Step Pulse Shift Register
signal REG_ST : std_logic; -- Step Pulse Detect
signal CS : std_logic; -- Chip Select
signal RSEL : std_logic_vector(4 downto 0); -- Register Select
signal HSEL : std_logic; -- Register Select by Head
signal GAP3 : std_logic_vector(7 downto 0); -- GAP3 length
signal GAP4 : std_logic_vector(15 downto 0); -- GAP4 length
signal BADRi : std_logic_vector(22 downto 0); -- RAM Address(internal)
signal BDOi : std_logic_vector(7 downto 0); -- RAM Write Data(internal)
signal OUTEN : std_logic; -- Drive Selected, Disk Inserted, Motor On
---- Register set of side 0
signal DDEN0 : std_logic; -- density 0=FM,1=MFM side0
signal COUNT0 : std_logic_vector(10 downto 0); -- Timing Counter(Count down)
signal PSECT0 : std_logic_vector(3 downto 0); -- Phisical Sector Number
signal LSECT0 : std_logic_vector(7 downto 0); -- Logical Sector Number
signal MAXSECT0 : std_logic_vector(3 downto 0); -- Number of Sectors side0
signal TRADR0 : std_logic_vector(22 downto 0); -- Track data top address side0
signal FDO0i : std_logic_vector(7 downto 0); -- Output Data(internal)
signal PC0 : std_logic_vector(4 downto 0); -- ROM Address
signal ROMOUT0 : std_logic_vector(31 downto 0); -- ROM Data
signal OP0 : std_logic_vector(7 downto 0); -- OP code
signal FDAT0 : std_logic_vector(7 downto 0); -- Format Data
signal PHASE0 : std_logic; -- Phase of Process
signal DCLK0 : std_logic; -- Data Clock(internal)
signal FIRST0 : std_logic; -- First Action
signal MF0 : std_logic; -- Modify Flag
signal LSEL0 : std_logic_vector(3 downto 0); -- ID register select
signal LSEC00 : std_logic_vector(7 downto 0); -- Logical Sector Number table side0
signal LSEC01 : std_logic_vector(7 downto 0);
signal LSEC02 : std_logic_vector(7 downto 0);
signal LSEC03 : std_logic_vector(7 downto 0);
signal LSEC04 : std_logic_vector(7 downto 0);
signal LSEC05 : std_logic_vector(7 downto 0);
signal LSEC06 : std_logic_vector(7 downto 0);
signal LSEC07 : std_logic_vector(7 downto 0);
signal LSEC08 : std_logic_vector(7 downto 0);
signal LSEC09 : std_logic_vector(7 downto 0);
signal LSEC0A : std_logic_vector(7 downto 0);
signal LSEC0B : std_logic_vector(7 downto 0);
signal LSEC0C : std_logic_vector(7 downto 0);
signal LSEC0D : std_logic_vector(7 downto 0);
signal LSEC0E : std_logic_vector(7 downto 0);
signal LSEC0F : std_logic_vector(7 downto 0);
signal BADR0i : std_logic_vector(22 downto 0); -- RAM Address(internal)
signal BDO0i : std_logic_vector(7 downto 0); -- RAM Write Data(internal)
signal INDEX0_n : std_logic; -- Index Pulse(internal)
signal IPCNT0 : std_logic_vector(2 downto 0); -- Index Pulse Counter
signal GAP30 : std_logic_vector(7 downto 0); -- GAP3 length
signal GAP40 : std_logic_vector(15 downto 0); -- GAP4 length
---- Register set of side 1
signal DDEN1 : std_logic; -- density 0=FM,1=MFM side1
signal COUNT1 : std_logic_vector(10 downto 0); -- Timing Counter(Count down)
signal PSECT1 : std_logic_vector(3 downto 0); -- Phisical Sector Number
signal LSECT1 : std_logic_vector(7 downto 0); -- Logical Sector Number
signal MAXSECT1 : std_logic_vector(3 downto 0); -- Number of Sectors side1
signal TRADR1 : std_logic_vector(22 downto 0); -- Track data top address side1
signal FDO1i : std_logic_vector(7 downto 0); -- Output Data(internal)
signal PC1 : std_logic_vector(4 downto 0); -- ROM Address
signal ROMOUT1 : std_logic_vector(31 downto 0); -- ROM Data
signal OP1 : std_logic_vector(7 downto 0); -- OP code
signal FDAT1 : std_logic_vector(7 downto 0); -- Format Data
signal PHASE1 : std_logic; -- Phase of Process
signal DCLK1 : std_logic; -- Data Clock(internal)
signal FIRST1 : std_logic; -- First Action
signal MF1 : std_logic; -- Modify Flag
signal LSEL1 : std_logic_vector(3 downto 0); -- ID register select
signal LSEC10 : std_logic_vector(7 downto 0); -- Logical Sector Number table side1
signal LSEC11 : std_logic_vector(7 downto 0);
signal LSEC12 : std_logic_vector(7 downto 0);
signal LSEC13 : std_logic_vector(7 downto 0);
signal LSEC14 : std_logic_vector(7 downto 0);
signal LSEC15 : std_logic_vector(7 downto 0);
signal LSEC16 : std_logic_vector(7 downto 0);
signal LSEC17 : std_logic_vector(7 downto 0);
signal LSEC18 : std_logic_vector(7 downto 0);
signal LSEC19 : std_logic_vector(7 downto 0);
signal LSEC1A : std_logic_vector(7 downto 0);
signal LSEC1B : std_logic_vector(7 downto 0);
signal LSEC1C : std_logic_vector(7 downto 0);
signal LSEC1D : std_logic_vector(7 downto 0);
signal LSEC1E : std_logic_vector(7 downto 0);
signal LSEC1F : std_logic_vector(7 downto 0);
signal BADR1i : std_logic_vector(22 downto 0); -- RAM Address(internal)
signal BDO1i : std_logic_vector(7 downto 0); -- RAM Write Data(internal)
signal INDEX1_n : std_logic; -- Index Pulse(internal)
signal IPCNT1 : std_logic_vector(2 downto 0); -- Index Pulse Counter
signal GAP31 : std_logic_vector(7 downto 0); -- GAP3 length
signal GAP41 : std_logic_vector(15 downto 0); -- GAP4 length
begin
--
-- Format Direction Table
--
process( PC ) begin
case( PC ) is
-- FM
when "00000" => ROMOUT<="1111"&"0000"&"11111111"&"0000000000001111";
when "00001" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000101";
when "00010" => ROMOUT<="1111"&"0000"&"11111110"&"0000000000000000";
when "00011" => ROMOUT<="0010"&"0000"&"00000000"&"0000000000000011";
when "00100" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "00101" => ROMOUT<="1111"&"0000"&"11111111"&"0000000000001010";
when "00110" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000101";
when "00111" => ROMOUT<="0100"&"0000"&"11111011"&"00000"&SSIZE&"0000000";
when "01000" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "01001" => ROMOUT<="1100"&"0001"&"11111111"&"00000000"&GAP3;
when "01010" => ROMOUT<="0000"&"0000"&"11111111"&GAP4;
-- MFM
when "10000" => ROMOUT<="1111"&"0000"&"01001110"&"0000000000011111";
when "10001" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000001011";
when "10010" => ROMOUT<="1111"&"0000"&"10100001"&"0000000000000010";
when "10011" => ROMOUT<="1111"&"0000"&"11111110"&"0000000000000000";
when "10100" => ROMOUT<="0010"&"0000"&"00000000"&"0000000000000011";
when "10101" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "10110" => ROMOUT<="1111"&"0000"&"01001110"&"0000000000010101";
when "10111" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000001011";
when "11000" => ROMOUT<="1111"&"0000"&"10100001"&"0000000000000010";
when "11001" => ROMOUT<="0100"&"0000"&"11111011"&"00000"&SSIZE&"0000000";
when "11010" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "11011" => ROMOUT<="1100"&"0001"&"01001110"&"00000000"&GAP3;
when "11100" => ROMOUT<="0000"&"0000"&"01001110"&GAP4;
when others => ROMOUT<=(others=>'0');
end case;
end process;
--
-- Decode Sector size from Sector ID
--
process( SS, LSECT0(1 downto 0), LSECT1(1 downto 0) ) begin
case( SS ) is
when '0' =>
case( LSECT0(1 downto 0) ) is
when "00" => SSIZE<="0001";
when "01" => SSIZE<="0010";
when "10" => SSIZE<="0100";
when others => SSIZE<="1000";
end case;
when others =>
case( LSECT1(1 downto 0) ) is
when "00" => SSIZE<="0001";
when "01" => SSIZE<="0010";
when "10" => SSIZE<="0100";
when others => SSIZE<="1000";
end case;
end case;
end process;
--
-- Select GAP3/GAP4 length
--
GAP3 <= GAP30 when SS='0' else GAP31;
GAP4 <= GAP40 when SS='0' else GAP41;
--
-- FDT access
--
process( RST_n, FCLK ) begin
if RST_n='0' then
SS<='0';
elsif FCLK'event and FCLK='1' then
SS<=not SS;
if SS='0' then
ROMOUT0<=ROMOUT;
else
ROMOUT1<=ROMOUT;
end if;
end if;
end process;
PC<=PC0 when SS='0' else PC1;
--
-- Sector Table
--
process( PSECT0, LSEC00, LSEC01, LSEC02, LSEC03, LSEC04, LSEC05, LSEC06, LSEC07, LSEC08, LSEC09, LSEC0A, LSEC0B, LSEC0C, LSEC0D, LSEC0E, LSEC0F ) begin
case PSECT0 is
when "0000" => LSECT0<=LSEC00;
when "0001" => LSECT0<=LSEC01;
when "0010" => LSECT0<=LSEC02;
when "0011" => LSECT0<=LSEC03;
when "0100" => LSECT0<=LSEC04;
when "0101" => LSECT0<=LSEC05;
when "0110" => LSECT0<=LSEC06;
when "0111" => LSECT0<=LSEC07;
when "1000" => LSECT0<=LSEC08;
when "1001" => LSECT0<=LSEC09;
when "1010" => LSECT0<=LSEC0A;
when "1011" => LSECT0<=LSEC0B;
when "1100" => LSECT0<=LSEC0C;
when "1101" => LSECT0<=LSEC0D;
when "1110" => LSECT0<=LSEC0E;
when others => LSECT0<=LSEC0F;
end case;
end process;
process( PSECT1, LSEC10, LSEC11, LSEC12, LSEC13, LSEC14, LSEC15, LSEC16, LSEC17, LSEC18, LSEC19, LSEC1A, LSEC1B, LSEC1C, LSEC1D, LSEC1E, LSEC1F ) begin
case PSECT1 is
when "0000" => LSECT1<=LSEC10;
when "0001" => LSECT1<=LSEC11;
when "0010" => LSECT1<=LSEC12;
when "0011" => LSECT1<=LSEC13;
when "0100" => LSECT1<=LSEC14;
when "0101" => LSECT1<=LSEC15;
when "0110" => LSECT1<=LSEC16;
when "0111" => LSECT1<=LSEC17;
when "1000" => LSECT1<=LSEC18;
when "1001" => LSECT1<=LSEC19;
when "1010" => LSECT1<=LSEC1A;
when "1011" => LSECT1<=LSEC1B;
when "1100" => LSECT1<=LSEC1C;
when "1101" => LSECT1<=LSEC1D;
when "1110" => LSECT1<=LSEC1E;
when others => LSECT1<=LSEC1F;
end case;
end process;
--
-- Clock Divider
--
process( RST_n, FCLK ) begin
if RST_n='0' then
DIV<=(others=>'0');
DCLK0<='0';
DCLK1<='0';
elsif FCLK'event and FCLK='1' then
DIV<=DIV+'1';
if DIV(5 downto 0)="111111" then
if MOTOR_n='0' and (DDEN0='1' or (DDEN0='0' and DIV(6)='1')) then
DCLK0<='1';
else
DCLK0<='0';
end if;
if MOTOR_n='0' and (DDEN1='1' or (DDEN1='0' and DIV(6)='1')) then
DCLK1<='1';
else
DCLK1<='0';
end if;
else
DCLK0<='0';
DCLK1<='0';
end if;
end if;
end process;
--
-- Track Sequencer
--
process( RST_n, FCLK ) begin
if RST_n='0' then
-- Side 0
PHASE0<='0';
COUNT0<=(others=>'0');
PSECT0<=(others=>'0');
PC0(3 downto 0)<=(others=>'0');
BADR0i<=(others=>'0');
BDO0i<=(others=>'0');
INDEX0_n<='1';
IPCNT0<=(others=>'1');
-- Side 1
PHASE1<='0';
COUNT1<=(others=>'0');
PSECT1<=(others=>'0');
PC1(3 downto 0)<=(others=>'0');
BADR1i<=(others=>'0');
BDO1i<=(others=>'0');
INDEX1_n<='1';
IPCNT1<=(others=>'1');
elsif FCLK'event and FCLK='1' then
-- Disk Removed
if DISK='0' then
MF0<='0';
MF1<='0';
end if;
-- Sequencer
-- Side 0
if DCLK0='1' then
PHASE0<=not PHASE0;
if PHASE0='0' then
case OP0(7 downto 4) is
when "0010" => -- ID
case COUNT0(1 downto 0) is
when "11" =>
FDO0i<="00"&TRACK;
when "10" =>
FDO0i<="0000000"&LSECT0(7);
when "01" =>
FDO0i<="000"&LSECT0(6 downto 2);
when others =>
FDO0i<="000000"&LSECT0(1 downto 0);
end case;
when "0100" => -- DATA
if FIRST0='1' then
FDO0i<=FDAT0;
else
FDO0i<=BDI;
BADR0i<=BADR0i+'1';
end if;
when "0000" => -- JMP
if COUNT0="00000000000" then
PC0(3 downto 0)<=OP0(3 downto 0);
end if;
FDO0i<=FDAT0;
when "1100" => -- LOOP
if COUNT0="00000000000" then
if PSECT0=MAXSECT0 then
PSECT0<=(others=>'0');
else
PC0(3 downto 0)<=OP0(3 downto 0);
PSECT0<=PSECT0+'1';
end if;
end if;
FDO0i<=FDAT0;
when others => -- NOP
FDO0i<=FDAT0;
end case;
else -- PHASE='1'
if COUNT0="00000000000" then
OP0<=ROMOUT0(31 downto 24);
FDAT0<=ROMOUT0(23 downto 16);
COUNT0<=ROMOUT0(10 downto 0);
FIRST0<='1';
PC0(3 downto 0)<=PC0(3 downto 0)+'1';
if PC0(3 downto 0)="0000" then
BADR0i<=TRADR0;
end if;
if OP0(7 downto 4)="0100" and D88='1' then -- DATA
BADR0i<=BADR0i+"10000";
end if;
else
FIRST0<='0';
COUNT0<=COUNT0-'1';
if OP0(7 downto 4)="0100" then -- DATA
if WG_n='0' and WP='0' then
BDO0i<=FDI;
MF0<='1';
end if;
end if;
end if;
end if;
-- Index Pulse
if PC0(3 downto 0)="0000" then
IPCNT0<=(others=>'0');
INDEX0_n<='0';
else
if IPCNT0="111" then
INDEX0_n<='1';
else
IPCNT0<=IPCNT0+'1';
end if;
end if;
end if;
-- Side 1
if DCLK1='1' then
PHASE1<=not PHASE1;
if PHASE1='0' then
case OP1(7 downto 4) is
when "0010" => -- ID
case COUNT1(1 downto 0) is
when "11" =>
FDO1i<="00"&TRACK;
when "10" =>
FDO1i<="0000000"&LSECT1(7);
when "01" =>
FDO1i<="000"&LSECT1(6 downto 2);
when others =>
FDO1i<="000000"&LSECT1(1 downto 0);
end case;
when "0100" => -- DATA
if FIRST1='1' then
FDO1i<=FDAT1;
else
FDO1i<=BDI;
BADR1i<=BADR1i+'1';
end if;
when "0000" => -- JMP
if COUNT1="00000000000" then
PC1(3 downto 0)<=OP1(3 downto 0);
end if;
FDO1i<=FDAT1;
when "1100" => -- LOOP
if COUNT1="00000000000" then
if PSECT1=MAXSECT1 then
PSECT1<=(others=>'0');
else
PC1(3 downto 0)<=OP1(3 downto 0);
PSECT1<=PSECT1+'1';
end if;
end if;
FDO1i<=FDAT1;
when others => -- NOP
FDO1i<=FDAT1;
end case;
else -- PHASE='1'
if COUNT1="00000000000" then
OP1<=ROMOUT1(31 downto 24);
FDAT1<=ROMOUT1(23 downto 16);
COUNT1<=ROMOUT1(10 downto 0);
FIRST1<='1';
PC1(3 downto 0)<=PC1(3 downto 0)+'1';
if PC1(3 downto 0)="0000" then
BADR1i<=TRADR1;
end if;
if OP1(7 downto 4)="0100" and D88='1' then -- DATA
BADR1i<=BADR1i+"10000";
end if;
else
FIRST1<='0';
COUNT1<=COUNT1-'1';
if OP1(7 downto 4)="0100" then -- DATA
if WG_n='0' and WP='0' then
BDO1i<=FDI;
MF1<='1';
end if;
end if;
end if;
end if;
-- Index Pulse
if PC1(3 downto 0)="0000" then
IPCNT1<=(others=>'0');
INDEX1_n<='0';
else
if IPCNT1="111" then
INDEX1_n<='1';
else
IPCNT1<=IPCNT1+'1';
end if;
end if;
end if;
end if;
end process;
PC0(4) <= DDEN0;
PC1(4) <= DDEN1;
MF <= MF0 or MF1;
DS <= not((DS_n(1) or DS_SW(1)) and (DS_n(2) or DS_SW(2)) and (DS_n(3) or DS_SW(3)) and (DS_n(4) or DS_SW(4)));
OUTEN <= '1' when DS='1' and DISK='1' and MOTOR_n='0' else '0';
HS_n <= not HS;
WPRT_n <= not WP when DS='1' and DISK='1' else '1';
TRACK00 <= '0' when TRACK="000000" and DS='1' else '1';
FDO <= FDOi when DS='1' and DISK='1' else (others=>'0');
DTCLK <= not PHASE when OUTEN='1' else '0';
--
-- Select Output with Head Select
--
process( HS_n, PHASE0, FDO0i, INDEX0_n, OP0, BADR0i, BDO0i, PHASE1, FDO1i, INDEX1_n, OP1, BADR1i, BDO1i ) begin
if HS_n='0' then
PHASE <= PHASE0;
FDOi <= FDO0i;
BADRi <= BADR0i;
BDOi <= BDO0i;
INDEX_n <= INDEX0_n or (not (DS and DISK));
OP <= OP0;
else
PHASE <= PHASE1;
FDOi <= FDO1i;
BADRi <= BADR1i;
BDOi <= BDO1i;
INDEX_n <= INDEX1_n or (not (DS and DISK));
OP <= OP1;
end if;
end process;
BCS_n <= '0' when PHASE='0' and OP(7 downto 4)="0100" and OUTEN='1' else '1'; -- DATA
BWR_n <= '0' when PHASE='0' and OP(7 downto 4)="0100" and WG_n='0' and WP='0' and OUTEN='1' else '1'; -- DATA
BADR <= BADRi when DS='1' else (others=>'0');
BDO <= BDOi when DS='1' else (others=>'0');
--
-- Avalon Bus
--
process( RST_n, CLK ) begin
if RST_n='0' then
DISK <='0';
DDEN0 <='0';
DDEN1 <='0';
REG_ST <='0';
TRACK <=(others=>'0');
WP <='0';
elsif CLK'event and CLK='1' then
-- Edge Sense
RSTBUF <= RSTBUF(1 downto 0)&((not STEP_n) and DS);
if RSTBUF(2 downto 1)="01" then
REG_ST <= '1';
end if;
-- Register
if IOCTL_RD='1' and IOCTL_WR='1' and CS='1' then
case RSEL is
when "00000"|"00001" => -- MZ_FDx_CTRL
D88 <= IOCTL_DOUT(2);
WP <= IOCTL_DOUT(1);
DISK <= IOCTL_DOUT(0);
when "00010"|"00011" => -- MZ_FDx_TRK
TRACK <= IOCTL_DOUT(5 downto 0);
when "00100"|"00101" => -- MZ_FDx_STEP
REG_ST <= REG_ST and (not IOCTL_DOUT(0));
when "00110"|"00111" => -- MZ_FDx_HSEL
HSEL <= IOCTL_DOUT(0);
when "01000" => -- MZ_FDx_ID
case LSEL0 is
when "0000" => LSEC00<=IOCTL_DOUT;
when "0001" => LSEC01<=IOCTL_DOUT;
when "0010" => LSEC02<=IOCTL_DOUT;
when "0011" => LSEC03<=IOCTL_DOUT;
when "0100" => LSEC04<=IOCTL_DOUT;
when "0101" => LSEC05<=IOCTL_DOUT;
when "0110" => LSEC06<=IOCTL_DOUT;
when "0111" => LSEC07<=IOCTL_DOUT;
when "1000" => LSEC08<=IOCTL_DOUT;
when "1001" => LSEC09<=IOCTL_DOUT;
when "1010" => LSEC0A<=IOCTL_DOUT;
when "1011" => LSEC0B<=IOCTL_DOUT;
when "1100" => LSEC0C<=IOCTL_DOUT;
when "1101" => LSEC0D<=IOCTL_DOUT;
when "1110" => LSEC0E<=IOCTL_DOUT;
when others => LSEC0F<=IOCTL_DOUT;
end case;
when "01001" =>
case LSEL1 is
when "0000" => LSEC10<=IOCTL_DOUT;
when "0001" => LSEC11<=IOCTL_DOUT;
when "0010" => LSEC12<=IOCTL_DOUT;
when "0011" => LSEC13<=IOCTL_DOUT;
when "0100" => LSEC14<=IOCTL_DOUT;
when "0101" => LSEC15<=IOCTL_DOUT;
when "0110" => LSEC16<=IOCTL_DOUT;
when "0111" => LSEC17<=IOCTL_DOUT;
when "1000" => LSEC18<=IOCTL_DOUT;
when "1001" => LSEC19<=IOCTL_DOUT;
when "1010" => LSEC1A<=IOCTL_DOUT;
when "1011" => LSEC1B<=IOCTL_DOUT;
when "1100" => LSEC1C<=IOCTL_DOUT;
when "1101" => LSEC1D<=IOCTL_DOUT;
when "1110" => LSEC1E<=IOCTL_DOUT;
when others => LSEC1F<=IOCTL_DOUT;
end case;
when "01010" => LSEL0 <=IOCTL_DOUT(3 downto 0); -- MZ_FDx_LSEL
when "01011" => LSEL1 <=IOCTL_DOUT(3 downto 0);
when "01100" => DDEN0 <=IOCTL_DOUT(0); -- MZ_FDx_DDEN
when "01101" => DDEN1 <=IOCTL_DOUT(0);
when "01110" => MAXSECT0 <=IOCTL_DOUT(3 downto 0); -- MZ_FDx_MAXS
when "01111" => MAXSECT1 <=IOCTL_DOUT(3 downto 0);
when "10000" => TRADR0(7 downto 0) <=IOCTL_DOUT; -- MZ_FDx_TA0
when "10010" => TRADR0(15 downto 8) <=IOCTL_DOUT; -- MZ_FDx_TA1
when "10100" => TRADR0(22 downto 16) <=IOCTL_DOUT(6 downto 0); -- MZ_FDx_TA2
when "10001" => TRADR1(7 downto 0) <=IOCTL_DOUT;
when "10011" => TRADR1(15 downto 8) <=IOCTL_DOUT;
when "10101" => TRADR1(22 downto 16) <=IOCTL_DOUT(6 downto 0);
when "11000" => GAP30 <=IOCTL_DOUT; -- MZ_FDx_G30
when "11001" => GAP31 <=IOCTL_DOUT;
when "11100" => GAP40(7 downto 0) <=IOCTL_DOUT; -- MZ_FDx_G40
when "11110" => GAP40(15 downto 8) <=IOCTL_DOUT; -- MZ_FDx_G41
when "11101" => GAP41(7 downto 0) <=IOCTL_DOUT;
when "11111" => GAP41(15 downto 8) <=IOCTL_DOUT;
when others =>
end case;
end if;
end if;
end process;
CS <= '1' when IOCTL_ADDR(15 downto 4)=REG_ADDR(15 downto 4) else '0';
RSEL <= IOCTL_ADDR(3 downto 0)&HSEL;
IOCTL_DIN <= "0000"&MF&D88&WP&DISK when IOCTL_RD='1' and CS='1' and IOCTL_ADDR(3 downto 0)="0000" else -- MZ_FDx_CTRL
"000000"&DIREC&REG_ST when IOCTL_RD='1' and CS='1' and IOCTL_ADDR(3 downto 0)="0010" else -- MZ_FDx_STEP
"00000000";
INTO <= REG_ST;
end RTL;

226
mz80b/fdunit.vhd Normal file
View File

@@ -0,0 +1,226 @@
--
-- fdunit.vhd
--
-- Floppy Disk Drive Unit Emulation module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fdunit is
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Step Pulse interrupt
-- FD signals
FCLK : in std_logic;
DS_n : in std_logic_vector(4 downto 1); -- Drive Select
HS : in std_logic; -- Head Select
MOTOR_n : in std_logic; -- Motor On
INDEX_n : out std_logic; -- Index Hole Detect
TRACK00 : out std_logic; -- Track 0
WPRT_n : out std_logic; -- Write Protect
STEP_n : in std_logic; -- Head Step In/Out
DIREC : in std_logic; -- Head Step Direction
WG_n : in std_logic; -- Write Gate
DTCLK : out std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Write Data
FDO : out std_logic_vector(7 downto 0); -- Read Data
-- Buffer RAM I/F
BCS_n : out std_logic; -- RAM Request
BADR : out std_logic_vector(22 downto 0); -- RAM Address
BWR_n : out std_logic; -- RAM Write Signal
BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end fdunit;
architecture RTL of fdunit is
--
-- Floppy Signals
--
signal RDO0 : std_logic_vector(7 downto 0);
signal RDO1 : std_logic_vector(7 downto 0);
signal IDX_0 : std_logic;
signal IDX_1 : std_logic;
signal TRK00_0 : std_logic;
signal TRK00_1 : std_logic;
signal WPRT_0 : std_logic;
signal WPRT_1 : std_logic;
signal FDO0 : std_logic_vector(7 downto 0);
signal FDO1 : std_logic_vector(7 downto 0);
signal DTCLK0 : std_logic;
signal DTCLK1 : std_logic;
--
-- Control
--
signal INT0 : std_logic;
signal INT1 : std_logic;
--
-- Memory Access
--
signal BCS0_n : std_logic;
signal BCS1_n : std_logic;
signal BADR0 : std_logic_vector(22 downto 0);
signal BADR1 : std_logic_vector(22 downto 0);
signal BWR0_n : std_logic;
signal BWR1_n : std_logic;
signal BDO0 : std_logic_vector(7 downto 0);
signal BDO1 : std_logic_vector(7 downto 0);
--
-- Component
--
component fd55b
generic
(
DS_SW : std_logic_vector(4 downto 1) := "1111";
REG_ADDR : std_logic_vector(15 downto 0) := "0000000000000000"
);
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Step Pulse interrupt
-- FD signals
FCLK : in std_logic;
DS_n : in std_logic_vector(4 downto 1); -- Drive Select
HS : in std_logic; -- Head Select
MOTOR_n : in std_logic; -- Motor On
INDEX_n : out std_logic; -- Index Hole Detect
TRACK00 : out std_logic; -- Track 0
WPRT_n : out std_logic; -- Write Protect
STEP_n : in std_logic; -- Head Step In/Out
DIREC : in std_logic; -- Head Step Direction
WG_n : in std_logic; -- Write Gate
DTCLK : out std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Write Data
FDO : out std_logic_vector(7 downto 0); -- Read Data
-- Buffer RAM I/F
BCS_n : out std_logic; -- RAM Request
BADR : out std_logic_vector(22 downto 0); -- RAM Address
BWR_n : out std_logic; -- RAM Write Signal
BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
begin
FDD0 : fd55b generic map (
DS_SW => "1110",
REG_ADDR => X"0040"
)
Port map (
RST_n => RST_n, -- Reset
CLK => CLK, -- System Clock
-- Interrupt
INTO => INT0, -- Step Pulse interrupt
-- FD signals
FCLK => FCLK,
DS_n => DS_n, -- Drive Select
HS => HS, -- Head Select
MOTOR_n => MOTOR_n, -- Motor On
INDEX_n => IDX_0, -- Index Hole Detect
TRACK00 => TRK00_0, -- Track 0
WPRT_n => WPRT_0, -- Write Protect
STEP_n => STEP_n, -- Head Step In/Out
DIREC => DIREC, -- Head Step Direction
WG_n => WG_n, -- Write Gate
DTCLK => DTCLK0, -- Data Clock
FDI => FDI, -- Write Data
FDO => FDO0, -- Read Data
-- Buffer RAM I/F
BCS_n => BCS0_n, -- RAM Request
BADR => BADR0, -- RAM Address
BWR_n => BWR0_n, -- RAM Write Signal
BDI => BDI, -- Data Bus Input from RAM
BDO => BDO0 -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
IOCTL_DIN => IOCTL_DIN, -- HPS Data to be read into HPS.
IOCTL_INTERRUPT => IOCTL_INTERRUPT -- HPS Interrupt.
);
FDD1 : fd55b generic map (
DS_SW => "1101",
REG_ADDR => X"0050"
)
Port map (
RST_n => RST_n, -- Reset
CLK => CLK, -- System Clock
-- Interrupt
INTO => INT1, -- Step Pulse interrupt
-- FD signals
FCLK => FCLK,
DS_n => DS_n, -- Drive Select
HS => HS, -- Head Select
MOTOR_n => MOTOR_n, -- Motor On
INDEX_n => IDX_1, -- Index Hole Detect
TRACK00 => TRK00_1, -- Track 0
WPRT_n => WPRT_1, -- Write Protect
STEP_n => STEP_n, -- Head Step In/Out
DIREC => DIREC, -- Head Step Direction
WG_n => WG_n, -- Write Gate
DTCLK => DTCLK1, -- Data Clock
FDI => FDI, -- Write Data
FDO => FDO1, -- Read Data
-- Buffer RAM I/F
BCS_n => BCS1_n, -- RAM Request
BADR => BADR1, -- RAM Address
BWR_n => BWR1_n, -- RAM Write Signal
BDI => BDI, -- Data Bus Input from RAM
BDO => BDO1 -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
IOCTL_DIN => IOCTL_DIN, -- HPS Data to be read into HPS.
IOCTL_INTERRUPT => IOCTL_INTERRUPT -- HPS Interrupt.
);
INDEX_n <= IDX_0 and IDX_1;
TRACK00 <= TRK00_0 and TRK00_1;
WPRT_n <= WPRT_0 and WPRT_1;
FDO <= FDO0 or FDO1;
DTCLK <= DTCLK0 or DTCLK1;
BCS_n <= BCS0_n and BCS1_n;
BADR <= BADR0 or BADR1;
BWR_n <= BWR0_n and BWR1_n;
BDO <= BDO0 or BDO1;
RDO <= RDO0 or RDO1;
INTO <= INT0 or INT1;
end RTL;

834
mz80b/mb8876.vhd Normal file
View File

@@ -0,0 +1,834 @@
--
-- mb8876.vhd
--
-- Floppy Disk Controller partiality compatible module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014-2015
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mb8876 is
Port (
-- CPU Signals
ZCLK : in std_logic;
MR_n : in std_logic;
A : in std_logic_vector(1 downto 0); -- CPU Address Bus
RE_n : in std_logic; -- CPU Read Signal
WE_n : in std_logic; -- CPU Write Signal
CS_n : in std_logic; -- CPU Chip Select
DALI_n : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
DALO_n : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- DALI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
-- DALO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- FD signals
DDEN_n : in std_logic; -- Double Density
IP_n : in std_logic; -- Index Pulse
READY : in std_logic; -- Drive Ready
TR00_n : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP : out std_logic; -- Head Step In/Out
DIRC : out std_logic; -- Head Step Direction
WG : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end mb8876;
architecture RTL of mb8876 is
signal DALI : std_logic_vector(7 downto 0); -- non-inverted Data bus(input)
signal DALO : std_logic_vector(7 downto 0); -- non-inverted Data bus(output)
signal STS : std_logic_vector(7 downto 0); -- Command Register(backup for status)
signal TRACK : std_logic_vector(7 downto 0); -- Track Counter
signal SECTOR : std_logic_vector(7 downto 0); -- Sector Counter
signal GAPVAL : std_logic_vector(7 downto 0); -- Gap's Value
signal FDIR : std_logic_vector(7 downto 0); -- Bulk Data(pre registered)
signal FDR : std_logic_vector(7 downto 0); -- Bulk Data
signal WDATA : std_logic_vector(7 downto 0); -- Write Data
signal BCOUNT : std_logic_vector(9 downto 0); -- Byte Counter
signal DELAY : std_logic_vector(16 downto 0); -- Delay Counter
signal DCSET : std_logic_vector(16 downto 0); -- Next Delay Count Number
signal PCOUNT : std_logic_vector(4 downto 0); -- Step Pulse Width
signal BUSY : std_logic; -- Busy Flag
signal DIRC0 : std_logic; -- Step Direction(current)
signal DIRR : std_logic; -- Step Direction(registered)
signal E_SEEK : std_logic; -- Seek Error
signal E_RNF : std_logic; -- Record Not Found Error
signal E_RLOST : std_logic; -- Lost Data Error(read)
signal E_WLOST : std_logic; -- Lost Data Error(write)
signal IDXBUF : std_logic_vector(2 downto 0); -- Index Pulse Detect
signal DTBUF : std_logic_vector(2 downto 0); -- Data Enable Detect
signal FDEN : std_logic; -- Data Enable Detected
signal IDXC : std_logic_vector(2 downto 0); -- Index Pulse Counter
signal RDRQ : std_logic; -- Read Data Request
signal WDRQ : std_logic; -- Write Data Request
signal MOVING : std_logic; -- Head Stepping Flag
signal RFND0 : std_logic; -- Record Found Flag(process)
signal RFND : std_logic; -- Record Found Flag(result)
signal TFND : std_logic; -- Track Found Flag
signal CMPT : std_logic; -- Track Compared Flag
signal VFLAG : std_logic; -- Record Verify Flag
signal UFLAG : std_logic; -- Track Number Update Flag
signal CFLAG : std_logic; -- Side Compare Flag
signal MFLAG : std_logic; -- Multi Record Flag
signal SFLAG : std_logic; -- Side Flag
--
-- State Machine
--
signal CUR : std_logic_vector(5 downto 0);
signal NXT : std_logic_vector(5 downto 0);
constant IDLE : std_logic_vector(5 downto 0) := "000000";
constant REST : std_logic_vector(5 downto 0) := "000001";
--constant REST1 : std_logic_vector(5 downto 0) := "000010";
--constant REST2 : std_logic_vector(5 downto 0) := "000011";
constant SEEK0 : std_logic_vector(5 downto 0) := "000100";
constant SEEK1 : std_logic_vector(5 downto 0) := "000101";
constant SEEK2 : std_logic_vector(5 downto 0) := "000110";
constant STEP0 : std_logic_vector(5 downto 0) := "000111";
constant STEP1 : std_logic_vector(5 downto 0) := "001000";
constant STEP2 : std_logic_vector(5 downto 0) := "001001";
constant STIN0 : std_logic_vector(5 downto 0) := "001010";
constant STIN1 : std_logic_vector(5 downto 0) := "001011";
constant STIN2 : std_logic_vector(5 downto 0) := "001100";
constant STOT0 : std_logic_vector(5 downto 0) := "001101";
constant STOT1 : std_logic_vector(5 downto 0) := "001110";
constant STOT2 : std_logic_vector(5 downto 0) := "001111";
constant VTRK0 : std_logic_vector(5 downto 0) := "010000";
constant VTRK1 : std_logic_vector(5 downto 0) := "010001";
constant VTRK_ER : std_logic_vector(5 downto 0) := "010010";
constant RDAT0 : std_logic_vector(5 downto 0) := "010011";
constant RDAT1 : std_logic_vector(5 downto 0) := "010100";
constant RDAT2 : std_logic_vector(5 downto 0) := "010101";
constant RDAT3 : std_logic_vector(5 downto 0) := "010110";
constant RDAT4 : std_logic_vector(5 downto 0) := "010111";
constant RDAT5 : std_logic_vector(5 downto 0) := "011000";
constant WDAT0 : std_logic_vector(5 downto 0) := "011001";
constant WDAT1 : std_logic_vector(5 downto 0) := "011010";
constant WDAT2 : std_logic_vector(5 downto 0) := "011011";
constant WDAT3 : std_logic_vector(5 downto 0) := "011100";
constant WDAT4 : std_logic_vector(5 downto 0) := "011101";
constant WDAT5 : std_logic_vector(5 downto 0) := "011110";
constant RNF_ER : std_logic_vector(5 downto 0) := "011111";
constant RADR0 : std_logic_vector(5 downto 0) := "100000";
constant RADR1 : std_logic_vector(5 downto 0) := "100001";
constant RADR2 : std_logic_vector(5 downto 0) := "100010";
constant RADR3 : std_logic_vector(5 downto 0) := "100011";
constant CMDQ : std_logic_vector(5 downto 0) := "100100";
signal CUR2 : std_logic_vector(4 downto 0);
signal NXT2 : std_logic_vector(4 downto 0);
constant HUNT : std_logic_vector(4 downto 0) := "00000";
constant GAP1 : std_logic_vector(4 downto 0) := "00001";
constant SYNC1 : std_logic_vector(4 downto 0) := "00010";
constant ADM1 : std_logic_vector(4 downto 0) := "00011";
constant ID_TRK : std_logic_vector(4 downto 0) := "00100";
constant ID_HEAD : std_logic_vector(4 downto 0) := "00101";
constant ID_SECT : std_logic_vector(4 downto 0) := "00110";
constant ID_FMT : std_logic_vector(4 downto 0) := "00111";
constant CRC1_1 : std_logic_vector(4 downto 0) := "01000";
constant CRC1_2 : std_logic_vector(4 downto 0) := "01001";
constant GAP2_2 : std_logic_vector(4 downto 0) := "01010";
constant GAP2_1 : std_logic_vector(4 downto 0) := "01011";
constant GAP2 : std_logic_vector(4 downto 0) := "01100";
constant SYNC2 : std_logic_vector(4 downto 0) := "01101";
constant ADM2 : std_logic_vector(4 downto 0) := "01110";
constant DATA : std_logic_vector(4 downto 0) := "01111";
constant DATA_1 : std_logic_vector(4 downto 0) := "10000";
constant DATA_2 : std_logic_vector(4 downto 0) := "10001";
constant DATA_3 : std_logic_vector(4 downto 0) := "10010";
constant CRC2 : std_logic_vector(4 downto 0) := "10011";
begin
--
-- Step pulse and Seek wait
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
DELAY <= (others=>'0');
PCOUNT <= (others=>'0');
MOVING <= '0';
STEP <= '0';
elsif ZCLK'event and ZCLK='1' then
if DELAY="00000000000000000" then
if CUR=SEEK1 or CUR=STEP1 or CUR=STIN1 or CUR=STOT1 then
DELAY <= DCSET;
PCOUNT <= (others=>'1');
MOVING <= '1';
else
MOVING <= '0';
end if;
else
DELAY <= DELAY-'1';
if PCOUNT="00000" then
STEP <= '0';
else
STEP <= '1';
PCOUNT <= PCOUNT-'1';
end if;
end if;
end if;
end process;
--
-- Select Step Rate
--
process( STS(1 downto 0) ) begin
case STS(1 downto 0) is -- r0,r1
when "00" => DCSET<=conv_std_logic_vector(24000, 17); -- 6ms
when "10" => DCSET<=conv_std_logic_vector(48000, 17); -- 12ms
when "01" => DCSET<=conv_std_logic_vector(80000, 17); -- 20ms
when others => DCSET<=conv_std_logic_vector(120000, 17); -- 30ms
end case;
end process;
--
-- FD Data Sync
--
process( MR_n, ZCLK ) begin
-- process( MR_n, DTCLK ) begin
if MR_n='0' then
FDR<=(others=>'0');
CUR2<=HUNT;
BCOUNT<=(others=>'0');
elsif ZCLK'event and ZCLK='1' then
-- elsif DTCLK'event and DTCLK='1' then
-- FDIRR<=FDIR;
if FDEN='1' then
if MOVING='1' then
CUR2<=HUNT;
else
CUR2<=NXT2;
end if;
FDR<=FDI;
if CUR2=ID_FMT then
case FDR(1 downto 0) is
when "00" => BCOUNT<="0001111101";
when "01" => BCOUNT<="0011111101";
when "10" => BCOUNT<="0111111101";
when others => BCOUNT<="1111111101";
end case;
end if;
if CUR2=DATA then
BCOUNT<=BCOUNT-'1';
end if;
end if;
end if;
end process;
process( CUR2, IP_n, FDI, GAPVAL, BCOUNT ) begin
case CUR2 is
when HUNT =>
if IP_n='0' and FDI=GAPVAL then
NXT2<=GAP1;
else
NXT2<=HUNT;
end if;
when GAP1 =>
if FDI=X"00" then
NXT2<=SYNC1;
else
NXT2<=GAP1;
end if;
when SYNC1 =>
if FDI=X"FE" then
NXT2<=ADM1;
else
NXT2<=SYNC1;
end if;
when ADM1 =>
NXT2<=ID_TRK;
when ID_TRK =>
NXT2<=ID_HEAD;
when ID_HEAD =>
NXT2<=ID_SECT;
when ID_SECT =>
NXT2<=ID_FMT;
when ID_FMT =>
NXT2<=CRC1_1;
when CRC1_1 =>
NXT2<=CRC1_2;
when CRC1_2 =>
NXT2<=GAP2_2;
when GAP2_2 =>
NXT2<=GAP2_1;
when GAP2_1 =>
NXT2<=GAP2;
when GAP2 =>
if FDI=X"00" then
NXT2<=SYNC2;
else
NXT2<=GAP2;
end if;
when SYNC2 =>
if FDI=X"FB" then
NXT2<=DATA;
else
NXT2<=SYNC2;
end if;
when DATA =>
if BCOUNT="0000000000" then
NXT2<=DATA_1;
else
NXT2<=DATA;
end if;
when DATA_1 =>
NXT2<=DATA_2;
when DATA_2 =>
NXT2<=DATA_3;
when DATA_3 =>
NXT2<=CRC2;
when CRC2 =>
if FDI=GAPVAL then
NXT2<=GAP1;
else
NXT2<=CRC2;
end if;
when others =>
NXT2<=HUNT;
end case;
end process;
GAPVAL<=X"4E" when DDEN_n='0' else X"FF";
--
-- FD data sample timing
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
DTBUF<=(others=>'0');
FDEN<='0';
elsif ZCLK'event and ZCLK='1' then
DTBUF<=DTBUF(1 downto 0)&DTCLK;
if DTBUF(2 downto 1)="01" then
FDEN<='1';
else
FDEN<='0';
end if;
end if;
end process;
--
-- DRQ
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
E_RLOST<='0';
E_WLOST<='0';
RDRQ<='0';
WDRQ<='0';
elsif ZCLK'event and ZCLK='1' then
-- Reset
if CUR=RDAT0 then
E_RLOST<='0';
RDRQ<='0';
end if;
if CUR=WDAT0 then
E_WLOST<='0';
WDRQ<='0';
end if;
if CUR=CMDQ then
if RDRQ='1' then
E_RLOST<='1';
end if;
if WDRQ='1' then
E_WLOST<='1';
end if;
RDRQ<='0';
WDRQ<='0';
end if;
-- DRQ on (Read)
if (CUR=RDAT3 and (CUR2=DATA or CUR2=DATA_1 or CUR2=DATA_2)) or (CUR=RADR2 and (CUR2=ADM1 or CUR2=ID_TRK or CUR2=ID_HEAD or CUR2=ID_SECT or CUR2=ID_FMT or CUR2=CRC1_1)) then
if FDEN='1' then
RDRQ<='1';
if RDRQ='1' then
E_RLOST<='1';
end if;
end if;
end if;
-- Write
if CUR=WDAT3 and (CUR2=DATA or CUR2=GAP2_1 or (CUR2=SYNC2 and FDI=X"FB")) then
if FDEN='1' then
WDRQ<='1';
if WDRQ='1' then
E_WLOST<='1';
end if;
end if;
end if;
-- DRQ off
if CS_n='0' and A="11" then
if WE_n='1' then
-- Read
RDRQ<='0';
else
-- Write
WDRQ<='0';
end if;
end if;
end if;
end process;
--
-- Index Pulse Counter with ID check
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
IDXC<=(others=>'0');
IDXBUF<=(others=>'1');
RFND0<='0';
RFND<='0';
TFND<='0';
CMPT<='0';
elsif ZCLK'event and ZCLK='1' then
-- stand by
if CUR=VTRK0 then
TFND<='0';
CMPT<='0';
end if;
-- count or reset
IDXBUF<=IDXBUF(1 downto 0)&IP_n;
if CUR=RDAT0 or CUR=WDAT0 then
IDXC<=(others=>'0');
else
if IDXBUF(2 downto 1)="10" then
IDXC<=IDXC+'1';
end if;
end if;
-- find and compare ID
if FDEN='1' then
if CUR2=ID_TRK then
if FDR=TRACK then
RFND0<='1';
TFND<='1';
else
RFND0<='0';
TFND<='0';
end if;
CMPT<='1';
end if;
if CUR2=ID_HEAD then
if CFLAG='1' then
if FDR(0)/=SFLAG then
RFND0<='0';
end if;
end if;
end if;
if CUR2=ID_SECT then
if FDR=SECTOR then
if RFND0='1' then
IDXC<=(others=>'0');
end if;
else
RFND0<='0';
end if;
end if;
if CUR2=GAP2_2 then
RFND<=RFND0;
end if;
if CUR2=CRC2 then
RFND<='0';
end if;
end if;
end if;
end process;
--
-- Compatibility
--
DALI<=not DALI_n;
DALO_n<=not DALO when CS_n='0' and RE_n='0' else (others=>'0');
--
-- CPU Interface and State movement
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
STS<=(others=>'0');
E_SEEK<='0';
E_RNF<='0';
TRACK<=(others=>'0');
SECTOR<=X"01";
WDATA<=(others=>'0');
CUR<=IDLE;
DIRR<='0';
FDO<=(others=>'0');
elsif ZCLK'event and ZCLK='1' then
-- Registers
if CS_n='0' then
if WE_n='0' then
case A is
when "00" =>
if DALI(7 downto 4)="1101" then
if BUSY='0' then
STS<=DALI;
end if;
else
STS<=DALI;
end if;
when "01" =>
if BUSY='0' then
TRACK<=DALI;
end if;
when "10" =>
if BUSY='0' then
SECTOR<=DALI;
end if;
when others =>
if CUR=WDAT3 then
FDO<=DALI;
else
WDATA<=DALI;
end if;
end case;
end if;
end if;
-- State Machine
if CS_n='0' and WE_n='0' and A="00" and DALI(7 downto 4)="1101" then
CUR<=CMDQ; -- Force Interrupt
else
CUR<=NXT;
end if;
--
-- Save Step Direction
if CUR=SEEK1 or CUR=STEP1 or CUR=STIN1 or CUR=STOT1 then
DIRR<=DIRC0;
end if;
-- Seek Error
if CUR=SEEK0 or CUR=STEP0 or CUR=STIN0 or CUR=STOT0 then
E_SEEK<='0';
end if;
if CUR=VTRK_ER then
E_SEEK<='1';
end if;
-- Restore
if CUR=REST then
TRACK<=(others=>'1');
WDATA<=(others=>'0');
end if;
-- Step
if (UFLAG='1' and (CUR=STIN1 or (CUR=STEP1 and DIRC0='1'))) or (CUR=SEEK1 and DIRC0='1') then
TRACK<=TRACK+'1';
elsif (UFLAG='1' and (CUR=STOT1 or (CUR=STEP1 and DIRC0='0'))) or (CUR=SEEK1 and DIRC0='0') then
TRACK<=TRACK-'1';
end if;
if (DIRC0='0' and (CUR=SEEK2 or CUR=STEP2)) or CUR=STOT2 then
if TR00_n='0' then
TRACK<=(others=>'0');
end if;
end if;
-- Multi Read/Write
if CUR=RDAT5 or CUR=WDAT5 then
SECTOR<=SECTOR+'1';
end if;
-- Record Not Found Error
if CUR=RDAT0 or CUR=WDAT0 then
E_RNF<='0';
end if;
if CUR=RNF_ER then
E_RNF<='1';
end if;
-- Read Address function
if CUR=RADR2 and CUR2=ID_TRK then
SECTOR<=FDR;
end if;
end if;
end process;
VFLAG<=STS(2);
UFLAG<=STS(4);
CFLAG<=STS(1);
MFLAG<=STS(4);
SFLAG<=STS(3);
--
-- State Machine
--
process( CUR, CS_n, WE_n, A, DALI(7 downto 4), TR00_n, VFLAG, MOVING, TRACK, WDATA, CMPT, TFND, RFND, DIRR, IDXC, MFLAG, E_RLOST , E_WLOST ) begin
case CUR is
when IDLE =>
if CS_n='0' and WE_n='0' and A="00" then
case DALI(7 downto 4) is
when "0000" => NXT<=REST;
when "0001" => NXT<=SEEK0;
when "0010"|"0011" => NXT<=STEP0;
when "0100"|"0101" => NXT<=STIN0;
when "0110"|"0111" => NXT<=STOT0;
when "1000"|"1001" => NXT<=RDAT0;
when "1010"|"1011" => NXT<=WDAT0;
when "1100" => NXT<=RADR0;
when others => NXT<=IDLE;
end case;
else
NXT<=IDLE;
end if;
-- TYPE I / Restore command
when REST =>
NXT<=SEEK1;
-- TYPE I / Seek command
when SEEK0 =>
if TRACK=WDATA then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=SEEK1;
end if;
when SEEK1 =>
NXT<=SEEK2;
when SEEK2 =>
if MOVING='0' then
NXT<=SEEK0;
else
NXT<=SEEK2;
end if;
-- TYPE I / Step command
when STEP0 =>
if DIRR='0' and TR00_n='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STEP1;
end if;
when STEP1 =>
NXT<=STEP2;
when STEP2 =>
if MOVING='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STEP2;
end if;
-- TYPE I / Step In command
when STIN0 =>
NXT<=STIN1;
when STIN1 =>
NXT<=STIN2;
when STIN2 =>
if MOVING='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STIN2;
end if;
-- TYPE I / Step Out command
when STOT0 =>
if TR00_n='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STOT1;
end if;
when STOT1 =>
NXT<=STOT2;
when STOT2 =>
if MOVING='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STOT2;
end if;
-- Verify Track Number(TYPE I)
when VTRK0 =>
NXT<=VTRK1;
when VTRK1 =>
if CMPT='0' then
NXT<=VTRK1;
else
if TFND='0' then
NXT<=VTRK_ER;
else
NXT<=CMDQ;
end if;
end if;
when VTRK_ER =>
NXT<=CMDQ;
-- TYPE II / Read Data command
when RDAT0 =>
NXT<=RDAT1;
when RDAT1 =>
if CUR2=GAP1 then
NXT<=RDAT2;
else
NXT<=RDAT1;
end if;
when RDAT2 =>
if RFND='1' then
NXT<=RDAT3;
else
if IDXC="0110" then
NXT<=RNF_ER;
else
NXT<=RDAT2;
end if;
end if;
when RDAT3 =>
if E_RLOST='1' then
NXT<=CMDQ;
else
if CUR2=CRC2 then
NXT<=RDAT4;
else
NXT<=RDAT3;
end if;
end if;
when RDAT4 =>
if MFLAG='0' then
NXT<=CMDQ;
else
NXT<=RDAT5;
end if;
when RDAT5 =>
NXT<=RDAT0;
-- TYPE II / Write Data command
when WDAT0 =>
NXT<=WDAT1;
when WDAT1 =>
if CUR2=GAP1 then
NXT<=WDAT2;
else
NXT<=WDAT1;
end if;
when WDAT2 =>
if RFND='1' then
NXT<=WDAT3;
else
if IDXC="0110" then
NXT<=RNF_ER;
else
NXT<=WDAT2;
end if;
end if;
when WDAT3 =>
if E_WLOST='1' then
NXT<=CMDQ;
else
if CUR2=CRC2 then
NXT<=WDAT4;
else
NXT<=WDAT3;
end if;
end if;
when WDAT4 =>
if MFLAG='0' then
NXT<=CMDQ;
else
NXT<=WDAT5;
end if;
when WDAT5 =>
NXT<=WDAT0;
-- Record Not Found(TYPE II)
when RNF_ER =>
NXT<=CMDQ;
-- TYPE III / Read Address command
when RADR0 =>
NXT<=RADR1;
when RADR1 =>
if CUR2=GAP1 then
NXT<=RADR2;
else
NXT<=RADR1;
end if;
when RADR2 =>
if E_RLOST='1' then
NXT<=CMDQ;
else
-- if CUR2=CRC1_2 then
if CUR2=GAP2_2 then
-- NXT<=RADR3;
NXT<=CMDQ;
else
NXT<=RADR2;
end if;
end if;
-- when RADR3 =>
-- NXT<=RADR0;
when CMDQ =>
NXT<=IDLE;
when others =>
NXT<=IDLE;
end case;
end process;
--
-- State Action
--
-- Busy
BUSY<='0' when CUR=IDLE else '1';
-- Step Direction
process( CUR, TRACK, WDATA, DIRR ) begin
case CUR is
when SEEK0|SEEK1|SEEK2 =>
if TRACK>WDATA then
DIRC0<='0';
elsif TRACK<WDATA then
DIRC0<='1';
else
DIRC0<=DIRR;
end if;
when STEP0|STEP1|STEP2 =>
DIRC0<=DIRR;
when STIN0|STIN1|STIN2 =>
DIRC0<='1';
when STOT0|STOT1|STOT2 =>
DIRC0<='0';
when others=>
DIRC0<=DIRR;
end case;
end process;
-- Write Gate
WG<='1' when CUR=WDAT3 and (CUR2=DATA or CUR2=DATA_1 or (CUR2=SYNC2 and (FDI=X"FB" or FDR=X"FB"))) else '0';
DALO<= -- TYPE I Status
(not READY)&(not WPRT_n)&'1'&E_SEEK&'0'&(not TR00_n)&(not IP_n)&BUSY when A="00" and CS_n='0' and RE_n='0' and STS(7)='0' else
-- TYPE II Status
(not READY)&"00"&E_RNF&'0'&E_RLOST&RDRQ&BUSY when A="00" and CS_n='0' and RE_n='0' and (STS(7 downto 5)="100" or STS(7 downto 4)="1100") else
(not READY)&(not WPRT_n)&'0'&E_RNF&'0'&E_WLOST&WDRQ&BUSY when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 5)="101" else
-- TYPE III Status
-- (not READY)&"00"&E_RNF&'0'&E_RLOST&RDRQ&BUSY when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 4)="1100" else
-- TYPE IV Status
(not READY)&(not WPRT_n)&"100"&(not TR00_n)&(not IP_n)&'0' when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 4)="1101" else
-- Registers
TRACK when A="01" and CS_n='0' and RE_n='0' else
SECTOR when A="10" and CS_n='0' and RE_n='0' else
FDR when A="11" and CS_n='0' and RE_n='0' and RDRQ='1' else
WDATA when A="11" and CS_n='0' and RE_n='0' else
-- Not Access
"00000000";
DIRC<=DIRC0;
end RTL;

183
mz80b/mz1e05.vhd Normal file
View File

@@ -0,0 +1,183 @@
--
-- mz1e05.vhd
--
-- Floppy Disk Interface Emulation module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mz1e05 is
Port (
-- CPU Signals
ZRST_n : in std_logic;
ZCLK : in std_logic;
ZADR : in std_logic_vector(7 downto 0); -- CPU Address Bus(lower)
ZRD_n : in std_logic; -- CPU Read Signal
ZWR_n : in std_logic; -- CPU Write Signal
ZIORQ_n : in std_logic; -- CPU I/O Request
ZDI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
ZDO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
SCLK : in std_logic; -- Slow Clock
-- FD signals
DS_n : out std_logic_vector(4 downto 1); -- Drive Select
HS : out std_logic; -- Head Select
MOTOR_n : out std_logic; -- Motor On
INDEX_n : in std_logic; -- Index Hole Detect
TRACK00 : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP_n : out std_logic; -- Head Step In/Out
DIREC : out std_logic; -- Head Step Direction
WGATE_n : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end mz1e05;
architecture RTL of mz1e05 is
--
-- Signals
--
signal CSFDC_n : std_logic;
signal CSDC : std_logic;
signal CSDD : std_logic;
signal CSDE : std_logic;
signal DDEN : std_logic;
signal READY : std_logic;
signal STEP : std_logic;
signal DIRC : std_logic;
signal WG : std_logic;
signal RCOUNT : std_logic_vector(12 downto 0);
--
-- Component
--
component mb8876
Port (
-- CPU Signals
ZCLK : in std_logic;
MR_n : in std_logic;
A : in std_logic_vector(1 downto 0); -- CPU Address Bus
RE_n : in std_logic; -- CPU Read Signal
WE_n : in std_logic; -- CPU Write Signal
CS_n : in std_logic; -- CPU Chip Select
DALI_n : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
DALO_n : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- DALI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
-- DALO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- FD signals
DDEN_n : in std_logic; -- Double Density
IP_n : in std_logic; -- Index Pulse
READY : in std_logic; -- Drive Ready
TR00_n : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP : out std_logic; -- Head Step In/Out
DIRC : out std_logic; -- Head Step Direction
WG : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end component;
begin
--
-- Instantiation
--
FDC0 : mb8876 Port map(
-- CPU Signals
ZCLK => ZCLK,
MR_n => ZRST_n,
A => ZADR(1 downto 0), -- CPU Address Bus
RE_n => ZRD_n, -- CPU Read Signal
WE_n => ZWR_n, -- CPU Write Signal
CS_n => CSFDC_n, -- CPU Chip Select
DALI_n => ZDI, -- CPU Data Bus(in)
DALO_n => ZDO, -- CPU Data Bus(out)
-- DALI => ZDI, -- CPU Data Bus(in)
-- DALO => ZDO, -- CPU Data Bus(out)
-- FD signals
DDEN_n => DDEN, -- Double Density
IP_n => INDEX_n, -- Index Pulse
READY => READY, -- Drive Ready
TR00_n => TRACK00, -- Track 0
WPRT_n => WPRT_n, -- Write Protect
STEP => STEP, -- Head Step In/Out
DIRC => DIRC, -- Head Step Direction
WG => WG, -- Write Gate
DTCLK => DTCLK, -- Data Clock
FDI => FDI, -- Read Data
FDO => FDO -- Write Data
);
--
-- Registers
--
process( ZRST_n, ZCLK ) begin
if ZRST_n='0' then
MOTOR_n<='1';
HS<='0';
DS_n<="1111";
DDEN<='0';
elsif ZCLK'event and ZCLK='0' then
if ZWR_n='0' then
if CSDC='1' then
MOTOR_n<=not ZDI(7);
case ZDI(2 downto 0) is
when "100" => DS_n<="1110";
when "101" => DS_n<="1101";
when "110" => DS_n<="1011";
when "111" => DS_n<="0111";
when others => DS_n<="1111";
end case;
end if;
if CSDD='1' then
HS<=not ZDI(0);
end if;
if CSDE='1' then
DDEN<=ZDI(0);
end if;
end if;
end if;
end process;
CSFDC_n<='0' when ZIORQ_n='0' and ZADR(7 downto 2)="110110" else '1';
CSDC<='1' when ZIORQ_n='0' and ZADR=X"DC" else '0';
CSDD<='1' when ZIORQ_n='0' and ZADR=X"DD" else '0';
CSDE<='1' when ZIORQ_n='0' and ZADR=X"DE" else '0';
--
-- Ready Signal
--
process( ZRST_n, SCLK ) begin
if ZRST_n='0' then
RCOUNT<=(others=>'0');
READY<='0';
elsif SCLK'event and SCLK='0' then
if INDEX_n='0' then
RCOUNT<=(others=>'1');
else
if RCOUNT="0000000000000" then
READY<='0';
else
RCOUNT<=RCOUNT-'1';
READY<='1';
end if;
end if;
end if;
end process;
--
-- FDC signals
--
STEP_n<=not STEP;
DIREC<=not DIRC;
WGATE_n<=not WG;
end RTL;

767
mz80b/mz80b.vhd Normal file
View File

@@ -0,0 +1,767 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: mz80b.vhd
-- Created: August 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Business Computer:
-- Models MZ-80B, MZ-2000
--
-- This module is the main (top level) container for the Business MZ Computer
-- Emulation.
--
-- The design tries to work from top-down, where components which are common
-- to the Business and Personal MZ series are at the top (ie. main memory,
-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
-- to the machine specific modules and components. Some components are common
-- by their nature (ie. 8255 PIO) but these are instantiated within the lower
-- tree branch as their design use is less generic.
--
-- The tree is as follows;-
--
-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
-- |
-- |
-- | -> cmt.vhd (common)
-- | -> keymatrix.vhd (common)
-- | -> pll.v (common)
-- | -> clkgen.vhd (common)
-- | -> T80 (common)
-- | -> i8255 (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- | -> i8254 (common)
-- | -> dpram.vhd (common)
-- | -> dprom.vhd (common)
-- | -> mctrl.vhd (common)
-- | -> video.vhd (common)
-- |
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd
--
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: August 2018 - Initial module created.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.config_pkg.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity mz80b is
PORT (
-- Clocks
CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module.
-- Resets.
COLD_RESET : in std_logic;
SYSTEM_RESET : in std_logic;
-- Z80 CPU
T80_RST_n : in std_logic;
T80_WAIT_n : out std_logic;
T80_INT_n : out std_logic;
T80_NMI_n : out std_logic;
T80_BUSRQ_n : out std_logic;
T80_M1_n : in std_logic;
T80_MREQ_n : in std_logic;
T80_IORQ_n : in std_logic;
T80_RD_n : in std_logic;
T80_WR_n : in std_logic;
T80_RFSH_n : in std_logic;
T80_HALT_n : in std_logic;
T80_BUSAK_n : in std_logic;
T80_A16 : in std_logic_vector(15 downto 0);
T80_DI : out std_logic_vector(7 downto 0);
T80_DO : in std_logic_vector(7 downto 0);
-- Chip selects to common resources.
CS_ROM_n : out std_logic; -- ROM Select
CS_RAM_n : out std_logic; -- RAM Select
CS_VRAM_n : out std_logic; -- VRAM Select
CS_GRAM_n : out std_logic; -- Colour Graphics GRAM Select
CS_GRAM_80B_n : out std_logic; -- MZ80B GRAM Option Select
CS_IO_GFB_n : out std_logic; -- Graphics Framebuffer IO Select range
CS_IO_G_n : out std_logic; -- Graphics Options IO Select range
CS_SWP_MEMBANK_n : out std_logic; -- Move lower 32K into upper block.
-- Audio.
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- I/O -- I/O down to the core.
KEYB_SCAN : out std_logic_vector(3 downto 0); -- Keyboard scan lines out.
KEYB_DATA : in std_logic_vector(7 downto 0); -- Keyboard scan data in.
KEYB_STALL : out std_logic; -- Keyboard Stall out.
KEYB_BREAKDETECT : in std_logic; -- Keyboard break detect.
-- Cassette magnetic tape signals.
CMT_BUS_OUT : in std_logic_vector(CMT_BUS_OUT_WIDTH);
CMT_BUS_IN : out std_logic_vector(CMT_BUS_IN_WIDTH);
-- Video signals
VGATE_n : out std_logic; -- Video Gate enable.
INVERSE_n : out std_logic; -- Invert video output.
CONFIG_CHAR80 : out std_logic; -- 40 Char = 0, 80 Char = 1 select.
HBLANK : in std_logic; -- Horizontal Blanking Signal
VBLANK : in std_logic; -- Vertical Blanking Signal
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0); -- HPS Data to be read into HPS.
-- Debug Status Leds
DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status.
);
end mz80b;
architecture rtl of mz80b is
--
-- Decodes, misc
--
signal BOOTSTRAP_n : std_logic; -- Memory select, Low = ROM 0000 - 07FF, High = RAM 0000 - 7FFF
signal SEL_VRAM_ENABLE : std_logic; -- Enable VRAM/GRAM = 1.
signal SEL_VRAM_HIGHADDR : std_logic; -- Select VRAM as High (D000-FFFF) address, Low (5000-7FFF)
signal BST_n : std_logic;
signal NST : std_logic;
signal MZ_GRAM_ENABLE : std_logic;
signal CS_VRAM_ni : std_logic;
signal CS_IO_8255_n : std_logic;
signal CS_IO_8254_n : std_logic;
signal CS_IO_8254_RST_CLK_n : std_logic;
signal CS_IO_Z80PIO_n : std_logic;
signal CS_GRAM_ni : std_logic;
signal CS_GRAM_80B_ni : std_logic;
signal CS_IO_GRAMENABLE_n : std_logic;
signal CS_IO_GRAMDISABLE_n : std_logic;
signal CS_IO_GFB_ni : std_logic;
signal CS_IO_G_ni : std_logic;
signal CS_ROM_ni : std_logic;
signal CS_RAM_ni : std_logic;
signal T80_INT_ni : std_logic;
signal IRQ_CMT : std_logic;
signal IRQ_FDD : std_logic;
--
-- PPI
--
signal PPI_DO : std_logic_vector(7 downto 0);
signal i8255_PA_O : std_logic_vector(7 downto 0);
signal i8255_PA_OE_n : std_logic_vector(7 downto 0);
signal i8255_PB_I : std_logic_vector(7 downto 0);
signal i8255_PB_O : std_logic_vector(7 downto 0);
signal i8255_PC_O : std_logic_vector(7 downto 0);
signal i8255_PC_OE_n : std_logic_vector(7 downto 0);
--
-- PIT
--
signal PIT_DO : std_logic_vector(7 downto 0);
--
-- PIO
--
signal PIO_DO : std_logic_vector(7 downto 0);
signal Z80PIO_INT_n : std_logic;
signal Z80PIO_PA : std_logic_vector(7 downto 0);
signal Z80PIO_PB : std_logic_vector(7 downto 0);
--
-- Clocks
--
signal CASCADE01 : std_logic;
signal CASCADE12 : std_logic;
--
-- Video
--
signal HBLANKi : std_logic;
signal VBLANKi : std_logic;
signal HSYNC_ni : std_logic;
signal VSYNC_ni : std_logic;
signal Ri : std_logic;
signal Gi : std_logic;
signal Bi : std_logic;
signal VGATE_ni : std_logic; -- Video Outpu Enable
signal VRAM_DO : std_logic_vector(7 downto 0);
--
-- Keyboard.
--
signal LED_RVS : std_logic;
signal LED_GRPH : std_logic;
signal LED_SHIFT_LOCK : std_logic;
--
-- Audio
--
signal SOUND : std_logic;
--
-- FDD,FDC
--
signal DOFDC : std_logic_vector(7 downto 0);
signal DS : std_logic_vector(3 downto 0);
signal HS : std_logic;
signal MOTOR_n : std_logic;
signal INDEX_n : std_logic;
signal TRACK00_n : std_logic;
signal WPRT_n : std_logic;
signal STEP_n : std_logic;
signal DIREC : std_logic;
signal FDO : std_logic_vector(7 downto 0);
signal FDI : std_logic_vector(7 downto 0);
signal WGATE_n : std_logic;
signal DTCLK : std_logic;
--
-- Debug
--
signal PULSECPU : std_logic;
--
-- Components
--
component i8255
port (
RESET : in std_logic;
CLK : in std_logic;
ENA : in std_logic; -- (CPU) clk enable
ADDR : in std_logic_vector(1 downto 0); -- A1-A0
DI : in std_logic_vector(7 downto 0); -- D7-D0
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
PA_I : in std_logic_vector(7 downto 0);
PA_O : out std_logic_vector(7 downto 0);
PA_O_OE_n : out std_logic_vector(7 downto 0);
PB_I : in std_logic_vector(7 downto 0);
PB_O : out std_logic_vector(7 downto 0);
PB_O_OE_n : out std_logic_vector(7 downto 0);
PC_I : in std_logic_vector(7 downto 0);
PC_O : out std_logic_vector(7 downto 0);
PC_O_OE_n : out std_logic_vector(7 downto 0)
);
end component;
component i8254
Port (
RST : in std_logic;
CLK : in std_logic;
ENA : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
WR_n : in std_logic;
RD_n : in std_logic;
CLK0 : in std_logic;
GATE0 : in std_logic;
OUT0 : out std_logic;
CLK1 : in std_logic;
GATE1 : in std_logic;
OUT1 : out std_logic;
CLK2 : in std_logic;
GATE2 : in std_logic;
OUT2 : out std_logic
);
end component;
component z8420
Port (
-- System
RST_n : in std_logic; -- Only Power On Reset
-- Z80 Bus Signals
CLK : in std_logic;
ENA : in std_logic;
BASEL : in std_logic;
CDSEL : in std_logic;
CE : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
IORQ_n : in std_logic;
M1_n : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
IEI : in std_logic;
IEO : out std_logic;
INT_n : out std_logic;
-- Port
A : out std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0)
);
end component;
begin
--
-- Instantiation
--
-- 8255 Used for Tape Control and interfacing and system boot control.
--
PPI0B : i8255
port map (
RESET => SYSTEM_RESET,
CLK => CLKBUS(CKMASTER),
ENA => CLKBUS(CKENCPU),
ADDR => T80_A16(1 downto 0),
DI => T80_DO,
DO => PPI_DO,
CS_n => CS_IO_8255_n,
RD_n => T80_RD_n,
WR_n => T80_WR_n,
PA_I => i8255_PA_O,
PA_O => i8255_PA_O,
PA_O_OE_n => i8255_PA_OE_n,
PB_I => i8255_PB_I,
PB_O => open,
PB_O_OE_n => open,
PC_I => i8255_PC_O,
PC_O => i8255_PC_O,
PC_O_OE_n => i8255_PC_OE_n
);
-- 8253 Timer used for the real time clock.
--
PIT0 : i8254
port map (
RST => SYSTEM_RESET,
CLK => CLKBUS(CKMASTER),
ENA => CLKBUS(CKENCPU),
A => T80_A16(1 downto 0),
DI => T80_DO,
DO => PIT_DO,
CS_n => CS_IO_8254_n,
WR_n => T80_WR_n,
RD_n => T80_RD_n,
CLK0 => CLKBUS(CKRTC),
GATE0 => CS_IO_8254_RST_CLK_n,
OUT0 => CASCADE01,
CLK1 => CASCADE01,
GATE1 => CS_IO_8254_RST_CLK_n,
OUT1 => CASCADE12,
CLK2 => CASCADE12,
GATE2 => '1',
OUT2 => open
);
-- Z80 PIO used for keyboard, RAM and Video control.
--
PIO0 : z8420
port map (
-- System
RST_n => T80_RST_n, -- Only Power On Reset
-- Z80 Bus Signals
CLK => CLKBUS(CKMASTER),
ENA => CLKBUS(CKENCPU),
BASEL => T80_A16(1),
CDSEL => T80_A16(0),
CE => CS_IO_Z80PIO_n,
RD_n => T80_RD_n,
WR_n => T80_WR_n,
IORQ_n => T80_IORQ_n,
M1_n => T80_M1_n and T80_RST_n,
DI => T80_DO,
DO => PIO_DO,
IEI => '1',
IEO => open,
INT_n => Z80PIO_INT_n,
A => Z80PIO_PA,
B => Z80PIO_PB
);
-- A1 clocked by C5, if A1 = L when C5 (SEEK) pulses high, then tape rewinds on activation of A0. If A1 is high, then
-- tape will fast forward. A0, when pulsed high, activates the motor to go forward/backward.
-- A2 pulsed high activates the play motor.which cancels a FF/REW event.
-- A3 when High, stops the Play/FF/REW events.
-- B5 when high indicates tape drive present and ready.
-- C4 when Low, ejects the tape.
-- C6 when Low enables record, otherwise whe High enables play.
-- C7 is the data to write to tape.
-- B6 is the data read from tape.
-- BW ehn Low blocks recording.
-- PPI Port A - Output connections.
--
LED_RVS <= i8255_PA_O(7) when i8255_PA_OE_n(7) = '0'
else '0';
LED_GRPH <= i8255_PA_O(6) when i8255_PA_OE_n(6) = '0'
else '0';
LED_SHIFT_LOCK <= i8255_PA_O(5) when i8255_PA_OE_n(5) = '0'
else '0';
INVERSE_n <= i8255_PA_O(4) when i8255_PA_OE_n(4) = '0'
else '1';
CMT_BUS_IN(STOP) <= i8255_PA_O(3) when i8255_PA_OE_n(3) = '0'
else '0';
CMT_BUS_IN(PLAY) <= i8255_PA_O(2) when i8255_PA_OE_n(2) = '0'
else '0';
CMT_BUS_IN(DIRECTION) <= i8255_PA_O(1) when i8255_PA_OE_n(1) = '0'
else '0';
CMT_BUS_IN(REEL_MOTOR) <= i8255_PA_O(0) when i8255_PA_OE_n(0) = '0'
else '0';
-- PPI Port B - Input connections.
--
i8255_PB_I(7) <= KEYB_BREAKDETECT;
i8255_PB_I(6) <= CMT_BUS_OUT(WRITEBIT); -- Tape is loaded in deck when L (0).
i8255_PB_I(5) <= CMT_BUS_OUT(TAPEREADY); -- Tape is loaded in deck when L (0).
i8255_PB_I(4) <= CMT_BUS_OUT(WRITEREADY); -- Prohibit Write when L (0).
i8255_PB_I(3 downto 1) <= (others => '1');
i8255_PB_I(0) <= VBLANK;
-- PPI Port C - Output connections. Feed output to input to be able to read latched value.
--
CMT_BUS_IN(READBIT) <= i8255_PC_O(7) when i8255_PC_OE_n(7) = '0'
else '0';
CMT_BUS_IN(WRITEENABLE) <= i8255_PC_O(6) when i8255_PC_OE_n(6) = '0'
else '0';
CMT_BUS_IN(SEEK) <= i8255_PC_O(5) when i8255_PC_OE_n(5) = '0'
else '0';
CMT_BUS_IN(EJECT) <= i8255_PC_O(4) when i8255_PC_OE_n(4) = '0'
else '0';
BST_n <= i8255_PC_O(3) when i8255_PC_OE_n(3) = '0'
else '1';
SOUND <= i8255_PC_O(2) when i8255_PC_OE_n(2) = '0'
else '0';
NST <= i8255_PC_O(1) when i8255_PC_OE_n(1) = '0'
else '0';
VGATE_ni <= i8255_PC_O(0) when i8255_PC_OE_n(0) = '0'
else '1';
-- Z80 PIO Port A - Output.
--
SEL_VRAM_ENABLE <= Z80PIO_PA(7);
SEL_VRAM_HIGHADDR <= Z80PIO_PA(6);
CONFIG_CHAR80 <= Z80PIO_PA(5);
KEYB_STALL <= Z80PIO_PA(4);
KEYB_SCAN <= Z80PIO_PA(3 downto 0);
-- Z80 PIO Port B - Input - Keyboard data.
--
Z80PIO_PB <= KEYB_DATA;
-- Parent signals onto local wires.
--
T80_BUSRQ_n <= '1';
T80_NMI_n <= '1';
T80_WAIT_n <= '1';
--
-- MZ-80B - Interrupts from the Z80PIO or external sources.
T80_INT_ni <= '0' when Z80PIO_INT_n = '0'
else '1';
T80_INT_n <= T80_INT_ni;
--
-- Data Bus Multiplexing, plex all the output devices onto the Z80 Data Input according to the CS.
--
T80_DI <= PPI_DO when CS_IO_8255_n ='0' and T80_RD_n = '0' -- Read from 8255
else
PIT_DO when CS_IO_8254_n ='0' and T80_RD_n = '0' -- Read from 8254
else
PIO_DO when CS_IO_Z80PIO_n='0' and T80_RD_n = '0' -- Read from Z80PIO
else
(others=>'1');
-- HPS Bus Multiplexing for reads.
IOCTL_DIN <= "00000000111111111100110010101010"; -- Test pattern.
--
-- Chip Select map.
--
-- 0000 - FFFF : MZ80B/2000 unless portion paged out by below selects.
-- 5000 - 5FFF : MZ80B = Alternate VRAM location
-- 6000 - 7FFF : MZ80B = Alternate GRAM location
-- C000 - FFFF : MZ2000 = GRAM
-- D000 - DFFF : MZ80B/2000 = VRAM
-- E000 - FFFF : MZ80B = GRAM
--
--
-- Video RAM Select.
-- 5000 - 5FFF
-- D000 - DFFF
CS_VRAM_ni <= -- D000 - DFFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "1101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
else
-- 5000 - 5FFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "0101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
else
-- D000 - DFFF
'0' when CONFIG(MZ2000) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "1101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
else '1';
-- MZ80B/2000 Graphics RAM Select.
--
CS_GRAM_80B_ni <= -- E000 - FFFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 13) = "111" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
else
-- 6000 - 7FFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 13) = "011" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
else
-- C000 - FFFF
'0' when CONFIG(MZ2000) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 14) = "11" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
else '1';
-- Colour frame buffer.
-- C000 - FFFF
--
CS_GRAM_ni <= '0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and MZ_GRAM_ENABLE = '1' and T80_A16(15 downto 14) = "11" and T80_MREQ_n='0'
else '1';
-- Boot ROM. Enabled only at startup when
--
-- 0000 -> 07FF when in IPL mode.
CS_ROM_ni <= '0' when BOOTSTRAP_n = '0' and T80_A16(15 downto 11) = "00000" and T80_MREQ_n = '0'
else '1';
--
CS_RAM_ni <= '0' when BOOTSTRAP_n = '0' and T80_A16(15) = '1' and CS_VRAM_ni = '1' and CS_GRAM_ni = '1' and CS_GRAM_80B_ni = '1' and T80_MREQ_n = '0'
else
'0' when BOOTSTRAP_n = '1' and CS_VRAM_ni = '1' and CS_GRAM_ni = '1' and CS_GRAM_80B_ni = '1' and T80_MREQ_n = '0'
else '1';
--
-- IO Select Map.
-- E0 - EF are used by the MZ80B/2000 to perform memory switching and graphics control.
-- F0-F3 write is used to set the gates of the 8254
-- F4-F7 is used to control the graphics options.
-- F8 is used to write the MSB of the Rom Expansion
-- F9 is used to write the LSB of the Rom Expansion and to read the data byte back.
--
-- IO Range for Graphics enhancements is set by the MCTRL DISPLAY2{7:3] register.
-- x[0|8],<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
-- x[1|9],<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- x[2|A],<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- x[3|B],<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- x[4|C] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. This overrides all MZ700 page switching functions.
-- x[5|D] switches out the graphics ram and returns to previous state.
--
CS_IO_8255_n <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111000" -- IO E0-E3 = 8255
else '1';
CS_IO_8254_n <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111001" -- IO E4-E7 = 8254
else '1';
CS_IO_Z80PIO_n <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111010" -- IO E8-EB = Z80PIO
else '1';
CS_IO_8254_RST_CLK_n<= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111100" and T80_WR_n = '0' -- IO F0-F3 = 8254 Clock reset.
else '1';
CS_IO_G_ni <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111101" and T80_WR_n = '0' -- IO Range for Graphics framebuffer register controlled by mctrl register.
else '1';
CS_IO_GFB_ni <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 3) = CONFIG(GRAMIOADDR) and T80_WR_n = '0' -- IO Range for Graphics framebuffer register controlled by mctrl register.
else '1';
CS_IO_GRAMENABLE_n <= '0' when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "100" -- IO Addr base+4 sets C000 -> FFFF map to Graphics RAM.
else '1';
CS_IO_GRAMDISABLE_n <= '0' when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "101" -- IO Addr base+5 sets C000 -> FFFF revert to previous mode.
else '1';
-- Send signals to module interface.
--
CS_ROM_n <= CS_ROM_ni;
CS_RAM_n <= CS_RAM_ni;
CS_VRAM_n <= CS_VRAM_ni;
CS_GRAM_n <= CS_GRAM_ni;
CS_GRAM_80B_n <= CS_GRAM_80B_ni;
CS_IO_GFB_n <= CS_IO_GFB_ni;
CS_IO_G_n <= CS_IO_G_ni;
CS_SWP_MEMBANK_n <= BOOTSTRAP_n;
VGATE_n <= VGATE_ni;
-- On initial reset, BOOTSTRAP_n is set active, a reset setup and hold takes place, then the processor is set running with the
-- IPL monitor rom at 0000-07ff.
-- If NST goes High (due to the IPL setting it), then a flip flop is clocked setting BOOTSTRAP_n to inactive which places RAM
-- into the normal running state at 0000-7fff and the IPL monitor rom is disabled.
-- BOOT_RESET (external input) or BST_n when Low sets the BOOTSTRAP_n so that IPL mode is entered and the IPL monitor rom
-- is active at 0000.
--
process( COLD_RESET, CONFIG(BOOT_RESET), BST_n, CLKBUS(CKMASTER), NST )
begin
-- A cold reset sets up the initial state, further resets just reset variables as needed.
--
if COLD_RESET = '1' then
BOOTSTRAP_n <= '0';
elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
if CLKBUS(CKENCPU) = '1' then
if CONFIG(BOOT_RESET) = '1' or BST_n = '0' then
-- Only a boot reset or BST_n can set the BOOTSTRAP signal. A system reset just
-- resets the cpu and peripherals.
--
if CONFIG(BOOT_RESET) = '1' or BST_n = '0' then
BOOTSTRAP_n <= '0';
end if;
else
-- If the NST signal goes high, then reset the BOOTSTRAP signal. This signal can only be set
-- by a reset action.
--
if NST = '1' then
BOOTSTRAP_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- Graphics Ram - Latch wether to enable Graphics RAM page from C000 - FFFF.
--
process( SYSTEM_RESET, CLKBUS(CKMASTER), CS_IO_GRAMENABLE_n, CS_IO_GRAMDISABLE_n ) begin
if(SYSTEM_RESET = '1') then
MZ_GRAM_ENABLE <= '0';
elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
if CLKBUS(CKENCPU) = '1' then
if(CS_IO_GRAMENABLE_n = '0') then
MZ_GRAM_ENABLE <= '0';
elsif(CS_IO_GRAMDISABLE_n = '0') then
MZ_GRAM_ENABLE <= '0';
end if;
end if;
end if;
end process;
-- Audio output. Choose between generated sound and CMT pulse audio.
--
AUDIO_L <= SOUND when CONFIG(AUDIOSRC) = '0' -- Sound Output Left
else
CMT_BUS_OUT(WRITEBIT);
AUDIO_R <= SOUND when CONFIG(AUDIOSRC) = '0' -- Sound Output Right
else
CMT_BUS_OUT(READBIT);
-- Only enable debugging LEDS if enabled in the config package.
--
DEBUG80B: if DEBUG_ENABLE = 1 generate
-- A simple 1*cpufreq second pulse to indicate accuracy of CPU frequency for debug purposes..
--
process (SYSTEM_RESET, CLKBUS(CKMASTER))
variable cnt : integer range 0 to 1999999 := 0;
begin
if SYSTEM_RESET = '1' then
PULSECPU <= '0';
cnt := 0;
elsif rising_edge(CLKBUS(CKMASTER)) then
if CLKBUS(CKENCPU) = '1' then
cnt := cnt + 1;
if cnt = 0 then
PULSECPU <= not PULSECPU;
end if;
end if;
end if;
end process;
-- Debug leds.
--
DEBUG_STATUS_LEDS(0) <= CS_VRAM_ni;
DEBUG_STATUS_LEDS(1) <= CS_GRAM_ni;
DEBUG_STATUS_LEDS(2) <= CS_GRAM_80B_ni;
DEBUG_STATUS_LEDS(3) <= CS_IO_8255_n;
DEBUG_STATUS_LEDS(4) <= CS_IO_8254_n;
DEBUG_STATUS_LEDS(5) <= CS_IO_Z80PIO_n;
DEBUG_STATUS_LEDS(6) <= CS_ROM_ni;
DEBUG_STATUS_LEDS(7) <= CS_RAM_ni;
--
DEBUG_STATUS_LEDS(8) <= '0';
DEBUG_STATUS_LEDS(9) <= CS_IO_8254_RST_CLK_n;
DEBUG_STATUS_LEDS(10) <= CS_IO_GRAMENABLE_n;
DEBUG_STATUS_LEDS(11) <= CS_IO_GRAMDISABLE_n;
DEBUG_STATUS_LEDS(12) <= CS_IO_GFB_ni;
DEBUG_STATUS_LEDS(13) <= CS_IO_G_ni;
DEBUG_STATUS_LEDS(14) <= '0';
DEBUG_STATUS_LEDS(15) <= '0';
--
DEBUG_STATUS_LEDS(16) <= BST_n;
DEBUG_STATUS_LEDS(17) <= NST;
DEBUG_STATUS_LEDS(18) <= MZ_GRAM_ENABLE;
DEBUG_STATUS_LEDS(19) <= BOOTSTRAP_n;
DEBUG_STATUS_LEDS(20) <= SEL_VRAM_ENABLE;
DEBUG_STATUS_LEDS(21) <= SEL_VRAM_HIGHADDR;
DEBUG_STATUS_LEDS(22) <= VGATE_ni;
DEBUG_STATUS_LEDS(23) <= CONFIG(BOOT_RESET);
--
DEBUG_STATUS_LEDS(24) <= PULSECPU;
DEBUG_STATUS_LEDS(25) <= T80_INT_ni;
DEBUG_STATUS_LEDS(26) <= '0';
DEBUG_STATUS_LEDS(27) <= COLD_RESET;
DEBUG_STATUS_LEDS(28) <= SYSTEM_RESET;
DEBUG_STATUS_LEDS(29) <= '0';
DEBUG_STATUS_LEDS(30) <= CONFIG(BOOT_RESET);
DEBUG_STATUS_LEDS(31) <= BST_n;
--
DEBUG_STATUS_LEDS(32) <= LED_RVS;
DEBUG_STATUS_LEDS(33) <= LED_GRPH;
DEBUG_STATUS_LEDS(34) <= LED_SHIFT_LOCK;
DEBUG_STATUS_LEDS(35) <= '0';
DEBUG_STATUS_LEDS(36) <= '0';
DEBUG_STATUS_LEDS(37) <= CASCADE01;
DEBUG_STATUS_LEDS(38) <= CASCADE12;
DEBUG_STATUS_LEDS(39) <= PULSECPU;
--
DEBUG_STATUS_LEDS(40) <= i8255_PA_O(0);
DEBUG_STATUS_LEDS(41) <= i8255_PA_O(1);
DEBUG_STATUS_LEDS(42) <= i8255_PA_O(2);
DEBUG_STATUS_LEDS(43) <= i8255_PA_O(3);
DEBUG_STATUS_LEDS(44) <= i8255_PA_O(4);
DEBUG_STATUS_LEDS(45) <= i8255_PA_O(5);
DEBUG_STATUS_LEDS(46) <= i8255_PA_O(6);
DEBUG_STATUS_LEDS(47) <= i8255_PA_O(7);
--
DEBUG_STATUS_LEDS(48) <= i8255_PB_I(0);
DEBUG_STATUS_LEDS(49) <= i8255_PB_I(1);
DEBUG_STATUS_LEDS(50) <= i8255_PB_I(2);
DEBUG_STATUS_LEDS(51) <= i8255_PB_I(3);
DEBUG_STATUS_LEDS(52) <= i8255_PB_I(4);
DEBUG_STATUS_LEDS(53) <= i8255_PB_I(5);
DEBUG_STATUS_LEDS(54) <= i8255_PB_I(6);
DEBUG_STATUS_LEDS(55) <= i8255_PB_I(7);
--
DEBUG_STATUS_LEDS(56) <= i8255_PC_O(0);
DEBUG_STATUS_LEDS(57) <= i8255_PC_O(1);
DEBUG_STATUS_LEDS(58) <= i8255_PC_O(2);
DEBUG_STATUS_LEDS(59) <= i8255_PC_O(3);
DEBUG_STATUS_LEDS(60) <= i8255_PC_O(4);
DEBUG_STATUS_LEDS(61) <= i8255_PC_O(5);
DEBUG_STATUS_LEDS(62) <= i8255_PC_O(6);
DEBUG_STATUS_LEDS(63) <= i8255_PC_O(7);
-- LEDS 64 .. 112 are available.
DEBUG_STATUS_LEDS(111 downto 64) <= (others => '0');
end generate;
end rtl;

169
mz80b/mz80b_dummy.vhd Normal file
View File

@@ -0,0 +1,169 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: mz80b.vhd
-- Created: August 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Business Computer:
-- Models MZ-80B, MZ-2000
--
-- This module is the main (top level) container for the Business MZ Computer
-- Emulation.
--
-- The design tries to work from top-down, where components which are common
-- to the Business and Personal MZ series are at the top (ie. main memory,
-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
-- to the machine specific modules and components. Some components are common
-- by their nature (ie. 8255 PIO) but these are instantiated within the lower
-- tree branch as their design use is less generic.
--
-- The tree is as follows;-
--
-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
-- |
-- |
-- | -> cmt.vhd (common)
-- | -> keymatrix.vhd (common)
-- | -> pll.v (common)
-- | -> clkgen.vhd (common)
-- | -> T80 (common)
-- | -> i8255 (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- | -> i8253 (common)
-- | -> dpram.vhd (common)
-- | -> dprom.vhd (common)
-- | -> mctrl.vhd (common)
-- | -> video.vhd (common)
-- |
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development)
--
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: August 2018 - Initial module created.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity mz80b is
PORT (
-- Clocks
CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module.
-- Resets.
SYSTEM_RESET : in std_logic;
-- Z80 CPU
T80_RST_n : in std_logic;
T80_CLK : in std_logic;
T80_CLKEN : out std_logic;
T80_WAIT_n : out std_logic;
T80_INT_n : out std_logic;
T80_NMI_n : out std_logic;
T80_BUSRQ_n : out std_logic;
T80_M1_n : in std_logic;
T80_MREQ_n : in std_logic;
T80_IORQ_n : in std_logic;
T80_RD_n : in std_logic;
T80_WR_n : in std_logic;
T80_RFSH_n : in std_logic;
T80_HALT_n : in std_logic;
T80_BUSAK_n : in std_logic;
T80_A16 : in std_logic_vector(15 downto 0);
T80_DI : out std_logic_vector(7 downto 0);
T80_DO : in std_logic_vector(7 downto 0);
-- Chip selects to common resources.
CS_ROM_n : out std_logic; -- ROM Select
CS_RAM_n : out std_logic; -- RAM Select
CS_VRAM_n : out std_logic; -- VRAM Select
CS_MEM_G_n : out std_logic; -- Memory mapped Peripherals Select
CS_GRAM_n : out std_logic; -- GRAM Select
CS_GRAM_80B_n : out std_logic; -- GRAM Select
CS_IO_G_n : out std_logic; -- Graphics FB IO Select range
CS_SWP_MEMBANK_n : out std_logic;
-- Audio.
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- I/O -- I/O down to the core.
KEYB_SCAN : out std_logic_vector(3 downto 0); -- Keyboard scan lines out.
KEYB_DATA : in std_logic_vector(7 downto 0); -- Keyboard scan data in.
KEYB_STALL : out std_logic; -- Keyboard Stall out.
-- Cassette magnetic tape signals.
CMT_BUS_OUT : in std_logic_vector(CMT_BUS_OUT_WIDTH);
CMT_BUS_IN : out std_logic_vector(CMT_BUS_IN_WIDTH);
-- Video signals
VGATE_n : out std_logic; -- Video Gate enable.
INVERSE : out std_logic; -- Invert video output.
CHAR80 : out std_logic; --
HBLANK : in std_logic; -- Horizontal Blanking Signal
VBLANK : in std_logic; -- Vertical Blanking Signal
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
-- Debug Status Leds
DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status.
);
end mz80b;
architecture rtl of mz80b is
begin
T80_CLKEN <= '1';
T80_WAIT_n <= '1';
T80_INT_n <= '1';
T80_NMI_n <= '1';
T80_BUSRQ_n <= '1';
T80_DI <= (others => '0');
CS_ROM_n <= '1';
CS_RAM_n <= '1';
CS_VRAM_n <= '1';
CS_MEM_G_n <= '1';
CS_GRAM_n <= '1';
CS_GRAM_80B_n <= '1';
CS_IO_G_n <= '1';
CS_SWP_MEMBANK_n <= '1';
AUDIO_L <= '1';
AUDIO_R <= '1';
VGATE_n <= '1';
INVERSE <= '0';
CHAR80 <= '0';
CMT_BUS_IN(MOTORON)<= '0';
CMT_BUS_IN(READBIT)<= '0';
IOCTL_DIN <= (others => '0');
DEBUG_STATUS_LEDS <= (others => '0');
end rtl;

647
mz80b/mz80b_video.vhd Normal file
View File

@@ -0,0 +1,647 @@
--
-- mz80b_video.vhd
--
-- Video display signal generator
-- for MZ-80B on FPGA
--
-- Nibbles Lab. 2013-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mz80b_video is
Port (
RST_n : in std_logic; -- Reset
BOOTM : in std_logic; -- BOOT Mode
-- Type of machine we are emulating.
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
-- Type of display to emulate.
DISPLAY_NORMAL : in std_logic;
DISPLAY_NIDECOM : in std_logic;
DISPLAY_GAL5 : in std_logic;
DISPLAY_COLOUR : in std_logic;
-- Different operations modes.
CONFIG_PCGRAM : in std_logic; -- PCG Mode Switch, 0 = CGROM, 1 = CGRAM.
-- Clocks
CK16M : in std_logic; -- 15.6kHz Dot Clock(16MHz)
T80_CLK_n : in std_logic; -- Z80 Current Clock
T80_CLK : in std_logic; -- Z80 Current Clock Inverted
-- CPU Signals
T80_A : in std_logic_vector(13 downto 0); -- CPU Address Bus
CSV_n : in std_logic; -- CPU Memory Request(VRAM)
CSG_n : in std_logic; -- CPU Memory Request(GRAM)
T80_RD_n : in std_logic; -- CPU Read Signal
T80_WR_n : in std_logic; -- CPU Write Signal
T80_MREQ_n : in std_logic; -- CPU Memory Request
T80_BUSACK_n : in std_logic; -- CPU Bus Acknowledge
T80_WAIT_n : out std_logic; -- CPU Wait Request
T80_DI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
T80_DO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- Graphic VRAM Access
GCS_n : out std_logic; -- GRAM Request
GADR : out std_logic_vector(20 downto 0); -- GRAM Address
GT80_WR_n : out std_logic; -- GRAM Write Signal
GBE_n : out std_logic_vector(3 downto 0); -- GRAM Byte Enable
GDI : in std_logic_vector(31 downto 0); -- Data Bus Input from GRAM
GDO : out std_logic_vector(31 downto 0); -- Data Bus Output to GRAM
-- Video Control from outside
INV : in std_logic; -- Reverse mode(8255 PA4)
VGATE : in std_logic; -- Video Output Control(8255 PC0)
CH80 : in std_logic; -- Text Character Width(Z80PIO A5)
-- Video Signals
VGATE_n : in std_logic; -- Video Output Control
HBLANK : out std_logic; -- Horizontal Blanking
VBLANK : out std_logic; -- Vertical Blanking
HSYNC_n : out std_logic; -- Horizontal Sync
VSYNC_n : out std_logic; -- Vertical Sync
ROUT : out std_logic; -- Red Output
GOUT : out std_logic; -- Green Output
BOUT : out std_logic; -- Green Output
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0) -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end mz80b_video;
architecture RTL of mz80b_video is
--
-- Registers
--
signal DIV : std_logic_vector(8 downto 0); -- Clock Divider
signal HCOUNT : std_logic_vector(9 downto 0); -- Counter for Horizontal Signals
signal VCOUNT : std_logic_vector(8 downto 0); -- Counter for Vertical Signals
signal VADR : std_logic_vector(10 downto 0); -- VRAM Address(selected)
signal VADRC : std_logic_vector(10 downto 0); -- VRAM Address
signal GADRC : std_logic_vector(13 downto 0); -- GRAM Address
signal GADRi : std_logic_vector(13 downto 0); -- GRAM Address(for GRAM Access)
signal VADRL : std_logic_vector(10 downto 0); -- VRAM Address(latched)
signal SDAT : std_logic_vector(7 downto 0); -- Shift Register to Display
signal SDATB : std_logic_vector(7 downto 0); -- Shift Register to Display
signal SDATR : std_logic_vector(7 downto 0); -- Shift Register to Display
signal SDATG : std_logic_vector(7 downto 0); -- Shift Register to Display
signal S2DAT : std_logic_vector(7 downto 0); -- Shift Register to Display(for 40-char)
signal S2DAT0 : std_logic_vector(7 downto 0); -- Shift Register to Display(for 80B)
signal S2DAT1 : std_logic_vector(7 downto 0); -- Shift Register to Display(for 80B)
--
-- CPU Access
--
signal MA : std_logic_vector(11 downto 0); -- Masked Address
signal CSB4_x : std_logic; -- Chip Select (PIO-3039 Color Board)
signal CSF4_x : std_logic; -- Chip Select (Background Color)
signal CSF5_x : std_logic; -- Chip Select (Display Select for C-Monitor)
signal CSF6_x : std_logic; -- Chip Select (Display Select for G-Monitor)
signal CSF7_x : std_logic; -- Chip Select (GRAM Select)
signal GCSi_x : std_logic; -- Chip Select (GRAM)
signal RCSV : std_logic; -- Chip Select (VRAM, NiosII)
signal RCSC : std_logic; -- Chip Select (CGROM, NiosII)
signal VWEN : std_logic; -- WR + MREQ (VRAM)
signal RVWEN : std_logic; -- WR + CS (VRAM, NiosII)
signal RCWEN : std_logic; -- WR + CS (CGROM, NiosII)
signal WAITi_n : std_logic; -- Wait
signal WAITii_n : std_logic; -- Wait(delayed)
signal ZGBE_n : std_logic_vector(3 downto 0); -- Byte Enable by Z80 access
--
-- Internal Signals
--
signal HDISPEN : std_logic; -- Display Enable for Horizontal, almost same as HBLANK
signal HBLANKi : std_logic; -- Horizontal Blanking
signal BLNK : std_logic; -- Horizontal Blanking (for wait)
signal XBLNK : std_logic; -- Horizontal Blanking (for wait)
signal VDISPEN : std_logic; -- Display Enable for Vertical, same as VBLANK
signal MB : std_logic; -- Display Signal (Mono, Blue)
signal MG : std_logic; -- Display Signal (Mono, Green)
signal MR : std_logic; -- Display Signal (Mono, Red)
signal BB : std_logic; -- Display Signal (Color, Blue)
signal BG : std_logic; -- Display Signal (Color, Green)
signal BR : std_logic; -- Display Signal (Color, Red)
signal PBGR : std_logic_vector(2 downto 0); -- Display Signal (Color)
signal POUT : std_logic_vector(2 downto 0); -- Display Signal (Color)
signal VRAMDO : std_logic_vector(7 downto 0); -- Data Bus Output for VRAM
signal DCODE : std_logic_vector(7 downto 0); -- Display Code, Read From VRAM
signal CGDAT : std_logic_vector(7 downto 0); -- Font Data To Display
signal CGADR : std_logic_vector(10 downto 0); -- Font Address To Display
signal CCOL : std_logic_vector(2 downto 0); -- Character Color
signal BCOL : std_logic_vector(2 downto 0); -- Background Color
signal CCOLi : std_logic_vector(2 downto 0); -- Character Color(reg)
signal BCOLi : std_logic_vector(2 downto 0); -- Background Color(reg)
signal GPRI : std_logic;
signal GPAGE : std_logic_vector(2 downto 0);
signal GPAGEi : std_logic_vector(2 downto 0);
signal GDISPEN : std_logic;
signal GDISPENi : std_logic;
signal GBANK : std_logic_vector(1 downto 0);
signal INVi : std_logic;
signal VGATEi : std_logic;
signal GRAMBDI : std_logic_vector(7 downto 0); -- Data from GRAM(Blue)
signal GRAMRDI : std_logic_vector(7 downto 0); -- Data from GRAM(Red)
signal GRAMGDI : std_logic_vector(7 downto 0); -- Data from GRAM(Green)
signal CH80i : std_logic;
signal CDISPEN : std_logic;
signal PALET0 : std_logic_vector(2 downto 0);
signal PALET1 : std_logic_vector(2 downto 0);
signal PALET2 : std_logic_vector(2 downto 0);
signal PALET3 : std_logic_vector(2 downto 0);
signal PALET4 : std_logic_vector(2 downto 0);
signal PALET5 : std_logic_vector(2 downto 0);
signal PALET6 : std_logic_vector(2 downto 0);
signal PALET7 : std_logic_vector(2 downto 0);
--
-- Components
--
component dprom
GENERIC (
init_file : string;
widthad_a : natural;
width_a : natural
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_b : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_b : IN STD_LOGIC;
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
end component;
component dpram
generic (
init_file : string;
widthad_a : natural;
width_a : natural
);
Port (
clock_a : in std_logic ;
clocken_a : in std_logic := '1';
address_a : in std_logic_vector (widthad_a-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0);
wren_a : in std_logic;
q_a : out std_logic_vector (width_a-1 downto 0);
clock_b : in std_logic ;
clocken_b : in std_logic := '1';
address_b : in std_logic_vector (widthad_a-1 downto 0);
data_b : in std_logic_vector (width_a-1 downto 0);
wren_b : in std_logic;
q_b : out std_logic_vector (width_a-1 downto 0)
);
end component;
component cgrom
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
component dpram2k
PORT
(
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
VRAM0 : dpram
GENERIC MAP (
init_file => "./roms/MZFONT.mif",
widthad_a => 11,
width_a => 8
)
PORT MAP (
clock_a => CK8M,
clocken_a => CK16M,
address_a => VADR,
data_a => T80_DI,
wren_a => VWEN,
q_a => VRAMDO,
clock_b => CK16M,
clocken_b => IOCTL_CSVVRAM_n,
address_b => IOCTL_ADDR(10 DOWNTO 0),
data_b => IOCTL_DOUT(7 DOWNTO 0),
wren_b => RVWEN, --IOCTL_WR,
q_b => open
);
CGROM0 : dprom
GENERIC MAP (
init_file => "./roms/MZ80K_cgrom.mif",
widthad_a => 11,
width_a => 8
)
PORT MAP (
address_a => CGADR,
clock_a => CK16M,
data_a => IOCTL_DOUT(7 DOWNTO 0),
wren_a => '0',
q_a => CGDAT,
address_b => IOCTL_ADDR(10 DOWNTO 0),
clock_b => IOCTL_CSCGROM_n,
data_b => IOCTL_DOUT(7 DOWNTO 0),
wren_b => ROWEN,--IOCTL_WR
q_b => open
);
--
-- Blank & Sync Generation
--
process( RST_n, CK16M ) begin
if RST_n='0' then
HCOUNT <= "1111111000";
HBLANKi <= '0';
HDISPEN <= '0';
BLNK <= '0';
HSYNC_n <= '1';
VDISPEN <= '1';
VSYNC_n <= '1';
GCSi_x <= '1';
VADRC <= (others=>'0');
GADRC <= (others=>'0');
VADRL <= (others=>'0');
elsif CK16M'event and CK16M='1' then
-- Counters
if HCOUNT=1015 then
--HCOUNT<=(others=>'0');
HCOUNT <= "1111111000";
VADRC <= VADRL; -- Return to Most-Left-Column Address
if VCOUNT=259 then
VCOUNT <= (others=>'0');
VADRC <= (others=>'0'); -- Home Position
GADRC <= (others=>'0'); -- Home Position
VADRL <= (others=>'0');
else
VCOUNT <= VCOUNT+'1';
end if;
else
HCOUNT <= HCOUNT+'1';
end if;
-- Horizontal Signals Decode
if HCOUNT=0 then
HDISPEN <= VDISPEN; -- if V-DISP is Enable then H-DISP Start
elsif HCOUNT=632 then
HBLANKi <= '1'; -- H-Blank Start
BLNK <= '1';
elsif HCOUNT=640 then
HDISPEN <= '0'; -- H-DISP End
elsif HCOUNT=768 then
HSYNC_n <= '0'; -- H-Sync Pulse Start
elsif HCOUNT=774 and VCOUNT(2 downto 0)="111" then
VADRL <= VADRC; -- Save Most-Left-Column Address
elsif HCOUNT=859 then
HSYNC_n <= '1'; -- H-Sync Pulse End
elsif HCOUNT=992 then
BLNK <= '0';
elsif HCOUNT=1015 then
HBLANKi <= '0'; -- H-Blank End
end if;
-- VRAM Address counter(per 8dot)
if HBLANKi='0' then
if (HCOUNT(2 downto 0)="111" and CH80i='1') or (HCOUNT(3 downto 0)="1111" and CH80i='0') then
VADRC <= VADRC+'1';
end if;
if (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
GADRC <= GADRC+'1';
end if;
end if;
-- Graphics VRAM Access signal
if HBLANKi='0' then
if (HCOUNT(2 downto 0)="000" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1000" and MODE_MZ80B='1') then
GCSi_x <= '0';
elsif (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
GCSi_x <= '1';
end if;
else
GCSi_x <= '1';
end if;
-- Get Font/Pattern data and Shift
if HCOUNT(3 downto 0)="0000" then
if CH80i='1' then
SDAT <= CGDAT;
else
SDAT <= CGDAT(7)&CGDAT(7)&CGDAT(6)&CGDAT(6)&CGDAT(5)&CGDAT(5)&CGDAT(4)&CGDAT(4);
S2DAT <= CGDAT(3)&CGDAT(3)&CGDAT(2)&CGDAT(2)&CGDAT(1)&CGDAT(1)&CGDAT(0)&CGDAT(0);
end if;
if MODE_MZ2000='1' then
SDATB <= GRAMBDI;
SDATR <= GRAMRDI;
SDATG <= GRAMGDI;
else
SDATB <= GRAMBDI(3)&GRAMBDI(3)&GRAMBDI(2)&GRAMBDI(2)&GRAMBDI(1)&GRAMBDI(1)&GRAMBDI(0)&GRAMBDI(0);
S2DAT0 <= GRAMBDI(7)&GRAMBDI(7)&GRAMBDI(6)&GRAMBDI(6)&GRAMBDI(5)&GRAMBDI(5)&GRAMBDI(4)&GRAMBDI(4);
SDATR <= GRAMRDI(3)&GRAMRDI(3)&GRAMRDI(2)&GRAMRDI(2)&GRAMRDI(1)&GRAMRDI(1)&GRAMRDI(0)&GRAMRDI(0);
S2DAT1 <= GRAMRDI(7)&GRAMRDI(7)&GRAMRDI(6)&GRAMRDI(6)&GRAMRDI(5)&GRAMRDI(5)&GRAMRDI(4)&GRAMRDI(4);
end if;
elsif HCOUNT(3 downto 0)="1000" then
if CH80i='1' then
SDAT <= CGDAT;
else
SDAT <= S2DAT;
end if;
if MODE_MZ2000='1' then
SDATB <= GRAMBDI;
SDATR <= GRAMRDI;
SDATG <= GRAMGDI;
else
SDATB <= S2DAT0;
SDATR <= S2DAT1;
end if;
else
SDAT <= SDAT(6 downto 0)&'0';
SDATB <= '0'&SDATB(7 downto 1);
SDATR <= '0'&SDATR(7 downto 1);
SDATG <= '0'&SDATG(7 downto 1);
end if;
-- Vertical Signals Decode
if VCOUNT=0 then
VDISPEN <= '1'; -- V-DISP Start
elsif VCOUNT=200 then
VDISPEN <= '0'; -- V-DISP End
elsif VCOUNT=219 then
VSYNC_n <= '0'; -- V-Sync Pulse Start
elsif VCOUNT=223 then
VSYNC_n <= '1'; -- V-Sync Pulse End
end if;
end if;
end process;
--
-- Control Registers
--
process( RST_n, T80_CLK ) begin
if RST_n='0' then
BCOLi <= (others=>'0');
CCOLi <= (others=>'1');
GPRI <= '0';
GPAGEi <= "000";
GDISPENi <= '0';
CDISPEN <= '1';
GBANK <= "00";
PALET0 <= "000";
PALET1 <= "111";
PALET2 <= "111";
PALET3 <= "111";
PALET4 <= "111";
PALET5 <= "111";
PALET6 <= "111";
PALET7 <= "111";
elsif T80_CLK'event and T80_CLK='0' then
if T80_WR_n='0' then
if MODE_MZ2000='1' then -- MZ-2000
-- Background Color
if CSF4_x='0' then
BCOLi <= T80_DI(2 downto 0);
end if;
-- Character Color and Priority
if CSF5_x='0' then
CCOLi <= T80_DI(2 downto 0);
GPRI <= T80_DI(3);
end if;
-- Display Graphics and Pages
if CSF6_x='0' then
GPAGEi <= T80_DI(2 downto 0);
GDISPENi <= not T80_DI(3);
end if;
-- Select Accessable Graphic Banks
if CSF7_x='0' then
GBANK <= T80_DI(1 downto 0);
end if;
else -- MZ-80B
-- Color Control(PIO-3039)
if CSB4_x='0' then
if T80_DI(6)='1' then
CDISPEN <= T80_DI(7);
else
case T80_DI(2 downto 0) is
when "000" => PALET0<=T80_DI(5 downto 3);
when "001" => PALET1<=T80_DI(5 downto 3);
when "010" => PALET2<=T80_DI(5 downto 3);
when "011" => PALET3<=T80_DI(5 downto 3);
when "100" => PALET4<=T80_DI(5 downto 3);
when "101" => PALET5<=T80_DI(5 downto 3);
when "110" => PALET6<=T80_DI(5 downto 3);
when "111" => PALET7<=T80_DI(5 downto 3);
when others => PALET0<=T80_DI(5 downto 3);
end case;
end if;
end if;
-- Select Accessable Graphic Banks and Outpu Pages
if CSF4_x='0' then
GBANK <= T80_DI(0)&(not T80_DI(0));
GPAGEi(1 downto 0)<=T80_DI(2 downto 1);
end if;
end if;
end if;
end if;
end process;
--
-- Timing Conditioning and Wait
--
process( T80_MREQ_n ) begin
if T80_MREQ_n'event and T80_MREQ_n='0' then
XBLNK<=BLNK;
end if;
end process;
process( T80_CLK ) begin
if T80_CLK'event and T80_CLK='1' then
WAITii_n<=WAITi_n;
end if;
end process;
WAITi_n<='0' when (CSV_n='0' or CSG_n='0') and XBLNK='0' and BLNK='0' else '1';
T80_WAIT_n<=WAITi_n and WAITii_n;
--
-- Mask by Mode
--
ZGBE_n <= "1110" when GBANK="01" else
"1101" when GBANK="10" else
"1011" when GBANK="11" else "1111";
GBE_n <= ZGBE_n when BLNK='1' else "1000";
GT80_WR_n <= T80_WR_n when BLNK='1' else '1';
GCS_n <= CSG_n when BLNK='1' else GCSi_x;
RCSV <= '0' when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11010" else '1';
RCSC <='0' when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11001" else '1';
VWEN <='1' when T80_WR_n='0' and CSV_n='0' and BLNK='1' else '0';
RVWEN <= not(IOCTL_WR='1' or RCSV);
RCWEN <= not(IOCTL_WR='1' or RCSC);
CSB4_x <= '0' when T80_A(7 downto 0)=X"B4" and T80_IORQ_n='0' else '1';
CSF4_x <= '0' when T80_A(7 downto 0)=X"F4" and T80_IORQ_n='0' else '1';
CSF5_x <= '0' when T80_A(7 downto 0)=X"F5" and T80_IORQ_n='0' else '1';
CSF6_x <= '0' when T80_A(7 downto 0)=X"F6" and T80_IORQ_n='0' else '1';
CSF7_x <= '0' when T80_A(7 downto 0)=X"F7" and T80_IORQ_n='0' else '1';
CCOL <= CCOLi when T80_BUSACK_n='1' else "111";
BCOL <= BCOLi when T80_BUSACK_n='1' else "000";
INVi <= INV when BOOTM='0' and T80_BUSACK_n='1' else '1';
VGATEi <= VGATE when BOOTM='0' and T80_BUSACK_n='1' else '0';
GPAGE <= GPAGEi when BOOTM='0' and T80_BUSACK_n='1' else "000";
GDISPEN <= '0' when BOOTM='1' or T80_BUSACK_n='0' else
'1' when MODE_MZ80B='1' else GDISPENi;
CH80i <= CH80 when BOOTM='0' and T80_BUSACK_n='1' else '0';
--
-- Bus Select
--
VADR <= T80_A(10 downto 0) when CSV_n='0' and BLNK='1' else VADRC;
GADRi <= T80_A(13 downto 0) when CSG_n='0' and BLNK='1' and MODE_MZ2000='1' else
'0'&T80_A(12 downto 0) when CSG_n='0' and BLNK='1' and MODE_MZ80B='1' else GADRC;
GADR <= "1111101"&GADRi; -- 0x7D0000
DCODE <= T80_DI when CSV_n='0' and BLNK='1' and T80_WR_n='0' else VRAMDO;
T80_DO <= VRAMDO when T80_RD_n='0' and CSV_n='0' else
GDI(7 downto 0) when T80_RD_n='0' and CSG_n='0' and GBANK="01" else
GDI(15 downto 8) when T80_RD_n='0' and CSG_n='0' and GBANK="10" else
GDI(23 downto 16) when T80_RD_n='0' and CSG_n='0' and GBANK="11" else (others=>'0');
CGADR <= DCODE&VCOUNT(2 downto 0);
GRAMBDI <= GDI(7 downto 0) when GPAGE(0)='1' else (others=>'0');
GRAMRDI <= GDI(15 downto 8) when GPAGE(1)='1' else (others=>'0');
GRAMGDI <= GDI(23 downto 16) when GPAGE(2)='1' else (others=>'0');
GDO <= "00000000"&T80_DI&T80_DI&T80_DI;
--
-- Color Decode
--
-- Monoclome Monitor
-- MB<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
-- MR<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
MB <= '0';
MR <= '0';
MG <= not (SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0)))) when HDISPEN='1' and VGATEi='0' and INVi='0' else
SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0))) when HDISPEN='1' and VGATEi='0' and INVi='1' else '0';
-- Color Monitor(MZ-2000)
process( HDISPEN, VGATEi, GPRI, SDAT(7), SDATB(0), SDATR(0), SDATG(0), CCOL, BCOL ) begin
if HDISPEN='1' and VGATEi='0' then
if SDAT(7)='0' and SDATB(0)='0' then
BB<=BCOL(0);
else
if GPRI='0' then
if SDAT(7)='1' then
BB<=CCOL(0);
else
BB<='1'; -- SDATB(0)='1'
end if;
else --GPRI='1'
if SDATB(0)='1' then
BB<='1';
else
BB<=CCOL(0); -- SDAT(7)='1'
end if;
end if;
end if;
if SDAT(7)='0' and SDATR(0)='0' then
BR<=BCOL(1);
else
if GPRI='0' then
if SDAT(7)='1' then
BR<=CCOL(1);
else
BR<='1'; -- SDATR(0)='1'
end if;
else --GPRI='1' then
if SDATR(0)='1' then
BR<='1';
else
BR<=CCOL(1); -- SDAT(7)='1'
end if;
end if;
end if;
if SDAT(7)='0' and SDATG(0)='0' then
BG<=BCOL(2);
else
if GPRI='0' then
if SDAT(7)='1' then
BG<=CCOL(2);
else
BG<='1'; -- SDATG(0)='1'
end if;
else --GPRI='1' then
if SDATG(0)='1' then
BG<='1';
else
BG<=CCOL(2); -- SDAT(7)='1'
end if;
end if;
end if;
else
BB<='0';
BR<='0';
BG<='0';
end if;
end process;
-- Color Monitor(PIO-3039)
POUT<=(SDAT(7) and CDISPEN)&SDATR(0)&SDATB(0);
process(POUT, PALET0, PALET1, PALET2, PALET3, PALET4, PALET5, PALET6, PALET7) begin
case POUT is
when "000" => PBGR<=PALET0;
when "001" => PBGR<=PALET1;
when "010" => PBGR<=PALET2;
when "011" => PBGR<=PALET3;
when "100" => PBGR<=PALET4;
when "101" => PBGR<=PALET5;
when "110" => PBGR<=PALET6;
when "111" => PBGR<=PALET7;
when others => PBGR<=PALET7;
end case;
end process;
--
-- Output
--
CK16M <= CK16M;
VBLANK <= VDISPEN;
HBLANK <= HBLANKi;
ROUT <= MR when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
BR when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(0);
GOUT <= MG when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
BG when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(1);
BOUT <= MB when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
BB when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(2);
end RTL;

854
mz80b/mz80b_x.vhd Normal file
View File

@@ -0,0 +1,854 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: mz80b.vhd
-- Created: August 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Business Computer:
-- Models MZ-80B, MZ-2000
--
-- This module is the main (top level) container for the Business MZ Computer
-- Emulation.
--
-- The design tries to work from top-down, where components which are common
-- to the Business and Personal MZ series are at the top (ie. main memory,
-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
-- to the machine specific modules and components. Some components are common
-- by their nature (ie. 8255 PIO) but these are instantiated within the lower
-- tree branch as their design use is less generic.
--
-- The tree is as follows;-
--
-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
-- | -> mz80c_video.vhd
-- | -> pcg.vhd
-- | -> cmt.vhd (this may move to common and be shared with mz80b)
-- | -> keymatrix.vhd (common)
-- | -> pll.v (common)
-- | -> clkgen.vhd (common)
-- | -> T80 (common)
-- | -> i8255 (common)
-- | -> i8253 (common)
-- | -> dpram.vhd (common)
-- | -> dprom.vhd (common)
-- | -> mctrl.vhd (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development)
--
--
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: August 2018 - Initial module created.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mz80b is
PORT (
-- Clocks
CK50M : in std_logic; -- Master Clock(50MHz)
CK25M : in std_logic; -- VGA Clock MZ80B (25MHz)
CK16M : in std_logic; -- MZ80B CPU Clock (16MHz)
CK12M5 : in std_logic; -- VGA Clock MZ80C (12.5MHz)
CK8M : in std_logic; -- 15.6kHz Dot Clock(8MHz)
CK4M : in std_logic; -- CPU Turbo Clock MZ80C (4MHz)
CK3M125 : in std_logic; -- Music Base Clock(31.25kHz)
CK2M : in std_logic; -- Z80 Original Clock MZ80C
CLKVIDEO : out std_logic; -- Base clock for video.
-- Resets.
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
-- Z80 CPU
T80_RST_n : in std_logic;
T80_CLK_n : in std_logic;
T80_CLKEN : out std_logic;
T80_WAIT_n : out std_logic;
T80_INT_n : out std_logic;
T80_NMI_n : out std_logic;
T80_BUSRQ_n : out std_logic;
T80_M1_n : in std_logic;
T80_MREQ_n : in std_logic;
T80_IORQ_n : in std_logic;
T80_RD_n : in std_logic;
T80_WR_n : in std_logic;
T80_RFSH_n : in std_logic;
T80_HALT_n : in std_logic;
T80_BUSAK_n : in std_logic;
T80_A16 : in std_logic_vector(15 downto 0);
T80_DI : out std_logic_vector(7 downto 0);
T80_DO : in std_logic_vector(7 downto 0);
-- Chip selects to common resources.
CSROM_n : out std_logic;
CSRAM_n : out std_logic;
-- Audio.
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
-- Video signals.
R : out std_logic;
G : out std_logic;
B : out std_logic;
HSYNC_n : out std_logic;
VSYNC_n : out std_logic;
HBLANK : out std_logic;
VBLANK : out std_logic;
-- Type of machine we are emulating.
MODE_MZ80K : in std_logic;
MODE_MZ80C : in std_logic;
MODE_MZ1200 : in std_logic;
MODE_MZ80A : in std_logic;
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
MODE_MZ700 : in std_logic;
MODE_MZ800 : in std_logic;
MODE_MZ_KC : in std_logic;
MODE_MZ_A : in std_logic;
MODE_MZ_B : in std_logic;
MODE_MZ_80C : in std_logic;
MODE_MZ_80B : in std_logic;
-- Type of display to emulate.
DISPLAY_NORMAL : in std_logic;
DISPLAY_NIDECOM : in std_logic;
DISPLAY_GAL5 : in std_logic;
DISPLAY_COLOUR : in std_logic;
-- Buttons to emulate.
BUTTON_PLAYSW : in std_logic; -- Tape Play Switch, 1 = Play.
-- Different operations modes
CONFIG_TURBO : in std_logic; -- CPU Speed, 0 = Normal, 1 = Turbo
-- I/O -- I/O down to the core.
PS2_KEY : in std_logic_vector(10 downto 0);
PS2_MOUSE : in std_logic_vector(24 downto 0);
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic; -- HPS Interrupt.
-- Debug Status Leds
DEBUG_STATUS_LEDS : out std_logic_vector(23 downto 0) -- 24 leds to display status.
);
end mz80b;
-- Switch
SW : in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
-- PS2
PS2_KBDAT : in std_logic; -- PS2 Keyboard Data
PS2_KBCLK : in std_logic; -- PS2 Keyboard Clock
);
end mz80b_core;
architecture rtl of mz80b_core is
DEBUG_STATUS_LEDS : out std_logic_vector(23 downto 0) -- 24 leds to display status.
--
-- T80
--
signal MREQ_n : std_logic;
signal IORQ_n : std_logic;
signal RD_n : std_logic;
--signal MWR : std_logic;
--signal MRD : std_logic;
signal IWR : std_logic;
signal ZWAIT_n : std_logic;
signal M1 : std_logic;
signal RFSH_n : std_logic;
signal ZDTO : std_logic_vector(7 downto 0);
signal ZDTI : std_logic_vector(7 downto 0);
--signal RAMCS_n : std_logic;
signal RAMDI : std_logic_vector(7 downto 0);
signal BAK_n : std_logic;
signal BREQ_n : std_logic;
--
-- Clocks
--
signal CK4M : std_logic;
signal CK16M : std_logic;
signal CK25M : std_logic;
signal CK3125 : std_logic;
--signal SCLK : std_logic;
--signal HCLK : std_logic;
signal CASCADE01 : std_logic;
signal CASCADE12 : std_logic;
--
-- Decodes, misc
--
--signal CSE_n : std_logic;
--signal CSE2_n : std_logic;
--signal BUF : std_logic_vector(9 downto 0);
signal CSHSK : std_logic;
signal MZMODE : std_logic;
signal DMODE : std_logic;
signal KBEN : std_logic;
signal KBDT : std_logic_vector(7 downto 0);
signal BOOTM : std_logic;
signal F_BTN : std_logic;
signal IRQ_CMT : std_logic;
signal C_LEDG : std_logic_vector(9 downto 0);
signal IRQ_FDD : std_logic;
signal F_LEDG : std_logic_vector(9 downto 0);
--
-- Video
--
signal HBLANKi : std_logic;
signal VBLANKi : std_logic;
signal HSYNC_ni : std_logic;
signal VSYNC_ni : std_logic;
signal Ri : std_logic;
signal Gi : std_logic;
signal Bi : std_logic;
--signal VGATE : std_logic;
signal CSV_n : std_logic;
signal CSG_n : std_logic;
signal VRAMDO : std_logic_vector(7 downto 0);
--
-- PPI
--
signal CSE0_n : std_logic;
signal PPI_DO : std_logic_vector(7 downto 0);
signal PPIPA : std_logic_vector(7 downto 0);
signal PPIPB : std_logic_vector(7 downto 0);
signal PPIPC : std_logic_vector(7 downto 0);
signal BST_n : std_logic;
--
-- PIT
--
signal CSE4_n : std_logic;
signal DOPIT : std_logic_vector(7 downto 0);
signal RST8253_n : std_logic;
--
-- PIO
--
signal CSE8_n : std_logic;
signal PIO_DO : std_logic_vector(7 downto 0);
signal INT_n : std_logic;
signal PIOPA : std_logic_vector(7 downto 0);
signal PIOPB : std_logic_vector(7 downto 0);
--
-- FDD,FDC
--
signal DOFDC : std_logic_vector(7 downto 0);
signal DS : std_logic_vector(3 downto 0);
signal HS : std_logic;
signal MOTOR_n : std_logic;
signal INDEX_n : std_logic;
signal TRACK00_n : std_logic;
signal WPRT_n : std_logic;
signal STEP_n : std_logic;
signal DIREC : std_logic;
signal FDO : std_logic_vector(7 downto 0);
signal FDI : std_logic_vector(7 downto 0);
signal WGATE_n : std_logic;
signal DTCLK : std_logic;
--
-- for Debug
--
--
-- Components
--
component i8255
Port (
RST : in std_logic;
CLK : in std_logic;
A : in std_logic_vector(1 downto 0);
CS : in std_logic;
RD : in std_logic;
WR : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
-- Port
PA : out std_logic_vector(7 downto 0);
PB : in std_logic_vector(7 downto 0);
PC : out std_logic_vector(7 downto 0);
-- Mode
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic
);
end component;
component i8253
Port (
RST : in std_logic;
CLK_n : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
WR_n : in std_logic;
RD_n : in std_logic;
CLK0 : in std_logic;
GATE0 : in std_logic;
OUT0 : out std_logic;
CLK1 : in std_logic;
GATE1 : in std_logic;
OUT1 : out std_logic;
CLK2 : in std_logic;
GATE2 : in std_logic;
OUT2 : out std_logic
);
end component;
component z8420
Port (
-- System
RST_n : in std_logic; -- Only Power On Reset
-- Z80 Bus Signals
CLK : in std_logic;
BASEL : in std_logic;
CDSEL : in std_logic;
CE : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
IORQ_n : in std_logic;
M1_n : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
IEI : in std_logic;
IEO : out std_logic;
INT_n : out std_logic;
-- Port
A : out std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
);
end component;
component keymatrix
Port (
RST_n : in std_logic;
CLK : in std_logic; -- System Clock
-- Operating mode of emulator
MZ_MODE_B : in std_logic;
-- i8255
PA : in std_logic_vector(3 downto 0);
PB : out std_logic_vector(7 downto 0);
STALL : in std_logic;
-- PS/2 Keyboard Data
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
PS2_MOUSE : in std_logic_vector(24 downto 0); -- PS2 Mouse data.
-- Type of machine we are emulating.
MODE_MZ80K : in std_logic;
MODE_MZ80C : in std_logic;
MODE_MZ1200 : in std_logic;
MODE_MZ80A : in std_logic;
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
MODE_MZ700 : in std_logic;
MODE_MZ_KC : in std_logic;
MODE_MZ_A : in std_logic;
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable to FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
component mz80b_videoout
Port (
RST_n : in std_logic; -- Reset
BOOTM : in std_logic; -- BOOT Mode
-- Type of machine we are emulating.
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
-- Type of display to emulate.
DISPLAY_NORMAL : in std_logic;
DISPLAY_NIDECOM : in std_logic;
DISPLAY_GAL5 : in std_logic;
DISPLAY_COLOUR : in std_logic;
-- Different operations modes.
CONFIG_PCGRAM : in std_logic; -- PCG Mode Switch, 0 = CGROM, 1 = CGRAM.
-- Clocks
CK16M : in std_logic; -- 15.6kHz Dot Clock(16MHz)
T80_CLK_n : in std_logic; -- Z80 Current Clock
T80_CLK : in std_logic; -- Z80 Current Clock Inverted
-- CPU Signals
T80_A : in std_logic_vector(13 downto 0); -- CPU Address Bus
CSV_n : in std_logic; -- CPU Memory Request(VRAM)
CSG_n : in std_logic; -- CPU Memory Request(GRAM)
T80_RD_n : in std_logic; -- CPU Read Signal
T80_WR_n : in std_logic; -- CPU Write Signal
T80_MREQ_n : in std_logic; -- CPU Memory Request
T80_BUSACK_n : in std_logic; -- CPU Bus Acknowledge
T80_WAIT_n : out std_logic; -- CPU Wait Request
T80_DI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
T80_DO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- Video Control from outside
INV : in std_logic; -- Reverse mode(8255 PA4)
VGATE : in std_logic; -- Video Output Control(8255 PC0)
CH80 : in std_logic; -- Text Character Width(Z80PIO A5)
-- Video Signals
VGATE_n : in std_logic; -- Video Output Control
HBLANK : out std_logic; -- Horizontal Blanking
VBLANK : out std_logic; -- Vertical Blanking
HSYNC_n : out std_logic; -- Horizontal Sync
VSYNC_n : out std_logic; -- Vertical Sync
ROUT : out std_logic; -- Red Output
GOUT : out std_logic; -- Green Output
BOUT : out std_logic; -- Green Output
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0) -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
component cmt
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Tape action interrupt
-- Z80 Bus
ZCLK : in std_logic;
-- ZA8 : in std_logic_vector(7 downto 0);
-- ZIWR_n : in std_logic;
-- ZDI : in std_logic_vector(7 downto 0);
-- ZDO : out std_logic_vector(7 downto 0);
-- Tape signals
T_END : out std_logic; -- Sense CMT(Motor on/off)
OPEN_n : in std_logic; -- Open
PLAY_n : in std_logic; -- Play
STOP_n : in std_logic; -- Stop
FF_n : in std_logic; -- Fast Foward
REW_n : in std_logic; -- Rewind
APSS_n : in std_logic; -- APSS
FFREW : in std_logic; -- FF/REW mode
FMOTOR : in std_logic; -- FF/REW start
FLATCH : in std_logic; -- FF/REW latch
WREADY : out std_logic; -- Write enable
TREADY : out std_logic; -- Tape exist
-- EXIN : in std_logic; -- CMT IN from I/O board
RDATA : out std_logic; -- to 8255
-- Status Signal
SCLK : in std_logic; -- Slow Clock(31.25kHz)
MZMODE : in std_logic; -- Hardware Mode
DMODE : in std_logic -- Display Mode
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
component mz1e05
Port (
-- CPU Signals
ZRST_n : in std_logic;
ZCLK : in std_logic;
ZADR : in std_logic_vector(7 downto 0); -- CPU Address Bus(lower)
ZRD_n : in std_logic; -- CPU Read Signal
ZWR_n : in std_logic; -- CPU Write Signal
ZIORQ_n : in std_logic; -- CPU I/O Request
ZDI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
ZDO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
SCLK : in std_logic; -- Slow Clock
-- FD signals
DS_n : out std_logic_vector(4 downto 1); -- Drive Select
HS : out std_logic; -- Head Select
MOTOR_n : out std_logic; -- Motor On
INDEX_n : in std_logic; -- Index Hole Detect
TRACK00 : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP_n : out std_logic; -- Head Step In/Out
DIREC : out std_logic; -- Head Step Direction
WGATE_n : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end component;
-- PDS : needs buffer ram and an interface to HPS to write into buffer memory.
--component fdunit
-- Port (
-- RST_n : in std_logic; -- Reset
-- CLK : in std_logic; -- System Clock
-- -- Interrupt
-- INTO : out std_logic; -- Step Pulse interrupt
-- -- FD signals
-- FCLK : in std_logic;
-- DS_n : in std_logic_vector(4 downto 1); -- Drive Select
-- HS : in std_logic; -- Head Select
-- MOTOR_n : in std_logic; -- Motor On
-- INDEX_n : out std_logic; -- Index Hole Detect
-- TRACK00 : out std_logic; -- Track 0
-- WPRT_n : out std_logic; -- Write Protect
-- STEP_n : in std_logic; -- Head Step In/Out
-- DIREC : in std_logic; -- Head Step Direction
-- WG_n : in std_logic; -- Write Gate
-- DTCLK : out std_logic; -- Data Clock
-- FDI : in std_logic_vector(7 downto 0); -- Write Data
-- FDO : out std_logic_vector(7 downto 0); -- Read Data
-- -- Buffer RAM I/F
-- BCS_n : out std_logic; -- RAM Request
-- BADR : out std_logic_vector(22 downto 0); -- RAM Address
-- BWR_n : out std_logic; -- RAM Write Signal
-- BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
-- BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- -- HPS Interface
-- IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
-- IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
-- IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
-- IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
-- IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
-- IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
-- IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
-- IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
-- );
--end component;
begin
--
-- Instantiation
--
CPU0 : T80se
generic map(
Mode => 0, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write => 1, -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait => 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
)
port map (
RESET_n => T80_RST_n,
CLK_n => CK4M,
CLKEN => '1',
WAIT_n => ZWAIT_n,
INT_n => INT_n,
-- INT_n => '1',
NMI_n => '1',
BUSRQ_n => BREQ_n,
M1_n => M1,
MREQ_n => MREQ_n,
IORQ_n => IORQ_n,
RD_n => RD_n,
WR_n => T80_WR_n,
RFSH_n => RFSH_n,
HALT_n => open,
BUSAK_n => BAK_n,
A => T80_A16,
DI => ZDTI,
DO => ZDTO
);
PPI0 : i8255 port map (
RST => T80_RST,
CLK => CK4M,
A => T80_A16(1 downto 0),
CS => CSE0_n,
RD => RD_n,
WR => T80_WR_n,
DI => ZDTO,
DO => PPI_DO,
-- Port
PA => PPIPA,
PB => PPIPB,
PC => PPIPC,
-- Mode
MODE_MZ80B => MODE_MZ80B,
MODE_MZ2000 => MODE_MZ2000
);
PPIPB(7)<=PIOPB(7);
-- WDATA<=PPIPC(7);
-- REC_n<=PPIPC(6);
-- WRIT_n<=PPIPC(6);
-- KINH<=PPIPC(5);
-- L_FR<=PPIPC(5);
BST_n<=PPIPC(3);
-- NST<=PPIPC(1);
CMT0 : cmt port map (
-- Interrupt
INTO => IRQ_CMT, -- Tape action interrupt
-- Z80 Bus
ZCLK => CK4M,
-- Tape signals
T_END => PPIPB(3), -- Sense CMT(Motor on/off)
OPEN_n => PPIPC(4), -- Open
PLAY_n => PPIPA(2), -- Play
STOP_n => PPIPA(3), -- Stop
FF_n => PPIPA(1), -- Fast Foward
REW_n => PPIPA(0), -- Rewind
APSS_n => PPIPA(7), -- APSS
FFREW => PPIPA(1), -- FF/REW mode
FMOTOR => PPIPA(0), -- FF/REW start
FLATCH => PPIPC(5), -- FF/REW latch
WREADY => PPIPB(4), -- Write enable
TREADY => PPIPB(5), -- Tape exist
RDATA => PPIPB(6), -- to 8255
-- Status Signal
SCLK => CK3125, -- Slow Clock(31.25kHz)
MZMODE => MZMODE,
DMODE => DMODE
);
PIT0 : i8253 port map (
RST => T80_RST,
CLK => CK4M,
A => T80_A16(1 downto 0),
DI => ZDTO,
DO => DOPIT,
CS => CSE4_n,
WR => T80_WR_n,
RD => RD_n,
CLK0 => CK3125,
GATE0 => RST8253_n,
OUT0 => CASCADE01,
CLK1 => CASCADE01,
GATE1 => RST8253_n,
OUT1 => CASCADE12,
CLK2 => CASCADE12,
GATE2 => '1',
OUT2 => open
);
PIO0 : z8420 port map (
-- System
RST_n => T80_RST_n, -- Only Power On Reset
-- Z80 Bus Signals
CLK => CK4M,
BASEL => T80_A16(1),
CDSEL => T80_A16(0),
CE => CSE8_n,
RD_n => RD_n,
WR_n => T80_WR_n,
IORQ_n => IORQ_n,
M1_n => M1,
DI => ZDTO,
DO => PIO_DO,
IEI => '1',
IEO => open,
-- INT_n => open,
INT_n => INT_n,
-- Port
A => PIOPA,
B => PIOPB,
);
KEYS : keymatrix
port map (
RST_n => T80_RST_n,
CLK => T80_CLK, -- System clock.
-- Operating mode of emulator
MZ_MODE_B => MODE_MZ_B,
-- i8255
PA => i8255_PA_O(3 downto 0),
PB => i8255_PB_I,
STALL => i8255_PA_O(4),
-- PS/2 Keyboard Data
PS2_KEY => PS2_KEY, -- PS2 Key data.
PS2_MOUSE => PS2_MOUSE, -- PS2 Mouse data.
-- Type of machine we are emulating.
MODE_MZ80K => MODE_MZ80K,
MODE_MZ80C => MODE_MZ80C,
MODE_MZ1200 => MODE_MZ1200,
MODE_MZ80A => MODE_MZ80A,
MODE_MZ80B => MODE_MZ80B,
MODE_MZ2000 => MODE_MZ2000,
MODE_MZ700 => MODE_MZ700,
MODE_MZ_KC => MODE_MZ_KC,
MODE_MZ_A => MODE_MZ_A,
-- HPS Interface
IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
IOCTL_DIN => IOCTL_DIN_KEY, -- HPS Data to be sent to HPS.
IOCTL_INTERRUPT => IOCTL_INTERRUPT -- Interrupt to HPS.
);
VIDEO0 : mz80b_videoout Port map (
RST => T80_RST_n -- Reset
MZMODE => MZMODE, -- Hardware Mode
DMODE => DMODE, -- Display Mode
-- Clocks
CK50M => CK50M, -- Master Clock(50MHz)
CK25M => CK25M, -- VGA Clock(25MHz)
CK16M => CK16M, -- 15.6kHz Dot Clock(16MHz)
CK4M => CK4M, -- CPU/CLOCK Clock(4MHz)
CK3125 => CK3125, -- Time Base Clock(31.25kHz)
-- CPU Signals
A => T80_A16(13 downto 0), -- CPU Address Bus
CSV_n => CSV_n, -- CPU Memory Request(VRAM)
CSG_n => CSG_n, -- CPU Memory Request(GRAM)
RD_n => RD_n, -- CPU Read Signal
WR_n => T80_WR_n, -- CPU Write Signal
MREQ_n => MREQ_n, -- CPU Memory Request
IORQ_n => IORQ_n, -- CPU I/O Request
WAIT_n => ZWAIT_n, -- CPU Wait Request
DI => ZDTO, -- CPU Data Bus(in)
DO => VRAMDO, -- CPU Data Bus(out)
-- Video Control from outside
INV => PPIPA(4), -- Reverse mode(8255 PA4)
VGATE => PPIPC(0), -- Video Output Control
CH80 => PIOPA(5),
-- Video Signals
VGATE_n => VGATE_n, -- Video Output Control
HBLANK => HBLANKi, -- Horizontal Blanking
VBLANK => VBLANKi, -- Vertical Blanking
HSYNC_n => HSYNC_ni, -- Horizontal Sync
VSYNC_n => VSYNC_ni, -- Vertical Sync
ROUT => Ri, -- Red Output
GOUT => Gi, -- Green Output
BOUT => Bi, -- Blue Output
HBLANK => HBLANKi, -- Horizontal Blanking
VBLANK => VBLANKi, -- Vertical Blanking
-- Control Signal
BOOTM => BOOTM, -- BOOT Mode
BACK => BAK_n -- Z80 Bus Acknowlegde
);
PDS :- Need BOOTM
FDIF0 : mz1e05 Port map(
-- CPU Signals
ZRST_n => T80_RST_n,
ZCLK => CK4M,
ZADR => T80_A16(7 downto 0), -- CPU Address Bus(lower)
ZRD_n => RD_n, -- CPU Read Signal
ZWR_n => T80_WR_n, -- CPU Write Signal
ZIORQ_n => IORQ_n, -- CPU I/O Request
ZDI => ZDTO, -- CPU Data Bus(in)
ZDO => DOFDC, -- CPU Data Bus(out)
SCLK => CK3125, -- Slow Clock
-- FD signals
DS_n => DS, -- Drive Select
HS => HS, -- Head Select
MOTOR_n => MOTOR_n, -- Motor On
INDEX_n => INDEX_n, -- Index Hole Detect
TRACK00 => TRACK00_n, -- Track 0
WPRT_n => WPRT_n, -- Write Protect
STEP_n => STEP_n, -- Head Step In/Out
DIREC => DIREC, -- Head Step Direction
WGATE_n => WGATE_n, -- Write Gate
DTCLK => DTCLK, -- Data Clock
FDI => FDI, -- Read Data
FDO => FDO -- Write Data
);
-- FDU0 : fdunit Port map(
-- -- Interrupt
-- INTO => IRQ_FDD, -- Step Pulse interrupt
-- -- FD signals
-- FCLK => CK4M,
-- DS_n => DS, -- Drive Select
-- HS => HS, -- Head Select
-- MOTOR_n => MOTOR_n, -- Motor On
-- INDEX_n => INDEX_n, -- Index Hole Detect
-- TRACK00 => TRACK00_n, -- Track 0
-- WPRT_n => WPRT_n, -- Write Protect
-- STEP_n => STEP_n, -- Head Step In/Out
-- DIREC => DIREC, -- Head Step Direction
-- WG_n => WGATE_n, -- Write Gate
-- DTCLK => DTCLK, -- Data Clock
-- FDO => FDI, -- Read Data
-- FDI => FDO, -- Write Data
-- -- Buffer RAM I/F
-- BCS_n => BCS_n, -- RAM Request
-- BADR => BADR, -- RAM Address
-- BWR_n => BWR_n, -- RAM Write Signal
-- BDI => BDI, -- Data Bus Input from RAM
-- BDO => BDO -- Data Bus Output to RAM
-- );
--
-- Control Signals
--
IWR <= IORQ_n or T80_WR_n;
--
-- Data Bus
--
ZDTI <= PPI_DO or DOPIT or PIO_DO or VRAMDO or RAMDI or DOFDC;
RAMDI <= T80_DO when RD_n='0' and MREQ_n='0' and CSV_n='1' and CSG_n='1' else (others=>'0');
-- HSKDI when CSHSK='0' else T80_DO;
--
-- Chip Select
--
CSV_n <= '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 12)="1101" and MREQ_n='0' and PIOPA(6)='0' else -- $D000 - $DFFF (80B)
'0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 12)="0101" and MREQ_n='0' and PIOPA(6)='1' else -- $5000 - $5FFF (80B)
'0' when MZMODE='1' and PIOPA(7)='1' and T80_A16(15 downto 12)="1101" and MREQ_n='0' and PIOPA(6)='1' else '1'; -- $D000 - $DFFF (2000)
CSG_n <= '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 13)="111" and MREQ_n='0' and PIOPA(6)='0' else -- $E000 - $FFFF (80B)
'0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 13)="011" and MREQ_n='0' and PIOPA(6)='1' else -- $6000 - $7FFF (80B)
'0' when MZMODE='1' and PIOPA(7)='1' and T80_A16(15 downto 14)="11" and MREQ_n='0' and PIOPA(6)='0' else '1'; -- $C000 - $FFFF (2000)
CSHSK <= '0' when T80_A16(7 downto 3)="10001" and IORQ_n='0' else '1'; -- HandShake Port
CSE0_n <= '0' when T80_A16(7 downto 2)="111000" and IORQ_n='0' else '1'; -- 8255
CSE4_n <= '0' when T80_A16(7 downto 2)="111001" and IORQ_n='0' else '1'; -- 8253
CSE8_n <= '0' when T80_A16(7 downto 2)="111010" and IORQ_n='0' else '1'; -- PIO
--
-- Video Output.
--
HSYNC_n <= HSYNC_ni;
VSYNC_n <= VSYNC_ni;
R <= Ri;
G <= Gi;
B <= Bi;
VBLANK <= VBLANKi;
HBLANK <= HBLANKi;
VBLANKi <= PPIPB(0); -- Vertical Blanking
--
-- Ports
--
CSRAM_n <= MREQ_n when CSV_n='1' and CSG_n='1' and RFSH_n='1' else '1';
T80_DI <= ZDTO;
ZWR_n <= T80_WR_n;
--
-- Misc
--
MZMODE <= SW(9);
DMODE <= SW(8);
T80_RST <= not T80_RST_n;
RST8253_n <= '0' when T80_A16(7 downto 2)="111100" and IWR='0' else '1';
GPIO1_D(15)<=PPIPC(2); -- Sound Output
GPIO1_D(14)<=PPIPC(2);
end rtl;

133
mz80b/old/ScanConv.vhd Normal file
View File

@@ -0,0 +1,133 @@
--
-- ScanConv.vhd
--
-- Up Scan Converter (15.6kHz->VGA)
-- for MZ-80B on FPGA
--
-- Nibbles Lab. 2013
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ScanConv is
Port (
CK16M : in STD_LOGIC; -- MZ Dot Clock
CK25M : in STD_LOGIC; -- VGA Dot Clock
RI : in STD_LOGIC; -- Red Input
GI : in STD_LOGIC; -- Green Input
BI : in STD_LOGIC; -- Blue Input
HSI : in STD_LOGIC; -- H-Sync Input(MZ,15.6kHz)
RO : out STD_LOGIC; -- Red Output
GO : out STD_LOGIC; -- Green Output
BO : out STD_LOGIC; -- Blue Output
HSO : out STD_LOGIC); -- H-Sync Output(VGA, 31kHz)
end ScanConv;
architecture RTL of ScanConv is
--
-- Signals
--
signal CTR12M5 : std_logic_vector(10 downto 0); --
--signal CLK12M5 : std_logic; -- Divider for VGA Sync Signal
signal TS : std_logic_vector(9 downto 0); -- Half of Horizontal
signal OCTR : std_logic_vector(9 downto 0); -- Buffer Output Pointer
signal ICTR : std_logic_vector(9 downto 0); -- Buffer Input Pointer
signal Hi : std_logic_vector(5 downto 0); -- Shift Register for H-Sync Detect(VGA)
signal Si : std_logic_vector(5 downto 0); -- Shift Register for H-Sync Detect(15.6kHz)
signal DO : std_logic_vector(2 downto 0);
--
-- Components
--
component linebuf
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
SBUF : linebuf PORT MAP (
data => RI&GI&BI, -- Input RGB
rdaddress => OCTR, -- Buffer Output Counter
rdclock => CK25M, -- Dot Clock(VGA)
wraddress => ICTR, -- Buffer Input Counter
wrclock => CK16M, -- Dot Clock(15.6kHz)
wren => '1', -- Write only
q => DO -- Output RGB
);
--
-- Buffer Input
--
process( CK16M ) begin
if CK16M'event and CK16M='1' then
-- Filtering HSI
Si<=Si(4 downto 0)&HSI;
-- Counter start
if Si="111000" then
ICTR<="1110000100"; -- X"3B8";
else
ICTR<=ICTR+'1';
end if;
end if;
end process;
--
-- Buffer and Signal Output
--
process( CK25M ) begin
if CK25M'event and CK25M='1' then
-- Filtering HSI
Hi<=Hi(4 downto 0)&HSI;
-- Detect HSYNC
if Hi="111000" then
CTR12M5<=(others=>'0');
TS<=CTR12M5(10 downto 1); -- Half of Horizontal
OCTR<=(others=>'0');
elsif OCTR=TS then
OCTR<=(others=>'0');
CTR12M5<=CTR12M5+'1';
else
OCTR<=OCTR+'1';
CTR12M5<=CTR12M5+'1';
end if;
-- Horizontal Sync genarate
if OCTR=0 then
HSO<='0';
elsif OCTR=96 then
HSO<='1';
end if;
end if;
end process;
--
-- Output
--
RO<=DO(2);
GO<=DO(1);
BO<=DO(0);
end RTL;

1094
mz80b/old/T80/T80.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

194
mz80b/old/T80/T8080se.vhd Normal file
View File

@@ -0,0 +1,194 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

371
mz80b/old/T80/T80_ALU.vhd Normal file
View File

@@ -0,0 +1,371 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

2029
mz80b/old/T80/T80_MCode.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

220
mz80b/old/T80/T80_Pack.vhd Normal file
View File

@@ -0,0 +1,220 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

114
mz80b/old/T80/T80_Reg.vhd Normal file
View File

@@ -0,0 +1,114 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

176
mz80b/old/T80/T80_RegX.vhd Normal file
View File

@@ -0,0 +1,176 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;

262
mz80b/old/T80/T80a.vhd Normal file
View File

@@ -0,0 +1,262 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

192
mz80b/old/T80/T80se.vhd Normal file
View File

@@ -0,0 +1,192 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

179
mz80b/old/T80/T80sed.vhd Normal file
View File

@@ -0,0 +1,179 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

5
mz80b/old/cgrom.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cgrom.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cgrom_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cgrom.cmp"]

198
mz80b/old/cgrom.vhd Normal file
View File

@@ -0,0 +1,198 @@
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: cgrom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY cgrom IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END cgrom;
ARCHITECTURE SYN OF cgrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 2048,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 11,
widthad_b => 11,
width_a => 8,
width_b => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "font.hex"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
-- Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

5
mz80b/old/dpram1kr.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "11.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dpram1kr.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram1kr_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram1kr.cmp"]

234
mz80b/old/dpram1kr.vhd Normal file
View File

@@ -0,0 +1,234 @@
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram1kr.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram1kr IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END dpram1kr;
ARCHITECTURE SYN OF dpram1kr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_b : STRING;
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 8,
width_a => 8,
width_b => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./logic/kmap_80c.hex"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

5
mz80b/old/dpram2k.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "12.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dpram2k.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram2k_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram2k.cmp"]

270
mz80b/old/dpram2k.vhd Normal file
View File

@@ -0,0 +1,270 @@
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram2k.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram2k IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END dpram2k;
ARCHITECTURE SYN OF dpram2k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock1 : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 2048,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
widthad_b => 11,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clock0 => clock_a,
wren_a => wren_a,
address_b => address_b,
clock1 => clock_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "vramtest0.hex"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

203
mz80b/old/keymatrix.vhd Normal file
View File

@@ -0,0 +1,203 @@
--
-- keymatrix.vhd
--
-- Convert from PS/2 key-matrix to MZ-80B/2000 key-matrix module
-- for MZ-80B on FPGA
--
-- Nibbles Lab. 2005-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keymatrix is
Port (
-- i8255/PIO
ZRST_x : in std_logic;
STROBE : in std_logic_vector(3 downto 0);
STALL : in std_logic;
KDATA : out std_logic_vector(7 downto 0);
-- PS/2 Keyboard Data
KCLK : in std_logic; -- Key controller base clock
KBEN : in std_logic; -- PS/2 Keyboard Data Valid
KBDT : in std_logic_vector(7 downto 0); -- PS/2 Keyboard Data
-- for Debug
LDDAT : out std_logic_vector(7 downto 0);
-- Avalon Bus
RRST_x : in std_logic; -- NiosII Reset
RCLK : in std_logic; -- NiosII Clock
RADR : in std_logic_vector(15 downto 0); -- NiosII Address Bus
RCS_x : in std_logic; -- NiosII Read Signal
RWE_x : in std_logic; -- NiosII Write Signal
RDI : in std_logic_vector(7 downto 0); -- NiosII Data Bus(in)
RDO : out std_logic_vector(7 downto 0) -- NiosII Data Bus(out)
);
end keymatrix;
architecture Behavioral of keymatrix is
--
-- prefix flag
--
signal FLGF0 : std_logic;
signal FLGE0 : std_logic;
--
-- MZ-series matrix registers
--
signal SCAN00 : std_logic_vector(7 downto 0);
signal SCAN01 : std_logic_vector(7 downto 0);
signal SCAN02 : std_logic_vector(7 downto 0);
signal SCAN03 : std_logic_vector(7 downto 0);
signal SCAN04 : std_logic_vector(7 downto 0);
signal SCAN05 : std_logic_vector(7 downto 0);
signal SCAN06 : std_logic_vector(7 downto 0);
signal SCAN07 : std_logic_vector(7 downto 0);
signal SCAN08 : std_logic_vector(7 downto 0);
signal SCAN09 : std_logic_vector(7 downto 0);
signal SCAN10 : std_logic_vector(7 downto 0);
signal SCAN11 : std_logic_vector(7 downto 0);
signal SCAN12 : std_logic_vector(7 downto 0);
signal SCAN13 : std_logic_vector(7 downto 0);
signal SCAN14 : std_logic_vector(7 downto 0);
signal SCANLL : std_logic_vector(7 downto 0);
--
-- Key code exchange table
--
signal MTEN : std_logic_vector(3 downto 0);
signal MTDT : std_logic_vector(7 downto 0);
signal F_KBDT : std_logic_vector(7 downto 0);
--
-- Backdoor Access
--
signal RWEN : std_logic;
signal RCSK_x : std_logic;
--
-- Components
--
component dpram1kr
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
MAP0 : dpram1kr PORT MAP (
data => RDI,
rdaddress => F_KBDT,
rdclock => KCLK,
wraddress => RADR(7 downto 0),
wrclock => RCLK,
wren => RWEN,
q => MTDT
);
--
-- Convert
--
process( ZRST_x, KCLK ) begin
if ZRST_x='0' then
SCAN00<=(others=>'0');
SCAN01<=(others=>'0');
SCAN02<=(others=>'0');
SCAN03<=(others=>'0');
SCAN04<=(others=>'0');
SCAN05<=(others=>'0');
SCAN06<=(others=>'0');
SCAN07<=(others=>'0');
SCAN08<=(others=>'0');
SCAN09<=(others=>'0');
SCAN10<=(others=>'0');
SCAN11<=(others=>'0');
SCAN12<=(others=>'0');
SCAN13<=(others=>'0');
SCAN14<=(others=>'0');
FLGF0<='0';
FLGE0<='0';
MTEN<=(others=>'0');
F_KBDT<=(others=>'1');
elsif KCLK'event and KCLK='1' then
MTEN<=MTEN(2 downto 0)&KBEN;
if KBEN='1' then
case KBDT is
when X"AA" => F_KBDT<=X"EF";
when X"F0" => FLGF0<='1'; F_KBDT<=X"EF";
when X"E0" => FLGE0<='1'; F_KBDT<=X"EF";
when others => F_KBDT(6 downto 0)<=KBDT(6 downto 0); F_KBDT(7)<=FLGE0 or KBDT(7); FLGE0<='0';
end case;
end if;
if MTEN(3)='1' then
case MTDT(7 downto 4) is
when "0000" => SCAN00(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0001" => SCAN01(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0010" => SCAN02(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0011" => SCAN03(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0100" => SCAN04(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0101" => SCAN05(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0110" => SCAN06(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0111" => SCAN07(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1000" => SCAN08(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1001" => SCAN09(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1010" => SCAN10(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1011" => SCAN11(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1100" => SCAN12(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1101" => SCAN13(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1110" => SCAN14(conv_integer(MTDT(2 downto 0)))<=not FLGF0;
when others => SCAN14(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
end case;
end if;
end if;
end process;
STROBE_L : for I in 0 to 7 generate
SCANLL(I)<=SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I)
or SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I)
or SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I);
end generate STROBE_L;
--
-- response from key access
--
KDATA<=(not SCANLL) when STALL='0' else
(not SCAN00) when STROBE="0000" else
(not SCAN01) when STROBE="0001" else
(not SCAN02) when STROBE="0010" else
(not SCAN03) when STROBE="0011" else
(not SCAN04) when STROBE="0100" else
(not SCAN05) when STROBE="0101" else
(not SCAN06) when STROBE="0110" else
(not SCAN07) when STROBE="0111" else
(not SCAN08) when STROBE="1000" else
(not SCAN09) when STROBE="1001" else
(not SCAN10) when STROBE="1010" else
(not SCAN11) when STROBE="1011" else
(not SCAN12) when STROBE="1100" else
(not SCAN13) when STROBE="1101" else (others=>'1');
--
-- NiosII access
--
RCSK_x<='0' when RADR(15 downto 8)="11000000" else '1';
RWEN<=not(RWE_x or RCSK_x);
RDO<=(others=>'0');
end Behavioral;

5
mz80b/old/linebuf.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "12.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "linebuf.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf.cmp"]

Some files were not shown because too many files have changed in this diff Show More