commit 4a64af4a0090f0f2ce00f6bbcad390b6bc36e64a
Author: Philip Smart <support@nowhere.com>
Date:   Fri Oct 25 17:16:34 2019 +0100

    Initial commit

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+# Sharp MZ Series Personal and Business Computer Emulation
+Written by Philip Smart, 2018 for the Terasic DE10 Nano board under the MiSTer framework.
+
+This project aims to provide full emulation (along with extensions) of the Sharp MZ Series Computers.
+
+The following emulations have been written
+  - MZ80K                                                              
+  - MZ80C
+  - MZ1200 
+  - MZ80A
+  - MZ700
+  
+ and the following are under development:
+ - MZ800
+ - MZ80B
+ - MZ2000
+
+The current emulations provide:
+
+  -	48K RAM for MZ80K,C,1200,A
+  -	64K RAM for MZ700
+  -	Hardware Tape Read/Write with selectable 1x - 32x Fast Mode
+  -	Turbo Mode 1x - 32x (ie. 112MHz for MZ700)
+  -	Programmable Character Generator (PCG-8000/PCG-1200)
+  -	40x25, 80x25 Mono and Colour Display Modes
+  -	320x200, 640x200 8 Colour Bit addressed Graphics
+  -	Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type.
+  -	i8253 mono audio
+
+### Enhancements in test/under development:
+-	Floppy Disk Drive/Controller 5.25"
+-	Quick Disk Controller
+-	Dual digital Joystick Input (MZ700)
+
+### Known Issues
+-	Tape Write isn’t working correctly, I made some structural changes resulting in it no longer working, so this needs to be resolved.
+-	Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A.
+-	HDMI needs to be re-enabled in the design.
+- The Aspect Ratio/Scandoubler options aren’t working on the VGA output.
+
+
+## Installation
+1.	Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide
+2.	Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:-
+
+    scp SharpMZ_MiSTer/releases/SharpMZ_\<date\>.rbf root@\<de10 ip address\>/media/fat/SharpMZ.rbf
+    
+    Target name can be anything you like ending with .rbf
+3.	Make a SharpMZ directory on the SD card, ie:
+
+    ssh root@\<de10 ip address\>
+    
+    mkdir /media/fat/SharpMZ
+4.	Copy any Rom Files, MZF Tape Files, DSK files across to the new directory, ie:
+  
+    scp \*.mzf root@\<de10 ip address\>:/media/fat/SharpMZ/
+5.	Start the MiSTer menu (ie. press the DE10 reset button if it is not showing).
+6.	Select the SharpMZ core (or whatever name you called it).
+7.	The emulator will boot into an MZ80K model with the SP-1002 monitor.
+8.	Press F12 to change the configuration, select Save Config to store it.
+
+## Detail
+
+### Design Summary
+The idea of this design is to keep the emulation as independent of the HPS as possible (so it works standalone), only needing the HPS to set control registers,
+read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
+
+As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
+
+### Menu System
+The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the display parameters, debugging and access to the MiSTer control menu.
+
+### Tape Storage
+
+In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved on to Floppy/Quick Disks.
+
+This menu controls the hardware CMT unit and has the following choices:
+- Load direct to RAM
+
+  This option allows you to load an MZF format tape file (ie. 128 bytes header + code) directly into RAM. It uses the Load Address and Size stored in the header in order to correctly locate the code and also stores the header in the Cassette Work area at 10F0H. After load is completed and warm reset is made, the details of the tape are displayed on-screen. In order to run the loaded program, simply issue the correct monitor command, ie. J1200 (Jump to 1200H where 1200H is shown as the Execution Address in the tape summary).
+- Queue Tape
+
+  A real cassette has 1 or more programs stored on it sequentially. The emulation cache only stores 1 full program so this is a mechanism to line up multiple programs and they will be fed into the emulation cache as it becomes empty, thus simulating a real cassette.
+  Selecting this option presents you with a directory listing of all MZF files. Choose one per selection and it will be added to the Queue. The programs queued will be displayed on the menu.
+- Clear Queue
+
+  This option allows you to purge all queue entries.
+- Save Tape
+
+  This option allows you to save a program to the MiSTer SD card which is in the emulation cache. Normally the emulation would have written a program/data to tape (ie. via the BASIC ‘SAVE’ command) which in reality is stored in the emulation cache.
+  The tape is saved under the name given in the emulation save command (ie. in BASIC ‘SAVE “myfile”’ would result in a file called myfile.mzf being saved).
+- Auto Save Tape
+
+  This option allows you to auto save the emulation cache. Ie. when an emulation save completes, a flag is raised which is seen by the MiSTer program and the emulation cache is saved to SD under the name given in the emulation.
+- Tape Buttons
+
+  This option allows you to set the active Tape buttons, ie. Play, Record or Auto. Auto is a hardware mechanism to detect if the emulation is reading or writing to tape and process accordingly.
+- Fast Tape Load
+
+  This option allows you to set the speed of the tape drive. On the original machines, the tape runs at 1200baud which is quite slow, so use of this option is recommended.
+  
+  You can select one of: "Off", "2x", "4x", "8x", "16x", "32x"
+  
+  Selecting “Off” runs the tape drive at the original speed.
+
+
+### Machine
+The emulation emulates several Sharp MZ computers and this menu allows you to make selections accordingly.
+- Machine Model
+
+  This option allows you to choose which Sharp MZ computer is emulated. Currently the choices are:
+  
+  "MZ80K", "MZ80C", "MZ1200", "MZ80A", "MZ700" with "MZ800", "MZ80B", "MZ2000" in the pipeline.
+- CPU Speed
+
+  This option allows you to set the speed at which the emulation runs. Generally speaking, higher speeds can be beneficial in non-graphics based applications although some games benefit from a small speed boost. The choices are:
+  
+  - MZ80K/C/1200/A  => "2MHz",   "4MHz", "8MHz",  "16MHz", "32MHz", "64MHz"
+  - MZ700           => "3.5MHz", "7MHz", "14MHz", "28MHz", "56MHz", "112MHz"
+- Audio Source
+
+  This option allows you to choose what is played through the audio output. The choices are:
+  
+  - Sound   => The mono audio generated by the emulation output on L/R channels.
+  - Tape    => The CMT signals as sound, Playback on Right channel, Record on Left channel. In theory you should be able to connect the right channel to an external tape drive and record to physical tape.
+- Audio Volume
+
+  This option allows you to set the output volume. There are 16 possible steps from Min .. Max.
+- Audio Mute
+
+  This option allows you to Mute the output.
+- Rom Management
+
+  The emulation comes with the Monitor, Character Generator and Key Mapping Roms built-in for each machine emulated. This option selects a sub-menu which allows you to upload non-standard Roms when the emulation is started (ie. the Core is selected).
+
+  - Machine Model
+
+    This option allows you to select the emulated Sharp MZ computer to which the custom rom images will affect. The choices are:
+
+    "MZ80K", "MZ80C", "MZ1200", "MZ80A", "MZ700" with "MZ800", "MZ80B", "MZ2000" in the pipeline.
+  - User ROM
+
+    On some machine models (ie. MZ80A) there exists a socket to place a User ROM, which will have control passed to it should the first byte be 0 and non-writeable. Although this option only exists on certain models, it is a nice to have feature it is available for all machine models.
+    This option allows you to enable or disable the User ROM (NB. If you enable this option, it only enables hardware select, you still need to upload a ROM which has the first byte set to 0).
+  -	Floppy Disk ROM
+
+    A Floppy Disk drive was an expansion option for the Sharp MZ computers, and with the advent of the MZ700, a Quick Disk drive was also an option. These options typically held control software in a ROM at location F000H. This option allows you to enable this feature, albeit you still need to upload a ROM.
+
+  -	Enable Custom Rom
+    This section allows you to enable custom Roms and select the image which will be uploaded. For each Rom, you can enable or disable. If enabled, you can choose the required file. The Roms which can be customized are:
+    - Monitor (40x25)
+    - Monitor (80x25)
+    -	Char Generator
+    -	Key Mapping
+    -	User Rom
+    -	Floppy Disk
+    
+    The Monitor Rom is a special case. Most of the Personal Sharp MZ Computers were only able to display 40x25 characters so the Rom hardcodes these parameters. Some people required wider screens for use with CPM, so hardware modifications were made to create an 80x25 display. The emulation is capable of both modes but in order to run correctly, a different Monitor Rom for 80x25 display is needed.
+
+
+### Display
+The display on the Sharp MZ computers was originally quite simplistic. In order to cater for enhancements made in each model and by external vendors, the emulation has several configurable parameters which are grouped under this menu.
+
+-	Display Type
+  This option allows you to select the display used. Normally, when a machine model is chosen, it defaults to the original display, this option allows you to override the default. The choices are:
+  
+  "Mono 40x25", "Mono 80x25 ", "Colour 40x25", "Colour 80x25"
+-	Video
+  An extension to the original design was the addition of a graphics frame buffer. It is possible to blend the original display video with the graphics frame buffer. This option allows you to enable or disable the original display video (ie. if you only want graphics). 
+-	Graphics
+  There were various add-on boards made available in order to display bit addressable pixel graphics. This is my extension to the original design and as I gather information on other add-on boards, I will adapt the hardware interface so it accommodates these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
+-	VRAM CPU Wait
+  I deviated from the original design by adding a pixel based display buffer. During the Vertical Blanking period, I expand the character based VRAM and Attribute RAM into pixels and store them in the display buffer (a double buffer technique). This consequently means that no snow/tearing will occur if the CPU accesses the VRAM/Attribute RAM during the visible display period. The original design added software waits (MZ80K) and hardware CPU wait states (MZ80A/700) to eliminate snow/tearing and due to the addition of double buffering, this is no longer needed. You can thus disable the wait states with this option and gain some speed or enable them to keep compatibility.
+-	PCG Mode
+  All of the Sharp MZ computers used character generators which were hard coded in a ROM. External vendors offered add-ons to allow for a Programmable Character Generator based in RAM. This option enables the Programmable Character Generator which is compatible with the HAL PCG-8000/PCG-1200 add-ons.
+-	Aspect Ratio
+  This option is a MiSTer framework extension which converts the Aspect Ratio from 4:3 to 16:9. It doesn’t work at the moment with VGA output but should work on HDMI. Use this option to choose the desired format.
+-	Scandoubler
+  This option is a MiSTer framework extension which doubles the scan lines to widen/improve the image of older computer displays. It doesn’t work correctly with VGA output at the moment but should work on HDMI.
+  
+  The choices are: "None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%"
+
+### System
+This is the MiSTer main control menu which allows you to select a core, map keys etc.
+
+### Debugging
+As you cannot easily get out a trusty Oscilloscope or write breakpoint/debug messages with an FPGA, I’ve added a debugging mode which can be used at any time without affecting the emulation (unless you choose a debug frequency in which case the emulation will run at the selected frequency).
+Basically, the 8 LED’s on the main DE10 main board can display a selectable set of signals, either in auto mode (move from set to set after a fixed period) or a static set. The sample rate of the signals displayed on the LED’s is selectable from the Z80 CPU frequency down to 1Hz. You can also attach an oscilloscope onto the LED’s and thus see the waveform if a simple flicker is not sufficient. In addition, you can slow the CPU frequency down in steps from 1MHz to 1/10Hz so you have a good chance of seeing what is happening internally.
+This debugging addition is also a great method of understanding the internals of a computer and seeing the Z80 in action.
+
+To use the debug mode, press F12 to enter the MiSTer menu, then select Debug and you are offered the following choices:
+-	Select Memory Bank
+
+    This option allows you to select one of the memory banks so it can be written to a local (DE10 SD Card) file.
+  
+    - SysROM     = System ROM. This is the complete concatenated set of Monitor ROM’s for all the emulations.
+    - SysRAM     = System RAM. This is the 64K Main RAM.
+    - KeyMap     = Key Mapping ROM. This is the complete concatenated set of Key Mapping’s for all the emulations.
+    - VRAM       = Video RAM. This is the 2K Video RAM concatenated with the 2K Attribute RAM.
+    - CMTHDR     = Cassette Header. This is the 128 byte memory holding the last loaded or saved tape header.
+    - CMTDATA    = Cassette Data. This is the 64K memory holding the last loaded or saved tape data.
+    - CGROM      = Character Generator ROM. This is the complete concatenated set of CGROM’s for all the emulations.
+    - CGRAM      = Character Generator RAM. This is the 2K contents of the Programmable Character Generator RAM.
+    - All        = This is the complete memory set as one file.
+  
+-	Dump To <memory bank name>
+    Dump the selected memory bank. The system will show the file name used for the dump.
+  
+-	Debug Mode
+    Select to Enable or Disable
+  
+  -	CPU Frequency
+    Select the CPU Frequency which can be one of:
+    
+    "CPU/CMT", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz"
+    
+  -	Debug LEDS
+    Select to Enable or Disable
+    
+  -	Sample Freq
+    This is the sampling frequency used to sample the displayed signals. It can be one of:
+    
+    "CPU/CMT", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz"
+    
+  -	Signal Block
+    This is the signal block for display. It can be one of:
+    
+    - T80               => CPU Address/Data Bus and associated signals.
+    - I/O               => Video, Keyboard and Select signals.
+    - IOCTL             => External I/O Control. Address/Data and Select signals.
+    - Config            => Register configuration signals.
+    - MZ80C I           => 5 sets of signals relating to the MZ80K/C/1200/A/700/800.
+    - MZ80C II          => An additional 5 sets of signals.
+    - MZ80B I           => 5 sets of signals relating to the MZ80B/MZ2000.
+    - MZ80B II          => An additional 5 sets of signals.
+    
+  -	Bank
+    This is the Bank within the Block to be displayed on the LED’s. It can be one of:
+    
+    - T80               => "Auto",   "A7-0",     "A15-8",    "DI",       "Signals"
+    - I/O               => "Auto",   "Video",    "PS2Key",   "Signals"
+    - IOCTL             => "Auto",   "A23-16",   "A15-8",    "A7-0",     "Signals"
+    - Config            => "Auto",   "Config 1", "Config 2", "Config 3", "Config 4", "Config 5"
+    - MZ80C I           => "Auto",   "CS 1",     "CS 2",     "CS 3",     "INT/RE",   "Clk"
+    - MZ80C II          => "Auto",   "CMT 1",    "CMT 2",    "CMT 3"
+    - MZ80B I           => Not yet defined.
+    - MZ80B II          => Not yet defined.
+
+
+### Graphics Frame Buffer
+An addition to the original design is a 640x200/320x200 8 colour Graphics frame buffer. There were many additions to the Sharp MZ series to allow graphics (ie. MZ80B comes with standard mono graphics) display and as I don’t have detailed information of these to date, I designed my own extension with the intention of adding hardware abstraction layers at a later date to add compatibility to external vendor add-ons.
+
+This frame buffer is made up of 3x16K RAM blocks, 1 per colour with a resolution of 640x200 which matches the output display buffer bit for bit. If the display is working at 40x25 characters then the resolution is 320x200, otherwise for 80x25 it is 640x200.
+
+The RAM for the Graphics frame buffer can be switched into the main CPU address range C000H – FFFFH by programmable registers, 1 bank at a time (ie. Red, Green, Blue banks). This allows for direct CPU addressable pixels to be read and/or written. Each pixel is stored in groups of 8 (1 byte in RAM) scanning from right to left per byte, left to right per row, top to bottom. Ie. if the Red bank is mapped into CPU address space, the byte at C000H represents pixels 7 - 0 of 320/640 (X) at pixel 0 of 200 (Y). Thus 01H written to C000H would set Pixel 7 (X) on Row 0 (Y). This applies for Green and Blue banks when mapped into CPU address space.
+
+In order to speed up display, there is a Colour Write register, so that a write to the graphics RAM will update all 3 banks at the same time.
+
+The programmable registers are as follows:
+
+*Switching Graphics RAM Bank into ZPU CPU Address Range*
+
+- Graphics Bank Switch Set Register: I/O Address: E8H (232 decimal)
+
+  Switches in 1 of the 16Kb Graphics RAM pages (of the 3 pages) to C000 - FFFF. The bank which is switched in is set in the Control Register by bits 1/0 for Read operations and 3/2 for Write operations. This bank switch overrides all MZ80A/MZ700 page switching functions.
+- Graphics Bank Switch Reset Register: I/O Address: E9H (233 decimal)
+
+  Switches out the Graphics RAM and returns to previous state.
+
+*Control Register: I/O Address: EAH (234 decimal)*
+
+- Bit 1:0 
+Read mode (00=Red Bank, 01=Green Bank, 10=Blue Bank, 11=Not used). Select which bank to be read when enabled in CPU address space.
+
+- Bit 3:2
+Write mode (00=Red Bank, 01=Green Bank, 10=Blue Bank, 11=Indirect). Select which bank to be written to when enabled in CPU address space.
+
+- Bit 4
+VRAM Output. 0=Enable, 1=Disable. Output Character RAM to the display.
+
+- Bit 5
+GRAM Output. 0=Enable, 1=Disable. Output Graphics RAM to the display.
+
+- Bit 7:6
+Blend Operator (00=OR ,01=AND, 10=NAND, 11=XOR). Operator to blend Character display with Graphics Display.
+
+*Red Colour Writer Register: I/O Address: EBH (235 decimal)*
+
+- Bit 0 Pixel 7 Set to Red during indirect write.
+- Bit 1 Pixel 6
+- Bit 2 Pixel 5
+- Bit 3 Pixel 4
+- Bit 4 Pixel 3
+- Bit 5 Pixel 2
+- Bit 6 Pixel 1
+- Bit 7 Pixel 0 Set to Red during indirect write.
+
+*Green Colour Writer Register: I/O Address: ECH (236 decimal)*
+- Bit 0 Pixel 7 Set to Green during indirect write.
+- Bit 1 Pixel 6
+- Bit 2 Pixel 5
+- Bit 3 Pixel 4
+- Bit 4 Pixel 3
+- Bit 5 Pixel 2
+- Bit 6 Pixel 1
+- Bit 7 Pixel 0 Set to Green during indirect write.
+
+*Blue Colour Writer Register: I/O Address: EDH (237 decimal)*
+- Bit 0 Pixel 7 Set to Blue during indirect write.
+- Bit 1 Pixel 6
+- Bit 2 Pixel 5
+- Bit 3 Pixel 4
+- Bit 4 Pixel 3
+- Bit 5 Pixel 2
+- Bit 6 Pixel 1
+- Bit 7 Pixel 0 Set to Blue during indirect write.
+
+For Indirect mode (Control Register bits 3/2 set to 11), a write to the Graphics RAM when mapped into CPU address space C000H – FFFFH will see the byte masked by the Red Colour Writer Register and written to the Red Bank with the same operation for Green and Blue. This allows rapid setting of a colour across the 3 banks.
+
+## Credits
+My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab and his excellent work.
+
+Also credit to Sorgelig for his hard work in creating the MiSTer framework and design of some excellent hardware add-ons. The MiSTer framework makes it significantly easier to design/port emulations.
+
+## Links
+The Sharp MZ Series Computers were not as wide spread as Commodore, Atari or Sinclair but they had a dedicated following. Given their open design it was very easy to modify and extend applications such as the BASIC interpreters and likewise easy to add hardware extension. As such, a look round the web finds some very comprehensive User Groups with invaluable resources. If you need manuals, programs, information then please look (for starters) at the following sites:
+
+- https://original.sharpmz.org/
+- https://www.sharpmz.no/
+- https://mz-80a.com
+- http://www.sharpusersclub.org/
+- http://www.scav.cz/uvod.htm (use chrome to auto translate Czech)
+
diff --git a/bridge.vhd b/bridge.vhd
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--- /dev/null
+++ b/bridge.vhd
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+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            bridge.vhd
+-- Created:         November 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series compatible logic IO Control.
+--                                                     
+--                  This module is the IO control layer which provides io services to the emulation,
+--                  which at time of writing can come from the DE10 Nano HPS or the soft-core STORM
+--                  or NEO430 microcontroller.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         November 2018 - Initial creation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity bridge is
+  port(
+        --------------------                Clock Input                         ----------------------------     
+        clkmaster             : in    std_logic;                                -- Master Clock(50MHz)
+        clksys                : out   std_logic;                                -- System clock.
+        clkvid                : out   std_logic;                                -- Pixel base clock of video.
+        --------------------             Reset                                  ----------------------------
+        cold_reset            : in    std_logic;
+        warm_reset            : in    std_logic;
+        --------------------                     main_leds                      ----------------------------
+        main_leds             : out   std_logic_vector(7 downto 0);             -- main_leds Green[7:0]
+        --------------------                     PS2                            ----------------------------
+        ps2_key               : in    std_logic_vector(10 downto 0);            -- PS2 Key data.
+        --------------------                     VGA                            ----------------------------
+        vga_hb_o              : out   std_logic;                                -- VGA Horizontal Blank
+        vga_vb_o              : out   std_logic;                                -- VGA Vertical Blank
+        vga_hs_o              : out   std_logic;                                -- VGA H_SYNC
+        vga_vs_o              : out   std_logic;                                -- VGA V_SYNC
+        vga_r_o               : out   std_logic_vector(7 downto 0);             -- VGA Red[3:0], [7:4] = 0
+        vga_g_o               : out   std_logic_vector(7 downto 0);             -- VGA Green[3:0]
+        vga_b_o               : out   std_logic_vector(7 downto 0);             -- VGA Blue[3:0]
+        --------------------                     AUDIO                          ------------------------------
+        audio_l_o             : out   std_logic;
+        audio_r_o             : out   std_logic;
+
+        uart_rx               : in    std_logic;
+        uart_tx               : out   std_logic; 
+        sd_sck                : out   std_logic; 
+        sd_mosi               : out   std_logic; 
+        sd_miso               : in    std_logic; 
+        sd_cs                 : out   std_logic;
+        sd_cd                 : out   std_logic; 
+        --------------------                   HPS Interface                    ------------------------------
+        ioctl_download        : in    std_logic;                                -- HPS Downloading to FPGA.
+        ioctl_upload          : in    std_logic;                                -- HPS Uploading from FPGA.
+        ioctl_clk             : in    std_logic;                                -- HPS I/O Clock.
+        ioctl_wr              : in    std_logic;                                -- HPS Write Enable to FPGA.
+        ioctl_rd              : in    std_logic;                                -- HPS Read Enable from FPGA.
+        ioctl_addr            : in    std_logic_vector(24 downto 0);            -- HPS Address in FPGA to write into.
+        ioctl_dout            : in    std_logic_vector(15 downto 0);            -- HPS Data to be written into FPGA.
+        ioctl_din             : out   std_logic_vector(15 downto 0)             -- HPS Data to be read into HPS.
+);
+end bridge;
+
+architecture rtl of bridge is
+
+--
+-- Signals.
+--
+signal CON_CLKMASTER          :       std_logic;
+signal CON_CLKSYS             :       std_logic;
+signal CON_CLKVID             :       std_logic;
+signal CON_CLKIOP             :       std_logic;
+signal CON_COLD_RESET         :       std_logic;
+signal CON_WARM_RESET         :       std_logic;
+signal CON_MAIN_LEDS          :       std_logic_vector(7 downto 0);
+signal CON_PS2_KEY            :       std_logic_vector(10 downto 0);
+signal CON_VGA_HB_O           :       std_logic;
+signal CON_VGA_VB_O           :       std_logic;
+signal CON_VGA_HS_O           :       std_logic;
+signal CON_VGA_VS_O           :       std_logic;
+signal CON_VGA_R_O            :       std_logic_vector(7 downto 0);
+signal CON_VGA_G_O            :       std_logic_vector(7 downto 0);
+signal CON_VGA_B_O            :       std_logic_vector(7 downto 0);
+signal CON_AUDIO_L_O          :       std_logic;
+signal CON_AUDIO_R_O          :       std_logic;
+signal CON_IOCTL_DOWNLOAD     :       std_logic;
+signal CON_IOCTL_UPLOAD       :       std_logic;
+signal CON_IOCTL_CLK          :       std_logic;
+signal CON_IOCTL_WR           :       std_logic;
+signal CON_IOCTL_RD           :       std_logic;
+signal CON_IOCTL_ADDR         :       std_logic_vector(24 downto 0);
+signal CON_IOCTL_DOUT         :       std_logic_vector(31 downto 0);
+signal CON_IOCTL_DIN          :       std_logic_vector(31 downto 0);
+--
+-- IO Processor Signals.
+--
+signal IOP_IOCTL_DOWNLOAD     :       std_logic;
+signal IOP_IOCTL_UPLOAD       :       std_logic;
+signal IOP_IOCTL_CLK          :       std_logic;
+signal IOP_IOCTL_WR           :       std_logic;
+signal IOP_IOCTL_RD           :       std_logic;
+signal IOP_IOCTL_ADDR         :       std_logic_vector(24 downto 0);
+signal IOP_IOCTL_DOUT         :       std_logic_vector(31 downto 0);
+signal IOP_IOCTL_DIN          :       std_logic_vector(31 downto 0);
+signal IOP_IOCTL_SENSE        :       std_logic;
+signal IOP_IOCTL_SELECT       :       std_logic;
+--
+--
+--
+signal CON_UART_TX            :       std_logic;
+signal CON_UART_RX            :       std_logic;
+signal CON_SPI_SCLK           :       std_logic;
+signal CON_SPI_MOSI           :       std_logic;
+signal CON_SPI_MISO           :       std_logic;
+signal CON_SPI_CS             :       std_logic_vector(7 downto 0);
+
+--
+-- Components
+--
+component sharpmz
+    port (
+        --------------------                Clock Input                         ----------------------------     
+        CLKMASTER             : in    std_logic;                                -- Master Clock(50MHz)
+        CLKSYS                : out   std_logic;                                -- System clock.
+        CLKVID                : out   std_logic;                                -- Pixel base clock of video.
+        CLKIOP                : out   std_logic;                                -- IO processor clock.
+        --------------------             Reset                                  ----------------------------
+        COLD_RESET            : in    std_logic;
+        WARM_RESET            : in    std_logic;
+        --------------------                     main_leds                      ----------------------------
+        MAIN_LEDS             : out   std_logic_vector(7 downto 0);             -- main_leds Green[7:0]
+        --------------------                     PS2                            ----------------------------
+        PS2_KEY               : in    std_logic_vector(10 downto 0);            -- PS2 Key data.
+        --------------------                     VGA                            ----------------------------
+        VGA_HB_O              : out   std_logic;                                -- VGA Horizontal Blank
+        VGA_VB_O              : out   std_logic;                                -- VGA Vertical Blank
+        VGA_HS_O              : out   std_logic;                                -- VGA H_SYNC
+        VGA_VS_O              : out   std_logic;                                -- VGA V_SYNC
+        VGA_R_O               : out   std_logic_vector(7 downto 0);             -- VGA Red[3:0], [7:4] = 0
+        VGA_G_O               : out   std_logic_vector(7 downto 0);             -- VGA Green[3:0]
+        VGA_B_O               : out   std_logic_vector(7 downto 0);             -- VGA Blue[3:0]
+        --------------------                     AUDIO                          ------------------------------
+        AUDIO_L_O             : out   std_logic;
+        AUDIO_R_O             : out   std_logic;
+        --------------------                   HPS Interface                    ------------------------------
+        IOCTL_DOWNLOAD        : in    std_logic;                                -- Downloading to FPGA.
+        IOCTL_UPLOAD          : in    std_logic;                                -- Uploading from FPGA.
+        IOCTL_CLK             : in    std_logic;                                -- I/O Clock.
+        IOCTL_WR              : in    std_logic;                                -- Write Enable to FPGA.
+        IOCTL_RD              : in    std_logic;                                -- Read Enable from FPGA.
+        IOCTL_ADDR            : in    std_logic_vector(24 downto 0);            -- Address in FPGA to write into.
+        IOCTL_DOUT            : in    std_logic_vector(31 downto 0);            -- Data to be written into FPGA.
+        IOCTL_DIN             : out   std_logic_vector(31 downto 0)             -- Data to be read into HPS.
+    );
+end component;
+
+component STORM_SoC
+    port (
+        -- Global Control --
+        CLK_I                 : in    std_logic;
+        RST_I                 : in    std_logic;
+
+        -- General purpose (debug) UART --
+        UART0_RXD_I           : in    std_logic;
+        UART0_TXD_O           : out   std_logic;
+
+        -- System Control --
+        START_I               : in    std_logic; -- low active
+        BOOT_CONFIG_I         : in    std_logic_vector(03 downto 0); -- low active
+        LED_BAR_O             : out   std_logic_vector(07 downto 0);
+
+        -- GP Input Pins --
+        GP_INPUT_I            : in    std_logic_vector(07 downto 0);
+
+        -- GP Output Pins --
+        GP_OUTPUT_O           : out   std_logic_vector(07 downto 0);
+
+        -- I�C Port --
+        I2C_SCL_IO            : inout std_logic;
+        I2C_SDA_IO            : inout std_logic;
+
+        -- SPI Port 0 [3 devices] --
+        SPI_P0_CLK_O          : out   std_logic;
+        SPI_P0_MISO_I         : in    std_logic;
+        SPI_P0_MOSI_O         : out   std_logic;
+        SPI_P0_CS_O           : out   std_logic_vector(02 downto 0);
+
+        -- SPI Port 1 [3 devices] --
+        SPI_P1_CLK_O          : out   std_logic;
+        SPI_P1_MISO_I         : in    std_logic;
+        SPI_P1_MOSI_O         : out   std_logic;
+        SPI_P1_CS_O           : out   std_logic_vector(02 downto 0);
+
+        -- SPI Port 2 [2 devices] --
+        SPI_P2_CLK_O          : out   std_logic;
+        SPI_P2_MISO_I         : in    std_logic;
+        SPI_P2_MOSI_O         : out   std_logic;
+        SPI_P2_CS_O           : out   std_logic_vector(01 downto 0);
+
+        -- PWM Port 0 --
+--      PWM0_PORT_O           : out   std_logic_vector(07 downto 0)
+
+        -- IOCTL Bus --
+        IOCTL_DOWNLOAD        : out   std_logic;                                  -- Downloading to FPGA.
+        IOCTL_UPLOAD          : out   std_logic;                                  -- Uploading from FPGA.
+        IOCTL_CLK             : out   std_logic;                                  -- I/O Clock.
+        IOCTL_WR              : out   std_logic;                                  -- Write Enable to FPGA.
+        IOCTL_RD              : out   std_logic;                                  -- Read Enable from FPGA.
+        IOCTL_SENSE           : in    std_logic;                                  -- Sense to see if HPS accessing ioctl bus.
+        IOCTL_SELECT          : out   std_logic;                                  -- Enable IOP control over ioctl bus.
+        IOCTL_ADDR            : out   std_logic_vector(24 downto 0);              -- Address in FPGA to write into.
+        IOCTL_DOUT            : out   std_logic_vector(31 downto 0);              -- Data to be written into FPGA.
+        IOCTL_DIN             : in    std_logic_vector(31 downto 0)               -- Data to be read into HPS.
+
+--      -- SDRAM Interface --
+--      SDRAM_CLK_O           : out   std_logic;
+--      SDRAM_CSN_O           : out   std_logic;
+--      SDRAM_CKE_O           : out   std_logic;
+--      SDRAM_RASN_O          : out   std_logic;
+--      SDRAM_CASN_O          : out   std_logic;
+--      SDRAM_WEN_O           : out   std_logic;
+--      SDRAM_DQM_O           : out   std_logic_vector(01 downto 0);
+--      SDRAM_BA_O            : out   std_logic_vector(01 downto 0);
+--      SDRAM_ADR_O           : out   std_logic_vector(11 downto 0);
+--      SDRAM_DAT_IO          : inout std_logic_vector(15 downto 0)
+    );
+end component;
+
+component neo430
+    generic (
+        -- general configuration --
+        CLOCK_SPEED           : natural := 100000000; -- main clock in Hz
+        IMEM_SIZE             : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
+        DMEM_SIZE             : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
+        -- additional configuration --
+        USER_CODE             : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
+        -- module configuration --
+        DADD_USE              : boolean := true; -- implement DADD instruction? (default=true)
+        MULDIV_USE            : boolean := true; -- implement multiplier/divider unit? (default=true)
+        WB32_USE              : boolean := false;-- implement WB32 unit? (default=true)
+        WDT_USE               : boolean := true; -- implement WDT? (default=true)
+        GPIO_USE              : boolean := true; -- implement GPIO unit? (default=true)
+        TIMER_USE             : boolean := true; -- implement timer? (default=true)
+        UART_USE              : boolean := true; -- implement UART? (default=true)
+        CRC_USE               : boolean := true; -- implement CRC unit? (default=true)
+        CFU_USE               : boolean := true; -- implement custom functions unit? (default=false)
+        PWM_USE               : boolean := true; -- implement PWM controller?
+        TWI_USE               : boolean := true; -- implement two wire serial interface? (default=true)
+        SPI_USE               : boolean := true; -- implement SPI? (default=true)
+        -- boot configuration --
+        BOOTLD_USE            : boolean := true; -- implement and use bootloader? (default=true)
+        IMEM_AS_ROM           : boolean := false -- implement IMEM as read-only memory? (default=false)
+   );
+    port (
+        -- global control --
+        clk_i                 : in    std_logic; -- global clock, rising edge
+        rst_i                 : in    std_logic; -- global reset, async, low-active
+        -- gpio --
+        gpio_o                : out   std_logic_vector(15 downto 0); -- parallel output
+        gpio_i                : in    std_logic_vector(15 downto 0); -- parallel input
+        -- pwm channels --
+        pwm_o                 : out   std_logic_vector(02 downto 0); -- pwm channels
+        -- serial com --
+        uart_txd_o            : out   std_logic; -- UART send data
+        uart_rxd_i            : in    std_logic; -- UART receive data
+        spi_sclk_o            : out   std_logic; -- serial clock line
+        spi_mosi_o            : out   std_logic; -- serial data line out
+        spi_miso_i            : in    std_logic; -- serial data line in
+        spi_cs_o              : out   std_logic_vector(07 downto 0); -- SPI CS 0..7
+        twi_sda_io            : inout std_logic; -- twi serial data line
+        twi_scl_io            : inout std_logic; -- twi serial clock line
+        -- IOCTL Bus --
+        ioctl_download        : out   std_logic;                                  -- Downloading to FPGA.
+        ioctl_upload          : out   std_logic;                                  -- Uploading from FPGA.
+        ioctl_clk             : out   std_logic;                                  -- I/O Clock.
+        ioctl_wr              : out   std_logic;                                  -- Write Enable to FPGA.
+        ioctl_rd              : out   std_logic;                                  -- Read Enable from FPGA.
+        ioctl_sense           : in    std_logic;                                  -- Sense to see if HPS accessing ioctl bus.
+        ioctl_select          : out   std_logic;                                  -- Enable CFU control over ioctl bus.
+        ioctl_addr            : out   std_logic_vector(24 downto 0);              -- Address in FPGA to write into.
+        ioctl_dout            : out   std_logic_vector(31 downto 0);              -- Data to be written into FPGA.
+        ioctl_din             : in    std_logic_vector(31 downto 0);              -- Data to be read into HPS.
+        -- 32-bit wishbone interface --
+        wb_adr_o              : out   std_logic_vector(31 downto 0); -- address
+        wb_dat_i              : in    std_logic_vector(31 downto 0); -- read data
+        wb_dat_o              : out   std_logic_vector(31 downto 0); -- write data
+        wb_we_o               : out   std_logic; -- read/write
+        wb_sel_o              : out   std_logic_vector(03 downto 0); -- byte enable
+        wb_stb_o              : out   std_logic; -- strobe
+        wb_cyc_o              : out   std_logic; -- valid cycle
+        wb_ack_i              : in    std_logic; -- transfer acknowledge
+        -- interrupts --
+        irq_i                 : in    std_logic; -- external interrupt request line
+        irq_ack_o             : out   std_logic  -- external interrupt request acknowledge
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    SHARPMZ_0 : sharpmz
+        port map (
+            --------------------                Clock Input                         ----------------------------     
+            CLKMASTER             => CON_CLKMASTER,                                 -- Master Clock(50MHz)
+            CLKSYS                => CON_CLKSYS,                                    -- System clock.
+            CLKVID                => CON_CLKVID,                                    -- Pixel base clock of video.
+            CLKIOP                => CON_CLKIOP,                                    -- IO Processor Clock.
+            --------------------                                                    ----------------------------
+            COLD_RESET            => CON_COLD_RESET,
+            WARM_RESET            => CON_WARM_RESET,
+            --------------------                                                    ----------------------------
+            MAIN_LEDS             => CON_MAIN_LEDS,                                 -- main_leds Green[7:0]
+            --------------------                                                    ----------------------------
+            PS2_KEY               => CON_PS2_KEY,                                   -- PS2 Key data.
+            --------------------                                                    ----------------------------
+            VGA_HB_O              => CON_VGA_HB_O,                                  -- VGA Horizontal Blank
+            VGA_VB_O              => CON_VGA_VB_O,                                  -- VGA Vertical Blank
+            VGA_HS_O              => CON_VGA_HS_O,                                  -- VGA H_SYNC
+            VGA_VS_O              => CON_VGA_VS_O,                                  -- VGA V_SYNC
+            VGA_R_O               => CON_VGA_R_O,                                   -- VGA Red[3:0], [7:4] = 0
+            VGA_G_O               => CON_VGA_G_O,                                   -- VGA Green[3:0]
+            VGA_B_O               => CON_VGA_B_O,                                   -- VGA Blue[3:0]
+            --------------------                                                    ------------------------------
+            AUDIO_L_O             => CON_AUDIO_L_O,
+            AUDIO_R_O             => CON_AUDIO_R_O,
+            --------------------                                                    ------------------------------
+            IOCTL_DOWNLOAD        => CON_IOCTL_DOWNLOAD,                            -- Downloading to FPGA.
+            IOCTL_UPLOAD          => CON_IOCTL_UPLOAD,                              -- Uploading from FPGA.
+            IOCTL_CLK             => CON_IOCTL_CLK,                                 -- I/O Clock.
+            IOCTL_WR              => CON_IOCTL_WR,                                  -- Write Enable to FPGA.
+            IOCTL_RD              => CON_IOCTL_RD,                                  -- Read Enable from FPGA.
+            IOCTL_ADDR            => CON_IOCTL_ADDR,                                -- Address in FPGA to write into.
+            IOCTL_DOUT            => CON_IOCTL_DOUT,                                -- Data to be written into FPGA.
+            IOCTL_DIN             => CON_IOCTL_DIN                                  -- Data to be read into HPS.
+    );
+
+    -- If enabled, instantiate the local STORM IO processor to provide IO and user interface services.
+    --
+    STORM_ENABLED: if STORM_ENABLE = 1 generate
+      STORM_0: STORM_SoC
+        port map (
+            -- Global Control --
+            CLK_I                 => CON_CLKIOP,                                    -- global clock, rising edge
+            RST_I                 => (CON_COLD_RESET or CON_WARM_RESET),            -- global reset, async
+
+            -- General purpose (debug) UART --
+            UART0_RXD_I           => CON_UART_RX,
+            UART0_TXD_O           => CON_UART_TX,
+
+            -- System Control --
+            START_I               => '1',
+            BOOT_CONFIG_I         => "0000",
+            LED_BAR_O             => open,
+
+            -- GP Input Pins --
+            GP_INPUT_I            => x"FF",
+
+            -- GP Output Pins --
+            GP_OUTPUT_O           => open,
+
+            -- I�C Port --
+            I2C_SCL_IO            => open,
+            I2C_SDA_IO            => open,
+
+            -- SPI Port 0 [3 devices] --
+            SPI_P0_CLK_O          => CON_SPI_SCLK,
+            SPI_P0_MISO_I         => CON_SPI_MISO,
+            SPI_P0_MOSI_O         => CON_SPI_MOSI,
+            SPI_P0_CS_O           => CON_SPI_CS(2 downto 0),
+
+            -- SPI Port 1 [3 devices] --
+            SPI_P1_CLK_O          => open,
+            SPI_P1_MISO_I         => '0',
+            SPI_P1_MOSI_O         => open,
+            SPI_P1_CS_O           => open,
+
+            -- SPI Port 2 [2 devices] --
+            SPI_P2_CLK_O          => open,
+            SPI_P2_MISO_I         => '0',
+            SPI_P2_MOSI_O         => open,
+            SPI_P2_CS_O           => open,
+
+            -- PWM Port 0 --
+--          PWM0_PORT_O           => open
+
+            -- IOCTL Bus --
+            IOCTL_DOWNLOAD        => IOP_IOCTL_DOWNLOAD,                            -- Downloading to FPGA.
+            IOCTL_UPLOAD          => IOP_IOCTL_UPLOAD,                              -- Uploading from FPGA.
+            IOCTL_CLK             => IOP_IOCTL_CLK,                                 -- I/O Clock.
+            IOCTL_WR              => IOP_IOCTL_WR,                                  -- Write Enable to FPGA.
+            IOCTL_RD              => IOP_IOCTL_RD,                                  -- Read Enable from FPGA.
+            IOCTL_SENSE           => IOP_IOCTL_SENSE,                               -- Sense to see if HPS accessing ioctl bus.
+            IOCTL_SELECT          => IOP_IOCTL_SELECT,                              -- Enable IOP control over ioctl bus.
+            IOCTL_ADDR            => IOP_IOCTL_ADDR,                                -- Address in FPGA to write into.
+            IOCTL_DOUT            => IOP_IOCTL_DOUT,                                -- Data to be written into FPGA.
+            IOCTL_DIN             => IOP_IOCTL_DIN                                  -- Data to be read into HPS.
+
+--          -- SDRAM Interface --
+--          SDRAM_CLK_O           => open,
+--          SDRAM_CSN_O           => open,
+--          SDRAM_CKE_O           => open,
+--          SDRAM_RASN_O          => open,
+--          SDRAM_CASN_O          => open,
+--          SDRAM_WEN_O           => open,
+--          SDRAM_DQM_O           => open,
+--          SDRAM_BA_O            => open,
+--          SDRAM_ADR_O           => open,
+--          SDRAM_DAT_IO          => open
+        );
+    end generate;
+
+    -- If enabled, instantiate the local IO processor to provide IO and user interface services.
+    --
+    NEO430_ENABLED: if NEO_ENABLE = 1 generate
+      NEO430_0 : neo430
+        generic map (
+            -- general configuration --
+            CLOCK_SPEED           => 64000000,                                      -- main clock in Hz
+            IMEM_SIZE             => 48*1024,                                       -- internal IMEM size in bytes, max 48kB (default=4kB)
+            DMEM_SIZE             => 12*1024,                                       -- internal DMEM size in bytes, max 12kB (default=2kB)
+            -- additional configuration --
+            USER_CODE             => x"0000",                                       -- custom user code
+            -- module configuration --
+            DADD_USE              => true,                                          -- implement DADD instruction? (default=true)
+            MULDIV_USE            => true,                                          -- implement multiplier/divider unit? (default=true)
+            WB32_USE              => false,                                         -- implement WB32 unit? (default=true)
+            WDT_USE               => true,                                          -- implement WDT? (default=true)
+            GPIO_USE              => true,                                          -- implement GPIO unit? (default=true)
+            TIMER_USE             => true,                                          -- implement timer? (default=true)
+            UART_USE              => true,                                          -- implement UART? (default=true)
+            CRC_USE               => false,                                         -- implement CRC unit? (default=true)
+            CFU_USE               => false,                                         -- implement custom functions unit? (default=false)
+            PWM_USE               => true,                                          -- implement PWM controller?
+            TWI_USE               => false,                                         -- implement two wire serial interface? (default=true)
+            SPI_USE               => true,                                          -- implement SPI? (default=true)
+            -- boot configuration --
+            BOOTLD_USE            => true,                                          -- implement and use bootloader? (default=true)
+            IMEM_AS_ROM           => false                                          -- implement IMEM as read-only memory? (default=false)
+        )
+        port map (
+            -- global control --
+            clk_i                 => CON_CLKIOP,                                    -- global clock, rising edge
+            rst_i                 => not (CON_COLD_RESET or CON_WARM_RESET),        -- global reset, async
+            -- gpio --
+            gpio_o                => open,                                          -- parallel output
+            gpio_i                => X"0000",                                       -- parallel input
+            -- pwm channels --
+            pwm_o                 => open,                                          -- pwm channels
+            -- serial com --
+            uart_txd_o            => CON_UART_TX,                                   -- UART send data
+            uart_rxd_i            => CON_UART_RX,                                   -- UART receive data
+            spi_sclk_o            => CON_SPI_SCLK,                                  -- serial clock line
+            spi_mosi_o            => CON_SPI_MOSI,                                  -- serial data line out
+            spi_miso_i            => CON_SPI_MISO,                                  -- serial data line in
+            spi_cs_o              => CON_SPI_CS,                                    -- SPI CS 0..7
+            twi_sda_io            => open,                                          -- twi serial data line
+            twi_scl_io            => open,                                          -- twi serial clock line
+            -- IOCTL Bus --
+            ioctl_download        => IOP_IOCTL_DOWNLOAD,                            -- Downloading to FPGA.
+            ioctl_upload          => IOP_IOCTL_UPLOAD,                              -- Uploading from FPGA.
+            ioctl_clk             => IOP_IOCTL_CLK,                                 -- I/O Clock.
+            ioctl_wr              => IOP_IOCTL_WR,                                  -- Write Enable to FPGA.
+            ioctl_rd              => IOP_IOCTL_RD,                                  -- Read Enable from FPGA.
+            ioctl_sense           => IOP_IOCTL_SENSE,                               -- Sense to see if HPS accessing ioctl bus.
+            ioctl_select          => IOP_IOCTL_SELECT,                              -- Enable CFU control over ioctl bus.
+            ioctl_addr            => IOP_IOCTL_ADDR,                                -- Address in FPGA to write into.
+            ioctl_dout            => IOP_IOCTL_DOUT,                                -- Data to be written into FPGA.
+            ioctl_din             => IOP_IOCTL_DIN,                                 -- Data to be read into HPS.
+            -- 32-bit wishbone interface --
+            wb_adr_o              => open,                                          -- address
+            wb_dat_i              => (others => '0'),                               -- read data
+            wb_dat_o              => open,                                          -- write data
+            wb_we_o               => open,                                          -- read/write
+            wb_sel_o              => open,                                          -- byte enable
+            wb_stb_o              => open,                                          -- strobe
+            wb_cyc_o              => open,                                          -- valid cycle
+            wb_ack_i              => '0',                                           -- transfer acknowledge
+            -- interrupts --
+            irq_i                 => '0',                                           -- external interrupt request line
+            irq_ack_o             => open                                           -- external interrupt request acknowledge
+        );
+    end generate;
+
+    -- If the IO Processor is disabled, set the signals to inactive.
+    --
+    IOP_DISABLED: if NEO_ENABLE = 0 and STORM_ENABLE = 0 generate
+        IOP_IOCTL_DOWNLOAD        <= '0';
+        IOP_IOCTL_UPLOAD          <= '0';
+        IOP_IOCTL_CLK             <= '0';
+        IOP_IOCTL_WR              <= '0';
+        IOP_IOCTL_RD              <= '0';
+        IOP_IOCTL_ADDR            <= (others => '0');
+        IOP_IOCTL_DOUT            <= (others => '0');
+        --IOP_IOCTL_DIN           => open;
+        --IOP_IOCTL_SENSE         => open;
+        IOP_IOCTL_SELECT          <= '0';
+    end generate;
+
+    -- Assign signals from the emu onto local wires.
+    --
+    CON_CLKMASTER                 <= clkmaster; 
+    clksys                        <= CON_CLKSYS;
+    clkvid                        <= CON_CLKVID;
+    CON_COLD_RESET                <= cold_reset; 
+    CON_WARM_RESET                <= warm_reset; 
+    main_leds                     <= CON_MAIN_LEDS;
+    CON_PS2_KEY                   <= ps2_key; 
+    vga_hb_o                      <= CON_VGA_HB_O;
+    vga_vb_o                      <= CON_VGA_VB_O;
+    vga_hs_o                      <= CON_VGA_HS_O;
+    vga_vs_o                      <= CON_VGA_VS_O;
+    vga_r_o                       <= CON_VGA_R_O;
+    vga_g_o                       <= CON_VGA_G_O;
+    vga_b_o                       <= CON_VGA_B_O;
+    audio_l_o                     <= CON_AUDIO_L_O;
+    audio_r_o                     <= CON_AUDIO_R_O;
+
+    uart_tx                       <= CON_UART_TX;
+    CON_UART_RX                   <= uart_rx;
+    sd_sck                        <= CON_SPI_SCLK;
+    sd_mosi                       <= CON_SPI_MOSI;
+    CON_SPI_MISO                  <= sd_miso;
+    sd_cs                         <= CON_SPI_CS(0);
+    --
+    -- Multiplexer, default IO control to the HPS unless the IOP is enabled and selects. 
+    -- The IOP first senses to ensure there is no activity on the bus, then takes control
+    --
+    CON_IOCTL_DOWNLOAD            <= ioctl_download              when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     IOP_IOCTL_DOWNLOAD; 
+    CON_IOCTL_UPLOAD              <= ioctl_upload                when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     IOP_IOCTL_UPLOAD; 
+    CON_IOCTL_CLK                 <= ioctl_clk                   when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     IOP_IOCTL_CLK; 
+    CON_IOCTL_WR                  <= ioctl_wr                    when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     IOP_IOCTL_WR; 
+    CON_IOCTL_RD                  <= ioctl_rd                    when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     IOP_IOCTL_RD; 
+    CON_IOCTL_ADDR                <= ioctl_addr                  when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     IOP_IOCTL_ADDR; 
+    CON_IOCTL_DOUT                <= X"0000" & ioctl_dout        when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     IOP_IOCTL_DOUT; 
+    ioctl_din                     <= CON_IOCTL_DIN(15 downto 0)  when IOP_IOCTL_SELECT = '0'
+                                     else
+                                     (others => '0');
+    IOP_IOCTL_DIN                 <= CON_IOCTL_DIN               when IOP_IOCTL_SELECT = '1'
+                                     else
+                                     (others => '0');
+    IOP_IOCTL_SENSE               <= ioctl_download or ioctl_upload or ioctl_wr or ioctl_rd;
+
+end rtl;
diff --git a/build_id.v b/build_id.v
new file mode 100644
index 0000000..0759dda
--- /dev/null
+++ b/build_id.v
@@ -0,0 +1,2 @@
+`define BUILD_DATE "190107"
+`define BUILD_TIME "222840"
diff --git a/c5_pin_model_dump.txt b/c5_pin_model_dump.txt
new file mode 100644
index 0000000..31bb72c
--- /dev/null
+++ b/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/clean.bat b/clean.bat
new file mode 100644
index 0000000..7ac8e34
--- /dev/null
+++ b/clean.bat
@@ -0,0 +1,38 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del *.cdf
+del *.rpt
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+pause
diff --git a/clean.sh b/clean.sh
new file mode 100644
index 0000000..8ebda37
--- /dev/null
+++ b/clean.sh
@@ -0,0 +1,37 @@
+#!/bin/bash -x
+
+rm -f *.bak
+rm -f *.orig
+rm -f *.rej
+rm -f *~
+rm -fr db
+rm -fr incremental_db
+rm -fr output_files
+rm -fr simulation
+rm -fr greybox_tmp
+rm -fr hc_output
+rm -fr .qsys_edit
+rm -fr hps_isw_handoff
+rm -fr sys\.qsys_edit
+rm -fr sys\vip
+#rm build_id.v
+rm -f c5_pin_model_dump.txt
+rm -f PLLJ_PLLSPE_INFO.txt
+rm -f *.qws
+rm -f *.ppf
+rm -f *.ddb
+rm -f *.csv
+rm -f *.cmp
+rm -f *.sip
+rm -f *.spd
+rm -f *.bsf
+rm -f *.f
+rm -f *.sopcinfo
+rm -f *.xml
+rm -f *.cdf
+rm -f *.rpt
+rm -f new_rtl_netlist
+rm -f old_rtl_netlist
+rm -f asm/*.obj
+rm -f asm/*.sym
+(cd ../Main_MiSTer; make clean)
diff --git a/common/.qsys_edit/filters.xml b/common/.qsys_edit/filters.xml
new file mode 100644
index 0000000..21d8ce6
--- /dev/null
+++ b/common/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="17.1" />
diff --git a/common/.qsys_edit/pll.xml b/common/.qsys_edit/pll.xml
new file mode 100644
index 0000000..8f69dab
--- /dev/null
+++ b/common/.qsys_edit/pll.xml
@@ -0,0 +1,2440 @@
+<?xml version='1.0'?>
+<root>
+	<resource name="dock.ui.ThemeMap">
+		<key>eclipse</key>
+	</resource>
+	<resource name="ccontrol.frontend">
+		<frontend>
+			<settings>
+				<setting name="main">
+					<base>
+						<roots>
+							<root name="external">
+								<layout factory="predefined">
+									<replacement id="rootexternal"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>external</id>
+										<root>true</root>
+										<content delegate="screen dock">
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CExternalizeArea</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol north">
+								<layout factory="predefined">
+									<replacement id="rootccontrol north"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol north</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol south">
+								<layout factory="predefined">
+									<replacement id="rootccontrol south"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol south</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol east">
+								<layout factory="predefined">
+									<replacement id="rootccontrol east"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol east</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol center">
+								<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+									<replacement id="rootccontrol center"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol center</id>
+										<root>true</root>
+										<content delegate="SplitDockStationFactory">
+											<fullscreen-action>false</fullscreen-action>
+											<node nodeId="-1" orientation="HORIZONTAL" divider="0.2">
+												<leaf id="0" nodeId="-1"/>
+												<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+													<node nodeId="-1" orientation="HORIZONTAL" divider="0.75">
+														<node nodeId="-1" orientation="HORIZONTAL" divider="0.3333333333333333">
+															<leaf id="1" nodeId="-1"/>
+															<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+																<leaf id="2" nodeId="-1"/>
+																<leaf id="3" nodeId="-1"/>
+															</node>
+														</node>
+														<node nodeId="-1" orientation="VERTICAL" divider="0.5">
+															<leaf id="4" nodeId="-1"/>
+															<leaf id="5" nodeId="-1"/>
+														</node>
+													</node>
+													<leaf id="6" nodeId="-1"/>
+												</node>
+											</node>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.center</type>
+									</layout>
+								</adjacent>
+								<children ignore="false">
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+													<replacement id="dockablesingle IP Catalog"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>IP\ Catalog</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Hierarchy">
+													<replacement id="dockablesingle Hierarchy"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Hierarchy</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.System\ Contents</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Address\ Map</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instrumentation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">2</item>
+													<item key="dock.index" type="i">2</item>
+													<item key="dock.placeholder" type="s">dock.single.Instrumentation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Clock\ Settings</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">3</item>
+													<item key="dock.index" type="i">3</item>
+													<item key="dock.placeholder" type="s">dock.single.Clock\ Settings</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instance\ Parameters</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">4</item>
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+													<item key="dock.placeholder" type="s">dock.single.Instance\ Parameters</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.HDL\ Example</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
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+													<item key="dock.index" type="i">6</item>
+													<item key="dock.placeholder" type="s">dock.single.HDL\ Example</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Generation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">7</item>
+													<item key="dock.index" type="i">7</item>
+													<item key="dock.placeholder" type="s">dock.single.Generation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Connections</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">8</item>
+													<item key="dock.index" type="i">8</item>
+													<item key="dock.placeholder" type="s">dock.single.Connections</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Domains</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">10</item>
+													<item key="dock.index" type="i">10</item>
+													<item key="dock.placeholder" type="s">dock.single.Domains</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.System\ Contents">
+													<replacement id="dockablesingle System Contents"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>System Contents</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Address\ Map">
+													<replacement id="dockablesingle Address Map"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Address Map</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instrumentation">
+													<replacement id="dockablesingle Instrumentation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instrumentation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Clock\ Settings">
+													<replacement id="dockablesingle Clock Settings"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Clock Settings</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+													<replacement id="dockablesingle Instance Parameters"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instance Parameters</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.HDL\ Example">
+													<replacement id="dockablesingle HDL Example"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>HDL Example</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Generation">
+													<replacement id="dockablesingle Generation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Generation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Connections">
+													<replacement id="dockablesingle Connections"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Connections</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Domains">
+													<replacement id="dockablesingle Domains"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Domains</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Parameter\ Editor</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Parameter\ Editor</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Parameter\ Editor">
+													<replacement id="dockablesingle Parameter Editor"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Parameter Editor</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Block\ Symbol</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
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+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Block\ Symbol</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Element\ Docs</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Element\ Docs</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+													<replacement id="dockablesingle Block Symbol"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Block Symbol</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Element\ Docs">
+													<replacement id="dockablesingle Element Docs"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Element Docs</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Presets</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Presets</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Presets">
+													<replacement id="dockablesingle Presets"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Presets</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Messages</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Messages</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Messages">
+													<replacement id="dockablesingle Messages"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Messages</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+								</children>
+							</root>
+							<root name="ccontrol west">
+								<layout factory="predefined">
+									<replacement id="rootccontrol west"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol west</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+						</roots>
+						<children/>
+					</base>
+					<modes>
+						<dockables>
+							<entry id="single ccontrol center">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single IP Catalog">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Hierarchy">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single System Contents">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Address Map">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instrumentation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Clock Settings">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instance Parameters">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single HDL Example">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Generation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Connections">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Domains">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Parameter Editor">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Block Symbol">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Element Docs">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Presets">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Messages">
+								<history/>
+								<properties/>
+							</entry>
+						</dockables>
+						<modes/>
+					</modes>
+				</setting>
+			</settings>
+			<current name="main">
+				<base>
+					<roots>
+						<root name="external">
+							<layout factory="predefined">
+								<replacement id="rootexternal"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="screen dock">
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Parameters</placeholder>
+												</key>
+												<item key="item" type="b">true</item>
+												<item key="item-keys" type="a">
+													<item type="s">x</item>
+													<item type="s">width</item>
+													<item type="s">y</item>
+													<item type="s">height</item>
+												</item>
+												<item key="item.x" type="i">6108</item>
+												<item key="item.width" type="i">400</item>
+												<item key="item.y" type="i">410</item>
+												<item key="item.height" type="i">1004</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.System\ Contents</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Address\ Map</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+														</key>
+													</entry>
+												</item>
+												<item key="item" type="b">true</item>
+												<item key="item-keys" type="a">
+													<item type="s">x</item>
+													<item type="s">width</item>
+													<item type="s">y</item>
+													<item type="s">height</item>
+												</item>
+												<item key="item.x" type="i">4726</item>
+												<item key="item.width" type="i">1773</item>
+												<item key="item.y" type="i">350</item>
+												<item key="item.height" type="i">742</item>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CExternalizeArea</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol north">
+							<layout factory="predefined">
+								<replacement id="rootccontrol north"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="SOUTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.IP\ Catalog</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.System\ Contents</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Address\ Map</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
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+						<root name="ccontrol south">
+							<layout factory="predefined">
+								<replacement id="rootccontrol south"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="NORTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol east">
+							<layout factory="predefined">
+								<replacement id="rootccontrol east"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="WEST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Parameters</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">size</item>
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+													<item type="s">hold</item>
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+												<item key="dock.size" type="i">488</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.Parameters</item>
+												<item key="dock.hold" type="b">true</item>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Parameters">
+										<replacement id="dockablesingle Parameters"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Parameters</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol center">
+							<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+								<replacement id="rootccontrol center"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<id>ccontrol center</id>
+									<root>true</root>
+									<content delegate="SplitDockStationFactory">
+										<fullscreen-action>false</fullscreen-action>
+										<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.1889799635701275">
+											<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
+												<leaf id="0" nodeId="1375985003630">
+													<placeholders>
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+														<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.IP\ Catalog</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+												<leaf id="1" nodeId="1375985011087">
+													<placeholders>
+														<placeholder>dock.single.Hierarchy</placeholder>
+														<placeholder>dock.single.Device\ Family</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Hierarchy</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Device\ Family</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+											<node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+												<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6150921451885029">
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+																<placeholders>
+																	<placeholder>dock.single.Connections</placeholder>
+																	<placeholder>dock.single.System\ Contents</placeholder>
+																	<placeholder>dock.single.Assignments</placeholder>
+																	<placeholder>dock.single.Schematic</placeholder>
+																	<placeholder>dock.single.Clocks</placeholder>
+																	<placeholder>dock.single.Interface\ Requirements\ \-\ Alpha</placeholder>
+																	<placeholder>dock.single.Generation</placeholder>
+																	<placeholder>dock.single.Clock\ Settings</placeholder>
+																	<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																	<placeholder>dock.single.HDL\ Example</placeholder>
+																	<placeholder>dock.single.Clock\ Domains</placeholder>
+																	<placeholder>dock.single.Interface\ Requirements</placeholder>
+																	<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																	<placeholder>dock.single.Instrumentation</placeholder>
+																	<placeholder>dock.single.Instance\ Parameters</placeholder>
+																	<placeholder>dock.single.Address\ Map</placeholder>
+																	<placeholder>dock.single.Domains</placeholder>
+																</placeholders>
+																<placeholder-map>
+																	<version>0</version>
+																	<format>dock.PlaceholderList</format>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.System\ Contents</placeholder>
+																		</key>
+																		<item key="convert" type="b">true</item>
+																		<item key="convert-keys" type="a"/>
+																	</entry>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.Address\ Map</placeholder>
+																		</key>
+																		<item key="convert" type="b">true</item>
+																		<item key="convert-keys" type="a"/>
+																	</entry>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.Assignments</placeholder>
+																		</key>
+																	</entry>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.Connections</placeholder>
+																		</key>
+																	</entry>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.Instance\ Parameters</placeholder>
+																		</key>
+																	</entry>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																		</key>
+																	</entry>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.Schematic</placeholder>
+																		</key>
+																	</entry>
+																	<entry>
+																		<key shared="false">
+																			<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																		</key>
+																		<item key="convert" type="b">true</item>
+																		<item key="convert-keys" type="a"/>
+																	</entry>
+																</placeholder-map>
+															</leaf>
+															<leaf id="-1" nodeId="1544275870043">
+																<placeholders>
+																	<placeholder>dock.single.Parameters</placeholder>
+																</placeholders>
+															</leaf>
+														</node>
+														<leaf id="-1" nodeId="1372710005737">
+															<placeholders>
+																<placeholder>dock.single.Parameter\ Editor</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+													<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
+														<leaf id="-1" nodeId="1389812800464">
+															<placeholders>
+																<placeholder>dock.single.Details</placeholder>
+																<placeholder>dock.single.Block\ Symbol</placeholder>
+																<placeholder>dock.single.Presets</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Block\ Symbol</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Details</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Presets</placeholder>
+																	</key>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005741">
+															<placeholders>
+																<placeholder>dock.single.Element\ Docs</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+												</node>
+												<leaf id="-1" nodeId="1372710005745">
+													<placeholders>
+														<placeholder>dock.single.Messages</placeholder>
+														<placeholder>dock.single.Generation\ Messages</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Messages</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Generation\ Messages</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+										</node>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.center</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Clock\ Domains\ \-\ Beta</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+												<replacement id="dockablesingle IP Catalog"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>IP Catalog</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Clock\ Domains\ \-\ Beta">
+												<replacement id="dockablesingle Clock Domains"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Clock Domains - Beta</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Hierarchy">
+										<replacement id="dockablesingle Hierarchy"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Hierarchy</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Assignments</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Connections</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instance\ Parameters</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Schematic</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">2</item>
+												<item key="dock.id" type="i">2</item>
+												<item key="dock.placeholder" type="s">dock.single.Interconnect\ Requirements</item>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.System\ Contents">
+												<replacement id="dockablesingle System Contents"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>System Contents</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Address\ Map">
+												<replacement id="dockablesingle Address Map"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Address Map</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Interconnect\ Requirements">
+												<replacement id="dockablesingle Interconnect Requirements"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Interconnect Requirements</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol west">
+							<layout factory="predefined">
+								<replacement id="rootccontrol west"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="WEST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+					</roots>
+					<children>
+						<child key="single Details" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Details</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38490785481149714" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
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+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Details">
+									<replacement id="dockablesingle Details"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Details</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Assignments" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Assignments</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
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+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Assignments</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Assignments">
+									<replacement id="dockablesingle Assignments"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Assignments</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Schematic" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Schematic</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6150921451885029" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<node location="LEFT" size="0.6571107363687464" id="1542445668024"/>
+										<leaf id="1372710005735"/>
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+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>2</index>
+									<placeholder>dock.single.Schematic</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Schematic">
+									<replacement id="dockablesingle Schematic"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Schematic</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Messages">
+									<replacement id="dockablesingle Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Presets" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Presets</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Presets</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Presets">
+									<replacement id="dockablesingle Presets"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Presets</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Device Family" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Device\ Family</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.1889799635701275" id="1372710005721"/>
+										<node location="BOTTOM" size="0.495945945945946" id="1375985011088"/>
+										<leaf id="1375985011087"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Device\ Family</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Device\ Family">
+									<replacement id="dockablesingle Device Family"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Device Family</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Generation Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Generation\ Messages">
+									<replacement id="dockablesingle Generation Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Generation Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Connections" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Connections</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>4</index>
+									<placeholder>dock.single.Connections</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Connections">
+									<replacement id="dockablesingle Connections"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Connections</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instance Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6150921451885029" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<node location="LEFT" size="0.6571107363687464" id="1542445668024"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>2</index>
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+									<replacement id="dockablesingle Instance Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instance Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instrumentation - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>6</index>
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instrumentation\ \-\ Beta">
+									<replacement id="dockablesingle Instrumentation - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instrumentation - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Block Symbol" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Block\ Symbol</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+									<replacement id="dockablesingle Block Symbol"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Block Symbol</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Reset Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Reset\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Reset Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Reset Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+					</children>
+				</base>
+				<modes>
+					<dockables>
+						<entry id="single Details">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Details</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Details</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Parameters" current="dock.mode.minimized">
+							<history>
+								<mode>dock.mode.externalized</mode>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.normal</mode>
+								<mode>dock.mode.minimized</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol east</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>true</holding>
+											<size>488</size>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.externalized">
+									<mode>dock.mode.externalized</mode>
+									<root>external</root>
+									<location>
+										<property factory="screen dock">
+											<x>6108</x>
+											<y>410</y>
+											<width>400</width>
+											<height>1004</height>
+											<fullscreen>false</fullscreen>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6150921451885029" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="RIGHT" size="0.3097345132743363" id="1544275870044"/>
+												<leaf id="1544275870043"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Assignments">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Assignments</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="TOP" size="0.6682769726247987" id="1411773509398"/>
+												<leaf id="1411773473878"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Address Map" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.externalized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.externalized">
+									<mode>dock.mode.externalized</mode>
+									<root>external</root>
+									<location>
+										<property factory="screen dock">
+											<x>4726</x>
+											<y>350</y>
+											<width>1773</width>
+											<height>742</height>
+											<fullscreen>false</fullscreen>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Address\ Map</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6150921451885029" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="LEFT" size="0.6571107363687464" id="1542445668024"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Schematic">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Schematic</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Schematic</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Presets">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Presets</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="BOTTOM" size="0.5" id="1372710005739"/>
+												<leaf id="1372710005743"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Messages</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="BOTTOM" size="0.25" id="1372710005725"/>
+												<leaf id="1372710005745"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Device Family">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Device\ Family</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="BOTTOM" size="0.3317230273752013" id="1411773509398"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Device\ Family</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Clock Domains - Beta" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Generation Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Generation\ Messages</placeholder>
+											<backup-path>
+												<node location="TOP" size="0.5" id="1411773534479"/>
+												<leaf id="1411773534477"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Connections">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Connections</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>5</index>
+											<placeholder>dock.single.Connections</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single System Contents" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.externalized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.externalized">
+									<mode>dock.mode.externalized</mode>
+									<root>external</root>
+									<location>
+										<property factory="screen dock">
+											<x>4726</x>
+											<y>350</y>
+											<width>1773</width>
+											<height>742</height>
+											<fullscreen>false</fullscreen>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.System\ Contents</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6150921451885029" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="LEFT" size="0.6571107363687464" id="1542445668024"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Interconnect Requirements" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.externalized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.externalized">
+									<mode>dock.mode.externalized</mode>
+									<root>external</root>
+									<location>
+										<property factory="screen dock">
+											<x>4726</x>
+											<y>350</y>
+											<width>1773</width>
+											<height>742</height>
+											<fullscreen>false</fullscreen>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8110200364298725" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6150921451885029" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="LEFT" size="0.6571107363687464" id="1542445668024"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instrumentation - Beta">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instance Parameters">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single IP Catalog" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Hierarchy" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Hierarchy</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Hierarchy</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.2" id="1372710005721"/>
+												<node location="BOTTOM" size="0.2928870292887029" id="1375985011088"/>
+												<leaf id="1375985011087"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Block Symbol">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Reset Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+					</dockables>
+					<modes>
+						<entry id="dock.mode.maximized"/>
+					</modes>
+				</modes>
+			</current>
+		</frontend>
+	</resource>
+	<resource name="ccontrol.preferences"/>
+</root>
\ No newline at end of file
diff --git a/common/.qsys_edit/pll_schematic.nlv b/common/.qsys_edit/pll_schematic.nlv
new file mode 100644
index 0000000..00a6893
--- /dev/null
+++ b/common/.qsys_edit/pll_schematic.nlv
@@ -0,0 +1,34 @@
+# # File gsaved with Nlview version 6.3.8  2013-12-19 bk=1.2992 VDI=34 GEI=35
+# 
+preplace inst pll.pll_0 -pg 1 -lvl 2 -y 170
+preplace inst pll.pll_1 -pg 1 -lvl 3 -y 170
+preplace inst pll.pll_2 -pg 1 -lvl 2 -y 370
+preplace inst pll.clk_0 -pg 1 -lvl 1 -y 260
+preplace inst pll -pg 1 -lvl 1 -y 40 -regy -20
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_2_outclk3,(MASTER)pll_2.outclk3) 1 2 2 NJ 440 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_0_outclk4,(MASTER)pll_0.outclk4) 1 2 2 NJ 120 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.pll_2_refclk,(SLAVE)pll_2.refclk) 1 0 2 NJ 400 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll_1.reset,(SLAVE)pll.pll_1_reset) 1 0 3 NJ 250 NJ 360 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk2,(MASTER)pll.pll_0_outclk2) 1 2 2 NJ 80 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_2_outclk2,(MASTER)pll_2.outclk2) 1 2 2 NJ 420 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk6,(MASTER)pll.pll_0_outclk6) 1 2 2 NJ 160 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk5,(MASTER)pll.pll_0_outclk5) 1 2 2 NJ 140 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll_1.refclk,(SLAVE)pll.pll_1_refclk) 1 0 3 NJ 160 NJ 160 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk1,(MASTER)pll.pll_1_outclk1) 1 3 1 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)clk_0.clk_in,(SLAVE)pll.clk) 1 0 1 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_2.outclk1,(MASTER)pll.pll_2_outclk1) 1 2 2 NJ 400 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_1_outclk2,(MASTER)pll_1.outclk2) 1 3 1 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_0_outclk3,(MASTER)pll_0.outclk3) 1 2 2 NJ 100 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk3,(MASTER)pll.pll_1_outclk3) 1 3 1 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_2.outclk4,(MASTER)pll.pll_2_outclk4) 1 2 2 NJ 460 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll.pll_0_outclk1,(MASTER)pll_0.outclk1) 1 2 2 NJ 60 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_0.outclk0,(MASTER)pll.pll_0_outclk0) 1 2 2 NJ 40 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk4,(MASTER)pll.pll_1_outclk4) 1 3 1 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_2.outclk0,(MASTER)pll.pll_2_outclk0) 1 2 2 NJ 380 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll_0.refclk,(SLAVE)pll.pll_0_refclk) 1 0 2 NJ 210 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.pll_2_reset,(SLAVE)pll_2.reset) 1 0 2 NJ 420 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(MASTER)pll_1.outclk0,(MASTER)pll.pll_1_outclk0) 1 3 1 NJ
+preplace netloc EXPORT<net_container>pll</net_container>(SLAVE)pll.pll_0_reset,(SLAVE)pll_0.reset) 1 0 2 NJ 230 NJ
+levelinfo -pg 1 0 90 970
+levelinfo -hier pll 100 130 370 730 860
diff --git a/common/.qsys_edit/preferences.xml b/common/.qsys_edit/preferences.xml
new file mode 100644
index 0000000..683d967
--- /dev/null
+++ b/common/.qsys_edit/preferences.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="319" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Library,Project" />
+ <window width="1988" height="1246" x="4127" y="162" />
+ <generation synthesis="VHDL" path="pll" />
+</preferences>
diff --git a/common/T80/T80.vhd b/common/T80/T80.vhd
new file mode 100644
index 0000000..0912e3d
--- /dev/null
+++ b/common/T80/T80.vhd
@@ -0,0 +1,1094 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+	signal XYbit_undoc          : std_logic;
+
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			XY_State    => XY_State,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write,
+			XYbit_undoc => XYbit_undoc);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+				if XYbit_undoc='1' then
+					DO <= ALU_Q;
+				end if;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			if XYbit_undoc='1' then
+				BusA <= DI_Reg;
+				BusB <= DI_Reg;
+			end if;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/common/T80/T8080se.vhd b/common/T80/T8080se.vhd
new file mode 100644
index 0000000..b18b47a
--- /dev/null
+++ b/common/T80/T8080se.vhd
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT                     : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/common/T80/T80_ALU.vhd b/common/T80/T80_ALU.vhd
new file mode 100644
index 0000000..95c98da
--- /dev/null
+++ b/common/T80/T80_ALU.vhd
@@ -0,0 +1,371 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
+	process (Carry_v, Carry7_v, Q_v)
+	begin
+		if(Mode=2) then
+			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
+			OverFlow_v <= Carry_v xor Carry7_v;
+		end if;
+	end process;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/common/T80/T80_MCode.vhd b/common/T80/T80_MCode.vhd
new file mode 100644
index 0000000..1d40210
--- /dev/null
+++ b/common/T80/T80_MCode.vhd
@@ -0,0 +1,2029 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		XY_State                : in std_logic_vector(1 downto 0);
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic;
+		XYbit_undoc             : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+--	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_state)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+		XYbit_undoc <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  ALU_Op <= "1000";
+					  Read_To_Reg <= '1';
+					  Save_ALU <= '1';
+					end if;
+				else
+				-- R/S (IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1000";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+
+
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+					  ALU_Op <= "1001";
+					end if;
+				else
+				-- BIT b,(IX+d), undocumented
+					MCycles <= "010";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1001";
+						TStates <= "100";
+					when others => null;
+					end case;
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  ALU_Op <= "1010";
+					  Read_To_Reg <= '1';
+					  Save_ALU <= '1';
+					end if;
+				else
+				-- SET b,(IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1010";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  ALU_Op <= "1011";
+					  Read_To_Reg <= '1';
+					  Save_ALU <= '1';
+					end if;
+				else
+				-- RES b,(IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1011";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+				
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/common/T80/T80_Pack.vhd b/common/T80/T80_Pack.vhd
new file mode 100644
index 0000000..6904b66
--- /dev/null
+++ b/common/T80/T80_Pack.vhd
@@ -0,0 +1,220 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		XY_State                : in  std_logic_vector(1 downto 0);
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic;
+		XYbit_undoc             : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/common/T80/T80_Reg.vhd b/common/T80/T80_Reg.vhd
new file mode 100644
index 0000000..1c0f263
--- /dev/null
+++ b/common/T80/T80_Reg.vhd
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/common/T80/T80_RegX.vhd b/common/T80/T80_RegX.vhd
new file mode 100644
index 0000000..ebeee09
--- /dev/null
+++ b/common/T80/T80_RegX.vhd
@@ -0,0 +1,176 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers for Xilinx Select RAM
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Removed UNISIM library and added componet declaration
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	component RAM16X1D
+		port(
+			DPO         : out std_ulogic;
+			SPO         : out std_ulogic;
+			A0          : in std_ulogic;
+			A1          : in std_ulogic;
+			A2          : in std_ulogic;
+			A3          : in std_ulogic;
+			D           : in std_ulogic;
+			DPRA0       : in std_ulogic;
+			DPRA1       : in std_ulogic;
+			DPRA2       : in std_ulogic;
+			DPRA3       : in std_ulogic;
+			WCLK        : in std_ulogic;
+			WE          : in std_ulogic);
+	end component;
+
+	signal      ENH             : std_logic;
+	signal      ENL             : std_logic;
+
+begin
+
+	ENH <= CEN and WEH;
+	ENL <= CEN and WEL;
+
+	bG1: for I in 0 to 7 generate
+	begin
+		Reg1H : RAM16X1D
+			port map(
+			DPO => DOBH(i),
+			SPO => DOAH(i),
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIH(i),
+			DPRA0 => AddrB(0),
+			DPRA1 => AddrB(1),
+			DPRA2 => AddrB(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENH);
+		Reg1L : RAM16X1D
+			port map(
+			DPO => DOBL(i),
+			SPO => DOAL(i),
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIL(i),
+			DPRA0 => AddrB(0),
+			DPRA1 => AddrB(1),
+			DPRA2 => AddrB(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENL);
+		Reg2H : RAM16X1D
+			port map(
+			DPO => DOCH(i),
+			SPO => open,
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIH(i),
+			DPRA0 => AddrC(0),
+			DPRA1 => AddrC(1),
+			DPRA2 => AddrC(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENH);
+		Reg2L : RAM16X1D
+			port map(
+			DPO => DOCL(i),
+			SPO => open,
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIL(i),
+			DPRA0 => AddrC(0),
+			DPRA1 => AddrC(1),
+			DPRA2 => AddrC(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENL);
+	end generate;
+
+end;
diff --git a/common/T80/T80a.vhd b/common/T80/T80a.vhd
new file mode 100644
index 0000000..75636aa
--- /dev/null
+++ b/common/T80/T80a.vhd
@@ -0,0 +1,262 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core, asynchronous top level
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed interrupt cycle
+--
+--      0235 : Updated for T80 interface change
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80a is
+	generic(
+		Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		D                       : inout std_logic_vector(7 downto 0)
+	);
+end T80a;
+
+architecture rtl of T80a is
+
+	signal CEN                  : std_logic;
+	signal Reset_s              : std_logic;
+	signal IntCycle_n   : std_logic;
+	signal IORQ                 : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal MREQ                 : std_logic;
+	signal MReq_Inhibit : std_logic;
+	signal Req_Inhibit  : std_logic;
+	signal RD                   : std_logic;
+	signal MREQ_n_i             : std_logic;
+	signal IORQ_n_i             : std_logic;
+	signal RD_n_i               : std_logic;
+	signal WR_n_i               : std_logic;
+	signal RFSH_n_i             : std_logic;
+	signal BUSAK_n_i    : std_logic;
+	signal A_i                  : std_logic_vector(15 downto 0);
+	signal DO                   : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector (7 downto 0);        -- Input synchroniser
+	signal Wait_s               : std_logic;
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+
+begin
+
+	CEN <= '1';
+
+	BUSAK_n <= BUSAK_n_i;
+	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
+	RD_n_i <= not RD or Req_Inhibit;
+
+	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
+	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
+	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
+	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
+	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
+	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
+	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			Reset_s <= '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			Reset_s <= '1';
+		end if;
+	end process;
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 1)
+		port map(
+			CEN => CEN,
+			M1_n => M1_n,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => RFSH_n_i,
+			HALT_n => HALT_n,
+			WAIT_n => Wait_s,
+			INT_n => INT_n,
+			NMI_n => NMI_n,
+			RESET_n => Reset_s,
+			BUSRQ_n => BUSRQ_n,
+			BUSAK_n => BUSAK_n_i,
+			CLK_n => CLK_n,
+			A => A_i,
+			DInst => D,
+			DI => DI_Reg,
+			DO => DO,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '0' then
+			Wait_s <= WAIT_n;
+			if TState = "011" and BUSAK_n_i = '1' then
+				DI_Reg <= to_x01(D);
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			WR_n_i <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			WR_n_i <= '1';
+			if TState = "001" then      -- To short for IO writes !!!!!!!!!!!!!!!!!!!
+				WR_n_i <= not Write;
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			Req_Inhibit <= '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if MCycle = "001" and TState = "010" then
+				Req_Inhibit <= '1';
+			else
+				Req_Inhibit <= '0';
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			MReq_Inhibit <= '0';
+		elsif CLK_n'event and CLK_n = '0' then
+			if MCycle = "001" and TState = "010" then
+				MReq_Inhibit <= '1';
+			else
+				MReq_Inhibit <= '0';
+			end if;
+		end if;
+	end process;
+
+	process(Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			RD <= '0';
+			IORQ_n_i <= '1';
+			MREQ <= '0';
+		elsif CLK_n'event and CLK_n = '0' then
+
+			if MCycle = "001" then
+				if TState = "001" then
+					RD <= IntCycle_n;
+					MREQ <= IntCycle_n;
+					IORQ_n_i <= IntCycle_n;
+				end if;
+				if TState = "011" then
+					RD <= '0';
+					IORQ_n_i <= '1';
+					MREQ <= '1';
+				end if;
+				if TState = "100" then
+					MREQ <= '0';
+				end if;
+			else
+				if TState = "001" and NoRead = '0' then
+					RD <= not Write;
+					IORQ_n_i <= not IORQ;
+					MREQ <= not IORQ;
+				end if;
+				if TState = "011" then
+					RD <= '0';
+					IORQ_n_i <= '1';
+					MREQ <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/common/T80/T80se.vhd b/common/T80/T80se.vhd
new file mode 100644
index 0000000..1b0cb9b
--- /dev/null
+++ b/common/T80/T80se.vhd
@@ -0,0 +1,192 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0240
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0235 : First release
+--
+--      0236 : Added T2Write generic
+--
+--      0237 : Fixed T2Write with wait state
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80se is
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0;  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+		IOWait : integer := 1   -- 0 => Single cycle I/O, 1 => Std I/O cycle
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CLKEN           : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0)
+	);
+end T80se;
+
+architecture rtl of T80se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead       : std_logic;
+	signal Write        : std_logic;
+	signal IORQ         : std_logic;
+	signal DI_Reg       : std_logic_vector(7 downto 0);
+	signal MCycle       : std_logic_vector(2 downto 0);
+	signal TState       : std_logic_vector(2 downto 0);
+
+begin
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => IOWait)
+		port map(
+			CEN        => CLKEN,
+			M1_n       => M1_n,
+			IORQ       => IORQ,
+			NoRead     => NoRead,
+			Write      => Write,
+			RFSH_n     => RFSH_n,
+			HALT_n     => HALT_n,
+			WAIT_n     => Wait_n,
+			INT_n      => INT_n,
+			NMI_n      => NMI_n,
+			RESET_n    => RESET_n,
+			BUSRQ_n    => BUSRQ_n,
+			BUSAK_n    => BUSAK_n,
+			CLK_n      => CLK_n,
+			A          => A,
+			DInst      => DI,
+			DI         => DI_Reg,
+			DO         => DO,
+			MC         => MCycle,
+			TS         => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			if CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and Wait_n = '0') then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					end if;
+				end if;
+				if TState = "010" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/common/T80/T80sed.vhd b/common/T80/T80sed.vhd
new file mode 100644
index 0000000..0c28ec2
--- /dev/null
+++ b/common/T80/T80sed.vhd
@@ -0,0 +1,179 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0238
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0235 : First release
+--
+--      0236 : Added T2Write generic
+--
+--      0237 : Fixed T2Write with wait state
+--
+--      0238 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80sed is
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CLKEN           : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0)
+	);
+end T80sed;
+
+architecture rtl of T80sed is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead       : std_logic;
+	signal Write        : std_logic;
+	signal IORQ         : std_logic;
+	signal DI_Reg       : std_logic_vector(7 downto 0);
+	signal MCycle       : std_logic_vector(2 downto 0);
+	signal TState       : std_logic_vector(2 downto 0);
+
+begin
+
+	u0 : T80
+		generic map(
+			Mode      => 0,
+			IOWait    => 1)
+		port map(
+			CEN        => CLKEN,
+			M1_n       => M1_n,
+			IORQ       => IORQ,
+			NoRead     => NoRead,
+			Write      => Write,
+			RFSH_n     => RFSH_n,
+			HALT_n     => HALT_n,
+			WAIT_n     => Wait_n,
+			INT_n      => INT_n,
+			NMI_n      => NMI_n,
+			RESET_n    => RESET_n,
+			BUSRQ_n    => BUSRQ_n,
+			BUSAK_n    => BUSAK_n,
+			CLK_n      => CLK_n,
+			A          => A,
+			DInst      => DI,
+			DI         => DI_Reg,
+			DO         => DO,
+			MC         => MCycle,
+			TS         => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			if CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and Wait_n = '0') then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				else
+					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+						if ((TState = "001") or (TState = "010")) and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+				end if;
+				if TState = "010" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/common/cgrom.dump b/common/cgrom.dump
new file mode 100755
index 0000000..99ff4d1
--- /dev/null
+++ b/common/cgrom.dump
@@ -0,0 +1 @@
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\ No newline at end of file
diff --git a/common/clk_div.vhd b/common/clk_div.vhd
new file mode 100644
index 0000000..ee039ba
--- /dev/null
+++ b/common/clk_div.vhd
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            clk_div.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     A basic frequency divider module.
+--                  This module takes an input frequency and divides it based on a provided divider.
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018   - Initial module written.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_div is
+    GENERIC (
+        divider : natural
+    );
+    PORT (
+        clk_in  : in  std_logic;
+        reset   : in  std_logic;
+        clk_out : out std_logic
+    );
+end clk_div;
+
+architecture Behavioral of clk_div is
+    signal temporal: std_logic;
+    signal counter : integer range 0 to divider-1 := 0;
+begin
+    process (reset, clk_in) begin
+        if (reset = '1') then
+            temporal     <= '0';
+            counter      <= 0;
+
+        elsif rising_edge(clk_in) then
+            if (counter = divider-1) then
+                temporal <= NOT(temporal);
+                counter  <= 0;
+            else
+                counter  <= counter + 1;
+            end if;
+        end if;
+    end process;
+    
+    clk_out <= temporal;
+end Behavioral;
diff --git a/common/clkgen.vhd b/common/clkgen.vhd
new file mode 100644
index 0000000..ae7eeef
--- /dev/null
+++ b/common/clkgen.vhd
@@ -0,0 +1,794 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            clkgen.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     A programmable Clock Generate module using division.
+--                  
+--                  This module is the heart of the emulator, providing all required frequencies
+--                  from a given input clock (ie. DE10 Nano 50MHz).
+--
+--                  Based on input control signals from the MCTRL block, it changes the core frequencies
+--                  according to requirements and adjusts delays (such as memory) accordingly.
+--
+--                  The module also has debugging logic to create debug frequencies (in the FPGA, static
+--                  is quite possible). The debug frequencies can range from CPU down to 1/10 Hz.
+--
+--                  Note: Generally on FPGA's you try to minimise clocks generated by division, this is
+--                  due to following:-
+--                    o The fpga may need to have the routing to bring a clock signal from a register
+--                      output into a clock net.
+--                    o Clock nets are a limited resource, some fpga's can clock flip flops off normal
+--                      nets but doing this is likely to affect timing behaviour.
+--                    o You may need to add constraints to tell the timing analyser the clock details in
+--                      order to get proper timing behaviour/analysis.
+--                    o There may be substantial phase-skew between the original clock and the generated
+--                      clock.
+--                    o To ensure the clock is clean it should come directly from a register output, not
+--                      from combinatorial logic.
+--
+--                  This module has been written with the above in mind and on the Cyclone SE it works fine.
+--                  Basically it uses Clock Enables on the Master clock to minimise skew. Only core frequencies
+--                  that cannot be clock enabled remain.
+--                  
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018   - Initial module written.
+--                  October 2018- Updated and seperated so that debug code can be removed at compile time.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+package clkgen_pkg is
+
+    -- Clock bus, various clocks on a single bus construct.
+    --
+    subtype  CLKBUS_WIDTH is integer range 8 downto 0;
+
+    -- Indexes to the various clocks on the bus.
+    --
+    constant CKMASTER               : integer := 0;
+    constant CKSOUND                : integer := 1;                      -- Sound clock.
+    constant CKRTC                  : integer := 2;                      -- RTC clock.
+    constant CKENVIDEO              : integer := 3;                      -- Video clock enable.
+    constant CKVIDEO                : integer := 4;                      -- Video clock.
+    constant CKIOP                  : integer := 5;
+    constant CKENCPU                : integer := 6;                      -- CPU clock enable.
+    constant CKENLEDS               : integer := 7;                      -- LEDS display clock enable.
+    constant CKENPERIPH             : integer := 8;                      -- Peripheral clock enable.
+end clkgen_pkg;
+
+library IEEE;
+library pkgs;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity clkgen is
+    Port (
+        RST                        : in  std_logic;                      -- Reset
+
+        -- Clocks
+        CKBASE                     : in  std_logic;                      -- Base system main clock.
+        CLKBUS                     : out std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by this module.
+
+        -- Different operations modes.
+        CONFIG                     : in  std_logic_vector(CONFIG_WIDTH);    
+
+        -- Debug modes.
+        DEBUG                      : in std_logic_vector(DEBUG_WIDTH)
+    );
+end clkgen;
+
+architecture RTL of clkgen is
+
+--
+-- Selectable output Clocks
+--
+signal PLLLOCKED1                  : std_logic;           
+signal PLLLOCKED2                  : std_logic;           
+signal PLLLOCKED3                  : std_logic;           
+signal CK448Mi                     : std_logic;                          -- 448MHz
+signal CK112Mi                     : std_logic;                          -- 112MHz
+signal CK64Mi                      : std_logic;                          -- 64MHz
+signal CK56M750i                   : std_logic;                          -- 56MHz
+signal CK32Mi                      : std_logic;                          -- 32MHz
+signal CK31M5i                     : std_logic;                          -- 31.5MHz
+signal CK28M375i                   : std_logic;                          -- 28MHz
+signal CK25M175i                   : std_logic;                          -- 25.175MHz
+signal CK17M734i                   : std_logic;                          -- 17.7MHz
+signal CK16Mi                      : std_logic;                          -- 16MHz
+signal CK14M1875i                  : std_logic;                          -- 14MHz
+signal CK8M8672i                   : std_logic;                          -- 8.8MHz
+signal CK8Mi                       : std_logic;                          -- 8MHz
+signal CK7M709i                    : std_logic;                          -- 7MHz
+signal CK4Mi                       : std_logic;                          -- 4MHz
+signal CK3M546875i                 : std_logic;                          -- 3.5MHz
+signal CK2Mi                       : std_logic;                          -- 2MHz
+signal CK1Mi                       : std_logic;                          -- 1MHz
+signal CK895Ki                     : std_logic;                          -- 895KHz Sound frequency.
+signal CK100Ki                     : std_logic;                          -- Debug frequency.
+signal CK31500i                    : std_logic;                          -- Clock base frequency,
+signal CK31250i                    : std_logic;                          -- Clock base frequency.
+signal CK15611i                    : std_logic;                          -- Clock base frequency.
+signal CK10Ki                      : std_logic;                          -- 10KHz debug CPU frequency.
+signal CK5Ki                       : std_logic;                          -- 5KHz debug CPU frequency.
+signal CK1Ki                       : std_logic;                          -- 1KHz debug CPU frequency.
+signal CK500i                      : std_logic;                          -- 500Hz debug CPU frequency.
+signal CK100i                      : std_logic;                          -- 100Hz debug CPU frequency.
+signal CK50i                       : std_logic;                          -- 50Hz debug CPU frequency.
+signal CK10i                       : std_logic;                          -- 10Hz debug CPU frequency.
+signal CK5i                        : std_logic;                          -- 5Hz debug CPU frequency.
+signal CK2i                        : std_logic;                          -- 2Hz debug CPU frequency.
+signal CK1i                        : std_logic;                          -- 1Hz debug CPU frequency.
+signal CK0_5i                      : std_logic;                          -- 0.5Hz debug CPU frequency.
+signal CK0_2i                      : std_logic;                          -- 0.2Hz debug CPU frequency.
+signal CK0_1i                      : std_logic;                          -- 0.1Hz debug CPU frequency.
+signal CKSOUNDi                    : std_logic;                          -- Sound clock 50/50 Duty cycle.
+signal CKRTCi                      : std_logic;                          -- RTC clock 50/50 Duty cycle.
+signal CKVIDEOi                    : std_logic;                          -- Video clock 50/50 Duty cycle.
+signal CKIOPi                      : std_logic;                          -- IO Processor clock.
+--
+-- Enable signals for target clocks.
+--
+signal CKENCPUi                    : std_logic;
+signal CKENLEDSi                   : std_logic;
+signal CKENVIDEOi                  : std_logic;
+signal CKENPERi                    : std_logic;
+--
+-- Clock edge detection for creating clock enables.
+--
+signal CPUEDGE                     : std_logic_vector(1 downto 0);
+signal LEDSEDGE                    : std_logic_vector(1 downto 0);
+signal VIDEOEDGE                   : std_logic_vector(1 downto 0);
+signal PEREDGE                     : std_logic_vector(1 downto 0);
+    
+--
+-- Components
+--
+component pll_pll_0 is
+    port (
+        refclk                     : in  std_logic := 'X';               -- clk
+        rst                        : in  std_logic := 'X';               -- reset
+        outclk_0                   : out std_logic;                      -- clk
+        outclk_1                   : out std_logic;                      -- clk
+        outclk_2                   : out std_logic;                      -- clk
+        outclk_3                   : out std_logic;                      -- clk
+        outclk_4                   : out std_logic;                      -- clk
+        outclk_5                   : out std_logic;                      -- clk
+        outclk_6                   : out std_logic;                      -- clk
+        outclk_7                   : out std_logic;                      -- clk
+        locked                     : out std_logic                       -- export
+    );
+end component pll_pll_0;
+
+component pll_pll_1 is
+    port (
+        refclk                     : in  std_logic := 'X';               -- clk
+        rst                        : in  std_logic := 'X';               -- reset
+        outclk_0                   : out std_logic;                      -- clk
+        outclk_1                   : out std_logic;                      -- clk
+        outclk_2                   : out std_logic;                      -- clk
+        outclk_3                   : out std_logic;                      -- clk
+        outclk_4                   : out std_logic;                      -- clk
+        locked                     : out std_logic                       -- export
+    );
+end component pll_pll_1;
+
+component pll_pll_2 is
+    port (
+        refclk                     : in  std_logic := 'X';               -- clk
+        rst                        : in  std_logic := 'X';               -- reset
+        outclk_0                   : out std_logic;                      -- clk
+        outclk_1                   : out std_logic;                      -- clk
+        outclk_2                   : out std_logic;                      -- clk
+        outclk_3                   : out std_logic;                      -- clk
+        locked                     : out std_logic                       -- export
+    );
+end component pll_pll_2;
+
+begin
+
+    PLLMAIN01 : pll_pll_0
+        port map (
+            refclk                 => CKBASE,                            -- Reference clock
+            rst                    => RST,                               -- Reset
+            outclk_0               => CK448Mi,                           -- 448MHz
+            outclk_1               => CK112Mi,                           -- 112MHz
+            outclk_2               => CK64Mi,                            -- 64MHz
+            outclk_3               => CK32Mi,                            -- 328MHz
+            outclk_4               => CK16Mi,                            -- 16MHz
+            outclk_5               => CK8Mi,                             -- 8MHz
+            outclk_6               => CK4Mi,                             -- 4MHz
+            outclk_7               => CK2Mi,                             -- 2MHz
+            locked                 => PLLLOCKED1                         -- PLL locked.
+        );
+
+    PLLMAIN02 : pll_pll_1
+        port map (
+            refclk                 => CK448Mi,                           -- Reference clock
+            rst                    => RST,                               -- Reset
+            outclk_0               => CK56M750i,                         -- 56.750MHz
+            outclk_1               => CK28M375i,                         -- 28.375MHz
+            outclk_2               => CK14M1875i,                        -- 14.1875MHz
+            outclk_3               => CK7M709i,                          -- 7.709MHz
+            outclk_4               => CK3M546875i,                       -- 3.546875MHz
+            locked                 => PLLLOCKED2                         -- PLL locked.
+        );
+
+    PLLMAIN03 : pll_pll_2
+        port map (
+            refclk                 => CK448Mi,                           -- Reference clock
+            rst                    => RST,                               -- Reset
+            outclk_0               => CK31M5i,                           -- 31.5MHz
+            outclk_1               => CK25M175i,                         -- 25.175MHz
+            outclk_2               => CK17M734i,                         -- 17.734MHz
+            outclk_3               => CK8M8672i,                         -- 8.8672MHz
+            locked                 => PLLLOCKED3                         -- PLL locked.
+        );
+
+    --
+    -- Clock Generator - Basic divide circuit for higher end frequencies.
+    --
+    process (RST, PLLLOCKED1, PLLLOCKED2, PLLLOCKED3, CK2Mi) 
+        --
+        -- Divide by counters to create the various Clock enable signals.
+        --
+        variable counter1Mi        : unsigned(0 downto 0);                -- Binary divider to create 1Mi clock.
+        variable counter895Ki      : unsigned(0 downto 0);                -- Binary divider to create 895Ki clock.
+        variable counter100Ki      : unsigned(4 downto 0);                -- Binary divider to create 100Ki clock.
+        variable counter31500i     : unsigned(5 downto 0);                -- Binary divider to create 31500i clock.
+        variable counter31250i     : unsigned(5 downto 0);                -- Binary divider to create 31250i clock.
+        variable counter15611i     : unsigned(6 downto 0);                -- Binary divider to create 15611i clock.
+        variable counter10Ki       : unsigned(7 downto 0);                -- Binary divider to create 10Ki clock.
+        variable counter5Ki        : unsigned(8 downto 0);                -- Binary divider to create 5Ki clock.
+        variable counter1Ki        : unsigned(10 downto 0);               -- Binary divider to create 1Ki clock.
+        variable counter500i       : unsigned(11 downto 0);               -- Binary divider to create 500i clock.
+        variable counter100i       : unsigned(14 downto 0);               -- Binary divider to create 100i clock.
+        variable counter50i        : unsigned(15 downto 0);               -- Binary divider to create 50i clock.
+        variable counter10i        : unsigned(17 downto 0);               -- Binary divider to create 10i clock.
+        variable counter5i         : unsigned(18 downto 0);               -- Binary divider to create 5i clock.
+        variable counter2i         : unsigned(29 downto 0);               -- Binary divider to create 1i clock.
+        variable counter1i         : unsigned(20 downto 0);               -- Binary divider to create 1i clock.
+        variable counter0_5i       : unsigned(21 downto 0);               -- Binary divider to create 0_5i clock.
+        variable counter0_2i       : unsigned(23 downto 0);               -- Binary divider to create 0_2i clock.
+        variable counter0_1i       : unsigned(24 downto 0);               -- Binary divider to create 0_1i clock.
+
+    begin
+        if RST = '1' or PLLLOCKED1 = '0' or PLLLOCKED2 = '0' or PLLLOCKED3 = '0' then
+            counter1Mi             := (others => '0');
+            counter895Ki           := (others => '0');
+            counter100Ki           := (others => '0');
+            counter31500i          := (others => '0');
+            counter31250i          := (others => '0');
+            counter15611i          := (others => '0');
+            counter10Ki            := (others => '0');
+            counter5Ki             := (others => '0');
+            counter1Ki             := (others => '0');
+            counter500i            := (others => '0');
+            counter100i            := (others => '0');
+            counter50i             := (others => '0');
+            counter10i             := (others => '0');
+            counter5i              := (others => '0');
+            counter2i              := (others => '0');
+            counter1i              := (others => '0');
+            counter0_5i            := (others => '0');
+            counter0_2i            := (others => '0');
+            counter0_1i            := (others => '0');
+            CK1Mi                  <= '0';
+            CK895Ki                <= '0';
+            CK100Ki                <= '0';
+            CK31500i               <= '0';
+            CK31250i               <= '0';
+            CK15611i               <= '0';
+            CK10Ki                 <= '0';
+            CK5Ki                  <= '0';
+            CK1Ki                  <= '0';
+            CK500i                 <= '0';
+            CK100i                 <= '0';
+            CK50i                  <= '0';
+            CK10i                  <= '0';
+            CK5i                   <= '0';
+            CK2i                   <= '0';
+            CK1i                   <= '0';
+            CK0_5i                 <= '0';
+            CK0_2i                 <= '0';
+            CK0_1i                 <= '0';
+            --
+           -- CKSOUNDi               <= '0';
+            CKRTCi                 <= '0';
+
+        elsif rising_edge(CK2Mi) then
+
+            -- 1000000Hz 
+            if counter1Mi = 0 or counter1Mi = 1 then
+                CK1Mi              <= not CK1Mi;
+                if counter1Mi  = 1 then
+                    counter1Mi     := (others => '0');
+                else
+                    counter1Mi     := counter1Mi + 1;
+                end if;
+            else
+                counter1Mi         := counter1Mi + 1;
+            end if;
+            -- 895000Hz 
+            if counter895Ki = 0 or counter895Ki = 1 then
+                CK895Ki            <= not CK895Ki;
+
+                if counter895Ki  = 1 then
+                    counter895Ki   := (others => '0');
+                else
+                    counter895Ki   := counter895Ki + 1;
+                end if;
+            else
+                counter895Ki       := counter895Ki + 1;
+            end if;
+            -- 100000Hz 
+            if counter100Ki = 9 or counter100Ki = 19 then
+                CK100Ki            <= not CK100Ki;
+                if counter100Ki  = 19 then
+                    counter100Ki   := (others => '0');
+                else
+                    counter100Ki   := counter100Ki + 1;
+                end if;
+            else
+                counter100Ki       := counter100Ki + 1;
+            end if;
+            -- 31500Hz 
+            if counter31500i = 30 or counter31500i = 62 then
+                CK31500i           <= not CK31500i;
+
+                if CONFIG(RTCSPEED) = "00" then
+                    CKRTCi         <= not CKRTCi;
+                end if;
+
+                if counter31500i  = 62 then
+                    counter31500i  := (others => '0');
+                else
+                    counter31500i  := counter31500i + 1;
+                end if;
+            else
+                counter31500i      := counter31500i + 1;
+            end if;
+            -- 31250Hz 
+            if counter31250i = 31 or counter31250i = 63 then
+                CK31250i           <= not CK31250i;
+
+                if CONFIG(RTCSPEED) = "01" then
+                    CKRTCi         <= not CKRTCi;
+                end if;
+
+                if counter31250i  = 63 then
+                    counter31250i  := (others => '0');
+                else
+                    counter31250i  := counter31250i + 1;
+                end if;
+            else
+                counter31250i      := counter31250i + 1;
+            end if;
+            -- 15611Hz 
+            if counter15611i = 63 or counter15611i = 127 then
+                CK15611i           <= not CK15611i;
+
+                if CONFIG(RTCSPEED) = "10" then
+                    CKRTCi         <= not CKRTCi;
+                end if;
+
+                if counter15611i  = 127 then
+                    counter15611i  := (others => '0');
+                else
+                    counter15611i  := counter15611i + 1;
+                end if;
+            else
+                counter15611i      := counter15611i + 1;
+            end if;
+            -- 10000Hz 
+            if counter10Ki = 99 or counter10Ki = 199 then
+                CK10Ki             <= not CK10Ki;
+                if counter10Ki  = 199 then
+                    counter10Ki    := (others => '0');
+                else
+                    counter10Ki    := counter10Ki + 1;
+                end if;
+            else
+                counter10Ki        := counter10Ki + 1;
+            end if;
+            -- 5000Hz 
+            if counter5Ki = 199 or counter5Ki = 399 then
+                CK5Ki              <= not CK5Ki;
+                if counter5Ki  = 399 then
+                    counter5Ki     := (others => '0');
+                else
+                    counter5Ki     := counter5Ki + 1;
+                end if;
+            else
+                counter5Ki         := counter5Ki + 1;
+            end if;
+            -- 1000Hz 
+            if counter1Ki = 999 or counter1Ki = 1999 then
+                CK1Ki              <= not CK1Ki;
+                if counter1Ki  = 1999 then
+                    counter1Ki     := (others => '0');
+                else
+                    counter1Ki     := counter1Ki + 1;
+                end if;
+            else
+                counter1Ki         := counter1Ki + 1;
+            end if;
+            -- 500Hz 
+            if counter500i = 1999 or counter500i = 3999 then
+                CK500i             <= not CK500i;
+                if counter500i  = 3999 then
+                    counter500i    := (others => '0');
+                else
+                    counter500i    := counter500i + 1;
+                end if;
+            else
+                counter500i        := counter500i + 1;
+            end if;
+            -- 100Hz 
+            if counter100i = 9999 or counter100i = 19999 then
+                CK100i             <= not CK100i;
+                if counter100i  = 19999 then
+                    counter100i    := (others => '0');
+                else
+                    counter100i    := counter100i + 1;
+                end if;
+            else
+                counter100i        := counter100i + 1;
+            end if;
+            -- 50Hz 
+            if counter50i = 19999 or counter50i = 39999 then
+                CK50i              <= not CK50i;
+                if counter50i  = 39999 then
+                    counter50i     := (others => '0');
+                else
+                    counter50i     := counter50i + 1;
+                end if;
+            else
+                counter50i         := counter50i + 1;
+            end if;
+            -- 10Hz 
+            if counter10i = 99999 or counter10i = 199999 then
+                CK10i              <= not CK10i;
+                if counter10i  = 199999 then
+                    counter10i     := (others => '0');
+                else
+                    counter10i     := counter10i + 1;
+                end if;
+            else
+                counter10i         := counter10i + 1;
+            end if;
+            -- 5Hz 
+            if counter5i = 199999 or counter5i = 399999 then
+                CK5i               <= not CK5i;
+                if counter5i  = 399999 then
+                    counter5i      := (others => '0');
+                else
+                    counter5i      := counter5i + 1;
+                end if;
+            else
+                counter5i          := counter5i + 1;
+            end if;
+            -- 2Hz 
+            if counter2i = 499999 or counter2i = 999999 then
+                CK2i               <= not CK2i;
+                if counter2i  = 999999 then
+                    counter2i      := (others => '0');
+                else
+                    counter2i      := counter2i + 1;
+                end if;
+            else
+                counter2i          := counter2i + 1;
+            end if;
+            -- 1Hz 
+            if counter1i = 999999 or counter1i = 1999999 then
+                CK1i               <= not CK1i;
+                if counter1i  = 1999999 then
+                    counter1i      := (others => '0');
+                else
+                    counter1i      := counter1i + 1;
+                end if;
+            else
+                counter1i          := counter1i + 1;
+            end if;
+            -- 0.5Hz 
+            if counter0_5i = 1999999 or counter0_5i = 3999999 then
+                CK0_5i             <= not CK0_5i;
+                if counter0_5i  = 3999999 then
+                    counter0_5i    := (others => '0');
+                else
+                    counter0_5i    := counter0_5i + 1;
+                end if;
+            else
+                counter0_5i        := counter0_5i + 1;
+            end if;
+            -- 0.2Hz 
+            if counter0_2i = 4999999 or counter0_2i = 9999999 then
+                CK0_2i             <= not CK0_2i;
+                if counter0_2i  = 9999999 then
+                    counter0_2i    := (others => '0');
+                else
+                    counter0_2i    := counter0_2i + 1;
+                end if;
+            else
+                counter0_2i        := counter0_2i + 1;
+            end if;
+            -- 0.1Hz 
+            if counter0_1i = 9999999 or counter0_1i = 19999999 then
+                CK0_1i             <= not CK0_1i;
+                if counter0_1i  = 19999999 then
+                    counter0_1i    := (others => '0');
+                else
+                    counter0_1i    := counter0_1i + 1;
+                end if;
+            else
+                counter0_1i        := counter0_1i + 1;
+            end if;
+        end if;
+    end process;
+
+    -- Process the clocks according to the user selections and assign.
+    --
+    process (RST, PLLLOCKED1, PLLLOCKED2, PLLLOCKED3, CK112Mi) 
+    begin
+        if RST = '1' or PLLLOCKED1 = '0' or PLLLOCKED2 = '0' or PLLLOCKED3 = '0' then
+            CKENCPUi               <= '0';
+            CKENLEDSi              <= '0';
+            CKENPERi               <= '0';
+            CPUEDGE                <= "00";
+            LEDSEDGE               <= "00";
+            VIDEOEDGE              <= "00";
+            CKVIDEOi               <= '0';
+            PEREDGE                <= "00";
+
+        elsif rising_edge(CK112Mi) then
+
+            -- Once the rising edge of the CPU clock is detected, enable the CPU Clock Enable signal
+            -- which is used to enable the master clock onto the logic.
+            CPUEDGE(0)             <= CPUEDGE(1);
+            CKENCPUi               <= '0';
+            if CPUEDGE = "10" then
+                CKENCPUi           <= '1';
+            end if;
+
+            -- Once the rising edge of the LED clock is detected, enable the LED Clock Enable signal
+            -- which is used to enable the master clock onto the LED logic.
+            LEDSEDGE(0)            <= LEDSEDGE(1);
+            CKENLEDSi              <= '0';
+            if LEDSEDGE = "10" then
+                CKENLEDSi          <= '1';
+            end if;
+
+            -- Once the rising edge of the Video clock is detected, enable the LED Clock Enable signal
+            -- which is used to enable the master clock onto the Video logic.
+            VIDEOEDGE(0)           <= VIDEOEDGE(1);
+            CKENVIDEOi             <= '0';
+            if VIDEOEDGE = "10" then
+                CKENVIDEOi         <= '1';
+            end if;
+
+            -- Form the video frequency enable signal according to the user selection.
+            --
+            case CONFIG(VIDSPEED) is
+                when "000" => -- 8MHz
+                    VIDEOEDGE(1)   <= CK8Mi;
+   
+                when "001" => -- 16MHz
+                    VIDEOEDGE(1)   <= CK16Mi;
+  
+                when "010" => -- 8.8672375MHz
+                    VIDEOEDGE(1)   <= CK8M8672i;
+ 
+                when "011" => -- 17.734475MHz
+                    VIDEOEDGE(1)   <= CK17M734i;
+                    
+                when "100" => -- 25.175MHz - Standard VGA 640x480 mode.
+                    VIDEOEDGE(1)   <= CK25M175i;
+
+                when "101" => -- 8MHz
+                    VIDEOEDGE(1)   <= CK25M175i;
+
+                when "110" => -- 1368x768 VGA mode.
+                    VIDEOEDGE(1)   <= CK31M5i;
+
+                when "111" => -- Pixel clock for 1024x768 VGA mode. Should be 65Mhz.
+                    VIDEOEDGE(1)   <= CK25M175i;
+            end case;
+
+            -- The video clock is multiplexed with the correct frequency chosen for the video
+            -- mode. The actual clock is sent to the video module rather than an enable as skew
+            -- is less of an issue.
+            --
+            case CONFIG(VIDSPEED) is
+                when "000" => -- 8MHz
+                    CKVIDEOi       <= CK8Mi;
+   
+                when "001" => -- 16MHz
+                    CKVIDEOi       <= CK16Mi;
+  
+                when "010" => -- 8.8672375MHz
+                    CKVIDEOi       <= CK8M8672i;
+ 
+                when "011" => -- 17.734475MHz
+                    CKVIDEOi       <= CK17M734i;
+
+                when "100" => -- 25.175MHz - Standard VGA 640x480@60Hz mode.
+                    CKVIDEOi       <= CK25M175i;
+
+                when "101" => -- 25.175MHz - Standard VGA 640x480@60Hz mode.
+                    CKVIDEOi       <= CK25M175i;
+
+                when "110" => -- 640x480@75Hz mode.
+                    CKVIDEOi       <= CK31M5i;
+
+                when "111" => -- 25.175MHz - Standard VGA 640x480@60Hz mode.
+                    CKVIDEOi       <= CK25M175i;
+            end case;
+
+            -- The sound clock is multiplexed with the correct frequency according to model.
+            --
+            case CONFIG(SNDSPEED) is
+                when "01" =>
+                    CKSOUNDi     <= CK895Ki;
+
+                when "00" | "10" | "11" =>
+                    CKSOUNDi     <= CK2Mi;
+            end case;
+
+            -- Once the rising edge of the Peripherals clock is detected, enable the Peripheral Clock Enable signal
+            -- which is used to enable the master clock onto the Peripheral logic.
+            PEREDGE(0)             <= PEREDGE(1);
+            CKENPERi               <= '0';
+            if PEREDGE = "10" then
+                CKENPERi           <= '1';
+            end if;
+            
+            -- If debugging has been enabled and the debug cpu frequency set to a valid value, change cpu clock accordingly.
+            if DEBUG_ENABLE = 0 or DEBUG(ENABLED) = '0' or DEBUG(CPUFREQ) = "0000" then
+
+                -- The CPU speed is configured by the CMT register and CMT state or the CPU register. Select the right
+                -- frequency and form the clock by flipping on the right flip flag.
+                --
+                case CONFIG(CPUSPEED) is
+                    when "0001" => -- 3.546875MHz
+                        CPUEDGE(1) <= CK3M546875i;
+                    when "0010" => -- 4MHz
+                        CPUEDGE(1) <= CK4Mi;
+                    when "0011" => -- 7.709MHz
+                        CPUEDGE(1) <= CK7M709i;
+                    when "0100" => -- 8MHz
+                        CPUEDGE(1) <= CK8Mi;
+                    when "0101" => -- 14.1875MHz
+                        CPUEDGE(1) <= CK14M1875i;
+                    when "0110" => -- 16MHz
+                        CPUEDGE(1) <= CK16Mi;
+                    when "0111" => -- 28.375MHz
+                        CPUEDGE(1) <= CK28M375i;
+                    when "1000" => -- 32MHz
+                        CPUEDGE(1) <= CK32Mi;
+                    when "1001" => -- 56.750MHz
+                        CPUEDGE(1) <= CK56M750i;
+                    when "1010" => -- 64MHz
+                        CPUEDGE(1) <= CK64Mi;
+    
+                    -- Unallocated frequencies, use default.
+                    when "0000" | "1011" | "1100" | "1101" | "1110" | "1111" => -- 2MHz
+                        CPUEDGE(1) <= CK2Mi;
+                end case;
+            else
+                case DEBUG(CPUFREQ) is
+                    when "0000" => -- Use normal cpu frequency, so this choice shouldnt be selected.
+                        CPUEDGE(1) <= CK2Mi;
+                    when "0001" => -- 1MHz
+                        CPUEDGE(1) <= CK1Mi;
+                    when "0010" => -- 100KHz
+                        CPUEDGE(1) <= CK100Ki;
+                    when "0011" => -- 10KHz
+                        CPUEDGE(1) <= CK10Ki;
+                    when "0100" => -- 5KHz
+                        CPUEDGE(1) <= CK5Ki;
+                    when "0101" => -- 1KHz
+                        CPUEDGE(1) <= CK1Ki;
+                    when "0110" => -- 500Hz
+                        CPUEDGE(1) <= CK500i;
+                    when "0111" => -- 100Hz
+                        CPUEDGE(1) <= CK100i;
+                    when "1000" => -- 50Hz
+                        CPUEDGE(1) <= CK50i;
+                    when "1001" => -- 10Hz
+                        CPUEDGE(1) <= CK10i;
+                    when "1010" => -- 5Hz
+                        CPUEDGE(1) <= CK5i;
+                    when "1011" => -- 2Hz
+                        CPUEDGE(1) <= CK2i;
+                    when "1100" => -- 1Hz
+                        CPUEDGE(1) <= CK1i;
+                    when "1101" => -- 0.5Hz
+                        CPUEDGE(1) <= CK0_5i;
+                    when "1110" => -- 0.2Hz
+                        CPUEDGE(1) <= CK0_2i;
+                    when "1111" => -- 0.1Hz
+                        CPUEDGE(1) <= CK0_1i;
+                end case;
+            end if;
+
+            -- Sampling frequency of signals, typically used to drive LED outputs but could easily be read by an oscilloscope.
+            --
+            case DEBUG(SMPFREQ) is
+                when "0000" => -- Use normal cpu frequency.
+                    LEDSEDGE(1)    <= CPUEDGE(1);
+                when "0001" => -- 1MHz
+                    LEDSEDGE(1)    <= CK1Mi;
+                when "0010" => -- 100KHz
+                    LEDSEDGE(1)    <= CK100Ki;
+                when "0011" => -- 10KHz
+                    LEDSEDGE(1)    <= CK10Ki;
+                when "0100" => -- 5KHz
+                    LEDSEDGE(1)    <= CK5Ki;
+                when "0101" => -- 1KHz
+                    LEDSEDGE(1)    <= CK1Ki;
+                when "0110" => -- 500Hz
+                    LEDSEDGE(1)    <= CK500i;
+                when "0111" => -- 100Hz
+                    LEDSEDGE(1)    <= CK100i;
+                when "1000" => -- 50Hz
+                    LEDSEDGE(1)    <= CK50i;
+                when "1001" => -- 10Hz
+                    LEDSEDGE(1)    <= CK10i;
+                when "1010" => -- 5Hz
+                    LEDSEDGE(1)    <= CK5i;
+                when "1011" => -- 2Hz
+                    LEDSEDGE(1)    <= CK2i;
+                when "1100" => -- 1Hz
+                    LEDSEDGE(1)    <= CK1i;
+                when "1101" => -- 0.5Hz
+                    LEDSEDGE(1)    <= CK0_5i;
+                when "1110" => -- 0.2Hz
+                    LEDSEDGE(1)    <= CK0_2i;
+                when "1111" => -- 0.1Hz
+                    LEDSEDGE(1)    <= CK0_1i;
+            end case;
+
+            -- Form the RTC frequency enable signal according to the user selection.
+            --
+            case CONFIG(PERSPEED) is
+                when "00" =>        -- 2MHz
+                    PEREDGE(1)     <= CK2Mi;
+
+                when "01" | "10" | "11" => -- 2MHz
+                    PEREDGE(1)     <= CK2Mi;
+            end case;
+
+        end if;
+    end process;
+
+    -- Assign necessary clocks and enables.
+    --
+    CLKBUS(CKMASTER)               <= CK112Mi;
+    CLKBUS(CKSOUND)                <= CKSOUNDi;                          -- Sound base clock, 50/50 duty cycle.
+    CLKBUS(CKRTC)                  <= CKRTCi;                            -- RTC base clock, 50/50 duty cycle.
+    CLKBUS(CKENVIDEO)              <= CKENVIDEOi;                        -- Enable signal for video base clock.
+    CLKBUS(CKVIDEO)                <= CKVIDEOi;                          -- Clock signal for video base clock.
+    CLKBUS(CKENCPU)                <= CKENCPUi;                          -- Enable signal for CPU base clock.
+    CLKBUS(CKENLEDS)               <= CKENLEDSi;                         -- Enable signal for LEDS base clock.
+    CLKBUS(CKENPERIPH)             <= CKENPERi;                          -- Enable signal for Peripheral base clock.
+    CLKBUS(CKIOP)                  <= CK64Mi;
+
+end RTL;
diff --git a/common/cmt.vhd b/common/cmt.vhd
new file mode 100644
index 0000000..187c56c
--- /dev/null
+++ b/common/cmt.vhd
@@ -0,0 +1,1615 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            cmt.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series PWM Tape Interface.
+--                  This module fully emulates the Sharp PWM tape interface. It uses cache ram
+--                  to simulate the tape. Data is played out to the Sharp or read from the Sharp
+--                  and stored in the ram.
+--                  For reading of data from Tape to the Sharp, the HPS or other controller loads a
+--                  complete tape into ram and should the Play/Auto function be enabled, playback
+--                  starts immediately.
+--                  For writing of data from the Sharp to Tape, the data is stored in ram and the
+--                  HPS or other controller, when it gets the completed signal, can read out the ram
+--                  and store the data onto a local filesystem.
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018    - Initial module written and playback mode tested and debugged.
+--                  August 2018  - Record mode written but not yet debugged/completed.
+--                  October 2018 - Added APSS for MZ80B emulation.
+--                                 Major rework of read (MZ Write) logic.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+use ieee.numeric_std.all;
+
+entity cmt is
+    Port (
+        RST                  : in  std_logic;
+
+        -- Clock signals needed by this module.
+        CLKBUS               : in  std_logic_vector(CLKBUS_WIDTH);        
+
+        -- Different operations modes.
+        CONFIG               : in  std_logic_vector(CONFIG_WIDTH);
+
+        -- Cassette magnetic tape signals.
+        CMT_BUS_OUT          : out std_logic_vector(CMT_BUS_OUT_WIDTH);
+        CMT_BUS_IN           : in  std_logic_vector(CMT_BUS_IN_WIDTH);
+
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_UPLOAD         : in  std_logic;                            -- HPS Uploading from FPGA.
+        IOCTL_CLK            : in  std_logic;                            -- HPS I/O Clock.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+        -- Debug Status Leds
+        DEBUG_STATUS_LEDS    : out std_logic_vector(31 downto 0)         -- 32 leds to display cmt internal status.
+    );
+end cmt;
+
+architecture RTL of cmt is
+
+--
+-- Components
+--
+component dpram
+    generic (
+          init_file          :     string;
+          widthad_a          :     natural;
+          width_a            :     natural;
+          widthad_b          :     natural;
+          width_b            :     natural;
+          outdata_reg_a      :     string := "UNREGISTERED";
+          outdata_reg_b      :     string := "UNREGISTERED"
+    );
+    Port (
+          clock_a            : in  std_logic  := '1';
+          clocken_a          : in  std_logic  := '1';
+          address_a          : in  std_logic_vector (widthad_a-1 downto 0);
+          data_a             : in  std_logic_vector (width_a-1 downto 0);
+          wren_a             : in  std_logic  := '0';
+          q_a                : out std_logic_vector (width_a-1 downto 0);
+
+          clock_b            : in  std_logic;
+          clocken_b          : in  std_logic  := '1';
+          address_b          : in  std_logic_vector (widthad_b-1 downto 0);
+          data_b             : in  std_logic_vector (width_b-1 downto 0);
+          wren_b             : in  std_logic  := '0';
+          q_b                : out std_logic_vector (width_b-1 downto 0)
+      );
+end component;
+
+-- HPS Control signals.
+signal IOCTL_CS_HDR_n        :     std_logic;
+signal IOCTL_CS_DATA_n       :     std_logic;
+signal IOCTL_CS_ASCII_n      :     std_logic;
+signal IOCTL_TAPEHDR_WEN     :     std_logic;
+signal IOCTL_TAPEDATA_WEN    :     std_logic;
+signal IOCTL_ASCII_WEN       :     std_logic;
+signal IOCTL_DIN_HDR         :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_DATA        :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_ASCII       :     std_logic_vector(7 downto 0);
+-- CMT Control signals.
+signal CMT_BUS_OUTi          :     std_logic_vector(CMT_BUS_OUT_WIDTH);      -- CMT bus output.
+signal BUTTONS_LAST          :     std_logic_vector(1 downto 0);             -- Virtual buttons last sample, used to detect changes.
+signal PLAY_READY_SET_CNT    :     integer range 0 to 32000000   := 0;       -- 1 second timer from last cache upload to PLAY_READY being set.
+signal PLAY_READY_CLR_CNT    :     unsigned(21 downto 0);                    -- 2 second timer from motor being stopped to PLAY_READY being cleared.
+signal PLAY_READY            :     std_logic;                                -- Cache loaded, playback ready to commence.
+signal PLAY_READY_CLR        :     std_logic;                                -- Clear PLAY_READY signal.
+signal PLAY_BUTTON           :     std_logic;                                -- Virtual Play button.
+signal PLAYING               :     std_logic_vector(2 downto 0);             -- Playing state, 3 cycle, 0 = inactive, 1 = active, msb = most recent.
+signal RECORD_READY          :     std_logic;                                -- Record buffer full (data received from MZ). Active = 1
+signal RECORD_READY_SET      :     std_logic;                                -- Trigger to activate the RECORD_READY signal.
+signal RECORD_READY_SEQ      :     std_logic_vector(1 downto 0);             -- Setup and hold sequencer.
+signal RECORD_BUTTON         :     std_logic;                                -- Virtual Record button.
+signal RECORDING             :     std_logic;                                -- Signal indicating a Record is underway, Active = 1.
+signal RECSEQ                :     std_logic_vector(2 downto 0);             -- Signal, 3 cycles, indicating 
+signal MOTOR_TOGGLE          :     std_logic_vector(1 downto 0);             -- Signal indicating if the MZ wants to start or toggle the motor.
+signal APSS_TIMER_CNT        :     unsigned(20 downto 0);                    -- 1 second virtual APSS SEEK time.
+signal WRITEBIT              :     std_logic;                                -- Tape data signal sent to the MZ (for playback).
+signal READBIT               :     std_logic;                                -- Tape data signal eminating from the MZ (for recording).
+signal TAPE_MOTOR_ON_n       :     std_logic;                                -- Virtual motor signal, tape motor running = 0.
+-- Bit transmitter signals.
+signal XMIT_DONE             :     std_logic;                                -- Transmit of bit complete.
+signal XMIT_SEQ              :     std_logic_vector(2 downto 0);             -- Setup and hold sequencer.
+signal XMIT_LOAD_1           :     std_logic;                                -- Load bit and start transmission selector 1.
+signal XMIT_LOAD_2           :     std_logic;                                -- Load bit and start transmission selector 2.
+signal XMIT_BIT_1            :     std_logic;                                -- Transmit bit for XMIT_LOAD_2 to be PWM modulated and sent to MZ.
+signal XMIT_BIT_2            :     std_logic;                                -- Working bit for active XMIT_BIT.
+signal XMIT_COUNT            :     integer range -7999 to 8000 := 0;
+signal XMIT_LIMIT            :     integer range -7999 to 8000 := 0;
+-- Bit padding transmitter signals.
+signal XMIT_PADDING_LOAD     :     std_logic;
+signal XMIT_PADDING_BIT      :     std_logic;
+signal XMIT_PADDING_DONE     :     std_logic;
+signal XMIT_PADDING_CNT1     :     integer range 0 to 32767   := 0;
+signal XMIT_PADDING_CNT2     :     integer range 0 to 32767   := 0;
+signal XMIT_PADDING_LEVEL1   :     std_logic;
+signal XMIT_PADDING_LEVEL2   :     std_logic;
+signal PADDING_SEQ           :     std_logic_vector(2 downto 0);             -- Setup and hold sequencer.
+signal PADDING_CNT1          :     integer range 0 to 32767   := 0;
+signal PADDING_CNT2          :     integer range 0 to 32767   := 0;
+signal PADDING_LEVEL1        :     std_logic;
+signal PADDING_LEVEL2        :     std_logic;
+-- Cache RAM header/data transmitter signals.
+signal XMIT_RAM_LOAD         :     std_logic;
+signal XMIT_RAM_DONE         :     std_logic;
+signal XMIT_RAM_SEQ          :     std_logic_vector(2 downto 0);             -- Setup and hold sequencer.
+signal XMIT_RAM_ADDR         :     std_logic_vector(15 downto 0);
+signal XMIT_ASCII_RAM_ADDR   :     std_logic_vector(8 downto 0);             -- Address for the Sharp Ascii to Ascii conversion table.
+signal XMIT_RAM_COUNT        :     unsigned(15 downto 0);
+signal XMIT_RAM_CHKSUM_CNT   :     unsigned(1 downto 0);
+signal XMIT_RAM_CHECKSUM     :     std_logic_vector(15 downto 0);
+signal XMIT_RAM_TYPE         :     std_logic;
+signal XMIT_RAM_STATE        :     integer range 0 to 7 := 0;
+signal XMIT_RAM_SR           :     std_logic_vector(8 downto 0);
+signal XMIT_RAM_BIT_CNT      :     integer range 0 to 8 := 0;
+signal XMIT_TAPE_SIZE        :     unsigned(15 downto 0);
+-- RAM control signals.
+signal RAM_ADDR              :     std_logic_vector(15 downto 0);            -- Multiplexed (Header, Data) RAM address
+signal RAM_DATAIN            :     std_logic_vector(7 downto 0);             -- Multiplexed RAM data in.
+signal HDR_RAM_DATAOUT       :     std_logic_vector(7 downto 0);             -- Header RAM data output.
+signal HDR_RAM_WEN           :     std_logic;                                -- Header RAM data write enable.
+signal DATA_RAM_DATAOUT      :     std_logic_vector(7 downto 0);             -- Data RAM data output.
+signal DATA_RAM_WEN          :     std_logic;                                -- Data RAM data write enable.
+signal ASCII_RAM_ADDR        :     std_logic_vector(8 downto 0);             -- Multiplexed RAM address for the Ascii conversion table.
+signal ASCII_RAM_DATAOUT     :     std_logic_vector(7 downto 0);             -- Sharp Ascii to Ascii conversion output.
+--
+-- Main process Finite State Machine variables.
+signal TAPE_READ_STATE       :     integer range 0 to 15       := 0;
+signal TAPE_READ_SEQ         :     std_logic_vector(2 downto 0);             -- Setup and hold sequencer.
+-- Receiver (for recording) signals.
+signal RCV_RAM_SUCCESS       :     std_logic;
+signal RCV_RAM_ADDR          :     std_logic_vector(15 downto 0);
+signal RCV_ASCII_RAM_ADDR    :     std_logic_vector(8 downto 0);             -- Address for the Sharp Ascii to Ascii conversion table.
+signal RCV_RAM_STATE         :     integer range 0 to 8 := 0;
+signal RCV_RAM_CHECKSUM      :     std_logic_vector(15 downto 0);
+signal RCV_TAPE_SIZE         :     std_logic_vector(15 downto 0);
+signal RCV_RAM_TRY           :     integer range 0 to 1;
+signal RCV_BYTE_AVAIL        :     std_logic;
+signal RCV_BYTE_CLR          :     std_logic;
+signal RCV_BYTE              :     std_logic_vector(7 downto 0);
+signal RCV_LOAD              :     std_logic;
+signal RCV_DONE              :     std_logic;
+signal RCV_CLR               :     std_logic;
+signal RCV_ERROR             :     std_logic;
+signal RCV_STATE             :     integer range 0 to 9;
+signal RCV_BLOCK             :     integer range 0 to 1;
+signal RCV_TYPE              :     integer range 0 to 1;
+signal RCV_TMH_CNT           :     integer range 0 to 40;
+signal RCV_TML_CNT           :     integer range 0 to 40;
+signal RCV_DATASIZE          :     unsigned(15 downto 0);
+signal RCV_SR                :     std_logic_vector(7 downto 0);
+signal RCV_CHECKSUM          :     std_logic_vector(15 downto 0);
+signal RCV_SEQ               :     std_logic_vector(1 downto 0);             -- Setup and hold sequencer.
+signal RCV_CNT               :     unsigned(15 downto 0); 
+signal TMH_CNT               :     integer range 0 to 40;
+signal TML_CNT               :     integer range 0 to 40;
+signal DATA_CNT              :     unsigned(15 downto 0);
+signal SPC_CNT               :     integer range 0 to 256;
+signal BIT_CNT               :     unsigned(2 downto 0);
+
+--
+begin
+    -- Wired signals between this CMT unit and the MZ/MCtrl bus.
+    --
+    CMT_BUS_OUTi(pkgs.mctrl_pkg.WRITEBIT)     <= WRITEBIT;                    -- Write a bit to the MZ PIO.
+    CMT_BUS_OUTi(pkgs.mctrl_pkg.SENSE)        <= not TAPE_MOTOR_ON_n;         -- Indiate current state of Motor, 0 if not running, 1 if running.
+    CMT_BUS_OUTi(pkgs.mctrl_pkg.ACTIVE)       <= PLAYING(2) or RECORDING; 
+    CMT_BUS_OUTi(pkgs.mctrl_pkg.PLAY_READY)   <= PLAY_READY;
+    CMT_BUS_OUTi(pkgs.mctrl_pkg.PLAYING)      <= PLAYING(2);
+    CMT_BUS_OUTi(pkgs.mctrl_pkg.RECORD_READY) <= RECORD_READY;
+    CMT_BUS_OUTi(pkgs.mctrl_pkg.RECORDING)    <= RECORDING;
+    --
+    READBIT                                   <= CMT_BUS_IN(pkgs.mctrl_pkg.READBIT); -- Read a bit from the MZ PIO.
+    MOTOR_TOGGLE(1)                           <= CMT_BUS_IN(PLAY);
+    CMT_BUS_OUT                               <= CMT_BUS_OUTi;
+
+    -- Mux Signals from different sources.
+    RAM_ADDR                                  <= RCV_RAM_ADDR                when RECORDING = '1'
+                                                 else
+                                                 XMIT_RAM_ADDR;
+    ASCII_RAM_ADDR                            <= RCV_ASCII_RAM_ADDR          when RECORDING = '1'
+                                                 else
+                                                 XMIT_ASCII_RAM_ADDR;
+    IOCTL_CS_HDR_n                            <= '0'                         when IOCTL_ADDR(24 downto 16) = "001000000"
+                                                 else '1';
+    IOCTL_CS_DATA_n                           <= '0'                         when IOCTL_ADDR(24 downto 16) = "001000001"
+                                                 else '1';
+    IOCTL_CS_ASCII_n                          <= '0'                         when IOCTL_ADDR(24 downto 16) = "001000010"
+                                                 else '1';
+    IOCTL_TAPEHDR_WEN                         <= '1'                         when IOCTL_CS_HDR_n  = '0'   and IOCTL_WR = '1'
+                                                 else '0';
+    IOCTL_TAPEDATA_WEN                        <= '1'                         when IOCTL_CS_DATA_n = '0'   and IOCTL_WR = '1'
+                                                 else '0';
+    IOCTL_ASCII_WEN                           <= '1'                         when IOCTL_CS_ASCII_n  = '0' and IOCTL_WR = '1'
+                                                 else '0';
+    IOCTL_DIN                                 <= X"000000" & IOCTL_DIN_HDR   when IOCTL_CS_HDR_n  = '0'
+                                                 else
+                                                 X"000000" & IOCTL_DIN_DATA  when IOCTL_CS_DATA_n = '0'
+                                                 else
+                                                 X"000000" & IOCTL_DIN_ASCII when IOCTL_CS_ASCII_n = '0'
+                                                 else
+                                                 (others => '0');
+
+    -- Header Cache RAM.
+    -- Storage of the tape header for play and record operations.
+    TAPEHDR : dpram
+    GENERIC MAP (
+        init_file            => null,
+        widthad_a            => 7,
+        width_a              => 8,
+        widthad_b            => 7,
+        width_b              => 8
+    )
+    PORT MAP (
+        clock_a              => CLKBUS(CKMASTER), --CLKBUS(CKMEM),
+        clocken_a            => '1',
+        address_a            => RAM_ADDR(6 downto 0),
+        data_a               => RAM_DATAIN,
+        wren_a               => HDR_RAM_WEN,
+        q_a                  => HDR_RAM_DATAOUT,
+
+        clock_b              => IOCTL_CLK,
+        address_b            => IOCTL_ADDR(6 downto 0),
+        data_b               => IOCTL_DOUT(7 downto 0),
+        wren_b               => IOCTL_TAPEHDR_WEN,
+        q_b                  => IOCTL_DIN_HDR
+    );
+
+    -- Data Cache RAM.
+    -- Storage of the tape data for play and record operations.
+    -- Maximum size of 64K as this is the limit that can be accommodated by the MZ software.
+    TAPEDATA : dpram
+    GENERIC MAP (
+        init_file            => null,
+        widthad_a            => 16,
+        width_a              => 8,
+        widthad_b            => 16,
+        width_b              => 8
+    )
+    PORT MAP (
+        clock_a              => CLKBUS(CKMASTER), --CLKBUS(CKMEM),
+        clocken_a            => '1',
+        address_a            => RAM_ADDR,
+        data_a               => RAM_DATAIN,
+        wren_a               => DATA_RAM_WEN,
+        q_a                  => DATA_RAM_DATAOUT,
+
+        clock_b              => IOCTL_CLK,
+        address_b            => IOCTL_ADDR(15 downto 0),
+        data_b               => IOCTL_DOUT(7 downto 0),
+        wren_b               => IOCTL_TAPEDATA_WEN,
+        q_b                  => IOCTL_DIN_DATA
+    );
+
+    -- Sharp Ascii <-> Ascii conversion table.
+    -- Filenames are generally in Sharp Ascii format which is incompatible with modern
+    -- systems, ie. name of files on a file system, so conversion is needed in both directions.
+    ADCNV : dpram
+    GENERIC MAP (
+        init_file            => "./software/mif/ascii_conv.mif",
+        widthad_a            => 9,
+        width_a              => 8,
+        widthad_b            => 9,
+        width_b              => 8
+    )
+    PORT MAP (
+        clock_a              => CLKBUS(CKMASTER), --CLKBUS(CKMEM),
+        clocken_a            => '1',
+        address_a            => ASCII_RAM_ADDR(8 downto 0),
+        data_a               => (others => '0'),
+        wren_a               => '0',
+        q_a                  => ASCII_RAM_DATAOUT,
+
+        clock_b              => IOCTL_CLK,
+        address_b            => IOCTL_ADDR(8 downto 0),
+        data_b               => IOCTL_DOUT(7 downto 0),
+        wren_b               => IOCTL_ASCII_WEN,
+        q_b                  => IOCTL_DIN_ASCII
+    );
+
+
+    -- MZ80B/2000 control signals.
+    --
+    -- A0 MOTORON     Activates reel motor
+    -- A1 DIRECTION   Prepares for FF state (prepares for REW with L)
+    -- A2 PLAY        plays cassette
+    -- A3 STOP        Stops casette operation
+    -- B4 WRITEREADY  Pawl applied to prohibit writing casette tape
+    -- B5 TAPEREADY   Indicates tape is set in the casette deck
+    -- B6 WRITEBIT    Input terminal for casette data
+    -- B7 BREAKDETECT Detects break key during casette play
+    -- C4 EJECT       Starts eject operation
+    -- C5 SEEK        Latches ready state for FF and REW
+    -- C6 WRITEENABLE Sets head amp to READ state (WRITE with L)
+    -- C7 READBIT     Outpus data to be written into casette
+    --
+    -- DIRECTION clocked by SEEK, if DIRECTION = L when SEEK pulses high, then tape rewinds on activation of MOTORON.
+    -- If DIRECTION is high, then tape will fast forward. MOTORON, when pulsed high, activates the motor to go forward/backward.
+    -- PLAY pulsed high activates the play motor.which cancels a FF/REW event.
+    -- STOP when High, stops the Play/FF/REW events.
+    -- TAPEREADY when high indicates tape drive present and ready.
+    -- EJECT when Low, ejects the tape.
+    -- WRITEENABLE when Low enables record, otherwise when High enables play.
+    -- READBIT is the data to write to tape.
+    -- WRITEBIT is the data read from tape.
+    -- WRITEREADY when Low blocks recording.
+
+    --------------------------------------------------------------------
+    -- TAPE HEADER FORMAT
+    --------------------------------------------------------------------
+    -- LGAP | LTM | L | HDR  | CHKH | L | 256S | HDRC  | CHKH | L
+    -- SGAP | STM | L | FILE | CHKF | L | 256S | FILEC | CHKF | L
+    -- LGAP  is a long GAP
+    -- SGAP  is a short GAP
+    -- LTM   is a long tapemark - 40 long pulses then 40 short pulses
+    -- STM   is a short tapemark - 20 long pulses then 20 short puses 
+    -- HDR   is the tapeheader
+    -- HDRC  is a copy of the tapeheader
+    -- FILE  is the file
+    -- FILEC is a copy of the file
+    -- CHKH  is a 2 byte checksum of the tape header or its copy
+    -- CHKF  is a 2 byte checksum of the file or its copy
+    -- L     is 1 long pulse
+    -- 256S contains 256 short pulses
+    --------------------------------------------------------------------
+
+    -----------------------------------------------------------------------------------------------------------------------------------------
+    ------------------------------------------------------------- CMT control ---------------------------------------------------------------
+    -----------------------------------------------------------------------------------------------------------------------------------------
+
+    -- Process to determine CMT state according to inputs. ie. If we are STOPPED, PLAYING or RECORDING.
+    -- This is determined by the input switches in CONFIG(BUTTOS), 00 = Off, 01 = Play, 02 = Record and 03 = Auto.
+    -- Auto mode indicates the CMT logic has to determine wether it is PLAYING or RECORDING. The default is PLAYING
+    -- but if a bit is received from the MZ then we switch to RECORDING until a full tape dump has been received.
+    --
+    process( RST, CLKBUS(CKMASTER), CONFIG(BUTTONS), MOTOR_TOGGLE, CMT_BUS_IN) begin
+        if RST='1' then
+            TAPE_MOTOR_ON_n                         <= '1';
+            PLAY_BUTTON                             <= '0';
+            RECORD_BUTTON                           <= '0';
+            BUTTONS_LAST                            <= "00";
+            PLAYING                                 <= "000";
+            RECORDING                               <= '0';
+            MOTOR_TOGGLE(0)                         <= '0';
+            APSS_TIMER_CNT                          <= (others => '0');
+            CMT_BUS_OUTi(APSS_SEEK)                 <= '0';
+            CMT_BUS_OUTi(APSS_DIR)                  <= '0';
+            CMT_BUS_OUTi(APSS_EJECT)                <= '0';
+            CMT_BUS_OUTi(APSS_PLAY)                 <= '0';
+            CMT_BUS_OUTi(APSS_STOP)                 <= '1';
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                -- Store last state so we detect change.
+                BUTTONS_LAST                            <= CONFIG(BUTTONS);
+                MOTOR_TOGGLE(0)                         <= MOTOR_TOGGLE(1);
+    
+                -- Store last state so we can detect a switch to recording or play mode.
+                PLAYING(1 downto 0)                     <= PLAYING(2 downto 1);
+    
+                -- The MZ80C series use a manual cassette deck with motor automation, so we
+                -- need to simulate buttons and the states therein.
+                --
+                if CONFIG(MZ_80C) = '1' then
+    
+                    -- Process the buttons and adapt signals accordingly.
+                    --
+                    if BUTTONS_LAST /= CONFIG(BUTTONS) then
+                        case CONFIG(BUTTONS) is
+                            when "00" => -- Off
+                                PLAY_BUTTON             <= '0';
+                                RECORD_BUTTON           <= '0';
+                                TAPE_MOTOR_ON_n         <= '1';
+                                CMT_BUS_OUTi(TAPEREADY) <= '1';                         -- Indicates tape ejected.
+                                CMT_BUS_OUTi(WRITEREADY)<= '1';                         -- Indicates write mechanism disabled.
+                            when "10" => -- Record
+                                PLAY_BUTTON             <= '0';
+                                RECORD_BUTTON           <= '1';
+                                TAPE_MOTOR_ON_n         <= '0';
+                                CMT_BUS_OUTi(TAPEREADY) <= '0';                         -- Indicates tape loaded, active Low.
+                                CMT_BUS_OUTi(WRITEREADY)<= '1';                         -- Indicates write mechanism enabled.
+                            when "01"|"11" => -- Play/Auto
+                                -- Assume playback mode for Auto unless activity is detected from the MZ,
+                                -- in which case switch to Recording.
+                                PLAY_BUTTON             <= '1';
+                                RECORD_BUTTON           <= '0';
+                                TAPE_MOTOR_ON_n         <= '0';
+                                CMT_BUS_OUTi(TAPEREADY) <= '0';                         -- Indicates tape loaded, active Low.
+                                CMT_BUS_OUTi(WRITEREADY)<= '0';                         -- Indicates write mechanism disabled.
+                        end case;
+                    end if;
+    
+                    -- Once a recording becomes available to save, disable recording state.
+                    --
+                    if RECORD_READY = '1' then
+                        RECORDING                       <= '0';
+                    end if;
+        
+                    -- If in auto mode and data starts being received from the MZ, enter record mode. Once record
+                    -- mode completes, switch back to play mode.
+                    --
+                    if CONFIG(BUTTONS) = "11" then
+                        if RCV_SEQ = "11" or RECORDING = '1' then
+                            PLAY_BUTTON                 <= '0';
+                            RECORD_BUTTON               <= '1';
+                            CMT_BUS_OUTi(WRITEREADY)    <= '1';                         -- Indicates write mechanism disabled.
+                        else
+                            PLAY_BUTTON                 <= '1';
+                            RECORD_BUTTON               <= '0';
+                        end if;
+                    end if;
+    
+                    -- If the motor is running then setup the state according to the buttons pressed and the data availability.
+                    --
+                    if TAPE_MOTOR_ON_n = '0'    and PLAY_BUTTON = '1'   and PLAY_READY = '1' then
+                        PLAYING(2)                      <= '1';
+                        RECORDING                       <= '0';
+                    elsif TAPE_MOTOR_ON_n = '0' and RECORD_BUTTON = '1' then
+                        PLAYING(2)                      <= '0';
+                        RECORDING                       <= '1';
+                    else
+                        PLAYING(2)                      <= '0';
+                        RECORDING                       <= '0';
+                    end if;
+        
+                    -- The play motor is controlled by an on/off toggle. A high pulse on MOTOR_TOGGLE will toggle the motor state.
+                    --
+                    if MOTOR_TOGGLE = "10" then
+                        TAPE_MOTOR_ON_n                 <= not TAPE_MOTOR_ON_n;
+                    end if;
+        
+                -- The MZ80B uses a fully automated APSS cassette deck, so just take actions on
+                -- the signals sent.
+                --
+                else
+                    -- Tape is always ready and able to write.
+                    --
+                    CMT_BUS_OUTi(TAPEREADY)             <= '0';                         -- Indicates tape loaded, active low.
+                    CMT_BUS_OUTi(WRITEREADY)            <= '1';                         -- Indicates write mechanism disabled.
+    
+                    -- If seek pulses high, store the direction.
+                    --
+                    if CMT_BUS_IN(pkgs.mctrl_pkg.SEEK) = '1' then
+                        CMT_BUS_OUTi(APSS_DIR)          <= CMT_BUS_IN(pkgs.mctrl_pkg.DIRECTION);
+                    end if;
+        
+                    -- If Eject goes active, latch and invert it for reading.
+                    --
+                    if CMT_BUS_IN(pkgs.mctrl_pkg.EJECT) = '0' then
+                        CMT_BUS_OUTi(APSS_EJECT)        <= '1';
+                        CMT_BUS_OUTi(APSS_SEEK)         <= '0';
+                        CMT_BUS_OUTi(APSS_PLAY)         <= '0';
+                        CMT_BUS_OUTi(APSS_STOP)         <= '0';
+                    end if;
+        
+                    -- The play motor is started/stopped by the PLAY/STOP signals.
+                    --
+                    if MOTOR_TOGGLE = "11"  and CMT_BUS_IN(pkgs.mctrl_pkg.STOP) = '0' then
+                        TAPE_MOTOR_ON_n                 <= '0';
+                        CMT_BUS_OUTi(APSS_PLAY)         <= '1';
+                        CMT_BUS_OUTi(APSS_EJECT)        <= '0';
+                        CMT_BUS_OUTi(APSS_SEEK)         <= '0';
+                        CMT_BUS_OUTi(APSS_STOP)         <= '0';
+    
+                    elsif MOTOR_TOGGLE /= "11" and CMT_BUS_IN(pkgs.mctrl_pkg.STOP) = '1' then
+                        TAPE_MOTOR_ON_n                 <= '1';
+                        CMT_BUS_OUTi(APSS_STOP)         <= '1';
+                        CMT_BUS_OUTi(APSS_PLAY)         <= '0';
+                        CMT_BUS_OUTi(APSS_EJECT)        <= '0';
+                        CMT_BUS_OUTi(APSS_SEEK)         <= '0';
+    
+                    -- If REEL_MOTOR pulses high, then engage APSS seek.
+                    --
+                    elsif CMT_BUS_IN(REEL_MOTOR) = '1' then
+                        CMT_BUS_OUTi(APSS_SEEK)         <= '1';
+                        CMT_BUS_OUTi(APSS_EJECT)        <= '0';
+                        CMT_BUS_OUTi(APSS_PLAY)         <= '0';
+                        CMT_BUS_OUTi(APSS_STOP)         <= '0';
+                        APSS_TIMER_CNT                  <= to_unsigned(1, 21);
+                    end if;
+    
+                    -- If the APSS SEEK action has been started, reset it after 1 second to simulate the real action.
+                    --
+                    if APSS_TIMER_CNT > 0 then
+                        APSS_TIMER_CNT                  <= APSS_TIMER_CNT + 1;
+                    end if;
+                    if APSS_TIMER_CNT = X"FFFFF" then
+                        CMT_BUS_OUTi(APSS_SEEK)         <= '0';
+                    end if;
+    
+                    -- Update the status as to wether we are playing, recording or idle.
+                    --
+                    PLAYING(2)                          <= PLAY_READY and CMT_BUS_OUTi(APSS_PLAY);
+                    RECORDING                           <= not CMT_BUS_IN(pkgs.mctrl_pkg.WRITEENABLE) and CMT_BUS_OUTi(APSS_PLAY);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Trigger, when a write occurs to ram, start a counter. Each write resets the counter. After 1 second of
+    -- no further writes, then the ram data is ready to play.
+    -- Clear funtionality allows the logic to clear the ready signal to indicate data has been processed.
+    --
+    process( RST, IOCTL_CLK, IOCTL_TAPEHDR_WEN, IOCTL_TAPEDATA_WEN, IOCTL_CS_HDR_n, IOCTL_CS_DATA_n )
+    begin
+        if RST = '1' then
+            PLAY_READY                              <= '0';
+            PLAY_READY_SET_CNT                      <= 0;
+            RECORD_READY                            <= '0';
+            RECORD_READY_SEQ                        <= "00";
+
+        elsif IOCTL_CLK'event and IOCTL_CLK = '1' then
+
+            -- Sample record complete signal and hold. Shift righ 2 bits, msb = latest value.
+            RECORD_READY_SEQ(0)                     <= RECORD_READY_SEQ(1);
+            RECORD_READY_SEQ(1)                     <= RECORD_READY_SET;
+
+            -- If the external clear is triggered, reset ready signal.
+            if PLAY_READY_CLR = '1' then
+                PLAY_READY                          <= '0';
+                PLAY_READY_SET_CNT                  <= 0;
+
+            -- Every write to ram resets the counter.
+            elsif IOCTL_TAPEHDR_WEN = '1' or IOCTL_TAPEDATA_WEN = '1' then
+                PLAY_READY                          <= '0';
+                PLAY_READY_SET_CNT                  <= 1;
+
+            -- 1 second timer, if no new writes have occurred to RAM, then set the ready flag.
+            elsif PLAY_READY_SET_CNT >= 32000000 then
+                PLAY_READY_SET_CNT                  <= 0;
+                PLAY_READY                          <= '1';
+            end if;
+
+            -- Set RECORD_READY if fsm determines a full tape message received.
+            if RECORD_READY_SEQ = "10" then
+                PLAY_READY                          <= '0';
+                RECORD_READY                        <= '1';
+
+            -- HPS access resets signal.
+            elsif IOCTL_CS_HDR_n = '0' or IOCTL_CS_DATA_n = '0' then
+                RECORD_READY                        <= '0';
+
+            -- If the fsm resets the signal then clear the flag as it will be receiving a new tape message.
+            elsif RECORD_READY_SEQ = "00" then
+                RECORD_READY                        <= '0';
+            end if;
+
+            -- Increment counters if enabled.
+            if PLAY_READY_SET_CNT >= 1 then
+                PLAY_READY_SET_CNT                  <= PLAY_READY_SET_CNT + 1;
+            end if;
+        end if;
+    end process;
+
+    -----------------------------------------------------------------------------------------------------------------------------------------
+    -------------------------------------------- Read from MZ (Write to Tape) logic ---------------------------------------------------------
+    -----------------------------------------------------------------------------------------------------------------------------------------
+
+    ----------------------------------------------------------------------------------------------------------------------
+    -- Write To Tape logic.
+    --
+    -- This block concentrates all the logic required to receive data from the MZ into RAM (virtual tape).
+    -- Viewed from the CMT, it is the reception of data from computer onto tape.
+    ----------------------------------------------------------------------------------------------------------------------
+
+    -- Process to receive the header/data blocks and checksum from the MZ and store it into the cache RAM. ie. MZ -> RAM.
+    -- The bit stream is assumed to be at the correct point and the data is serialised and loaded into the RAM.
+    --
+    process( RST, CLKBUS(CKMASTER) )
+    begin
+        if RST = '1' then
+            RCV_RAM_SUCCESS                         <= '0';
+            RCV_RAM_ADDR                            <= (others => '0');
+            RCV_RAM_CHECKSUM                        <= (others => '0');
+            RCV_RAM_STATE                           <= 0;
+            RCV_RAM_TRY                             <= 0;
+            RCV_LOAD                                <= '0';
+            RCV_CLR                                 <= '1';
+            RCV_BYTE_CLR                            <= '0';
+            RCV_TMH_CNT                             <= 0;
+            RCV_TML_CNT                             <= 0;
+            RCV_DATASIZE                            <= to_unsigned(0, 16);
+            RCV_TAPE_SIZE                           <= (others => '0');
+            RECORD_READY_SET                        <= '0';
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                -- Store the recording state to trigger events on changes.
+                RECSEQ(1 downto 0)                      <= RECSEQ(2 downto 1);
+                RECSEQ(2)                               <= RECORDING;
+    
+                -- If Receiver clear state is active, reset, only active for one clock.
+                --
+                if RCV_CLR = '1' then
+                    RCV_CLR                             <= '0';
+                end if;
+    
+                -- If a load command was executed, when the DONE signal goes inactive, acknowledging the command, reset
+                -- the load signal.
+                if RCV_LOAD = '1' and RCV_DONE = '0' then
+                    RCV_LOAD                            <= '0';
+                end if;
+    
+                -- If an error occurs, reset to the very beginning.
+                if RCV_ERROR = '1' then
+                    RCV_RAM_STATE                       <= 1;
+                    RCV_TYPE                            <= 0;
+                    RCV_CLR                             <= '1';
+                end if;
+    
+                -- At the end of a recording run, make a full reset ready for next save.
+                --
+                if RECSEQ = "001" then
+                    RCV_RAM_SUCCESS                     <= '0';
+                    RCV_RAM_ADDR                        <= (others => '0');
+                    RCV_RAM_CHECKSUM                    <= (others => '0');
+                    RCV_RAM_STATE                       <= 0;
+                    RCV_RAM_TRY                         <= 0;
+                    RCV_LOAD                            <= '0';
+                    RCV_CLR                             <= '1';
+                    RCV_BYTE_CLR                        <= '0';
+                    RCV_TMH_CNT                         <= 0;
+                    RCV_TML_CNT                         <= 0;
+                    RCV_DATASIZE                        <= to_unsigned(0, 16);
+    
+                -- If recording mode starts, setup required state.
+                elsif RECSEQ = "100" then
+                    RECORD_READY_SET                    <= '0';
+                    RCV_RAM_STATE                       <= 1;
+        
+                -- If recording, run the FSM.
+                elsif RECSEQ = "111" then
+    
+                    -- FSM to implement the receiption of data from MZ and storage in cache RAM>
+                    case(RCV_RAM_STATE) is
+                        when 0 => 
+                            RCV_RAM_STATE               <= 0;
+    
+                        -- Load up parameters for the Header or Data block according to expected type.
+                        when 1 =>
+                            if RCV_TYPE = 0 then
+                                RCV_TMH_CNT             <= 40;
+                                RCV_TML_CNT             <= 40;
+                                RCV_DATASIZE            <= to_unsigned(128 + 2, 16);    -- 2 Additional bytes for the checksum.
+                            else
+                                RCV_TMH_CNT             <= 20;
+                                RCV_TML_CNT             <= 20;
+                                RCV_DATASIZE            <= unsigned(RCV_TAPE_SIZE + 2);
+                            end if;
+                            RCV_RAM_SUCCESS             <= '0';
+                            RCV_RAM_ADDR                <= (others => '0');
+                            RCV_RAM_CHECKSUM            <= (others => '0');
+                            RCV_RAM_STATE               <= 2;
+                            RCV_RAM_TRY                 <= 0;
+                            RCV_LOAD                    <= '1';
+                            RCV_BYTE_CLR                <= '0';
+                            HDR_RAM_WEN                 <= '0';
+                            DATA_RAM_WEN                <= '0';
+    
+                        -- As data bytes become available, assemble them into RAM. The last
+                        -- 2 bytes are the checksum. If this is the header, then byes 18 and 19
+                        -- are the data block size to be received next.
+                        when 2 =>
+                            if RCV_BYTE_AVAIL = '1' then
+                                RCV_BYTE_CLR            <= '1';
+    
+                                -- During header reception, bytes 18 and 19 represent the size of the data segment.
+                                --
+                                if RCV_TYPE = 0 and RCV_RAM_SUCCESS = '0' then
+                                    if RCV_RAM_ADDR = 18 then
+                                        RCV_TAPE_SIZE(7 downto 0)  <= RCV_BYTE;
+                                    elsif RCV_RAM_ADDR = 19 then
+                                        RCV_TAPE_SIZE(15 downto 8) <= RCV_BYTE;
+                                    end if;
+                                end if;
+    
+                                -- If all data received, then next 2 bytes are the checksums.
+                                if RCV_RAM_ADDR = std_logic_vector(RCV_DATASIZE - 2) then
+                                    RCV_RAM_CHECKSUM(15 downto 8)  <= RCV_BYTE;
+                                    RCV_RAM_STATE       <= 6;
+                                elsif RCV_RAM_ADDR = std_logic_vector(RCV_DATASIZE - 1) then
+                                    RCV_RAM_CHECKSUM(7 downto 0)   <= RCV_BYTE;
+                                    if RCV_RAM_TRY = 0 then
+                                        RCV_RAM_STATE   <= 8;
+                                    else
+                                        RCV_RAM_STATE   <= 7;
+                                    end if;
+                                elsif RCV_RAM_TRY = 1 and RCV_RAM_SUCCESS = '1' then
+                                    RCV_RAM_STATE       <= 6;
+    
+                                -- If enabled, convert the filename to standard ascii.
+                                elsif RCV_TYPE = 0 and CONFIG(MZ_80C) = '1' and CONFIG(CMTASCII_IN) = '1' and RCV_RAM_ADDR >= std_logic_vector(to_unsigned(1, 9)) and RCV_RAM_ADDR <= std_logic_vector(to_unsigned(17,9)) then
+                                    RCV_ASCII_RAM_ADDR  <= '0' & RCV_BYTE;
+                                    RCV_RAM_STATE       <= 3;    
+                                else
+                                    RAM_DATAIN          <= RCV_BYTE;
+                                    RCV_RAM_STATE       <= 4;
+                                end if;
+                             end if;
+    
+                        -- Byte to be written is mapped via the Sharp Ascii <-> Ascii lookup table.
+                        when 3 =>
+                            RAM_DATAIN                  <= ASCII_RAM_DATAOUT;
+                            RCV_RAM_STATE               <= 4;
+    
+                        -- Assert Write to load data into RAM.
+                        when 4 =>
+                            if RCV_TYPE = 0 then
+                                HDR_RAM_WEN             <= '1';
+                            else
+                                DATA_RAM_WEN            <= '1';
+                            end if;
+                            RCV_RAM_STATE               <= 5;
+    
+                        -- Deassert write.
+                        when 5 =>
+                            HDR_RAM_WEN                 <= '0';
+                            DATA_RAM_WEN                <= '0';
+                            RCV_RAM_STATE               <= 6;
+    
+                        when 6 =>
+                            -- Once write transaction has completed, update the RAM address.
+                            RCV_RAM_ADDR                <= RCV_RAM_ADDR + 1;
+                            -- Receive the next byte.
+                            RCV_RAM_STATE               <= 2;
+    
+                        when 7 =>
+                            if RCV_DONE = '1' then
+                                RCV_RAM_STATE           <= 8;
+                            end if;
+    
+                        -- Compare checksums, raise SUCCESS flag if they match.
+                        when 8 =>
+                            if RCV_RAM_SUCCESS = '0' and RCV_RAM_CHECKSUM = RCV_CHECKSUM then
+                                RCV_RAM_SUCCESS         <= '1';
+                            end if;
+                            if RCV_RAM_TRY = 0 then
+                                RCV_RAM_TRY             <= 1;
+                                RCV_RAM_ADDR            <= (others => '0');
+                                RCV_RAM_STATE           <= 2;
+                            elsif RCV_TYPE = 0 and RCV_DONE = '1' then
+                                RCV_RAM_TRY             <= 0;
+                                RCV_TYPE                <= 1;      -- Receive data
+                                RCV_RAM_STATE           <= 1;
+                                RECSEQ                  <= "001";
+                              --RCV_CLR                 <= '1';
+                            else
+                                RCV_RAM_STATE           <= 1;      -- Start waiting for a new header.
+                                RCV_CLR                 <= '1';
+                                RCV_TYPE                <= 0;      -- Receive header
+                                RECORD_READY_SET        <= '1';
+                            end if;
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+    -- Process to read a bit (PWM decode) from the MZ output and process it according to the expected MZ Tape format framing.
+    -- Basically we detect when the bit rises then start counting a fixed period of time. Once the period has
+    -- elapsed, we sample the data and indicate it is available.
+    -- The bit is then fed through an FSM which evaluates the value and the position in order to setup the correct framing and
+    -- commence data extraction. The data is then provided byte by byte to the external process which assembles it into memory
+    -- and checks the checksums.
+    --
+    process( RST, CLKBUS(CKMASTER), READBIT )
+    begin
+        if RST = '1' then
+            RCV_CNT                                 <= (others => '0');
+            RCV_SEQ                                 <= "00";
+            RCV_ERROR                               <= '0';
+            RCV_STATE                               <= 0;
+            RCV_DONE                                <= '1';
+            RCV_BLOCK                               <= 0;
+            RCV_BYTE_AVAIL                          <= '0';
+            RCV_BYTE                                <= (others => '0');
+            RCV_SR                                  <= (others => '0');
+            RCV_CHECKSUM                            <= (others => '0');
+            TMH_CNT                                 <= 0;
+            TML_CNT                                 <= 0;
+            DATA_CNT                                <= (others => '0');
+            SPC_CNT                                 <= 0;
+            BIT_CNT                                 <= (others => '0');
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                -- Sample incoming bit and hold. Detect when a valid transmission starts.
+                RCV_SEQ(0)                              <= RCV_SEQ(1);
+                RCV_SEQ(1)                              <= READBIT;
+    
+                -- Clear byte available flag?
+                --
+                if RCV_BYTE_CLR = '1' then
+                    RCV_BYTE_AVAIL                      <= '0';
+                end if;
+    
+                -- Countdown measurement timer until till we reach 0 to take a sample.
+                if RCV_CNT > 0 then
+                    RCV_CNT                             <= RCV_CNT - 1;
+                end if;
+    
+                -- If external request made to read a tape block, sample the parameters and set the state machine running.
+                -- Same is applicable for a clear, when we receive the clear, reload the parameters and run from start.
+                --
+                if RCV_LOAD = '1' or RCV_CLR = '1' then
+                    RCV_DONE                            <= '0';
+                    RCV_CNT                             <= (others => '0');
+                    RCV_SEQ                             <= (others => '0');
+                    RCV_ERROR                           <= '0';
+                    if RCV_CLR = '1' then
+                        RCV_STATE                       <= 0;
+                    else
+                        RCV_STATE                       <= 1;
+                    end if;
+                    RCV_BLOCK                           <= 0;
+                    TMH_CNT                             <= RCV_TMH_CNT;
+                    TML_CNT                             <= RCV_TML_CNT;
+                    DATA_CNT                            <= RCV_DATASIZE;
+                    SPC_CNT                             <= 256;                 -- 256 short pulses (0) between data blocks.
+                    BIT_CNT                             <= "111";               -- 7 .. 0 = 8 bits
+                    RCV_BYTE_AVAIL                      <= '0';
+                    RCV_BYTE                            <= (others => '0');
+                    RCV_SR                              <= (others => '0');
+                    RCV_CHECKSUM                        <= (others => '0');
+                end if;
+    
+                -- A rising edge on the incoming data line indicates the start of data. We measure in from this edge the following
+                -- amount of time, then sample the bit as the 'read' value.
+                --
+                if RCV_SEQ = "10" then
+                    -- Pulse periods for MZ80C type machines
+                    if CONFIG(MZ_KC) = '1' or CONFIG(MZ_A) = '1' then
+                        RCV_CNT                         <= to_unsigned(736, 16);     -- 368uS @ 2Mhz
+                    elsif CONFIG(MZ700) = '1' then
+                        RCV_CNT                         <= to_unsigned(1302, 16);    -- 368uS @ 3.54MHz
+                    else
+                        RCV_CNT                         <= to_unsigned(1020, 16);    -- 255uS @ 4MHz
+                    end if;
+                end if;
+    
+                -- Sample bit and set flag.
+                if RCV_CNT = 1 then
+    
+                    -- State machine clocked by reception of bits.
+                    --
+                    case RCV_STATE is
+    
+                        -- Parking state.
+                        when 0  =>
+                            RCV_STATE                   <= 0;
+    
+                        -- Long or Short Gap. Actual number is not so important as some bits can be lost on initial startup. 
+                        -- The purpose of the gap is to synchronise and we use it to fine tune our sampling.
+                        when 1  =>
+                            if READBIT = '1' then
+                                RCV_STATE               <= 2;
+                                TMH_CNT                 <= TMH_CNT - 1;
+                            end if;
+    
+                        -- Long or Short Tape Mark part 1.
+                        when 2  =>
+                            if TMH_CNT > 0 and READBIT = '1' then
+                                TMH_CNT                 <= TMH_CNT - 1;
+                                if TMH_CNT = 1 then
+                                    RCV_STATE           <= 3;
+                                end if;
+                            elsif READBIT = '0' then
+                                RCV_ERROR               <= '1';
+                                RCV_STATE               <= 0;
+                            end if;
+    
+                        -- Long or Short Tape Mark part 2.
+                        when 3  =>
+                            if TML_CNT > 0 and READBIT = '0' then
+                                TML_CNT                 <= TML_CNT - 1;
+                                if TML_CNT = 1 then
+                                    RCV_STATE           <= 4;
+                                end if;
+                            elsif READBIT = '1' then
+                                RCV_ERROR               <= '1';
+                                RCV_STATE               <= 0;
+                            end if;
+    
+                        -- Single long pulse.
+                        when 4  =>
+                            if READBIT = '1' then
+                                RCV_CHECKSUM            <= (others => '0');
+                                RCV_STATE               <= 5;
+                            else
+                                RCV_ERROR               <= '1';
+                                RCV_STATE               <= 0;
+                            end if;
+    
+                        -- Each byte is preceded by a single long pulse.
+                        when 5  =>
+                            if READBIT = '1' then
+                                RCV_STATE               <= 6;
+                            else
+                                RCV_ERROR               <= '1';
+                                RCV_STATE               <= 0;
+                            end if;
+    
+                        -- Store 1 bit.
+                        when 6 =>
+                            -- Count each 1 as sum represents the checksum.
+                            if READBIT = '1' and DATA_CNT > 2 then
+                                RCV_CHECKSUM            <= RCV_CHECKSUM + 1;
+                            end if;
+                            RCV_SR                      <= RCV_SR(6 downto 0) & READBIT;
+                            BIT_CNT                     <= BIT_CNT - 1;
+    
+                            -- If this was the last bit, make byte available and then move to next state.
+                            if BIT_CNT = "000" then
+                                RCV_BYTE                <= RCV_SR(6 downto 0) & READBIT;
+                                RCV_BYTE_AVAIL          <= '1';
+                                DATA_CNT                <= DATA_CNT - 1;
+    
+                                -- All bytes been received?
+                                if DATA_CNT = 1 then
+                                    RCV_STATE           <= 8;
+                                else
+                                    RCV_STATE           <= 5;       -- Back to get next byte.
+                                end if;
+                            end if;
+    
+                        when 7 =>
+    
+                        -- Single long pulse.
+                        when 8 =>
+                            if READBIT = '1' then
+                                -- If this is the second copy received, then finish.
+                                if RCV_BLOCK = 1 then
+                                    RCV_STATE           <= 0;
+                                    RCV_DONE            <= '1';
+                                else
+                                    RCV_STATE           <= 9;
+                                end if;
+                            else
+                                RCV_ERROR               <= '1';
+                                RCV_STATE               <= 9;       -- Bit is less important, flag the error but assembler can check the checksum to verify.
+                            end if;
+    
+                        -- 256 Short padding block to seperate the data blocks.
+                        when 9 =>
+                            if SPC_CNT > 0 and READBIT = '0' then
+                                SPC_CNT                 <= SPC_CNT - 1;
+    
+                                -- Last space byte, move to next block receipt.
+                                if SPC_CNT = 1 then
+                                    RCV_BLOCK           <= 1;
+                                    DATA_CNT            <= RCV_DATASIZE;
+                                    RCV_STATE           <= 5;   -- Go back to retrieve second copy.
+                                end if;
+                            elsif READBIT = '1' then
+                                RCV_ERROR               <= '1';
+                                RCV_STATE               <= 0;
+                            end if;
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -----------------------------------------------------------------------------------------------------------------------------------------
+    ---------------------------------------- Write to MZ (Playback from Tape) logic ---------------------------------------------------------
+    -----------------------------------------------------------------------------------------------------------------------------------------
+
+    ----------------------------------------------------------------------------------------------------------------------
+    -- Read From Tape logic (write to MZ).
+    -- Definitions: Read  = Read from virtual tape (RAM).
+    --              Write = Write into virtual tape (RAM).
+    --              Xmit  = Transmit from CMT to MZ.
+    --              Rcv   = Receive from MZ into CMT.
+    --              Thus you read Read from tape and transmit to MZ, or Receive from MZ and write onto virtual tape.
+    --              Playing is when the CMT is reading from tape, Recording is when the CMT is writing to tape.
+    --
+    -- This block concentrates all the logic required to deliver data from RAM (virtual tape) to the MZ.
+    -- Viewed from the CMT, it is the transmission of data from tape to computer.
+    ----------------------------------------------------------------------------------------------------------------------
+
+    -- State machine to represent the tape drive READ mode (RAM -> MZ) using cache memory as the tape, which is populated by the HPS.
+    --
+    process( RST, CLKBUS(CKMASTER), PLAYING ) begin
+        -- For reset, hold machine in reset.
+        if RST = '1' then 
+            PLAY_READY_CLR                          <= '0';
+            PLAY_READY_CLR_CNT                      <= (others => '0');
+            TAPE_READ_STATE                         <=  0;
+            TAPE_READ_SEQ                           <= "000";
+            XMIT_PADDING_LOAD                       <= '0';
+            XMIT_RAM_LOAD                           <= '0';
+            XMIT_RAM_TYPE                           <= '0';
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                -- 2 second after the tape motor goes off clear the PLAY_READY signal, indicating cache tape is no
+                -- longer in use.
+                --
+                if PLAY_READY_CLR_CNT = X"1EFFFF" then
+                    PLAY_READY_CLR                      <= '1';
+    
+                -- A short time after activation (22 bits expiration), clear the reset signal so as to allow
+                -- further loads to take place.
+                --
+                elsif PLAY_READY_CLR_CNT = X"1FFFFF" then
+                    PLAY_READY_CLR_CNT                  <= (others => '0');
+                    PLAY_READY_CLR                      <= '0';
+                end if;
+    
+                -- If the PLAY_READY reset timer is running (> 0), increment until we reach timeout.
+                --
+                if PLAY_READY_CLR_CNT > 0 then
+                    PLAY_READY_CLR_CNT                  <= PLAY_READY_CLR_CNT + 1;
+                end if;
+                
+                -- If playing has been suspended, on 3rd clock determine the next state, setup and clear necessary signals.
+                if PLAYING = "001" then
+                    XMIT_PADDING_LOAD                   <= '0';
+                    XMIT_RAM_LOAD                       <= '0';
+                    PLAY_READY_CLR_CNT                  <= to_unsigned(1, 22);
+    
+                    -- If the data block was received on first attempt, MZ will stop the motor, so skip the second block.
+                    if XMIT_RAM_TYPE = '0' and TAPE_READ_STATE > 6 and TAPE_READ_STATE < 15 then
+                        TAPE_READ_STATE                 <= 14;
+                    else
+                        TAPE_READ_STATE                 <= 15;
+                    end if;
+    
+                -- Change in play state, start fsm to play out the ram contents when the HPS upload has completed.
+                elsif PLAYING = "110" then
+                    if TAPE_READ_STATE = 15 then
+                        TAPE_READ_STATE                 <= 0;
+                        XMIT_RAM_TYPE                   <= '0';
+                    end if;
+                    PLAY_READY_CLR_CNT                  <= (others => '0');
+    
+                -- If playing, run the FSM.
+                elsif PLAYING = "111" then
+                    
+                    -- Sample the done signal, when setup and stable, we can continue.
+                    TAPE_READ_SEQ(1 downto 0)           <= TAPE_READ_SEQ(2 downto 1);
+                    TAPE_READ_SEQ(2)                    <= (XMIT_PADDING_LOAD or XMIT_RAM_LOAD) and (XMIT_PADDING_DONE and XMIT_RAM_DONE);
+    
+                    -- If a transmission has just been started and acknowledged by the DONE flag being reset, reset the activation strobe.
+                    --
+                    if TAPE_READ_SEQ(0) = '1' then
+                        XMIT_PADDING_LOAD               <= '0';
+                        XMIT_RAM_LOAD                   <= '0';
+                    end if;
+    
+                    -- If a transmission is in progress, run the FSM.
+                    --
+                    if XMIT_PADDING_LOAD = '0' and XMIT_RAM_LOAD = '0' then
+    
+                        -- Default is to move onto next state per clock cycle, unless modified by the state action.
+                        TAPE_READ_STATE                 <= TAPE_READ_STATE + 1;
+    
+                        -- Execute current state.
+                        case TAPE_READ_STATE is
+    
+                        -- Section 1 - Header
+                            --
+                            when 0 => 
+                                -- Header = 0, Data = 1
+                                if XMIT_RAM_TYPE = '0' then
+                                    -- Setup to send a Long Gap.
+                                    if CONFIG(MZ_80C) = '1' or CONFIG(MZ700) = '1' then
+                                        XMIT_PADDING_CNT1<= 22000;
+                                    else
+                                        XMIT_PADDING_CNT1<= 10000;
+                                    end if;
+                                else
+                                    if CONFIG(MZ_80C) = '1' or CONFIG(MZ700) = '1' then
+                                        XMIT_PADDING_CNT1<= 11000;
+                                    else
+                                        XMIT_PADDING_CNT1<= 10000;
+                                    end if;
+                                end if;
+                                XMIT_PADDING_LEVEL1     <= '0';                     -- Short Pulses
+                                XMIT_PADDING_CNT2       <= 0;
+                                XMIT_PADDING_LEVEL2     <= '0';
+                                XMIT_PADDING_LOAD       <= '1';
+        
+                            when 1 =>
+                                -- Wait for the padding transmission to complete.
+                                if XMIT_PADDING_DONE = '0' then
+                                    TAPE_READ_STATE     <= 1;
+                                end if;
+        
+                            when 2 =>
+                                -- Header = 0, Data = 1
+                                if XMIT_RAM_TYPE = '0' then
+                                    -- Setup to send a Long Tape Mark.
+                                    XMIT_PADDING_CNT1   <= 40;
+                                    XMIT_PADDING_CNT2   <= 40;
+                                else
+                                    -- Setup to send a Short Tape Mark.
+                                    XMIT_PADDING_CNT1   <= 20;
+                                    XMIT_PADDING_CNT2   <= 20;
+                                end if;
+                                XMIT_PADDING_LEVEL1     <= '1';                     -- Long Pulses
+                                XMIT_PADDING_LEVEL2     <= '0';                     -- Short Pulses
+                                XMIT_PADDING_LOAD       <= '1';
+        
+                            when 3 =>
+                                if XMIT_PADDING_DONE = '0' then
+                                    TAPE_READ_STATE     <= 3;
+                                end if;
+        
+                            when 4 =>
+                                -- Setup to send a Long Pulse.
+                                XMIT_PADDING_CNT1       <= 1;
+                                XMIT_PADDING_LEVEL1     <= '1';                     -- Long Pulse
+                                XMIT_PADDING_CNT2       <= 0;
+                                XMIT_PADDING_LEVEL2     <= '0';
+                                XMIT_PADDING_LOAD       <= '1';
+        
+                            when 5 =>
+                                if XMIT_PADDING_DONE = '0' then
+                                    TAPE_READ_STATE     <= 5;
+                                end if;
+        
+                            -- Send the header and checksum for header.
+                            when 6 =>
+                                XMIT_RAM_LOAD           <= '1';                     -- Send First copy of header/data.
+        
+                            when 7 =>
+                                if XMIT_RAM_DONE = '0' then                        -- If first copy successfully received, MZ will issue a motor stop.
+                                    TAPE_READ_STATE     <= 7;
+                                end if;
+        
+                            when 8 =>
+                                -- Setup to send 256 short pulse padding.
+                                XMIT_PADDING_CNT1       <= 256;
+                                XMIT_PADDING_LEVEL1     <= '0';
+                                XMIT_PADDING_CNT2       <= 0;
+                                XMIT_PADDING_LEVEL2     <= '0';
+                                XMIT_PADDING_LOAD       <= '1';
+        
+                            when 9 =>
+                                if XMIT_PADDING_DONE = '0' then
+                                    TAPE_READ_STATE     <= 9;
+                                end if;
+        
+                            -- Resend the header/data as backup copy.
+                            when 10 => 
+                                XMIT_RAM_LOAD           <= '1';                     -- If required, send second copy of header/data.
+        
+                            when 11 =>
+                                if XMIT_RAM_DONE = '0' then
+                                    TAPE_READ_STATE     <= 11;
+                                end if;
+        
+                            when 12 =>
+                                -- Setup to send a Long Pulse.
+                                XMIT_PADDING_CNT1       <= 1;
+                                XMIT_PADDING_LEVEL1     <= '1';
+                                XMIT_PADDING_CNT2       <= 0;
+                                XMIT_PADDING_LEVEL2     <= '0';
+                                XMIT_PADDING_LOAD       <= '1';
+        
+                            when 13 =>
+                                if XMIT_PADDING_DONE = '0' then
+                                    TAPE_READ_STATE     <= 13;
+                                end if;
+            
+                            -- Switch to data if we have just transmitted the header, else terminate the process.
+                            when 14 => 
+                                if XMIT_RAM_TYPE = '0' then
+                                    XMIT_RAM_TYPE       <= '1';
+                                    TAPE_READ_STATE     <= 0;
+                                end if;
+        
+                            -- Clear the Play Ready strobe and wait at this state until external actions reset the state.
+                            when 15 =>
+                                TAPE_READ_STATE         <= 15;
+                        end case;
+                end if;
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Process to read the tape data blocks and checksum from RAM and transmit it to the MZ.
+--
+-- The ram is serialised and written to the MZ. A checksum (count of 1's) is calculated and transmitted 
+-- immediately after the data.
+-- XMIT_READ_DONE is high when the tape header and checksum transmission are complete.
+-- Normally, XMIT_RAM_LOAD is asserted high and then wait until XMIT_DONE goes high, finally deassert XMIT_RAM_LOAD to low.
+--
+-- XMIT_LOAD_2        =           = Load signal to commence bit transmission.
+-- XMIT_BIT_2         =           = Input into bit transmitter of bit value to be sent. 
+-- XMIT_RAM_DONE      =           = Transmission of RAM block complete (= 1).
+-- XMIT_RAM_TYPE      =           = 0 - Header, 1 = Data
+-- XMIT_RAM_ADDR      =           = Address of the RAM to be transmitted. RAM can be header or data ram block
+-- XMIT_RAM_COUNT     =           = Count of bytes to be sent, 0 = end.
+-- XMIT_RAM_CHECKSUM  =           = Sum of number of 1's transmitted.
+-- XMIT_RAM_STATE     =           = State machine current state.
+-- CLKBUS(CKMASTER)   =           = Base clock for encoding/decoding of pwm pulse.
+--
+process( RST, CLKBUS(CKMASTER), XMIT_RAM_LOAD, XMIT_RAM_TYPE ) begin
+    if RST = '1' then
+         XMIT_RAM_DONE                              <= '1';                                  -- Default state is DONE, data transmitted. Set to 0 when transmission in progress.
+         XMIT_LOAD_2                                <= '0';                                  -- LOAD signal to the bit writer. 1 = start bit transmission.
+         --
+         XMIT_BIT_2                                 <= '0';                                  -- Level of bit to transmit.
+         XMIT_RAM_ADDR                              <= std_logic_vector(to_unsigned(0, 16)); -- Address of cache memory for next byte.
+         XMIT_RAM_COUNT                             <= to_unsigned(0, 16);                   -- Count of bytes to transmit, excludes checksum.
+         XMIT_RAM_CHKSUM_CNT                        <= to_unsigned(0, 2);                    -- Count of checksum bytes to transmit.
+         XMIT_RAM_CHECKSUM                          <= std_logic_vector(to_unsigned(0, 16)); -- Calculated checksum, count of all 1's in data bytes.
+         XMIT_RAM_STATE                             <= 0;                                    -- FSM state.
+         XMIT_RAM_SEQ                               <= "000";
+
+    elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
+
+        if CLKBUS(CKENCPU) = '1' then
+
+            -- Sample load signal and hold. Shift right 3 bits, msb = latest value.
+            XMIT_RAM_SEQ(1 downto 0)                    <= XMIT_RAM_SEQ(2 downto 1);
+            XMIT_RAM_SEQ(2)                             <= XMIT_RAM_LOAD;
+    
+            -- If load is stable, acknowledge by bringing DONE low and start process.
+            if XMIT_RAM_SEQ = "111" then
+                XMIT_RAM_DONE                           <= '0';
+    
+            -- When XMIT_RAM_LOAD is asserted and setled, sample parameters, set address and count for the given ram block and commence serialisation.
+            --
+            elsif XMIT_RAM_SEQ = "110" then
+                 if XMIT_RAM_TYPE = '0' then
+                     XMIT_RAM_COUNT                     <= to_unsigned(128, 16);
+                 else
+                     XMIT_RAM_COUNT                     <= XMIT_TAPE_SIZE;
+                 end if;
+                 XMIT_RAM_CHKSUM_CNT                    <= to_unsigned(1, 2);
+                 XMIT_RAM_ADDR                          <= std_logic_vector(to_unsigned(0, 16));
+                 XMIT_RAM_CHECKSUM                      <= std_logic_vector(to_unsigned(0, 16));
+                 XMIT_RAM_STATE                         <= 1;
+                 XMIT_LOAD_2                            <= '0';
+    
+            -- If the DONE signal is low, then run the actual process, raising DONE when complete.
+            elsif XMIT_RAM_DONE = '0' then
+    
+                -- Simple FSM to implement transmission of RAM contents according to MZ Tape Protocol.
+                case(XMIT_RAM_STATE) is
+                    when 0 => 
+                    when 1 =>
+                        XMIT_RAM_BIT_CNT                <= 8;      -- 9 bits to transmit, pre 1 + 8 bits of data byte.
+                        XMIT_RAM_STATE                  <= 3;
+    
+                        if XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT = 1 then
+                            XMIT_RAM_SR                 <= '1' & XMIT_RAM_CHECKSUM(15 downto 8);
+                        elsif XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT = 0 then
+                            XMIT_RAM_SR                 <= '1' & XMIT_RAM_CHECKSUM(7 downto 0);
+                        else
+                            -- Extract the size of the tape data block and the load address if this is the header.
+                            --
+                            if XMIT_RAM_TYPE = '0' then
+                                if XMIT_RAM_ADDR = 18 then 
+                                    XMIT_TAPE_SIZE(7 downto 0)  <= unsigned(HDR_RAM_DATAOUT);
+                                elsif XMIT_RAM_ADDR = 19 then
+                                    XMIT_TAPE_SIZE(15 downto 8) <= unsigned(HDR_RAM_DATAOUT);
+                                -- If enabled, convert the filename to sharp ascii.
+                                elsif CONFIG(MZ_80C) = '1' and CONFIG(CMTASCII_OUT) = '1' and XMIT_RAM_ADDR >= std_logic_vector(to_unsigned(1, 9)) and XMIT_RAM_ADDR <= std_logic_vector(to_unsigned(17,9)) then
+                                    XMIT_ASCII_RAM_ADDR <= '1' & HDR_RAM_DATAOUT;
+                                    XMIT_RAM_STATE      <= 2;    
+                                end if;
+                                XMIT_RAM_SR             <= '1' & HDR_RAM_DATAOUT;
+                            else
+                                XMIT_RAM_SR             <= '1' & DATA_RAM_DATAOUT;
+                            end if;
+                        end if;
+                    -- Byte to be output is mapped via the Sharp Ascii <-> Ascii lookup table.
+                    when 2 =>
+                            XMIT_RAM_SR                 <= '1' & ASCII_RAM_DATAOUT;
+                            XMIT_RAM_STATE              <= 3;
+                    when 3 =>
+                        XMIT_BIT_2                      <= XMIT_RAM_SR(8);
+                        XMIT_LOAD_2                     <= '1';
+                        if XMIT_RAM_SR(8) = '1' and XMIT_RAM_BIT_CNT < 8 and XMIT_RAM_COUNT > 0 then
+                            XMIT_RAM_CHECKSUM           <= XMIT_RAM_CHECKSUM + 1;
+                        end if;
+                        XMIT_RAM_SR                     <= XMIT_RAM_SR(7 downto 0) & '0';
+                        XMIT_RAM_STATE                  <= 4;
+                    when 4 => 
+                        -- As we are using the same clock freq, need to wait until XMIT_DONE is set to 0, indicating transmission in progress.
+                        if XMIT_LOAD_2 = '1' and XMIT_DONE = '0' then
+                            XMIT_LOAD_2                 <= '0';
+                            XMIT_RAM_STATE              <= 5;
+                        end if;
+                    when 5 =>
+                        -- Wait until the DONE signal is asserted before continuing.
+                        if XMIT_DONE = '1' then
+                            XMIT_RAM_STATE              <= 6;
+                        end if;
+                    when 6 =>
+                        XMIT_BIT_2                      <= '0';                   -- Reset bit..
+                        if XMIT_RAM_BIT_CNT = 0 then
+                            if XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT = 0 then
+                                XMIT_RAM_STATE          <= 7;
+                            else
+                                if XMIT_RAM_COUNT > 0 then
+                                    XMIT_RAM_COUNT      <= XMIT_RAM_COUNT - 1;
+                                    XMIT_RAM_ADDR       <= XMIT_RAM_ADDR + 1;
+                                elsif XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT > 0 then
+                                    XMIT_RAM_CHKSUM_CNT <= XMIT_RAM_CHKSUM_CNT - 1;
+                                end if;
+                                XMIT_RAM_STATE          <= 1;
+                            end if;
+                        else
+                            XMIT_RAM_BIT_CNT            <= XMIT_RAM_BIT_CNT - 1;
+                            XMIT_RAM_STATE              <= 3;
+                        end if;
+                    when others => XMIT_RAM_DONE        <= '1';
+                end case;
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Process to send padding from CMT to MZ.
+--
+-- This process transmits a set of pulses to represent the Gap, Tape Mark, Short Seperator or Long pulse of an MZ tape
+-- message. XMIT_PADDING_LOAD when high starts the generation, XMIT_PADDING_DONE is set high when generation completes.
+-- Normally, the invoker process sets up the number of bits and level in the parameters:
+
+-- XMIT_PADDING_CNT1   = Internal = If > 0, then transmit this number of bits first.
+-- XMIT PADDING_LEVEL1 = Internal = Level of the bit to transmit CNT1 times.
+-- XMIT PADDING_CNT2   = Internal = If > 0, then tramsit this number of bits second.
+-- XMIT_PADDING_LEVEL2 = Internal = Level of the bit to transmit CNT2 times.
+--
+-- After completion of transmission, the Done signal is asserted high:
+-- XMIT_PADDING_DONE   = Internal = 0 when transmission in progress, 1 when transmission completed.
+--
+-- Clocks:
+-- CLKBUS(CKMASTER)    = Internal = Base clock for encoding/decoding of pwm pulse.
+--
+process( RST, CLKBUS(CKMASTER), XMIT_PADDING_LOAD ) begin
+    if RST = '1' then
+         XMIT_PADDING_DONE                          <= '1';          -- PADDING transmission complete signal, DONE = 1 when complete, 0 during transmit.
+         XMIT_LOAD_1                                <= '0';          -- LOAD signal to bit transmitted, loads required bit when = 1 for 1 cycle. 
+         PADDING_CNT1                               <= 0;
+         PADDING_LEVEL1                             <= '0';
+         PADDING_CNT2                               <= 0;
+         PADDING_LEVEL2                             <= '0';
+         PADDING_SEQ                                <= "000";
+
+    elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
+
+        if CLKBUS(CKENCPU) = '1' then
+
+            -- Sample load signal and hold. Shift right 3 bits, msb = latest value.
+            PADDING_SEQ(1 downto 0)                     <= PADDING_SEQ(2 downto 1);
+            PADDING_SEQ(2)                              <= XMIT_PADDING_LOAD;
+    
+            -- If LOAD active for 3 periods, bring DONE low to acknowledge LOAD signal and start processing.
+            --
+            if PADDING_SEQ = "111" then
+                XMIT_PADDING_DONE                       <= '0';
+            end if;
+    
+            -- If LOAD active for 2 periods, sample and store the provided parameters.
+            --
+            if PADDING_SEQ = "110" then
+                -- Sample the parameters XMIT_PADDING_CNT1, XMIT_PADDING_CNT2, XMIT_PADDING_LEVEL1, XMIT_PADDING_LEVEL2 and
+                -- write out the number of Level1 @ Cnt1, Level2 @ Cnt2 bits.
+                PADDING_CNT1                            <= XMIT_PADDING_CNT1;
+                PADDING_LEVEL1                          <= XMIT_PADDING_LEVEL1;
+                PADDING_CNT2                            <= XMIT_PADDING_CNT2;
+                PADDING_LEVEL2                          <= XMIT_PADDING_LEVEL2;
+                XMIT_LOAD_1                             <= '0';
+            end if;
+    
+            -- If DONE is low, we are processing.
+            if XMIT_PADDING_DONE = '0' then
+    
+                -- Reset strobe when acknowledged by XMIT_DONE going low.
+                if XMIT_LOAD_1 = '1' and XMIT_DONE = '0' then
+                    XMIT_LOAD_1                         <= '0';
+    
+                -- If we arent loading a padding sequence, then we are either waiting for a Done signal 
+                -- or need to commence a new transmission.
+                --
+                elsif XMIT_LOAD_1 = '0' then
+    
+                    -- If transmission buffer empty, setup next bit to transmit.
+                    --
+                    if XMIT_DONE = '1' then
+    
+                        -- Set the completion flag if the counters expire or PLAYING is disabled.
+                        --.
+                        if PLAYING = "000" or (PADDING_CNT1 = 0 and PADDING_CNT2 = 0) then
+                            -- Final wait for done on the last bit before setting our done flag.
+                            XMIT_PADDING_DONE           <= '1';
+    
+                        -- First, transmit the nummber of Counter 1 bits defined in Level 1.
+                        elsif PADDING_CNT1 > 0 then
+                            XMIT_BIT_1                  <= PADDING_LEVEL1;    -- Set the mux input bit according to input level, 
+                            XMIT_LOAD_1                 <= '1';               -- Set the mux input to commence xmit.
+                            PADDING_CNT1                <= PADDING_CNT1 - 1;  -- Decrement counter as this bit is now being transmitted.
+        
+                        -- Then transmit the number of Counter 2 bits defined in Level 2.
+                        elsif PADDING_CNT2 > 0 then
+                            XMIT_BIT_1                  <= PADDING_LEVEL2;   
+                            XMIT_LOAD_1                 <= '1';
+                            PADDING_CNT2                <= PADDING_CNT2 - 1;
+                        end if;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Process to write a bit (PWM encode) to the MZ input.
+-- The timings are as follows with a default SCLK of 2MHz. For faster operation, MZ clock is boosted
+-- and the SCLK is also boosted on a 1:1 relationship, thus the dividers are halved per boost.
+--
+-- XMIT_LOAD_1     = FROM TAPE = When high, Bit available on XMIT_BIT_1 to encode and transmit to MZ.
+-- XMIT_LOAD_2     = FROM TAPE = When high, Bit available on XMIT_BIT_2 to encode and transmit to MZ.
+-- XMIT_DONE       = TO TAPE   = When high, transmission of bit complete. Resets to 0 on active XMIT_LOAD signal.
+-- WRITEBIT        = FROM MZ   = Encoded bit tranmitted to MZ.
+-- CLKBUS(CKMASTER)=           = Base clock for encoding/decoding of pwm pulse.
+--
+-- Machine          Time uS   Description         N-80K(CKMEM)   N-80K(CPU)   N-700(CPU)     N-700(CKMEM)
+--  MZ80KCA/700     464.00    Long Pulse Start    1856            928          1624           3248
+--                  494.00    Long Pulse End      1976            988          1729           3458
+--                  240.00    Short Pulse Start    960            480           840           1680
+--                  264.00    Short Pulse End     1056            528           924           1848
+--                  368.00    Read point.         1472            736          1288           2576
+--  MZ80B           333.00    Long Pulse Start    2664           1332
+--                  334.00    Long Pulse End      2672           1336
+--                  166.75    Short Pulse Start   1334            667
+--                  166.00    Short Pulse End     1328            664
+--                  255.00    Read point.         2040           1020
+--
+process( RST, CLKBUS(CKMASTER), XMIT_LOAD_1, XMIT_LOAD_2 ) begin
+    -- When RESET is high, hold in reset mode.
+    if RST = '1' then
+        XMIT_DONE                                   <= '1';                    -- Completion signal, 0 when transmitting, 1 when done.
+        WRITEBIT                                    <= '0';                    -- Bit facing towards MZ input.
+        XMIT_LIMIT                                  <= 0;                      -- End of pulse.
+        XMIT_COUNT                                  <= 0;                      -- Pulse start, bit set to 1, reset to 0 on counter = 0
+        XMIT_SEQ                                    <= "000";
+
+    elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
+
+        if CLKBUS(CKENCPU) = '1' then
+
+            -- Sample load signal and hold. Shift right 3 bits, msb = latest value.
+            XMIT_SEQ(1 downto 0)                        <= XMIT_SEQ(2 downto 1);
+            XMIT_SEQ(2)                                 <= XMIT_LOAD_1 or XMIT_LOAD_2;
+    
+            -- If load is stable, acknowledge by bringing DONE low and start process.
+            if XMIT_SEQ = "111" then
+                XMIT_DONE                               <= '0';
+                WRITEBIT                                <= '1';
+    
+            -- Store run values on 2nd clock cycle of LOAD being active.
+            elsif XMIT_SEQ = "110" then
+    
+                -- Pulse periods for MZ80C type machines
+                if CONFIG(MZ_KC) = '1' or CONFIG(MZ_A) = '1' then
+                    if (XMIT_LOAD_1 = '1' and XMIT_BIT_1 = '1') or (XMIT_LOAD_2 = '1' and XMIT_BIT_2 = '1') then
+                        XMIT_LIMIT                      <=  988;     --  1976;
+                        XMIT_COUNT                      <= -928;     -- -1856;
+                    else
+                        XMIT_LIMIT                      <=  528;     --  1056;
+                        XMIT_COUNT                      <= -480;     --  -960;
+                    end if;
+                elsif CONFIG(MZ700) = '1' then
+                -- Pulse periods for MZ700 type machines
+                    if (XMIT_LOAD_1 = '1' and XMIT_BIT_1 = '1') or (XMIT_LOAD_2 = '1' and XMIT_BIT_2 = '1') then
+                        XMIT_LIMIT                      <= 1729;     --  3458;
+                        XMIT_COUNT                      <= -1624;    -- -3248;
+                    else
+                        XMIT_LIMIT                      <=  924;     --  1848;
+                        XMIT_COUNT                      <= -840;     -- -1680;
+                    end if;
+                else
+                -- Pulse periods for MZ80B type machines
+                    if (XMIT_LOAD_1 = '1' and XMIT_BIT_1 = '1') or (XMIT_LOAD_2 = '1' and XMIT_BIT_2 = '1') then
+                        XMIT_LIMIT                      <=  1336;    --  2672;
+                        XMIT_COUNT                      <= -1332;    -- -2664;
+                    else
+                        XMIT_LIMIT                      <=  664;     --  1328;
+                        XMIT_COUNT                      <= -667;     -- -1334;
+                    end if;
+                end if;
+    
+            -- On expiration of timer, signal completion.
+            elsif XMIT_COUNT = XMIT_LIMIT then
+                XMIT_DONE                               <= '1';
+             
+            -- If the counter is running, format the output pulse.
+            elsif XMIT_COUNT /= XMIT_LIMIT then
+                -- At zero, we have elapsed the correct high period for the write bit, now bring it low for the remaining period.
+                if XMIT_COUNT = 0 then
+                    WRITEBIT                            <= '0';
+                end if;
+                XMIT_COUNT                              <= XMIT_COUNT + 1;
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Only enable debugging LEDS if enabled in the config package.
+--
+DEBUGCMT: if DEBUG_ENABLE = 1 generate
+    DEBUG_STATUS_LEDS(0)                            <= WRITEBIT;
+    DEBUG_STATUS_LEDS(1)                            <= XMIT_DONE;
+    DEBUG_STATUS_LEDS(2)                            <= XMIT_LOAD_1;
+    DEBUG_STATUS_LEDS(3)                            <= XMIT_LOAD_2;
+    DEBUG_STATUS_LEDS(4)                            <= XMIT_PADDING_LOAD;
+    DEBUG_STATUS_LEDS(5)                            <= XMIT_PADDING_DONE;
+    DEBUG_STATUS_LEDS(6)                            <= XMIT_RAM_LOAD;
+    DEBUG_STATUS_LEDS(7)                            <= XMIT_RAM_DONE;
+    
+    DEBUG_STATUS_LEDS(8)                            <= PLAY_READY;
+    DEBUG_STATUS_LEDS(9)                            <= PLAY_READY_CLR;
+    DEBUG_STATUS_LEDS(10)                           <= PLAYING(2);
+    DEBUG_STATUS_LEDS(11)                           <= PLAYING(1);
+    DEBUG_STATUS_LEDS(12)                           <= PLAYING(0);
+    DEBUG_STATUS_LEDS(13)                           <= '0';
+    DEBUG_STATUS_LEDS(14)                           <= '0';
+    DEBUG_STATUS_LEDS(15)                           <= RECORDING;
+    
+    DEBUG_STATUS_LEDS(16)                           <= READBIT;
+    DEBUG_STATUS_LEDS(17)                           <= RCV_ERROR;
+    DEBUG_STATUS_LEDS(18)                           <= '0';
+    DEBUG_STATUS_LEDS(19)                           <= RCV_CLR;
+    DEBUG_STATUS_LEDS(20)                           <= RCV_DONE;
+    DEBUG_STATUS_LEDS(21)                           <= RCV_LOAD;
+    DEBUG_STATUS_LEDS(22)                           <= RCV_BYTE_CLR;
+    DEBUG_STATUS_LEDS(23)                           <= RCV_BYTE_AVAIL;
+
+    DEBUG_STATUS_LEDS(24)                           <= CMT_BUS_IN(pkgs.mctrl_pkg.STOP);
+    DEBUG_STATUS_LEDS(25)                           <= CMT_BUS_IN(pkgs.mctrl_pkg.PLAY);
+    DEBUG_STATUS_LEDS(26)                           <= CMT_BUS_IN(pkgs.mctrl_pkg.SEEK);
+    DEBUG_STATUS_LEDS(27)                           <= CMT_BUS_IN(pkgs.mctrl_pkg.DIRECTION);
+    DEBUG_STATUS_LEDS(28)                           <= CMT_BUS_IN(pkgs.mctrl_pkg.EJECT);
+    DEBUG_STATUS_LEDS(29)                           <= CMT_BUS_IN(pkgs.mctrl_pkg.WRITEENABLE);
+    DEBUG_STATUS_LEDS(31 downto 30)                 <= CONFIG(BUTTONS);
+end generate;
+DEBUGCMT1: if DEBUG_ENABLE = 0 generate
+    DEBUG_STATUS_LEDS                               <= (others => '0');
+end generate;
+
+end RTL;
diff --git a/common/config_pkg.vhd b/common/config_pkg.vhd
new file mode 100644
index 0000000..e9475c2
--- /dev/null
+++ b/common/config_pkg.vhd
@@ -0,0 +1,34 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            config_pkg.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series compilation configuration parameters.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         September 2018   - Initial module written.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+package config_pkg is
+
+    constant DEBUG_ENABLE           : integer := 1;                      -- Enable debug logic,
+    constant NEO_ENABLE             : integer := 0;                      -- Enable local NEO430 IO processor,
+    constant STORM_ENABLE           : integer := 1;                      -- Enable local STORM IO processor,
+
+end config_pkg;
diff --git a/common/dpram.vhd b/common/dpram.vhd
new file mode 100644
index 0000000..e61f2ac
--- /dev/null
+++ b/common/dpram.vhd
@@ -0,0 +1,169 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            dpram.vhd
+-- Created:         July 2018
+-- Author(s):       Altera/Intel - refactored by Philip Smart
+-- Description:     Dual Port RAM as provided by Altera in the Megafunctions suite.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018   - Initial module written.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+    GENERIC
+    (
+        init_file                        : string                                         := "";
+        widthad_a                        : natural;
+        width_a                          : natural                                        := 8;
+        widthad_b                        : natural;
+        width_b                          : natural                                        := 8;
+--      clock_en_a                       : string                                         := "NORMAL";
+--      clock_en_b                       : string                                         := "NORMAL";
+        outdata_reg_a                    : string                                         := "UNREGISTERED";
+        outdata_reg_b                    : string                                         := "UNREGISTERED"
+    );
+    PORT
+    (
+        clock_a                          : IN STD_LOGIC;
+        clocken_a                        : IN STD_LOGIC                                   := '1';
+        address_a                        : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+        data_a                           : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+        wren_a                           : IN STD_LOGIC                                   := '1';
+        q_a                              : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+        clock_b                          : IN STD_LOGIC;
+        clocken_b                        : IN STD_LOGIC                                   := '1';
+        address_b                        : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
+        data_b                           : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
+        wren_b                           : IN STD_LOGIC                                   := '1';
+        q_b                              : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
+    );
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+    SIGNAL sub_wire0                     : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+    SIGNAL sub_wire1                     : STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
+
+    COMPONENT altsyncram
+    GENERIC (
+        address_reg_b                    : STRING;
+        clock_enable_input_a             : STRING;
+        clock_enable_input_b             : STRING;
+        clock_enable_output_a            : STRING;
+        clock_enable_output_b            : STRING;
+        indata_reg_b                     : STRING;
+        init_file                        : STRING;
+        intended_device_family           : STRING;
+        lpm_type                         : STRING;
+        numwords_a                       : NATURAL;
+        numwords_b                       : NATURAL;
+        operation_mode                   : STRING;
+        outdata_aclr_a                   : STRING;
+        outdata_aclr_b                   : STRING;
+        outdata_reg_a                    : STRING;
+        outdata_reg_b                    : STRING;
+        power_up_uninitialized           : STRING;
+        read_during_write_mode_port_a    : STRING;
+        read_during_write_mode_port_b    : STRING;
+        widthad_a                        : NATURAL;
+        widthad_b                        : NATURAL;
+        width_a                          : NATURAL;
+        width_b                          : NATURAL;
+        width_byteena_a                  : NATURAL;
+        width_byteena_b                  : NATURAL;
+        wrcontrol_wraddress_reg_b        : STRING
+    );
+    PORT (
+            clock0                       : IN  STD_LOGIC ;
+            clocken0                     : IN  STD_LOGIC ;
+            address_a                    : IN  STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+            data_a                       : IN  STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+            wren_a                       : IN  STD_LOGIC ;
+            q_a                          : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+            clock1                       : IN  STD_LOGIC ;
+            clocken1                     : IN  STD_LOGIC ;
+            address_b                    : IN  STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
+            data_b                       : IN  STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
+            wren_b                       : IN  STD_LOGIC ;
+            q_b                          : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+BEGIN
+    q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+    q_b    <= sub_wire1(width_b-1 DOWNTO 0);
+
+    altsyncram_component : altsyncram
+    GENERIC MAP (
+        address_reg_b                    => "CLOCK1",
+        clock_enable_input_a             => "NORMAL",
+        clock_enable_input_b             => "NORMAL",
+        clock_enable_output_a            => "BYPASS",
+        clock_enable_output_b            => "BYPASS",
+        indata_reg_b                     => "CLOCK1",
+        init_file                        => init_file,
+        intended_device_family           => "Cyclone V",
+        lpm_type                         => "altsyncram",
+        numwords_a                       => 2**widthad_a,
+        numwords_b                       => 2**widthad_b,
+        operation_mode                   => "BIDIR_DUAL_PORT",
+      --operation_mode                   => "ROM",
+        outdata_aclr_a                   => "NONE",
+        outdata_aclr_b                   => "NONE",
+        outdata_reg_a                    => outdata_reg_a,
+        outdata_reg_b                    => outdata_reg_b,
+        power_up_uninitialized           => "FALSE",
+        read_during_write_mode_port_a    => "NEW_DATA_NO_NBE_READ",
+        read_during_write_mode_port_b    => "NEW_DATA_NO_NBE_READ",
+        widthad_a                        => widthad_a,
+        widthad_b                        => widthad_b,
+        width_a                          => width_a,
+        width_b                          => width_b,
+        width_byteena_a                  => 1,
+        width_byteena_b                  => 1,
+        wrcontrol_wraddress_reg_b        => "CLOCK1"
+    )
+    PORT MAP (
+        clock0                           => clock_a,
+        clocken0                         => clocken_a,
+        address_a                        => address_a,
+        data_a                           => data_a,
+        wren_a                           => wren_a,
+        q_a                              => sub_wire0,
+
+        clock1                           => clock_b,
+        clocken1                         => clocken_b,
+        address_b                        => address_b,
+        wren_b                           => wren_b,
+        data_b                           => data_b,
+        q_b                              => sub_wire1
+    );
+
+
+
+END SYN;
diff --git a/common/dprom.vhd b/common/dprom.vhd
new file mode 100644
index 0000000..8591047
--- /dev/null
+++ b/common/dprom.vhd
@@ -0,0 +1,160 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            dprom.vhd
+-- Created:         July 2018
+-- Author(s):       Altera/Intel - refactored by Philip Smart
+-- Description:     Dual Port ROM as provided by Altera in the Megafunctions suite.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018   - Initial module written.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dprom IS
+    GENERIC
+    (
+        init_file                        : string := "";
+        widthad_a                        : natural;
+        width_a                          : natural := 8;
+        outdata_reg_a                    : string := "UNREGISTERED";
+        outdata_reg_b                    : string := "UNREGISTERED"
+    );
+    PORT
+    (
+        address_a                        : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+        clock_a                          : IN STD_LOGIC ;
+        data_a                           : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+        wren_a                           : IN STD_LOGIC;
+        q_a                              : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+        address_b                        : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+        clock_b                          : IN STD_LOGIC ;
+        data_b                           : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+        wren_b                           : IN STD_LOGIC;
+        q_b                              : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+    );
+END dprom;
+
+
+ARCHITECTURE SYN OF dprom IS
+
+    SIGNAL sub_wire0                     : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+    SIGNAL sub_wire1                     : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+    COMPONENT altsyncram
+    GENERIC (
+        address_reg_b                    : STRING;
+        clock_enable_input_a             : STRING;
+        clock_enable_input_b             : STRING;
+        clock_enable_output_a            : STRING;
+        clock_enable_output_b            : STRING;
+        indata_reg_b                     : STRING;
+        init_file                        : STRING;
+        intended_device_family           : STRING;
+        lpm_type                         : STRING;
+        numwords_a                       : NATURAL;
+        numwords_b                       : NATURAL;
+        operation_mode                   : STRING;
+        outdata_aclr_a                   : STRING;
+        outdata_aclr_b                   : STRING;
+        outdata_reg_a                    : STRING;
+        outdata_reg_b                    : STRING;
+        power_up_uninitialized           : STRING;
+        read_during_write_mode_port_a    : STRING;
+        read_during_write_mode_port_b    : STRING;
+        widthad_a                        : NATURAL;
+        widthad_b                        : NATURAL;
+        width_a                          : NATURAL;
+        width_b                          : NATURAL;
+        width_byteena_a                  : NATURAL;
+        width_byteena_b                  : NATURAL;
+        wrcontrol_wraddress_reg_b        : STRING
+    );
+    PORT (
+            address_a                    : IN  STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+            clock0                       : IN  STD_LOGIC ;
+            data_a                       : IN  STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+            wren_a                       : IN  STD_LOGIC ;
+            q_a                          : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+            address_b                    : IN  STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+            clock1                       : IN  STD_LOGIC ;
+            data_b                       : IN  STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+            wren_b                       : IN  STD_LOGIC ;
+            q_b                          : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+BEGIN
+    q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+    q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+
+    altsyncram_component : altsyncram
+    GENERIC MAP (
+        address_reg_b                    => "CLOCK1",
+        clock_enable_input_a             => "BYPASS",
+        clock_enable_input_b             => "BYPASS",
+        clock_enable_output_a            => "BYPASS",
+        clock_enable_output_b            => "BYPASS",
+        indata_reg_b                     => "CLOCK1",
+        init_file                        => init_file,
+        intended_device_family           => "Cyclone V",
+        lpm_type                         => "altsyncram",
+        numwords_a                       => 2**widthad_a,
+        numwords_b                       => 2**widthad_a,
+        operation_mode                   => "BIDIR_DUAL_PORT",
+      --operation_mode                   => "ROM",
+        outdata_aclr_a                   => "NONE",
+        outdata_aclr_b                   => "NONE",
+        outdata_reg_a                    => outdata_reg_a,
+        outdata_reg_b                    => outdata_reg_b,
+        power_up_uninitialized           => "FALSE",
+        read_during_write_mode_port_a    => "NEW_DATA_NO_NBE_READ",
+        read_during_write_mode_port_b    => "NEW_DATA_NO_NBE_READ",
+        widthad_a                        => widthad_a,
+        widthad_b                        => widthad_a,
+        width_a                          => width_a,
+        width_b                          => width_a,
+        width_byteena_a                  => 1,
+        width_byteena_b                  => 1,
+        wrcontrol_wraddress_reg_b        => "CLOCK1"
+    )
+    PORT MAP (
+        address_a                        => address_a,
+        clock0                           => clock_a,
+        data_a                           => data_a,
+        wren_a                           => wren_a,
+        q_a                              => sub_wire0,
+
+        address_b                        => address_b,
+        clock1                           => clock_b,
+        data_b                           => data_b,
+        wren_b                           => wren_b,
+        q_b                              => sub_wire1
+    );
+
+
+
+END SYN;
diff --git a/common/functions.vhd b/common/functions.vhd
new file mode 100644
index 0000000..0b20016
--- /dev/null
+++ b/common/functions.vhd
@@ -0,0 +1,65 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            functions.vhd
+-- Created:         October 2018
+-- Author(s):       Philip Smart
+-- Description:     Collection of re-usable functions for the SharpMZ Project.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         October 2018   - Initial module written.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+library IEEE;
+library pkgs;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package functions_pkg is
+
+  -- Function to reverse the order of the bits in a standard logic vector.
+  -- ie. 1010 becomes 0101
+  function reverse_vector(slv:std_logic_vector) return std_logic_vector; 
+
+  -- Function to convert an integer (0 or 1) into std_logic.
+  --
+  function to_std_logic(i : in integer) return std_logic;
+
+end functions_pkg;
+
+package body functions_pkg is
+
+    function reverse_vector(slv:std_logic_vector) return std_logic_vector is 
+       variable target : std_logic_vector(slv'high downto slv'low); 
+    begin 
+      for idx in slv'high downto slv'low loop 
+        target(idx) := slv(slv'low + (slv'high-idx)); 
+      end loop; 
+      return target; 
+    end reverse_vector;
+
+    function to_std_logic(i : in integer) return std_logic is
+    begin
+      if i = 0 then
+        return '0';
+      end if;
+      return '1';
+    end function;
+
+end functions_pkg;
diff --git a/common/i8254/i8254.vhd b/common/i8254/i8254.vhd
new file mode 100644
index 0000000..f8a48fd
--- /dev/null
+++ b/common/i8254/i8254.vhd
@@ -0,0 +1,214 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            i8254.vhd
+-- Created:         November 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series i8254 Timer
+--                  This module emulates the Intel i8254 Programmable Interval Timer.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         November 2018 - Initial write.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity i8254 is
+    Port (
+        RST                  : in  std_logic;
+        CLK                  : in  std_logic;
+        ENA                  : in  std_logic;
+        A                    : in  std_logic_vector(1 downto 0);
+        DI                   : in  std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        CS_n                 : in  std_logic;
+        WR_n                 : in  std_logic;
+        RD_n                 : in  std_logic;
+        --
+        CLK0                 : in  std_logic;
+        GATE0                : in  std_logic;
+        OUT0                 : out std_logic;
+        CLK1                 : in  std_logic;
+        GATE1                : in  std_logic;
+        OUT1                 : out std_logic;
+        CLK2                 : in  std_logic;
+        GATE2                : in  std_logic;
+        OUT2                 : out std_logic
+    );
+end i8254;
+
+architecture Behavioral of i8254 is
+
+signal WREN                  : std_logic;
+signal RDEN                  : std_logic;
+signal WRCTRLEN              : std_logic;
+signal WR0                   : std_logic;
+signal WR1                   : std_logic;
+signal WR2                   : std_logic;
+signal RD0                   : std_logic;
+signal RD1                   : std_logic;
+signal RD2                   : std_logic;
+signal DO0                   : std_logic_vector(7 downto 0);
+signal DO1                   : std_logic_vector(7 downto 0);
+signal DO2                   : std_logic_vector(7 downto 0);
+signal LDO0                  : std_logic_vector(7 downto 0);
+signal LDO1                  : std_logic_vector(7 downto 0);
+signal LDO2                  : std_logic_vector(7 downto 0);
+signal READDATA_NEXT         : std_logic_vector(7 downto 0);
+signal CTRLM0                : std_logic;
+signal CTRLM1                : std_logic;
+signal CTRLM2                : std_logic;
+signal LATCNT0               : std_logic;
+signal LATCNT1               : std_logic;
+signal LATCNT2               : std_logic;
+signal LATSTS0               : std_logic;
+signal LATSTS1               : std_logic;
+signal LATSTS2               : std_logic;
+
+component i8254_counter
+    Port (
+        CLK                  : in  std_logic;
+        RESET                : in  std_logic;
+        --
+        DATA_IN              : in  std_logic_vector(7 downto 0);
+        DATA_OUT             : out std_logic_vector(7 downto 0);
+        WRITE                : in  std_logic;
+        READ                 : in  std_logic;
+        CTRL_MODE_EN         : in  std_logic;
+        LATCH_COUNT_EN       : in  std_logic;
+        LATCH_STATUS_EN      : in  std_logic;
+        --
+        CTR_CLK              : in  std_logic;
+        CTR_GATE             : in  std_logic;
+        CTR_OUT              : out std_logic
+    );
+end component;
+
+begin
+
+    -- Create signals to select a given register for read or write.
+    --
+    WREN     <= '1' when ENA = '1' and CS_n = '0' and WR_n = '0'
+                else '0';
+    RDEN     <= '1' when ENA = '1' and CS_n = '0' and RD_n = '0'
+                else '0';
+    WRCTRLEN <= '1' when WREN = '1' and A    = "11"
+                else '0';
+    WR0      <= '1' when WREN = '1' and A = "00" 
+                else '0';
+    WR1      <= '1' when WREN = '1' and A = "01"
+                else '0';
+    WR2      <= '1' when WREN = '1' and A = "10"
+                else '0';
+    RD0      <= '1' when RDEN = '1' and A = "00"
+                else '0';
+    RD1      <= '1' when RDEN = '1' and A = "01"
+                else '0';
+    RD2      <= '1' when RDEN = '1' and A = "10"
+                else '0';
+
+    -- Create signals to enable setting of a command, a count value or latching status per counter.
+    --
+    CTRLM0   <= '1' when WRCTRLEN = '1' and   DI(7 downto 6) = "00" and DI(5 downto 4) /= "00"
+                else '0';
+    CTRLM1   <= '1' when WRCTRLEN = '1' and   DI(7 downto 6) = "01" and DI(5 downto 4) /= "00"
+                else '0';
+    CTRLM2   <= '1' when WRCTRLEN = '1' and   DI(7 downto 6) = "10" and DI(5 downto 4) /= "00"
+                else '0';
+    LATCNT0  <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "00" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(1) = '1'))
+                else '0';
+    LATCNT1  <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "01" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(2) = '1'))
+                else '0';
+    LATCNT2  <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "10" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(3) = '1'))
+                else '0';
+    LATSTS0  <= '1' when WRCTRLEN = '1' and   DI(7 downto 6) = "11" and DI(4) = '0' and DI(1) = '1'
+                else '0';
+    LATSTS1  <= '1' when WRCTRLEN = '1' and   DI(7 downto 6) = "11" and DI(4) = '0' and DI(2) = '1'
+                else '0';
+    LATSTS2  <= '1' when WRCTRLEN = '1' and   DI(7 downto 6) = "11" and DI(4) = '0' and DI(3) = '1'
+                else '0';
+ 
+    -- Assign the counter whose address is active. Not permissible to read back control register.
+    --
+    DO       <= DO0 when A = "00"
+                else
+                DO1 when A = "01"
+                else
+                DO2 when A = "10"
+                else
+                (others => '0');
+
+
+    -- Instantiate the 3 counters within the 8254.
+    --
+    CTR0 : i8254_counter port map (
+        CLK                  => CLK,
+        RESET                => RST,
+        --
+        DATA_IN              => DI,
+        DATA_OUT             => DO0,
+        WRITE                => WR0,
+        READ                 => RD0,
+        CTRL_MODE_EN         => CTRLM0,
+        LATCH_COUNT_EN       => LATCNT0, 
+        LATCH_STATUS_EN      => LATSTS0, 
+        --
+        CTR_CLK              => CLK0,
+        CTR_GATE             => GATE0,
+        CTR_OUT              => OUT0
+    );
+
+    CTR1 : i8254_counter port map (
+        CLK                  => CLK,
+        RESET                => RST,
+        --
+        DATA_IN              => DI,
+        DATA_OUT             => DO1,
+        WRITE                => WR1,
+        READ                 => RD1,
+        CTRL_MODE_EN         => CTRLM1, 
+        LATCH_COUNT_EN       => LATCNT1,
+        LATCH_STATUS_EN      => LATSTS1,
+        --
+        CTR_CLK              => CLK1,
+        CTR_GATE             => GATE1,
+        CTR_OUT              => OUT1
+    );
+
+    CTR2 : i8254_counter port map (
+        CLK                  => CLK,
+        RESET                => RST,
+        --
+        DATA_IN              => DI,
+        DATA_OUT             => DO2,
+        WRITE                => WR2,
+        READ                 => RD2,
+        CTRL_MODE_EN         => CTRLM2,
+        LATCH_COUNT_EN       => LATCNT2,
+        LATCH_STATUS_EN      => LATSTS2,
+        --
+        CTR_CLK              => CLK2,
+        CTR_GATE             => GATE2,
+        CTR_OUT              => OUT2
+    );
+
+
+end Behavioral;
diff --git a/common/i8254/i8254_counter.vhd b/common/i8254/i8254_counter.vhd
new file mode 100644
index 0000000..0406a99
--- /dev/null
+++ b/common/i8254/i8254_counter.vhd
@@ -0,0 +1,523 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            i8254_counter.vhd
+-- Created:         November 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series i8254 Timer
+--                  This module emulates the Intel i8254 Programmable Interval Timer.
+--
+-- Credits:         Based on Verilog pit_counter by Aleksander Osman, 2014.
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         November 2018 - Initial write.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity i8254_counter is
+    Port (
+        CLK                  : in  std_logic;
+        RESET                : in  std_logic;
+        --
+        DATA_IN              : in  std_logic_vector(7 downto 0);
+        DATA_OUT             : out std_logic_vector(7 downto 0);
+        WRITE                : in  std_logic;
+        READ                 : in  std_logic;
+        CTRL_MODE_EN         : in  std_logic;
+        LATCH_COUNT_EN       : in  std_logic;
+        LATCH_STATUS_EN      : in  std_logic;
+        --
+        CTR_CLK              : in  std_logic;
+        CTR_GATE             : in  std_logic;
+        CTR_OUT              : out std_logic
+    );
+end i8254_counter;
+
+architecture Behavioral of i8254_counter is
+
+subtype LSB is integer range 7 downto 0;
+subtype MSB is integer range 15 downto 8;
+
+signal MODE                  : std_logic_vector(2 downto 0);
+signal RW_MODE               : std_logic_vector(1 downto 0);
+signal BCD                   : std_logic;
+signal REGISTER_IN           : std_logic_vector(15 downto 0);
+signal REGISTER_OUT          : std_logic_vector(15 downto 0);
+signal REGISTER_OUT_LATCHED  : std_logic;
+signal NULL_COUNTER          : std_logic;
+signal MSB_WRITE             : std_logic;
+signal MSB_READ              : std_logic;
+signal STATUS                : std_logic_vector(7 downto 0);
+signal STATUS_LATCHED        : std_logic;
+--
+signal CLOCK_LAST            : std_logic;
+signal CLOCK_PULSE           : std_logic;
+signal GATE_LAST             : std_logic;
+signal GATE_SAMPLED          : std_logic;
+signal TRIGGER               : std_logic;
+signal TRIGGER_SAMPLED       : std_logic;
+signal WRITTEN               : std_logic;
+signal LOADED                : std_logic;
+signal CTR_OUTi              : std_logic;
+--
+signal MODE0                 : std_logic;
+signal MODE1                 : std_logic;
+signal MODE2                 : std_logic;
+signal MODE3                 : std_logic;
+signal MODE4                 : std_logic;
+signal MODE5                 : std_logic;
+signal LOAD                  : std_logic;
+signal LOAD_MODE0            : std_logic;
+signal LOAD_MODE1            : std_logic;
+signal LOAD_MODE2            : std_logic;
+signal LOAD_MODE3            : std_logic;
+signal LOAD_MODE4            : std_logic;
+signal LOAD_MODE5            : std_logic;
+signal LOAD_EVEN             : std_logic;
+signal ENABLE_MODE0          : std_logic;
+signal ENABLE_MODE1          : std_logic;
+signal ENABLE_MODE2          : std_logic;
+signal ENABLE_MODE3          : std_logic;
+signal ENABLE_MODE4          : std_logic;
+signal ENABLE_MODE5          : std_logic;
+signal ENABLE_DOUBLE         : std_logic;
+signal ENABLE                : std_logic;
+signal BCD_DIGIT_1           : std_logic_vector(3 downto 0);
+signal BCD_DIGIT_2           : std_logic_vector(3 downto 0);
+signal BCD_DIGIT_3           : std_logic_vector(3 downto 0);
+signal COUNTER_MINUS_1       : std_logic_vector(15 downto 0);
+signal COUNTER_MINUS_2       : std_logic_vector(15 downto 0);
+signal COUNTER               : std_logic_vector(15 downto 0);
+
+begin
+
+    -- Control register settings. A write to the control register sets up the mode of this counter, wether it 
+    -- uses BCD or 16 bit binary and how the data is accessed, ie. LSB, MSB or both.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            MODE                     <= "010";
+            BCD                      <= '0';
+            RW_MODE                  <= "01";
+        elsif CLK'event and CLK = '1' then
+            if CTRL_MODE_EN = '1' then
+                MODE                 <= DATA_IN(3 downto 1);
+                BCD                  <= DATA_IN(0);
+                RW_MODE              <= DATA_IN(5 downto 4);
+            end if;
+        end if;
+    end process;
+
+    -- Staging counter loading. Depending on the mode, the byte is stored in the LSB, NSB or according to the write flag
+    -- for 16 bit mode. The staging counter is used to load the main counter.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            REGISTER_IN              <= (others => '0');
+
+        elsif CLK'event and CLK = '1' then
+
+            if CTRL_MODE_EN = '1' then
+                REGISTER_IN          <= (others => '0');
+            elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '0' then
+                REGISTER_IN(LSB)     <= DATA_IN;
+            elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '1' then
+                REGISTER_IN(MSB)     <= DATA_IN;
+            elsif WRITE = '1' and RW_MODE = "01" then
+                REGISTER_IN(LSB)     <= DATA_IN;
+            elsif WRITE = '1' and RW_MODE = "10" then
+                REGISTER_IN(MSB)     <= DATA_IN;
+            end if;
+        end if;
+    end process;
+
+    -- Store the counter contents on every clock until a latch request is made, then we suspend storing
+    -- until data is read.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            REGISTER_OUT             <= (others => '0');
+        elsif CLK'event and CLK = '1' then
+
+            -- Store each clock cycle, stop on the clock between LATCH going active and REGISTER_OUT_LATCHED going active.
+            --
+            if LATCH_COUNT_EN = '1' and REGISTER_OUT_LATCHED = '0' then
+                REGISTER_OUT         <= COUNTER(15 downto 0);
+            elsif REGISTER_OUT_LATCHED = '0' then
+                REGISTER_OUT         <= COUNTER(15 downto 0);
+            end if;
+        end if;
+    end process;
+
+    -- Set the output latched signal if LATCH_COUNT_EN goes high, this will stop the storing of the counter until
+    -- output latch is cleared, which can be done by a control register access or a 1/2 byte read depending on mode.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            REGISTER_OUT_LATCHED     <= '0';
+        elsif CLK'event and CLK = '1' then
+            if CTRL_MODE_EN = '1' then
+                REGISTER_OUT_LATCHED <= '0';
+            elsif LATCH_COUNT_EN = '1' then
+                REGISTER_OUT_LATCHED <= '1';
+            elsif (READ = '1' and (RW_MODE /= "11" or MSB_READ = '1')) then
+                REGISTER_OUT_LATCHED <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- Status flag null count - indicates if the counter can be read (0) or it is being loaded (1).
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            NULL_COUNTER             <= '0';
+        elsif CLK'event and CLK = '1' then
+            if CTRL_MODE_EN = '1' then
+                NULL_COUNTER         <= '1';
+            elsif (WRITE = '1' and (RW_MODE /= "11" or MSB_WRITE = '1')) then
+                NULL_COUNTER         <= '1';
+            elsif LOAD = '1' then
+                NULL_COUNTER         <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- Double byte handling for 16 bit load and fetch. An access to the control register resets the flag,
+    -- but on each write or read it gets toggled. The flag indicates wether the LSB(0) or MSB(1) is being read or writted.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            MSB_WRITE                <= '0';
+            MSB_READ                 <= '0';
+        elsif CLK'event and CLK = '1' then
+            if CTRL_MODE_EN = '1' then
+                MSB_WRITE            <= '0';
+                MSB_READ             <= '0';
+            elsif WRITE = '1' and RW_MODE = "11" then
+                MSB_WRITE            <= not MSB_WRITE;
+            elsif READ = '1' and RW_MODE = "11" then
+                MSB_READ             <= not MSB_READ;
+            end if;
+        end if;
+    end process;
+
+    -- Status register, contains the Output pin value, the state on the counter being read (1 = can be read) and the programmed
+    -- mode of the counter. The current values are latched during the clock between the LATCH_STATUS_EN going active and the latched
+    -- signal going active.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            STATUS                   <= (others => '0');
+        elsif CLK'event and CLK = '1' then
+            if LATCH_STATUS_EN = '1' and STATUS_LATCHED = '0' then
+                STATUS               <= CTR_OUTi & NULL_COUNTER & RW_MODE & MODE & BCD;
+            end if;
+        end if;
+    end process;
+
+    -- Set the status latch signal if the LATCH_STATUS_EN goes active. Any read or control mode access resets the flag.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            STATUS_LATCHED           <= '0';
+        elsif CLK'event and CLK = '1' then
+            if CTRL_MODE_EN = '1' then
+                STATUS_LATCHED       <= '0';
+            elsif LATCH_STATUS_EN = '1' then
+                STATUS_LATCHED       <= '1';
+            elsif READ = '1' then
+                STATUS_LATCHED       <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- Set the internal counter signals according to the output clock and gate.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            CLOCK_PULSE              <= '0';
+            CLOCK_LAST               <= '0';
+            GATE_LAST                <= '1';
+            GATE_SAMPLED             <= '0';
+            TRIGGER                  <= '0';
+            TRIGGER_SAMPLED          <= '0';
+        elsif CLK'event and CLK = '1' then
+            CLOCK_LAST               <= CTR_CLK;
+            GATE_LAST                <= CTR_GATE;
+
+            if CLOCK_LAST = '1' and CTR_CLK = '0' then
+                CLOCK_PULSE          <= '1';
+            else
+                CLOCK_PULSE          <= '0';
+            end if;
+
+            if CLOCK_LAST = '0' and CTR_CLK = '1' then
+                GATE_SAMPLED         <= CTR_GATE;
+                TRIGGER_SAMPLED      <= TRIGGER;
+            end if;
+
+            if GATE_LAST = '0' and CTR_GATE = '1' then
+                TRIGGER              <= '1';
+            elsif CLOCK_LAST = '0' and CTR_CLK = '1' then
+                TRIGGER              <= '0';
+            end if;
+
+        end if;
+    end process;
+
+    -- Set the counter output according to programmed mode and events.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            CTR_OUTi                 <= '1';
+        elsif CLK'event and CLK = '1' then
+
+            if    CTRL_MODE_EN = '1' then
+                if MODE0 = '1' then
+                    CTR_OUTi         <= '0';
+                elsif MODE1 = '1' or MODE2 = '1' or MODE3 = '1' or MODE4 = '1' or MODE5 = '1' then
+                    CTR_OUTi         <= '1';
+                end if;
+
+            elsif MODE0 = '1' then
+                if WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '0' then
+                    CTR_OUTi     <= '0';
+                elsif WRITTEN = '1' then
+                    CTR_OUTi     <= '0';
+                elsif COUNTER = "0000000000000001" and ENABLE = '1' then
+                    CTR_OUTi     <= '1';
+                end if;
+
+            elsif MODE1 = '1' then
+                if LOAD = '1' then
+                    CTR_OUTi     <= '0';
+                elsif COUNTER = "0000000000000001" and ENABLE = '1' then
+                    CTR_OUTi     <= '1';
+                end if;
+
+            elsif MODE2 = '1' then
+                if CTR_GATE = '0' then
+                    CTR_OUTi     <= '1';
+                elsif COUNTER = "0000000000000010" and ENABLE = '1' then
+                    CTR_OUTi     <= '0';
+                elsif LOAD = '1' then
+                    CTR_OUTi     <= '1';
+                end if;
+
+            elsif MODE3 = '1' then
+                if CTR_GATE = '0' then
+                    CTR_OUTi     <= '1';
+                elsif LOAD = '1' and COUNTER = "000000000000010" and CTR_OUTi = '1' and REGISTER_IN(0) = '0' then
+                    CTR_OUTi     <= '0';
+                elsif LOAD = '1' and COUNTER = "000000000000000" and CTR_OUTi = '1' and REGISTER_IN(0) = '1' then
+                    CTR_OUTi     <= '0';
+                elsif LOAD = '1' then
+                    CTR_OUTi     <= '1';
+                end if;
+
+            elsif MODE4 = '1' then
+                if LOAD = '1' then
+                    CTR_OUTi     <= '1';
+                elsif COUNTER = "0000000000000010" and ENABLE = '1' then
+                    CTR_OUTi     <= '0';
+                elsif COUNTER = "0000000000000001" and ENABLE = '1' then
+                    CTR_OUTi     <= '1';
+                end if;
+
+            elsif MODE5 = '1' then
+                if    COUNTER = "0000000000000010" and ENABLE = '1' then
+                    CTR_OUTi     <= '0';
+                elsif COUNTER = "0000000000000001" and ENABLE = '1' then
+                    CTR_OUTi     <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Setup flags to indicate if the counter has been written to or loaded. These flags then determine loading operation
+    -- of the staging counter into the counter.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            WRITTEN                  <= '0';
+            LOADED                   <= '0';
+        elsif CLK'event and CLK = '1' then
+            if CTRL_MODE_EN = '1' then
+                WRITTEN              <= '0';
+            elsif WRITE = '1' and RW_MODE /= "11" then
+                WRITTEN              <= '1';
+            elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '1' then
+                WRITTEN              <= '1';
+            elsif LOAD = '1' then
+                WRITTEN              <= '0';
+            end if;
+
+            if CTRL_MODE_EN = '1' then
+                LOADED               <= '0';
+            elsif LOAD = '1' then
+                LOADED               <= '1';
+            end if;
+        end if;
+    end process;
+
+    -- Process to present the requested data, according to mode, to the uC. The data is latched for timing delay to allow the uC
+    -- more time to read the byte.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            DATA_OUT                 <= (others => '0');
+        elsif CLK'event and CLK = '1' then
+            if STATUS_LATCHED = '1' then
+                DATA_OUT             <= STATUS;
+            elsif RW_MODE = "11" and MSB_READ = '0' then
+                DATA_OUT             <= REGISTER_OUT(LSB);
+            elsif RW_MODE = "11" and MSB_READ = '1' then
+                DATA_OUT             <= REGISTER_OUT(MSB);
+            elsif RW_MODE = "01" then
+                DATA_OUT             <= REGISTER_OUT(LSB);
+            else
+                DATA_OUT             <= REGISTER_OUT(MSB);
+            end if;
+        end if;
+    end process;
+
+    -- Load up the primary counter according to the programmed mode and load signals coming from the uC.
+    --
+    process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            COUNTER                  <= (others => '1');
+        elsif CLK'event and CLK = '1' then
+            if LOAD_EVEN = '1' then
+                COUNTER              <= REGISTER_IN(15 downto 1) & '0';
+            elsif LOAD = '1' then
+                COUNTER              <= REGISTER_IN;
+            elsif ENABLE_DOUBLE = '1' then
+                COUNTER              <= COUNTER_MINUS_2;
+            elsif ENABLE = '1' then
+                COUNTER              <= COUNTER_MINUS_1;
+            end if;
+        end if;
+    end process;
+
+
+    -- Quick reference signals to indicate programmed mode.
+    --
+    MODE0        <= '1' when MODE = "000"
+                    else '0';
+    MODE1        <= '1' when MODE = "001"
+                    else '0';
+    MODE2        <= '1' when MODE(1 downto 0) = "10"
+                    else '0';
+    MODE3        <= '1' when MODE(1 downto 0) = "11"
+                    else '0';
+    MODE4        <= '1' when MODE = "100"
+                    else '0';
+    MODE5        <= '1' when MODE = "101"
+                    else '0';
+
+    -- Quick reference signals to indicate a load is required for a given mode.
+    --
+    LOAD_MODE0   <= '1' when MODE0 = '1' and WRITTEN = '1'
+                    else '0';
+    LOAD_MODE1   <= '1' when MODE1 = '1' and WRITTEN = '1' and TRIGGER_SAMPLED = '1'
+                    else '0';
+    LOAD_MODE2   <= '1' when MODE2 = '1' and (WRITTEN = '1' or TRIGGER_SAMPLED = '1' or (LOADED = '1' and GATE_SAMPLED = '1' and COUNTER = "0000000000000001"))
+                    else '0';
+    LOAD_MODE3   <= '1' when MODE3 = '1' and (WRITTEN = '1' or TRIGGER_SAMPLED = '1' or (LOADED = '1' and GATE_SAMPLED = '1' and ((COUNTER = "0000000000000010" and (REGISTER_IN(0) = '0' or CTR_OUTi = '0')) or (COUNTER = "0000000000000000" and REGISTER_IN(0) = '1' and CTR_OUTi = '1')))) 
+                    else '0';
+    LOAD_MODE4   <= '1' when MODE4 = '1' and WRITTEN = '1'
+                    else '0';
+    LOAD_MODE5   <= '1' when MODE5 = '1' and (WRITTEN = '1' or LOADED = '1') and TRIGGER_SAMPLED = '1'
+                    else '0';
+
+    -- Quick reference signals to indicate a programmed mode can be enabled and set running.
+    --
+    ENABLE_MODE0 <= '1' when MODE0 = '1' and GATE_SAMPLED = '1' and MSB_WRITE = '0'
+                    else '0';
+    ENABLE_MODE1 <= '1' when MODE1 = '1'
+                    else '0';
+    ENABLE_MODE2 <= '1' when MODE2 = '1' and GATE_SAMPLED = '1'
+                    else '0';
+    ENABLE_MODE3 <= '1' when MODE3 = '1' and GATE_SAMPLED = '1'
+                    else '0';
+    ENABLE_MODE4 <= '1' when MODE4 = '1' and GATE_SAMPLED = '1'
+                    else '0';
+    ENABLE_MODE5 <= '1' when MODE5 = '1'
+                    else '0';
+
+    -- Signals to indicate the type of data to be loaded into the primary counter according to programmed mode.
+    --
+    LOAD         <= '1' when CLOCK_PULSE = '1' and (LOAD_MODE0 = '1' or LOAD_MODE1 = '1' or LOAD_MODE2 = '1' or LOAD_MODE3 = '1' or LOAD_MODE4 = '1' or LOAD_MODE5 = '1')
+                    else '0';
+    LOAD_EVEN    <= '1' when LOAD = '1' and MODE3 = '1' 
+                    else '0';
+    ENABLE       <= '1' when LOAD = '0' and LOADED = '1' and CLOCK_PULSE = '1' and (ENABLE_MODE0 = '1' or ENABLE_MODE1 = '1' or ENABLE_MODE2 = '1' or ENABLE_MODE4 = '1' or ENABLE_MODE5 = '1')
+                    else '0';
+    ENABLE_DOUBLE<= '1' when LOAD = '0' and LOADED = '1' and CLOCK_PULSE = '1' and ENABLE_MODE3 = '1'
+                    else '0';
+
+
+    -- BCD logic. Calculate each digit to ease the main 
+    BCD_DIGIT_3  <= COUNTER(15 downto 12) - X"1";
+    BCD_DIGIT_2  <= COUNTER(11 downto 8)  - X"1";
+    BCD_DIGIT_1  <= COUNTER(7  downto 4)  - X"1";
+
+    -- Count down of the primary counter, 1 clock at a time. If we are in BCD mode, adjust count to reflect the BCD value, otherwise make
+    -- a normal binary countdown.
+    --
+    COUNTER_MINUS_1 <= X"9999"                                     when BCD = '1' and COUNTER = X"0000"
+                      else
+                      BCD_DIGIT_3 & X"999"                        when BCD = '1' and COUNTER(11 downto 0) = X"000"
+                      else
+                      COUNTER(15 downto 12) & BCD_DIGIT_2 & X"99" when BCD = '1' and COUNTER(7 downto 0) = X"00"
+                      else
+                      COUNTER(15 downto 8) & BCD_DIGIT_1 & X"9"   when BCD = '1' and COUNTER(3 downto 0) = X"0"
+                      else
+                      COUNTER - X"0001";
+
+    -- Count down evenly. Same as above but we count down 2 clocks at a time.
+    --
+    COUNTER_MINUS_2 <= X"9998"                                     when BCD = '1' and COUNTER = X"0000"
+                       else
+                       BCD_DIGIT_3 & X"998"                        when BCD = '1' and COUNTER(11 downto 0) = X"000"
+                       else
+                       COUNTER(15 downto 12) & BCD_DIGIT_2 & X"98" when BCD = '1' and COUNTER(7 downto 0) = X"00"
+                       else
+                       COUNTER(15 downto 8) & BCD_DIGIT_1 & X"8"   when BCD = '1' and COUNTER(3 downto 0) = X"0"
+                       else
+                       COUNTER - X"0002";
+
+    -- Counter output.
+    --
+    CTR_OUT      <= CTR_OUTi;
+end Behavioral;
diff --git a/common/i8255/i8255.vhd b/common/i8255/i8255.vhd
new file mode 100644
index 0000000..dc86541
--- /dev/null
+++ b/common/i8255/i8255.vhd
@@ -0,0 +1,715 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            i8255.vhd
+-- Created:         Feb 2007
+-- Author(s):       MikeJ (fpgaarcade), refactored and adapted for this emulation by Philip Smart
+-- Description:     Sharp MZ series i8255 PPI
+--                  This module emulates the Intel i8255 Programmable Peripheral Interface chip.
+--
+-- Credits:         
+-- Copyright:       (c) MikeJ - Feb 2007
+--
+-- History:         July 2018   - Initial module refactored and updated for this emulation.
+--
+---------------------------------------------------------------------------------------------------------
+--
+-- Original copyright notice below:-
+--
+-- A simulation model of i8255 PIA
+-- Copyright (c) MikeJ - Feb 2007
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+---------------------------------------------------------------------------------------------------------
+
+library ieee ;
+  use ieee.std_logic_1164.all ;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity i8255 is
+    port (
+        RESET                : in    std_logic;
+        CLK                  : in    std_logic;
+        ENA                  : in    std_logic;                    -- (CPU) clk enable
+        ADDR                 : in    std_logic_vector(1 downto 0); -- A1-A0
+        DI                   : in    std_logic_vector(7 downto 0); -- D7-D0
+        DO                   : out   std_logic_vector(7 downto 0);
+
+        CS_n                 : in    std_logic;
+        RD_n                 : in    std_logic;
+        WR_n                 : in    std_logic;
+    
+        PA_I                 : in    std_logic_vector(7 downto 0);
+        PA_O                 : out   std_logic_vector(7 downto 0);
+        PA_O_OE_n            : out   std_logic_vector(7 downto 0);
+    
+        PB_I                 : in    std_logic_vector(7 downto 0);
+        PB_O                 : out   std_logic_vector(7 downto 0);
+        PB_O_OE_n            : out   std_logic_vector(7 downto 0);
+    
+        PC_I                 : in    std_logic_vector(7 downto 0);
+        PC_O                 : out   std_logic_vector(7 downto 0);
+        PC_O_OE_n            : out   std_logic_vector(7 downto 0)
+    );
+end;
+
+architecture RTL of i8255 is
+
+    -- registers
+    signal BIT_MASK          : std_logic_vector(7 downto 0);
+    signal R_PORTA           : std_logic_vector(7 downto 0);
+    signal R_PORTB           : std_logic_vector(7 downto 0);
+    signal R_PORTC           : std_logic_vector(7 downto 0);
+    signal R_CONTROL         : std_logic_vector(7 downto 0);
+    --
+    signal PORTA_WE          : std_logic;
+    signal PORTB_WE          : std_logic;
+    signal PORTA_RE          : std_logic;
+    signal PORTB_RE          : std_logic;
+    --
+    signal PORTA_WE_T1       : std_logic;
+    signal PORTB_WE_T1       : std_logic;
+    signal PORTA_RE_T1       : std_logic;
+    signal PORTB_RE_T1       : std_logic;
+    --
+    signal PORTA_WE_RISING   : boolean;
+    signal PORTB_WE_RISING   : boolean;
+    signal PORTA_RE_RISING   : boolean;
+    signal PORTB_RE_RISING   : boolean;
+    --
+    signal GROUPA_MODE       : std_logic_vector(1 downto 0); -- port a/c upper
+    signal GROUPB_MODE       : std_logic;                    -- port b/c lower
+    --
+    signal PORTA_READ        : std_logic_vector(7 downto 0);
+    signal PORTB_READ        : std_logic_vector(7 downto 0);
+    signal PORTC_READ        : std_logic_vector(7 downto 0);
+    signal CONTROL_READ      : std_logic_vector(7 downto 0);
+    signal MODE_CLEAR        : std_logic;
+    --
+    signal A_INTE1           : std_logic;
+    signal A_INTE2           : std_logic;
+    signal B_INTE            : std_logic;
+    --
+    signal A_INTR            : std_logic;
+    signal A_OBF_L           : std_logic;
+    signal A_IBF             : std_logic;
+    signal A_ACK_L           : std_logic;
+    signal A_STB_L           : std_logic;
+    signal A_ACK_L_T1        : std_logic;
+    signal A_STB_L_T1        : std_logic;
+    --
+    signal B_INTR            : std_logic;
+    signal B_OBF_L           : std_logic;
+    signal B_IBF             : std_logic;
+    signal B_ACK_L           : std_logic;
+    signal B_STB_L           : std_logic;
+    signal B_ACK_L_T1        : std_logic;
+    signal B_STB_L_T1        : std_logic;
+    --
+    signal A_ACK_L_RISING    : boolean;
+    signal A_STB_L_RISING    : boolean;
+    signal B_ACK_L_RISING    : boolean;
+    signal B_STB_L_RISING    : boolean;
+    --
+    signal PORTA_IPREG       : std_logic_vector(7 downto 0);
+    signal PORTB_IPREG       : std_logic_vector(7 downto 0);
+begin
+    --
+    -- mode 0     - basic input/output
+    -- mode 1     - strobed input/output
+    -- mode 2/3 - bi-directional bus
+    --
+    -- control word (write)
+    --
+    -- D7        mode set flag                1 = active
+    -- D6..5 GROUPA mode selection (mode 0,1,2)
+    -- D4        GROUPA porta                 1 = input, 0 = output
+    -- D3        GROUPA portc upper     1 = input, 0 = output
+    -- D2        GROUPB mode selection (mode 0 ,1)
+    -- D1        GROUPB portb                 1 = input, 0 = output
+    -- D0        GROUPB portc lower     1 = input, 0 = output
+    --
+    -- D7        bit set/reset                0 = active
+    -- D6..4 x
+    -- D3..1 bit select
+    -- d0        1 = set, 0 - reset
+    --
+    -- all output registers including status are reset when mode is changed
+    --    1. Port A:
+    --    All Modes: Output data is cleared, input data is not cleared.
+
+    --    2. Port B:
+    --    Mode 0: Output data is cleared, input data is not cleared.
+    --    Mode 1 and 2: Both output and input data are cleared.
+
+    --    3. Port C:
+    --    Mode 0:Output data is cleared, input data is not cleared.
+    --    Mode 1 and 2: IBF and INTR are cleared and OBF# is set.
+    --    Outputs in Port C which are not used for handshaking or interrupt signals are cleared.
+    --    Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled.
+
+    P_BIT_MASK : process(DI)
+    begin
+        BIT_MASK                            <= x"01";
+        case DI(3 downto 1) is
+            when "000"  => BIT_MASK         <= x"01";
+            when "001"  => BIT_MASK         <= x"02";
+            when "010"  => BIT_MASK         <= x"04";
+            when "011"  => BIT_MASK         <= x"08";
+            when "100"  => BIT_MASK         <= x"10";
+            when "101"  => BIT_MASK         <= x"20";
+            when "110"  => BIT_MASK         <= x"40";
+            when "111"  => BIT_MASK         <= x"80";
+            when others => null;
+        end case;
+    end process;
+
+    P_WRITE_REG_RESET : process(RESET, CLK)
+        variable R_PORTC_masked : std_logic_vector(7 downto 0);
+        variable R_PORTC_setclr : std_logic_vector(7 downto 0);
+    begin
+        if (RESET = '1') then
+            R_PORTA                         <= x"00";
+            R_PORTB                         <= x"00";
+            R_PORTC                         <= x"00";
+            R_CONTROL                       <= x"9B"; -- 10011011
+            MODE_CLEAR                      <= '1';
+
+        elsif CLK'event and CLK = '1' then
+
+            R_PORTC_masked := (not BIT_MASK) and R_PORTC;
+            for i in 0 to 7 loop
+                R_PORTC_setclr(i) := BIT_MASK(i) and DI(0);
+            end loop;
+
+            if (ENA = '1') then
+                MODE_CLEAR                  <= '0';
+                if (CS_n = '0') and (WR_n = '0') then
+                    case ADDR is
+                        when "00" => R_PORTA<= DI;
+                        when "01" => R_PORTB<= DI;
+                        when "10" => R_PORTC<= DI;
+
+                        when "11" =>
+                            if (DI(7) = '0') then -- set/clr
+                                R_PORTC     <= R_PORTC_masked or R_PORTC_setclr;
+                            else
+                                --MODE_CLEAR <= '1';
+                                --R_PORTA        <= x"00";
+                                --R_PORTB        <= x"00"; -- clear port b input reg
+                                --R_PORTC        <= x"00"; -- clear control sigs
+                                R_CONTROL   <= DI; -- load new mode
+                            end if;
+                        when others => null;
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    P_DECODE_CONTROL : process(R_CONTROL)
+    begin
+        GROUPA_MODE                         <= R_CONTROL(6 downto 5);
+        GROUPB_MODE                         <= R_CONTROL(2);
+    end process;
+
+    P_READ : process(ADDR, PORTA_READ, PORTB_READ, PORTC_READ, CONTROL_READ)
+    begin
+        DO <= x"00"; -- default
+        --if (CS_n = '0') and (RD_n = '0') then -- not required
+            case ADDR is
+                when "00"   => DO           <= PORTA_READ;
+                when "01"   => DO           <= PORTB_READ;
+                when "10"   => DO           <= PORTC_READ;
+                when "11"   => DO           <= CONTROL_READ;
+                when others => null;
+            end case;
+        --end if;
+    end process;
+    CONTROL_READ(7)                         <= '1'; -- always 1
+    CONTROL_READ(6 downto 0)                <= R_CONTROL(6 downto 0);
+
+    P_RW_CONTROL : process(CS_n, RD_n, WR_n, ADDR)
+    begin
+        PORTA_WE                            <= '0';
+        PORTB_WE                            <= '0';
+        PORTA_RE                            <= '0';
+        PORTB_RE                            <= '0';
+
+        if (CS_n = '0') and (ADDR     = "00") then
+            PORTA_WE                        <= not WR_n;
+            PORTA_RE                        <= not RD_n;
+        end if;
+
+        if (CS_n = '0') and (ADDR     = "01") then
+            PORTB_WE                        <= not WR_n;
+            PORTB_RE                        <= not RD_n;
+        end if;
+    end process;
+
+    P_RW_CONTROL_REG : process(RESET, CLK)
+    begin
+        if RESET = '1' then
+                PORTA_WE_T1                 <= '0';
+                PORTB_WE_T1                 <= '0';
+                PORTA_RE_T1                 <= '0';
+                PORTB_RE_T1                 <= '0';
+                A_STB_L_T1                  <= '0';
+                A_ACK_L_T1                  <= '0';
+                B_STB_L_T1                  <= '0';
+                B_ACK_L_T1                  <= '0';
+
+        elsif CLK'event and CLK = '1' then
+            if (ENA = '1') then
+                PORTA_WE_T1                 <= PORTA_WE;
+                PORTB_WE_T1                 <= PORTB_WE;
+                PORTA_RE_T1                 <= PORTA_RE;
+                PORTB_RE_T1                 <= PORTB_RE;
+
+                A_STB_L_T1                  <= A_STB_L;
+                A_ACK_L_T1                  <= A_ACK_L;
+                B_STB_L_T1                  <= B_STB_L;
+                B_ACK_L_T1                  <= B_ACK_L;
+            end if ;
+        end if;
+    end process;
+
+    PORTA_WE_RISING                         <= (PORTA_WE = '0') and (PORTA_WE_T1 = '1'); -- falling as inverted
+    PORTB_WE_RISING                         <= (PORTB_WE = '0') and (PORTB_WE_T1 = '1'); --    "
+    PORTA_RE_RISING                         <= (PORTA_RE = '0') and (PORTA_RE_T1 = '1'); -- falling as inverted
+    PORTB_RE_RISING                         <= (PORTB_RE = '0') and (PORTB_RE_T1 = '1'); --    "
+    --
+    A_STB_L_RISING                          <= (A_STB_L = '1') and (A_STB_L_T1 = '0');
+    A_ACK_L_RISING                          <= (A_ACK_L = '1') and (A_ACK_L_T1 = '0');
+    B_STB_L_RISING                          <= (B_STB_L = '1') and (B_STB_L_T1 = '0');
+    B_ACK_L_RISING                          <= (B_ACK_L = '1') and (B_ACK_L_T1 = '0');
+    --
+    -- GROUP A
+    -- in mode 1
+    --
+    -- d4=1 (porta = input)
+    --     pc7,6 io (d3=1 input, d3=0 output)
+    --     pc5 output A_IBF
+    --     pc4 input  A_STB_L
+    --     pc3 output A_INTR
+    --
+    -- d4=0 (porta = output)
+    --     pc7 output A_OBF_L
+    --     pc6 input  A_ACK_L
+    --     pc5,4 io (d3=1 input, d3=0 output)
+    --     pc3 output A_INTR
+    --
+    -- GROUP B
+    -- in mode 1
+    -- d1=1 (portb = input)
+    --     pc2 input  B_STB_L
+    --     pc1 output B_IBF
+    --     pc0 output B_INTR
+    --
+    -- d1=0 (portb = output)
+    --     pc2 input  B_ACK_L
+    --     pc1 output B_OBF_L
+    --     pc0 output B_INTR
+
+
+    -- WHEN AN INPUT
+    --
+    -- stb_l a low on this input latches input data
+    -- ibf     a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L
+    -- intr    a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L
+    -- inte A controlled by bit/set PC4
+    -- inte B controlled by bit/set PC2
+
+    -- WHEN AN OUTPUT
+    --
+    -- obf_l output will go low when cpu has written data
+    -- ack_l input - a low on this clears obf_l
+    -- intr    output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L
+    -- inte A controlled by bit/set PC6
+    -- inte B controlled by bit/set PC2
+
+    -- GROUP A
+    -- in mode 2
+    --
+    -- porta = IO
+    --
+    --    control bits 2..0 still control groupb/c lower 2..0
+    --
+    --
+    --    PC7 output a_obf
+    --    PC6 input    A_ACK_L
+    --    PC5 output A_IBF
+    --    PC4 input    A_STB_L
+    --    PC3 is still interrupt out
+    P_CONTROL_FLAGS : process(RESET, CLK)
+        variable we     : boolean;
+        variable set1   : boolean;
+        variable set2   : boolean;
+    begin
+        if (RESET = '1') then
+            A_OBF_L                         <= '1';
+            A_INTE1                         <= '0';
+            A_IBF                           <= '0';
+            A_INTE2                         <= '0';
+            A_INTR                          <= '0';
+            --
+            B_INTE                          <= '0';
+            B_OBF_L                         <= '1';
+            B_IBF                           <= '0';
+            B_INTR                          <= '0';
+        elsif rising_edge(CLK) then
+            we := (CS_n = '0') and (WR_n = '0') and (ADDR = "11") and (DI(7) = '0');
+
+            if (ENA = '1') then
+                if (MODE_CLEAR = '1') then
+                    A_OBF_L                 <= '1';
+                    A_INTE1                 <= '0';
+                    A_IBF                   <= '0';
+                    A_INTE2                 <= '0';
+                    A_INTR                  <= '0';
+                    --
+                    B_INTE                  <= '0';
+                    B_OBF_L                 <= '1';
+                    B_IBF                   <= '0';
+                    B_INTR                  <= '0';
+                else
+                    if (BIT_MASK(7) = '1') and we then
+                        A_OBF_L             <= DI(0);
+                    else
+                        if PORTA_WE_RISING then
+                            A_OBF_L         <= '0';
+                        elsif (A_ACK_L = '0') then
+                            A_OBF_L         <= '1';
+                        end if;
+                    end if;
+                    --
+                    if (BIT_MASK(6) = '1') and we then
+                        A_INTE1             <= DI(0);
+                    end if; -- bus set when mode1 & input?
+                    --
+                    if (BIT_MASK(5) = '1') and we then
+                        A_IBF               <= DI(0);
+                    else
+                        if PORTA_RE_RISING then
+                            A_IBF           <= '0';
+                        elsif (A_STB_L = '0') then
+                            A_IBF           <= '1';
+                        end if;
+                    end if;
+                    --
+                    if (BIT_MASK(4) = '1') and we then
+                        A_INTE2             <= DI(0);
+                    end if; -- bus set when mode1 & output?
+                    --
+                    set1 := A_ACK_L_RISING and (A_OBF_L = '1') and (A_INTE1 = '1');
+                    set2 := A_STB_L_RISING and (A_IBF   = '1') and (A_INTE2 = '1');
+                    --
+                    if (BIT_MASK(3) = '1') and we then
+                        A_INTR              <= DI(0);
+                    else
+                        if (GROUPA_MODE(1) = '1') then
+                            if (PORTA_WE = '1') or (PORTA_RE = '1') then
+                                 A_INTR     <= '0';
+                             elsif set1 or set2 then
+                                 A_INTR     <= '1';
+                             end if;
+                        else
+                            if (R_CONTROL(4) = '0') then -- output
+                                if (PORTA_WE = '1') then -- falling ?
+                                    A_INTR  <= '0';
+                                elsif set1 then
+                                    A_INTR  <= '1';
+                                end if;
+                            elsif (R_CONTROL(4) = '1') then -- input
+                                if (PORTA_RE = '1') then -- falling ?
+                                    A_INTR  <= '0';
+                                elsif set2 then
+                                    A_INTR  <= '1';
+                                end if;
+                            end if;
+                        end if;
+                    end if;
+                    --
+                    if (BIT_MASK(2) = '1') and we then
+                        B_INTE              <= DI(0);
+                    end if; -- bus set?
+
+                    if (BIT_MASK(1) = '1') and we then
+                        B_OBF_L             <= DI(0);
+                    else
+                        if (R_CONTROL(1) = '0') then -- output
+                            if PORTB_WE_RISING then
+                                B_OBF_L     <= '0';
+                            elsif (B_ACK_L = '0') then
+                                B_OBF_L     <= '1';
+                            end if;
+                        else
+                            if PORTB_RE_RISING then
+                                B_IBF       <= '0';
+                            elsif (B_STB_L = '0') then
+                                B_IBF       <= '1';
+                            end if;
+                        end if;
+                    end if;
+
+                    if (BIT_MASK(0) = '1') and we then
+                        B_INTR              <= DI(0);
+                    else
+                        if (R_CONTROL(1) = '0') then -- output
+                            if (PORTB_WE = '1') then -- falling ?
+                                B_INTR      <= '0';
+                            elsif B_ACK_L_RISING and (B_OBF_L = '1') and (B_INTE = '1') then
+                                B_INTR      <= '1';
+                            end if;
+                        else
+                            if (PORTB_RE = '1') then -- falling ?
+                                B_INTR      <= '0';
+                            elsif B_STB_L_RISING and (B_IBF = '1') and (B_INTE = '1') then
+                                B_INTR      <= '1';
+                            end if;
+                        end if;
+                    end if;
+
+                end if;
+            end if;
+        end if;
+    end process;
+
+    P_PORTA : process(R_PORTA, R_CONTROL, GROUPA_MODE, PA_I, PORTA_IPREG, A_ACK_L)
+    begin
+        -- D4 GROUPA porta 1 = input, 0 = output
+        PA_O                                <= x"FF"; -- if not driven, float high
+        PA_O_OE_n                           <= x"FF";
+        PORTA_READ                          <= x"00";
+
+        if (GROUPA_MODE = "00") then -- simple io
+        PA_O                                <= R_CONTROL; -- x"5F"; -- if not driven, float high
+            if (R_CONTROL(4) = '0') then -- output
+                PA_O                        <= R_PORTA;
+                PA_O_OE_n                   <= x"00";
+            end if;
+            PORTA_READ                      <= PA_I;
+        elsif (GROUPA_MODE = "01") then -- strobed
+            if (R_CONTROL(4) = '0') then -- output
+                PA_O                        <= R_PORTA;
+                PA_O_OE_n                   <= x"00";
+            end if;
+            PORTA_READ                      <= PORTA_IPREG;
+        else -- if (GROUPA_MODE(1) = '1') then -- bi dir
+            if (A_ACK_L = '0') then -- output enable
+                PA_O                        <= R_PORTA;
+                PA_O_OE_n                   <= x"00";
+            end if;
+            PORTA_READ                      <= PORTA_IPREG; -- latched dat
+        end if;
+
+    end process;
+
+    P_PORTB : process(R_PORTB, R_CONTROL, GROUPB_MODE, PB_I, PORTB_IPREG)
+    begin
+        PB_O                                <= x"FF"; -- if not driven, float high
+        PB_O_OE_n                           <= x"FF";
+        PORTB_READ                          <= x"00";
+
+        if (GROUPB_MODE = '0') then -- simple io
+            if (R_CONTROL(1) = '0') then -- output
+                PB_O                        <= R_PORTB;
+                PB_O_OE_n                   <= x"00";
+            end if;
+            PORTB_READ                      <= PB_I;
+        else -- strobed mode
+            if (R_CONTROL(1) = '0') then -- output
+                PB_O                        <= R_PORTB;
+                PB_O_OE_n                   <= x"00";
+            end if;
+            PORTB_READ                      <= PORTB_IPREG;
+        end if;
+    end process;
+
+    P_PORTC_OUT : process(R_PORTC, R_CONTROL, GROUPA_MODE, GROUPB_MODE, A_OBF_L, A_IBF, A_INTR,B_OBF_L, B_IBF, B_INTR)
+    begin
+        PC_O                                <= x"FF"; -- if not driven, float high
+        PC_O_OE_n                           <= x"FF";
+
+        -- bits 7..4
+        if (GROUPA_MODE = "00") then -- simple io
+            if (R_CONTROL(3) = '0') then -- output
+                PC_O(7 downto 4)            <= R_PORTC(7 downto 4);
+                PC_O_OE_n(7 downto 4)       <= x"0";
+            end if;
+        elsif (GROUPA_MODE = "01") then -- mode1
+
+            if (R_CONTROL(4) = '0') then -- port a output
+                PC_O(7)                     <= A_OBF_L;
+                PC_O_OE_n(7)                <= '0';
+                -- 6 is ack_l input
+                if (R_CONTROL(3) = '0') then -- port c output
+                    PC_O(5 downto 4)        <= R_PORTC(5 downto 4);
+                    PC_O_OE_n(5 downto 4)   <= "00";
+                end if;
+            else -- port a input
+                if (R_CONTROL(3) = '0') then -- port c output
+                    PC_O(7 downto 6)        <= R_PORTC(7 downto 6);
+                    PC_O_OE_n(7 downto 6)   <= "00";
+                end if;
+                PC_O(5)                     <= A_IBF;
+                PC_O_OE_n(5)                <= '0';
+                -- 4 is stb_l input
+            end if;
+
+        else -- if (GROUPA_MODE(1) = '1') then -- mode2
+            PC_O(7)                         <= A_OBF_L;
+            PC_O_OE_n(7)                    <= '0';
+            -- 6 is ack_l input
+            PC_O(5)                         <= A_IBF;
+            PC_O_OE_n(5)                    <= '0';
+            -- 4 is stb_l input
+        end if;
+
+        -- bit 3 (controlled by group a)
+        if (GROUPA_MODE = "00") then -- group a steals this bit
+            --if (GROUPB_MODE = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this
+            if (R_CONTROL(0) = '0') then -- ouput (note, groupb control bit)
+                PC_O(3)                     <= R_PORTC(3);
+                PC_O_OE_n(3)                <= '0';
+            end if;
+            --
+        else -- stolen
+            PC_O(3)                         <= A_INTR;
+            PC_O_OE_n(3)                    <= '0';
+        end if;
+
+        -- bits 2..0
+        if (GROUPB_MODE = '0') then -- simple io
+            if (R_CONTROL(0) = '0') then -- output
+                PC_O(2 downto 0)            <= R_PORTC(2 downto 0);
+                PC_O_OE_n(2 downto 0)       <= "000";
+            end if;
+        else
+            -- mode 1
+            -- 2 is input
+            if (R_CONTROL(1) = '0') then -- output
+                PC_O(1)                     <= B_OBF_L;
+                PC_O_OE_n(1)                <= '0';
+            else -- input
+                PC_O(1)                     <= B_IBF;
+                PC_O_OE_n(1)                <= '0';
+            end if;
+            PC_O(0)                         <= B_INTR;
+            PC_O_OE_n(0)                    <= '0';
+        end if;
+    end process;
+
+    P_PORTC_IN : process(R_PORTC, PC_I, R_CONTROL, GROUPA_MODE, GROUPB_MODE, A_IBF, B_OBF_L, A_OBF_L, A_INTE1, A_INTE2, A_INTR, B_INTE, B_IBF, B_INTR)
+    begin
+        PORTC_READ                          <= x"00";
+        A_STB_L                             <= '1';
+        A_ACK_L                             <= '1';
+        B_STB_L                             <= '1';
+        B_ACK_L                             <= '1';
+
+        if (GROUPA_MODE = "01") then -- mode1 or 2
+            if (R_CONTROL(4) = '0') then -- port a output
+                A_ACK_L                     <= PC_I(6);
+            else -- port a input
+                A_STB_L                     <= PC_I(4);
+            end if;
+        elsif (GROUPA_MODE(1) = '1') then -- mode 2
+            A_ACK_L                         <= PC_I(6);
+            A_STB_L                         <= PC_I(4);
+        end if;
+
+        if (GROUPB_MODE = '1') then
+            if (R_CONTROL(1) = '0') then -- output
+                B_ACK_L                     <= PC_I(2);
+            else -- input
+                B_STB_L                     <= PC_I(2);
+            end if;
+        end if;
+
+        if (GROUPA_MODE = "00") then -- simple io
+            PORTC_READ(7 downto 3)          <= PC_I(7 downto 3);
+        elsif (GROUPA_MODE = "01") then
+            if (R_CONTROL(4) = '0') then -- port a output
+                PORTC_READ(7 downto 3)      <= A_OBF_L & A_INTE1 & PC_I(5 downto 4) & A_INTR;
+            else -- input
+                PORTC_READ(7 downto 3)      <= PC_I(7 downto 6)  & A_IBF & A_INTE2 & A_INTR;
+            end if;
+        else -- mode 2
+            PORTC_READ(7 downto 3)          <= A_OBF_L & A_INTE1 & A_IBF & A_INTE2 & A_INTR;
+        end if;
+
+        if (GROUPB_MODE = '0') then -- simple io
+            PORTC_READ(2 downto 0)          <= PC_I(2 downto 0);
+        else
+            if (R_CONTROL(1) = '0') then -- output
+                PORTC_READ(2 downto 0)      <= B_INTE & B_OBF_L & B_INTR;
+            else -- input
+                PORTC_READ(2 downto 0)      <= B_INTE & B_IBF   & B_INTR;
+            end if;
+        end if;
+    end process;
+
+    P_IPREG : process(RESET, CLK)
+    begin
+        if RESET = '1' then
+            PORTA_IPREG                     <= (others => '0');
+            PORTB_IPREG                     <= (others => '0');
+            PORTB_IPREG                     <= (others => '0');
+
+        elsif CLK'event and CLK = '1' then
+            --     pc4 input    A_STB_L
+            --     pc2 input    B_STB_L
+
+            if (ENA = '1') then
+                if (A_STB_L = '0') then
+                    PORTA_IPREG             <= PA_I;
+                end if;
+
+                if (MODE_CLEAR = '1') then
+                    PORTB_IPREG             <= (others => '0');
+                elsif (B_STB_L = '0') then
+                    PORTB_IPREG             <= PB_I;
+                end if;
+            end if;
+        end if;
+    end process;
+
+end architecture RTL;
diff --git a/common/keymatrix.vhd b/common/keymatrix.vhd
new file mode 100644
index 0000000..c0066fc
--- /dev/null
+++ b/common/keymatrix.vhd
@@ -0,0 +1,319 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            keymatrix.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     Keyboard module to convert PS2 key codes into Sharp scan matrix key connections.
+--                  For each scan output (10 lines) sent by the Sharp, an 8bit response is read in 
+--                  and the bits set indicate keys pressed. This allows for multiple keys to be pressed
+--                  at the same time. The PS2 scan code is mapped via a rom and the output is used to drive
+--                  the data in lines of the 8255.
+--
+-- Credits:         Nibbles Lab (c) 2005-2012
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018   - Initial module written, originally based on the Nibbles Lab code but
+--                                rewritten to match the overall design of this emulation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library IEEE;
+library pkgs;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity keymatrix is
+    Port (
+        RST_n                : in  std_logic;
+
+        -- i8255
+        PA                   : in  std_logic_vector(3 downto 0);
+        PB                   : out std_logic_vector(7 downto 0);
+        STALL                : in  std_logic;
+        BREAKDETECT          : out std_logic;
+
+        -- PS/2 Keyboard Data
+        PS2_KEY              : in  std_logic_vector(10 downto 0);        -- PS2 Key data.
+
+        -- Different operations modes.
+        CONFIG               : in  std_logic_vector(CONFIG_WIDTH);
+
+        -- Clock signals used by this module.
+        CLKBUS               : in  std_logic_vector(CLKBUS_WIDTH);
+
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_UPLOAD         : in  std_logic;                            -- HPS Uploading from FPGA.
+        IOCTL_CLK            : in  std_logic;                            -- HPS I/O Clock.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(31 downto 0)         -- HPS Data to be read into HPS.
+    );
+end keymatrix;
+
+architecture Behavioral of keymatrix is
+
+--
+-- prefix flag
+--
+signal FLGF0                 : std_logic;
+signal FLGE0                 : std_logic;
+--
+-- MZ-series matrix registers
+--
+signal SCAN00                : std_logic_vector(7 downto 0);
+signal SCAN01                : std_logic_vector(7 downto 0);
+signal SCAN02                : std_logic_vector(7 downto 0);
+signal SCAN03                : std_logic_vector(7 downto 0);
+signal SCAN04                : std_logic_vector(7 downto 0);
+signal SCAN05                : std_logic_vector(7 downto 0);
+signal SCAN06                : std_logic_vector(7 downto 0);
+signal SCAN07                : std_logic_vector(7 downto 0);
+signal SCAN08                : std_logic_vector(7 downto 0);
+signal SCAN09                : std_logic_vector(7 downto 0);
+signal SCAN10                : std_logic_vector(7 downto 0);
+signal SCAN11                : std_logic_vector(7 downto 0);
+signal SCAN12                : std_logic_vector(7 downto 0);
+signal SCAN13                : std_logic_vector(7 downto 0);
+signal SCAN14                : std_logic_vector(7 downto 0);
+signal SCANLL                : std_logic_vector(7 downto 0);
+--
+-- Key code exchange table
+--
+signal MTEN                  : std_logic_vector(3 downto 0);
+signal F_KBDT                : std_logic_vector(7 downto 0);
+signal MAP_DATA              : std_logic_vector(7 downto 0);
+signal KEY_BANK              : std_logic_vector(2 downto 0);
+
+--
+-- HPS access
+--
+signal IOCTL_KEYMAP_WEN      : std_logic;
+signal IOCTL_DIN_KEYMAP      : std_logic_vector(7 downto 0);        -- HPS Data to be read into HPS.
+
+signal KEY_EXTENDED          : std_logic;
+signal KEY_FLAG              : std_logic;
+signal KEY_PRESS             : std_logic;
+signal KEY_VALID             : std_logic;
+--
+-- Components
+--
+component dprom
+    GENERIC (
+          init_file          : string;
+          widthad_a          : natural;
+          width_a            : natural
+    );
+    PORT
+    (
+          address_a          : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+          address_b          : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+          clock_a            : IN STD_LOGIC ;
+          clock_b            : IN STD_LOGIC ;
+--        data_a             : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+          data_b             : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+--        wren_a             : IN STD_LOGIC;
+          wren_b             : IN STD_LOGIC;
+          q_a                : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+          q_b                : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+    );
+end component;
+
+begin
+    --
+    -- Instantiation
+    --
+    -- 0 = MZ80K  KEYMAP = 256Bytes -> 0000:00ff 0000 bytes padding
+    -- 1 = MZ80C  KEYMAP = 256Bytes -> 0100:01ff 0000 bytes padding
+    -- 2 = MZ1200 KEYMAP = 256Bytes -> 0200:02ff 0000 bytes padding
+    -- 3 = MZ80A  KEYMAP = 256Bytes -> 0300:03ff 0000 bytes padding
+    -- 4 = MZ700  KEYMAP = 256Bytes -> 0400:04ff 0000 bytes padding
+    -- 5 = MZ80B  KEYMAP = 256Bytes -> 0500:05ff 0000 bytes padding
+
+    MAP0 : dprom
+    GENERIC MAP (
+      --init_file            => "./software/mif/key_80k_80b.mif",
+        init_file            => "./software/mif/combined_keymap.mif",
+        widthad_a            => 11,
+        width_a              => 8
+    ) 
+    PORT MAP (
+        clock_a              => CLKBUS(CKMASTER),
+        address_a            => KEY_BANK & F_KBDT,
+--      data_a               => IOCTL_DOUT(7 DOWNTO 0),
+--      wren_a               => 
+        q_a                  => MAP_DATA,
+
+        clock_b              => IOCTL_CLK,
+        address_b            => IOCTL_ADDR(10 DOWNTO 0),
+        data_b               => IOCTL_DOUT(7 DOWNTO 0),
+        wren_b               => IOCTL_KEYMAP_WEN,
+        q_b                  => IOCTL_DIN_KEYMAP
+    );
+
+    -- Store changes to the key valid flag in a flip flop.
+    process( CLKBUS(CKMASTER) ) begin
+        if rising_edge(CLKBUS(CKMASTER)) then
+            if CLKBUS(CKENCPU) = '1' then
+                KEY_FLAG <= PS2_KEY(10);
+            end if;
+        end if;
+    end process;
+
+    -- Set the key mapping to use according to selected machine.
+    --
+    process( RST_n, CLKBUS(CKMASTER) ) begin
+        if RST_n = '0' then
+            KEY_BANK <= "000";
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
+            if CLKBUS(CKENCPU) = '1' then
+                if CONFIG(MZ80K)  = '1' then                                 -- Key map for MZ80K
+                    KEY_BANK <= "000";
+                elsif CONFIG(MZ80C)  = '1' then                              -- Key map for MZ80C
+                    KEY_BANK <= "001";
+                elsif CONFIG(MZ1200) = '1' then                              -- Key map for MZ1200
+                    KEY_BANK <= "010";
+                elsif CONFIG(MZ80A)  = '1' then                              -- Key map for MZ80A
+                    KEY_BANK <= "011";
+                elsif CONFIG(MZ700)  = '1' then                              -- Key map for MZ700
+                    KEY_BANK <= "100";
+                elsif CONFIG(MZ800)  = '1' then                              -- Key map for MZ800
+                    KEY_BANK <= "101";
+                elsif CONFIG(MZ80B)  = '1' then                              -- Key map for MZ80B
+                    KEY_BANK <= "110";
+                elsif CONFIG(MZ2000) = '1' then                              -- Key map for MZ2000
+                    KEY_BANK <= "111";
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Convert
+    --
+    process( RST_n, CLKBUS(CKMASTER) ) begin
+        if RST_n = '0' then
+            SCAN00   <= (others=>'0');
+            SCAN01   <= (others=>'0');
+            SCAN02   <= (others=>'0');
+            SCAN03   <= (others=>'0');
+            SCAN04   <= (others=>'0');
+            SCAN05   <= (others=>'0');
+            SCAN06   <= (others=>'0');
+            SCAN07   <= (others=>'0');
+            SCAN08   <= (others=>'0');
+            SCAN09   <= (others=>'0');
+            SCAN10   <= (others=>'0');
+            SCAN11   <= (others=>'0');
+            SCAN12   <= (others=>'0');
+            SCAN13   <= (others=>'0');
+            SCAN14   <= (others=>'0');
+            FLGF0    <= '0';
+            FLGE0    <= '0';
+            MTEN     <= (others=>'0');
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
+            if CLKBUS(CKENCPU) = '1' then
+                MTEN           <= MTEN(2 downto 0) & KEY_VALID;
+                if KEY_VALID='1' then
+                    if(KEY_EXTENDED='1') then
+                        FLGE0  <= '1';
+                    end if;
+                    if(KEY_PRESS='0') then
+                        FLGF0  <= '1';
+                    end if;
+                    if(PS2_KEY(7 downto 0) = X"AA" ) then
+                        F_KBDT <= X"EF";
+                    else
+                        F_KBDT <= FLGE0 & PS2_KEY(6 downto 0); FLGE0<='0';
+                    end if;
+                end if;
+    
+                if MTEN(3)='1' then
+                    case MAP_DATA(7 downto 4) is                                 
+                        when "0000" => SCAN00(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "0001" => SCAN01(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "0010" => SCAN02(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "0011" => SCAN03(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "0100" => SCAN04(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "0101" => SCAN05(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "0110" => SCAN06(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "0111" => SCAN07(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "1000" => SCAN08(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "1001" => SCAN09(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "1010" => SCAN10(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "1011" => SCAN11(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "1100" => SCAN12(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "1101" => SCAN13(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                        when "1110" => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0;
+                        when others => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    PA_L : for I in 0 to 7 generate
+        SCANLL(I) <= SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I) or
+                     SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I) or
+                     SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I);
+    end generate PA_L;
+
+    --
+    -- response from key access
+    --
+    PB <= (not SCANLL) when STALL='0' and CONFIG(MZ_B)='1'  else
+          (not SCAN00) when PA="0000"                       else
+          (not SCAN01) when PA="0001"                       else
+          (not SCAN02) when PA="0010"                       else
+          (not SCAN03) when PA="0011"                       else
+          (not SCAN04) when PA="0100"                       else
+          (not SCAN05) when PA="0101"                       else
+          (not SCAN06) when PA="0110"                       else
+          (not SCAN07) when PA="0111"                       else
+          (not SCAN08) when PA="1000"                       else
+          (not SCAN09) when PA="1001"                       else
+          (not SCAN10) when PA="1010"                       else
+          (not SCAN11) when PA="1011"                       else
+          (not SCAN12) when PA="1100"                       else
+          (not SCAN13) when PA="1101"                       else (others=>'1');
+
+    -- Setup key extension signals to use in mapping.
+    --
+    KEY_PRESS        <= PS2_KEY(9);
+    KEY_EXTENDED     <= PS2_KEY(8);
+    KEY_VALID        <= '1' when KEY_FLAG /= PS2_KEY(10)
+                        else '0';
+
+    -- Break detect is connected to SCAN line 3, bit 7. When the strobe is set to 03H and the break key is pressed
+    -- this signal will go low and detected in the IPL.
+    BREAKDETECT      <= not SCAN03(7);
+
+    --
+    -- HPS access to reload keymap.
+    --
+    IOCTL_KEYMAP_WEN <= '1'                          when IOCTL_ADDR(24 downto 16) = "000100011" and IOCTL_WR = '1'
+                        else '0';
+    IOCTL_DIN        <= X"000000" & IOCTL_DIN_KEYMAP when IOCTL_ADDR(24 downto 16) = "000100011" and IOCTL_RD = '1'
+                        else
+                        (others=>'0');
+
+end Behavioral;
diff --git a/common/mctrl.vhd b/common/mctrl.vhd
new file mode 100644
index 0000000..aca28c4
--- /dev/null
+++ b/common/mctrl.vhd
@@ -0,0 +1,707 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            mctrl.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series Programmable Machine Control logic.
+--                  This module forms the Programmable control of the emulation along with sync reset
+--                  management.
+--                  A set of 16 addressable registers is presented on the external IOCTL interface.
+--                  Each register controls an aspect of the emulation, such as video mode or cpu speed.
+--
+--                  Reset to all components is managed by this module, taking cold, warm and internally
+--                  generated reset signals and creating a unified system reset output.
+--
+--                  Please see the docs/SharpMZ_Notes.xlsx spreadsheet for details on these registers
+--                  and the values they take.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018   - Initial module written.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+package mctrl_pkg is
+
+    -- Config Bus
+    --
+    subtype  CONFIG_WIDTH is integer range 70 downto 0;
+
+
+    -- Mode signals indicating type of machine we are emulating.
+    --
+    constant MZ80K           : integer := 0;                             -- Machine is an MZ80K
+    constant MZ80C           : integer := 1;                             -- Machine is an MZ80C
+    constant MZ1200          : integer := 2;                             -- Machine is an MZ1200
+    constant MZ80A           : integer := 3;                             -- Machine is an MZ80A
+    constant MZ700           : integer := 4;                             -- Machine is an MZ700
+    constant MZ800           : integer := 5;                             -- Machine is an MZ800
+    constant MZ80B           : integer := 6;                             -- Machine is an MZ80B
+    constant MZ2000          : integer := 7;                             -- Machine is an MZ2000
+    subtype  CURRENTMACHINE  is integer range 7 downto 0;                -- Range of bits to indicate current machine, only 1 bit is set at a time.
+    constant MZ_KC           : integer := 8;                             -- Machine is an MZ80K/MZ80C Series
+    constant MZ_A            : integer := 9;                             -- Machine is an MZ1200/MZ80A Series
+    constant MZ_B            : integer := 10;                            -- Machine is an MZ2000/MZ80B Series
+    constant MZ_80B          : integer := 11;                            -- Machine is an MZ2000/MZ80B Series
+    constant MZ_80C          : integer := 12;                            -- Machine is an MZ80K/MZ80C/MZ1200/MZ80A Series
+
+    -- Type of display to emulate.
+    --
+    constant NORMAL          : integer := 13;                            -- Normal 40 x 25 character monochrome display.
+    constant NORMAL80        : integer := 14;                            -- Normal 80 x 25 character monochrome display.
+    constant COLOUR          : integer := 15;                            -- Colour 40 x 25 character display.
+    constant COLOUR80        : integer := 16;                            -- Colour 80 x 25 character display.
+    subtype  VGAMODE         is integer range 18 downto 17;              -- Output display to 640x400 or 640x480, double up pixels as required.
+
+    -- Option Roms Enable (some machines by design dont have them, but this emulation allows them to be enabled if needed).
+    --
+    subtype  USERROM         is integer range 26 downto 19;              -- User ROM E800 - EFFF enable per machine.
+    subtype  FDCROM          is integer range 34 downto 27;              -- FDC ROM F000 - FFFF enable per machine.
+
+    subtype  GRAMIOADDR      is integer range 39 downto 35;
+
+    -- Various configurable settings.
+    --
+    constant AUDIOSRC        : integer := 40;                            -- Audio source, 0 = sound generator, 1 = tape audio.
+    subtype  TURBO           is integer range 43 downto 41;              -- 2MHz/4MHz/8MHz/16MHz/32MHz switch (various).
+    subtype  FASTTAPE        is integer range 46 downto 44;              -- Speed of tape read/write.
+    subtype  BUTTONS         is integer range 48 downto 47;              -- Various external buttons, such as CMT play/record.
+    constant PCGRAM          : integer := 49;                            -- PCG ROM(0) or RAM(1) based.
+    constant VRAMWAIT        : integer := 50;                            -- Insert video wait states on CPU access as per original design.
+    constant VRAMDISABLE     : integer := 51;                            -- Disable the Video RAM from display output.
+    constant GRAMDISABLE     : integer := 52;                            -- Disable the graphics RAM from display output.
+    constant MENUENABLE      : integer := 53;                            -- Enable the OSD menu on display output.
+    constant STATUSENABLE    : integer := 54;                            -- Enable the OSD menu on display output.
+    constant BOOT_RESET      : integer := 55;                            -- MZ80B/2000 Boot IPL Reset Enable.
+    constant CMTASCII_IN     : integer := 56;                            -- Enable CMT conversion of Sharp Ascii <-> Ascii on receipt of data from Sharp.
+    constant CMTASCII_OUT    : integer := 57;                            -- Enable CMT conversion of Sharp Ascii <-> Ascii on sending data to Sharp.
+
+    -- Derivative settings to program the clock generator.
+    --
+    subtype  CPUSPEED        is integer range 61 downto 58;              -- Active CPU Speed.
+    subtype  VIDSPEED        is integer range 64 downto 62;              -- Active Video Speed.
+    subtype  PERSPEED        is integer range 66 downto 65;              -- Active Peripheral Speed.
+    subtype  RTCSPEED        is integer range 68 downto 67;              -- Active RTC Speed.
+    subtype  SNDSPEED        is integer range 70 downto 69;              -- Active Sound Speed.
+
+    -- CMT Bus
+    --
+    subtype  CMT_BUS_OUT_WIDTH  is integer range 13 downto 0;
+    subtype  CMT_BUS_IN_WIDTH   is integer range 7 downto 0;
+
+    -- CMT exported Signals.
+    --
+    constant PLAY_READY      : integer := 0;                             -- Tape play back buffer, 0 = empty, 1 = full.
+    constant PLAYING         : integer := 1;                             -- Tape playback, 0 = stopped, 1 = in progress.
+    constant RECORD_READY    : integer := 2;                             -- Tape record buffer full, 0 = empty, 1 = full.
+    constant RECORDING       : integer := 3;                             -- Tape recording, 0 = stopped, 1 = in progress.
+    constant ACTIVE          : integer := 4;                             -- Tape transfer in progress, 0 = no activity, 1 = activity.
+    constant SENSE           : integer := 5;                             -- Tape state Sense out.
+    constant WRITEBIT        : integer := 6;                             -- Write bit to MZ.
+    constant TAPEREADY       : integer := 7;                             -- Tape is loaded in deck when L = 0.
+    constant WRITEREADY      : integer := 8;                             -- Write is prohibited when L = 0.
+    constant APSS_SEEK       : integer := 9;                             -- Start to seek the next program according to APSS_DIR
+    constant APSS_DIR        : integer := 10;                            -- Direction for APSS Seek, 0 = Rewind, 1 = Forward.
+    constant APSS_EJECT      : integer := 11;                            -- Eject cassette.
+    constant APSS_PLAY       : integer := 12;                            -- Play cassette.
+    constant APSS_STOP       : integer := 13;                            -- Stop playing/rwd/ff of cassette.
+
+    -- CMT imported Signals.
+    --
+    constant READBIT         : integer := 0;                             -- Receive bit from MZ.
+    constant REEL_MOTOR      : integer := 1;                             -- APSS Reel Motor on/off.
+    constant STOP            : integer := 2;                             -- Stop the motor.
+    constant PLAY            : integer := 3;                             -- Play cassette.
+    constant SEEK            : integer := 4;                             -- Seek cassette using DIRECTION (L = Rewind, H = FF).
+    constant DIRECTION       : integer := 5;                             -- Seek direction, L = Rewind, H = Fast Forward.
+    constant EJECT           : integer := 6;                             -- Eject the cassette.
+    constant WRITEENABLE     : integer := 7;                             -- Enable writing to cassette.
+
+    -- Debug Bus
+    --
+    subtype  DEBUG_WIDTH is integer range 15 downto 0;
+
+    -- Debugging signals.
+    --
+    subtype  LEDS_BANK       is integer range 2 downto 0;
+    subtype  LEDS_SUBBANK    is integer range 5 downto 3;
+    constant LEDS_ON         : integer := 6;
+    constant ENABLED         : integer := 7;
+    subtype  SMPFREQ         is integer range 11 downto 8;
+    subtype  CPUFREQ         is integer range 15 downto 12;
+end mctrl_pkg;
+
+
+library IEEE;
+library pkgs;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+use pkgs.config_pkg.all;
+use pkgs.mctrl_pkg.all;
+use pkgs.clkgen_pkg.all;
+
+entity mctrl is
+    Port (
+        -- Clock signals used by this module.
+        CLKBUS               : in  std_logic_vector(CLKBUS_WIDTH);
+
+        -- Reset's
+        COLD_RESET           : in  std_logic;
+        WARM_RESET           : in  std_logic;
+        SYSTEM_RESET         : out std_logic;
+
+        -- HPS Interface
+        IOCTL_CLK            : in  std_logic;                            -- HPS I/O Clock.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+        -- Different operations modes.
+        CONFIG               : out std_logic_vector(CONFIG_WIDTH);
+
+        -- Cassette magnetic tape signals.
+        CMT_BUS_OUT          : in  std_logic_vector(CMT_BUS_OUT_WIDTH);
+        CMT_BUS_IN           : in  std_logic_vector(CMT_BUS_IN_WIDTH);
+
+        -- MZ80B series can dynamically change the video frequency to attain 40/80 character display.
+        CONFIG_CHAR80        : in  std_logic;
+
+        -- Debug modes.
+        DEBUG                : out std_logic_vector(DEBUG_WIDTH) 
+    );
+end mctrl;
+
+architecture rtl of mctrl is
+
+signal REGISTER_MODEL        : std_logic_vector(7 downto 0)     := "00000011";
+signal REGISTER_DISPLAY      : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_DISPLAY2     : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_DISPLAY3     : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_CPU          : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_AUDIO        : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_CMT          : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_CMT2         : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_USERROM      : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_FDCROM       : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_10           : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_11           : std_logic_vector(7 downto 0)     := "00000000";
+signal REGISTER_12           : std_logic_vector(7 downto 0)     := "00000000";
+-- REGISTER_13 is a read only configuration, so no register required.
+signal REGISTER_DEBUG        : std_logic_vector(7 downto 0)     := "00001000";
+signal REGISTER_DEBUG2       : std_logic_vector(7 downto 0)     := "00000000";
+signal delay                 : integer range 0 to 63;
+signal READ_STATUS           : std_logic_vector(15 downto 0);
+signal RESET_MACHINE         : std_logic;
+signal CMT_BUS_OUT_LAST      : std_logic_vector(CMT_BUS_OUT_WIDTH);
+
+begin
+    -- Synchronise the register update with the configuration signals according to the CPU clock.
+    --
+    process (COLD_RESET, CLKBUS(CKMASTER))
+    begin
+        if COLD_RESET = '1' then
+            CONFIG(CONFIG_WIDTH) <= "00000000000000000000000000000000011000000000000000000000011001000001000";
+            DEBUG(DEBUG_WIDTH)   <= "0000000000000000";
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                if REGISTER_MODEL(2 downto 0)  = "000" then
+                    CONFIG(MZ80K)     <= '1';
+                else
+                    CONFIG(MZ80K)     <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "001" then
+                    CONFIG(MZ80C)     <= '1';
+                else
+                    CONFIG(MZ80C)     <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "010" then
+                    CONFIG(MZ1200)    <= '1';
+                else
+                    CONFIG(MZ1200)    <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "011" then
+                    CONFIG(MZ80A)     <= '1';
+                else
+                    CONFIG(MZ80A)     <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "100" then
+                    CONFIG(MZ700)     <= '1';
+                else
+                    CONFIG(MZ700)     <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "101" then
+                    CONFIG(MZ800)     <= '1';
+                else
+                    CONFIG(MZ800)     <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "110" then
+                    CONFIG(MZ80B)     <= '1';
+                else
+                    CONFIG(MZ80B)     <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "111" then
+                    CONFIG(MZ2000)    <= '1';
+                else
+                    CONFIG(MZ2000)    <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "000" or  REGISTER_MODEL(2 downto 0)  = "001" then
+                    CONFIG(MZ_KC)     <= '1';
+                else
+                    CONFIG(MZ_KC)     <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "010" or  REGISTER_MODEL(2 downto 0)  = "011" then
+                    CONFIG(MZ_A)      <= '1';
+                else
+                    CONFIG(MZ_A)      <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "110" or  REGISTER_MODEL(2 downto 0)  = "111" then
+                    CONFIG(MZ_B)      <= '1';
+                else
+                    CONFIG(MZ_B)      <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
+                    CONFIG(MZ_80C)    <= '1';
+                else
+                    CONFIG(MZ_80C)    <= '0';
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "110" or  REGISTER_MODEL(2 downto 0)  = "111" then
+                    CONFIG(MZ_80B)    <= '1';
+                else
+                    CONFIG(MZ_80B)    <= '0';
+                end if;
+    
+                if REGISTER_DISPLAY(2 downto 0)  = "000" then
+                    CONFIG(NORMAL)    <= '1';
+                else
+                    CONFIG(NORMAL)    <= '0';
+                end if;
+    
+                if REGISTER_DISPLAY(2 downto 0)  = "001" then
+                    CONFIG(NORMAL80)  <= '1';
+                else
+                    CONFIG(NORMAL80)  <= '0';
+                end if;
+    
+                if REGISTER_DISPLAY(2 downto 0)  = "010" then
+                    CONFIG(COLOUR)    <= '1';
+                else
+                    CONFIG(COLOUR)    <= '0';
+                end if;
+    
+                if REGISTER_DISPLAY(2 downto 0)  = "011" then
+                    CONFIG(COLOUR80)  <= '1';
+                else
+                    CONFIG(COLOUR80)  <= '0';
+                end if;
+
+                -- Convert CPU/CMT and Debug speed selections to actual CPU speed.
+                -- If debugging enabled and Debug freq not 0, select otherwise CMT if CMT is active, otherwise CPU speed as required.
+                --
+                -- Mapping could be made in software or 1-1 with the register, but setting restrictions and mapping in hw preferred, it
+                -- limits frequencies belonging to a given machine and makes it easier to change the frequency by NIOS or other controller if 
+                -- MiSTer not used.
+    
+                if CMT_BUS_OUT(ACTIVE) = '1' then
+                    if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
+                        case REGISTER_CMT(2 downto 0) is
+                            when "000" => CONFIG(CPUSPEED) <= "0000";   -- 2MHz
+                            when "001" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "010" => CONFIG(CPUSPEED) <= "0100";   -- 8MHz
+                            when "011" => CONFIG(CPUSPEED) <= "0110";   -- 16MHz
+                            when "100" => CONFIG(CPUSPEED) <= "1000";   -- 32MHz
+                            when "101" => CONFIG(CPUSPEED) <= "1010";   -- 64MHz
+                            when "110" => CONFIG(CPUSPEED) <= "0000";   -- 2MHz
+                            when "111" => CONFIG(CPUSPEED) <= "0000";   -- 2MHz
+                        end case;
+                    elsif REGISTER_MODEL(2 downto 0)  = "100" then
+                        case REGISTER_CMT(2 downto 0) is
+                            when "000" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                            when "001" => CONFIG(CPUSPEED) <= "0011";   -- 7MHz
+                            when "010" => CONFIG(CPUSPEED) <= "0101";   -- 14MHz
+                            when "011" => CONFIG(CPUSPEED) <= "0111";   -- 28MHz
+                            when "100" => CONFIG(CPUSPEED) <= "1001";   -- 56MHz
+                            when "101" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                            when "110" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                            when "111" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                        end case;
+                    elsif REGISTER_MODEL(2 downto 0)  = "110" or  REGISTER_MODEL(2 downto 0)  = "110" then
+                        case REGISTER_CMT(2 downto 0) is
+                            when "000" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "001" => CONFIG(CPUSPEED) <= "0100";   -- 8MHz
+                            when "010" => CONFIG(CPUSPEED) <= "0110";   -- 16MHz
+                            when "011" => CONFIG(CPUSPEED) <= "1000";   -- 32MHz
+                            when "100" => CONFIG(CPUSPEED) <= "1010";   -- 64MHz
+                            when "101" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "110" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "111" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                        end case;
+                    else
+                        CONFIG(CPUSPEED) <= "0000";    -- Default 2MHz
+                    end if;
+                else
+                    if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
+                        case REGISTER_CPU(2 downto 0) is
+                            when "000" => CONFIG(CPUSPEED) <= "0000";   -- 2MHz
+                            when "001" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "010" => CONFIG(CPUSPEED) <= "0100";   -- 8MHz
+                            when "011" => CONFIG(CPUSPEED) <= "0110";   -- 16MHz
+                            when "100" => CONFIG(CPUSPEED) <= "1000";   -- 32MHz
+                            when "101" => CONFIG(CPUSPEED) <= "1010";   -- 64MHz
+                            when "110" => CONFIG(CPUSPEED) <= "0000";   -- 2MHz
+                            when "111" => CONFIG(CPUSPEED) <= "0000";   -- 2MHz
+                        end case;
+                    elsif REGISTER_MODEL(2 downto 0)  = "100" then
+                        case REGISTER_CPU(2 downto 0) is
+                            when "000" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                            when "001" => CONFIG(CPUSPEED) <= "0011";   -- 7MHz
+                            when "010" => CONFIG(CPUSPEED) <= "0101";   -- 14MHz
+                            when "011" => CONFIG(CPUSPEED) <= "0111";   -- 28MHz
+                            when "100" => CONFIG(CPUSPEED) <= "1001";   -- 56MHz
+                            when "101" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                            when "110" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                            when "111" => CONFIG(CPUSPEED) <= "0001";   -- 3.5MHz
+                        end case;
+                    elsif REGISTER_MODEL(2 downto 0)  = "110" or  REGISTER_MODEL(2 downto 0)  = "110" then
+                        case REGISTER_CPU(2 downto 0) is
+                            when "000" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "001" => CONFIG(CPUSPEED) <= "0100";   -- 8MHz
+                            when "010" => CONFIG(CPUSPEED) <= "0110";   -- 16MHz
+                            when "011" => CONFIG(CPUSPEED) <= "1000";   -- 32MHz
+                            when "100" => CONFIG(CPUSPEED) <= "1010";   -- 64MHz
+                            when "101" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "110" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                            when "111" => CONFIG(CPUSPEED) <= "0010";   -- 4MHz
+                        end case;
+                    else
+                        CONFIG(CPUSPEED) <= "0000";    -- Default 2MHz
+                    end if;
+                end if;
+    
+                -- Setup the video speed dependent upon model and graphics option. VGA OUT currently
+                -- forces all pixel clocks to 25.175MHz, otherwise the original pixel clock is chosen.
+                --
+                case REGISTER_MODEL(2 downto 0) is
+
+                    -- MZ80K/C/1200/A
+                    when "000" | "001" | "010" | "011" =>
+
+                        case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
+
+                            -- 40x25 mode requires 8MHz clock, Mono and Colour.
+                            when "11000" | "11010" | "11100" | "11101" | "11110" | "11111" =>
+                                CONFIG(VIDSPEED) <= "000";
+
+                            -- 80x25 mode requires 16MHz clock, Mono and Colour.
+                            when "11001" | "11011" =>
+                                CONFIG(VIDSPEED) <= "001";
+
+                            -- VGA Timing 640x480 @ 60Hz
+                            when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
+                                CONFIG(VIDSPEED) <= "100";
+
+                            -- VGA Timing 640x480 @ 75Hz
+                            when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
+                                CONFIG(VIDSPEED) <= "110";
+
+                            -- VGA Timing 640x480 @ 85Hz
+                            when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
+                                CONFIG(VIDSPEED) <= "111";
+                        end case;
+
+                    -- MZ700/MZ800 Models.
+                    when "100" | "101" =>
+                        -- Currently all modes default to one speed!
+                        case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
+
+                            -- 40x25 mode requires 8.8MHz clock, Mono and Colour.
+                            when "11000" | "11010" | "11100" | "11101" | "11110" | "11111" =>
+                                CONFIG(VIDSPEED) <= "010";
+    
+                            -- 80x25 mode requires 17.7MHz clock, Mono and Colour.
+                            when "11001" | "11011" =>
+                                CONFIG(VIDSPEED) <= "011";
+
+                            -- VGA Timing 640x480 @ 60Hz
+                            when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
+                                CONFIG(VIDSPEED) <= "100";
+
+                            -- VGA Timing 640x480 @ 75Hz
+                            when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
+                                CONFIG(VIDSPEED) <= "110";
+
+                            -- VGA Timing 640x480 @ 85Hz
+                            when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
+                                CONFIG(VIDSPEED) <= "111";
+                        end case;
+
+                    -- MZ80B or MZ2200
+                    when "110" | "111" =>
+                        case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
+
+                            -- 80x25 mode requires 16MHz clock, 40x25 requires 8MHz, switched on the CHAR80 signal.
+                            when "11000" | "11001" | "11010" | "11011" | "11100" | "11101" | "11110" | "11111" =>
+                                if CONFIG_CHAR80 = '1' then
+                                    CONFIG(VIDSPEED) <= "001";
+                                else
+                                    CONFIG(VIDSPEED) <= "000";
+                                end if;
+
+                            -- VGA Timing 640x480 @ 60Hz
+                            when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
+                                CONFIG(VIDSPEED) <= "100";
+
+                            -- VGA Timing 640x480 @ 75Hz
+                            when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
+                                CONFIG(VIDSPEED) <= "110";
+
+                            -- VGA Timing 640x480 @ 85Hz
+                            when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
+                                CONFIG(VIDSPEED) <= "111";
+                        end case;
+                end case;
+    
+                -- Setup RTC clock frequency dependent upon model.
+                if REGISTER_MODEL(2 downto 0) = "110" and REGISTER_MODEL(2 downto 0) = "111" then
+                    CONFIG(RTCSPEED) <= "01";
+                elsif REGISTER_MODEL(2 downto 0)  = "100" or  REGISTER_MODEL(2 downto 0)  = "101" then
+                    CONFIG(RTCSPEED) <= "10";
+                else
+                    CONFIG(RTCSPEED) <= "00";
+                end if;
+    
+                if REGISTER_MODEL(2 downto 0)  = "100" then
+                    CONFIG(SNDSPEED) <= "01";
+                elsif REGISTER_MODEL(2 downto 0)  = "101" or  REGISTER_MODEL(2 downto 0)  = "110" then
+                    CONFIG(SNDSPEED) <= "00";
+                elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
+                    CONFIG(SNDSPEED) <= "00";
+                else
+                    CONFIG(SNDSPEED) <= "00";
+                end if;
+    
+                -- Setup the peripheral speed.
+                if REGISTER_MODEL(2 downto 0)  = "101" or  REGISTER_MODEL(2 downto 0)  = "110" then
+                    CONFIG(PERSPEED) <= "00";
+                elsif REGISTER_MODEL(2 downto 0)  = "100" then
+                    CONFIG(PERSPEED) <= "00";
+                elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
+                    CONFIG(PERSPEED) <= "00";
+                else
+                    CONFIG(PERSPEED) <= "00";
+                end if;
+    
+                CONFIG(GRAMIOADDR)   <= REGISTER_DISPLAY2(7 downto 3);
+                CONFIG(VRAMDISABLE)  <= REGISTER_DISPLAY(4);
+                CONFIG(GRAMDISABLE)  <= REGISTER_DISPLAY(5);
+                CONFIG(VRAMWAIT)     <= REGISTER_DISPLAY(6);
+                CONFIG(PCGRAM)       <= REGISTER_DISPLAY(7);
+                CONFIG(VGAMODE)      <= REGISTER_DISPLAY2(1 downto 0);
+                CONFIG(MENUENABLE)   <= REGISTER_DISPLAY3(0);
+                CONFIG(STATUSENABLE) <= REGISTER_DISPLAY3(1);
+                CONFIG(TURBO)        <= REGISTER_CPU(2 downto 0);
+                CONFIG(FASTTAPE)     <= REGISTER_CMT(2 downto 0);
+                CONFIG(BUTTONS)      <= REGISTER_CMT(4 downto 3);
+                CONFIG(CMTASCII_IN)  <= REGISTER_CMT(5);
+                CONFIG(CMTASCII_OUT) <= REGISTER_CMT(6);
+                CONFIG(AUDIOSRC)     <= REGISTER_AUDIO(0);
+                CONFIG(USERROM)      <= REGISTER_USERROM;
+                CONFIG(FDCROM)       <= REGISTER_FDCROM;
+                CONFIG(BOOT_RESET)   <= REGISTER_CPU(7);
+    
+                DEBUG(LEDS_BANK)     <= REGISTER_DEBUG(2 downto 0);
+                DEBUG(LEDS_SUBBANK)  <= REGISTER_DEBUG(5 downto 3);
+                DEBUG(LEDS_ON)       <= REGISTER_DEBUG(6);
+                DEBUG(ENABLED)       <= REGISTER_DEBUG(7);
+                DEBUG(SMPFREQ)       <= REGISTER_DEBUG2(3 downto 0);
+                DEBUG(CPUFREQ)       <= REGISTER_DEBUG2(7 downto 4);
+            end if;
+        end if;
+    end process;
+
+    -- Machine control is just a set of registers holding latched signals to configure machine components.
+    -- A write is made on address 100000000000000000000AAAA to read/write the registers, direction is via the
+    -- RD/WR signals.
+    -- AAAA specifies which register to read/write.
+    --
+    process (COLD_RESET, IOCTL_CLK)
+    begin
+        if COLD_RESET = '1' then
+            REGISTER_MODEL   <= "00000011";   
+            REGISTER_DISPLAY <= "00000000";
+            REGISTER_DISPLAY2<= "00000000";
+            REGISTER_DISPLAY3<= "00000000";
+            REGISTER_CPU     <= "00000000";
+            REGISTER_AUDIO   <= "00000000";
+            REGISTER_CMT     <= "00000000";
+            REGISTER_CMT2    <= "00000000";
+            REGISTER_USERROM <= "00000000";
+            REGISTER_FDCROM  <= "00000000";
+            REGISTER_10      <= "00000000";
+            REGISTER_11      <= "00000000";
+            REGISTER_12      <= "00000000";
+            REGISTER_DEBUG   <= "00000000";
+            REGISTER_DEBUG2  <= "00000000";
+            READ_STATUS      <= (others => '0');
+            RESET_MACHINE    <= '1';
+            CMT_BUS_OUT_LAST <= (others => '0');
+        elsif IOCTL_CLK'event and IOCTL_CLK='1' then
+
+            -- Reset a register if it has been read, ready for next status change.
+            --
+            if READ_STATUS(6) = '1' then
+                REGISTER_CMT2    <= (others => '0');
+            end if;
+
+            -- CMT Register 2, for bits 0,2,3 & 4, they set an active bit, then upon read it is reset.
+            --
+            if CMT_BUS_OUT(APSS_STOP) /= CMT_BUS_OUT_LAST(APSS_STOP) and CMT_BUS_OUT(APSS_STOP) = '1' then
+                REGISTER_CMT2(4) <= CMT_BUS_OUT(APSS_STOP);
+            end if;
+            --if CMT_BUS_OUT(APSS_PLAY) /= CMT_BUS_OUT_LAST(APSS_PLAY) and CMT_BUS_OUT(APSS_PLAY) = '1' then
+                REGISTER_CMT2(3) <= CMT_BUS_OUT(APSS_PLAY);
+            --end if;
+            if CMT_BUS_OUT(APSS_EJECT) /= CMT_BUS_OUT_LAST(APSS_EJECT) and CMT_BUS_OUT(APSS_EJECT) = '1' then
+                REGISTER_CMT2(2) <= '1';
+            end if;
+            REGISTER_CMT2(1)     <= CMT_BUS_OUT(APSS_DIR);
+            if CMT_BUS_OUT(APSS_SEEK) /= CMT_BUS_OUT_LAST(APSS_SEEK) and CMT_BUS_OUT(APSS_SEEK) = '1' then
+                REGISTER_CMT2(0) <= '1';
+            end if;
+            CMT_BUS_OUT_LAST     <= CMT_BUS_OUT;
+            READ_STATUS          <= (others => '0');
+            
+            -- For reading of registers, if no specific signal is required, just read back the output latch.
+            --
+            if IOCTL_ADDR(24) = '1' and IOCTL_RD = '1' then
+                case IOCTL_ADDR(3 downto 0) is
+                    when "0000" => IOCTL_DIN        <= X"000000" & REGISTER_MODEL;          READ_STATUS(0)  <= '1';
+                    when "0001" => IOCTL_DIN        <= X"000000" & REGISTER_DISPLAY;        READ_STATUS(1)  <= '1';
+                    when "0010" => IOCTL_DIN        <= X"000000" & REGISTER_DISPLAY2;       READ_STATUS(2)  <= '1';
+                    when "0011" => IOCTL_DIN        <= X"000000" & REGISTER_DISPLAY3;       READ_STATUS(3)  <= '1';
+                    when "0100" => IOCTL_DIN        <= X"000000" & REGISTER_CPU;            READ_STATUS(4)  <= '1';
+                    when "0101" => IOCTL_DIN        <= X"000000" & REGISTER_AUDIO;          READ_STATUS(5)  <= '1';
+                    when "0110" => IOCTL_DIN        <= X"000000" & CMT_BUS_OUT(7 downto 0); READ_STATUS(6)  <= '1';
+                    when "0111" => IOCTL_DIN        <= X"000000" & REGISTER_CMT2;           READ_STATUS(7)  <= '1';
+                    when "1000" => IOCTL_DIN        <= X"000000" & REGISTER_USERROM;        READ_STATUS(8)  <= '1';
+                    when "1001" => IOCTL_DIN        <= X"000000" & REGISTER_FDCROM;         READ_STATUS(9)  <= '1';
+                    when "1010" => IOCTL_DIN        <= X"000000" & REGISTER_10;             READ_STATUS(10) <= '1';
+                    when "1011" => IOCTL_DIN        <= X"000000" & REGISTER_11;             READ_STATUS(11) <= '1';
+                    when "1100" => IOCTL_DIN        <= X"000000" & REGISTER_12;             READ_STATUS(12) <= '1';
+                    when "1101" => IOCTL_DIN        <= X"000000" & "000000" & std_logic_vector(to_unsigned(NEO_ENABLE, 1)) & std_logic_vector(to_unsigned(DEBUG_ENABLE, 1));
+                    when "1110" => IOCTL_DIN        <= X"000000" & REGISTER_DEBUG;          READ_STATUS(14) <= '1';
+                    when "1111" => IOCTL_DIN        <= X"000000" & REGISTER_DEBUG2;         READ_STATUS(15) <= '1';
+                end case;
+            end if;
+            -- For writing of registers, just assign the input bus to the register.
+            if IOCTL_ADDR(24) = '1' and IOCTL_WR = '1' then
+                case IOCTL_ADDR(3 downto 0) is
+                    when "0000" => 
+                        -- Assign the model data to the register and preset the default display hardware.
+                        REGISTER_MODEL   <= IOCTL_DOUT(7 downto 0);
+                        case IOCTL_DOUT(2 downto 0) is
+                            when "000" | "001" | "010" | "011" =>
+                                 REGISTER_DISPLAY   <= REGISTER_DISPLAY(7 downto 3) & "000";
+                            when "100" | "101" =>
+                                 REGISTER_DISPLAY   <= REGISTER_DISPLAY(7 downto 3) & "010";
+                            when "110" | "111" =>
+                                 REGISTER_DISPLAY   <= REGISTER_DISPLAY(7 downto 3) & "001";
+                        end case;
+                        RESET_MACHINE <= '1';
+                    when "0001" =>
+                        REGISTER_DISPLAY            <= IOCTL_DOUT(7 downto 0);
+
+                        -- Reset display if the mode changes.
+                        if REGISTER_DISPLAY(2 downto 0) /= IOCTL_DOUT(2 downto 0) then
+                            RESET_MACHINE           <= '1';
+                        end if;
+                    when "0010" =>
+                        -- Check the sanity, certain address ranges are blocked by the underlying machine.
+                        --
+                        if IOCTL_DOUT(7 downto 4) /= "1111" and IOCTL_DOUT(7 downto 4) /= "1110" and IOCTL_DOUT(7 downto 4) /= "1101" then
+                            REGISTER_DISPLAY2       <= IOCTL_DOUT(7 downto 0);
+                        end if;
+
+                    when "0011" => REGISTER_DISPLAY3<= IOCTL_DOUT(7 downto 0);
+
+                    when "0100" => REGISTER_CPU     <= IOCTL_DOUT(7 downto 0);
+                                   if REGISTER_CPU(7) = '1' then
+                                       RESET_MACHINE<= '1';
+                                   end if;
+                    when "0101" => REGISTER_AUDIO   <= IOCTL_DOUT(7 downto 0);
+                    when "0110" => REGISTER_CMT     <= IOCTL_DOUT(7 downto 0);
+                    when "0111" => REGISTER_CMT2    <= IOCTL_DOUT(7 downto 0);
+                    when "1000" => REGISTER_USERROM <= IOCTL_DOUT(7 downto 0);
+                    when "1001" => REGISTER_FDCROM  <= IOCTL_DOUT(7 downto 0);
+                    when "1010" => REGISTER_10      <= IOCTL_DOUT(7 downto 0);
+                    when "1011" => REGISTER_11      <= IOCTL_DOUT(7 downto 0);
+                    when "1100" => REGISTER_12      <= IOCTL_DOUT(7 downto 0);
+                    when "1101" => -- Setup register showing configuration, cannot be changed.
+                    when "1110" => REGISTER_DEBUG   <= IOCTL_DOUT(7 downto 0);
+                    when "1111" => REGISTER_DEBUG2  <= IOCTL_DOUT(7 downto 0);
+                end case;
+            end if;
+
+            -- Only allow reset signal to be active for 1 clock cycle, just enough to trigger a system reset.
+            --
+            if RESET_MACHINE = '1' then
+                RESET_MACHINE <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- System reset oneshot, triggered on COLD/WARM reset or a status change.
+    process (CLKBUS(CKMASTER), COLD_RESET, WARM_RESET, RESET_MACHINE)
+    begin
+        if COLD_RESET = '1' or WARM_RESET = '1' or RESET_MACHINE = '1' then
+            if COLD_RESET = '1' then
+                delay <= 15;
+            elsif WARM_RESET = '1' then
+                delay <= 31;
+            else
+                delay <= 31;
+            end if;
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
+            if delay /= 0 then
+                delay <= delay + 1;
+            elsif delay >= 63 then
+                delay <= 0;
+            end if;
+        end if;
+    end process;
+    SYSTEM_RESET <= '1' when delay > 0
+                    else '0';
+end rtl;
diff --git a/common/pll.qip b/common/pll.qip
new file mode 100644
index 0000000..f6e2a4a
--- /dev/null
+++ b/common/pll.qip
@@ -0,0 +1,987 @@
+set_global_assignment -entity "clkgen" -library "pll" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "pll" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../pll.sopcinfo"]
+set_global_assignment -entity "clkgen" -library "pll" -name SLD_INFO "QSYS_NAME pll HAS_SOPCINFO 1 GENERATION_ID 1544470692"
+set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../pll.cmp"]
+set_global_assignment -library "pll" -name SLD_FILE [file join $::quartus(qip_path) "pll.debuginfo"]
+set_global_assignment -entity "clkgen" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../../pll.qsys"]
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_NAME "cGxs"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "cGxs"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU0NDQ3MDY5Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "clkgen" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8y"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MzEuMQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTAy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MzYuMDAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjUuMTc1::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTI2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MzEuNTAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTcuNzM0NDc1::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTc4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MjUuNTY4NjI3IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzU4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MzEuMDk5OTk4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjUuMTc2MTg4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTcuODIxMzQ2IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::OC44NjA4OTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Niw2LDEsMSxmYWxzZSxmYWxzZSxmYWxzZSxmYWxzZSwyNiwyNSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMyLDMxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsNDUsNDQsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw5MCw4OSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDEsMzAsMjAwMCwxNTg2LjA5OTgwMSBNSHosMTY4MTA3MDM2NixnY2xrLGdsYixmYl8xLHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8x"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTYuNzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NDA2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjguMzc1::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::ODEy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTQuMTg3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTYyNA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzI0OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NjQ5Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTYuNzQ4NzY4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjguMzc0Mzg0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTQuMTg3MTkyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::Ny4wOTM1OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::My41NDY3OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NDUsNDUsMTUsMTQsZmFsc2UsZmFsc2UsZmFsc2UsdHJ1ZSw3LDcsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTQsMTQsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMjgsMjgsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNTYsNTYsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTEyLDExMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDc5NC40ODI3NTggTUh6LDEsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8w"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::OA==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::OA==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjU2LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MTIwLjAwMDAwMCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NjQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MzIuNTMzMzI0IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NDg=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::OC4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::OTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::NC4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MTky::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::Mi4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::Mzg0::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MS4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjU1Ljk5OTg3MiBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTA5LjcxNDI1NyBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NjMuOTk5OTgxIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MzEuOTk5OTg5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MTUuOTk5OTk0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::Ny45OTk5OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::My45OTk5OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MS45OTk5OTkgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTUgSGkgRGl2aWRlLEMtQ291bnRlci01IExvdyBEaXZpZGUsQy1Db3VudGVyLTUgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci01IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTUgSW5wdXQgU291cmNlLEMtQ291bnRlci01IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTUgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTYgSGkgRGl2aWRlLEMtQ291bnRlci02IExvdyBEaXZpZGUsQy1Db3VudGVyLTYgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci02IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTYgSW5wdXQgU291cmNlLEMtQ291bnRlci02IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTYgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTcgSGkgRGl2aWRlLEMtQ291bnRlci03IExvdyBEaXZpZGUsQy1Db3VudGVyLTcgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci03IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTcgSW5wdXQgU291cmNlLEMtQ291bnRlci03IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTcgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OCw3LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDIsMSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDQsMywxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDYsNiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMiwxMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyNCwyNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw0OCw0OCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw5Niw5NiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxOTIsMTkyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCw3NjcuOTk5NjcxIE1IeiwxNTQ2MTU5OTY2LGdjbGssZ2xiLGZiXzEscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll" -name VHDL_FILE [file join $::quartus(qip_path) "clkgen.vhd"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.qip"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.qip"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.qip"]
+
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_ENV "Qsys"
diff --git a/common/pll.qsys b/common/pll.qsys
new file mode 100644
index 0000000..ee6e029
--- /dev/null
+++ b/common/pll.qsys
@@ -0,0 +1,783 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element clk_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element pll_0
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element pll_1
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element pll_2
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5CSEBA6U23I7" />
+ <parameter name="deviceFamily" value="Cyclone V" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
+ <interface
+   name="pll_0_outclk1"
+   internal="pll_0.outclk1"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_0_outclk2"
+   internal="pll_0.outclk2"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_0_outclk3"
+   internal="pll_0.outclk3"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_0_outclk4"
+   internal="pll_0.outclk4"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_0_outclk5"
+   internal="pll_0.outclk5"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_0_outclk6"
+   internal="pll_0.outclk6"
+   type="clock"
+   dir="start" />
+ <interface name="pll_0_refclk" internal="pll_0.refclk" type="clock" dir="end" />
+ <interface name="pll_0_reset" internal="pll_0.reset" type="reset" dir="end" />
+ <interface
+   name="pll_1_outclk0"
+   internal="pll_1.outclk0"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_1_outclk1"
+   internal="pll_1.outclk1"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_1_outclk2"
+   internal="pll_1.outclk2"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_1_outclk3"
+   internal="pll_1.outclk3"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_1_outclk4"
+   internal="pll_1.outclk4"
+   type="clock"
+   dir="start" />
+ <interface name="pll_1_reset" internal="pll_1.reset" type="reset" dir="end" />
+ <interface
+   name="pll_2_outclk0"
+   internal="pll_2.outclk0"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_2_outclk1"
+   internal="pll_2.outclk1"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_2_outclk2"
+   internal="pll_2.outclk2"
+   type="clock"
+   dir="start" />
+ <interface
+   name="pll_2_outclk3"
+   internal="pll_2.outclk3"
+   type="clock"
+   dir="start" />
+ <interface name="pll_2_outclk4" internal="pll_2.outclk4" />
+ <interface name="pll_2_reset" internal="pll_2.reset" type="reset" dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
+ <module name="clk_0" kind="clock_source" version="17.1" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module name="pll_0" kind="altera_pll" version="17.1" enabled="1">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device" value="5CSEBA6U23I7" />
+  <parameter name="device_family" value="Cyclone V" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_output_clock_frequency0" value="120.000000 MHz" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency3" value="32.533324 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_number_of_clocks" value="8" />
+  <parameter name="gui_operation_mode" value="normal" />
+  <parameter name="gui_output_clock_frequency0" value="256.0" />
+  <parameter name="gui_output_clock_frequency1" value="112.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="64.0" />
+  <parameter name="gui_output_clock_frequency3" value="32.0" />
+  <parameter name="gui_output_clock_frequency4" value="16.0" />
+  <parameter name="gui_output_clock_frequency5" value="8.0" />
+  <parameter name="gui_output_clock_frequency6" value="4.0" />
+  <parameter name="gui_output_clock_frequency7" value="2.0" />
+  <parameter name="gui_output_clock_frequency8" value="1.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="On" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="gui_pll_mode" value="Fractional-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="50.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="false" />
+ </module>
+ <module name="pll_1" kind="altera_pll" version="17.1" enabled="1">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device" value="5CSEBA6U23I7" />
+  <parameter name="device_family" value="Cyclone V" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_number_of_clocks" value="5" />
+  <parameter name="gui_operation_mode" value="normal" />
+  <parameter name="gui_output_clock_frequency0" value="56.75" />
+  <parameter name="gui_output_clock_frequency1" value="28.375" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="14.1875" />
+  <parameter name="gui_output_clock_frequency3" value="7.09375" />
+  <parameter name="gui_output_clock_frequency4" value="3.546875" />
+  <parameter name="gui_output_clock_frequency5" value="7.09375" />
+  <parameter name="gui_output_clock_frequency6" value="3.546875" />
+  <parameter name="gui_output_clock_frequency7" value="3.546875" />
+  <parameter name="gui_output_clock_frequency8" value="3.546875" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="On" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="256.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="false" />
+ </module>
+ <module name="pll_2" kind="altera_pll" version="17.1" enabled="1">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device" value="5CSEBA6U23I7" />
+  <parameter name="device_family" value="Cyclone V" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_output_clock_frequency0" value="36.000000 MHz" />
+  <parameter name="gui_actual_output_clock_frequency1" value="31.500000 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="25.568627 MHz" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_number_of_clocks" value="4" />
+  <parameter name="gui_operation_mode" value="normal" />
+  <parameter name="gui_output_clock_frequency0" value="31.1" />
+  <parameter name="gui_output_clock_frequency1" value="25.175" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="17.734475" />
+  <parameter name="gui_output_clock_frequency3" value="8.867237" />
+  <parameter name="gui_output_clock_frequency4" value="8.867237" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="On" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="gui_pll_mode" value="Fractional-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="degrees" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="256.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="false" />
+ </module>
+ <connection kind="clock" version="17.1" start="pll_0.outclk0" end="pll_1.refclk" />
+ <connection kind="clock" version="17.1" start="pll_0.outclk0" end="pll_2.refclk" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/common/pll.sopcinfo b/common/pll.sopcinfo
new file mode 100644
index 0000000..8ddc5b2
--- /dev/null
+++ b/common/pll.sopcinfo
@@ -0,0 +1,13411 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="pll" kind="pll" version="1.0" fabric="QSYS">
+ <!-- Format version 17.1 593 (Future versions may contain additional information.) -->
+ <!-- 2018.12.10.19:38:12 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1544470692</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>CYCLONEV</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>5CSEBA6U23I7</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>7</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_PLL_0_REFCLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>pll_0_refclk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_PLL_0_REFCLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>pll_0_refclk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_PLL_0_REFCLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>pll_0_refclk</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>Cyclone V</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module name="clk_0" kind="clock_source" version="17.1" path="clk_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="clockFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockFrequencyKnown">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inputClockFrequency">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk_in</sysinfo_arg>
+  </parameter>
+  <parameter name="resetSynchronousEdges">
+   <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk_in" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>clk</value>
+   </assignment>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="clk_in_reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>reset</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value>clk_in</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>50000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>clk_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="clk_reset" kind="reset_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_n_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+ </module>
+ <module name="pll_0" kind="altera_pll" version="17.1" path="pll_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="debug_print_output">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_use_rbc_taf_method">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="device_family">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="device">
+   <type>java.lang.String</type>
+   <value>5CSEBA6U23I7</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="gui_device_speed_grade">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_mode">
+   <type>java.lang.String</type>
+   <value>Fractional-N PLL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fractional_vco_multiplier">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_reference_clock_frequency">
+   <type>double</type>
+   <value>50.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reference_clock_frequency">
+   <type>java.lang.String</type>
+   <value>50.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_channel_spacing">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_feedback_clock">
+   <type>java.lang.String</type>
+   <value>Global Clock</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_use_locked">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_adv_params">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_number_of_clocks">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_clocks">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_cascade_counters">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_multiply_factor">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_frac_multiply_factor">
+   <type>long</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_n">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter0">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency0">
+   <type>double</type>
+   <value>256.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c0">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor0">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor0">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor0">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>120.000000 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units0">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg0">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift0">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter1">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency1">
+   <type>double</type>
+   <value>112.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c1">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor1">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor1">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor1">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units1">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg1">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift1">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter2">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency2">
+   <type>double</type>
+   <value>64.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c2">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor2">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor2">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor2">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units2">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg2">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift2">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter3">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency3">
+   <type>double</type>
+   <value>32.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c3">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor3">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor3">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor3">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>32.533324 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units3">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg3">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift3">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter4">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency4">
+   <type>double</type>
+   <value>16.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c4">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor4">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor4">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor4">
+   <type>int</type>
+   <value>48</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units4">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg4">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift4">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter5">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency5">
+   <type>double</type>
+   <value>8.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c5">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor5">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor5">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor5">
+   <type>int</type>
+   <value>96</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units5">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg5">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift5">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter6">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency6">
+   <type>double</type>
+   <value>4.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c6">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor6">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor6">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor6">
+   <type>int</type>
+   <value>192</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units6">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg6">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift6">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter7">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency7">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c7">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor7">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor7">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor7">
+   <type>int</type>
+   <value>384</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units7">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg7">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift7">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter8">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency8">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c8">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor8">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units8">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg8">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift8">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter9">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency9">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c9">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor9">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units9">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg9">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift9">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter10">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency10">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c10">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor10">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units10">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg10">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift10">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter11">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency11">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c11">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor11">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units11">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg11">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift11">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter12">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency12">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c12">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor12">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units12">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg12">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift12">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter13">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency13">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c13">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor13">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units13">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg13">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift13">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter14">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency14">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c14">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor14">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units14">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg14">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift14">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter15">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency15">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c15">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor15">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units15">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg15">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift15">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter16">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency16">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c16">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor16">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units16">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift16">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg16">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift16">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter17">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency17">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c17">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor17">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units17">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift17">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg17">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift17">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>255.999872 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift0">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>109.714257 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift1">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>63.999981 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift2">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>31.999989 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift3">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>15.999994 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift4">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>7.999996 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift5">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>3.999998 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift6">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>1.999999 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift7">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift8">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift9">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift10">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift11">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift12">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift13">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift14">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift15">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift16">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift17">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_auto_reset">
+   <type>java.lang.String</type>
+   <value>On</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_bandwidth_preset">
+   <type>java.lang.String</type>
+   <value>Auto</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_reconf">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_dps_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_phout_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phout_division">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vcoph_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_type">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_subtype">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_hi_div">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_lo_div">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_hi_div">
+   <type>int</type>
+   <value>256</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_lo_div">
+   <type>int</type>
+   <value>256</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div0">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src0">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en0">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div1">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div1">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src1">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en1">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div2">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div2">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src2">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div3">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div3">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src3">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div4">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div4">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src4">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div5">
+   <type>int</type>
+   <value>48</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div5">
+   <type>int</type>
+   <value>48</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src5">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div6">
+   <type>int</type>
+   <value>96</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div6">
+   <type>int</type>
+   <value>96</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src6">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div7">
+   <type>int</type>
+   <value>192</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div7">
+   <type>int</type>
+   <value>192</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src7">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst8">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src8">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en8">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en8">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst9">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src9">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en9">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en9">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst10">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src10">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en10">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en10">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst11">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src11">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en11">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en11">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst12">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src12">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en12">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en12">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst13">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src13">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en13">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en13">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst14">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src14">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en14">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en14">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst15">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src15">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en15">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en15">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst16">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src16">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en16">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en16">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst17">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src17">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en17">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en17">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vco_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_cp_current">
+   <type>int</type>
+   <value>20</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_bwctrl">
+   <type>int</type>
+   <value>4000</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_output_clk_frequency">
+   <type>java.lang.String</type>
+   <value>767.999671 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_division">
+   <type>java.lang.String</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mimic_fbclk_type">
+   <type>java.lang.String</type>
+   <value>gclk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_1">
+   <type>java.lang.String</type>
+   <value>glb</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_2">
+   <type>java.lang.String</type>
+   <value>fb_1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_m_cnt_in_src">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_slf_rst">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_list">
+   <type>[Ljava.lang.String;</type>
+   <value>M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,C-Counter-5 Hi Divide,C-Counter-5 Low Divide,C-Counter-5 Coarse Phase Shift,C-Counter-5 VCO Phase Tap,C-Counter-5 Input Source,C-Counter-5 Bypass Enable,C-Counter-5 Odd Divide Enable,C-Counter-6 Hi Divide,C-Counter-6 Low Divide,C-Counter-6 Coarse Phase Shift,C-Counter-6 VCO Phase Tap,C-Counter-6 Input Source,C-Counter-6 Bypass Enable,C-Counter-6 Odd Divide Enable,C-Counter-7 Hi Divide,C-Counter-7 Low Divide,C-Counter-7 Coarse Phase Shift,C-Counter-7 VCO Phase Tap,C-Counter-7 Input Source,C-Counter-7 Bypass Enable,C-Counter-7 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_values">
+   <type>[Ljava.lang.String;</type>
+   <value>8,7,256,256,false,true,true,false,2,1,1,0,ph_mux_clk,false,true,4,3,1,0,ph_mux_clk,false,true,6,6,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,24,24,1,0,ph_mux_clk,false,false,48,48,1,0,ph_mux_clk,false,false,96,96,1,0,ph_mux_clk,false,false,192,192,1,0,ph_mux_clk,false,false,1,20,4000,767.999671 MHz,1546159966,gclk,glb,fb_1,ph_mux_clk,true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_mif_generate">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_mif_dps">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_cntr">
+   <type>java.lang.String</type>
+   <value>C0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_num">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_dir">
+   <type>java.lang.String</type>
+   <value>Positive</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk_switch">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk1_frequency">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_mode">
+   <type>java.lang.String</type>
+   <value>Automatic Switchover</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_delay">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_active_clk">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_clk_bad">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="refclk1_frequency">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_loss_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_manu_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_auto_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_1_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_sw_dly">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_outclk_index">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_0_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_cascading_mode">
+   <type>java.lang.String</type>
+   <value>Create an adjpllin signal to connect with an upstream PLL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="refclk" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>refclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="outclk0" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>255999872</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>pll_1</moduleName>
+    <slaveName>refclk</slaveName>
+    <name>pll_1.refclk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>pll_2</moduleName>
+    <slaveName>refclk</slaveName>
+    <name>pll_2.refclk</name>
+   </clockDomainMember>
+  </interface>
+  <interface name="outclk1" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>109714257</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk2" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>63999981</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk3" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>31999989</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk4" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>15999994</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_4</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk5" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>7999996</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_5</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk6" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>3999998</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_6</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk7" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>1999999</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_7</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <module name="pll_1" kind="altera_pll" version="17.1" path="pll_1">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="debug_print_output">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_use_rbc_taf_method">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="device_family">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="device">
+   <type>java.lang.String</type>
+   <value>5CSEBA6U23I7</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="gui_device_speed_grade">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_mode">
+   <type>java.lang.String</type>
+   <value>Integer-N PLL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fractional_vco_multiplier">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_reference_clock_frequency">
+   <type>double</type>
+   <value>256.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reference_clock_frequency">
+   <type>java.lang.String</type>
+   <value>256.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_channel_spacing">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_feedback_clock">
+   <type>java.lang.String</type>
+   <value>Global Clock</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_use_locked">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_adv_params">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_number_of_clocks">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_clocks">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_cascade_counters">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_multiply_factor">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_frac_multiply_factor">
+   <type>long</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_n">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter0">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency0">
+   <type>double</type>
+   <value>56.75</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c0">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor0">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor0">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor0">
+   <type>int</type>
+   <value>406</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units0">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg0">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift0">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter1">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency1">
+   <type>double</type>
+   <value>28.375</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c1">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor1">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor1">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor1">
+   <type>int</type>
+   <value>812</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units1">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg1">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift1">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter2">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency2">
+   <type>double</type>
+   <value>14.1875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c2">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor2">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor2">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor2">
+   <type>int</type>
+   <value>1624</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units2">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg2">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift2">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter3">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency3">
+   <type>double</type>
+   <value>7.09375</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c3">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor3">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor3">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor3">
+   <type>int</type>
+   <value>3248</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units3">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg3">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift3">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter4">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency4">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c4">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor4">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor4">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor4">
+   <type>int</type>
+   <value>6496</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units4">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg4">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift4">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter5">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency5">
+   <type>double</type>
+   <value>7.09375</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c5">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor5">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units5">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg5">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift5">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter6">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency6">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c6">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor6">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units6">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg6">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift6">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter7">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency7">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c7">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor7">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units7">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg7">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift7">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter8">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency8">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c8">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor8">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units8">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg8">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift8">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter9">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency9">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c9">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor9">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units9">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg9">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift9">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter10">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency10">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c10">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor10">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units10">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg10">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift10">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter11">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency11">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c11">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor11">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units11">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg11">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift11">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter12">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency12">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c12">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor12">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units12">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg12">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift12">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter13">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency13">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c13">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor13">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units13">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg13">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift13">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter14">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency14">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c14">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor14">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units14">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg14">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift14">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter15">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency15">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c15">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor15">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units15">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg15">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift15">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter16">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency16">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c16">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor16">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units16">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift16">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg16">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift16">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter17">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency17">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c17">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor17">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units17">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift17">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg17">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift17">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>56.748768 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift0">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>28.374384 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift1">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>14.187192 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift2">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>7.093596 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift3">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>3.546798 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift4">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift5">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift6">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift7">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift8">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift9">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift10">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift11">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift12">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift13">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift14">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift15">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift16">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift17">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_auto_reset">
+   <type>java.lang.String</type>
+   <value>On</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_bandwidth_preset">
+   <type>java.lang.String</type>
+   <value>Auto</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_reconf">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_dps_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_phout_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phout_division">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vcoph_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_type">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_subtype">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_hi_div">
+   <type>int</type>
+   <value>45</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_lo_div">
+   <type>int</type>
+   <value>45</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_hi_div">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_lo_div">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div0">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div0">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src0">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div1">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div1">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src1">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div2">
+   <type>int</type>
+   <value>28</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div2">
+   <type>int</type>
+   <value>28</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src2">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div3">
+   <type>int</type>
+   <value>56</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div3">
+   <type>int</type>
+   <value>56</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src3">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div4">
+   <type>int</type>
+   <value>112</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div4">
+   <type>int</type>
+   <value>112</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src4">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src5">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en5">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src6">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en6">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src7">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en7">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst8">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src8">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en8">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en8">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst9">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src9">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en9">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en9">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst10">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src10">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en10">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en10">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst11">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src11">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en11">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en11">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst12">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src12">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en12">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en12">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst13">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src13">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en13">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en13">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst14">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src14">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en14">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en14">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst15">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src15">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en15">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en15">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst16">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src16">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en16">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en16">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst17">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src17">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en17">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en17">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vco_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_cp_current">
+   <type>int</type>
+   <value>20</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_bwctrl">
+   <type>int</type>
+   <value>10000</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_output_clk_frequency">
+   <type>java.lang.String</type>
+   <value>794.482758 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_division">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mimic_fbclk_type">
+   <type>java.lang.String</type>
+   <value>gclk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_1">
+   <type>java.lang.String</type>
+   <value>glb</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_2">
+   <type>java.lang.String</type>
+   <value>fb_1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_m_cnt_in_src">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_slf_rst">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_list">
+   <type>[Ljava.lang.String;</type>
+   <value>M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_values">
+   <type>[Ljava.lang.String;</type>
+   <value>45,45,15,14,false,false,false,true,7,7,1,0,ph_mux_clk,false,false,14,14,1,0,ph_mux_clk,false,false,28,28,1,0,ph_mux_clk,false,false,56,56,1,0,ph_mux_clk,false,false,112,112,1,0,ph_mux_clk,false,false,1,20,10000,794.482758 MHz,1,gclk,glb,fb_1,ph_mux_clk,true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_mif_generate">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_mif_dps">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_cntr">
+   <type>java.lang.String</type>
+   <value>C0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_num">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_dir">
+   <type>java.lang.String</type>
+   <value>Positive</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk_switch">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk1_frequency">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_mode">
+   <type>java.lang.String</type>
+   <value>Automatic Switchover</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_delay">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_active_clk">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_clk_bad">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="refclk1_frequency">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_loss_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_manu_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_auto_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_1_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_sw_dly">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_outclk_index">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_0_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_cascading_mode">
+   <type>java.lang.String</type>
+   <value>Create an adjpllin signal to connect with an upstream PLL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="refclk" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>refclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="outclk0" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>56748768</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk1" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>28374384</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk2" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>14187192</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk3" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>7093596</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk4" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>3546798</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_4</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <module name="pll_2" kind="altera_pll" version="17.1" path="pll_2">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="debug_print_output">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_use_rbc_taf_method">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="device_family">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="device">
+   <type>java.lang.String</type>
+   <value>5CSEBA6U23I7</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="gui_device_speed_grade">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_mode">
+   <type>java.lang.String</type>
+   <value>Fractional-N PLL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fractional_vco_multiplier">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_reference_clock_frequency">
+   <type>double</type>
+   <value>256.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reference_clock_frequency">
+   <type>java.lang.String</type>
+   <value>256.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_channel_spacing">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_feedback_clock">
+   <type>java.lang.String</type>
+   <value>Global Clock</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_use_locked">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_adv_params">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_number_of_clocks">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_clocks">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_cascade_counters">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_multiply_factor">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_frac_multiply_factor">
+   <type>long</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_n">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter0">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency0">
+   <type>double</type>
+   <value>31.1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c0">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor0">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor0">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor0">
+   <type>int</type>
+   <value>102</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>36.000000 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units0">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg0">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift0">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter1">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency1">
+   <type>double</type>
+   <value>25.175</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c1">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor1">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor1">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor1">
+   <type>int</type>
+   <value>126</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>31.500000 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units1">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg1">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift1">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter2">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency2">
+   <type>double</type>
+   <value>17.734475</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c2">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor2">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor2">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor2">
+   <type>int</type>
+   <value>178</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>25.568627 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units2">
+   <type>java.lang.String</type>
+   <value>degrees</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg2">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift2">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter3">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency3">
+   <type>double</type>
+   <value>8.867237</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c3">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor3">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor3">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor3">
+   <type>int</type>
+   <value>358</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units3">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg3">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift3">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter4">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency4">
+   <type>double</type>
+   <value>8.867237</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c4">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor4">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units4">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg4">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift4">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter5">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency5">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c5">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor5">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units5">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg5">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift5">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter6">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency6">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c6">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor6">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units6">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg6">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift6">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter7">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency7">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c7">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor7">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units7">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg7">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift7">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter8">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency8">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c8">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor8">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units8">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg8">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift8">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter9">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency9">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c9">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor9">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units9">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg9">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift9">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter10">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency10">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c10">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor10">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units10">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg10">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift10">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter11">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency11">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c11">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor11">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units11">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg11">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift11">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter12">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency12">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c12">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor12">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units12">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg12">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift12">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter13">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency13">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c13">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor13">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units13">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg13">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift13">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter14">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency14">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c14">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor14">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units14">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg14">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift14">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter15">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency15">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c15">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor15">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units15">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg15">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift15">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter16">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency16">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c16">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor16">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units16">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift16">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg16">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift16">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter17">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency17">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c17">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor17">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units17">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift17">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg17">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift17">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>31.099998 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift0">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>25.176188 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift1">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>17.821346 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift2">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>8.860892 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift3">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift4">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift5">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift6">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift7">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift8">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift9">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift10">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift11">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift12">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift13">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift14">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift15">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift16">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift17">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_auto_reset">
+   <type>java.lang.String</type>
+   <value>On</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_bandwidth_preset">
+   <type>java.lang.String</type>
+   <value>Auto</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_reconf">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_dps_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_phout_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phout_division">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vcoph_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_type">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_subtype">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_hi_div">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_lo_div">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_hi_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_lo_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div0">
+   <type>int</type>
+   <value>26</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div0">
+   <type>int</type>
+   <value>25</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src0">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en0">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div1">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div1">
+   <type>int</type>
+   <value>31</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src1">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en1">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div2">
+   <type>int</type>
+   <value>45</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div2">
+   <type>int</type>
+   <value>44</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src2">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en2">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div3">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div3">
+   <type>int</type>
+   <value>89</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src3">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en3">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src4">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en4">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src5">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en5">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src6">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en6">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src7">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en7">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst8">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src8">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en8">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en8">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst9">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src9">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en9">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en9">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst10">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src10">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en10">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en10">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst11">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src11">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en11">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en11">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst12">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src12">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en12">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en12">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst13">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src13">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en13">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en13">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst14">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src14">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en14">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en14">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst15">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src15">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en15">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en15">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst16">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src16">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en16">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en16">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst17">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src17">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en17">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en17">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vco_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_cp_current">
+   <type>int</type>
+   <value>30</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_bwctrl">
+   <type>int</type>
+   <value>2000</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_output_clk_frequency">
+   <type>java.lang.String</type>
+   <value>1586.099801 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_division">
+   <type>java.lang.String</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mimic_fbclk_type">
+   <type>java.lang.String</type>
+   <value>gclk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_1">
+   <type>java.lang.String</type>
+   <value>glb</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_2">
+   <type>java.lang.String</type>
+   <value>fb_1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_m_cnt_in_src">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_slf_rst">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_list">
+   <type>[Ljava.lang.String;</type>
+   <value>M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_values">
+   <type>[Ljava.lang.String;</type>
+   <value>6,6,1,1,false,false,false,false,26,25,1,0,ph_mux_clk,false,true,32,31,1,0,ph_mux_clk,false,true,45,44,1,0,ph_mux_clk,false,true,90,89,1,0,ph_mux_clk,false,true,1,30,2000,1586.099801 MHz,1681070366,gclk,glb,fb_1,ph_mux_clk,true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_mif_generate">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_mif_dps">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_cntr">
+   <type>java.lang.String</type>
+   <value>C0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_num">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_dir">
+   <type>java.lang.String</type>
+   <value>Positive</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk_switch">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk1_frequency">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_mode">
+   <type>java.lang.String</type>
+   <value>Automatic Switchover</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_delay">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_active_clk">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_clk_bad">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="refclk1_frequency">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_loss_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_manu_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_auto_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_1_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_sw_dly">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_outclk_index">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_0_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_cascading_mode">
+   <type>java.lang.String</type>
+   <value>Create an adjpllin signal to connect with an upstream PLL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="refclk" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>refclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="outclk0" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>31099998</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk1" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>25176188</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk2" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>17821346</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk3" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>8860892</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <connection
+   name="pll_0.outclk0/pll_1.refclk"
+   kind="clock"
+   version="17.1"
+   start="pll_0.outclk0"
+   end="pll_1.refclk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>pll_0</startModule>
+  <startConnectionPoint>outclk0</startConnectionPoint>
+  <endModule>pll_1</endModule>
+  <endConnectionPoint>refclk</endConnectionPoint>
+ </connection>
+ <connection
+   name="pll_0.outclk0/pll_2.refclk"
+   kind="clock"
+   version="17.1"
+   start="pll_0.outclk0"
+   end="pll_2.refclk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>pll_0</startModule>
+  <startConnectionPoint>outclk0</startConnectionPoint>
+  <endModule>pll_2</endModule>
+  <endConnectionPoint>refclk</endConnectionPoint>
+ </connection>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Clock Source</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Output</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>altera_pll</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Altera PLL</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>17</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>clock</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Clock Connection</displayName>
+  <version>17.1</version>
+ </plugin>
+ <reportVersion>17.1 593</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/common/pll/pll.bsf b/common/pll/pll.bsf
new file mode 100644
index 0000000..e40613b
--- /dev/null
+++ b/common/pll/pll.bsf
@@ -0,0 +1,268 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2017  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 664)
+	(text "pll" (rect 122 -1 129 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 648 20 660)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
+		(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 96 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "pll_0_refclk_clk" (rect 0 0 62 12)(font "Arial" (font_size 8)))
+		(text "pll_0_refclk_clk" (rect 4 101 100 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 96 112)(line_width 1))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "pll_0_reset_reset" (rect 0 0 69 12)(font "Arial" (font_size 8)))
+		(text "pll_0_reset_reset" (rect 4 141 106 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 96 152)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "pll_1_reset_reset" (rect 0 0 68 12)(font "Arial" (font_size 8)))
+		(text "pll_1_reset_reset" (rect 4 181 106 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 96 192)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "pll_2_reset_reset" (rect 0 0 69 12)(font "Arial" (font_size 8)))
+		(text "pll_2_reset_reset" (rect 4 221 106 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 96 232)(line_width 1))
+	)
+	(port
+		(pt 0 272)
+		(input)
+		(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
+		(text "reset_reset_n" (rect 4 261 82 272)(font "Arial" (font_size 8)))
+		(line (pt 0 272)(pt 96 272)(line_width 1))
+	)
+	(port
+		(pt 256 72)
+		(output)
+		(text "pll_0_outclk1_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
+		(text "pll_0_outclk1_clk" (rect 172 61 274 72)(font "Arial" (font_size 8)))
+		(line (pt 256 72)(pt 160 72)(line_width 1))
+	)
+	(port
+		(pt 256 112)
+		(output)
+		(text "pll_0_outclk2_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_0_outclk2_clk" (rect 170 101 272 112)(font "Arial" (font_size 8)))
+		(line (pt 256 112)(pt 160 112)(line_width 1))
+	)
+	(port
+		(pt 256 152)
+		(output)
+		(text "pll_0_outclk3_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_0_outclk3_clk" (rect 170 141 272 152)(font "Arial" (font_size 8)))
+		(line (pt 256 152)(pt 160 152)(line_width 1))
+	)
+	(port
+		(pt 256 192)
+		(output)
+		(text "pll_0_outclk4_clk" (rect 0 0 68 12)(font "Arial" (font_size 8)))
+		(text "pll_0_outclk4_clk" (rect 170 181 272 192)(font "Arial" (font_size 8)))
+		(line (pt 256 192)(pt 160 192)(line_width 1))
+	)
+	(port
+		(pt 256 232)
+		(output)
+		(text "pll_0_outclk5_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_0_outclk5_clk" (rect 170 221 272 232)(font "Arial" (font_size 8)))
+		(line (pt 256 232)(pt 160 232)(line_width 1))
+	)
+	(port
+		(pt 256 272)
+		(output)
+		(text "pll_0_outclk6_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_0_outclk6_clk" (rect 170 261 272 272)(font "Arial" (font_size 8)))
+		(line (pt 256 272)(pt 160 272)(line_width 1))
+	)
+	(port
+		(pt 256 312)
+		(output)
+		(text "pll_1_outclk0_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
+		(text "pll_1_outclk0_clk" (rect 172 301 274 312)(font "Arial" (font_size 8)))
+		(line (pt 256 312)(pt 160 312)(line_width 1))
+	)
+	(port
+		(pt 256 352)
+		(output)
+		(text "pll_1_outclk1_clk" (rect 0 0 64 12)(font "Arial" (font_size 8)))
+		(text "pll_1_outclk1_clk" (rect 174 341 276 352)(font "Arial" (font_size 8)))
+		(line (pt 256 352)(pt 160 352)(line_width 1))
+	)
+	(port
+		(pt 256 392)
+		(output)
+		(text "pll_1_outclk2_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
+		(text "pll_1_outclk2_clk" (rect 172 381 274 392)(font "Arial" (font_size 8)))
+		(line (pt 256 392)(pt 160 392)(line_width 1))
+	)
+	(port
+		(pt 256 432)
+		(output)
+		(text "pll_1_outclk3_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
+		(text "pll_1_outclk3_clk" (rect 172 421 274 432)(font "Arial" (font_size 8)))
+		(line (pt 256 432)(pt 160 432)(line_width 1))
+	)
+	(port
+		(pt 256 472)
+		(output)
+		(text "pll_1_outclk4_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_1_outclk4_clk" (rect 172 461 274 472)(font "Arial" (font_size 8)))
+		(line (pt 256 472)(pt 160 472)(line_width 1))
+	)
+	(port
+		(pt 256 512)
+		(output)
+		(text "pll_2_outclk0_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_2_outclk0_clk" (rect 170 501 272 512)(font "Arial" (font_size 8)))
+		(line (pt 256 512)(pt 160 512)(line_width 1))
+	)
+	(port
+		(pt 256 552)
+		(output)
+		(text "pll_2_outclk1_clk" (rect 0 0 66 12)(font "Arial" (font_size 8)))
+		(text "pll_2_outclk1_clk" (rect 172 541 274 552)(font "Arial" (font_size 8)))
+		(line (pt 256 552)(pt 160 552)(line_width 1))
+	)
+	(port
+		(pt 256 592)
+		(output)
+		(text "pll_2_outclk2_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_2_outclk2_clk" (rect 170 581 272 592)(font "Arial" (font_size 8)))
+		(line (pt 256 592)(pt 160 592)(line_width 1))
+	)
+	(port
+		(pt 256 632)
+		(output)
+		(text "pll_2_outclk3_clk" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "pll_2_outclk3_clk" (rect 170 621 272 632)(font "Arial" (font_size 8)))
+		(line (pt 256 632)(pt 160 632)(line_width 1))
+	)
+	(drawing
+		(text "clk" (rect 81 43 180 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 101 67 220 144)(font "Arial" (color 0 0 0)))
+		(text "pll_0_outclk1" (rect 161 43 400 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 67 308 144)(font "Arial" (color 0 0 0)))
+		(text "pll_0_outclk2" (rect 161 83 400 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 107 308 224)(font "Arial" (color 0 0 0)))
+		(text "pll_0_outclk3" (rect 161 123 400 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 147 308 304)(font "Arial" (color 0 0 0)))
+		(text "pll_0_outclk4" (rect 161 163 400 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 187 308 384)(font "Arial" (color 0 0 0)))
+		(text "pll_0_outclk5" (rect 161 203 400 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 227 308 464)(font "Arial" (color 0 0 0)))
+		(text "pll_0_outclk6" (rect 161 243 400 499)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 267 308 544)(font "Arial" (color 0 0 0)))
+		(text "pll_0_refclk" (rect 28 83 128 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 101 107 220 224)(font "Arial" (color 0 0 0)))
+		(text "pll_0_reset" (rect 31 123 128 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 101 147 232 304)(font "Arial" (color 0 0 0)))
+		(text "pll_1_outclk0" (rect 161 283 400 579)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 307 308 624)(font "Arial" (color 0 0 0)))
+		(text "pll_1_outclk1" (rect 161 323 400 659)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 347 308 704)(font "Arial" (color 0 0 0)))
+		(text "pll_1_outclk2" (rect 161 363 400 739)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 387 308 784)(font "Arial" (color 0 0 0)))
+		(text "pll_1_outclk3" (rect 161 403 400 819)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 427 308 864)(font "Arial" (color 0 0 0)))
+		(text "pll_1_outclk4" (rect 161 443 400 899)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 467 308 944)(font "Arial" (color 0 0 0)))
+		(text "pll_1_reset" (rect 33 163 132 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 101 187 232 384)(font "Arial" (color 0 0 0)))
+		(text "pll_2_outclk0" (rect 161 483 400 979)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 507 308 1024)(font "Arial" (color 0 0 0)))
+		(text "pll_2_outclk1" (rect 161 523 400 1059)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 547 308 1104)(font "Arial" (color 0 0 0)))
+		(text "pll_2_outclk2" (rect 161 563 400 1139)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 587 308 1184)(font "Arial" (color 0 0 0)))
+		(text "pll_2_outclk3" (rect 161 603 400 1219)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 145 627 308 1264)(font "Arial" (color 0 0 0)))
+		(text "pll_2_reset" (rect 31 203 128 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 101 227 232 464)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 67 243 164 499)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset_n" (rect 101 267 244 544)(font "Arial" (color 0 0 0)))
+		(text " pll " (rect 244 648 518 1306)(font "Arial" ))
+		(line (pt 96 32)(pt 160 32)(line_width 1))
+		(line (pt 160 32)(pt 160 648)(line_width 1))
+		(line (pt 96 648)(pt 160 648)(line_width 1))
+		(line (pt 96 32)(pt 96 648)(line_width 1))
+		(line (pt 97 52)(pt 97 76)(line_width 1))
+		(line (pt 98 52)(pt 98 76)(line_width 1))
+		(line (pt 159 52)(pt 159 76)(line_width 1))
+		(line (pt 158 52)(pt 158 76)(line_width 1))
+		(line (pt 159 92)(pt 159 116)(line_width 1))
+		(line (pt 158 92)(pt 158 116)(line_width 1))
+		(line (pt 159 132)(pt 159 156)(line_width 1))
+		(line (pt 158 132)(pt 158 156)(line_width 1))
+		(line (pt 159 172)(pt 159 196)(line_width 1))
+		(line (pt 158 172)(pt 158 196)(line_width 1))
+		(line (pt 159 212)(pt 159 236)(line_width 1))
+		(line (pt 158 212)(pt 158 236)(line_width 1))
+		(line (pt 159 252)(pt 159 276)(line_width 1))
+		(line (pt 158 252)(pt 158 276)(line_width 1))
+		(line (pt 97 92)(pt 97 116)(line_width 1))
+		(line (pt 98 92)(pt 98 116)(line_width 1))
+		(line (pt 97 132)(pt 97 156)(line_width 1))
+		(line (pt 98 132)(pt 98 156)(line_width 1))
+		(line (pt 159 292)(pt 159 316)(line_width 1))
+		(line (pt 158 292)(pt 158 316)(line_width 1))
+		(line (pt 159 332)(pt 159 356)(line_width 1))
+		(line (pt 158 332)(pt 158 356)(line_width 1))
+		(line (pt 159 372)(pt 159 396)(line_width 1))
+		(line (pt 158 372)(pt 158 396)(line_width 1))
+		(line (pt 159 412)(pt 159 436)(line_width 1))
+		(line (pt 158 412)(pt 158 436)(line_width 1))
+		(line (pt 159 452)(pt 159 476)(line_width 1))
+		(line (pt 158 452)(pt 158 476)(line_width 1))
+		(line (pt 97 172)(pt 97 196)(line_width 1))
+		(line (pt 98 172)(pt 98 196)(line_width 1))
+		(line (pt 159 492)(pt 159 516)(line_width 1))
+		(line (pt 158 492)(pt 158 516)(line_width 1))
+		(line (pt 159 532)(pt 159 556)(line_width 1))
+		(line (pt 158 532)(pt 158 556)(line_width 1))
+		(line (pt 159 572)(pt 159 596)(line_width 1))
+		(line (pt 158 572)(pt 158 596)(line_width 1))
+		(line (pt 159 612)(pt 159 636)(line_width 1))
+		(line (pt 158 612)(pt 158 636)(line_width 1))
+		(line (pt 97 212)(pt 97 236)(line_width 1))
+		(line (pt 98 212)(pt 98 236)(line_width 1))
+		(line (pt 97 252)(pt 97 276)(line_width 1))
+		(line (pt 98 252)(pt 98 276)(line_width 1))
+		(line (pt 0 0)(pt 256 0)(line_width 1))
+		(line (pt 256 0)(pt 256 664)(line_width 1))
+		(line (pt 0 664)(pt 256 664)(line_width 1))
+		(line (pt 0 0)(pt 0 664)(line_width 1))
+	)
+)
diff --git a/common/pll/pll.cmp b/common/pll/pll.cmp
new file mode 100644
index 0000000..dbbe056
--- /dev/null
+++ b/common/pll/pll.cmp
@@ -0,0 +1,26 @@
+	component pll is
+		port (
+			clk_clk           : in  std_logic := 'X'; -- clk
+			pll_0_outclk1_clk : out std_logic;        -- clk
+			pll_0_outclk2_clk : out std_logic;        -- clk
+			pll_0_outclk3_clk : out std_logic;        -- clk
+			pll_0_outclk4_clk : out std_logic;        -- clk
+			pll_0_outclk5_clk : out std_logic;        -- clk
+			pll_0_outclk6_clk : out std_logic;        -- clk
+			pll_0_refclk_clk  : in  std_logic := 'X'; -- clk
+			pll_0_reset_reset : in  std_logic := 'X'; -- reset
+			pll_1_outclk0_clk : out std_logic;        -- clk
+			pll_1_outclk1_clk : out std_logic;        -- clk
+			pll_1_outclk2_clk : out std_logic;        -- clk
+			pll_1_outclk3_clk : out std_logic;        -- clk
+			pll_1_outclk4_clk : out std_logic;        -- clk
+			pll_1_reset_reset : in  std_logic := 'X'; -- reset
+			pll_2_outclk0_clk : out std_logic;        -- clk
+			pll_2_outclk1_clk : out std_logic;        -- clk
+			pll_2_outclk2_clk : out std_logic;        -- clk
+			pll_2_outclk3_clk : out std_logic;        -- clk
+			pll_2_reset_reset : in  std_logic := 'X'; -- reset
+			reset_reset_n     : in  std_logic := 'X'  -- reset_n
+		);
+	end component pll;
+
diff --git a/common/pll/pll.html b/common/pll/pll.html
new file mode 100644
index 0000000..956be9a
--- /dev/null
+++ b/common/pll/pll.html
@@ -0,0 +1,5938 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+  <title>datasheet for pll</title>
+  <style type="text/css">
+body { font-family:arial ;}
+a { text-decoration:underline ; color:#003000 ;}
+a:hover { text-decoration:underline ; color:0030f0 ;}
+td { padding : 5px ;}
+table.topTitle { width:100% ;}
+table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
+table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
+table.blueBar { width : 100% ; border-spacing : 0px ;}
+table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
+table.blueBar td.l { text-align : left ;}
+table.blueBar td.r { text-align : right ;}
+table.items { width:100% ; border-collapse:collapse ;}
+table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
+table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
+div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ; font-size:12px ;}
+body { font-family:arial ;}
+table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
+table.x td { border:1px solid #bbb ;}
+td.tableTitle { font-weight:bold ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ;}
+table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
+table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
+table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
+table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
+table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
+table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
+table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
+table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
+table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
+table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
+table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
+table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
+table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
+table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
+.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
+.flowbox { display:inline-block ;}
+.parametersbox table { font-size:10px ;}
+td.parametername { font-style:italic ;}
+td.parametervalue { font-weight:bold ;}
+div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
+ </head>
+ <body>
+  <table class="topTitle">
+   <tr>
+    <td class="l">pll</td>
+    <td class="r">
+     <br/>
+     <br/>
+    </td>
+   </tr>
+  </table>
+  <table class="blueBar">
+   <tr>
+    <td class="l">2018.12.10.19:38:12</td>
+    <td class="r">Datasheet</td>
+   </tr>
+  </table>
+  <div style="width:100% ;  height:10px"> </div>
+  <div class="label">Overview</div>
+  <div class="greydiv">
+   <div style="display:inline-block ; text-align:left">
+    <table class="connectionboxes">
+     <tr>
+      <td class="lefthandwire">&#160;&#160;clk_0&#160;</td>
+      <td class="main" rowspan="2">pll</td>
+     </tr>
+     <tr style="height:6px">
+      <td></td>
+     </tr>
+    </table>
+   </div><span style="display:inline-block ; width:28px"> </span>
+   <div style="display:inline-block ; text-align:left"><span>
+     <br/></span>
+   </div>
+  </div>
+  <div style="width:100% ;  height:10px"> </div>
+  <div class="label">Memory Map</div>
+  <table class="mmap">
+   <tr>
+    <td class="empty" rowspan="2"></td>
+   </tr>
+  </table>
+  <a name="module_clk_0"> </a>
+  <div>
+   <hr/>
+   <h2>clk_0</h2>clock_source v17.1
+   <br/>
+   <br/>
+   <br/>
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Parameters</h2>
+      <table>
+       <tr>
+        <td class="parametername">clockFrequency</td>
+        <td class="parametervalue">50000000</td>
+       </tr>
+       <tr>
+        <td class="parametername">clockFrequencyKnown</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">inputClockFrequency</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">resetSynchronousEdges</td>
+        <td class="parametervalue">NONE</td>
+       </tr>
+       <tr>
+        <td class="parametername">deviceFamily</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">generateLegacySim</td>
+        <td class="parametervalue">false</td>
+       </tr>
+      </table>
+     </td>
+    </tr>
+   </table>&#160;&#160;
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Software Assignments</h2>(none)</td>
+    </tr>
+   </table>
+  </div>
+  <a name="module_pll_0"> </a>
+  <div>
+   <hr/>
+   <h2>pll_0</h2>altera_pll v17.1
+   <br/>
+   <br/>
+   <br/>
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Parameters</h2>
+      <table>
+       <tr>
+        <td class="parametername">debug_print_output</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">debug_use_rbc_taf_method</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">device_family</td>
+        <td class="parametervalue">CYCLONEV</td>
+       </tr>
+       <tr>
+        <td class="parametername">device</td>
+        <td class="parametervalue">5CSEBA6U23I7</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_device_speed_grade</td>
+        <td class="parametervalue">2</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_mode</td>
+        <td class="parametervalue">Fractional-N PLL</td>
+       </tr>
+       <tr>
+        <td class="parametername">fractional_vco_multiplier</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_reference_clock_frequency</td>
+        <td class="parametervalue">50.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">reference_clock_frequency</td>
+        <td class="parametervalue">50.0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_channel_spacing</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_operation_mode</td>
+        <td class="parametervalue">normal</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_feedback_clock</td>
+        <td class="parametervalue">Global Clock</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_fractional_cout</td>
+        <td class="parametervalue">32</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fractional_cout</td>
+        <td class="parametervalue">32</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dsm_out_sel</td>
+        <td class="parametervalue">1st_order</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_dsm_out_sel</td>
+        <td class="parametervalue">1st_order</td>
+       </tr>
+       <tr>
+        <td class="parametername">operation_mode</td>
+        <td class="parametervalue">normal</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_use_locked</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_adv_params</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_number_of_clocks</td>
+        <td class="parametervalue">8</td>
+       </tr>
+       <tr>
+        <td class="parametername">number_of_clocks</td>
+        <td class="parametervalue">8</td>
+       </tr>
+       <tr>
+        <td class="parametername">number_of_cascade_counters</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_multiply_factor</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_frac_multiply_factor</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_n</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter0</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency0</td>
+        <td class="parametervalue">256.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor0</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor0</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor0</td>
+        <td class="parametervalue">3</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency0</td>
+        <td class="parametervalue">120.000000 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units0</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg0</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle0</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter1</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency1</td>
+        <td class="parametervalue">112.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c1</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor1</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor1</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor1</td>
+        <td class="parametervalue">7</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency1</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units1</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg1</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle1</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency2</td>
+        <td class="parametervalue">64.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c2</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor2</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor2</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor2</td>
+        <td class="parametervalue">12</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency2</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units2</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg2</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle2</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency3</td>
+        <td class="parametervalue">32.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c3</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor3</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor3</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor3</td>
+        <td class="parametervalue">24</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency3</td>
+        <td class="parametervalue">32.533324 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units3</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg3</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle3</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency4</td>
+        <td class="parametervalue">16.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor4</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor4</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor4</td>
+        <td class="parametervalue">48</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency4</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units4</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg4</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle4</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter5</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency5</td>
+        <td class="parametervalue">8.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor5</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor5</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor5</td>
+        <td class="parametervalue">96</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency5</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units5</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg5</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle5</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter6</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency6</td>
+        <td class="parametervalue">4.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor6</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor6</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor6</td>
+        <td class="parametervalue">192</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency6</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units6</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg6</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle6</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter7</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency7</td>
+        <td class="parametervalue">2.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor7</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor7</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor7</td>
+        <td class="parametervalue">384</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency7</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units7</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg7</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle7</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter8</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency8</td>
+        <td class="parametervalue">1.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency8</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units8</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg8</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle8</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter9</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency9</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency9</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units9</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg9</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle9</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter10</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency10</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency10</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units10</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg10</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle10</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter11</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency11</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency11</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units11</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg11</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle11</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter12</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency12</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency12</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units12</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg12</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle12</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter13</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency13</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency13</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units13</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg13</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle13</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter14</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency14</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency14</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units14</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg14</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle14</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter15</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency15</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency15</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units15</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg15</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle15</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter16</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency16</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency16</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units16</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg16</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle16</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter17</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency17</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency17</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units17</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg17</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle17</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency0</td>
+        <td class="parametervalue">255.999872 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift0</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle0</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency1</td>
+        <td class="parametervalue">109.714257 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift1</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle1</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency2</td>
+        <td class="parametervalue">63.999981 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift2</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle2</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency3</td>
+        <td class="parametervalue">31.999989 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift3</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle3</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency4</td>
+        <td class="parametervalue">15.999994 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift4</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle4</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency5</td>
+        <td class="parametervalue">7.999996 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift5</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle5</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency6</td>
+        <td class="parametervalue">3.999998 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift6</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle6</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency7</td>
+        <td class="parametervalue">1.999999 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift7</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle7</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency8</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift8</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle8</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency9</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift9</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle9</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency10</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift10</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle10</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency11</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift11</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle11</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency12</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift12</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle12</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency13</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift13</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle13</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency14</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift14</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle14</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency15</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift15</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle15</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency16</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift16</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle16</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency17</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift17</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle17</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_auto_reset</td>
+        <td class="parametervalue">On</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_bandwidth_preset</td>
+        <td class="parametervalue">Auto</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_reconf</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_dps_ports</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_phout_ports</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phout_division</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_vcoph_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_type</td>
+        <td class="parametervalue">General</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_subtype</td>
+        <td class="parametervalue">General</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_hi_div</td>
+        <td class="parametervalue">8</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_lo_div</td>
+        <td class="parametervalue">7</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_hi_div</td>
+        <td class="parametervalue">256</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_lo_div</td>
+        <td class="parametervalue">256</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_bypass_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_bypass_en</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_odd_div_duty_en</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_odd_div_duty_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div0</td>
+        <td class="parametervalue">2</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src0</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en0</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en0</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div1</td>
+        <td class="parametervalue">4</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div1</td>
+        <td class="parametervalue">3</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst1</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src1</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en1</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en1</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div2</td>
+        <td class="parametervalue">6</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div2</td>
+        <td class="parametervalue">6</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst2</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src2</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div3</td>
+        <td class="parametervalue">12</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div3</td>
+        <td class="parametervalue">12</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst3</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src3</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div4</td>
+        <td class="parametervalue">24</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div4</td>
+        <td class="parametervalue">24</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src4</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div5</td>
+        <td class="parametervalue">48</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div5</td>
+        <td class="parametervalue">48</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src5</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en5</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en5</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div6</td>
+        <td class="parametervalue">96</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div6</td>
+        <td class="parametervalue">96</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src6</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en6</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en6</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div7</td>
+        <td class="parametervalue">192</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div7</td>
+        <td class="parametervalue">192</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src7</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en7</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en7</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src8</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en8</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en8</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src9</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en9</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en9</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src10</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en10</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en10</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src11</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en11</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en11</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src12</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en12</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en12</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src13</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en13</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en13</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src14</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en14</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en14</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src15</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en15</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en15</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src16</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en16</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en16</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src17</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en17</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en17</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_vco_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_cp_current</td>
+        <td class="parametervalue">20</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_bwctrl</td>
+        <td class="parametervalue">4000</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_output_clk_frequency</td>
+        <td class="parametervalue">767.999671 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fractional_division</td>
+        <td class="parametervalue">1546159966</td>
+       </tr>
+       <tr>
+        <td class="parametername">mimic_fbclk_type</td>
+        <td class="parametervalue">gclk</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fbclk_mux_1</td>
+        <td class="parametervalue">glb</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fbclk_mux_2</td>
+        <td class="parametervalue">fb_1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_m_cnt_in_src</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_slf_rst</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_parameter_list</td>
+        <td class="parametervalue">M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,C-Counter-5 Hi Divide,C-Counter-5 Low Divide,C-Counter-5 Coarse Phase Shift,C-Counter-5 VCO Phase Tap,C-Counter-5 Input Source,C-Counter-5 Bypass Enable,C-Counter-5 Odd Divide Enable,C-Counter-6 Hi Divide,C-Counter-6 Low Divide,C-Counter-6 Coarse Phase Shift,C-Counter-6 VCO Phase Tap,C-Counter-6 Input Source,C-Counter-6 Bypass Enable,C-Counter-6 Odd Divide Enable,C-Counter-7 Hi Divide,C-Counter-7 Low Divide,C-Counter-7 Coarse Phase Shift,C-Counter-7 VCO Phase Tap,C-Counter-7 Input Source,C-Counter-7 Bypass Enable,C-Counter-7 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_parameter_values</td>
+        <td class="parametervalue">8,7,256,256,false,true,true,false,2,1,1,0,ph_mux_clk,false,true,4,3,1,0,ph_mux_clk,false,true,6,6,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,24,24,1,0,ph_mux_clk,false,false,48,48,1,0,ph_mux_clk,false,false,96,96,1,0,ph_mux_clk,false,false,192,192,1,0,ph_mux_clk,false,false,1,20,4000,767.999671 MHz,1546159966,gclk,glb,fb_1,ph_mux_clk,true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_mif_generate</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_mif_dps</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_cntr</td>
+        <td class="parametervalue">C0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_num</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_dir</td>
+        <td class="parametervalue">Positive</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_refclk_switch</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_refclk1_frequency</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_switchover_mode</td>
+        <td class="parametervalue">Automatic Switchover</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_switchover_delay</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_active_clk</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_clk_bad</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">refclk1_frequency</td>
+        <td class="parametervalue">100.0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clk_loss_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_manu_clk_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_auto_clk_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clkin_1_src</td>
+        <td class="parametervalue">clk_0</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clk_sw_dly</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_cascade_out</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_outclk_index</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_cascade_in</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clkin_0_src</td>
+        <td class="parametervalue">clk_0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_cascading_mode</td>
+        <td class="parametervalue">Create an adjpllin signal to connect with an upstream PLL</td>
+       </tr>
+       <tr>
+        <td class="parametername">deviceFamily</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">generateLegacySim</td>
+        <td class="parametervalue">false</td>
+       </tr>
+      </table>
+     </td>
+    </tr>
+   </table>&#160;&#160;
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Software Assignments</h2>(none)</td>
+    </tr>
+   </table>
+  </div>
+  <a name="module_pll_1"> </a>
+  <div>
+   <hr/>
+   <h2>pll_1</h2>altera_pll v17.1
+   <br/>
+   <div class="greydiv">
+    <table class="connectionboxes">
+     <tr>
+      <td class="neighbor" rowspan="2">
+       <a href="#module_pll_0">pll_0</a>
+      </td>
+      <td class="from">outclk0&#160;&#160;</td>
+      <td class="main" rowspan="2">pll_1</td>
+     </tr>
+     <tr>
+      <td class="to">&#160;&#160;refclk</td>
+     </tr>
+    </table>
+   </div>
+   <br/>
+   <br/>
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Parameters</h2>
+      <table>
+       <tr>
+        <td class="parametername">debug_print_output</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">debug_use_rbc_taf_method</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">device_family</td>
+        <td class="parametervalue">CYCLONEV</td>
+       </tr>
+       <tr>
+        <td class="parametername">device</td>
+        <td class="parametervalue">5CSEBA6U23I7</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_device_speed_grade</td>
+        <td class="parametervalue">2</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_mode</td>
+        <td class="parametervalue">Integer-N PLL</td>
+       </tr>
+       <tr>
+        <td class="parametername">fractional_vco_multiplier</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_reference_clock_frequency</td>
+        <td class="parametervalue">256.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">reference_clock_frequency</td>
+        <td class="parametervalue">256.0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_channel_spacing</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_operation_mode</td>
+        <td class="parametervalue">normal</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_feedback_clock</td>
+        <td class="parametervalue">Global Clock</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_fractional_cout</td>
+        <td class="parametervalue">32</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fractional_cout</td>
+        <td class="parametervalue">32</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dsm_out_sel</td>
+        <td class="parametervalue">1st_order</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_dsm_out_sel</td>
+        <td class="parametervalue">1st_order</td>
+       </tr>
+       <tr>
+        <td class="parametername">operation_mode</td>
+        <td class="parametervalue">normal</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_use_locked</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_adv_params</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_number_of_clocks</td>
+        <td class="parametervalue">5</td>
+       </tr>
+       <tr>
+        <td class="parametername">number_of_clocks</td>
+        <td class="parametervalue">5</td>
+       </tr>
+       <tr>
+        <td class="parametername">number_of_cascade_counters</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_multiply_factor</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_frac_multiply_factor</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_n</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter0</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency0</td>
+        <td class="parametervalue">56.75</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor0</td>
+        <td class="parametervalue">90</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor0</td>
+        <td class="parametervalue">406</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency0</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units0</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg0</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle0</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter1</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency1</td>
+        <td class="parametervalue">28.375</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c1</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor1</td>
+        <td class="parametervalue">90</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor1</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor1</td>
+        <td class="parametervalue">812</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency1</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units1</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg1</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle1</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency2</td>
+        <td class="parametervalue">14.1875</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c2</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor2</td>
+        <td class="parametervalue">90</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor2</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor2</td>
+        <td class="parametervalue">1624</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency2</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units2</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg2</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle2</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency3</td>
+        <td class="parametervalue">7.09375</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c3</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor3</td>
+        <td class="parametervalue">90</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor3</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor3</td>
+        <td class="parametervalue">3248</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency3</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units3</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg3</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle3</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency4</td>
+        <td class="parametervalue">3.546875</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor4</td>
+        <td class="parametervalue">90</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor4</td>
+        <td class="parametervalue">6496</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency4</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units4</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg4</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle4</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter5</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency5</td>
+        <td class="parametervalue">7.09375</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency5</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units5</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg5</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle5</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter6</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency6</td>
+        <td class="parametervalue">3.546875</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency6</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units6</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg6</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle6</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter7</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency7</td>
+        <td class="parametervalue">3.546875</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency7</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units7</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg7</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle7</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter8</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency8</td>
+        <td class="parametervalue">3.546875</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency8</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units8</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg8</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle8</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter9</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency9</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency9</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units9</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg9</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle9</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter10</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency10</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency10</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units10</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg10</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle10</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter11</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency11</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency11</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units11</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg11</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle11</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter12</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency12</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency12</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units12</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg12</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle12</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter13</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency13</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency13</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units13</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg13</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle13</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter14</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency14</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency14</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units14</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg14</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle14</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter15</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency15</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency15</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units15</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg15</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle15</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter16</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency16</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency16</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units16</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg16</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle16</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter17</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency17</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency17</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units17</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg17</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle17</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency0</td>
+        <td class="parametervalue">56.748768 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift0</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle0</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency1</td>
+        <td class="parametervalue">28.374384 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift1</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle1</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency2</td>
+        <td class="parametervalue">14.187192 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift2</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle2</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency3</td>
+        <td class="parametervalue">7.093596 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift3</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle3</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency4</td>
+        <td class="parametervalue">3.546798 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift4</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle4</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency5</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift5</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle5</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency6</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift6</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle6</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency7</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift7</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle7</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency8</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift8</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle8</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency9</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift9</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle9</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency10</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift10</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle10</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency11</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift11</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle11</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency12</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift12</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle12</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency13</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift13</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle13</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency14</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift14</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle14</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency15</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift15</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle15</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency16</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift16</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle16</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency17</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift17</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle17</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_auto_reset</td>
+        <td class="parametervalue">On</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_bandwidth_preset</td>
+        <td class="parametervalue">Auto</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_reconf</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_dps_ports</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_phout_ports</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phout_division</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_vcoph_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_type</td>
+        <td class="parametervalue">General</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_subtype</td>
+        <td class="parametervalue">General</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_hi_div</td>
+        <td class="parametervalue">45</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_lo_div</td>
+        <td class="parametervalue">45</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_hi_div</td>
+        <td class="parametervalue">15</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_lo_div</td>
+        <td class="parametervalue">14</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_bypass_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_bypass_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_odd_div_duty_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_odd_div_duty_en</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div0</td>
+        <td class="parametervalue">7</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div0</td>
+        <td class="parametervalue">7</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src0</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en0</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en0</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div1</td>
+        <td class="parametervalue">14</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div1</td>
+        <td class="parametervalue">14</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst1</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src1</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en1</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en1</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div2</td>
+        <td class="parametervalue">28</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div2</td>
+        <td class="parametervalue">28</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst2</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src2</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div3</td>
+        <td class="parametervalue">56</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div3</td>
+        <td class="parametervalue">56</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst3</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src3</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div4</td>
+        <td class="parametervalue">112</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div4</td>
+        <td class="parametervalue">112</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src4</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src5</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en5</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en5</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src6</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en6</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en6</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src7</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en7</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en7</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src8</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en8</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en8</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src9</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en9</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en9</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src10</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en10</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en10</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src11</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en11</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en11</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src12</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en12</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en12</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src13</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en13</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en13</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src14</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en14</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en14</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src15</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en15</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en15</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src16</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en16</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en16</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src17</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en17</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en17</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_vco_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_cp_current</td>
+        <td class="parametervalue">20</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_bwctrl</td>
+        <td class="parametervalue">10000</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_output_clk_frequency</td>
+        <td class="parametervalue">794.482758 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fractional_division</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">mimic_fbclk_type</td>
+        <td class="parametervalue">gclk</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fbclk_mux_1</td>
+        <td class="parametervalue">glb</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fbclk_mux_2</td>
+        <td class="parametervalue">fb_1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_m_cnt_in_src</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_slf_rst</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_parameter_list</td>
+        <td class="parametervalue">M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_parameter_values</td>
+        <td class="parametervalue">45,45,15,14,false,false,false,true,7,7,1,0,ph_mux_clk,false,false,14,14,1,0,ph_mux_clk,false,false,28,28,1,0,ph_mux_clk,false,false,56,56,1,0,ph_mux_clk,false,false,112,112,1,0,ph_mux_clk,false,false,1,20,10000,794.482758 MHz,1,gclk,glb,fb_1,ph_mux_clk,true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_mif_generate</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_mif_dps</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_cntr</td>
+        <td class="parametervalue">C0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_num</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_dir</td>
+        <td class="parametervalue">Positive</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_refclk_switch</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_refclk1_frequency</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_switchover_mode</td>
+        <td class="parametervalue">Automatic Switchover</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_switchover_delay</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_active_clk</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_clk_bad</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">refclk1_frequency</td>
+        <td class="parametervalue">100.0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clk_loss_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_manu_clk_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_auto_clk_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clkin_1_src</td>
+        <td class="parametervalue">clk_0</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clk_sw_dly</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_cascade_out</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_outclk_index</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_cascade_in</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clkin_0_src</td>
+        <td class="parametervalue">clk_0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_cascading_mode</td>
+        <td class="parametervalue">Create an adjpllin signal to connect with an upstream PLL</td>
+       </tr>
+       <tr>
+        <td class="parametername">deviceFamily</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">generateLegacySim</td>
+        <td class="parametervalue">false</td>
+       </tr>
+      </table>
+     </td>
+    </tr>
+   </table>&#160;&#160;
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Software Assignments</h2>(none)</td>
+    </tr>
+   </table>
+  </div>
+  <a name="module_pll_2"> </a>
+  <div>
+   <hr/>
+   <h2>pll_2</h2>altera_pll v17.1
+   <br/>
+   <div class="greydiv">
+    <table class="connectionboxes">
+     <tr>
+      <td class="neighbor" rowspan="2">
+       <a href="#module_pll_0">pll_0</a>
+      </td>
+      <td class="from">outclk0&#160;&#160;</td>
+      <td class="main" rowspan="2">pll_2</td>
+     </tr>
+     <tr>
+      <td class="to">&#160;&#160;refclk</td>
+     </tr>
+    </table>
+   </div>
+   <br/>
+   <br/>
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Parameters</h2>
+      <table>
+       <tr>
+        <td class="parametername">debug_print_output</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">debug_use_rbc_taf_method</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">device_family</td>
+        <td class="parametervalue">CYCLONEV</td>
+       </tr>
+       <tr>
+        <td class="parametername">device</td>
+        <td class="parametervalue">5CSEBA6U23I7</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_device_speed_grade</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_mode</td>
+        <td class="parametervalue">Fractional-N PLL</td>
+       </tr>
+       <tr>
+        <td class="parametername">fractional_vco_multiplier</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_reference_clock_frequency</td>
+        <td class="parametervalue">256.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">reference_clock_frequency</td>
+        <td class="parametervalue">256.0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_channel_spacing</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_operation_mode</td>
+        <td class="parametervalue">normal</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_feedback_clock</td>
+        <td class="parametervalue">Global Clock</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_fractional_cout</td>
+        <td class="parametervalue">32</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fractional_cout</td>
+        <td class="parametervalue">32</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dsm_out_sel</td>
+        <td class="parametervalue">1st_order</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_dsm_out_sel</td>
+        <td class="parametervalue">1st_order</td>
+       </tr>
+       <tr>
+        <td class="parametername">operation_mode</td>
+        <td class="parametervalue">normal</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_use_locked</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_adv_params</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_number_of_clocks</td>
+        <td class="parametervalue">4</td>
+       </tr>
+       <tr>
+        <td class="parametername">number_of_clocks</td>
+        <td class="parametervalue">4</td>
+       </tr>
+       <tr>
+        <td class="parametername">number_of_cascade_counters</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_multiply_factor</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_frac_multiply_factor</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_n</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter0</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency0</td>
+        <td class="parametervalue">31.1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor0</td>
+        <td class="parametervalue">12</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor0</td>
+        <td class="parametervalue">1681070366</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor0</td>
+        <td class="parametervalue">102</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency0</td>
+        <td class="parametervalue">36.000000 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units0</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg0</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle0</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter1</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency1</td>
+        <td class="parametervalue">25.175</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c1</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor1</td>
+        <td class="parametervalue">12</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor1</td>
+        <td class="parametervalue">1681070366</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor1</td>
+        <td class="parametervalue">126</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency1</td>
+        <td class="parametervalue">31.500000 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units1</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg1</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle1</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency2</td>
+        <td class="parametervalue">17.734475</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c2</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor2</td>
+        <td class="parametervalue">12</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor2</td>
+        <td class="parametervalue">1681070366</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor2</td>
+        <td class="parametervalue">178</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency2</td>
+        <td class="parametervalue">25.568627 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units2</td>
+        <td class="parametervalue">degrees</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg2</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle2</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency3</td>
+        <td class="parametervalue">8.867237</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c3</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor3</td>
+        <td class="parametervalue">12</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor3</td>
+        <td class="parametervalue">1681070366</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor3</td>
+        <td class="parametervalue">358</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency3</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units3</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg3</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle3</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency4</td>
+        <td class="parametervalue">8.867237</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency4</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units4</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg4</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle4</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter5</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency5</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency5</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units5</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg5</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle5</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter6</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency6</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency6</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units6</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg6</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle6</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter7</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency7</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency7</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units7</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg7</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle7</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter8</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency8</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency8</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units8</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg8</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle8</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter9</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency9</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency9</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units9</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg9</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle9</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter10</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency10</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency10</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units10</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg10</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle10</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter11</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency11</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency11</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units11</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg11</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle11</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter12</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency12</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency12</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units12</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg12</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle12</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter13</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency13</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency13</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units13</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg13</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle13</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter14</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency14</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency14</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units14</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg14</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle14</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter15</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency15</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency15</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units15</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg15</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle15</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter16</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency16</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency16</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units16</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg16</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle16</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_counter17</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_output_clock_frequency17</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_divide_factor_c17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_multiply_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_frac_multiply_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_divide_factor17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_output_clock_frequency17</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_ps_units17</td>
+        <td class="parametervalue">ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phase_shift_deg17</td>
+        <td class="parametervalue">0.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_actual_phase_shift17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_duty_cycle17</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency0</td>
+        <td class="parametervalue">31.099998 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift0</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle0</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency1</td>
+        <td class="parametervalue">25.176188 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift1</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle1</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency2</td>
+        <td class="parametervalue">17.821346 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift2</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle2</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency3</td>
+        <td class="parametervalue">8.860892 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift3</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle3</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency4</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift4</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle4</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency5</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift5</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle5</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency6</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift6</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle6</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency7</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift7</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle7</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency8</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift8</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle8</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency9</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift9</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle9</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency10</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift10</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle10</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency11</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift11</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle11</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency12</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift12</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle12</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency13</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift13</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle13</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency14</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift14</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle14</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency15</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift15</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle15</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency16</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift16</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle16</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">output_clock_frequency17</td>
+        <td class="parametervalue">0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">phase_shift17</td>
+        <td class="parametervalue">0 ps</td>
+       </tr>
+       <tr>
+        <td class="parametername">duty_cycle17</td>
+        <td class="parametervalue">50</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_auto_reset</td>
+        <td class="parametervalue">On</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_bandwidth_preset</td>
+        <td class="parametervalue">Auto</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_reconf</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_dps_ports</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_en_phout_ports</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_phout_division</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_vcoph_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_type</td>
+        <td class="parametervalue">General</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_subtype</td>
+        <td class="parametervalue">General</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_hi_div</td>
+        <td class="parametervalue">6</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_lo_div</td>
+        <td class="parametervalue">6</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_hi_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_lo_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_bypass_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_bypass_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">m_cnt_odd_div_duty_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">n_cnt_odd_div_duty_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div0</td>
+        <td class="parametervalue">26</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div0</td>
+        <td class="parametervalue">25</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst0</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst0</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src0</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en0</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en0</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div1</td>
+        <td class="parametervalue">32</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div1</td>
+        <td class="parametervalue">31</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst1</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst1</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src1</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en1</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en1</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div2</td>
+        <td class="parametervalue">45</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div2</td>
+        <td class="parametervalue">44</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst2</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst2</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src2</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en2</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en2</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div3</td>
+        <td class="parametervalue">90</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div3</td>
+        <td class="parametervalue">89</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst3</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst3</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src3</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en3</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en3</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst4</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst4</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src4</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en4</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en4</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst5</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst5</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src5</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en5</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en5</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst6</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst6</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src6</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en6</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en6</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst7</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst7</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src7</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en7</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en7</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst8</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst8</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src8</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en8</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en8</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst9</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst9</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src9</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en9</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en9</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst10</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst10</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src10</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en10</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en10</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst11</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst11</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src11</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en11</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en11</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst12</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst12</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src12</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en12</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en12</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst13</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst13</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src13</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en13</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en13</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst14</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst14</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src14</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en14</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en14</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst15</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst15</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src15</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en15</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en15</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst16</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst16</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src16</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en16</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en16</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_hi_div17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_lo_div17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_prst17</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_ph_mux_prst17</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_in_src17</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_bypass_en17</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">c_cnt_odd_div_duty_en17</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_vco_div</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_cp_current</td>
+        <td class="parametervalue">30</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_bwctrl</td>
+        <td class="parametervalue">2000</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_output_clk_frequency</td>
+        <td class="parametervalue">1586.099801 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fractional_division</td>
+        <td class="parametervalue">1681070366</td>
+       </tr>
+       <tr>
+        <td class="parametername">mimic_fbclk_type</td>
+        <td class="parametervalue">gclk</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fbclk_mux_1</td>
+        <td class="parametervalue">glb</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_fbclk_mux_2</td>
+        <td class="parametervalue">fb_1</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_m_cnt_in_src</td>
+        <td class="parametervalue">ph_mux_clk</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_slf_rst</td>
+        <td class="parametervalue">true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_parameter_list</td>
+        <td class="parametervalue">M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_parameter_values</td>
+        <td class="parametervalue">6,6,1,1,false,false,false,false,26,25,1,0,ph_mux_clk,false,true,32,31,1,0,ph_mux_clk,false,true,45,44,1,0,ph_mux_clk,false,true,90,89,1,0,ph_mux_clk,false,true,1,30,2000,1586.099801 MHz,1681070366,gclk,glb,fb_1,ph_mux_clk,true</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_mif_generate</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_mif_dps</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_cntr</td>
+        <td class="parametervalue">C0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_num</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_dps_dir</td>
+        <td class="parametervalue">Positive</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_refclk_switch</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_refclk1_frequency</td>
+        <td class="parametervalue">100.0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_switchover_mode</td>
+        <td class="parametervalue">Automatic Switchover</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_switchover_delay</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_active_clk</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_clk_bad</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">refclk1_frequency</td>
+        <td class="parametervalue">100.0 MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clk_loss_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_manu_clk_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_auto_clk_sw_en</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clkin_1_src</td>
+        <td class="parametervalue">clk_0</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clk_sw_dly</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_cascade_out</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_cascade_outclk_index</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_enable_cascade_in</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">pll_clkin_0_src</td>
+        <td class="parametervalue">clk_0</td>
+       </tr>
+       <tr>
+        <td class="parametername">gui_pll_cascading_mode</td>
+        <td class="parametervalue">Create an adjpllin signal to connect with an upstream PLL</td>
+       </tr>
+       <tr>
+        <td class="parametername">deviceFamily</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">generateLegacySim</td>
+        <td class="parametervalue">false</td>
+       </tr>
+      </table>
+     </td>
+    </tr>
+   </table>&#160;&#160;
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Software Assignments</h2>(none)</td>
+    </tr>
+   </table>
+  </div>
+  <table class="blueBar">
+   <tr>
+    <td class="l">generation took 0.00 seconds</td>
+    <td class="r">rendering took 0.06 seconds</td>
+   </tr>
+  </table>
+ </body>
+</html>
diff --git a/common/pll/pll.xml b/common/pll/pll.xml
new file mode 100644
index 0000000..bb952b9
--- /dev/null
+++ b/common/pll/pll.xml
@@ -0,0 +1,2212 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2018.12.10.19:38:13"
+ outputDirectory="/srv/dvlp/Projects/dev/github/em/common/pll/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="Cyclone V"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="5CSEBA6U23I7"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="7"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_PLL_0_REFCLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_PLL_0_REFCLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_PLL_0_REFCLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="clk" kind="clock" start="0">
+   <property name="clockRate" value="50000000" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_outclk1" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="109714257" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_0_outclk1_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_outclk2" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="63999981" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_0_outclk2_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_outclk3" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="31999989" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_0_outclk3_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_outclk4" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="15999994" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_0_outclk4_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_outclk5" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="7999996" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_0_outclk5_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_outclk6" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="3999998" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_0_outclk6_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_refclk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_0_refclk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="pll_0_reset" kind="reset" start="0">
+   <property name="associatedClock" value="" />
+   <property name="synchronousEdges" value="NONE" />
+   <port name="pll_0_reset_reset" direction="input" role="reset" width="1" />
+  </interface>
+  <interface name="pll_1_outclk0" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="56748768" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_1_outclk0_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_1_outclk1" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="28374384" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_1_outclk1_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_1_outclk2" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="14187192" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_1_outclk2_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_1_outclk3" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="7093596" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_1_outclk3_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_1_outclk4" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="3546798" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_1_outclk4_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_1_reset" kind="reset" start="0">
+   <property name="associatedClock" value="" />
+   <property name="synchronousEdges" value="NONE" />
+   <port name="pll_1_reset_reset" direction="input" role="reset" width="1" />
+  </interface>
+  <interface name="pll_2_outclk0" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="31099998" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_2_outclk0_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_2_outclk1" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="25176188" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_2_outclk1_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_2_outclk2" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="17821346" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_2_outclk2_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_2_outclk3" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="8860892" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="pll_2_outclk3_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="pll_2_reset" kind="reset" start="0">
+   <property name="associatedClock" value="" />
+   <property name="synchronousEdges" value="NONE" />
+   <port name="pll_2_reset_reset" direction="input" role="reset" width="1" />
+  </interface>
+  <interface name="reset" kind="reset" start="0">
+   <property name="associatedClock" value="" />
+   <property name="synchronousEdges" value="NONE" />
+   <port name="reset_reset_n" direction="input" role="reset_n" width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="pll:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=5CSEBA6U23I7,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_DEVICE_SPEEDGRADE=7,AUTO_GENERATION_ID=1544470692,AUTO_PLL_0_REFCLK_CLOCK_DOMAIN=-1,AUTO_PLL_0_REFCLK_CLOCK_RATE=-1,AUTO_PLL_0_REFCLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(clock_source:17.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_pll:17.1:c_cnt_bypass_en0=false,c_cnt_bypass_en1=false,c_cnt_bypass_en10=true,c_cnt_bypass_en11=true,c_cnt_bypass_en12=true,c_cnt_bypass_en13=true,c_cnt_bypass_en14=true,c_cnt_bypass_en15=true,c_cnt_bypass_en16=true,c_cnt_bypass_en17=true,c_cnt_bypass_en2=false,c_cnt_bypass_en3=false,c_cnt_bypass_en4=false,c_cnt_bypass_en5=false,c_cnt_bypass_en6=false,c_cnt_bypass_en7=false,c_cnt_bypass_en8=true,c_cnt_bypass_en9=true,c_cnt_hi_div0=2,c_cnt_hi_div1=4,c_cnt_hi_div10=1,c_cnt_hi_div11=1,c_cnt_hi_div12=1,c_cnt_hi_div13=1,c_cnt_hi_div14=1,c_cnt_hi_div15=1,c_cnt_hi_div16=1,c_cnt_hi_div17=1,c_cnt_hi_div2=6,c_cnt_hi_div3=12,c_cnt_hi_div4=24,c_cnt_hi_div5=48,c_cnt_hi_div6=96,c_cnt_hi_div7=192,c_cnt_hi_div8=1,c_cnt_hi_div9=1,c_cnt_in_src0=ph_mux_clk,c_cnt_in_src1=ph_mux_clk,c_cnt_in_src10=ph_mux_clk,c_cnt_in_src11=ph_mux_clk,c_cnt_in_src12=ph_mux_clk,c_cnt_in_src13=ph_mux_clk,c_cnt_in_src14=ph_mux_clk,c_cnt_in_src15=ph_mux_clk,c_cnt_in_src16=ph_mux_clk,c_cnt_in_src17=ph_mux_clk,c_cnt_in_src2=ph_mux_clk,c_cnt_in_src3=ph_mux_clk,c_cnt_in_src4=ph_mux_clk,c_cnt_in_src5=ph_mux_clk,c_cnt_in_src6=ph_mux_clk,c_cnt_in_src7=ph_mux_clk,c_cnt_in_src8=ph_mux_clk,c_cnt_in_src9=ph_mux_clk,c_cnt_lo_div0=1,c_cnt_lo_div1=3,c_cnt_lo_div10=1,c_cnt_lo_div11=1,c_cnt_lo_div12=1,c_cnt_lo_div13=1,c_cnt_lo_div14=1,c_cnt_lo_div15=1,c_cnt_lo_div16=1,c_cnt_lo_div17=1,c_cnt_lo_div2=6,c_cnt_lo_div3=12,c_cnt_lo_div4=24,c_cnt_lo_div5=48,c_cnt_lo_div6=96,c_cnt_lo_div7=192,c_cnt_lo_div8=1,c_cnt_lo_div9=1,c_cnt_odd_div_duty_en0=true,c_cnt_odd_div_duty_en1=true,c_cnt_odd_div_duty_en10=false,c_cnt_odd_div_duty_en11=false,c_cnt_odd_div_duty_en12=false,c_cnt_odd_div_duty_en13=false,c_cnt_odd_div_duty_en14=false,c_cnt_odd_div_duty_en15=false,c_cnt_odd_div_duty_en16=false,c_cnt_odd_div_duty_en17=false,c_cnt_odd_div_duty_en2=false,c_cnt_odd_div_duty_en3=false,c_cnt_odd_div_duty_en4=false,c_cnt_odd_div_duty_en5=false,c_cnt_odd_div_duty_en6=false,c_cnt_odd_div_duty_en7=false,c_cnt_odd_div_duty_en8=false,c_cnt_odd_div_duty_en9=false,c_cnt_ph_mux_prst0=0,c_cnt_ph_mux_prst1=0,c_cnt_ph_mux_prst10=0,c_cnt_ph_mux_prst11=0,c_cnt_ph_mux_prst12=0,c_cnt_ph_mux_prst13=0,c_cnt_ph_mux_prst14=0,c_cnt_ph_mux_prst15=0,c_cnt_ph_mux_prst16=0,c_cnt_ph_mux_prst17=0,c_cnt_ph_mux_prst2=0,c_cnt_ph_mux_prst3=0,c_cnt_ph_mux_prst4=0,c_cnt_ph_mux_prst5=0,c_cnt_ph_mux_prst6=0,c_cnt_ph_mux_prst7=0,c_cnt_ph_mux_prst8=0,c_cnt_ph_mux_prst9=0,c_cnt_prst0=1,c_cnt_prst1=1,c_cnt_prst10=1,c_cnt_prst11=1,c_cnt_prst12=1,c_cnt_prst13=1,c_cnt_prst14=1,c_cnt_prst15=1,c_cnt_prst16=1,c_cnt_prst17=1,c_cnt_prst2=1,c_cnt_prst3=1,c_cnt_prst4=1,c_cnt_prst5=1,c_cnt_prst6=1,c_cnt_prst7=1,c_cnt_prst8=1,c_cnt_prst9=1,debug_print_output=false,debug_use_rbc_taf_method=false,device=5CSEBA6U23I7,device_family=Cyclone V,duty_cycle0=50,duty_cycle1=50,duty_cycle10=50,duty_cycle11=50,duty_cycle12=50,duty_cycle13=50,duty_cycle14=50,duty_cycle15=50,duty_cycle16=50,duty_cycle17=50,duty_cycle2=50,duty_cycle3=50,duty_cycle4=50,duty_cycle5=50,duty_cycle6=50,duty_cycle7=50,duty_cycle8=50,duty_cycle9=50,fractional_vco_multiplier=true,gui_active_clk=false,gui_actual_divide_factor0=3,gui_actual_divide_factor1=7,gui_actual_divide_factor10=1,gui_actual_divide_factor11=1,gui_actual_divide_factor12=1,gui_actual_divide_factor13=1,gui_actual_divide_factor14=1,gui_actual_divide_factor15=1,gui_actual_divide_factor16=1,gui_actual_divide_factor17=1,gui_actual_divide_factor2=12,gui_actual_divide_factor3=24,gui_actual_divide_factor4=48,gui_actual_divide_factor5=96,gui_actual_divide_factor6=192,gui_actual_divide_factor7=384,gui_actual_divide_factor8=1,gui_actual_divide_factor9=1,gui_actual_frac_multiply_factor0=1546159966,gui_actual_frac_multiply_factor1=1546159966,gui_actual_frac_multiply_factor10=1,gui_actual_frac_multiply_factor11=1,gui_actual_frac_multiply_factor12=1,gui_actual_frac_multiply_factor13=1,gui_actual_frac_multiply_factor14=1,gui_actual_frac_multiply_factor15=1,gui_actual_frac_multiply_factor16=1,gui_actual_frac_multiply_factor17=1,gui_actual_frac_multiply_factor2=1546159966,gui_actual_frac_multiply_factor3=1546159966,gui_actual_frac_multiply_factor4=1546159966,gui_actual_frac_multiply_factor5=1546159966,gui_actual_frac_multiply_factor6=1546159966,gui_actual_frac_multiply_factor7=1546159966,gui_actual_frac_multiply_factor8=1,gui_actual_frac_multiply_factor9=1,gui_actual_multiply_factor0=15,gui_actual_multiply_factor1=15,gui_actual_multiply_factor10=1,gui_actual_multiply_factor11=1,gui_actual_multiply_factor12=1,gui_actual_multiply_factor13=1,gui_actual_multiply_factor14=1,gui_actual_multiply_factor15=1,gui_actual_multiply_factor16=1,gui_actual_multiply_factor17=1,gui_actual_multiply_factor2=15,gui_actual_multiply_factor3=15,gui_actual_multiply_factor4=15,gui_actual_multiply_factor5=15,gui_actual_multiply_factor6=15,gui_actual_multiply_factor7=15,gui_actual_multiply_factor8=1,gui_actual_multiply_factor9=1,gui_actual_output_clock_frequency0=120.000000 MHz,gui_actual_output_clock_frequency1=0 MHz,gui_actual_output_clock_frequency10=0 MHz,gui_actual_output_clock_frequency11=0 MHz,gui_actual_output_clock_frequency12=0 MHz,gui_actual_output_clock_frequency13=0 MHz,gui_actual_output_clock_frequency14=0 MHz,gui_actual_output_clock_frequency15=0 MHz,gui_actual_output_clock_frequency16=0 MHz,gui_actual_output_clock_frequency17=0 MHz,gui_actual_output_clock_frequency2=0 MHz,gui_actual_output_clock_frequency3=32.533324 MHz,gui_actual_output_clock_frequency4=0 MHz,gui_actual_output_clock_frequency5=0 MHz,gui_actual_output_clock_frequency6=0 MHz,gui_actual_output_clock_frequency7=0 MHz,gui_actual_output_clock_frequency8=0 MHz,gui_actual_output_clock_frequency9=0 MHz,gui_actual_phase_shift0=0,gui_actual_phase_shift1=0,gui_actual_phase_shift10=0,gui_actual_phase_shift11=0,gui_actual_phase_shift12=0,gui_actual_phase_shift13=0,gui_actual_phase_shift14=0,gui_actual_phase_shift15=0,gui_actual_phase_shift16=0,gui_actual_phase_shift17=0,gui_actual_phase_shift2=0,gui_actual_phase_shift3=0,gui_actual_phase_shift4=0,gui_actual_phase_shift5=0,gui_actual_phase_shift6=0,gui_actual_phase_shift7=0,gui_actual_phase_shift8=0,gui_actual_phase_shift9=0,gui_cascade_counter0=false,gui_cascade_counter1=false,gui_cascade_counter10=false,gui_cascade_counter11=false,gui_cascade_counter12=false,gui_cascade_counter13=false,gui_cascade_counter14=false,gui_cascade_counter15=false,gui_cascade_counter16=false,gui_cascade_counter17=false,gui_cascade_counter2=false,gui_cascade_counter3=false,gui_cascade_counter4=false,gui_cascade_counter5=false,gui_cascade_counter6=false,gui_cascade_counter7=false,gui_cascade_counter8=false,gui_cascade_counter9=false,gui_cascade_outclk_index=0,gui_channel_spacing=0.0,gui_clk_bad=false,gui_device_speed_grade=2,gui_divide_factor_c0=1,gui_divide_factor_c1=1,gui_divide_factor_c10=1,gui_divide_factor_c11=1,gui_divide_factor_c12=1,gui_divide_factor_c13=1,gui_divide_factor_c14=1,gui_divide_factor_c15=1,gui_divide_factor_c16=1,gui_divide_factor_c17=1,gui_divide_factor_c2=1,gui_divide_factor_c3=1,gui_divide_factor_c4=1,gui_divide_factor_c5=1,gui_divide_factor_c6=1,gui_divide_factor_c7=1,gui_divide_factor_c8=1,gui_divide_factor_c9=1,gui_divide_factor_n=1,gui_dps_cntr=C0,gui_dps_dir=Positive,gui_dps_num=1,gui_dsm_out_sel=1st_order,gui_duty_cycle0=50,gui_duty_cycle1=50,gui_duty_cycle10=50,gui_duty_cycle11=50,gui_duty_cycle12=50,gui_duty_cycle13=50,gui_duty_cycle14=50,gui_duty_cycle15=50,gui_duty_cycle16=50,gui_duty_cycle17=50,gui_duty_cycle2=50,gui_duty_cycle3=50,gui_duty_cycle4=50,gui_duty_cycle5=50,gui_duty_cycle6=50,gui_duty_cycle7=50,gui_duty_cycle8=50,gui_duty_cycle9=50,gui_en_adv_params=false,gui_en_dps_ports=false,gui_en_phout_ports=false,gui_en_reconf=false,gui_enable_cascade_in=false,gui_enable_cascade_out=false,gui_enable_mif_dps=false,gui_feedback_clock=Global Clock,gui_frac_multiply_factor=1,gui_fractional_cout=32,gui_mif_generate=false,gui_multiply_factor=1,gui_number_of_clocks=8,gui_operation_mode=normal,gui_output_clock_frequency0=256.0,gui_output_clock_frequency1=112.0,gui_output_clock_frequency10=100.0,gui_output_clock_frequency11=100.0,gui_output_clock_frequency12=100.0,gui_output_clock_frequency13=100.0,gui_output_clock_frequency14=100.0,gui_output_clock_frequency15=100.0,gui_output_clock_frequency16=100.0,gui_output_clock_frequency17=100.0,gui_output_clock_frequency2=64.0,gui_output_clock_frequency3=32.0,gui_output_clock_frequency4=16.0,gui_output_clock_frequency5=8.0,gui_output_clock_frequency6=4.0,gui_output_clock_frequency7=2.0,gui_output_clock_frequency8=1.0,gui_output_clock_frequency9=100.0,gui_parameter_list=M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,C-Counter-5 Hi Divide,C-Counter-5 Low Divide,C-Counter-5 Coarse Phase Shift,C-Counter-5 VCO Phase Tap,C-Counter-5 Input Source,C-Counter-5 Bypass Enable,C-Counter-5 Odd Divide Enable,C-Counter-6 Hi Divide,C-Counter-6 Low Divide,C-Counter-6 Coarse Phase Shift,C-Counter-6 VCO Phase Tap,C-Counter-6 Input Source,C-Counter-6 Bypass Enable,C-Counter-6 Odd Divide Enable,C-Counter-7 Hi Divide,C-Counter-7 Low Divide,C-Counter-7 Coarse Phase Shift,C-Counter-7 VCO Phase Tap,C-Counter-7 Input Source,C-Counter-7 Bypass Enable,C-Counter-7 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset,gui_parameter_values=8,7,256,256,false,true,true,false,2,1,1,0,ph_mux_clk,false,true,4,3,1,0,ph_mux_clk,false,true,6,6,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,24,24,1,0,ph_mux_clk,false,false,48,48,1,0,ph_mux_clk,false,false,96,96,1,0,ph_mux_clk,false,false,192,192,1,0,ph_mux_clk,false,false,1,20,4000,767.999671 MHz,1546159966,gclk,glb,fb_1,ph_mux_clk,true,gui_phase_shift0=0,gui_phase_shift1=0,gui_phase_shift10=0,gui_phase_shift11=0,gui_phase_shift12=0,gui_phase_shift13=0,gui_phase_shift14=0,gui_phase_shift15=0,gui_phase_shift16=0,gui_phase_shift17=0,gui_phase_shift2=0,gui_phase_shift3=0,gui_phase_shift4=0,gui_phase_shift5=0,gui_phase_shift6=0,gui_phase_shift7=0,gui_phase_shift8=0,gui_phase_shift9=0,gui_phase_shift_deg0=0.0,gui_phase_shift_deg1=0.0,gui_phase_shift_deg10=0.0,gui_phase_shift_deg11=0.0,gui_phase_shift_deg12=0.0,gui_phase_shift_deg13=0.0,gui_phase_shift_deg14=0.0,gui_phase_shift_deg15=0.0,gui_phase_shift_deg16=0.0,gui_phase_shift_deg17=0.0,gui_phase_shift_deg2=0.0,gui_phase_shift_deg3=0.0,gui_phase_shift_deg4=0.0,gui_phase_shift_deg5=0.0,gui_phase_shift_deg6=0.0,gui_phase_shift_deg7=0.0,gui_phase_shift_deg8=0.0,gui_phase_shift_deg9=0.0,gui_phout_division=1,gui_pll_auto_reset=On,gui_pll_bandwidth_preset=Auto,gui_pll_cascading_mode=Create an adjpllin signal to connect with an upstream PLL,gui_pll_mode=Fractional-N PLL,gui_ps_units0=ps,gui_ps_units1=ps,gui_ps_units10=ps,gui_ps_units11=ps,gui_ps_units12=ps,gui_ps_units13=ps,gui_ps_units14=ps,gui_ps_units15=ps,gui_ps_units16=ps,gui_ps_units17=ps,gui_ps_units2=ps,gui_ps_units3=ps,gui_ps_units4=ps,gui_ps_units5=ps,gui_ps_units6=ps,gui_ps_units7=ps,gui_ps_units8=ps,gui_ps_units9=ps,gui_refclk1_frequency=100.0,gui_refclk_switch=false,gui_reference_clock_frequency=50.0,gui_switchover_delay=0,gui_switchover_mode=Automatic Switchover,gui_use_locked=false,m_cnt_bypass_en=false,m_cnt_hi_div=8,m_cnt_lo_div=7,m_cnt_odd_div_duty_en=true,mimic_fbclk_type=gclk,n_cnt_bypass_en=true,n_cnt_hi_div=256,n_cnt_lo_div=256,n_cnt_odd_div_duty_en=false,number_of_cascade_counters=0,number_of_clocks=8,operation_mode=normal,output_clock_frequency0=255.999872 MHz,output_clock_frequency1=109.714257 MHz,output_clock_frequency10=0 MHz,output_clock_frequency11=0 MHz,output_clock_frequency12=0 MHz,output_clock_frequency13=0 MHz,output_clock_frequency14=0 MHz,output_clock_frequency15=0 MHz,output_clock_frequency16=0 MHz,output_clock_frequency17=0 MHz,output_clock_frequency2=63.999981 MHz,output_clock_frequency3=31.999989 MHz,output_clock_frequency4=15.999994 MHz,output_clock_frequency5=7.999996 MHz,output_clock_frequency6=3.999998 MHz,output_clock_frequency7=1.999999 MHz,output_clock_frequency8=0 MHz,output_clock_frequency9=0 MHz,phase_shift0=0 ps,phase_shift1=0 ps,phase_shift10=0 ps,phase_shift11=0 ps,phase_shift12=0 ps,phase_shift13=0 ps,phase_shift14=0 ps,phase_shift15=0 ps,phase_shift16=0 ps,phase_shift17=0 ps,phase_shift2=0 ps,phase_shift3=0 ps,phase_shift4=0 ps,phase_shift5=0 ps,phase_shift6=0 ps,phase_shift7=0 ps,phase_shift8=0 ps,phase_shift9=0 ps,pll_auto_clk_sw_en=false,pll_bwctrl=4000,pll_clk_loss_sw_en=false,pll_clk_sw_dly=0,pll_clkin_0_src=clk_0,pll_clkin_1_src=clk_0,pll_cp_current=20,pll_dsm_out_sel=1st_order,pll_fbclk_mux_1=glb,pll_fbclk_mux_2=fb_1,pll_fractional_cout=32,pll_fractional_division=1546159966,pll_m_cnt_in_src=ph_mux_clk,pll_manu_clk_sw_en=false,pll_output_clk_frequency=767.999671 MHz,pll_slf_rst=true,pll_subtype=General,pll_type=General,pll_vco_div=1,pll_vcoph_div=1,refclk1_frequency=100.0 MHz,reference_clock_frequency=50.0 MHz)(altera_pll:17.1:c_cnt_bypass_en0=false,c_cnt_bypass_en1=false,c_cnt_bypass_en10=true,c_cnt_bypass_en11=true,c_cnt_bypass_en12=true,c_cnt_bypass_en13=true,c_cnt_bypass_en14=true,c_cnt_bypass_en15=true,c_cnt_bypass_en16=true,c_cnt_bypass_en17=true,c_cnt_bypass_en2=false,c_cnt_bypass_en3=false,c_cnt_bypass_en4=false,c_cnt_bypass_en5=true,c_cnt_bypass_en6=true,c_cnt_bypass_en7=true,c_cnt_bypass_en8=true,c_cnt_bypass_en9=true,c_cnt_hi_div0=7,c_cnt_hi_div1=14,c_cnt_hi_div10=1,c_cnt_hi_div11=1,c_cnt_hi_div12=1,c_cnt_hi_div13=1,c_cnt_hi_div14=1,c_cnt_hi_div15=1,c_cnt_hi_div16=1,c_cnt_hi_div17=1,c_cnt_hi_div2=28,c_cnt_hi_div3=56,c_cnt_hi_div4=112,c_cnt_hi_div5=1,c_cnt_hi_div6=1,c_cnt_hi_div7=1,c_cnt_hi_div8=1,c_cnt_hi_div9=1,c_cnt_in_src0=ph_mux_clk,c_cnt_in_src1=ph_mux_clk,c_cnt_in_src10=ph_mux_clk,c_cnt_in_src11=ph_mux_clk,c_cnt_in_src12=ph_mux_clk,c_cnt_in_src13=ph_mux_clk,c_cnt_in_src14=ph_mux_clk,c_cnt_in_src15=ph_mux_clk,c_cnt_in_src16=ph_mux_clk,c_cnt_in_src17=ph_mux_clk,c_cnt_in_src2=ph_mux_clk,c_cnt_in_src3=ph_mux_clk,c_cnt_in_src4=ph_mux_clk,c_cnt_in_src5=ph_mux_clk,c_cnt_in_src6=ph_mux_clk,c_cnt_in_src7=ph_mux_clk,c_cnt_in_src8=ph_mux_clk,c_cnt_in_src9=ph_mux_clk,c_cnt_lo_div0=7,c_cnt_lo_div1=14,c_cnt_lo_div10=1,c_cnt_lo_div11=1,c_cnt_lo_div12=1,c_cnt_lo_div13=1,c_cnt_lo_div14=1,c_cnt_lo_div15=1,c_cnt_lo_div16=1,c_cnt_lo_div17=1,c_cnt_lo_div2=28,c_cnt_lo_div3=56,c_cnt_lo_div4=112,c_cnt_lo_div5=1,c_cnt_lo_div6=1,c_cnt_lo_div7=1,c_cnt_lo_div8=1,c_cnt_lo_div9=1,c_cnt_odd_div_duty_en0=false,c_cnt_odd_div_duty_en1=false,c_cnt_odd_div_duty_en10=false,c_cnt_odd_div_duty_en11=false,c_cnt_odd_div_duty_en12=false,c_cnt_odd_div_duty_en13=false,c_cnt_odd_div_duty_en14=false,c_cnt_odd_div_duty_en15=false,c_cnt_odd_div_duty_en16=false,c_cnt_odd_div_duty_en17=false,c_cnt_odd_div_duty_en2=false,c_cnt_odd_div_duty_en3=false,c_cnt_odd_div_duty_en4=false,c_cnt_odd_div_duty_en5=false,c_cnt_odd_div_duty_en6=false,c_cnt_odd_div_duty_en7=false,c_cnt_odd_div_duty_en8=false,c_cnt_odd_div_duty_en9=false,c_cnt_ph_mux_prst0=0,c_cnt_ph_mux_prst1=0,c_cnt_ph_mux_prst10=0,c_cnt_ph_mux_prst11=0,c_cnt_ph_mux_prst12=0,c_cnt_ph_mux_prst13=0,c_cnt_ph_mux_prst14=0,c_cnt_ph_mux_prst15=0,c_cnt_ph_mux_prst16=0,c_cnt_ph_mux_prst17=0,c_cnt_ph_mux_prst2=0,c_cnt_ph_mux_prst3=0,c_cnt_ph_mux_prst4=0,c_cnt_ph_mux_prst5=0,c_cnt_ph_mux_prst6=0,c_cnt_ph_mux_prst7=0,c_cnt_ph_mux_prst8=0,c_cnt_ph_mux_prst9=0,c_cnt_prst0=1,c_cnt_prst1=1,c_cnt_prst10=1,c_cnt_prst11=1,c_cnt_prst12=1,c_cnt_prst13=1,c_cnt_prst14=1,c_cnt_prst15=1,c_cnt_prst16=1,c_cnt_prst17=1,c_cnt_prst2=1,c_cnt_prst3=1,c_cnt_prst4=1,c_cnt_prst5=1,c_cnt_prst6=1,c_cnt_prst7=1,c_cnt_prst8=1,c_cnt_prst9=1,debug_print_output=false,debug_use_rbc_taf_method=false,device=5CSEBA6U23I7,device_family=Cyclone V,duty_cycle0=50,duty_cycle1=50,duty_cycle10=50,duty_cycle11=50,duty_cycle12=50,duty_cycle13=50,duty_cycle14=50,duty_cycle15=50,duty_cycle16=50,duty_cycle17=50,duty_cycle2=50,duty_cycle3=50,duty_cycle4=50,duty_cycle5=50,duty_cycle6=50,duty_cycle7=50,duty_cycle8=50,duty_cycle9=50,fractional_vco_multiplier=false,gui_active_clk=false,gui_actual_divide_factor0=406,gui_actual_divide_factor1=812,gui_actual_divide_factor10=1,gui_actual_divide_factor11=1,gui_actual_divide_factor12=1,gui_actual_divide_factor13=1,gui_actual_divide_factor14=1,gui_actual_divide_factor15=1,gui_actual_divide_factor16=1,gui_actual_divide_factor17=1,gui_actual_divide_factor2=1624,gui_actual_divide_factor3=3248,gui_actual_divide_factor4=6496,gui_actual_divide_factor5=1,gui_actual_divide_factor6=1,gui_actual_divide_factor7=1,gui_actual_divide_factor8=1,gui_actual_divide_factor9=1,gui_actual_frac_multiply_factor0=1,gui_actual_frac_multiply_factor1=1,gui_actual_frac_multiply_factor10=1,gui_actual_frac_multiply_factor11=1,gui_actual_frac_multiply_factor12=1,gui_actual_frac_multiply_factor13=1,gui_actual_frac_multiply_factor14=1,gui_actual_frac_multiply_factor15=1,gui_actual_frac_multiply_factor16=1,gui_actual_frac_multiply_factor17=1,gui_actual_frac_multiply_factor2=1,gui_actual_frac_multiply_factor3=1,gui_actual_frac_multiply_factor4=1,gui_actual_frac_multiply_factor5=1,gui_actual_frac_multiply_factor6=1,gui_actual_frac_multiply_factor7=1,gui_actual_frac_multiply_factor8=1,gui_actual_frac_multiply_factor9=1,gui_actual_multiply_factor0=90,gui_actual_multiply_factor1=90,gui_actual_multiply_factor10=1,gui_actual_multiply_factor11=1,gui_actual_multiply_factor12=1,gui_actual_multiply_factor13=1,gui_actual_multiply_factor14=1,gui_actual_multiply_factor15=1,gui_actual_multiply_factor16=1,gui_actual_multiply_factor17=1,gui_actual_multiply_factor2=90,gui_actual_multiply_factor3=90,gui_actual_multiply_factor4=90,gui_actual_multiply_factor5=1,gui_actual_multiply_factor6=1,gui_actual_multiply_factor7=1,gui_actual_multiply_factor8=1,gui_actual_multiply_factor9=1,gui_actual_output_clock_frequency0=0 MHz,gui_actual_output_clock_frequency1=0 MHz,gui_actual_output_clock_frequency10=0 MHz,gui_actual_output_clock_frequency11=0 MHz,gui_actual_output_clock_frequency12=0 MHz,gui_actual_output_clock_frequency13=0 MHz,gui_actual_output_clock_frequency14=0 MHz,gui_actual_output_clock_frequency15=0 MHz,gui_actual_output_clock_frequency16=0 MHz,gui_actual_output_clock_frequency17=0 MHz,gui_actual_output_clock_frequency2=0 MHz,gui_actual_output_clock_frequency3=0 MHz,gui_actual_output_clock_frequency4=0 MHz,gui_actual_output_clock_frequency5=0 MHz,gui_actual_output_clock_frequency6=0 MHz,gui_actual_output_clock_frequency7=0 MHz,gui_actual_output_clock_frequency8=0 MHz,gui_actual_output_clock_frequency9=0 MHz,gui_actual_phase_shift0=0,gui_actual_phase_shift1=0,gui_actual_phase_shift10=0,gui_actual_phase_shift11=0,gui_actual_phase_shift12=0,gui_actual_phase_shift13=0,gui_actual_phase_shift14=0,gui_actual_phase_shift15=0,gui_actual_phase_shift16=0,gui_actual_phase_shift17=0,gui_actual_phase_shift2=0,gui_actual_phase_shift3=0,gui_actual_phase_shift4=0,gui_actual_phase_shift5=0,gui_actual_phase_shift6=0,gui_actual_phase_shift7=0,gui_actual_phase_shift8=0,gui_actual_phase_shift9=0,gui_cascade_counter0=false,gui_cascade_counter1=false,gui_cascade_counter10=false,gui_cascade_counter11=false,gui_cascade_counter12=false,gui_cascade_counter13=false,gui_cascade_counter14=false,gui_cascade_counter15=false,gui_cascade_counter16=false,gui_cascade_counter17=false,gui_cascade_counter2=false,gui_cascade_counter3=false,gui_cascade_counter4=false,gui_cascade_counter5=false,gui_cascade_counter6=false,gui_cascade_counter7=false,gui_cascade_counter8=false,gui_cascade_counter9=false,gui_cascade_outclk_index=0,gui_channel_spacing=0.0,gui_clk_bad=false,gui_device_speed_grade=2,gui_divide_factor_c0=1,gui_divide_factor_c1=1,gui_divide_factor_c10=1,gui_divide_factor_c11=1,gui_divide_factor_c12=1,gui_divide_factor_c13=1,gui_divide_factor_c14=1,gui_divide_factor_c15=1,gui_divide_factor_c16=1,gui_divide_factor_c17=1,gui_divide_factor_c2=1,gui_divide_factor_c3=1,gui_divide_factor_c4=1,gui_divide_factor_c5=1,gui_divide_factor_c6=1,gui_divide_factor_c7=1,gui_divide_factor_c8=1,gui_divide_factor_c9=1,gui_divide_factor_n=1,gui_dps_cntr=C0,gui_dps_dir=Positive,gui_dps_num=1,gui_dsm_out_sel=1st_order,gui_duty_cycle0=50,gui_duty_cycle1=50,gui_duty_cycle10=50,gui_duty_cycle11=50,gui_duty_cycle12=50,gui_duty_cycle13=50,gui_duty_cycle14=50,gui_duty_cycle15=50,gui_duty_cycle16=50,gui_duty_cycle17=50,gui_duty_cycle2=50,gui_duty_cycle3=50,gui_duty_cycle4=50,gui_duty_cycle5=50,gui_duty_cycle6=50,gui_duty_cycle7=50,gui_duty_cycle8=50,gui_duty_cycle9=50,gui_en_adv_params=false,gui_en_dps_ports=false,gui_en_phout_ports=false,gui_en_reconf=false,gui_enable_cascade_in=false,gui_enable_cascade_out=false,gui_enable_mif_dps=false,gui_feedback_clock=Global Clock,gui_frac_multiply_factor=1,gui_fractional_cout=32,gui_mif_generate=false,gui_multiply_factor=1,gui_number_of_clocks=5,gui_operation_mode=normal,gui_output_clock_frequency0=56.75,gui_output_clock_frequency1=28.375,gui_output_clock_frequency10=100.0,gui_output_clock_frequency11=100.0,gui_output_clock_frequency12=100.0,gui_output_clock_frequency13=100.0,gui_output_clock_frequency14=100.0,gui_output_clock_frequency15=100.0,gui_output_clock_frequency16=100.0,gui_output_clock_frequency17=100.0,gui_output_clock_frequency2=14.1875,gui_output_clock_frequency3=7.09375,gui_output_clock_frequency4=3.546875,gui_output_clock_frequency5=7.09375,gui_output_clock_frequency6=3.546875,gui_output_clock_frequency7=3.546875,gui_output_clock_frequency8=3.546875,gui_output_clock_frequency9=100.0,gui_parameter_list=M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset,gui_parameter_values=45,45,15,14,false,false,false,true,7,7,1,0,ph_mux_clk,false,false,14,14,1,0,ph_mux_clk,false,false,28,28,1,0,ph_mux_clk,false,false,56,56,1,0,ph_mux_clk,false,false,112,112,1,0,ph_mux_clk,false,false,1,20,10000,794.482758 MHz,1,gclk,glb,fb_1,ph_mux_clk,true,gui_phase_shift0=0,gui_phase_shift1=0,gui_phase_shift10=0,gui_phase_shift11=0,gui_phase_shift12=0,gui_phase_shift13=0,gui_phase_shift14=0,gui_phase_shift15=0,gui_phase_shift16=0,gui_phase_shift17=0,gui_phase_shift2=0,gui_phase_shift3=0,gui_phase_shift4=0,gui_phase_shift5=0,gui_phase_shift6=0,gui_phase_shift7=0,gui_phase_shift8=0,gui_phase_shift9=0,gui_phase_shift_deg0=0.0,gui_phase_shift_deg1=0.0,gui_phase_shift_deg10=0.0,gui_phase_shift_deg11=0.0,gui_phase_shift_deg12=0.0,gui_phase_shift_deg13=0.0,gui_phase_shift_deg14=0.0,gui_phase_shift_deg15=0.0,gui_phase_shift_deg16=0.0,gui_phase_shift_deg17=0.0,gui_phase_shift_deg2=0.0,gui_phase_shift_deg3=0.0,gui_phase_shift_deg4=0.0,gui_phase_shift_deg5=0.0,gui_phase_shift_deg6=0.0,gui_phase_shift_deg7=0.0,gui_phase_shift_deg8=0.0,gui_phase_shift_deg9=0.0,gui_phout_division=1,gui_pll_auto_reset=On,gui_pll_bandwidth_preset=Auto,gui_pll_cascading_mode=Create an adjpllin signal to connect with an upstream PLL,gui_pll_mode=Integer-N PLL,gui_ps_units0=ps,gui_ps_units1=ps,gui_ps_units10=ps,gui_ps_units11=ps,gui_ps_units12=ps,gui_ps_units13=ps,gui_ps_units14=ps,gui_ps_units15=ps,gui_ps_units16=ps,gui_ps_units17=ps,gui_ps_units2=ps,gui_ps_units3=ps,gui_ps_units4=ps,gui_ps_units5=ps,gui_ps_units6=ps,gui_ps_units7=ps,gui_ps_units8=ps,gui_ps_units9=ps,gui_refclk1_frequency=100.0,gui_refclk_switch=false,gui_reference_clock_frequency=256.0,gui_switchover_delay=0,gui_switchover_mode=Automatic Switchover,gui_use_locked=false,m_cnt_bypass_en=false,m_cnt_hi_div=45,m_cnt_lo_div=45,m_cnt_odd_div_duty_en=false,mimic_fbclk_type=gclk,n_cnt_bypass_en=false,n_cnt_hi_div=15,n_cnt_lo_div=14,n_cnt_odd_div_duty_en=true,number_of_cascade_counters=0,number_of_clocks=5,operation_mode=normal,output_clock_frequency0=56.748768 MHz,output_clock_frequency1=28.374384 MHz,output_clock_frequency10=0 MHz,output_clock_frequency11=0 MHz,output_clock_frequency12=0 MHz,output_clock_frequency13=0 MHz,output_clock_frequency14=0 MHz,output_clock_frequency15=0 MHz,output_clock_frequency16=0 MHz,output_clock_frequency17=0 MHz,output_clock_frequency2=14.187192 MHz,output_clock_frequency3=7.093596 MHz,output_clock_frequency4=3.546798 MHz,output_clock_frequency5=0 MHz,output_clock_frequency6=0 MHz,output_clock_frequency7=0 MHz,output_clock_frequency8=0 MHz,output_clock_frequency9=0 MHz,phase_shift0=0 ps,phase_shift1=0 ps,phase_shift10=0 ps,phase_shift11=0 ps,phase_shift12=0 ps,phase_shift13=0 ps,phase_shift14=0 ps,phase_shift15=0 ps,phase_shift16=0 ps,phase_shift17=0 ps,phase_shift2=0 ps,phase_shift3=0 ps,phase_shift4=0 ps,phase_shift5=0 ps,phase_shift6=0 ps,phase_shift7=0 ps,phase_shift8=0 ps,phase_shift9=0 ps,pll_auto_clk_sw_en=false,pll_bwctrl=10000,pll_clk_loss_sw_en=false,pll_clk_sw_dly=0,pll_clkin_0_src=clk_0,pll_clkin_1_src=clk_0,pll_cp_current=20,pll_dsm_out_sel=1st_order,pll_fbclk_mux_1=glb,pll_fbclk_mux_2=fb_1,pll_fractional_cout=32,pll_fractional_division=1,pll_m_cnt_in_src=ph_mux_clk,pll_manu_clk_sw_en=false,pll_output_clk_frequency=794.482758 MHz,pll_slf_rst=true,pll_subtype=General,pll_type=General,pll_vco_div=1,pll_vcoph_div=1,refclk1_frequency=100.0 MHz,reference_clock_frequency=256.0 MHz)(altera_pll:17.1:c_cnt_bypass_en0=false,c_cnt_bypass_en1=false,c_cnt_bypass_en10=true,c_cnt_bypass_en11=true,c_cnt_bypass_en12=true,c_cnt_bypass_en13=true,c_cnt_bypass_en14=true,c_cnt_bypass_en15=true,c_cnt_bypass_en16=true,c_cnt_bypass_en17=true,c_cnt_bypass_en2=false,c_cnt_bypass_en3=false,c_cnt_bypass_en4=true,c_cnt_bypass_en5=true,c_cnt_bypass_en6=true,c_cnt_bypass_en7=true,c_cnt_bypass_en8=true,c_cnt_bypass_en9=true,c_cnt_hi_div0=26,c_cnt_hi_div1=32,c_cnt_hi_div10=1,c_cnt_hi_div11=1,c_cnt_hi_div12=1,c_cnt_hi_div13=1,c_cnt_hi_div14=1,c_cnt_hi_div15=1,c_cnt_hi_div16=1,c_cnt_hi_div17=1,c_cnt_hi_div2=45,c_cnt_hi_div3=90,c_cnt_hi_div4=1,c_cnt_hi_div5=1,c_cnt_hi_div6=1,c_cnt_hi_div7=1,c_cnt_hi_div8=1,c_cnt_hi_div9=1,c_cnt_in_src0=ph_mux_clk,c_cnt_in_src1=ph_mux_clk,c_cnt_in_src10=ph_mux_clk,c_cnt_in_src11=ph_mux_clk,c_cnt_in_src12=ph_mux_clk,c_cnt_in_src13=ph_mux_clk,c_cnt_in_src14=ph_mux_clk,c_cnt_in_src15=ph_mux_clk,c_cnt_in_src16=ph_mux_clk,c_cnt_in_src17=ph_mux_clk,c_cnt_in_src2=ph_mux_clk,c_cnt_in_src3=ph_mux_clk,c_cnt_in_src4=ph_mux_clk,c_cnt_in_src5=ph_mux_clk,c_cnt_in_src6=ph_mux_clk,c_cnt_in_src7=ph_mux_clk,c_cnt_in_src8=ph_mux_clk,c_cnt_in_src9=ph_mux_clk,c_cnt_lo_div0=25,c_cnt_lo_div1=31,c_cnt_lo_div10=1,c_cnt_lo_div11=1,c_cnt_lo_div12=1,c_cnt_lo_div13=1,c_cnt_lo_div14=1,c_cnt_lo_div15=1,c_cnt_lo_div16=1,c_cnt_lo_div17=1,c_cnt_lo_div2=44,c_cnt_lo_div3=89,c_cnt_lo_div4=1,c_cnt_lo_div5=1,c_cnt_lo_div6=1,c_cnt_lo_div7=1,c_cnt_lo_div8=1,c_cnt_lo_div9=1,c_cnt_odd_div_duty_en0=true,c_cnt_odd_div_duty_en1=true,c_cnt_odd_div_duty_en10=false,c_cnt_odd_div_duty_en11=false,c_cnt_odd_div_duty_en12=false,c_cnt_odd_div_duty_en13=false,c_cnt_odd_div_duty_en14=false,c_cnt_odd_div_duty_en15=false,c_cnt_odd_div_duty_en16=false,c_cnt_odd_div_duty_en17=false,c_cnt_odd_div_duty_en2=true,c_cnt_odd_div_duty_en3=true,c_cnt_odd_div_duty_en4=false,c_cnt_odd_div_duty_en5=false,c_cnt_odd_div_duty_en6=false,c_cnt_odd_div_duty_en7=false,c_cnt_odd_div_duty_en8=false,c_cnt_odd_div_duty_en9=false,c_cnt_ph_mux_prst0=0,c_cnt_ph_mux_prst1=0,c_cnt_ph_mux_prst10=0,c_cnt_ph_mux_prst11=0,c_cnt_ph_mux_prst12=0,c_cnt_ph_mux_prst13=0,c_cnt_ph_mux_prst14=0,c_cnt_ph_mux_prst15=0,c_cnt_ph_mux_prst16=0,c_cnt_ph_mux_prst17=0,c_cnt_ph_mux_prst2=0,c_cnt_ph_mux_prst3=0,c_cnt_ph_mux_prst4=0,c_cnt_ph_mux_prst5=0,c_cnt_ph_mux_prst6=0,c_cnt_ph_mux_prst7=0,c_cnt_ph_mux_prst8=0,c_cnt_ph_mux_prst9=0,c_cnt_prst0=1,c_cnt_prst1=1,c_cnt_prst10=1,c_cnt_prst11=1,c_cnt_prst12=1,c_cnt_prst13=1,c_cnt_prst14=1,c_cnt_prst15=1,c_cnt_prst16=1,c_cnt_prst17=1,c_cnt_prst2=1,c_cnt_prst3=1,c_cnt_prst4=1,c_cnt_prst5=1,c_cnt_prst6=1,c_cnt_prst7=1,c_cnt_prst8=1,c_cnt_prst9=1,debug_print_output=false,debug_use_rbc_taf_method=false,device=5CSEBA6U23I7,device_family=Cyclone V,duty_cycle0=50,duty_cycle1=50,duty_cycle10=50,duty_cycle11=50,duty_cycle12=50,duty_cycle13=50,duty_cycle14=50,duty_cycle15=50,duty_cycle16=50,duty_cycle17=50,duty_cycle2=50,duty_cycle3=50,duty_cycle4=50,duty_cycle5=50,duty_cycle6=50,duty_cycle7=50,duty_cycle8=50,duty_cycle9=50,fractional_vco_multiplier=true,gui_active_clk=false,gui_actual_divide_factor0=102,gui_actual_divide_factor1=126,gui_actual_divide_factor10=1,gui_actual_divide_factor11=1,gui_actual_divide_factor12=1,gui_actual_divide_factor13=1,gui_actual_divide_factor14=1,gui_actual_divide_factor15=1,gui_actual_divide_factor16=1,gui_actual_divide_factor17=1,gui_actual_divide_factor2=178,gui_actual_divide_factor3=358,gui_actual_divide_factor4=1,gui_actual_divide_factor5=1,gui_actual_divide_factor6=1,gui_actual_divide_factor7=1,gui_actual_divide_factor8=1,gui_actual_divide_factor9=1,gui_actual_frac_multiply_factor0=1681070366,gui_actual_frac_multiply_factor1=1681070366,gui_actual_frac_multiply_factor10=1,gui_actual_frac_multiply_factor11=1,gui_actual_frac_multiply_factor12=1,gui_actual_frac_multiply_factor13=1,gui_actual_frac_multiply_factor14=1,gui_actual_frac_multiply_factor15=1,gui_actual_frac_multiply_factor16=1,gui_actual_frac_multiply_factor17=1,gui_actual_frac_multiply_factor2=1681070366,gui_actual_frac_multiply_factor3=1681070366,gui_actual_frac_multiply_factor4=1,gui_actual_frac_multiply_factor5=1,gui_actual_frac_multiply_factor6=1,gui_actual_frac_multiply_factor7=1,gui_actual_frac_multiply_factor8=1,gui_actual_frac_multiply_factor9=1,gui_actual_multiply_factor0=12,gui_actual_multiply_factor1=12,gui_actual_multiply_factor10=1,gui_actual_multiply_factor11=1,gui_actual_multiply_factor12=1,gui_actual_multiply_factor13=1,gui_actual_multiply_factor14=1,gui_actual_multiply_factor15=1,gui_actual_multiply_factor16=1,gui_actual_multiply_factor17=1,gui_actual_multiply_factor2=12,gui_actual_multiply_factor3=12,gui_actual_multiply_factor4=1,gui_actual_multiply_factor5=1,gui_actual_multiply_factor6=1,gui_actual_multiply_factor7=1,gui_actual_multiply_factor8=1,gui_actual_multiply_factor9=1,gui_actual_output_clock_frequency0=36.000000 MHz,gui_actual_output_clock_frequency1=31.500000 MHz,gui_actual_output_clock_frequency10=0 MHz,gui_actual_output_clock_frequency11=0 MHz,gui_actual_output_clock_frequency12=0 MHz,gui_actual_output_clock_frequency13=0 MHz,gui_actual_output_clock_frequency14=0 MHz,gui_actual_output_clock_frequency15=0 MHz,gui_actual_output_clock_frequency16=0 MHz,gui_actual_output_clock_frequency17=0 MHz,gui_actual_output_clock_frequency2=25.568627 MHz,gui_actual_output_clock_frequency3=0 MHz,gui_actual_output_clock_frequency4=0 MHz,gui_actual_output_clock_frequency5=0 MHz,gui_actual_output_clock_frequency6=0 MHz,gui_actual_output_clock_frequency7=0 MHz,gui_actual_output_clock_frequency8=0 MHz,gui_actual_output_clock_frequency9=0 MHz,gui_actual_phase_shift0=0,gui_actual_phase_shift1=0,gui_actual_phase_shift10=0,gui_actual_phase_shift11=0,gui_actual_phase_shift12=0,gui_actual_phase_shift13=0,gui_actual_phase_shift14=0,gui_actual_phase_shift15=0,gui_actual_phase_shift16=0,gui_actual_phase_shift17=0,gui_actual_phase_shift2=0,gui_actual_phase_shift3=0,gui_actual_phase_shift4=0,gui_actual_phase_shift5=0,gui_actual_phase_shift6=0,gui_actual_phase_shift7=0,gui_actual_phase_shift8=0,gui_actual_phase_shift9=0,gui_cascade_counter0=false,gui_cascade_counter1=false,gui_cascade_counter10=false,gui_cascade_counter11=false,gui_cascade_counter12=false,gui_cascade_counter13=false,gui_cascade_counter14=false,gui_cascade_counter15=false,gui_cascade_counter16=false,gui_cascade_counter17=false,gui_cascade_counter2=false,gui_cascade_counter3=false,gui_cascade_counter4=false,gui_cascade_counter5=false,gui_cascade_counter6=false,gui_cascade_counter7=false,gui_cascade_counter8=false,gui_cascade_counter9=false,gui_cascade_outclk_index=0,gui_channel_spacing=0.0,gui_clk_bad=false,gui_device_speed_grade=1,gui_divide_factor_c0=1,gui_divide_factor_c1=1,gui_divide_factor_c10=1,gui_divide_factor_c11=1,gui_divide_factor_c12=1,gui_divide_factor_c13=1,gui_divide_factor_c14=1,gui_divide_factor_c15=1,gui_divide_factor_c16=1,gui_divide_factor_c17=1,gui_divide_factor_c2=1,gui_divide_factor_c3=1,gui_divide_factor_c4=1,gui_divide_factor_c5=1,gui_divide_factor_c6=1,gui_divide_factor_c7=1,gui_divide_factor_c8=1,gui_divide_factor_c9=1,gui_divide_factor_n=1,gui_dps_cntr=C0,gui_dps_dir=Positive,gui_dps_num=1,gui_dsm_out_sel=1st_order,gui_duty_cycle0=50,gui_duty_cycle1=50,gui_duty_cycle10=50,gui_duty_cycle11=50,gui_duty_cycle12=50,gui_duty_cycle13=50,gui_duty_cycle14=50,gui_duty_cycle15=50,gui_duty_cycle16=50,gui_duty_cycle17=50,gui_duty_cycle2=50,gui_duty_cycle3=50,gui_duty_cycle4=50,gui_duty_cycle5=50,gui_duty_cycle6=50,gui_duty_cycle7=50,gui_duty_cycle8=50,gui_duty_cycle9=50,gui_en_adv_params=false,gui_en_dps_ports=false,gui_en_phout_ports=false,gui_en_reconf=false,gui_enable_cascade_in=false,gui_enable_cascade_out=false,gui_enable_mif_dps=false,gui_feedback_clock=Global Clock,gui_frac_multiply_factor=1,gui_fractional_cout=32,gui_mif_generate=false,gui_multiply_factor=1,gui_number_of_clocks=4,gui_operation_mode=normal,gui_output_clock_frequency0=31.1,gui_output_clock_frequency1=25.175,gui_output_clock_frequency10=100.0,gui_output_clock_frequency11=100.0,gui_output_clock_frequency12=100.0,gui_output_clock_frequency13=100.0,gui_output_clock_frequency14=100.0,gui_output_clock_frequency15=100.0,gui_output_clock_frequency16=100.0,gui_output_clock_frequency17=100.0,gui_output_clock_frequency2=17.734475,gui_output_clock_frequency3=8.867237,gui_output_clock_frequency4=8.867237,gui_output_clock_frequency5=100.0,gui_output_clock_frequency6=100.0,gui_output_clock_frequency7=100.0,gui_output_clock_frequency8=100.0,gui_output_clock_frequency9=100.0,gui_parameter_list=M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset,gui_parameter_values=6,6,1,1,false,false,false,false,26,25,1,0,ph_mux_clk,false,true,32,31,1,0,ph_mux_clk,false,true,45,44,1,0,ph_mux_clk,false,true,90,89,1,0,ph_mux_clk,false,true,1,30,2000,1586.099801 MHz,1681070366,gclk,glb,fb_1,ph_mux_clk,true,gui_phase_shift0=0,gui_phase_shift1=0,gui_phase_shift10=0,gui_phase_shift11=0,gui_phase_shift12=0,gui_phase_shift13=0,gui_phase_shift14=0,gui_phase_shift15=0,gui_phase_shift16=0,gui_phase_shift17=0,gui_phase_shift2=0,gui_phase_shift3=0,gui_phase_shift4=0,gui_phase_shift5=0,gui_phase_shift6=0,gui_phase_shift7=0,gui_phase_shift8=0,gui_phase_shift9=0,gui_phase_shift_deg0=0.0,gui_phase_shift_deg1=0.0,gui_phase_shift_deg10=0.0,gui_phase_shift_deg11=0.0,gui_phase_shift_deg12=0.0,gui_phase_shift_deg13=0.0,gui_phase_shift_deg14=0.0,gui_phase_shift_deg15=0.0,gui_phase_shift_deg16=0.0,gui_phase_shift_deg17=0.0,gui_phase_shift_deg2=0.0,gui_phase_shift_deg3=0.0,gui_phase_shift_deg4=0.0,gui_phase_shift_deg5=0.0,gui_phase_shift_deg6=0.0,gui_phase_shift_deg7=0.0,gui_phase_shift_deg8=0.0,gui_phase_shift_deg9=0.0,gui_phout_division=1,gui_pll_auto_reset=On,gui_pll_bandwidth_preset=Auto,gui_pll_cascading_mode=Create an adjpllin signal to connect with an upstream PLL,gui_pll_mode=Fractional-N PLL,gui_ps_units0=ps,gui_ps_units1=ps,gui_ps_units10=ps,gui_ps_units11=ps,gui_ps_units12=ps,gui_ps_units13=ps,gui_ps_units14=ps,gui_ps_units15=ps,gui_ps_units16=ps,gui_ps_units17=ps,gui_ps_units2=degrees,gui_ps_units3=ps,gui_ps_units4=ps,gui_ps_units5=ps,gui_ps_units6=ps,gui_ps_units7=ps,gui_ps_units8=ps,gui_ps_units9=ps,gui_refclk1_frequency=100.0,gui_refclk_switch=false,gui_reference_clock_frequency=256.0,gui_switchover_delay=0,gui_switchover_mode=Automatic Switchover,gui_use_locked=false,m_cnt_bypass_en=false,m_cnt_hi_div=6,m_cnt_lo_div=6,m_cnt_odd_div_duty_en=false,mimic_fbclk_type=gclk,n_cnt_bypass_en=false,n_cnt_hi_div=1,n_cnt_lo_div=1,n_cnt_odd_div_duty_en=false,number_of_cascade_counters=0,number_of_clocks=4,operation_mode=normal,output_clock_frequency0=31.099998 MHz,output_clock_frequency1=25.176188 MHz,output_clock_frequency10=0 MHz,output_clock_frequency11=0 MHz,output_clock_frequency12=0 MHz,output_clock_frequency13=0 MHz,output_clock_frequency14=0 MHz,output_clock_frequency15=0 MHz,output_clock_frequency16=0 MHz,output_clock_frequency17=0 MHz,output_clock_frequency2=17.821346 MHz,output_clock_frequency3=8.860892 MHz,output_clock_frequency4=0 MHz,output_clock_frequency5=0 MHz,output_clock_frequency6=0 MHz,output_clock_frequency7=0 MHz,output_clock_frequency8=0 MHz,output_clock_frequency9=0 MHz,phase_shift0=0 ps,phase_shift1=0 ps,phase_shift10=0 ps,phase_shift11=0 ps,phase_shift12=0 ps,phase_shift13=0 ps,phase_shift14=0 ps,phase_shift15=0 ps,phase_shift16=0 ps,phase_shift17=0 ps,phase_shift2=0 ps,phase_shift3=0 ps,phase_shift4=0 ps,phase_shift5=0 ps,phase_shift6=0 ps,phase_shift7=0 ps,phase_shift8=0 ps,phase_shift9=0 ps,pll_auto_clk_sw_en=false,pll_bwctrl=2000,pll_clk_loss_sw_en=false,pll_clk_sw_dly=0,pll_clkin_0_src=clk_0,pll_clkin_1_src=clk_0,pll_cp_current=30,pll_dsm_out_sel=1st_order,pll_fbclk_mux_1=glb,pll_fbclk_mux_2=fb_1,pll_fractional_cout=32,pll_fractional_division=1681070366,pll_m_cnt_in_src=ph_mux_clk,pll_manu_clk_sw_en=false,pll_output_clk_frequency=1586.099801 MHz,pll_slf_rst=true,pll_subtype=General,pll_type=General,pll_vco_div=1,pll_vcoph_div=1,refclk1_frequency=100.0 MHz,reference_clock_frequency=256.0 MHz)(clock:17.1:)(clock:17.1:)"
+   instancePathKey="pll"
+   kind="pll"
+   version="1.0"
+   name="pll">
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_PLL_0_REFCLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1544470692" />
+  <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_PLL_0_REFCLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_PLL_0_REFCLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <generatedFiles>
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/pll.vhd"
+       type="VHDL" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_0.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_1.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_2.qip"
+       type="OTHER"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file path="/srv/dvlp/Projects/dev/github/em/common/pll.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/srv/CAD/QuartusII/17.1/ip/altera/altera_pll/source/top/pll_hw.tcl" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/guava-15.0.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/javasysmon.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/ip/altera/altera_pll/source/top/pll_hw.tcl" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/guava-15.0.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/javasysmon.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/ip/altera/altera_pll/source/top/pll_hw.tcl" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/guava-15.0.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/javasysmon.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="pll">queue size: 0 starting:pll "pll"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>4</b> modules, <b>2</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="pll"><![CDATA["<b>pll</b>" reuses <b>altera_pll</b> "<b>submodules/pll_pll_0</b>"]]></message>
+   <message level="Debug" culprit="pll"><![CDATA["<b>pll</b>" reuses <b>altera_pll</b> "<b>submodules/pll_pll_1</b>"]]></message>
+   <message level="Debug" culprit="pll"><![CDATA["<b>pll</b>" reuses <b>altera_pll</b> "<b>submodules/pll_pll_2</b>"]]></message>
+   <message level="Debug" culprit="pll">queue size: 2 starting:altera_pll "submodules/pll_pll_0"</message>
+   <message level="Info" culprit="pll_0"><![CDATA["<b>pll</b>" instantiated <b>altera_pll</b> "<b>pll_0</b>"]]></message>
+   <message level="Debug" culprit="pll">queue size: 1 starting:altera_pll "submodules/pll_pll_1"</message>
+   <message level="Info" culprit="pll_1"><![CDATA["<b>pll</b>" instantiated <b>altera_pll</b> "<b>pll_1</b>"]]></message>
+   <message level="Debug" culprit="pll">queue size: 0 starting:altera_pll "submodules/pll_pll_2"</message>
+   <message level="Info" culprit="pll_2"><![CDATA["<b>pll</b>" instantiated <b>altera_pll</b> "<b>pll_2</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_pll:17.1:c_cnt_bypass_en0=false,c_cnt_bypass_en1=false,c_cnt_bypass_en10=true,c_cnt_bypass_en11=true,c_cnt_bypass_en12=true,c_cnt_bypass_en13=true,c_cnt_bypass_en14=true,c_cnt_bypass_en15=true,c_cnt_bypass_en16=true,c_cnt_bypass_en17=true,c_cnt_bypass_en2=false,c_cnt_bypass_en3=false,c_cnt_bypass_en4=false,c_cnt_bypass_en5=false,c_cnt_bypass_en6=false,c_cnt_bypass_en7=false,c_cnt_bypass_en8=true,c_cnt_bypass_en9=true,c_cnt_hi_div0=2,c_cnt_hi_div1=4,c_cnt_hi_div10=1,c_cnt_hi_div11=1,c_cnt_hi_div12=1,c_cnt_hi_div13=1,c_cnt_hi_div14=1,c_cnt_hi_div15=1,c_cnt_hi_div16=1,c_cnt_hi_div17=1,c_cnt_hi_div2=6,c_cnt_hi_div3=12,c_cnt_hi_div4=24,c_cnt_hi_div5=48,c_cnt_hi_div6=96,c_cnt_hi_div7=192,c_cnt_hi_div8=1,c_cnt_hi_div9=1,c_cnt_in_src0=ph_mux_clk,c_cnt_in_src1=ph_mux_clk,c_cnt_in_src10=ph_mux_clk,c_cnt_in_src11=ph_mux_clk,c_cnt_in_src12=ph_mux_clk,c_cnt_in_src13=ph_mux_clk,c_cnt_in_src14=ph_mux_clk,c_cnt_in_src15=ph_mux_clk,c_cnt_in_src16=ph_mux_clk,c_cnt_in_src17=ph_mux_clk,c_cnt_in_src2=ph_mux_clk,c_cnt_in_src3=ph_mux_clk,c_cnt_in_src4=ph_mux_clk,c_cnt_in_src5=ph_mux_clk,c_cnt_in_src6=ph_mux_clk,c_cnt_in_src7=ph_mux_clk,c_cnt_in_src8=ph_mux_clk,c_cnt_in_src9=ph_mux_clk,c_cnt_lo_div0=1,c_cnt_lo_div1=3,c_cnt_lo_div10=1,c_cnt_lo_div11=1,c_cnt_lo_div12=1,c_cnt_lo_div13=1,c_cnt_lo_div14=1,c_cnt_lo_div15=1,c_cnt_lo_div16=1,c_cnt_lo_div17=1,c_cnt_lo_div2=6,c_cnt_lo_div3=12,c_cnt_lo_div4=24,c_cnt_lo_div5=48,c_cnt_lo_div6=96,c_cnt_lo_div7=192,c_cnt_lo_div8=1,c_cnt_lo_div9=1,c_cnt_odd_div_duty_en0=true,c_cnt_odd_div_duty_en1=true,c_cnt_odd_div_duty_en10=false,c_cnt_odd_div_duty_en11=false,c_cnt_odd_div_duty_en12=false,c_cnt_odd_div_duty_en13=false,c_cnt_odd_div_duty_en14=false,c_cnt_odd_div_duty_en15=false,c_cnt_odd_div_duty_en16=false,c_cnt_odd_div_duty_en17=false,c_cnt_odd_div_duty_en2=false,c_cnt_odd_div_duty_en3=false,c_cnt_odd_div_duty_en4=false,c_cnt_odd_div_duty_en5=false,c_cnt_odd_div_duty_en6=false,c_cnt_odd_div_duty_en7=false,c_cnt_odd_div_duty_en8=false,c_cnt_odd_div_duty_en9=false,c_cnt_ph_mux_prst0=0,c_cnt_ph_mux_prst1=0,c_cnt_ph_mux_prst10=0,c_cnt_ph_mux_prst11=0,c_cnt_ph_mux_prst12=0,c_cnt_ph_mux_prst13=0,c_cnt_ph_mux_prst14=0,c_cnt_ph_mux_prst15=0,c_cnt_ph_mux_prst16=0,c_cnt_ph_mux_prst17=0,c_cnt_ph_mux_prst2=0,c_cnt_ph_mux_prst3=0,c_cnt_ph_mux_prst4=0,c_cnt_ph_mux_prst5=0,c_cnt_ph_mux_prst6=0,c_cnt_ph_mux_prst7=0,c_cnt_ph_mux_prst8=0,c_cnt_ph_mux_prst9=0,c_cnt_prst0=1,c_cnt_prst1=1,c_cnt_prst10=1,c_cnt_prst11=1,c_cnt_prst12=1,c_cnt_prst13=1,c_cnt_prst14=1,c_cnt_prst15=1,c_cnt_prst16=1,c_cnt_prst17=1,c_cnt_prst2=1,c_cnt_prst3=1,c_cnt_prst4=1,c_cnt_prst5=1,c_cnt_prst6=1,c_cnt_prst7=1,c_cnt_prst8=1,c_cnt_prst9=1,debug_print_output=false,debug_use_rbc_taf_method=false,device=5CSEBA6U23I7,device_family=Cyclone V,duty_cycle0=50,duty_cycle1=50,duty_cycle10=50,duty_cycle11=50,duty_cycle12=50,duty_cycle13=50,duty_cycle14=50,duty_cycle15=50,duty_cycle16=50,duty_cycle17=50,duty_cycle2=50,duty_cycle3=50,duty_cycle4=50,duty_cycle5=50,duty_cycle6=50,duty_cycle7=50,duty_cycle8=50,duty_cycle9=50,fractional_vco_multiplier=true,gui_active_clk=false,gui_actual_divide_factor0=3,gui_actual_divide_factor1=7,gui_actual_divide_factor10=1,gui_actual_divide_factor11=1,gui_actual_divide_factor12=1,gui_actual_divide_factor13=1,gui_actual_divide_factor14=1,gui_actual_divide_factor15=1,gui_actual_divide_factor16=1,gui_actual_divide_factor17=1,gui_actual_divide_factor2=12,gui_actual_divide_factor3=24,gui_actual_divide_factor4=48,gui_actual_divide_factor5=96,gui_actual_divide_factor6=192,gui_actual_divide_factor7=384,gui_actual_divide_factor8=1,gui_actual_divide_factor9=1,gui_actual_frac_multiply_factor0=1546159966,gui_actual_frac_multiply_factor1=1546159966,gui_actual_frac_multiply_factor10=1,gui_actual_frac_multiply_factor11=1,gui_actual_frac_multiply_factor12=1,gui_actual_frac_multiply_factor13=1,gui_actual_frac_multiply_factor14=1,gui_actual_frac_multiply_factor15=1,gui_actual_frac_multiply_factor16=1,gui_actual_frac_multiply_factor17=1,gui_actual_frac_multiply_factor2=1546159966,gui_actual_frac_multiply_factor3=1546159966,gui_actual_frac_multiply_factor4=1546159966,gui_actual_frac_multiply_factor5=1546159966,gui_actual_frac_multiply_factor6=1546159966,gui_actual_frac_multiply_factor7=1546159966,gui_actual_frac_multiply_factor8=1,gui_actual_frac_multiply_factor9=1,gui_actual_multiply_factor0=15,gui_actual_multiply_factor1=15,gui_actual_multiply_factor10=1,gui_actual_multiply_factor11=1,gui_actual_multiply_factor12=1,gui_actual_multiply_factor13=1,gui_actual_multiply_factor14=1,gui_actual_multiply_factor15=1,gui_actual_multiply_factor16=1,gui_actual_multiply_factor17=1,gui_actual_multiply_factor2=15,gui_actual_multiply_factor3=15,gui_actual_multiply_factor4=15,gui_actual_multiply_factor5=15,gui_actual_multiply_factor6=15,gui_actual_multiply_factor7=15,gui_actual_multiply_factor8=1,gui_actual_multiply_factor9=1,gui_actual_output_clock_frequency0=120.000000 MHz,gui_actual_output_clock_frequency1=0 MHz,gui_actual_output_clock_frequency10=0 MHz,gui_actual_output_clock_frequency11=0 MHz,gui_actual_output_clock_frequency12=0 MHz,gui_actual_output_clock_frequency13=0 MHz,gui_actual_output_clock_frequency14=0 MHz,gui_actual_output_clock_frequency15=0 MHz,gui_actual_output_clock_frequency16=0 MHz,gui_actual_output_clock_frequency17=0 MHz,gui_actual_output_clock_frequency2=0 MHz,gui_actual_output_clock_frequency3=32.533324 MHz,gui_actual_output_clock_frequency4=0 MHz,gui_actual_output_clock_frequency5=0 MHz,gui_actual_output_clock_frequency6=0 MHz,gui_actual_output_clock_frequency7=0 MHz,gui_actual_output_clock_frequency8=0 MHz,gui_actual_output_clock_frequency9=0 MHz,gui_actual_phase_shift0=0,gui_actual_phase_shift1=0,gui_actual_phase_shift10=0,gui_actual_phase_shift11=0,gui_actual_phase_shift12=0,gui_actual_phase_shift13=0,gui_actual_phase_shift14=0,gui_actual_phase_shift15=0,gui_actual_phase_shift16=0,gui_actual_phase_shift17=0,gui_actual_phase_shift2=0,gui_actual_phase_shift3=0,gui_actual_phase_shift4=0,gui_actual_phase_shift5=0,gui_actual_phase_shift6=0,gui_actual_phase_shift7=0,gui_actual_phase_shift8=0,gui_actual_phase_shift9=0,gui_cascade_counter0=false,gui_cascade_counter1=false,gui_cascade_counter10=false,gui_cascade_counter11=false,gui_cascade_counter12=false,gui_cascade_counter13=false,gui_cascade_counter14=false,gui_cascade_counter15=false,gui_cascade_counter16=false,gui_cascade_counter17=false,gui_cascade_counter2=false,gui_cascade_counter3=false,gui_cascade_counter4=false,gui_cascade_counter5=false,gui_cascade_counter6=false,gui_cascade_counter7=false,gui_cascade_counter8=false,gui_cascade_counter9=false,gui_cascade_outclk_index=0,gui_channel_spacing=0.0,gui_clk_bad=false,gui_device_speed_grade=2,gui_divide_factor_c0=1,gui_divide_factor_c1=1,gui_divide_factor_c10=1,gui_divide_factor_c11=1,gui_divide_factor_c12=1,gui_divide_factor_c13=1,gui_divide_factor_c14=1,gui_divide_factor_c15=1,gui_divide_factor_c16=1,gui_divide_factor_c17=1,gui_divide_factor_c2=1,gui_divide_factor_c3=1,gui_divide_factor_c4=1,gui_divide_factor_c5=1,gui_divide_factor_c6=1,gui_divide_factor_c7=1,gui_divide_factor_c8=1,gui_divide_factor_c9=1,gui_divide_factor_n=1,gui_dps_cntr=C0,gui_dps_dir=Positive,gui_dps_num=1,gui_dsm_out_sel=1st_order,gui_duty_cycle0=50,gui_duty_cycle1=50,gui_duty_cycle10=50,gui_duty_cycle11=50,gui_duty_cycle12=50,gui_duty_cycle13=50,gui_duty_cycle14=50,gui_duty_cycle15=50,gui_duty_cycle16=50,gui_duty_cycle17=50,gui_duty_cycle2=50,gui_duty_cycle3=50,gui_duty_cycle4=50,gui_duty_cycle5=50,gui_duty_cycle6=50,gui_duty_cycle7=50,gui_duty_cycle8=50,gui_duty_cycle9=50,gui_en_adv_params=false,gui_en_dps_ports=false,gui_en_phout_ports=false,gui_en_reconf=false,gui_enable_cascade_in=false,gui_enable_cascade_out=false,gui_enable_mif_dps=false,gui_feedback_clock=Global Clock,gui_frac_multiply_factor=1,gui_fractional_cout=32,gui_mif_generate=false,gui_multiply_factor=1,gui_number_of_clocks=8,gui_operation_mode=normal,gui_output_clock_frequency0=256.0,gui_output_clock_frequency1=112.0,gui_output_clock_frequency10=100.0,gui_output_clock_frequency11=100.0,gui_output_clock_frequency12=100.0,gui_output_clock_frequency13=100.0,gui_output_clock_frequency14=100.0,gui_output_clock_frequency15=100.0,gui_output_clock_frequency16=100.0,gui_output_clock_frequency17=100.0,gui_output_clock_frequency2=64.0,gui_output_clock_frequency3=32.0,gui_output_clock_frequency4=16.0,gui_output_clock_frequency5=8.0,gui_output_clock_frequency6=4.0,gui_output_clock_frequency7=2.0,gui_output_clock_frequency8=1.0,gui_output_clock_frequency9=100.0,gui_parameter_list=M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,C-Counter-5 Hi Divide,C-Counter-5 Low Divide,C-Counter-5 Coarse Phase Shift,C-Counter-5 VCO Phase Tap,C-Counter-5 Input Source,C-Counter-5 Bypass Enable,C-Counter-5 Odd Divide Enable,C-Counter-6 Hi Divide,C-Counter-6 Low Divide,C-Counter-6 Coarse Phase Shift,C-Counter-6 VCO Phase Tap,C-Counter-6 Input Source,C-Counter-6 Bypass Enable,C-Counter-6 Odd Divide Enable,C-Counter-7 Hi Divide,C-Counter-7 Low Divide,C-Counter-7 Coarse Phase Shift,C-Counter-7 VCO Phase Tap,C-Counter-7 Input Source,C-Counter-7 Bypass Enable,C-Counter-7 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset,gui_parameter_values=8,7,256,256,false,true,true,false,2,1,1,0,ph_mux_clk,false,true,4,3,1,0,ph_mux_clk,false,true,6,6,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,24,24,1,0,ph_mux_clk,false,false,48,48,1,0,ph_mux_clk,false,false,96,96,1,0,ph_mux_clk,false,false,192,192,1,0,ph_mux_clk,false,false,1,20,4000,767.999671 MHz,1546159966,gclk,glb,fb_1,ph_mux_clk,true,gui_phase_shift0=0,gui_phase_shift1=0,gui_phase_shift10=0,gui_phase_shift11=0,gui_phase_shift12=0,gui_phase_shift13=0,gui_phase_shift14=0,gui_phase_shift15=0,gui_phase_shift16=0,gui_phase_shift17=0,gui_phase_shift2=0,gui_phase_shift3=0,gui_phase_shift4=0,gui_phase_shift5=0,gui_phase_shift6=0,gui_phase_shift7=0,gui_phase_shift8=0,gui_phase_shift9=0,gui_phase_shift_deg0=0.0,gui_phase_shift_deg1=0.0,gui_phase_shift_deg10=0.0,gui_phase_shift_deg11=0.0,gui_phase_shift_deg12=0.0,gui_phase_shift_deg13=0.0,gui_phase_shift_deg14=0.0,gui_phase_shift_deg15=0.0,gui_phase_shift_deg16=0.0,gui_phase_shift_deg17=0.0,gui_phase_shift_deg2=0.0,gui_phase_shift_deg3=0.0,gui_phase_shift_deg4=0.0,gui_phase_shift_deg5=0.0,gui_phase_shift_deg6=0.0,gui_phase_shift_deg7=0.0,gui_phase_shift_deg8=0.0,gui_phase_shift_deg9=0.0,gui_phout_division=1,gui_pll_auto_reset=On,gui_pll_bandwidth_preset=Auto,gui_pll_cascading_mode=Create an adjpllin signal to connect with an upstream PLL,gui_pll_mode=Fractional-N PLL,gui_ps_units0=ps,gui_ps_units1=ps,gui_ps_units10=ps,gui_ps_units11=ps,gui_ps_units12=ps,gui_ps_units13=ps,gui_ps_units14=ps,gui_ps_units15=ps,gui_ps_units16=ps,gui_ps_units17=ps,gui_ps_units2=ps,gui_ps_units3=ps,gui_ps_units4=ps,gui_ps_units5=ps,gui_ps_units6=ps,gui_ps_units7=ps,gui_ps_units8=ps,gui_ps_units9=ps,gui_refclk1_frequency=100.0,gui_refclk_switch=false,gui_reference_clock_frequency=50.0,gui_switchover_delay=0,gui_switchover_mode=Automatic Switchover,gui_use_locked=false,m_cnt_bypass_en=false,m_cnt_hi_div=8,m_cnt_lo_div=7,m_cnt_odd_div_duty_en=true,mimic_fbclk_type=gclk,n_cnt_bypass_en=true,n_cnt_hi_div=256,n_cnt_lo_div=256,n_cnt_odd_div_duty_en=false,number_of_cascade_counters=0,number_of_clocks=8,operation_mode=normal,output_clock_frequency0=255.999872 MHz,output_clock_frequency1=109.714257 MHz,output_clock_frequency10=0 MHz,output_clock_frequency11=0 MHz,output_clock_frequency12=0 MHz,output_clock_frequency13=0 MHz,output_clock_frequency14=0 MHz,output_clock_frequency15=0 MHz,output_clock_frequency16=0 MHz,output_clock_frequency17=0 MHz,output_clock_frequency2=63.999981 MHz,output_clock_frequency3=31.999989 MHz,output_clock_frequency4=15.999994 MHz,output_clock_frequency5=7.999996 MHz,output_clock_frequency6=3.999998 MHz,output_clock_frequency7=1.999999 MHz,output_clock_frequency8=0 MHz,output_clock_frequency9=0 MHz,phase_shift0=0 ps,phase_shift1=0 ps,phase_shift10=0 ps,phase_shift11=0 ps,phase_shift12=0 ps,phase_shift13=0 ps,phase_shift14=0 ps,phase_shift15=0 ps,phase_shift16=0 ps,phase_shift17=0 ps,phase_shift2=0 ps,phase_shift3=0 ps,phase_shift4=0 ps,phase_shift5=0 ps,phase_shift6=0 ps,phase_shift7=0 ps,phase_shift8=0 ps,phase_shift9=0 ps,pll_auto_clk_sw_en=false,pll_bwctrl=4000,pll_clk_loss_sw_en=false,pll_clk_sw_dly=0,pll_clkin_0_src=clk_0,pll_clkin_1_src=clk_0,pll_cp_current=20,pll_dsm_out_sel=1st_order,pll_fbclk_mux_1=glb,pll_fbclk_mux_2=fb_1,pll_fractional_cout=32,pll_fractional_division=1546159966,pll_m_cnt_in_src=ph_mux_clk,pll_manu_clk_sw_en=false,pll_output_clk_frequency=767.999671 MHz,pll_slf_rst=true,pll_subtype=General,pll_type=General,pll_vco_div=1,pll_vcoph_div=1,refclk1_frequency=100.0 MHz,reference_clock_frequency=50.0 MHz"
+   instancePathKey="pll:.:pll_0"
+   kind="altera_pll"
+   version="17.1"
+   name="pll_pll_0">
+  <parameter name="c_cnt_bypass_en17" value="true" />
+  <parameter name="c_cnt_bypass_en14" value="true" />
+  <parameter name="c_cnt_bypass_en13" value="true" />
+  <parameter name="c_cnt_bypass_en16" value="true" />
+  <parameter name="c_cnt_bypass_en15" value="true" />
+  <parameter name="c_cnt_bypass_en10" value="true" />
+  <parameter name="c_cnt_bypass_en12" value="true" />
+  <parameter
+     name="gui_pll_cascading_mode"
+     value="Create an adjpllin signal to connect with an upstream PLL" />
+  <parameter name="c_cnt_bypass_en11" value="true" />
+  <parameter name="pll_fbclk_mux_2" value="fb_1" />
+  <parameter name="pll_fbclk_mux_1" value="glb" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="c_cnt_prst6" value="1" />
+  <parameter name="c_cnt_prst5" value="1" />
+  <parameter name="c_cnt_prst8" value="1" />
+  <parameter name="c_cnt_prst7" value="1" />
+  <parameter name="c_cnt_prst9" value="1" />
+  <parameter name="c_cnt_in_src9" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src8" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src5" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="c_cnt_in_src4" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src7" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src6" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="c_cnt_in_src1" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="c_cnt_in_src0" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="c_cnt_in_src3" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="c_cnt_in_src2" value="ph_mux_clk" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="duty_cycle12" value="50" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="duty_cycle13" value="50" />
+  <parameter name="duty_cycle10" value="50" />
+  <parameter name="duty_cycle11" value="50" />
+  <parameter name="duty_cycle16" value="50" />
+  <parameter name="duty_cycle17" value="50" />
+  <parameter name="duty_cycle14" value="50" />
+  <parameter name="duty_cycle15" value="50" />
+  <parameter name="pll_vcoph_div" value="1" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="pll_fractional_cout" value="32" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="pll_manu_clk_sw_en" value="false" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="c_cnt_prst0" value="1" />
+  <parameter name="c_cnt_prst2" value="1" />
+  <parameter name="c_cnt_prst1" value="1" />
+  <parameter name="gui_actual_divide_factor8" value="1" />
+  <parameter name="c_cnt_prst4" value="1" />
+  <parameter name="gui_actual_divide_factor9" value="1" />
+  <parameter name="c_cnt_prst3" value="1" />
+  <parameter name="gui_pll_auto_reset" value="On" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="phase_shift12" value="0 ps" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="phase_shift11" value="0 ps" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="phase_shift10" value="0 ps" />
+  <parameter name="n_cnt_lo_div" value="256" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_operation_mode" value="normal" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_actual_divide_factor6" value="192" />
+  <parameter name="gui_actual_divide_factor7" value="384" />
+  <parameter name="gui_actual_divide_factor4" value="48" />
+  <parameter name="gui_actual_divide_factor5" value="96" />
+  <parameter name="gui_actual_divide_factor2" value="12" />
+  <parameter name="gui_actual_divide_factor3" value="24" />
+  <parameter name="gui_actual_divide_factor0" value="3" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_actual_divide_factor1" value="7" />
+  <parameter name="gui_actual_frac_multiply_factor8" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor9" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor6" value="1546159966" />
+  <parameter name="gui_actual_frac_multiply_factor7" value="1546159966" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="phase_shift17" value="0 ps" />
+  <parameter name="pll_clk_sw_dly" value="0" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="phase_shift16" value="0 ps" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="phase_shift15" value="0 ps" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="phase_shift14" value="0 ps" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="phase_shift13" value="0 ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_pll_mode" value="Fractional-N PLL" />
+  <parameter name="gui_actual_frac_multiply_factor4" value="1546159966" />
+  <parameter name="gui_actual_frac_multiply_factor5" value="1546159966" />
+  <parameter name="gui_actual_frac_multiply_factor2" value="1546159966" />
+  <parameter name="gui_actual_frac_multiply_factor3" value="1546159966" />
+  <parameter name="gui_actual_frac_multiply_factor0" value="1546159966" />
+  <parameter name="gui_actual_frac_multiply_factor1" value="1546159966" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="pll_slf_rst" value="true" />
+  <parameter name="duty_cycle9" value="50" />
+  <parameter name="duty_cycle7" value="50" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="duty_cycle8" value="50" />
+  <parameter name="duty_cycle5" value="50" />
+  <parameter name="duty_cycle6" value="50" />
+  <parameter name="duty_cycle3" value="50" />
+  <parameter name="duty_cycle4" value="50" />
+  <parameter name="duty_cycle1" value="50" />
+  <parameter name="duty_cycle2" value="50" />
+  <parameter name="duty_cycle0" value="50" />
+  <parameter name="m_cnt_lo_div" value="7" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="pll_clk_loss_sw_en" value="false" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_use_locked" value="false" />
+  <parameter name="gui_actual_output_clock_frequency3" value="32.533324 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="pll_type" value="General" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency0" value="120.000000 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="pll_output_clk_frequency" value="767.999671 MHz" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="c_cnt_lo_div14" value="1" />
+  <parameter name="c_cnt_lo_div15" value="1" />
+  <parameter name="c_cnt_lo_div12" value="1" />
+  <parameter name="c_cnt_lo_div13" value="1" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="c_cnt_lo_div16" value="1" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="c_cnt_lo_div17" value="1" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="c_cnt_lo_div10" value="1" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="c_cnt_lo_div11" value="1" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="pll_fractional_division" value="1546159966" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="fractional_vco_multiplier" value="true" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="m_cnt_bypass_en" value="false" />
+  <parameter name="gui_number_of_clocks" value="8" />
+  <parameter name="c_cnt_hi_div10" value="1" />
+  <parameter name="c_cnt_hi_div11" value="1" />
+  <parameter name="c_cnt_hi_div12" value="1" />
+  <parameter name="c_cnt_hi_div13" value="1" />
+  <parameter name="c_cnt_hi_div14" value="1" />
+  <parameter name="c_cnt_hi_div15" value="1" />
+  <parameter name="c_cnt_hi_div16" value="1" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="c_cnt_hi_div17" value="1" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_output_clock_frequency0" value="256.0" />
+  <parameter name="output_clock_frequency10" value="0 MHz" />
+  <parameter name="output_clock_frequency11" value="0 MHz" />
+  <parameter name="output_clock_frequency12" value="0 MHz" />
+  <parameter name="pll_bwctrl" value="4000" />
+  <parameter name="output_clock_frequency13" value="0 MHz" />
+  <parameter name="mimic_fbclk_type" value="gclk" />
+  <parameter name="pll_clkin_0_src" value="clk_0" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="output_clock_frequency14" value="0 MHz" />
+  <parameter name="output_clock_frequency15" value="0 MHz" />
+  <parameter name="output_clock_frequency16" value="0 MHz" />
+  <parameter name="output_clock_frequency17" value="0 MHz" />
+  <parameter name="n_cnt_bypass_en" value="true" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="m_cnt_odd_div_duty_en" value="true" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="2.0" />
+  <parameter name="gui_output_clock_frequency8" value="1.0" />
+  <parameter name="gui_output_clock_frequency5" value="8.0" />
+  <parameter name="gui_output_clock_frequency6" value="4.0" />
+  <parameter name="gui_output_clock_frequency3" value="32.0" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_output_clock_frequency4" value="16.0" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_output_clock_frequency1" value="112.0" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_output_clock_frequency2" value="64.0" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_actual_divide_factor10" value="1" />
+  <parameter name="gui_actual_divide_factor16" value="1" />
+  <parameter name="device_family" value="Cyclone V" />
+  <parameter name="gui_actual_divide_factor15" value="1" />
+  <parameter name="gui_actual_divide_factor17" value="1" />
+  <parameter name="gui_actual_divide_factor12" value="1" />
+  <parameter name="gui_actual_divide_factor11" value="1" />
+  <parameter name="gui_actual_divide_factor14" value="1" />
+  <parameter name="gui_actual_divide_factor13" value="1" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_actual_multiply_factor9" value="1" />
+  <parameter name="gui_actual_multiply_factor6" value="15" />
+  <parameter name="gui_actual_multiply_factor5" value="15" />
+  <parameter name="gui_actual_multiply_factor8" value="1" />
+  <parameter name="gui_actual_multiply_factor7" value="15" />
+  <parameter name="gui_actual_multiply_factor2" value="15" />
+  <parameter name="gui_actual_multiply_factor1" value="15" />
+  <parameter name="gui_actual_multiply_factor4" value="15" />
+  <parameter name="gui_actual_multiply_factor3" value="15" />
+  <parameter name="refclk1_frequency" value="100.0 MHz" />
+  <parameter name="gui_actual_multiply_factor0" value="15" />
+  <parameter name="reference_clock_frequency" value="50.0 MHz" />
+  <parameter name="pll_m_cnt_in_src" value="ph_mux_clk" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="c_cnt_hi_div0" value="2" />
+  <parameter name="c_cnt_hi_div1" value="4" />
+  <parameter name="c_cnt_hi_div2" value="6" />
+  <parameter name="c_cnt_hi_div3" value="12" />
+  <parameter name="c_cnt_hi_div4" value="24" />
+  <parameter name="m_cnt_hi_div" value="8" />
+  <parameter name="c_cnt_hi_div5" value="48" />
+  <parameter name="c_cnt_hi_div6" value="96" />
+  <parameter name="c_cnt_hi_div7" value="192" />
+  <parameter name="n_cnt_odd_div_duty_en" value="false" />
+  <parameter name="c_cnt_hi_div8" value="1" />
+  <parameter name="c_cnt_hi_div9" value="1" />
+  <parameter name="c_cnt_ph_mux_prst8" value="0" />
+  <parameter name="c_cnt_ph_mux_prst7" value="0" />
+  <parameter name="c_cnt_ph_mux_prst9" value="0" />
+  <parameter name="c_cnt_ph_mux_prst0" value="0" />
+  <parameter name="c_cnt_ph_mux_prst2" value="0" />
+  <parameter name="c_cnt_ph_mux_prst1" value="0" />
+  <parameter name="c_cnt_ph_mux_prst4" value="0" />
+  <parameter name="c_cnt_ph_mux_prst3" value="0" />
+  <parameter name="c_cnt_ph_mux_prst6" value="0" />
+  <parameter name="c_cnt_ph_mux_prst5" value="0" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_switchover_mode" value="Automatic Switchover" />
+  <parameter
+     name="gui_parameter_values"
+     value="8,7,256,256,false,true,true,false,2,1,1,0,ph_mux_clk,false,true,4,3,1,0,ph_mux_clk,false,true,6,6,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,24,24,1,0,ph_mux_clk,false,false,48,48,1,0,ph_mux_clk,false,false,96,96,1,0,ph_mux_clk,false,false,192,192,1,0,ph_mux_clk,false,false,1,20,4000,767.999671 MHz,1546159966,gclk,glb,fb_1,ph_mux_clk,true" />
+  <parameter name="pll_auto_clk_sw_en" value="false" />
+  <parameter name="pll_subtype" value="General" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_actual_multiply_factor10" value="1" />
+  <parameter name="gui_actual_multiply_factor11" value="1" />
+  <parameter name="c_cnt_in_src17" value="ph_mux_clk" />
+  <parameter name="gui_actual_multiply_factor12" value="1" />
+  <parameter name="c_cnt_in_src16" value="ph_mux_clk" />
+  <parameter name="gui_actual_multiply_factor13" value="1" />
+  <parameter name="c_cnt_in_src15" value="ph_mux_clk" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="c_cnt_odd_div_duty_en0" value="true" />
+  <parameter name="c_cnt_odd_div_duty_en1" value="true" />
+  <parameter name="c_cnt_in_src14" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src13" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src12" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src11" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src10" value="ph_mux_clk" />
+  <parameter name="pll_vco_div" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en2" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en3" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en4" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en5" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en6" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en7" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en8" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en9" value="false" />
+  <parameter name="c_cnt_prst13" value="1" />
+  <parameter name="c_cnt_prst12" value="1" />
+  <parameter name="c_cnt_prst11" value="1" />
+  <parameter name="c_cnt_prst10" value="1" />
+  <parameter name="c_cnt_prst17" value="1" />
+  <parameter name="c_cnt_prst16" value="1" />
+  <parameter name="pll_dsm_out_sel" value="1st_order" />
+  <parameter name="c_cnt_prst15" value="1" />
+  <parameter name="c_cnt_prst14" value="1" />
+  <parameter name="c_cnt_lo_div9" value="1" />
+  <parameter name="c_cnt_lo_div7" value="192" />
+  <parameter name="c_cnt_lo_div8" value="1" />
+  <parameter name="number_of_cascade_counters" value="0" />
+  <parameter name="c_cnt_lo_div5" value="48" />
+  <parameter name="c_cnt_lo_div6" value="96" />
+  <parameter name="c_cnt_lo_div3" value="12" />
+  <parameter name="c_cnt_lo_div4" value="24" />
+  <parameter name="c_cnt_lo_div1" value="3" />
+  <parameter name="c_cnt_lo_div2" value="6" />
+  <parameter name="c_cnt_lo_div0" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor12" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor11" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor10" value="1" />
+  <parameter name="pll_cp_current" value="20" />
+  <parameter name="gui_actual_frac_multiply_factor16" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor15" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor14" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor13" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor17" value="1" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="pll_clkin_1_src" value="clk_0" />
+  <parameter name="phase_shift1" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst17" value="0" />
+  <parameter name="phase_shift0" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst16" value="0" />
+  <parameter name="phase_shift3" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst15" value="0" />
+  <parameter name="phase_shift2" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst14" value="0" />
+  <parameter name="phase_shift5" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst13" value="0" />
+  <parameter name="phase_shift4" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst12" value="0" />
+  <parameter name="phase_shift7" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst11" value="0" />
+  <parameter name="phase_shift6" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst10" value="0" />
+  <parameter name="phase_shift9" value="0 ps" />
+  <parameter name="phase_shift8" value="0 ps" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="number_of_clocks" value="8" />
+  <parameter name="n_cnt_hi_div" value="256" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="output_clock_frequency7" value="1.999999 MHz" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="output_clock_frequency5" value="7.999996 MHz" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="output_clock_frequency6" value="3.999998 MHz" />
+  <parameter name="output_clock_frequency9" value="0 MHz" />
+  <parameter
+     name="gui_parameter_list"
+     value="M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,C-Counter-5 Hi Divide,C-Counter-5 Low Divide,C-Counter-5 Coarse Phase Shift,C-Counter-5 VCO Phase Tap,C-Counter-5 Input Source,C-Counter-5 Bypass Enable,C-Counter-5 Odd Divide Enable,C-Counter-6 Hi Divide,C-Counter-6 Low Divide,C-Counter-6 Coarse Phase Shift,C-Counter-6 VCO Phase Tap,C-Counter-6 Input Source,C-Counter-6 Bypass Enable,C-Counter-6 Odd Divide Enable,C-Counter-7 Hi Divide,C-Counter-7 Low Divide,C-Counter-7 Coarse Phase Shift,C-Counter-7 VCO Phase Tap,C-Counter-7 Input Source,C-Counter-7 Bypass Enable,C-Counter-7 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en17" value="false" />
+  <parameter name="operation_mode" value="normal" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_actual_multiply_factor14" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en16" value="false" />
+  <parameter name="gui_actual_multiply_factor15" value="1" />
+  <parameter name="output_clock_frequency0" value="255.999872 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en15" value="false" />
+  <parameter name="gui_actual_multiply_factor16" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en14" value="false" />
+  <parameter name="gui_actual_multiply_factor17" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en13" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="output_clock_frequency3" value="31.999989 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en12" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="output_clock_frequency4" value="15.999994 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en11" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="output_clock_frequency1" value="109.714257 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en10" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="output_clock_frequency2" value="63.999981 MHz" />
+  <parameter name="c_cnt_bypass_en6" value="false" />
+  <parameter name="c_cnt_bypass_en7" value="false" />
+  <parameter name="c_cnt_bypass_en8" value="true" />
+  <parameter name="c_cnt_bypass_en9" value="true" />
+  <parameter name="c_cnt_bypass_en0" value="false" />
+  <parameter name="c_cnt_bypass_en1" value="false" />
+  <parameter name="c_cnt_bypass_en2" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="50.0" />
+  <parameter name="c_cnt_bypass_en3" value="false" />
+  <parameter name="c_cnt_bypass_en4" value="false" />
+  <parameter name="c_cnt_bypass_en5" value="false" />
+  <generatedFiles>
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_0.qip"
+       type="OTHER"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/srv/CAD/QuartusII/17.1/ip/altera/altera_pll/source/top/pll_hw.tcl" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/guava-15.0.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/javasysmon.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="pll" as="pll_0" />
+  <messages>
+   <message level="Debug" culprit="pll">queue size: 2 starting:altera_pll "submodules/pll_pll_0"</message>
+   <message level="Info" culprit="pll_0"><![CDATA["<b>pll</b>" instantiated <b>altera_pll</b> "<b>pll_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_pll:17.1:c_cnt_bypass_en0=false,c_cnt_bypass_en1=false,c_cnt_bypass_en10=true,c_cnt_bypass_en11=true,c_cnt_bypass_en12=true,c_cnt_bypass_en13=true,c_cnt_bypass_en14=true,c_cnt_bypass_en15=true,c_cnt_bypass_en16=true,c_cnt_bypass_en17=true,c_cnt_bypass_en2=false,c_cnt_bypass_en3=false,c_cnt_bypass_en4=false,c_cnt_bypass_en5=true,c_cnt_bypass_en6=true,c_cnt_bypass_en7=true,c_cnt_bypass_en8=true,c_cnt_bypass_en9=true,c_cnt_hi_div0=7,c_cnt_hi_div1=14,c_cnt_hi_div10=1,c_cnt_hi_div11=1,c_cnt_hi_div12=1,c_cnt_hi_div13=1,c_cnt_hi_div14=1,c_cnt_hi_div15=1,c_cnt_hi_div16=1,c_cnt_hi_div17=1,c_cnt_hi_div2=28,c_cnt_hi_div3=56,c_cnt_hi_div4=112,c_cnt_hi_div5=1,c_cnt_hi_div6=1,c_cnt_hi_div7=1,c_cnt_hi_div8=1,c_cnt_hi_div9=1,c_cnt_in_src0=ph_mux_clk,c_cnt_in_src1=ph_mux_clk,c_cnt_in_src10=ph_mux_clk,c_cnt_in_src11=ph_mux_clk,c_cnt_in_src12=ph_mux_clk,c_cnt_in_src13=ph_mux_clk,c_cnt_in_src14=ph_mux_clk,c_cnt_in_src15=ph_mux_clk,c_cnt_in_src16=ph_mux_clk,c_cnt_in_src17=ph_mux_clk,c_cnt_in_src2=ph_mux_clk,c_cnt_in_src3=ph_mux_clk,c_cnt_in_src4=ph_mux_clk,c_cnt_in_src5=ph_mux_clk,c_cnt_in_src6=ph_mux_clk,c_cnt_in_src7=ph_mux_clk,c_cnt_in_src8=ph_mux_clk,c_cnt_in_src9=ph_mux_clk,c_cnt_lo_div0=7,c_cnt_lo_div1=14,c_cnt_lo_div10=1,c_cnt_lo_div11=1,c_cnt_lo_div12=1,c_cnt_lo_div13=1,c_cnt_lo_div14=1,c_cnt_lo_div15=1,c_cnt_lo_div16=1,c_cnt_lo_div17=1,c_cnt_lo_div2=28,c_cnt_lo_div3=56,c_cnt_lo_div4=112,c_cnt_lo_div5=1,c_cnt_lo_div6=1,c_cnt_lo_div7=1,c_cnt_lo_div8=1,c_cnt_lo_div9=1,c_cnt_odd_div_duty_en0=false,c_cnt_odd_div_duty_en1=false,c_cnt_odd_div_duty_en10=false,c_cnt_odd_div_duty_en11=false,c_cnt_odd_div_duty_en12=false,c_cnt_odd_div_duty_en13=false,c_cnt_odd_div_duty_en14=false,c_cnt_odd_div_duty_en15=false,c_cnt_odd_div_duty_en16=false,c_cnt_odd_div_duty_en17=false,c_cnt_odd_div_duty_en2=false,c_cnt_odd_div_duty_en3=false,c_cnt_odd_div_duty_en4=false,c_cnt_odd_div_duty_en5=false,c_cnt_odd_div_duty_en6=false,c_cnt_odd_div_duty_en7=false,c_cnt_odd_div_duty_en8=false,c_cnt_odd_div_duty_en9=false,c_cnt_ph_mux_prst0=0,c_cnt_ph_mux_prst1=0,c_cnt_ph_mux_prst10=0,c_cnt_ph_mux_prst11=0,c_cnt_ph_mux_prst12=0,c_cnt_ph_mux_prst13=0,c_cnt_ph_mux_prst14=0,c_cnt_ph_mux_prst15=0,c_cnt_ph_mux_prst16=0,c_cnt_ph_mux_prst17=0,c_cnt_ph_mux_prst2=0,c_cnt_ph_mux_prst3=0,c_cnt_ph_mux_prst4=0,c_cnt_ph_mux_prst5=0,c_cnt_ph_mux_prst6=0,c_cnt_ph_mux_prst7=0,c_cnt_ph_mux_prst8=0,c_cnt_ph_mux_prst9=0,c_cnt_prst0=1,c_cnt_prst1=1,c_cnt_prst10=1,c_cnt_prst11=1,c_cnt_prst12=1,c_cnt_prst13=1,c_cnt_prst14=1,c_cnt_prst15=1,c_cnt_prst16=1,c_cnt_prst17=1,c_cnt_prst2=1,c_cnt_prst3=1,c_cnt_prst4=1,c_cnt_prst5=1,c_cnt_prst6=1,c_cnt_prst7=1,c_cnt_prst8=1,c_cnt_prst9=1,debug_print_output=false,debug_use_rbc_taf_method=false,device=5CSEBA6U23I7,device_family=Cyclone V,duty_cycle0=50,duty_cycle1=50,duty_cycle10=50,duty_cycle11=50,duty_cycle12=50,duty_cycle13=50,duty_cycle14=50,duty_cycle15=50,duty_cycle16=50,duty_cycle17=50,duty_cycle2=50,duty_cycle3=50,duty_cycle4=50,duty_cycle5=50,duty_cycle6=50,duty_cycle7=50,duty_cycle8=50,duty_cycle9=50,fractional_vco_multiplier=false,gui_active_clk=false,gui_actual_divide_factor0=406,gui_actual_divide_factor1=812,gui_actual_divide_factor10=1,gui_actual_divide_factor11=1,gui_actual_divide_factor12=1,gui_actual_divide_factor13=1,gui_actual_divide_factor14=1,gui_actual_divide_factor15=1,gui_actual_divide_factor16=1,gui_actual_divide_factor17=1,gui_actual_divide_factor2=1624,gui_actual_divide_factor3=3248,gui_actual_divide_factor4=6496,gui_actual_divide_factor5=1,gui_actual_divide_factor6=1,gui_actual_divide_factor7=1,gui_actual_divide_factor8=1,gui_actual_divide_factor9=1,gui_actual_frac_multiply_factor0=1,gui_actual_frac_multiply_factor1=1,gui_actual_frac_multiply_factor10=1,gui_actual_frac_multiply_factor11=1,gui_actual_frac_multiply_factor12=1,gui_actual_frac_multiply_factor13=1,gui_actual_frac_multiply_factor14=1,gui_actual_frac_multiply_factor15=1,gui_actual_frac_multiply_factor16=1,gui_actual_frac_multiply_factor17=1,gui_actual_frac_multiply_factor2=1,gui_actual_frac_multiply_factor3=1,gui_actual_frac_multiply_factor4=1,gui_actual_frac_multiply_factor5=1,gui_actual_frac_multiply_factor6=1,gui_actual_frac_multiply_factor7=1,gui_actual_frac_multiply_factor8=1,gui_actual_frac_multiply_factor9=1,gui_actual_multiply_factor0=90,gui_actual_multiply_factor1=90,gui_actual_multiply_factor10=1,gui_actual_multiply_factor11=1,gui_actual_multiply_factor12=1,gui_actual_multiply_factor13=1,gui_actual_multiply_factor14=1,gui_actual_multiply_factor15=1,gui_actual_multiply_factor16=1,gui_actual_multiply_factor17=1,gui_actual_multiply_factor2=90,gui_actual_multiply_factor3=90,gui_actual_multiply_factor4=90,gui_actual_multiply_factor5=1,gui_actual_multiply_factor6=1,gui_actual_multiply_factor7=1,gui_actual_multiply_factor8=1,gui_actual_multiply_factor9=1,gui_actual_output_clock_frequency0=0 MHz,gui_actual_output_clock_frequency1=0 MHz,gui_actual_output_clock_frequency10=0 MHz,gui_actual_output_clock_frequency11=0 MHz,gui_actual_output_clock_frequency12=0 MHz,gui_actual_output_clock_frequency13=0 MHz,gui_actual_output_clock_frequency14=0 MHz,gui_actual_output_clock_frequency15=0 MHz,gui_actual_output_clock_frequency16=0 MHz,gui_actual_output_clock_frequency17=0 MHz,gui_actual_output_clock_frequency2=0 MHz,gui_actual_output_clock_frequency3=0 MHz,gui_actual_output_clock_frequency4=0 MHz,gui_actual_output_clock_frequency5=0 MHz,gui_actual_output_clock_frequency6=0 MHz,gui_actual_output_clock_frequency7=0 MHz,gui_actual_output_clock_frequency8=0 MHz,gui_actual_output_clock_frequency9=0 MHz,gui_actual_phase_shift0=0,gui_actual_phase_shift1=0,gui_actual_phase_shift10=0,gui_actual_phase_shift11=0,gui_actual_phase_shift12=0,gui_actual_phase_shift13=0,gui_actual_phase_shift14=0,gui_actual_phase_shift15=0,gui_actual_phase_shift16=0,gui_actual_phase_shift17=0,gui_actual_phase_shift2=0,gui_actual_phase_shift3=0,gui_actual_phase_shift4=0,gui_actual_phase_shift5=0,gui_actual_phase_shift6=0,gui_actual_phase_shift7=0,gui_actual_phase_shift8=0,gui_actual_phase_shift9=0,gui_cascade_counter0=false,gui_cascade_counter1=false,gui_cascade_counter10=false,gui_cascade_counter11=false,gui_cascade_counter12=false,gui_cascade_counter13=false,gui_cascade_counter14=false,gui_cascade_counter15=false,gui_cascade_counter16=false,gui_cascade_counter17=false,gui_cascade_counter2=false,gui_cascade_counter3=false,gui_cascade_counter4=false,gui_cascade_counter5=false,gui_cascade_counter6=false,gui_cascade_counter7=false,gui_cascade_counter8=false,gui_cascade_counter9=false,gui_cascade_outclk_index=0,gui_channel_spacing=0.0,gui_clk_bad=false,gui_device_speed_grade=2,gui_divide_factor_c0=1,gui_divide_factor_c1=1,gui_divide_factor_c10=1,gui_divide_factor_c11=1,gui_divide_factor_c12=1,gui_divide_factor_c13=1,gui_divide_factor_c14=1,gui_divide_factor_c15=1,gui_divide_factor_c16=1,gui_divide_factor_c17=1,gui_divide_factor_c2=1,gui_divide_factor_c3=1,gui_divide_factor_c4=1,gui_divide_factor_c5=1,gui_divide_factor_c6=1,gui_divide_factor_c7=1,gui_divide_factor_c8=1,gui_divide_factor_c9=1,gui_divide_factor_n=1,gui_dps_cntr=C0,gui_dps_dir=Positive,gui_dps_num=1,gui_dsm_out_sel=1st_order,gui_duty_cycle0=50,gui_duty_cycle1=50,gui_duty_cycle10=50,gui_duty_cycle11=50,gui_duty_cycle12=50,gui_duty_cycle13=50,gui_duty_cycle14=50,gui_duty_cycle15=50,gui_duty_cycle16=50,gui_duty_cycle17=50,gui_duty_cycle2=50,gui_duty_cycle3=50,gui_duty_cycle4=50,gui_duty_cycle5=50,gui_duty_cycle6=50,gui_duty_cycle7=50,gui_duty_cycle8=50,gui_duty_cycle9=50,gui_en_adv_params=false,gui_en_dps_ports=false,gui_en_phout_ports=false,gui_en_reconf=false,gui_enable_cascade_in=false,gui_enable_cascade_out=false,gui_enable_mif_dps=false,gui_feedback_clock=Global Clock,gui_frac_multiply_factor=1,gui_fractional_cout=32,gui_mif_generate=false,gui_multiply_factor=1,gui_number_of_clocks=5,gui_operation_mode=normal,gui_output_clock_frequency0=56.75,gui_output_clock_frequency1=28.375,gui_output_clock_frequency10=100.0,gui_output_clock_frequency11=100.0,gui_output_clock_frequency12=100.0,gui_output_clock_frequency13=100.0,gui_output_clock_frequency14=100.0,gui_output_clock_frequency15=100.0,gui_output_clock_frequency16=100.0,gui_output_clock_frequency17=100.0,gui_output_clock_frequency2=14.1875,gui_output_clock_frequency3=7.09375,gui_output_clock_frequency4=3.546875,gui_output_clock_frequency5=7.09375,gui_output_clock_frequency6=3.546875,gui_output_clock_frequency7=3.546875,gui_output_clock_frequency8=3.546875,gui_output_clock_frequency9=100.0,gui_parameter_list=M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset,gui_parameter_values=45,45,15,14,false,false,false,true,7,7,1,0,ph_mux_clk,false,false,14,14,1,0,ph_mux_clk,false,false,28,28,1,0,ph_mux_clk,false,false,56,56,1,0,ph_mux_clk,false,false,112,112,1,0,ph_mux_clk,false,false,1,20,10000,794.482758 MHz,1,gclk,glb,fb_1,ph_mux_clk,true,gui_phase_shift0=0,gui_phase_shift1=0,gui_phase_shift10=0,gui_phase_shift11=0,gui_phase_shift12=0,gui_phase_shift13=0,gui_phase_shift14=0,gui_phase_shift15=0,gui_phase_shift16=0,gui_phase_shift17=0,gui_phase_shift2=0,gui_phase_shift3=0,gui_phase_shift4=0,gui_phase_shift5=0,gui_phase_shift6=0,gui_phase_shift7=0,gui_phase_shift8=0,gui_phase_shift9=0,gui_phase_shift_deg0=0.0,gui_phase_shift_deg1=0.0,gui_phase_shift_deg10=0.0,gui_phase_shift_deg11=0.0,gui_phase_shift_deg12=0.0,gui_phase_shift_deg13=0.0,gui_phase_shift_deg14=0.0,gui_phase_shift_deg15=0.0,gui_phase_shift_deg16=0.0,gui_phase_shift_deg17=0.0,gui_phase_shift_deg2=0.0,gui_phase_shift_deg3=0.0,gui_phase_shift_deg4=0.0,gui_phase_shift_deg5=0.0,gui_phase_shift_deg6=0.0,gui_phase_shift_deg7=0.0,gui_phase_shift_deg8=0.0,gui_phase_shift_deg9=0.0,gui_phout_division=1,gui_pll_auto_reset=On,gui_pll_bandwidth_preset=Auto,gui_pll_cascading_mode=Create an adjpllin signal to connect with an upstream PLL,gui_pll_mode=Integer-N PLL,gui_ps_units0=ps,gui_ps_units1=ps,gui_ps_units10=ps,gui_ps_units11=ps,gui_ps_units12=ps,gui_ps_units13=ps,gui_ps_units14=ps,gui_ps_units15=ps,gui_ps_units16=ps,gui_ps_units17=ps,gui_ps_units2=ps,gui_ps_units3=ps,gui_ps_units4=ps,gui_ps_units5=ps,gui_ps_units6=ps,gui_ps_units7=ps,gui_ps_units8=ps,gui_ps_units9=ps,gui_refclk1_frequency=100.0,gui_refclk_switch=false,gui_reference_clock_frequency=256.0,gui_switchover_delay=0,gui_switchover_mode=Automatic Switchover,gui_use_locked=false,m_cnt_bypass_en=false,m_cnt_hi_div=45,m_cnt_lo_div=45,m_cnt_odd_div_duty_en=false,mimic_fbclk_type=gclk,n_cnt_bypass_en=false,n_cnt_hi_div=15,n_cnt_lo_div=14,n_cnt_odd_div_duty_en=true,number_of_cascade_counters=0,number_of_clocks=5,operation_mode=normal,output_clock_frequency0=56.748768 MHz,output_clock_frequency1=28.374384 MHz,output_clock_frequency10=0 MHz,output_clock_frequency11=0 MHz,output_clock_frequency12=0 MHz,output_clock_frequency13=0 MHz,output_clock_frequency14=0 MHz,output_clock_frequency15=0 MHz,output_clock_frequency16=0 MHz,output_clock_frequency17=0 MHz,output_clock_frequency2=14.187192 MHz,output_clock_frequency3=7.093596 MHz,output_clock_frequency4=3.546798 MHz,output_clock_frequency5=0 MHz,output_clock_frequency6=0 MHz,output_clock_frequency7=0 MHz,output_clock_frequency8=0 MHz,output_clock_frequency9=0 MHz,phase_shift0=0 ps,phase_shift1=0 ps,phase_shift10=0 ps,phase_shift11=0 ps,phase_shift12=0 ps,phase_shift13=0 ps,phase_shift14=0 ps,phase_shift15=0 ps,phase_shift16=0 ps,phase_shift17=0 ps,phase_shift2=0 ps,phase_shift3=0 ps,phase_shift4=0 ps,phase_shift5=0 ps,phase_shift6=0 ps,phase_shift7=0 ps,phase_shift8=0 ps,phase_shift9=0 ps,pll_auto_clk_sw_en=false,pll_bwctrl=10000,pll_clk_loss_sw_en=false,pll_clk_sw_dly=0,pll_clkin_0_src=clk_0,pll_clkin_1_src=clk_0,pll_cp_current=20,pll_dsm_out_sel=1st_order,pll_fbclk_mux_1=glb,pll_fbclk_mux_2=fb_1,pll_fractional_cout=32,pll_fractional_division=1,pll_m_cnt_in_src=ph_mux_clk,pll_manu_clk_sw_en=false,pll_output_clk_frequency=794.482758 MHz,pll_slf_rst=true,pll_subtype=General,pll_type=General,pll_vco_div=1,pll_vcoph_div=1,refclk1_frequency=100.0 MHz,reference_clock_frequency=256.0 MHz"
+   instancePathKey="pll:.:pll_1"
+   kind="altera_pll"
+   version="17.1"
+   name="pll_pll_1">
+  <parameter name="c_cnt_bypass_en17" value="true" />
+  <parameter name="c_cnt_bypass_en14" value="true" />
+  <parameter name="c_cnt_bypass_en13" value="true" />
+  <parameter name="c_cnt_bypass_en16" value="true" />
+  <parameter name="c_cnt_bypass_en15" value="true" />
+  <parameter name="c_cnt_bypass_en10" value="true" />
+  <parameter name="c_cnt_bypass_en12" value="true" />
+  <parameter
+     name="gui_pll_cascading_mode"
+     value="Create an adjpllin signal to connect with an upstream PLL" />
+  <parameter name="c_cnt_bypass_en11" value="true" />
+  <parameter name="pll_fbclk_mux_2" value="fb_1" />
+  <parameter name="pll_fbclk_mux_1" value="glb" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="c_cnt_prst6" value="1" />
+  <parameter name="c_cnt_prst5" value="1" />
+  <parameter name="c_cnt_prst8" value="1" />
+  <parameter name="c_cnt_prst7" value="1" />
+  <parameter name="c_cnt_prst9" value="1" />
+  <parameter name="c_cnt_in_src9" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src8" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src5" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="c_cnt_in_src4" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src7" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src6" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="c_cnt_in_src1" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="c_cnt_in_src0" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="c_cnt_in_src3" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="c_cnt_in_src2" value="ph_mux_clk" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="duty_cycle12" value="50" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="duty_cycle13" value="50" />
+  <parameter name="duty_cycle10" value="50" />
+  <parameter name="duty_cycle11" value="50" />
+  <parameter name="duty_cycle16" value="50" />
+  <parameter name="duty_cycle17" value="50" />
+  <parameter name="duty_cycle14" value="50" />
+  <parameter name="duty_cycle15" value="50" />
+  <parameter name="pll_vcoph_div" value="1" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="pll_fractional_cout" value="32" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="pll_manu_clk_sw_en" value="false" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="c_cnt_prst0" value="1" />
+  <parameter name="c_cnt_prst2" value="1" />
+  <parameter name="c_cnt_prst1" value="1" />
+  <parameter name="gui_actual_divide_factor8" value="1" />
+  <parameter name="c_cnt_prst4" value="1" />
+  <parameter name="gui_actual_divide_factor9" value="1" />
+  <parameter name="c_cnt_prst3" value="1" />
+  <parameter name="gui_pll_auto_reset" value="On" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="phase_shift12" value="0 ps" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="phase_shift11" value="0 ps" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="phase_shift10" value="0 ps" />
+  <parameter name="n_cnt_lo_div" value="14" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_operation_mode" value="normal" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_actual_divide_factor6" value="1" />
+  <parameter name="gui_actual_divide_factor7" value="1" />
+  <parameter name="gui_actual_divide_factor4" value="6496" />
+  <parameter name="gui_actual_divide_factor5" value="1" />
+  <parameter name="gui_actual_divide_factor2" value="1624" />
+  <parameter name="gui_actual_divide_factor3" value="3248" />
+  <parameter name="gui_actual_divide_factor0" value="406" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_actual_divide_factor1" value="812" />
+  <parameter name="gui_actual_frac_multiply_factor8" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor9" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor6" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor7" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="phase_shift17" value="0 ps" />
+  <parameter name="pll_clk_sw_dly" value="0" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="phase_shift16" value="0 ps" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="phase_shift15" value="0 ps" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="phase_shift14" value="0 ps" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="phase_shift13" value="0 ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_actual_frac_multiply_factor4" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor5" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor2" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor3" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor0" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor1" value="1" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="pll_slf_rst" value="true" />
+  <parameter name="duty_cycle9" value="50" />
+  <parameter name="duty_cycle7" value="50" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="duty_cycle8" value="50" />
+  <parameter name="duty_cycle5" value="50" />
+  <parameter name="duty_cycle6" value="50" />
+  <parameter name="duty_cycle3" value="50" />
+  <parameter name="duty_cycle4" value="50" />
+  <parameter name="duty_cycle1" value="50" />
+  <parameter name="duty_cycle2" value="50" />
+  <parameter name="duty_cycle0" value="50" />
+  <parameter name="m_cnt_lo_div" value="45" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="pll_clk_loss_sw_en" value="false" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_use_locked" value="false" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="pll_type" value="General" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="pll_output_clk_frequency" value="794.482758 MHz" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="c_cnt_lo_div14" value="1" />
+  <parameter name="c_cnt_lo_div15" value="1" />
+  <parameter name="c_cnt_lo_div12" value="1" />
+  <parameter name="c_cnt_lo_div13" value="1" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="c_cnt_lo_div16" value="1" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="c_cnt_lo_div17" value="1" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="c_cnt_lo_div10" value="1" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="c_cnt_lo_div11" value="1" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="pll_fractional_division" value="1" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="fractional_vco_multiplier" value="false" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="m_cnt_bypass_en" value="false" />
+  <parameter name="gui_number_of_clocks" value="5" />
+  <parameter name="c_cnt_hi_div10" value="1" />
+  <parameter name="c_cnt_hi_div11" value="1" />
+  <parameter name="c_cnt_hi_div12" value="1" />
+  <parameter name="c_cnt_hi_div13" value="1" />
+  <parameter name="c_cnt_hi_div14" value="1" />
+  <parameter name="c_cnt_hi_div15" value="1" />
+  <parameter name="c_cnt_hi_div16" value="1" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="c_cnt_hi_div17" value="1" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_output_clock_frequency0" value="56.75" />
+  <parameter name="output_clock_frequency10" value="0 MHz" />
+  <parameter name="output_clock_frequency11" value="0 MHz" />
+  <parameter name="output_clock_frequency12" value="0 MHz" />
+  <parameter name="pll_bwctrl" value="10000" />
+  <parameter name="output_clock_frequency13" value="0 MHz" />
+  <parameter name="mimic_fbclk_type" value="gclk" />
+  <parameter name="pll_clkin_0_src" value="clk_0" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="output_clock_frequency14" value="0 MHz" />
+  <parameter name="output_clock_frequency15" value="0 MHz" />
+  <parameter name="output_clock_frequency16" value="0 MHz" />
+  <parameter name="output_clock_frequency17" value="0 MHz" />
+  <parameter name="n_cnt_bypass_en" value="false" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="m_cnt_odd_div_duty_en" value="false" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="3.546875" />
+  <parameter name="gui_output_clock_frequency8" value="3.546875" />
+  <parameter name="gui_output_clock_frequency5" value="7.09375" />
+  <parameter name="gui_output_clock_frequency6" value="3.546875" />
+  <parameter name="gui_output_clock_frequency3" value="7.09375" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_output_clock_frequency4" value="3.546875" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_output_clock_frequency1" value="28.375" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_output_clock_frequency2" value="14.1875" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_actual_divide_factor10" value="1" />
+  <parameter name="gui_actual_divide_factor16" value="1" />
+  <parameter name="device_family" value="Cyclone V" />
+  <parameter name="gui_actual_divide_factor15" value="1" />
+  <parameter name="gui_actual_divide_factor17" value="1" />
+  <parameter name="gui_actual_divide_factor12" value="1" />
+  <parameter name="gui_actual_divide_factor11" value="1" />
+  <parameter name="gui_actual_divide_factor14" value="1" />
+  <parameter name="gui_actual_divide_factor13" value="1" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_actual_multiply_factor9" value="1" />
+  <parameter name="gui_actual_multiply_factor6" value="1" />
+  <parameter name="gui_actual_multiply_factor5" value="1" />
+  <parameter name="gui_actual_multiply_factor8" value="1" />
+  <parameter name="gui_actual_multiply_factor7" value="1" />
+  <parameter name="gui_actual_multiply_factor2" value="90" />
+  <parameter name="gui_actual_multiply_factor1" value="90" />
+  <parameter name="gui_actual_multiply_factor4" value="90" />
+  <parameter name="gui_actual_multiply_factor3" value="90" />
+  <parameter name="refclk1_frequency" value="100.0 MHz" />
+  <parameter name="gui_actual_multiply_factor0" value="90" />
+  <parameter name="reference_clock_frequency" value="256.0 MHz" />
+  <parameter name="pll_m_cnt_in_src" value="ph_mux_clk" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="c_cnt_hi_div0" value="7" />
+  <parameter name="c_cnt_hi_div1" value="14" />
+  <parameter name="c_cnt_hi_div2" value="28" />
+  <parameter name="c_cnt_hi_div3" value="56" />
+  <parameter name="c_cnt_hi_div4" value="112" />
+  <parameter name="m_cnt_hi_div" value="45" />
+  <parameter name="c_cnt_hi_div5" value="1" />
+  <parameter name="c_cnt_hi_div6" value="1" />
+  <parameter name="c_cnt_hi_div7" value="1" />
+  <parameter name="n_cnt_odd_div_duty_en" value="true" />
+  <parameter name="c_cnt_hi_div8" value="1" />
+  <parameter name="c_cnt_hi_div9" value="1" />
+  <parameter name="c_cnt_ph_mux_prst8" value="0" />
+  <parameter name="c_cnt_ph_mux_prst7" value="0" />
+  <parameter name="c_cnt_ph_mux_prst9" value="0" />
+  <parameter name="c_cnt_ph_mux_prst0" value="0" />
+  <parameter name="c_cnt_ph_mux_prst2" value="0" />
+  <parameter name="c_cnt_ph_mux_prst1" value="0" />
+  <parameter name="c_cnt_ph_mux_prst4" value="0" />
+  <parameter name="c_cnt_ph_mux_prst3" value="0" />
+  <parameter name="c_cnt_ph_mux_prst6" value="0" />
+  <parameter name="c_cnt_ph_mux_prst5" value="0" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_switchover_mode" value="Automatic Switchover" />
+  <parameter
+     name="gui_parameter_values"
+     value="45,45,15,14,false,false,false,true,7,7,1,0,ph_mux_clk,false,false,14,14,1,0,ph_mux_clk,false,false,28,28,1,0,ph_mux_clk,false,false,56,56,1,0,ph_mux_clk,false,false,112,112,1,0,ph_mux_clk,false,false,1,20,10000,794.482758 MHz,1,gclk,glb,fb_1,ph_mux_clk,true" />
+  <parameter name="pll_auto_clk_sw_en" value="false" />
+  <parameter name="pll_subtype" value="General" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_actual_multiply_factor10" value="1" />
+  <parameter name="gui_actual_multiply_factor11" value="1" />
+  <parameter name="c_cnt_in_src17" value="ph_mux_clk" />
+  <parameter name="gui_actual_multiply_factor12" value="1" />
+  <parameter name="c_cnt_in_src16" value="ph_mux_clk" />
+  <parameter name="gui_actual_multiply_factor13" value="1" />
+  <parameter name="c_cnt_in_src15" value="ph_mux_clk" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="c_cnt_odd_div_duty_en0" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en1" value="false" />
+  <parameter name="c_cnt_in_src14" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src13" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src12" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src11" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src10" value="ph_mux_clk" />
+  <parameter name="pll_vco_div" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en2" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en3" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en4" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en5" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en6" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en7" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en8" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en9" value="false" />
+  <parameter name="c_cnt_prst13" value="1" />
+  <parameter name="c_cnt_prst12" value="1" />
+  <parameter name="c_cnt_prst11" value="1" />
+  <parameter name="c_cnt_prst10" value="1" />
+  <parameter name="c_cnt_prst17" value="1" />
+  <parameter name="c_cnt_prst16" value="1" />
+  <parameter name="pll_dsm_out_sel" value="1st_order" />
+  <parameter name="c_cnt_prst15" value="1" />
+  <parameter name="c_cnt_prst14" value="1" />
+  <parameter name="c_cnt_lo_div9" value="1" />
+  <parameter name="c_cnt_lo_div7" value="1" />
+  <parameter name="c_cnt_lo_div8" value="1" />
+  <parameter name="number_of_cascade_counters" value="0" />
+  <parameter name="c_cnt_lo_div5" value="1" />
+  <parameter name="c_cnt_lo_div6" value="1" />
+  <parameter name="c_cnt_lo_div3" value="56" />
+  <parameter name="c_cnt_lo_div4" value="112" />
+  <parameter name="c_cnt_lo_div1" value="14" />
+  <parameter name="c_cnt_lo_div2" value="28" />
+  <parameter name="c_cnt_lo_div0" value="7" />
+  <parameter name="gui_actual_frac_multiply_factor12" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor11" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor10" value="1" />
+  <parameter name="pll_cp_current" value="20" />
+  <parameter name="gui_actual_frac_multiply_factor16" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor15" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor14" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor13" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor17" value="1" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="pll_clkin_1_src" value="clk_0" />
+  <parameter name="phase_shift1" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst17" value="0" />
+  <parameter name="phase_shift0" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst16" value="0" />
+  <parameter name="phase_shift3" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst15" value="0" />
+  <parameter name="phase_shift2" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst14" value="0" />
+  <parameter name="phase_shift5" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst13" value="0" />
+  <parameter name="phase_shift4" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst12" value="0" />
+  <parameter name="phase_shift7" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst11" value="0" />
+  <parameter name="phase_shift6" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst10" value="0" />
+  <parameter name="phase_shift9" value="0 ps" />
+  <parameter name="phase_shift8" value="0 ps" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="number_of_clocks" value="5" />
+  <parameter name="n_cnt_hi_div" value="15" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="output_clock_frequency6" value="0 MHz" />
+  <parameter name="output_clock_frequency9" value="0 MHz" />
+  <parameter
+     name="gui_parameter_list"
+     value="M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en17" value="false" />
+  <parameter name="operation_mode" value="normal" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_actual_multiply_factor14" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en16" value="false" />
+  <parameter name="gui_actual_multiply_factor15" value="1" />
+  <parameter name="output_clock_frequency0" value="56.748768 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en15" value="false" />
+  <parameter name="gui_actual_multiply_factor16" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en14" value="false" />
+  <parameter name="gui_actual_multiply_factor17" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en13" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="output_clock_frequency3" value="7.093596 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en12" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="output_clock_frequency4" value="3.546798 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en11" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="output_clock_frequency1" value="28.374384 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en10" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="output_clock_frequency2" value="14.187192 MHz" />
+  <parameter name="c_cnt_bypass_en6" value="true" />
+  <parameter name="c_cnt_bypass_en7" value="true" />
+  <parameter name="c_cnt_bypass_en8" value="true" />
+  <parameter name="c_cnt_bypass_en9" value="true" />
+  <parameter name="c_cnt_bypass_en0" value="false" />
+  <parameter name="c_cnt_bypass_en1" value="false" />
+  <parameter name="c_cnt_bypass_en2" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="256.0" />
+  <parameter name="c_cnt_bypass_en3" value="false" />
+  <parameter name="c_cnt_bypass_en4" value="false" />
+  <parameter name="c_cnt_bypass_en5" value="true" />
+  <generatedFiles>
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_1.qip"
+       type="OTHER"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/srv/CAD/QuartusII/17.1/ip/altera/altera_pll/source/top/pll_hw.tcl" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/guava-15.0.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/javasysmon.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="pll" as="pll_1" />
+  <messages>
+   <message level="Debug" culprit="pll">queue size: 1 starting:altera_pll "submodules/pll_pll_1"</message>
+   <message level="Info" culprit="pll_1"><![CDATA["<b>pll</b>" instantiated <b>altera_pll</b> "<b>pll_1</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_pll:17.1:c_cnt_bypass_en0=false,c_cnt_bypass_en1=false,c_cnt_bypass_en10=true,c_cnt_bypass_en11=true,c_cnt_bypass_en12=true,c_cnt_bypass_en13=true,c_cnt_bypass_en14=true,c_cnt_bypass_en15=true,c_cnt_bypass_en16=true,c_cnt_bypass_en17=true,c_cnt_bypass_en2=false,c_cnt_bypass_en3=false,c_cnt_bypass_en4=true,c_cnt_bypass_en5=true,c_cnt_bypass_en6=true,c_cnt_bypass_en7=true,c_cnt_bypass_en8=true,c_cnt_bypass_en9=true,c_cnt_hi_div0=26,c_cnt_hi_div1=32,c_cnt_hi_div10=1,c_cnt_hi_div11=1,c_cnt_hi_div12=1,c_cnt_hi_div13=1,c_cnt_hi_div14=1,c_cnt_hi_div15=1,c_cnt_hi_div16=1,c_cnt_hi_div17=1,c_cnt_hi_div2=45,c_cnt_hi_div3=90,c_cnt_hi_div4=1,c_cnt_hi_div5=1,c_cnt_hi_div6=1,c_cnt_hi_div7=1,c_cnt_hi_div8=1,c_cnt_hi_div9=1,c_cnt_in_src0=ph_mux_clk,c_cnt_in_src1=ph_mux_clk,c_cnt_in_src10=ph_mux_clk,c_cnt_in_src11=ph_mux_clk,c_cnt_in_src12=ph_mux_clk,c_cnt_in_src13=ph_mux_clk,c_cnt_in_src14=ph_mux_clk,c_cnt_in_src15=ph_mux_clk,c_cnt_in_src16=ph_mux_clk,c_cnt_in_src17=ph_mux_clk,c_cnt_in_src2=ph_mux_clk,c_cnt_in_src3=ph_mux_clk,c_cnt_in_src4=ph_mux_clk,c_cnt_in_src5=ph_mux_clk,c_cnt_in_src6=ph_mux_clk,c_cnt_in_src7=ph_mux_clk,c_cnt_in_src8=ph_mux_clk,c_cnt_in_src9=ph_mux_clk,c_cnt_lo_div0=25,c_cnt_lo_div1=31,c_cnt_lo_div10=1,c_cnt_lo_div11=1,c_cnt_lo_div12=1,c_cnt_lo_div13=1,c_cnt_lo_div14=1,c_cnt_lo_div15=1,c_cnt_lo_div16=1,c_cnt_lo_div17=1,c_cnt_lo_div2=44,c_cnt_lo_div3=89,c_cnt_lo_div4=1,c_cnt_lo_div5=1,c_cnt_lo_div6=1,c_cnt_lo_div7=1,c_cnt_lo_div8=1,c_cnt_lo_div9=1,c_cnt_odd_div_duty_en0=true,c_cnt_odd_div_duty_en1=true,c_cnt_odd_div_duty_en10=false,c_cnt_odd_div_duty_en11=false,c_cnt_odd_div_duty_en12=false,c_cnt_odd_div_duty_en13=false,c_cnt_odd_div_duty_en14=false,c_cnt_odd_div_duty_en15=false,c_cnt_odd_div_duty_en16=false,c_cnt_odd_div_duty_en17=false,c_cnt_odd_div_duty_en2=true,c_cnt_odd_div_duty_en3=true,c_cnt_odd_div_duty_en4=false,c_cnt_odd_div_duty_en5=false,c_cnt_odd_div_duty_en6=false,c_cnt_odd_div_duty_en7=false,c_cnt_odd_div_duty_en8=false,c_cnt_odd_div_duty_en9=false,c_cnt_ph_mux_prst0=0,c_cnt_ph_mux_prst1=0,c_cnt_ph_mux_prst10=0,c_cnt_ph_mux_prst11=0,c_cnt_ph_mux_prst12=0,c_cnt_ph_mux_prst13=0,c_cnt_ph_mux_prst14=0,c_cnt_ph_mux_prst15=0,c_cnt_ph_mux_prst16=0,c_cnt_ph_mux_prst17=0,c_cnt_ph_mux_prst2=0,c_cnt_ph_mux_prst3=0,c_cnt_ph_mux_prst4=0,c_cnt_ph_mux_prst5=0,c_cnt_ph_mux_prst6=0,c_cnt_ph_mux_prst7=0,c_cnt_ph_mux_prst8=0,c_cnt_ph_mux_prst9=0,c_cnt_prst0=1,c_cnt_prst1=1,c_cnt_prst10=1,c_cnt_prst11=1,c_cnt_prst12=1,c_cnt_prst13=1,c_cnt_prst14=1,c_cnt_prst15=1,c_cnt_prst16=1,c_cnt_prst17=1,c_cnt_prst2=1,c_cnt_prst3=1,c_cnt_prst4=1,c_cnt_prst5=1,c_cnt_prst6=1,c_cnt_prst7=1,c_cnt_prst8=1,c_cnt_prst9=1,debug_print_output=false,debug_use_rbc_taf_method=false,device=5CSEBA6U23I7,device_family=Cyclone V,duty_cycle0=50,duty_cycle1=50,duty_cycle10=50,duty_cycle11=50,duty_cycle12=50,duty_cycle13=50,duty_cycle14=50,duty_cycle15=50,duty_cycle16=50,duty_cycle17=50,duty_cycle2=50,duty_cycle3=50,duty_cycle4=50,duty_cycle5=50,duty_cycle6=50,duty_cycle7=50,duty_cycle8=50,duty_cycle9=50,fractional_vco_multiplier=true,gui_active_clk=false,gui_actual_divide_factor0=102,gui_actual_divide_factor1=126,gui_actual_divide_factor10=1,gui_actual_divide_factor11=1,gui_actual_divide_factor12=1,gui_actual_divide_factor13=1,gui_actual_divide_factor14=1,gui_actual_divide_factor15=1,gui_actual_divide_factor16=1,gui_actual_divide_factor17=1,gui_actual_divide_factor2=178,gui_actual_divide_factor3=358,gui_actual_divide_factor4=1,gui_actual_divide_factor5=1,gui_actual_divide_factor6=1,gui_actual_divide_factor7=1,gui_actual_divide_factor8=1,gui_actual_divide_factor9=1,gui_actual_frac_multiply_factor0=1681070366,gui_actual_frac_multiply_factor1=1681070366,gui_actual_frac_multiply_factor10=1,gui_actual_frac_multiply_factor11=1,gui_actual_frac_multiply_factor12=1,gui_actual_frac_multiply_factor13=1,gui_actual_frac_multiply_factor14=1,gui_actual_frac_multiply_factor15=1,gui_actual_frac_multiply_factor16=1,gui_actual_frac_multiply_factor17=1,gui_actual_frac_multiply_factor2=1681070366,gui_actual_frac_multiply_factor3=1681070366,gui_actual_frac_multiply_factor4=1,gui_actual_frac_multiply_factor5=1,gui_actual_frac_multiply_factor6=1,gui_actual_frac_multiply_factor7=1,gui_actual_frac_multiply_factor8=1,gui_actual_frac_multiply_factor9=1,gui_actual_multiply_factor0=12,gui_actual_multiply_factor1=12,gui_actual_multiply_factor10=1,gui_actual_multiply_factor11=1,gui_actual_multiply_factor12=1,gui_actual_multiply_factor13=1,gui_actual_multiply_factor14=1,gui_actual_multiply_factor15=1,gui_actual_multiply_factor16=1,gui_actual_multiply_factor17=1,gui_actual_multiply_factor2=12,gui_actual_multiply_factor3=12,gui_actual_multiply_factor4=1,gui_actual_multiply_factor5=1,gui_actual_multiply_factor6=1,gui_actual_multiply_factor7=1,gui_actual_multiply_factor8=1,gui_actual_multiply_factor9=1,gui_actual_output_clock_frequency0=36.000000 MHz,gui_actual_output_clock_frequency1=31.500000 MHz,gui_actual_output_clock_frequency10=0 MHz,gui_actual_output_clock_frequency11=0 MHz,gui_actual_output_clock_frequency12=0 MHz,gui_actual_output_clock_frequency13=0 MHz,gui_actual_output_clock_frequency14=0 MHz,gui_actual_output_clock_frequency15=0 MHz,gui_actual_output_clock_frequency16=0 MHz,gui_actual_output_clock_frequency17=0 MHz,gui_actual_output_clock_frequency2=25.568627 MHz,gui_actual_output_clock_frequency3=0 MHz,gui_actual_output_clock_frequency4=0 MHz,gui_actual_output_clock_frequency5=0 MHz,gui_actual_output_clock_frequency6=0 MHz,gui_actual_output_clock_frequency7=0 MHz,gui_actual_output_clock_frequency8=0 MHz,gui_actual_output_clock_frequency9=0 MHz,gui_actual_phase_shift0=0,gui_actual_phase_shift1=0,gui_actual_phase_shift10=0,gui_actual_phase_shift11=0,gui_actual_phase_shift12=0,gui_actual_phase_shift13=0,gui_actual_phase_shift14=0,gui_actual_phase_shift15=0,gui_actual_phase_shift16=0,gui_actual_phase_shift17=0,gui_actual_phase_shift2=0,gui_actual_phase_shift3=0,gui_actual_phase_shift4=0,gui_actual_phase_shift5=0,gui_actual_phase_shift6=0,gui_actual_phase_shift7=0,gui_actual_phase_shift8=0,gui_actual_phase_shift9=0,gui_cascade_counter0=false,gui_cascade_counter1=false,gui_cascade_counter10=false,gui_cascade_counter11=false,gui_cascade_counter12=false,gui_cascade_counter13=false,gui_cascade_counter14=false,gui_cascade_counter15=false,gui_cascade_counter16=false,gui_cascade_counter17=false,gui_cascade_counter2=false,gui_cascade_counter3=false,gui_cascade_counter4=false,gui_cascade_counter5=false,gui_cascade_counter6=false,gui_cascade_counter7=false,gui_cascade_counter8=false,gui_cascade_counter9=false,gui_cascade_outclk_index=0,gui_channel_spacing=0.0,gui_clk_bad=false,gui_device_speed_grade=1,gui_divide_factor_c0=1,gui_divide_factor_c1=1,gui_divide_factor_c10=1,gui_divide_factor_c11=1,gui_divide_factor_c12=1,gui_divide_factor_c13=1,gui_divide_factor_c14=1,gui_divide_factor_c15=1,gui_divide_factor_c16=1,gui_divide_factor_c17=1,gui_divide_factor_c2=1,gui_divide_factor_c3=1,gui_divide_factor_c4=1,gui_divide_factor_c5=1,gui_divide_factor_c6=1,gui_divide_factor_c7=1,gui_divide_factor_c8=1,gui_divide_factor_c9=1,gui_divide_factor_n=1,gui_dps_cntr=C0,gui_dps_dir=Positive,gui_dps_num=1,gui_dsm_out_sel=1st_order,gui_duty_cycle0=50,gui_duty_cycle1=50,gui_duty_cycle10=50,gui_duty_cycle11=50,gui_duty_cycle12=50,gui_duty_cycle13=50,gui_duty_cycle14=50,gui_duty_cycle15=50,gui_duty_cycle16=50,gui_duty_cycle17=50,gui_duty_cycle2=50,gui_duty_cycle3=50,gui_duty_cycle4=50,gui_duty_cycle5=50,gui_duty_cycle6=50,gui_duty_cycle7=50,gui_duty_cycle8=50,gui_duty_cycle9=50,gui_en_adv_params=false,gui_en_dps_ports=false,gui_en_phout_ports=false,gui_en_reconf=false,gui_enable_cascade_in=false,gui_enable_cascade_out=false,gui_enable_mif_dps=false,gui_feedback_clock=Global Clock,gui_frac_multiply_factor=1,gui_fractional_cout=32,gui_mif_generate=false,gui_multiply_factor=1,gui_number_of_clocks=4,gui_operation_mode=normal,gui_output_clock_frequency0=31.1,gui_output_clock_frequency1=25.175,gui_output_clock_frequency10=100.0,gui_output_clock_frequency11=100.0,gui_output_clock_frequency12=100.0,gui_output_clock_frequency13=100.0,gui_output_clock_frequency14=100.0,gui_output_clock_frequency15=100.0,gui_output_clock_frequency16=100.0,gui_output_clock_frequency17=100.0,gui_output_clock_frequency2=17.734475,gui_output_clock_frequency3=8.867237,gui_output_clock_frequency4=8.867237,gui_output_clock_frequency5=100.0,gui_output_clock_frequency6=100.0,gui_output_clock_frequency7=100.0,gui_output_clock_frequency8=100.0,gui_output_clock_frequency9=100.0,gui_parameter_list=M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset,gui_parameter_values=6,6,1,1,false,false,false,false,26,25,1,0,ph_mux_clk,false,true,32,31,1,0,ph_mux_clk,false,true,45,44,1,0,ph_mux_clk,false,true,90,89,1,0,ph_mux_clk,false,true,1,30,2000,1586.099801 MHz,1681070366,gclk,glb,fb_1,ph_mux_clk,true,gui_phase_shift0=0,gui_phase_shift1=0,gui_phase_shift10=0,gui_phase_shift11=0,gui_phase_shift12=0,gui_phase_shift13=0,gui_phase_shift14=0,gui_phase_shift15=0,gui_phase_shift16=0,gui_phase_shift17=0,gui_phase_shift2=0,gui_phase_shift3=0,gui_phase_shift4=0,gui_phase_shift5=0,gui_phase_shift6=0,gui_phase_shift7=0,gui_phase_shift8=0,gui_phase_shift9=0,gui_phase_shift_deg0=0.0,gui_phase_shift_deg1=0.0,gui_phase_shift_deg10=0.0,gui_phase_shift_deg11=0.0,gui_phase_shift_deg12=0.0,gui_phase_shift_deg13=0.0,gui_phase_shift_deg14=0.0,gui_phase_shift_deg15=0.0,gui_phase_shift_deg16=0.0,gui_phase_shift_deg17=0.0,gui_phase_shift_deg2=0.0,gui_phase_shift_deg3=0.0,gui_phase_shift_deg4=0.0,gui_phase_shift_deg5=0.0,gui_phase_shift_deg6=0.0,gui_phase_shift_deg7=0.0,gui_phase_shift_deg8=0.0,gui_phase_shift_deg9=0.0,gui_phout_division=1,gui_pll_auto_reset=On,gui_pll_bandwidth_preset=Auto,gui_pll_cascading_mode=Create an adjpllin signal to connect with an upstream PLL,gui_pll_mode=Fractional-N PLL,gui_ps_units0=ps,gui_ps_units1=ps,gui_ps_units10=ps,gui_ps_units11=ps,gui_ps_units12=ps,gui_ps_units13=ps,gui_ps_units14=ps,gui_ps_units15=ps,gui_ps_units16=ps,gui_ps_units17=ps,gui_ps_units2=degrees,gui_ps_units3=ps,gui_ps_units4=ps,gui_ps_units5=ps,gui_ps_units6=ps,gui_ps_units7=ps,gui_ps_units8=ps,gui_ps_units9=ps,gui_refclk1_frequency=100.0,gui_refclk_switch=false,gui_reference_clock_frequency=256.0,gui_switchover_delay=0,gui_switchover_mode=Automatic Switchover,gui_use_locked=false,m_cnt_bypass_en=false,m_cnt_hi_div=6,m_cnt_lo_div=6,m_cnt_odd_div_duty_en=false,mimic_fbclk_type=gclk,n_cnt_bypass_en=false,n_cnt_hi_div=1,n_cnt_lo_div=1,n_cnt_odd_div_duty_en=false,number_of_cascade_counters=0,number_of_clocks=4,operation_mode=normal,output_clock_frequency0=31.099998 MHz,output_clock_frequency1=25.176188 MHz,output_clock_frequency10=0 MHz,output_clock_frequency11=0 MHz,output_clock_frequency12=0 MHz,output_clock_frequency13=0 MHz,output_clock_frequency14=0 MHz,output_clock_frequency15=0 MHz,output_clock_frequency16=0 MHz,output_clock_frequency17=0 MHz,output_clock_frequency2=17.821346 MHz,output_clock_frequency3=8.860892 MHz,output_clock_frequency4=0 MHz,output_clock_frequency5=0 MHz,output_clock_frequency6=0 MHz,output_clock_frequency7=0 MHz,output_clock_frequency8=0 MHz,output_clock_frequency9=0 MHz,phase_shift0=0 ps,phase_shift1=0 ps,phase_shift10=0 ps,phase_shift11=0 ps,phase_shift12=0 ps,phase_shift13=0 ps,phase_shift14=0 ps,phase_shift15=0 ps,phase_shift16=0 ps,phase_shift17=0 ps,phase_shift2=0 ps,phase_shift3=0 ps,phase_shift4=0 ps,phase_shift5=0 ps,phase_shift6=0 ps,phase_shift7=0 ps,phase_shift8=0 ps,phase_shift9=0 ps,pll_auto_clk_sw_en=false,pll_bwctrl=2000,pll_clk_loss_sw_en=false,pll_clk_sw_dly=0,pll_clkin_0_src=clk_0,pll_clkin_1_src=clk_0,pll_cp_current=30,pll_dsm_out_sel=1st_order,pll_fbclk_mux_1=glb,pll_fbclk_mux_2=fb_1,pll_fractional_cout=32,pll_fractional_division=1681070366,pll_m_cnt_in_src=ph_mux_clk,pll_manu_clk_sw_en=false,pll_output_clk_frequency=1586.099801 MHz,pll_slf_rst=true,pll_subtype=General,pll_type=General,pll_vco_div=1,pll_vcoph_div=1,refclk1_frequency=100.0 MHz,reference_clock_frequency=256.0 MHz"
+   instancePathKey="pll:.:pll_2"
+   kind="altera_pll"
+   version="17.1"
+   name="pll_pll_2">
+  <parameter name="c_cnt_bypass_en17" value="true" />
+  <parameter name="c_cnt_bypass_en14" value="true" />
+  <parameter name="c_cnt_bypass_en13" value="true" />
+  <parameter name="c_cnt_bypass_en16" value="true" />
+  <parameter name="c_cnt_bypass_en15" value="true" />
+  <parameter name="c_cnt_bypass_en10" value="true" />
+  <parameter name="c_cnt_bypass_en12" value="true" />
+  <parameter
+     name="gui_pll_cascading_mode"
+     value="Create an adjpllin signal to connect with an upstream PLL" />
+  <parameter name="c_cnt_bypass_en11" value="true" />
+  <parameter name="pll_fbclk_mux_2" value="fb_1" />
+  <parameter name="pll_fbclk_mux_1" value="glb" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="c_cnt_prst6" value="1" />
+  <parameter name="c_cnt_prst5" value="1" />
+  <parameter name="c_cnt_prst8" value="1" />
+  <parameter name="c_cnt_prst7" value="1" />
+  <parameter name="c_cnt_prst9" value="1" />
+  <parameter name="c_cnt_in_src9" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src8" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src5" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="c_cnt_in_src4" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src7" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src6" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="c_cnt_in_src1" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="c_cnt_in_src0" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="c_cnt_in_src3" value="ph_mux_clk" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="c_cnt_in_src2" value="ph_mux_clk" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="duty_cycle12" value="50" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="duty_cycle13" value="50" />
+  <parameter name="duty_cycle10" value="50" />
+  <parameter name="duty_cycle11" value="50" />
+  <parameter name="duty_cycle16" value="50" />
+  <parameter name="duty_cycle17" value="50" />
+  <parameter name="duty_cycle14" value="50" />
+  <parameter name="duty_cycle15" value="50" />
+  <parameter name="pll_vcoph_div" value="1" />
+  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="pll_fractional_cout" value="32" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="pll_manu_clk_sw_en" value="false" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="c_cnt_prst0" value="1" />
+  <parameter name="c_cnt_prst2" value="1" />
+  <parameter name="c_cnt_prst1" value="1" />
+  <parameter name="gui_actual_divide_factor8" value="1" />
+  <parameter name="c_cnt_prst4" value="1" />
+  <parameter name="gui_actual_divide_factor9" value="1" />
+  <parameter name="c_cnt_prst3" value="1" />
+  <parameter name="gui_pll_auto_reset" value="On" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="phase_shift12" value="0 ps" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="phase_shift11" value="0 ps" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="phase_shift10" value="0 ps" />
+  <parameter name="n_cnt_lo_div" value="1" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_operation_mode" value="normal" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_actual_divide_factor6" value="1" />
+  <parameter name="gui_actual_divide_factor7" value="1" />
+  <parameter name="gui_actual_divide_factor4" value="1" />
+  <parameter name="gui_actual_divide_factor5" value="1" />
+  <parameter name="gui_actual_divide_factor2" value="178" />
+  <parameter name="gui_actual_divide_factor3" value="358" />
+  <parameter name="gui_actual_divide_factor0" value="102" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_actual_divide_factor1" value="126" />
+  <parameter name="gui_actual_frac_multiply_factor8" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor9" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor6" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor7" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="phase_shift17" value="0 ps" />
+  <parameter name="pll_clk_sw_dly" value="0" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="phase_shift16" value="0 ps" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="phase_shift15" value="0 ps" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="phase_shift14" value="0 ps" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="phase_shift13" value="0 ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_pll_mode" value="Fractional-N PLL" />
+  <parameter name="gui_actual_frac_multiply_factor4" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor5" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor2" value="1681070366" />
+  <parameter name="gui_actual_frac_multiply_factor3" value="1681070366" />
+  <parameter name="gui_actual_frac_multiply_factor0" value="1681070366" />
+  <parameter name="gui_actual_frac_multiply_factor1" value="1681070366" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="pll_slf_rst" value="true" />
+  <parameter name="duty_cycle9" value="50" />
+  <parameter name="duty_cycle7" value="50" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="duty_cycle8" value="50" />
+  <parameter name="duty_cycle5" value="50" />
+  <parameter name="duty_cycle6" value="50" />
+  <parameter name="duty_cycle3" value="50" />
+  <parameter name="duty_cycle4" value="50" />
+  <parameter name="duty_cycle1" value="50" />
+  <parameter name="duty_cycle2" value="50" />
+  <parameter name="duty_cycle0" value="50" />
+  <parameter name="m_cnt_lo_div" value="6" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="pll_clk_loss_sw_en" value="false" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units2" value="degrees" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_use_locked" value="false" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="25.568627 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="pll_type" value="General" />
+  <parameter name="gui_actual_output_clock_frequency1" value="31.500000 MHz" />
+  <parameter name="gui_actual_output_clock_frequency0" value="36.000000 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="pll_output_clk_frequency" value="1586.099801 MHz" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="c_cnt_lo_div14" value="1" />
+  <parameter name="c_cnt_lo_div15" value="1" />
+  <parameter name="c_cnt_lo_div12" value="1" />
+  <parameter name="c_cnt_lo_div13" value="1" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="c_cnt_lo_div16" value="1" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="c_cnt_lo_div17" value="1" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="c_cnt_lo_div10" value="1" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="c_cnt_lo_div11" value="1" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="pll_fractional_division" value="1681070366" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="fractional_vco_multiplier" value="true" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="m_cnt_bypass_en" value="false" />
+  <parameter name="gui_number_of_clocks" value="4" />
+  <parameter name="c_cnt_hi_div10" value="1" />
+  <parameter name="c_cnt_hi_div11" value="1" />
+  <parameter name="c_cnt_hi_div12" value="1" />
+  <parameter name="c_cnt_hi_div13" value="1" />
+  <parameter name="c_cnt_hi_div14" value="1" />
+  <parameter name="c_cnt_hi_div15" value="1" />
+  <parameter name="c_cnt_hi_div16" value="1" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="c_cnt_hi_div17" value="1" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_output_clock_frequency0" value="31.1" />
+  <parameter name="output_clock_frequency10" value="0 MHz" />
+  <parameter name="output_clock_frequency11" value="0 MHz" />
+  <parameter name="output_clock_frequency12" value="0 MHz" />
+  <parameter name="pll_bwctrl" value="2000" />
+  <parameter name="output_clock_frequency13" value="0 MHz" />
+  <parameter name="mimic_fbclk_type" value="gclk" />
+  <parameter name="pll_clkin_0_src" value="clk_0" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="output_clock_frequency14" value="0 MHz" />
+  <parameter name="output_clock_frequency15" value="0 MHz" />
+  <parameter name="output_clock_frequency16" value="0 MHz" />
+  <parameter name="output_clock_frequency17" value="0 MHz" />
+  <parameter name="n_cnt_bypass_en" value="false" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="m_cnt_odd_div_duty_en" value="false" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency3" value="8.867237" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_output_clock_frequency4" value="8.867237" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_output_clock_frequency1" value="25.175" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_output_clock_frequency2" value="17.734475" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_actual_divide_factor10" value="1" />
+  <parameter name="gui_actual_divide_factor16" value="1" />
+  <parameter name="device_family" value="Cyclone V" />
+  <parameter name="gui_actual_divide_factor15" value="1" />
+  <parameter name="gui_actual_divide_factor17" value="1" />
+  <parameter name="gui_actual_divide_factor12" value="1" />
+  <parameter name="gui_actual_divide_factor11" value="1" />
+  <parameter name="gui_actual_divide_factor14" value="1" />
+  <parameter name="gui_actual_divide_factor13" value="1" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_actual_multiply_factor9" value="1" />
+  <parameter name="gui_actual_multiply_factor6" value="1" />
+  <parameter name="gui_actual_multiply_factor5" value="1" />
+  <parameter name="gui_actual_multiply_factor8" value="1" />
+  <parameter name="gui_actual_multiply_factor7" value="1" />
+  <parameter name="gui_actual_multiply_factor2" value="12" />
+  <parameter name="gui_actual_multiply_factor1" value="12" />
+  <parameter name="gui_actual_multiply_factor4" value="1" />
+  <parameter name="gui_actual_multiply_factor3" value="12" />
+  <parameter name="refclk1_frequency" value="100.0 MHz" />
+  <parameter name="gui_actual_multiply_factor0" value="12" />
+  <parameter name="reference_clock_frequency" value="256.0 MHz" />
+  <parameter name="pll_m_cnt_in_src" value="ph_mux_clk" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="c_cnt_hi_div0" value="26" />
+  <parameter name="c_cnt_hi_div1" value="32" />
+  <parameter name="c_cnt_hi_div2" value="45" />
+  <parameter name="c_cnt_hi_div3" value="90" />
+  <parameter name="c_cnt_hi_div4" value="1" />
+  <parameter name="m_cnt_hi_div" value="6" />
+  <parameter name="c_cnt_hi_div5" value="1" />
+  <parameter name="c_cnt_hi_div6" value="1" />
+  <parameter name="c_cnt_hi_div7" value="1" />
+  <parameter name="n_cnt_odd_div_duty_en" value="false" />
+  <parameter name="c_cnt_hi_div8" value="1" />
+  <parameter name="c_cnt_hi_div9" value="1" />
+  <parameter name="c_cnt_ph_mux_prst8" value="0" />
+  <parameter name="c_cnt_ph_mux_prst7" value="0" />
+  <parameter name="c_cnt_ph_mux_prst9" value="0" />
+  <parameter name="c_cnt_ph_mux_prst0" value="0" />
+  <parameter name="c_cnt_ph_mux_prst2" value="0" />
+  <parameter name="c_cnt_ph_mux_prst1" value="0" />
+  <parameter name="c_cnt_ph_mux_prst4" value="0" />
+  <parameter name="c_cnt_ph_mux_prst3" value="0" />
+  <parameter name="c_cnt_ph_mux_prst6" value="0" />
+  <parameter name="c_cnt_ph_mux_prst5" value="0" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_switchover_mode" value="Automatic Switchover" />
+  <parameter
+     name="gui_parameter_values"
+     value="6,6,1,1,false,false,false,false,26,25,1,0,ph_mux_clk,false,true,32,31,1,0,ph_mux_clk,false,true,45,44,1,0,ph_mux_clk,false,true,90,89,1,0,ph_mux_clk,false,true,1,30,2000,1586.099801 MHz,1681070366,gclk,glb,fb_1,ph_mux_clk,true" />
+  <parameter name="pll_auto_clk_sw_en" value="false" />
+  <parameter name="pll_subtype" value="General" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_actual_multiply_factor10" value="1" />
+  <parameter name="gui_actual_multiply_factor11" value="1" />
+  <parameter name="c_cnt_in_src17" value="ph_mux_clk" />
+  <parameter name="gui_actual_multiply_factor12" value="1" />
+  <parameter name="c_cnt_in_src16" value="ph_mux_clk" />
+  <parameter name="gui_actual_multiply_factor13" value="1" />
+  <parameter name="c_cnt_in_src15" value="ph_mux_clk" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="c_cnt_odd_div_duty_en0" value="true" />
+  <parameter name="c_cnt_odd_div_duty_en1" value="true" />
+  <parameter name="c_cnt_in_src14" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src13" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src12" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src11" value="ph_mux_clk" />
+  <parameter name="c_cnt_in_src10" value="ph_mux_clk" />
+  <parameter name="pll_vco_div" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en2" value="true" />
+  <parameter name="c_cnt_odd_div_duty_en3" value="true" />
+  <parameter name="c_cnt_odd_div_duty_en4" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en5" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en6" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en7" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en8" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en9" value="false" />
+  <parameter name="c_cnt_prst13" value="1" />
+  <parameter name="c_cnt_prst12" value="1" />
+  <parameter name="c_cnt_prst11" value="1" />
+  <parameter name="c_cnt_prst10" value="1" />
+  <parameter name="c_cnt_prst17" value="1" />
+  <parameter name="c_cnt_prst16" value="1" />
+  <parameter name="pll_dsm_out_sel" value="1st_order" />
+  <parameter name="c_cnt_prst15" value="1" />
+  <parameter name="c_cnt_prst14" value="1" />
+  <parameter name="c_cnt_lo_div9" value="1" />
+  <parameter name="c_cnt_lo_div7" value="1" />
+  <parameter name="c_cnt_lo_div8" value="1" />
+  <parameter name="number_of_cascade_counters" value="0" />
+  <parameter name="c_cnt_lo_div5" value="1" />
+  <parameter name="c_cnt_lo_div6" value="1" />
+  <parameter name="c_cnt_lo_div3" value="89" />
+  <parameter name="c_cnt_lo_div4" value="1" />
+  <parameter name="c_cnt_lo_div1" value="31" />
+  <parameter name="c_cnt_lo_div2" value="44" />
+  <parameter name="c_cnt_lo_div0" value="25" />
+  <parameter name="gui_actual_frac_multiply_factor12" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor11" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor10" value="1" />
+  <parameter name="pll_cp_current" value="30" />
+  <parameter name="gui_actual_frac_multiply_factor16" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor15" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor14" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor13" value="1" />
+  <parameter name="gui_actual_frac_multiply_factor17" value="1" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="pll_clkin_1_src" value="clk_0" />
+  <parameter name="phase_shift1" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst17" value="0" />
+  <parameter name="phase_shift0" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst16" value="0" />
+  <parameter name="phase_shift3" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst15" value="0" />
+  <parameter name="phase_shift2" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst14" value="0" />
+  <parameter name="phase_shift5" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst13" value="0" />
+  <parameter name="phase_shift4" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst12" value="0" />
+  <parameter name="phase_shift7" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst11" value="0" />
+  <parameter name="phase_shift6" value="0 ps" />
+  <parameter name="c_cnt_ph_mux_prst10" value="0" />
+  <parameter name="phase_shift9" value="0 ps" />
+  <parameter name="phase_shift8" value="0 ps" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="number_of_clocks" value="4" />
+  <parameter name="n_cnt_hi_div" value="1" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="output_clock_frequency6" value="0 MHz" />
+  <parameter name="output_clock_frequency9" value="0 MHz" />
+  <parameter
+     name="gui_parameter_list"
+     value="M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="c_cnt_odd_div_duty_en17" value="false" />
+  <parameter name="operation_mode" value="normal" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_actual_multiply_factor14" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en16" value="false" />
+  <parameter name="gui_actual_multiply_factor15" value="1" />
+  <parameter name="output_clock_frequency0" value="31.099998 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en15" value="false" />
+  <parameter name="gui_actual_multiply_factor16" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en14" value="false" />
+  <parameter name="gui_actual_multiply_factor17" value="1" />
+  <parameter name="c_cnt_odd_div_duty_en13" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="output_clock_frequency3" value="8.860892 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en12" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="output_clock_frequency4" value="0 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en11" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="output_clock_frequency1" value="25.176188 MHz" />
+  <parameter name="c_cnt_odd_div_duty_en10" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="output_clock_frequency2" value="17.821346 MHz" />
+  <parameter name="c_cnt_bypass_en6" value="true" />
+  <parameter name="c_cnt_bypass_en7" value="true" />
+  <parameter name="c_cnt_bypass_en8" value="true" />
+  <parameter name="c_cnt_bypass_en9" value="true" />
+  <parameter name="c_cnt_bypass_en0" value="false" />
+  <parameter name="c_cnt_bypass_en1" value="false" />
+  <parameter name="c_cnt_bypass_en2" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="256.0" />
+  <parameter name="c_cnt_bypass_en3" value="false" />
+  <parameter name="c_cnt_bypass_en4" value="true" />
+  <parameter name="c_cnt_bypass_en5" value="true" />
+  <generatedFiles>
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/srv/dvlp/Projects/dev/github/em/common/pll/synthesis/submodules/pll_pll_2.qip"
+       type="OTHER"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/srv/CAD/QuartusII/17.1/ip/altera/altera_pll/source/top/pll_hw.tcl" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/guava-15.0.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/javasysmon.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/srv/CAD/QuartusII/17.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="pll" as="pll_2" />
+  <messages>
+   <message level="Debug" culprit="pll">queue size: 0 starting:altera_pll "submodules/pll_pll_2"</message>
+   <message level="Info" culprit="pll_2"><![CDATA["<b>pll</b>" instantiated <b>altera_pll</b> "<b>pll_2</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/common/pll/pll_bb.v b/common/pll/pll_bb.v
new file mode 100644
index 0000000..d010237
--- /dev/null
+++ b/common/pll/pll_bb.v
@@ -0,0 +1,46 @@
+
+module pll (
+	clk_clk,
+	pll_0_outclk1_clk,
+	pll_0_outclk2_clk,
+	pll_0_outclk3_clk,
+	pll_0_outclk4_clk,
+	pll_0_outclk5_clk,
+	pll_0_outclk6_clk,
+	pll_0_refclk_clk,
+	pll_0_reset_reset,
+	pll_1_outclk0_clk,
+	pll_1_outclk1_clk,
+	pll_1_outclk2_clk,
+	pll_1_outclk3_clk,
+	pll_1_outclk4_clk,
+	pll_1_reset_reset,
+	pll_2_outclk0_clk,
+	pll_2_outclk1_clk,
+	pll_2_outclk2_clk,
+	pll_2_outclk3_clk,
+	pll_2_reset_reset,
+	reset_reset_n);	
+
+	input		clk_clk;
+	output		pll_0_outclk1_clk;
+	output		pll_0_outclk2_clk;
+	output		pll_0_outclk3_clk;
+	output		pll_0_outclk4_clk;
+	output		pll_0_outclk5_clk;
+	output		pll_0_outclk6_clk;
+	input		pll_0_refclk_clk;
+	input		pll_0_reset_reset;
+	output		pll_1_outclk0_clk;
+	output		pll_1_outclk1_clk;
+	output		pll_1_outclk2_clk;
+	output		pll_1_outclk3_clk;
+	output		pll_1_outclk4_clk;
+	input		pll_1_reset_reset;
+	output		pll_2_outclk0_clk;
+	output		pll_2_outclk1_clk;
+	output		pll_2_outclk2_clk;
+	output		pll_2_outclk3_clk;
+	input		pll_2_reset_reset;
+	input		reset_reset_n;
+endmodule
diff --git a/common/pll/pll_generation.rpt b/common/pll/pll_generation.rpt
new file mode 100644
index 0000000..4b039fc
--- /dev/null
+++ b/common/pll/pll_generation.rpt
@@ -0,0 +1,54 @@
+Info: Starting: Create block symbol file (.bsf)
+Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --block-symbol-file --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll --family="Cyclone V" --part=5CSEBA6U23I7
+Progress: Loading common/pll.qsys
+Progress: Reading input file
+Progress: Adding clk_0 [clock_source 17.1]
+Progress: Parameterizing module clk_0
+Progress: Adding pll_0 [altera_pll 17.1]
+Progress: Parameterizing module pll_0
+Progress: Adding pll_1 [altera_pll 17.1]
+Progress: Parameterizing module pll_1
+Progress: Adding pll_2 [altera_pll 17.1]
+Progress: Parameterizing module pll_2
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
+Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
+Info: qsys-generate succeeded.
+Info: Finished: Create block symbol file (.bsf)
+Info: 
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --synthesis=VHDL --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll/synthesis --family="Cyclone V" --part=5CSEBA6U23I7
+Progress: Loading common/pll.qsys
+Progress: Reading input file
+Progress: Adding clk_0 [clock_source 17.1]
+Progress: Parameterizing module clk_0
+Progress: Adding pll_0 [altera_pll 17.1]
+Progress: Parameterizing module pll_0
+Progress: Adding pll_1 [altera_pll 17.1]
+Progress: Parameterizing module pll_1
+Progress: Adding pll_2 [altera_pll 17.1]
+Progress: Parameterizing module pll_2
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
+Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll: Generating pll "pll" for QUARTUS_SYNTH
+Info: pll_0: "pll" instantiated altera_pll "pll_0"
+Info: pll_1: "pll" instantiated altera_pll "pll_1"
+Info: pll_2: "pll" instantiated altera_pll "pll_2"
+Info: pll: Done "pll" with 4 modules, 7 files
+Info: qsys-generate succeeded.
+Info: Finished: Create HDL design files for synthesis
diff --git a/common/pll/pll_generation_previous.rpt b/common/pll/pll_generation_previous.rpt
new file mode 100644
index 0000000..4b039fc
--- /dev/null
+++ b/common/pll/pll_generation_previous.rpt
@@ -0,0 +1,54 @@
+Info: Starting: Create block symbol file (.bsf)
+Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --block-symbol-file --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll --family="Cyclone V" --part=5CSEBA6U23I7
+Progress: Loading common/pll.qsys
+Progress: Reading input file
+Progress: Adding clk_0 [clock_source 17.1]
+Progress: Parameterizing module clk_0
+Progress: Adding pll_0 [altera_pll 17.1]
+Progress: Parameterizing module pll_0
+Progress: Adding pll_1 [altera_pll 17.1]
+Progress: Parameterizing module pll_1
+Progress: Adding pll_2 [altera_pll 17.1]
+Progress: Parameterizing module pll_2
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
+Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
+Info: qsys-generate succeeded.
+Info: Finished: Create block symbol file (.bsf)
+Info: 
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --synthesis=VHDL --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll/synthesis --family="Cyclone V" --part=5CSEBA6U23I7
+Progress: Loading common/pll.qsys
+Progress: Reading input file
+Progress: Adding clk_0 [clock_source 17.1]
+Progress: Parameterizing module clk_0
+Progress: Adding pll_0 [altera_pll 17.1]
+Progress: Parameterizing module pll_0
+Progress: Adding pll_1 [altera_pll 17.1]
+Progress: Parameterizing module pll_1
+Progress: Adding pll_2 [altera_pll 17.1]
+Progress: Parameterizing module pll_2
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
+Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
+Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
+Info: pll: Generating pll "pll" for QUARTUS_SYNTH
+Info: pll_0: "pll" instantiated altera_pll "pll_0"
+Info: pll_1: "pll" instantiated altera_pll "pll_1"
+Info: pll_2: "pll" instantiated altera_pll "pll_2"
+Info: pll: Done "pll" with 4 modules, 7 files
+Info: qsys-generate succeeded.
+Info: Finished: Create HDL design files for synthesis
diff --git a/common/pll/pll_inst.v b/common/pll/pll_inst.v
new file mode 100644
index 0000000..24b8ab0
--- /dev/null
+++ b/common/pll/pll_inst.v
@@ -0,0 +1,24 @@
+	pll u0 (
+		.clk_clk           (<connected-to-clk_clk>),           //           clk.clk
+		.pll_0_outclk1_clk (<connected-to-pll_0_outclk1_clk>), // pll_0_outclk1.clk
+		.pll_0_outclk2_clk (<connected-to-pll_0_outclk2_clk>), // pll_0_outclk2.clk
+		.pll_0_outclk3_clk (<connected-to-pll_0_outclk3_clk>), // pll_0_outclk3.clk
+		.pll_0_outclk4_clk (<connected-to-pll_0_outclk4_clk>), // pll_0_outclk4.clk
+		.pll_0_outclk5_clk (<connected-to-pll_0_outclk5_clk>), // pll_0_outclk5.clk
+		.pll_0_outclk6_clk (<connected-to-pll_0_outclk6_clk>), // pll_0_outclk6.clk
+		.pll_0_refclk_clk  (<connected-to-pll_0_refclk_clk>),  //  pll_0_refclk.clk
+		.pll_0_reset_reset (<connected-to-pll_0_reset_reset>), //   pll_0_reset.reset
+		.pll_1_outclk0_clk (<connected-to-pll_1_outclk0_clk>), // pll_1_outclk0.clk
+		.pll_1_outclk1_clk (<connected-to-pll_1_outclk1_clk>), // pll_1_outclk1.clk
+		.pll_1_outclk2_clk (<connected-to-pll_1_outclk2_clk>), // pll_1_outclk2.clk
+		.pll_1_outclk3_clk (<connected-to-pll_1_outclk3_clk>), // pll_1_outclk3.clk
+		.pll_1_outclk4_clk (<connected-to-pll_1_outclk4_clk>), // pll_1_outclk4.clk
+		.pll_1_reset_reset (<connected-to-pll_1_reset_reset>), //   pll_1_reset.reset
+		.pll_2_outclk0_clk (<connected-to-pll_2_outclk0_clk>), // pll_2_outclk0.clk
+		.pll_2_outclk1_clk (<connected-to-pll_2_outclk1_clk>), // pll_2_outclk1.clk
+		.pll_2_outclk2_clk (<connected-to-pll_2_outclk2_clk>), // pll_2_outclk2.clk
+		.pll_2_outclk3_clk (<connected-to-pll_2_outclk3_clk>), // pll_2_outclk3.clk
+		.pll_2_reset_reset (<connected-to-pll_2_reset_reset>), //   pll_2_reset.reset
+		.reset_reset_n     (<connected-to-reset_reset_n>)      //         reset.reset_n
+	);
+
diff --git a/common/pll/pll_inst.vhd b/common/pll/pll_inst.vhd
new file mode 100644
index 0000000..9268f8d
--- /dev/null
+++ b/common/pll/pll_inst.vhd
@@ -0,0 +1,51 @@
+	component pll is
+		port (
+			clk_clk           : in  std_logic := 'X'; -- clk
+			pll_0_outclk1_clk : out std_logic;        -- clk
+			pll_0_outclk2_clk : out std_logic;        -- clk
+			pll_0_outclk3_clk : out std_logic;        -- clk
+			pll_0_outclk4_clk : out std_logic;        -- clk
+			pll_0_outclk5_clk : out std_logic;        -- clk
+			pll_0_outclk6_clk : out std_logic;        -- clk
+			pll_0_refclk_clk  : in  std_logic := 'X'; -- clk
+			pll_0_reset_reset : in  std_logic := 'X'; -- reset
+			pll_1_outclk0_clk : out std_logic;        -- clk
+			pll_1_outclk1_clk : out std_logic;        -- clk
+			pll_1_outclk2_clk : out std_logic;        -- clk
+			pll_1_outclk3_clk : out std_logic;        -- clk
+			pll_1_outclk4_clk : out std_logic;        -- clk
+			pll_1_reset_reset : in  std_logic := 'X'; -- reset
+			pll_2_outclk0_clk : out std_logic;        -- clk
+			pll_2_outclk1_clk : out std_logic;        -- clk
+			pll_2_outclk2_clk : out std_logic;        -- clk
+			pll_2_outclk3_clk : out std_logic;        -- clk
+			pll_2_reset_reset : in  std_logic := 'X'; -- reset
+			reset_reset_n     : in  std_logic := 'X'  -- reset_n
+		);
+	end component pll;
+
+	u0 : component pll
+		port map (
+			clk_clk           => CONNECTED_TO_clk_clk,           --           clk.clk
+			pll_0_outclk1_clk => CONNECTED_TO_pll_0_outclk1_clk, -- pll_0_outclk1.clk
+			pll_0_outclk2_clk => CONNECTED_TO_pll_0_outclk2_clk, -- pll_0_outclk2.clk
+			pll_0_outclk3_clk => CONNECTED_TO_pll_0_outclk3_clk, -- pll_0_outclk3.clk
+			pll_0_outclk4_clk => CONNECTED_TO_pll_0_outclk4_clk, -- pll_0_outclk4.clk
+			pll_0_outclk5_clk => CONNECTED_TO_pll_0_outclk5_clk, -- pll_0_outclk5.clk
+			pll_0_outclk6_clk => CONNECTED_TO_pll_0_outclk6_clk, -- pll_0_outclk6.clk
+			pll_0_refclk_clk  => CONNECTED_TO_pll_0_refclk_clk,  --  pll_0_refclk.clk
+			pll_0_reset_reset => CONNECTED_TO_pll_0_reset_reset, --   pll_0_reset.reset
+			pll_1_outclk0_clk => CONNECTED_TO_pll_1_outclk0_clk, -- pll_1_outclk0.clk
+			pll_1_outclk1_clk => CONNECTED_TO_pll_1_outclk1_clk, -- pll_1_outclk1.clk
+			pll_1_outclk2_clk => CONNECTED_TO_pll_1_outclk2_clk, -- pll_1_outclk2.clk
+			pll_1_outclk3_clk => CONNECTED_TO_pll_1_outclk3_clk, -- pll_1_outclk3.clk
+			pll_1_outclk4_clk => CONNECTED_TO_pll_1_outclk4_clk, -- pll_1_outclk4.clk
+			pll_1_reset_reset => CONNECTED_TO_pll_1_reset_reset, --   pll_1_reset.reset
+			pll_2_outclk0_clk => CONNECTED_TO_pll_2_outclk0_clk, -- pll_2_outclk0.clk
+			pll_2_outclk1_clk => CONNECTED_TO_pll_2_outclk1_clk, -- pll_2_outclk1.clk
+			pll_2_outclk2_clk => CONNECTED_TO_pll_2_outclk2_clk, -- pll_2_outclk2.clk
+			pll_2_outclk3_clk => CONNECTED_TO_pll_2_outclk3_clk, -- pll_2_outclk3.clk
+			pll_2_reset_reset => CONNECTED_TO_pll_2_reset_reset, --   pll_2_reset.reset
+			reset_reset_n     => CONNECTED_TO_reset_reset_n      --         reset.reset_n
+		);
+
diff --git a/common/pll/synthesis/pll.debuginfo b/common/pll/synthesis/pll.debuginfo
new file mode 100644
index 0000000..a0d195b
--- /dev/null
+++ b/common/pll/synthesis/pll.debuginfo
@@ -0,0 +1,13433 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="pll" kind="system" version="17.1" fabric="QSYS">
+ <!-- Format version 17.1 593 (Future versions may contain additional information.) -->
+ <!-- 2018.12.10.19:38:13 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>5CSEBA6U23I7</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>CYCLONEV</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>7</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1544470692</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module name="clk_0" kind="clock_source" version="17.1" path="clk_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="clockFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockFrequencyKnown">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inputClockFrequency">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk_in</sysinfo_arg>
+  </parameter>
+  <parameter name="resetSynchronousEdges">
+   <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk_in" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>clk</value>
+   </assignment>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="clk_in_reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>reset</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value>clk_in</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>50000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>clk_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="clk_reset" kind="reset_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_n_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+ </module>
+ <module name="pll_0" kind="altera_pll" version="17.1" path="pll_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="debug_print_output">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_use_rbc_taf_method">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="device_family">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="device">
+   <type>java.lang.String</type>
+   <value>5CSEBA6U23I7</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="gui_device_speed_grade">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_mode">
+   <type>java.lang.String</type>
+   <value>Fractional-N PLL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fractional_vco_multiplier">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_reference_clock_frequency">
+   <type>double</type>
+   <value>50.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reference_clock_frequency">
+   <type>java.lang.String</type>
+   <value>50.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_channel_spacing">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_feedback_clock">
+   <type>java.lang.String</type>
+   <value>Global Clock</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_use_locked">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_adv_params">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_number_of_clocks">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_clocks">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_cascade_counters">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_multiply_factor">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_frac_multiply_factor">
+   <type>long</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_n">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter0">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency0">
+   <type>double</type>
+   <value>256.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c0">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor0">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor0">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor0">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>120.000000 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units0">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg0">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift0">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter1">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency1">
+   <type>double</type>
+   <value>112.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c1">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor1">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor1">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor1">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units1">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg1">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift1">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter2">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency2">
+   <type>double</type>
+   <value>64.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c2">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor2">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor2">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor2">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units2">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg2">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift2">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter3">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency3">
+   <type>double</type>
+   <value>32.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c3">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor3">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor3">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor3">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>32.533324 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units3">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg3">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift3">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter4">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency4">
+   <type>double</type>
+   <value>16.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c4">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor4">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor4">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor4">
+   <type>int</type>
+   <value>48</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units4">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg4">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift4">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter5">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency5">
+   <type>double</type>
+   <value>8.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c5">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor5">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor5">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor5">
+   <type>int</type>
+   <value>96</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units5">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg5">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift5">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter6">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency6">
+   <type>double</type>
+   <value>4.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c6">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor6">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor6">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor6">
+   <type>int</type>
+   <value>192</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units6">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg6">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift6">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter7">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency7">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c7">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor7">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor7">
+   <type>long</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor7">
+   <type>int</type>
+   <value>384</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units7">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg7">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift7">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter8">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency8">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c8">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor8">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units8">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg8">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift8">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter9">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency9">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c9">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor9">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units9">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg9">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift9">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter10">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency10">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c10">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor10">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units10">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg10">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift10">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter11">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency11">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c11">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor11">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units11">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg11">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift11">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter12">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency12">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c12">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor12">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units12">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg12">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift12">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter13">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency13">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c13">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor13">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units13">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg13">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift13">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter14">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency14">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c14">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor14">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units14">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg14">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift14">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter15">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency15">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c15">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor15">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units15">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg15">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift15">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter16">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency16">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c16">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor16">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units16">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift16">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg16">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift16">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter17">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency17">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c17">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor17">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units17">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift17">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg17">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift17">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>255.999872 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift0">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>109.714257 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift1">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>63.999981 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift2">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>31.999989 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift3">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>15.999994 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift4">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>7.999996 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift5">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>3.999998 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift6">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>1.999999 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift7">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift8">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift9">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift10">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift11">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift12">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift13">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift14">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift15">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift16">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift17">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_auto_reset">
+   <type>java.lang.String</type>
+   <value>On</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_bandwidth_preset">
+   <type>java.lang.String</type>
+   <value>Auto</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_reconf">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_dps_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_phout_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phout_division">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vcoph_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_type">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_subtype">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_hi_div">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_lo_div">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_hi_div">
+   <type>int</type>
+   <value>256</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_lo_div">
+   <type>int</type>
+   <value>256</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div0">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src0">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en0">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div1">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div1">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src1">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en1">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div2">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div2">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src2">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div3">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div3">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src3">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div4">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div4">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src4">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div5">
+   <type>int</type>
+   <value>48</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div5">
+   <type>int</type>
+   <value>48</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src5">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div6">
+   <type>int</type>
+   <value>96</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div6">
+   <type>int</type>
+   <value>96</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src6">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div7">
+   <type>int</type>
+   <value>192</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div7">
+   <type>int</type>
+   <value>192</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src7">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst8">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src8">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en8">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en8">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst9">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src9">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en9">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en9">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst10">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src10">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en10">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en10">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst11">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src11">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en11">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en11">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst12">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src12">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en12">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en12">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst13">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src13">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en13">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en13">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst14">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src14">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en14">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en14">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst15">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src15">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en15">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en15">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst16">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src16">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en16">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en16">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst17">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src17">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en17">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en17">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vco_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_cp_current">
+   <type>int</type>
+   <value>20</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_bwctrl">
+   <type>int</type>
+   <value>4000</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_output_clk_frequency">
+   <type>java.lang.String</type>
+   <value>767.999671 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_division">
+   <type>java.lang.String</type>
+   <value>1546159966</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mimic_fbclk_type">
+   <type>java.lang.String</type>
+   <value>gclk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_1">
+   <type>java.lang.String</type>
+   <value>glb</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_2">
+   <type>java.lang.String</type>
+   <value>fb_1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_m_cnt_in_src">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_slf_rst">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_list">
+   <type>[Ljava.lang.String;</type>
+   <value>M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,C-Counter-5 Hi Divide,C-Counter-5 Low Divide,C-Counter-5 Coarse Phase Shift,C-Counter-5 VCO Phase Tap,C-Counter-5 Input Source,C-Counter-5 Bypass Enable,C-Counter-5 Odd Divide Enable,C-Counter-6 Hi Divide,C-Counter-6 Low Divide,C-Counter-6 Coarse Phase Shift,C-Counter-6 VCO Phase Tap,C-Counter-6 Input Source,C-Counter-6 Bypass Enable,C-Counter-6 Odd Divide Enable,C-Counter-7 Hi Divide,C-Counter-7 Low Divide,C-Counter-7 Coarse Phase Shift,C-Counter-7 VCO Phase Tap,C-Counter-7 Input Source,C-Counter-7 Bypass Enable,C-Counter-7 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_values">
+   <type>[Ljava.lang.String;</type>
+   <value>8,7,256,256,false,true,true,false,2,1,1,0,ph_mux_clk,false,true,4,3,1,0,ph_mux_clk,false,true,6,6,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,24,24,1,0,ph_mux_clk,false,false,48,48,1,0,ph_mux_clk,false,false,96,96,1,0,ph_mux_clk,false,false,192,192,1,0,ph_mux_clk,false,false,1,20,4000,767.999671 MHz,1546159966,gclk,glb,fb_1,ph_mux_clk,true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_mif_generate">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_mif_dps">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_cntr">
+   <type>java.lang.String</type>
+   <value>C0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_num">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_dir">
+   <type>java.lang.String</type>
+   <value>Positive</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk_switch">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk1_frequency">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_mode">
+   <type>java.lang.String</type>
+   <value>Automatic Switchover</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_delay">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_active_clk">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_clk_bad">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="refclk1_frequency">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_loss_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_manu_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_auto_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_1_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_sw_dly">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_outclk_index">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_0_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_cascading_mode">
+   <type>java.lang.String</type>
+   <value>Create an adjpllin signal to connect with an upstream PLL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="refclk" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>refclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="outclk0" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>255999872</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>pll_1</moduleName>
+    <slaveName>refclk</slaveName>
+    <name>pll_1.refclk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>pll_2</moduleName>
+    <slaveName>refclk</slaveName>
+    <name>pll_2.refclk</name>
+   </clockDomainMember>
+  </interface>
+  <interface name="outclk1" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>109714257</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk2" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>63999981</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk3" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>31999989</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk4" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>15999994</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_4</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk5" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>7999996</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_5</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk6" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>3999998</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_6</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk7" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>1999999</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_7</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <module name="pll_1" kind="altera_pll" version="17.1" path="pll_1">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="debug_print_output">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_use_rbc_taf_method">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="device_family">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="device">
+   <type>java.lang.String</type>
+   <value>5CSEBA6U23I7</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="gui_device_speed_grade">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_mode">
+   <type>java.lang.String</type>
+   <value>Integer-N PLL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fractional_vco_multiplier">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_reference_clock_frequency">
+   <type>double</type>
+   <value>256.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reference_clock_frequency">
+   <type>java.lang.String</type>
+   <value>256.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_channel_spacing">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_feedback_clock">
+   <type>java.lang.String</type>
+   <value>Global Clock</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_use_locked">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_adv_params">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_number_of_clocks">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_clocks">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_cascade_counters">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_multiply_factor">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_frac_multiply_factor">
+   <type>long</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_n">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter0">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency0">
+   <type>double</type>
+   <value>56.75</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c0">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor0">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor0">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor0">
+   <type>int</type>
+   <value>406</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units0">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg0">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift0">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter1">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency1">
+   <type>double</type>
+   <value>28.375</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c1">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor1">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor1">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor1">
+   <type>int</type>
+   <value>812</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units1">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg1">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift1">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter2">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency2">
+   <type>double</type>
+   <value>14.1875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c2">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor2">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor2">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor2">
+   <type>int</type>
+   <value>1624</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units2">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg2">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift2">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter3">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency3">
+   <type>double</type>
+   <value>7.09375</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c3">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor3">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor3">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor3">
+   <type>int</type>
+   <value>3248</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units3">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg3">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift3">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter4">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency4">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c4">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor4">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor4">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor4">
+   <type>int</type>
+   <value>6496</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units4">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg4">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift4">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter5">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency5">
+   <type>double</type>
+   <value>7.09375</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c5">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor5">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units5">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg5">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift5">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter6">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency6">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c6">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor6">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units6">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg6">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift6">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter7">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency7">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c7">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor7">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units7">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg7">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift7">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter8">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency8">
+   <type>double</type>
+   <value>3.546875</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c8">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor8">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units8">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg8">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift8">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter9">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency9">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c9">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor9">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units9">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg9">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift9">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter10">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency10">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c10">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor10">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units10">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg10">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift10">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter11">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency11">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c11">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor11">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units11">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg11">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift11">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter12">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency12">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c12">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor12">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units12">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg12">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift12">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter13">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency13">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c13">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor13">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units13">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg13">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift13">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter14">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency14">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c14">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor14">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units14">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg14">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift14">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter15">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency15">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c15">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor15">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units15">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg15">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift15">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter16">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency16">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c16">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor16">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units16">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift16">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg16">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift16">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter17">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency17">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c17">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor17">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units17">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift17">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg17">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift17">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>56.748768 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift0">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>28.374384 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift1">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>14.187192 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift2">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>7.093596 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift3">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>3.546798 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift4">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift5">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift6">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift7">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift8">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift9">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift10">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift11">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift12">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift13">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift14">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift15">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift16">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift17">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_auto_reset">
+   <type>java.lang.String</type>
+   <value>On</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_bandwidth_preset">
+   <type>java.lang.String</type>
+   <value>Auto</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_reconf">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_dps_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_phout_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phout_division">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vcoph_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_type">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_subtype">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_hi_div">
+   <type>int</type>
+   <value>45</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_lo_div">
+   <type>int</type>
+   <value>45</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_hi_div">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_lo_div">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div0">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div0">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src0">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div1">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div1">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src1">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div2">
+   <type>int</type>
+   <value>28</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div2">
+   <type>int</type>
+   <value>28</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src2">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div3">
+   <type>int</type>
+   <value>56</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div3">
+   <type>int</type>
+   <value>56</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src3">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div4">
+   <type>int</type>
+   <value>112</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div4">
+   <type>int</type>
+   <value>112</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src4">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src5">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en5">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src6">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en6">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src7">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en7">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst8">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src8">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en8">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en8">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst9">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src9">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en9">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en9">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst10">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src10">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en10">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en10">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst11">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src11">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en11">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en11">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst12">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src12">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en12">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en12">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst13">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src13">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en13">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en13">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst14">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src14">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en14">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en14">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst15">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src15">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en15">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en15">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst16">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src16">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en16">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en16">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst17">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src17">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en17">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en17">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vco_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_cp_current">
+   <type>int</type>
+   <value>20</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_bwctrl">
+   <type>int</type>
+   <value>10000</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_output_clk_frequency">
+   <type>java.lang.String</type>
+   <value>794.482758 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_division">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mimic_fbclk_type">
+   <type>java.lang.String</type>
+   <value>gclk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_1">
+   <type>java.lang.String</type>
+   <value>glb</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_2">
+   <type>java.lang.String</type>
+   <value>fb_1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_m_cnt_in_src">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_slf_rst">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_list">
+   <type>[Ljava.lang.String;</type>
+   <value>M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_values">
+   <type>[Ljava.lang.String;</type>
+   <value>45,45,15,14,false,false,false,true,7,7,1,0,ph_mux_clk,false,false,14,14,1,0,ph_mux_clk,false,false,28,28,1,0,ph_mux_clk,false,false,56,56,1,0,ph_mux_clk,false,false,112,112,1,0,ph_mux_clk,false,false,1,20,10000,794.482758 MHz,1,gclk,glb,fb_1,ph_mux_clk,true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_mif_generate">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_mif_dps">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_cntr">
+   <type>java.lang.String</type>
+   <value>C0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_num">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_dir">
+   <type>java.lang.String</type>
+   <value>Positive</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk_switch">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk1_frequency">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_mode">
+   <type>java.lang.String</type>
+   <value>Automatic Switchover</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_delay">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_active_clk">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_clk_bad">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="refclk1_frequency">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_loss_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_manu_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_auto_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_1_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_sw_dly">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_outclk_index">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_0_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_cascading_mode">
+   <type>java.lang.String</type>
+   <value>Create an adjpllin signal to connect with an upstream PLL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="refclk" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>refclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="outclk0" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>56748768</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk1" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>28374384</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk2" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>14187192</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk3" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>7093596</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk4" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>3546798</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_4</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <module name="pll_2" kind="altera_pll" version="17.1" path="pll_2">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="debug_print_output">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_use_rbc_taf_method">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="device_family">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="device">
+   <type>java.lang.String</type>
+   <value>5CSEBA6U23I7</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="gui_device_speed_grade">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_mode">
+   <type>java.lang.String</type>
+   <value>Fractional-N PLL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fractional_vco_multiplier">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_reference_clock_frequency">
+   <type>double</type>
+   <value>256.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reference_clock_frequency">
+   <type>java.lang.String</type>
+   <value>256.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_channel_spacing">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_feedback_clock">
+   <type>java.lang.String</type>
+   <value>Global Clock</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_cout">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_dsm_out_sel">
+   <type>java.lang.String</type>
+   <value>1st_order</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="operation_mode">
+   <type>java.lang.String</type>
+   <value>normal</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_use_locked">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_adv_params">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_number_of_clocks">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_clocks">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="number_of_cascade_counters">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_multiply_factor">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_frac_multiply_factor">
+   <type>long</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_n">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter0">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency0">
+   <type>double</type>
+   <value>31.1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c0">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor0">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor0">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor0">
+   <type>int</type>
+   <value>102</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>36.000000 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units0">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg0">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift0">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter1">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency1">
+   <type>double</type>
+   <value>25.175</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c1">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor1">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor1">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor1">
+   <type>int</type>
+   <value>126</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>31.500000 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units1">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg1">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift1">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter2">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency2">
+   <type>double</type>
+   <value>17.734475</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c2">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor2">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor2">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor2">
+   <type>int</type>
+   <value>178</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>25.568627 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units2">
+   <type>java.lang.String</type>
+   <value>degrees</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg2">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift2">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter3">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency3">
+   <type>double</type>
+   <value>8.867237</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c3">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor3">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor3">
+   <type>long</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor3">
+   <type>int</type>
+   <value>358</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units3">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg3">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift3">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter4">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency4">
+   <type>double</type>
+   <value>8.867237</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c4">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor4">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units4">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg4">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift4">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter5">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency5">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c5">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor5">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units5">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg5">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift5">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter6">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency6">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c6">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor6">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units6">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg6">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift6">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter7">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency7">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c7">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor7">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units7">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg7">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift7">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter8">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency8">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c8">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor8">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units8">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg8">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift8">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter9">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency9">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c9">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor9">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units9">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg9">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift9">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter10">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency10">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c10">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor10">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units10">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg10">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift10">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter11">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency11">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c11">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor11">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units11">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg11">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift11">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter12">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency12">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c12">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor12">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units12">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg12">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift12">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter13">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency13">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c13">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor13">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units13">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg13">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift13">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter14">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency14">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c14">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor14">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units14">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg14">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift14">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter15">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency15">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c15">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor15">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units15">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg15">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift15">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter16">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency16">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c16">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor16">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units16">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift16">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg16">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift16">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_counter17">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_output_clock_frequency17">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_divide_factor_c17">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_multiply_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_frac_multiply_factor17">
+   <type>long</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_divide_factor17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_ps_units17">
+   <type>java.lang.String</type>
+   <value>ps</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift17">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phase_shift_deg17">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_actual_phase_shift17">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency0">
+   <type>java.lang.String</type>
+   <value>31.099998 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift0">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle0">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency1">
+   <type>java.lang.String</type>
+   <value>25.176188 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift1">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle1">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency2">
+   <type>java.lang.String</type>
+   <value>17.821346 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift2">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle2">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency3">
+   <type>java.lang.String</type>
+   <value>8.860892 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift3">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle3">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency4">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift4">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle4">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency5">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift5">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle5">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency6">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift6">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle6">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency7">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift7">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle7">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency8">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift8">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle8">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency9">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift9">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle9">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency10">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift10">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle10">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency11">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift11">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle11">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency12">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift12">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle12">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency13">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift13">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle13">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency14">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift14">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle14">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency15">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift15">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle15">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency16">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift16">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle16">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="output_clock_frequency17">
+   <type>java.lang.String</type>
+   <value>0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phase_shift17">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="duty_cycle17">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_auto_reset">
+   <type>java.lang.String</type>
+   <value>On</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_bandwidth_preset">
+   <type>java.lang.String</type>
+   <value>Auto</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_reconf">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_dps_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_en_phout_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_phout_division">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vcoph_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_type">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_subtype">
+   <type>java.lang.String</type>
+   <value>General</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_hi_div">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_lo_div">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_hi_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_lo_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_bypass_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="m_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="n_cnt_odd_div_duty_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div0">
+   <type>int</type>
+   <value>26</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div0">
+   <type>int</type>
+   <value>25</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src0">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en0">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en0">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div1">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div1">
+   <type>int</type>
+   <value>31</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src1">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en1">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en1">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div2">
+   <type>int</type>
+   <value>45</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div2">
+   <type>int</type>
+   <value>44</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src2">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en2">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en2">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div3">
+   <type>int</type>
+   <value>90</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div3">
+   <type>int</type>
+   <value>89</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src3">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en3">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en3">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src4">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en4">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en4">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src5">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en5">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en5">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst6">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src6">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en6">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en6">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst7">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src7">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en7">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en7">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst8">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst8">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src8">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en8">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en8">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst9">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst9">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src9">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en9">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en9">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst10">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst10">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src10">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en10">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en10">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst11">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst11">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src11">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en11">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en11">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst12">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst12">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src12">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en12">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en12">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst13">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst13">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src13">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en13">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en13">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst14">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst14">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src14">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en14">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en14">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst15">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst15">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src15">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en15">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en15">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst16">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst16">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src16">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en16">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en16">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_hi_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_lo_div17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_prst17">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_ph_mux_prst17">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_in_src17">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_bypass_en17">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="c_cnt_odd_div_duty_en17">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_vco_div">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_cp_current">
+   <type>int</type>
+   <value>30</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_bwctrl">
+   <type>int</type>
+   <value>2000</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_output_clk_frequency">
+   <type>java.lang.String</type>
+   <value>1586.099801 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fractional_division">
+   <type>java.lang.String</type>
+   <value>1681070366</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mimic_fbclk_type">
+   <type>java.lang.String</type>
+   <value>gclk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_1">
+   <type>java.lang.String</type>
+   <value>glb</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_fbclk_mux_2">
+   <type>java.lang.String</type>
+   <value>fb_1</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_m_cnt_in_src">
+   <type>java.lang.String</type>
+   <value>ph_mux_clk</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_slf_rst">
+   <type>java.lang.String</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_list">
+   <type>[Ljava.lang.String;</type>
+   <value>M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_parameter_values">
+   <type>[Ljava.lang.String;</type>
+   <value>6,6,1,1,false,false,false,false,26,25,1,0,ph_mux_clk,false,true,32,31,1,0,ph_mux_clk,false,true,45,44,1,0,ph_mux_clk,false,true,90,89,1,0,ph_mux_clk,false,true,1,30,2000,1586.099801 MHz,1681070366,gclk,glb,fb_1,ph_mux_clk,true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_mif_generate">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_mif_dps">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_cntr">
+   <type>java.lang.String</type>
+   <value>C0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_num">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_dps_dir">
+   <type>java.lang.String</type>
+   <value>Positive</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk_switch">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_refclk1_frequency">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_mode">
+   <type>java.lang.String</type>
+   <value>Automatic Switchover</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_switchover_delay">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_active_clk">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_clk_bad">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="refclk1_frequency">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_loss_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_manu_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_auto_clk_sw_en">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_1_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clk_sw_dly">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_cascade_outclk_index">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_enable_cascade_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="pll_clkin_0_src">
+   <type>java.lang.String</type>
+   <value>clk_0</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gui_pll_cascading_mode">
+   <type>java.lang.String</type>
+   <value>Create an adjpllin signal to connect with an upstream PLL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="refclk" kind="clock_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>refclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="outclk0" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>31099998</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk1" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>25176188</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk2" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>17821346</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="outclk3" kind="clock_source" version="17.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>8860892</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>outclk_3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <connection
+   name="pll_0.outclk0/pll_1.refclk"
+   kind="clock"
+   version="17.1"
+   start="pll_0.outclk0"
+   end="pll_1.refclk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>pll_0</startModule>
+  <startConnectionPoint>outclk0</startConnectionPoint>
+  <endModule>pll_1</endModule>
+  <endConnectionPoint>refclk</endConnectionPoint>
+ </connection>
+ <connection
+   name="pll_0.outclk0/pll_2.refclk"
+   kind="clock"
+   version="17.1"
+   start="pll_0.outclk0"
+   end="pll_2.refclk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>pll_0</startModule>
+  <startConnectionPoint>outclk0</startConnectionPoint>
+  <endModule>pll_2</endModule>
+  <endConnectionPoint>refclk</endConnectionPoint>
+ </connection>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Clock Source</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Output</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>altera_pll</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Altera PLL</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>17</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>17.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>clock</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Clock Connection</displayName>
+  <version>17.1</version>
+ </plugin>
+ <reportVersion>17.1 593</reportVersion>
+ <uniqueIdentifier>005056C000080000016799A08545</uniqueIdentifier>
+</EnsembleReport>
diff --git a/common/pll/synthesis/pll.qip b/common/pll/synthesis/pll.qip
new file mode 100644
index 0000000..8ec8823
--- /dev/null
+++ b/common/pll/synthesis/pll.qip
@@ -0,0 +1,987 @@
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "pll" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../pll.sopcinfo"]
+set_global_assignment -entity "pll" -library "pll" -name SLD_INFO "QSYS_NAME pll HAS_SOPCINFO 1 GENERATION_ID 1544470692"
+set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../pll.cmp"]
+set_global_assignment -library "pll" -name SLD_FILE [file join $::quartus(qip_path) "pll.debuginfo"]
+set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "../../pll.qsys"]
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "cGxs"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU0NDQ3MDY5Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_PARAMETER "QVVUT19QTExfMF9SRUZDTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8y"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MzEuMQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTAy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MzYuMDAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjUuMTc1::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTI2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MzEuNTAwMDAwIE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTcuNzM0NDc1::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTc4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MjUuNTY4NjI3IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTY4MTA3MDM2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzU4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::OC44NjcyMzc=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MzEuMDk5OTk4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjUuMTc2MTg4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTcuODIxMzQ2IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::OC44NjA4OTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Niw2LDEsMSxmYWxzZSxmYWxzZSxmYWxzZSxmYWxzZSwyNiwyNSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMyLDMxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsNDUsNDQsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw5MCw4OSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDEsMzAsMjAwMCwxNTg2LjA5OTgwMSBNSHosMTY4MTA3MDM2NixnY2xrLGdsYixmYl8xLHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8x"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MjU2LjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MjU2LjAgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTYuNzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NDA2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjguMzc1::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::ODEy::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTQuMTg3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTYyNA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzI0OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::OTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NjQ5Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::Ny4wOTM3NQ==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::My41NDY4NzU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTYuNzQ4NzY4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjguMzc0Mzg0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTQuMTg3MTkyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::Ny4wOTM1OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::My41NDY3OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NDUsNDUsMTUsMTQsZmFsc2UsZmFsc2UsZmFsc2UsdHJ1ZSw3LDcsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTQsMTQsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMjgsMjgsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNTYsNTYsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTEyLDExMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDc5NC40ODI3NTggTUh6LDEsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_NAME "cGxsX3BsbF8w"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNTRUJBNlUyM0k3::ZGV2aWNl"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::OA==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::OA==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjU2LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MTIwLjAwMDAwMCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NjQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MzIuNTMzMzI0IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NDg=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::OC4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::OTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::NC4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MTky::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::Mi4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MTU0NjE1OTk2Ng==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::Mzg0::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MS4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjU1Ljk5OTg3MiBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTA5LjcxNDI1NyBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NjMuOTk5OTgxIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MzEuOTk5OTg5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MTUuOTk5OTk0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::Ny45OTk5OTYgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::My45OTk5OTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MS45OTk5OTkgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTUgSGkgRGl2aWRlLEMtQ291bnRlci01IExvdyBEaXZpZGUsQy1Db3VudGVyLTUgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci01IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTUgSW5wdXQgU291cmNlLEMtQ291bnRlci01IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTUgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTYgSGkgRGl2aWRlLEMtQ291bnRlci02IExvdyBEaXZpZGUsQy1Db3VudGVyLTYgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci02IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTYgSW5wdXQgU291cmNlLEMtQ291bnRlci02IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTYgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTcgSGkgRGl2aWRlLEMtQ291bnRlci03IExvdyBEaXZpZGUsQy1Db3VudGVyLTcgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci03IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTcgSW5wdXQgU291cmNlLEMtQ291bnRlci03IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTcgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OCw3LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDIsMSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDQsMywxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDYsNiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMiwxMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyNCwyNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw0OCw0OCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw5Niw5NiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxOTIsMTkyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCw3NjcuOTk5NjcxIE1IeiwxNTQ2MTU5OTY2LGdjbGssZ2xiLGZiXzEscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll" -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_2.qip"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_1.qip"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "submodules/pll_pll_0.qip"]
+
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_pll_2" -library "pll" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_pll_1" -library "pll" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_pll_0" -library "pll" -name IP_TOOL_ENV "Qsys"
diff --git a/common/pll/synthesis/pll.vhd b/common/pll/synthesis/pll.vhd
new file mode 100644
index 0000000..f848681
--- /dev/null
+++ b/common/pll/synthesis/pll.vhd
@@ -0,0 +1,119 @@
+-- pll.vhd
+
+-- Generated using ACDS version 17.1 593
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity pll is
+	port (
+		clk_clk           : in  std_logic := '0'; --           clk.clk
+		pll_0_outclk1_clk : out std_logic;        -- pll_0_outclk1.clk
+		pll_0_outclk2_clk : out std_logic;        -- pll_0_outclk2.clk
+		pll_0_outclk3_clk : out std_logic;        -- pll_0_outclk3.clk
+		pll_0_outclk4_clk : out std_logic;        -- pll_0_outclk4.clk
+		pll_0_outclk5_clk : out std_logic;        -- pll_0_outclk5.clk
+		pll_0_outclk6_clk : out std_logic;        -- pll_0_outclk6.clk
+		pll_0_refclk_clk  : in  std_logic := '0'; --  pll_0_refclk.clk
+		pll_0_reset_reset : in  std_logic := '0'; --   pll_0_reset.reset
+		pll_1_outclk0_clk : out std_logic;        -- pll_1_outclk0.clk
+		pll_1_outclk1_clk : out std_logic;        -- pll_1_outclk1.clk
+		pll_1_outclk2_clk : out std_logic;        -- pll_1_outclk2.clk
+		pll_1_outclk3_clk : out std_logic;        -- pll_1_outclk3.clk
+		pll_1_outclk4_clk : out std_logic;        -- pll_1_outclk4.clk
+		pll_1_reset_reset : in  std_logic := '0'; --   pll_1_reset.reset
+		pll_2_outclk0_clk : out std_logic;        -- pll_2_outclk0.clk
+		pll_2_outclk1_clk : out std_logic;        -- pll_2_outclk1.clk
+		pll_2_outclk2_clk : out std_logic;        -- pll_2_outclk2.clk
+		pll_2_outclk3_clk : out std_logic;        -- pll_2_outclk3.clk
+		pll_2_reset_reset : in  std_logic := '0'; --   pll_2_reset.reset
+		reset_reset_n     : in  std_logic := '0'  --         reset.reset_n
+	);
+end entity pll;
+
+architecture rtl of pll is
+	component pll_pll_0 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			outclk_2 : out std_logic;        -- clk
+			outclk_3 : out std_logic;        -- clk
+			outclk_4 : out std_logic;        -- clk
+			outclk_5 : out std_logic;        -- clk
+			outclk_6 : out std_logic;        -- clk
+			outclk_7 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_pll_0;
+
+	component pll_pll_1 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			outclk_2 : out std_logic;        -- clk
+			outclk_3 : out std_logic;        -- clk
+			outclk_4 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_pll_1;
+
+	component pll_pll_2 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			outclk_2 : out std_logic;        -- clk
+			outclk_3 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_pll_2;
+
+	signal pll_0_outclk0_clk : std_logic; -- pll_0:outclk_0 -> [pll_1:refclk, pll_2:refclk]
+
+begin
+
+	pll_0 : component pll_pll_0
+		port map (
+			refclk   => pll_0_refclk_clk,  --  refclk.clk
+			rst      => pll_0_reset_reset, --   reset.reset
+			outclk_0 => pll_0_outclk0_clk, -- outclk0.clk
+			outclk_1 => pll_0_outclk1_clk, -- outclk1.clk
+			outclk_2 => pll_0_outclk2_clk, -- outclk2.clk
+			outclk_3 => pll_0_outclk3_clk, -- outclk3.clk
+			outclk_4 => pll_0_outclk4_clk, -- outclk4.clk
+			outclk_5 => pll_0_outclk5_clk, -- outclk5.clk
+			outclk_6 => pll_0_outclk6_clk, -- outclk6.clk
+			outclk_7 => open,              -- outclk7.clk
+			locked   => open               -- (terminated)
+		);
+
+	pll_1 : component pll_pll_1
+		port map (
+			refclk   => pll_0_outclk0_clk, --  refclk.clk
+			rst      => pll_1_reset_reset, --   reset.reset
+			outclk_0 => pll_1_outclk0_clk, -- outclk0.clk
+			outclk_1 => pll_1_outclk1_clk, -- outclk1.clk
+			outclk_2 => pll_1_outclk2_clk, -- outclk2.clk
+			outclk_3 => pll_1_outclk3_clk, -- outclk3.clk
+			outclk_4 => pll_1_outclk4_clk, -- outclk4.clk
+			locked   => open               -- (terminated)
+		);
+
+	pll_2 : component pll_pll_2
+		port map (
+			refclk   => pll_0_outclk0_clk, --  refclk.clk
+			rst      => pll_2_reset_reset, --   reset.reset
+			outclk_0 => pll_2_outclk0_clk, -- outclk0.clk
+			outclk_1 => pll_2_outclk1_clk, -- outclk1.clk
+			outclk_2 => pll_2_outclk2_clk, -- outclk2.clk
+			outclk_3 => pll_2_outclk3_clk, -- outclk3.clk
+			locked   => open               -- (terminated)
+		);
+
+end architecture rtl; -- of pll
diff --git a/common/pll/synthesis/submodules/pll_pll_0.qip b/common/pll/synthesis/submodules/pll_pll_0.qip
new file mode 100644
index 0000000..d3272ad
--- /dev/null
+++ b/common/pll/synthesis/submodules/pll_pll_0.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
diff --git a/common/pll/synthesis/submodules/pll_pll_0.v b/common/pll/synthesis/submodules/pll_pll_0.v
new file mode 100644
index 0000000..87bc175
--- /dev/null
+++ b/common/pll/synthesis/submodules/pll_pll_0.v
@@ -0,0 +1,108 @@
+`timescale 1ns/10ps
+module  pll_pll_0(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'outclk2'
+	output wire outclk_2,
+
+	// interface 'outclk3'
+	output wire outclk_3,
+
+	// interface 'outclk4'
+	output wire outclk_4,
+
+	// interface 'outclk5'
+	output wire outclk_5,
+
+	// interface 'outclk6'
+	output wire outclk_6,
+
+	// interface 'outclk7'
+	output wire outclk_7,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(8),
+		.output_clock_frequency0("255.999872 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("109.714257 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("63.999981 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("31.999989 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("15.999994 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("7.999996 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("3.999998 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("1.999999 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_7, outclk_6, outclk_5, outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/common/pll/synthesis/submodules/pll_pll_1.qip b/common/pll/synthesis/submodules/pll_pll_1.qip
new file mode 100644
index 0000000..a5ee3a6
--- /dev/null
+++ b/common/pll/synthesis/submodules/pll_pll_1.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
diff --git a/common/pll/synthesis/submodules/pll_pll_1.v b/common/pll/synthesis/submodules/pll_pll_1.v
new file mode 100644
index 0000000..e01e8ad
--- /dev/null
+++ b/common/pll/synthesis/submodules/pll_pll_1.v
@@ -0,0 +1,99 @@
+`timescale 1ns/10ps
+module  pll_pll_1(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'outclk2'
+	output wire outclk_2,
+
+	// interface 'outclk3'
+	output wire outclk_3,
+
+	// interface 'outclk4'
+	output wire outclk_4,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("256.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(5),
+		.output_clock_frequency0("56.748768 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("28.374384 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("14.187192 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("7.093596 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("3.546798 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/common/pll/synthesis/submodules/pll_pll_2.qip b/common/pll/synthesis/submodules/pll_pll_2.qip
new file mode 100644
index 0000000..21d10bf
--- /dev/null
+++ b/common/pll/synthesis/submodules/pll_pll_2.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
diff --git a/common/pll/synthesis/submodules/pll_pll_2.v b/common/pll/synthesis/submodules/pll_pll_2.v
new file mode 100644
index 0000000..222ccad
--- /dev/null
+++ b/common/pll/synthesis/submodules/pll_pll_2.v
@@ -0,0 +1,96 @@
+`timescale 1ns/10ps
+module  pll_pll_2(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'outclk2'
+	output wire outclk_2,
+
+	// interface 'outclk3'
+	output wire outclk_3,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("256.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(4),
+		.output_clock_frequency0("31.099998 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("25.176188 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("17.821346 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("8.860892 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_3, outclk_2, outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/common/spi_master.vhd b/common/spi_master.vhd
new file mode 100644
index 0000000..ce11d46
--- /dev/null
+++ b/common/spi_master.vhd
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+--
+--   FileName:         spi_master.vhd
+--   Dependencies:     none
+--   Design Software:  Quartus II Version 9.0 Build 132 SJ Full Version
+--
+--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY
+--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+--   Version History
+--   Version 1.0 7/23/2010 Scott Larson
+--     Initial Public Release
+--   Version 1.1 4/11/2013 Scott Larson
+--     Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
+--    
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_master IS
+  GENERIC(
+    slaves  : INTEGER := 4;  --number of spi slaves
+    d_width : INTEGER := 2); --data bus width
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+    enable  : IN     STD_LOGIC;                             --initiate transaction
+    cpol    : IN     STD_LOGIC;                             --spi clock polarity
+    cpha    : IN     STD_LOGIC;                             --spi clock phase
+    cont    : IN     STD_LOGIC;                             --continuous mode command
+    clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+    addr    : IN     INTEGER;                               --address of slave
+    tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+    miso    : IN     STD_LOGIC;                             --master in, slave out
+    sclk    : BUFFER STD_LOGIC;                             --spi clock
+    ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+    mosi    : OUT    STD_LOGIC;                             --master out, slave in
+    busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+    rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+END spi_master;
+
+ARCHITECTURE logic OF spi_master IS
+  TYPE machine IS(ready, execute);                           --state machine data type
+  SIGNAL state       : machine;                              --current state
+  SIGNAL slave       : INTEGER;                              --slave selected for current transaction
+  SIGNAL clk_ratio   : INTEGER;                              --current clk_div
+  SIGNAL count       : INTEGER;                              --counter to trigger sclk from system clock
+  SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1;     --count spi clock toggles
+  SIGNAL assert_data : STD_LOGIC;                            --'1' is tx sclk toggle, '0' is rx sclk toggle
+  SIGNAL continue    : STD_LOGIC;                            --flag to continue transaction
+  SIGNAL rx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
+  SIGNAL tx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
+  SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2;         --last rx data bit location
+BEGIN
+  PROCESS(clock, reset_n)
+  BEGIN
+
+    IF(reset_n = '0') THEN        --reset system
+      busy <= '1';                --set busy signal
+      ss_n <= (OTHERS => '1');    --deassert all slave select lines
+      mosi <= '0';                --set master out to high impedance
+      rx_data <= (OTHERS => '0'); --clear receive data port
+      state <= ready;             --go to ready state when reset is exited
+
+    ELSIF(clock'EVENT AND clock = '1') THEN
+      CASE state IS               --state machine
+
+        WHEN ready =>
+          busy <= '0';             --clock out not busy signal
+          ss_n <= (OTHERS => '1'); --set all slave select outputs high
+          mosi <= '0';             --set mosi output high impedance
+          continue <= '0';         --clear continue flag
+
+          --user input to initiate transaction
+          IF(enable = '1') THEN       
+            busy <= '1';             --set busy signal
+            IF(addr < slaves) THEN   --check for valid slave address
+              slave <= addr;         --clock in current slave selection if valid
+            ELSE
+              slave <= 0;            --set to first slave if not valid
+            END IF;
+            IF(clk_div = 0) THEN     --check for valid spi speed
+              clk_ratio <= 1;        --set to maximum speed if zero
+              count <= 1;            --initiate system-to-spi clock counter
+            ELSE
+              clk_ratio <= clk_div;  --set to input selection if valid
+              count <= clk_div;      --initiate system-to-spi clock counter
+            END IF;
+            sclk <= cpol;            --set spi clock polarity
+            assert_data <= NOT cpha; --set spi clock phase
+            tx_buffer <= tx_data;    --clock in data for transmit into buffer
+            clk_toggles <= 0;        --initiate clock toggle counter
+            last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
+            state <= execute;        --proceed to execute state
+          ELSE
+            state <= ready;          --remain in ready state
+          END IF;
+
+        WHEN execute =>
+          busy <= '1';        --set busy signal
+          ss_n(slave) <= '0'; --set proper slave select output
+          
+          --system clock to sclk ratio is met
+          IF(count = clk_ratio) THEN        
+            count <= 1;                     --reset system-to-spi clock counter
+            assert_data <= NOT assert_data; --switch transmit/receive indicator
+            IF(clk_toggles = d_width*2 + 1) THEN
+              clk_toggles <= 0;               --reset spi clock toggles counter
+            ELSE
+              clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
+            END IF;
+            
+            --spi clock toggle needed
+            IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN 
+              sclk <= NOT sclk; --toggle spi clock
+            END IF;
+            
+            --receive spi clock toggle
+            IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN 
+              rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
+            END IF;
+            
+            --transmit spi clock toggle
+            IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN 
+              mosi <= tx_buffer(d_width-1);                     --clock out data bit
+              tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
+            END IF;
+            
+            --last data receive, but continue
+            IF(clk_toggles = last_bit_rx AND cont = '1') THEN 
+              tx_buffer <= tx_data;                       --reload transmit buffer
+              clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
+              continue <= '1';                            --set continue flag
+            END IF;
+            
+            --normal end of transaction, but continue
+            IF(continue = '1') THEN  
+              continue <= '0';      --clear continue flag
+              busy <= '0';          --clock out signal that first receive data is ready
+              rx_data <= rx_buffer; --clock out received data to output port    
+            END IF;
+            
+            --end of transaction
+            IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN   
+              busy <= '0';             --clock out not busy signal
+              ss_n <= (OTHERS => '1'); --set all slave selects high
+              mosi <= '0';             --set mosi output high impedance
+              rx_data <= rx_buffer;    --clock out received data to output port
+              state <= ready;          --return to ready state
+            ELSE                       --not end of transaction
+              state <= execute;        --remain in execute state
+            END IF;
+          
+          ELSE        --system clock to sclk ratio not met
+            count <= count + 1; --increment counter
+            state <= execute;   --remain in execute state
+          END IF;
+
+      END CASE;
+    END IF;
+  END PROCESS; 
+END logic;
diff --git a/common/submodules/pll_pll_0.qip b/common/submodules/pll_pll_0.qip
new file mode 100644
index 0000000..d3272ad
--- /dev/null
+++ b/common/submodules/pll_pll_0.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
diff --git a/common/submodules/pll_pll_0.v b/common/submodules/pll_pll_0.v
new file mode 100644
index 0000000..87bc175
--- /dev/null
+++ b/common/submodules/pll_pll_0.v
@@ -0,0 +1,108 @@
+`timescale 1ns/10ps
+module  pll_pll_0(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'outclk2'
+	output wire outclk_2,
+
+	// interface 'outclk3'
+	output wire outclk_3,
+
+	// interface 'outclk4'
+	output wire outclk_4,
+
+	// interface 'outclk5'
+	output wire outclk_5,
+
+	// interface 'outclk6'
+	output wire outclk_6,
+
+	// interface 'outclk7'
+	output wire outclk_7,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(8),
+		.output_clock_frequency0("255.999872 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("109.714257 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("63.999981 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("31.999989 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("15.999994 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("7.999996 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("3.999998 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("1.999999 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_7, outclk_6, outclk_5, outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/common/submodules/pll_pll_1.qip b/common/submodules/pll_pll_1.qip
new file mode 100644
index 0000000..a5ee3a6
--- /dev/null
+++ b/common/submodules/pll_pll_1.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
diff --git a/common/submodules/pll_pll_1.v b/common/submodules/pll_pll_1.v
new file mode 100644
index 0000000..e01e8ad
--- /dev/null
+++ b/common/submodules/pll_pll_1.v
@@ -0,0 +1,99 @@
+`timescale 1ns/10ps
+module  pll_pll_1(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'outclk2'
+	output wire outclk_2,
+
+	// interface 'outclk3'
+	output wire outclk_3,
+
+	// interface 'outclk4'
+	output wire outclk_4,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("256.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(5),
+		.output_clock_frequency0("56.748768 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("28.374384 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("14.187192 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("7.093596 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("3.546798 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/common/submodules/pll_pll_2.qip b/common/submodules/pll_pll_2.qip
new file mode 100644
index 0000000..21d10bf
--- /dev/null
+++ b/common/submodules/pll_pll_2.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
diff --git a/common/submodules/pll_pll_2.v b/common/submodules/pll_pll_2.v
new file mode 100644
index 0000000..222ccad
--- /dev/null
+++ b/common/submodules/pll_pll_2.v
@@ -0,0 +1,96 @@
+`timescale 1ns/10ps
+module  pll_pll_2(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'outclk2'
+	output wire outclk_2,
+
+	// interface 'outclk3'
+	output wire outclk_3,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("256.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(4),
+		.output_clock_frequency0("31.099998 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("25.176188 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("17.821346 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("8.860892 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_3, outclk_2, outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/common/sysrom.dump b/common/sysrom.dump
new file mode 100755
index 0000000..3baaba1
Binary files /dev/null and b/common/sysrom.dump differ
diff --git a/common/video.vhd b/common/video.vhd
new file mode 100644
index 0000000..e8a6053
--- /dev/null
+++ b/common/video.vhd
@@ -0,0 +1,1976 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            video.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series Video logic.
+--                  This module fully emulates the Sharp MZ Personal Computer series video display
+--                  logic plus extensions for MZ80K, MZ80C, MZ1200, MZ80A, MZ700, MZ80B & MZ2000.
+--                  
+--                  The display is capable of performing 40x25, 80x25 Mono/Colour display along with
+--                  a Programmable Character Generator, the MZ-80B/2000 Graphics Options and a bit mapped
+--                  320x200/640x200 framebuffer.                                                                                                    
+--
+--                  The design is slightly different to the original Sharp's in that I use a dual
+--                  buffer technique, ie. the original 1K/2K VRAM + ARAM and a pixel mapped displaybuffer.
+--                  During Horizontal/Vertical blanking, the VRAM+ARAM is copied and expanded into the display
+--                  buffer which is then displayed during the next display window. Part of the reasoning
+--                  was to cut down on snow/tearing on the older K/C models (but still provide the
+--                  blanking signals so any original software works) and also allow the option of
+--                  disabling the MZ80A/700 wait states.
+--
+--                  As an addition, I added a graphics framebuffer (320x200, 640x200 8 colours) 
+--                  the interface to which is, at the moment, non-standard, but as I get more details
+--                  on add on cards, I can add mapping layers so this graphics framebuffer can be used
+--                  by customised software. Pixels drawn in the graphics framebuffer can be blended into
+--                  the main display buffer via programmable logic mode (ie. XOR, OR etc).
+--
+--                  The MZ80B/2000 use a standard VRAM + CG for 40/80 character display with a Graphics
+--                  RAM option. These have been added and the output if blended into the display buffer.
+--
+--                  A lot of timing information can be found in the docs/SharpMZ_Notes.xlsx spreadsheet,
+--                  but the main info is:
+--                      MZ80K/C/1200/A (Monochrome)                
+--                      Signal    Start    End    Period    Comment
+--                      64uS 15.625KHz                
+--                      HDISPEN    0    320     40uS    
+--                      HBLANK    318    510     24uS    
+--                      BLNK        318    486     21uS    
+--                      HSYNC    393    438     5.625uS    
+--                 
+--                      16.64mS 60.10Hz                
+--                      VDISPEN    0    200     12.8mS    
+--                      VSYNC    219    223     256uS    
+--                      VBLANK    201    259     3.712mS    not VDISPEN
+--                 
+--                      MZ700 (Colour)                
+--                      Signal    Start    End    Period    Comment
+--                      64.056uS 15.611KHz                
+--                      HDISPEN    0    320     36.088uS    
+--                      HBLANK    320    567     27.968uS    
+--                      BLNK    320    548     25.7126uS    
+--                      HSYNC    400    440       4.567375uS    
+--                 
+--                      16.654mS 50.0374Hz                
+--                      VDISPEN    0    200     12.8112mS    
+--                      VSYNC    212    215     0.19216ms    
+--                      VBLANK    201    311     7.1738mS     not VDISPEN                                                                                                            
+--
+--                  A Look Up Table was added to allow for VGA display resolutions and upscaling as necessary. 
+--                  All video parameters are now stored in the LUT.
+--                                                         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018      - Initial module written.
+--                  August 2018    - Main portions written, including the display buffer.
+--                  September 2018 - Added the graphics framebuffer.
+--                                 - Reworked the transfer VRAM/GRAM -> Framebuffer logic, too conceptual
+--                                   and caused timing issues. 
+--                                   Reworked the Framebuffer display, too conceptual.
+--                                   Added MZ80B/MZ2000 logic.
+--                  October 2018   - Parameterised graphics modes via a LUT.
+--                  November 2018  - Added VGA upscaling.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+use pkgs.functions_pkg.all;
+
+entity video is
+Port (
+    RST_n                    : in  std_logic;                            -- Reset
+
+    -- Different operations modes.
+    CONFIG                   : in  std_logic_vector(CONFIG_WIDTH);
+
+    -- Clocks
+    CLKBUS                   : in  std_logic_vector(CLKBUS_WIDTH);       -- Clock signals created by clkgen module.
+
+    -- CPU Signals
+    T80_A                    : in  std_logic_vector(13 downto 0);        -- CPU Address Bus
+    T80_RD_n                 : in  std_logic;                            -- CPU Read Signal
+    T80_WR_n                 : in  std_logic;                            -- CPU Write Signal
+    T80_MREQ_n               : in  std_logic;                            -- CPU Memory Request
+    T80_BUSACK_n             : in  std_logic;                            -- CPU Bus Acknowledge
+    T80_WAIT_n               : out std_logic;                            -- CPU Wait Request
+    T80_DI                   : in  std_logic_vector(7 downto 0);         -- CPU Data Bus in
+    T80_DO                   : out std_logic_vector(7 downto 0);         -- CPU Data Bus out
+
+    -- Selects.
+    CS_VRAM_n                : in  std_logic;                            -- VRAM Select
+    CS_MEM_G_n               : in  std_logic;                            -- Memory mapped Peripherals Select
+    CS_GRAM_n                : in  std_logic;                            -- Colour GRAM Select
+    CS_GRAM_80B_n            : in  std_logic;                            -- MZ80B GRAM Select
+    CS_IO_GFB_n              : in  std_logic;                            -- Framebuffer register IO Select range.
+    CS_IO_G_n                : in  std_logic;                            -- MZ80B Graphics Options IO Select range.
+
+    -- Video Signals
+    VGATE_n                  : in  std_logic;                            -- Video Output Control
+    INVERSE_n                : in  std_logic;                            -- Invert video display.
+    CONFIG_CHAR80            : in  std_logic;                            -- 40 Char = 0, 80 Char = 1 select.
+    HBLANK                   : out std_logic;                            -- Horizontal Blanking
+    VBLANK                   : out std_logic;                            -- Vertical Blanking
+    HSYNC_n                  : out std_logic;                            -- Horizontal Sync
+    VSYNC_n                  : out std_logic;                            -- Vertical Sync
+    ROUT                     : out std_logic_vector(7 downto 0);         -- Red Output
+    GOUT                     : out std_logic_vector(7 downto 0);         -- Green Output
+    BOUT                     : out std_logic_vector(7 downto 0);         -- Green Output
+
+    -- HPS Interface
+    IOCTL_DOWNLOAD           : in  std_logic;                            -- HPS Downloading to FPGA.
+    IOCTL_UPLOAD             : in  std_logic;                            -- HPS Uploading from FPGA.
+    IOCTL_CLK                : in  std_logic;                            -- HPS I/O Clock..
+    IOCTL_WR                 : in  std_logic;                            -- HPS Write Enable to FPGA.
+    IOCTL_RD                 : in  std_logic;                            -- HPS Read Enable from FPGA.
+    IOCTL_ADDR               : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+    IOCTL_DOUT               : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+    IOCTL_DIN                : out std_logic_vector(31 downto 0)         -- HPS Data to be read into HPS.
+);
+end video;
+
+architecture RTL of video is
+
+type VIDEOLUT is array (integer range 0 to 19, integer range 0 to 28) of integer range 0 to 2000;
+
+-- Constants
+--
+constant MAX_SUBROW          : integer := 8;
+constant MENU_FG_RED         : integer := 15;
+constant MENU_FG_GREEN       : integer := 14;
+constant MENU_FG_BLUE        : integer := 13;
+constant MENU_BG_RED         : integer := 12;
+constant MENU_BG_GREEN       : integer := 11;
+constant MENU_BG_BLUE        : integer := 10;
+
+-- 
+-- Video Timings for different machines and display configuration.
+--
+constant FB_PARAMS           : VIDEOLUT := (
+
+-- Display window variables:-
+--   H_DSP_START,      H_DSP_END,H_DSP_WND_START,  H_DSP_WND_END,    H_MNU_START,      H_MNU_END,    H_HDR_START,      H_HDR_END,    H_FTR_START,      H_FTR_END,    V_DSP_START,      V_DSP_END,V_DSP_WND_START,  V_DSP_WND_END,    V_MNU_START,      V_MNU_END,    V_HDR_START,      V_HDR_END,    V_FTR_START,      V_FTR_END,     H_LINE_END,     V_LINE_END,   MAX_COLUMNS,        H_SYNC_START,                   H_SYNC_END,               V_SYNC_START,                   V_SYNC_END,           H_PX,             V_PX      			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             511,            259,         40,                320  + 73,              320 + 73  + 45,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 0  MZ80B/2000 machines have a monochrome 60Hz display  with scan of 512 x 260 for a 320x200 viewable area in 40Char mode.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1023,            259,         80,                640  + 146,             640 + 146 + 90,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 1  MZ80B/2000 machines have a monochrome 60Hz display  with scan of 1024 x 260 for a 640x200 viewable area in 80Char mode.			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             511,            259,         40,                320  + 73,              320 + 73  + 45,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 2  MZ80K/C/1200/A machines have a monochrome 60Hz display  with scan of 512 x 260 for a 320x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1023,            259,         80,                640  + 146,             640 + 146 + 90,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 3  MZ80K/C/1200/A machines with an adapted monochrome 60Hz display  with scan of 1024 x 260 for a 640x200 viewable area.			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             567,            311,         40,                320  + 80,              320 + 80  + 40,                   200 + 45,                 200 + 45 + 3,              0,               0),      -- 4  MZ700 has a colour 50Hz display  with scan of 568 x 320 for a 320x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1134,            311,         80,                640  + 160,             640 + 160 + 80,                   200 + 45,                 200 + 45 + 3,              0,               0),      -- 5  MZ700 has colour 50Hz display  with scan of 1136 x 320 for a 640x200 viewable area.			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             511,            259,         40,                320  + 73,              320 + 73  + 45,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 6  MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display  with scan of 512 x 260 for a 320x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1023,            259,         80,                640  + 146,             640 + 146 + 90,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 7  MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display  with scan of 1024 x 260 for a 640x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            519,         40,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              1,               1),      -- 8  640x480  @ 60Hz timings for 40Char mode monochrome. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            799,            524,         40,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              1,               1),      -- 9  640x480  @ 60Hz timings for 40Char mode monochrome.
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            508,         80,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              0,               1),      -- 10 640x480  @ 60Hz timings for 80Char mode monochrome.
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            799,            524,         80,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              0,               1),      -- 11 640x480  @ 60Hz timings for 80Char mode monochrome.
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            508,         40,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              1,               1),      -- 12 640x480  @ 60Hz timings for 80Char mode colour.
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            799,            524,         40,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              1,               1),      -- 13 640x480  @ 60Hz timings for 40Char mode colour.
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            508,         80,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              0,               1),      -- 14 640x480  @ 60Hz timings for 80Char mode colour.
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            799,            524,         80,                640  + 16,              640 + 16  + 96,                   480 + 10,                 480 + 10 + 2,              0,               1),      -- 15 640x480  @ 60Hz timings for 80Char mode colour.
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            519,         40,                640  + 24,              640 + 24  + 40,                   480 + 9,                  480 +  9 + 2,              1,               1),      -- 16 640x480  @ 72Hz timings for 40Char mode monochrome. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            519,         80,                640  + 24,              640 + 24  + 40,                   480 + 9,                  480 +  9 + 2,              0,               1),      -- 17 640x480  @ 72Hz timings for 80Char mode monochrome. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            519,         40,                640  + 24,              640 + 24  + 40,                   480 + 9,                  480 +  9 + 2,              1,               1),      -- 18 640x480  @ 72Hz timings for 40Char mode colour. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             39,            439,            111,            367,              8,             24,            444,            479,            831,            519,         80,                640  + 24,              640 + 24  + 40,                   480 + 9,                  480 +  9 + 2,              0,               1)       -- 19 640x480  @ 72Hz timings for 80Char mode colour. 			
+);
+
+
+--
+-- Registers
+--
+signal VIDEOMODE             :     integer range 0 to 20;
+signal VIDEOMODE_LAST        :     integer range 0 to 20;
+signal VIDEOMODE_CHANGED     :     std_logic;
+signal MAX_COLUMN            :     integer range 0 to 80;
+signal FB_ADDR               :     std_logic_vector(13 downto 0);        -- Frame buffer actual address
+signal FB_ADDR_STATUS        :     std_logic_vector(11 downto 0);        -- Status display frame buffer actual address
+signal FB_ADDR_MENU          :     std_logic_vector(12 downto 0);        -- Menu display frame buffer actual address
+signal OFFSET_ADDR           :     std_logic_vector(7 downto 0);         -- Display Offset - for MZ1200/80A machines with 2K VRAM
+signal SR_G_DATA             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Green pixels.
+signal SR_R_DATA             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Red pixels.
+signal SR_B_DATA             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Blue pixels.
+signal SR_G_MENU             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Menu pixels.
+signal SR_R_MENU             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Menu pixels.
+signal SR_B_MENU             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Menu pixels.
+signal DISPLAY_DATA          :     std_logic_vector(23 downto 0);
+signal DISPLAY_STATUS        :     std_logic_vector(23 downto 0);
+signal DISPLAY_MENU          :     std_logic_vector(23 downto 0);
+signal XFER_ADDR             :     std_logic_vector(10 downto 0);
+signal XFER_SUB_ADDR         :     std_logic_vector(2 downto 0);
+signal XFER_VRAM_DATA        :     std_logic_vector(15 downto 0);
+signal XFER_GRAM_DATA        :     std_logic_vector(39 downto 0);        -- 3 x 16Kb Colour Graphics + GRAM I (MZ80B) + GRAM II (MZ80B)
+signal XFER_MAPPED_DATA      :     std_logic_vector(23 downto 0);
+signal XFER_WEN              :     std_logic;
+signal XFER_VRAM_ADDR        :     std_logic_vector(10 downto 0);
+signal XFER_DST_ADDR         :     std_logic_vector(13 downto 0);
+signal XFER_CGROM_ADDR       :     std_logic_vector(11 downto 0);
+signal CGROM_DATA            :     std_logic_vector(7 downto 0);         -- Font Data To Display
+signal DISPLAY_INVERT        :     std_logic;                            -- Invert display Mode of MZ80A/1200
+signal H_SHIFT_CNT           :     integer range 0 to 7;
+signal H_MNU_SHIFT_CNT       :     integer range 0 to 7;
+signal H_PX                  :     integer range 0 to 3;                 -- Variable to indicate if horizontal pixels should be multiplied (for conversion to alternate formats).
+signal H_PX_CNT              :     integer range 0 to 3;                 -- Variable to indicate if horizontal pixels should be multiplied (for conversion to alternate formats).
+signal V_PX                  :     integer range 0 to 3;                 -- Variable to indicate if vertical pixels should be multiplied (for conversion to alternate formats).
+signal V_PX_CNT              :     integer range 0 to 3;                 -- Variable to indicate if vertical pixels should be multiplied (for conversion to alternate formats).
+
+--
+-- CPU/Video Access
+--
+signal VRAM_VIDEO_DATA       :     std_logic_vector(7 downto 0);         -- Display data output to CPU.
+signal VRAM_ADDR             :     std_logic_vector(11 downto 0);        -- VRAM Address.
+signal VRAM_DI               :     std_logic_vector(7 downto 0);         -- VRAM Data in.
+signal VRAM_DO               :     std_logic_vector(7 downto 0);         -- VRAM Data out.
+signal VRAM_WEN              :     std_logic;                            -- VRAM Write enable signal.
+signal VRAM_CLK              :     std_logic;                            -- Clock used to access the VRAM (CPU or IOCTL_CLK).
+signal VRAM_CLK_EN           :     std_logic;                            -- Clock enable for VRAM.
+signal GRAM_VIDEO_DATA       :     std_logic_vector(7 downto 0);         -- Graphics display data output to CPU.
+signal GRAM_ADDR             :     std_logic_vector(13 downto 0);        -- Graphics RAM Address.
+signal GRAM_DI_R             :     std_logic_vector(7 downto 0);         -- Graphics Red RAM Data.
+signal GRAM_DI_G             :     std_logic_vector(7 downto 0);         -- Graphics Green RAM Data.
+signal GRAM_DI_B             :     std_logic_vector(7 downto 0);         -- Graphics Blue RAM Data.
+signal GRAM_DI_GI            :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM I for MZ80B
+signal GRAM_DI_GII           :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM II for MZ80B
+signal GRAM_DO_R             :     std_logic_vector(7 downto 0);         -- Graphics Red RAM Data out.
+signal GRAM_DO_G             :     std_logic_vector(7 downto 0);         -- Graphics Green RAM Data out.
+signal GRAM_DO_B             :     std_logic_vector(7 downto 0);         -- Graphics Blue RAM Data out.
+signal GRAM_DO_GI            :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM I Data out for MZ80B.
+signal GRAM_DO_GII           :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM II Data out for MZ80B.
+signal GRAM_WEN_R            :     std_logic;                            -- Graphics Red RAM Write enable signal.
+signal GRAM_WEN_G            :     std_logic;                            -- Graphics Green RAM Write enable signal.
+signal GRAM_WEN_B            :     std_logic;                            -- Graphics Blue RAM Write enable signal.
+signal GRAM_WEN_GI           :     std_logic;                            -- Graphics Option GRAM I Write enable signal for MZ80B.
+signal GRAM_WEN_GII          :     std_logic;                            -- Graphics Option GRAM II Write enable signal for MZ80B.
+signal GRAM_CLK              :     std_logic;                            -- Clock used to access the GRAM (CPU or IOCTL_CLK).
+signal GRAM_CLK_EN           :     std_logic;                            -- Clock enable for GRAM.
+signal GRAM_MODE             :     std_logic_vector(7 downto 0);         -- Programmable mode register to control GRAM operations.
+signal GRAM_R_FILTER         :     std_logic_vector(7 downto 0);         -- Red pixel writer filter.
+signal GRAM_G_FILTER         :     std_logic_vector(7 downto 0);         -- Green pixel writer filter.
+signal GRAM_B_FILTER         :     std_logic_vector(7 downto 0);         -- Blue pixel writer filter.
+signal GRAM_OPT_WRITE        :     std_logic;                            -- Graphics write to GRAMI (0) or GRAMII (1) for MZ80B/MZ2000
+signal GRAM_OPT_OUT1         :     std_logic;                            -- Graphics enable GRAMI output to display
+signal GRAM_OPT_OUT2         :     std_logic;                            -- Graphics enable GRAMII output to display
+signal T80_MA                :     std_logic_vector(11 downto 0);        -- CPU Address Masked according to machine model.
+signal CS_INVERT_n           :     std_logic;                            -- Chip Select to enable Inverse mode.
+signal CS_SCROLL_n           :     std_logic;                            -- Chip Select to perform a hardware scroll.
+signal CS_GRAM_OPT_n         :     std_logic;                            -- Chip Select to write the graphics options for MZ80B/MZ2000.
+signal CS_FB_CTL_n           :     std_logic;                            -- Chip Select to write to the Graphics mode register.
+signal CS_FB_RED_n           :     std_logic;                            -- Chip Select to write to the Red pixel per byte indirect write register.
+signal CS_FB_GREEN_n         :     std_logic;                            -- Chip Select to write to the Green pixel per byte indirect write register.
+signal CS_FB_BLUE_n          :     std_logic;                            -- Chip Select to write to the Blue pixel per byte indirect write register.
+signal CS_PCG_n              :     std_logic;
+signal WAITi_n               :     std_logic;                            -- Wait
+signal WAITii_n              :     std_logic;                            -- Wait(delayed)
+signal VWEN                  :     std_logic;                            -- Write enable to VRAM.
+signal GWEN_R                :     std_logic;                            -- Write enable to Red GRAM.
+signal GWEN_G                :     std_logic;                            -- Write enable to Green GRAM.
+signal GWEN_B                :     std_logic;                            -- Write enable to Blue GRAM.
+signal GWEN_GI               :     std_logic;                            -- Write enable to for GRAMI option on MZ80B/2000.
+signal GWEN_GII              :     std_logic;                            -- Write enable to for GRAMII option on MZ80B/2000.
+--
+-- Internal Signals
+--
+signal H_COUNT               :     unsigned(10 downto 0);                -- Horizontal pixel counter
+signal H_BLANKi              :     std_logic;                            -- Horizontal Blanking
+signal H_SYNC_ni             :     std_logic;                            -- Horizontal Blanking
+signal H_DSP_START           :     integer range 0 to 2047;
+signal H_DSP_END             :     integer range 0 to 2047;
+signal H_DSP_WND_START       :     integer range 0 to 2047;              -- Window within the horizontal display when data is output.
+signal H_DSP_WND_END         :     integer range 0 to 2047;
+signal H_MNU_START           :     integer range 0 to 2047;
+signal H_MNU_END             :     integer range 0 to 2047;
+signal H_HDR_START           :     integer range 0 to 2047;
+signal H_HDR_END             :     integer range 0 to 2047;
+signal H_FTR_START           :     integer range 0 to 2047;
+signal H_FTR_END             :     integer range 0 to 2047;
+signal H_SYNC_START          :     integer range 0 to 2047;
+signal H_SYNC_END            :     integer range 0 to 2047;
+signal H_LINE_END            :     integer range 0 to 2047;
+signal V_COUNT               :     unsigned(10 downto 0);                -- Vertical pixel counter
+signal V_BLANKi              :     std_logic;                            -- Vertical Blanking
+signal V_SYNC_ni             :     std_logic;                            -- Horizontal Blanking
+signal V_DSP_START           :     integer range 0 to 2047;
+signal V_DSP_END             :     integer range 0 to 2047;
+signal V_DSP_WND_START       :     integer range 0 to 2047;              -- Window within the vertical display when data is output.
+signal V_DSP_WND_END         :     integer range 0 to 2047;
+signal V_MNU_START           :     integer range 0 to 2047;
+signal V_MNU_END             :     integer range 0 to 2047;
+signal V_HDR_START           :     integer range 0 to 2047;
+signal V_HDR_END             :     integer range 0 to 2047;
+signal V_FTR_START           :     integer range 0 to 2047;
+signal V_FTR_END             :     integer range 0 to 2047;
+signal V_SYNC_START          :     integer range 0 to 2047;
+signal V_SYNC_END            :     integer range 0 to 2047;
+signal V_LINE_END            :     integer range 0 to 2047;
+signal VRAM_WAIT             :     std_logic;                            -- Horizontal Blanking Memory Access
+--
+-- CG-ROM
+--
+signal CGROM_DO              :     std_logic_vector(7 downto 0);
+signal CGROM_BANK            :     std_logic_vector(3 downto 0);
+--
+-- PCG
+--
+signal CGRAM_DO              :     std_logic_vector(7 downto 0);
+signal CG_ADDR               :     std_logic_vector(11 downto 0);
+signal CGRAM_ADDR            :     std_logic_vector(11 downto 0);
+signal PCG_DATA              :     std_logic_vector(7 downto 0);
+signal CGRAM_DI              :     std_logic_vector(7 downto 0);
+signal CGRAM_WE_n            :     std_logic;
+signal CGRAM_WEN             :     std_logic;
+signal CGRAM_SEL             :     std_logic;
+--
+-- HPS Control.
+--
+signal IOCTL_CS_VRAM_n       :     std_logic;                            -- Chip Select to allow the HPS to access the VRAM.
+signal IOCTL_CS_GRAM_n       :     std_logic;                            -- Chip Select to allow the HPS to access the GRAM.
+signal IOCTL_CS_GRAM_80B_n   :     std_logic;                            -- Chip Select to allow the HPS to access the MZ80B/2000 GRAM option memory.
+signal IOCTL_CS_CGROM_n      :     std_logic;
+signal IOCTL_CS_CGRAM_n      :     std_logic;
+signal IOCTL_CS_STRAM_n      :     std_logic;
+signal IOCTL_CS_MNURAM_n     :     std_logic;
+signal IOCTL_CS_CONFIG_n     :     std_logic;
+signal IOCTL_WEN_VRAM        :     std_logic;                            -- Write Enable to allow the HPS to write to VRAM.
+signal IOCTL_WEN_GRAM_R      :     std_logic;                            -- Write Enable to allow the HPS to write to the Red GRAM.
+signal IOCTL_WEN_GRAM_G      :     std_logic;                            -- Write Enable to allow the HPS to write to the Green GRAM.
+signal IOCTL_WEN_GRAM_B      :     std_logic;                            -- Write Enable to allow the HPS to write to the Blue GRAM.
+signal IOCTL_WEN_GRAM_GI     :     std_logic;                            -- Write Enable to allow the HPS to write to the MZ80B GRAM I Option RAM.
+signal IOCTL_WEN_GRAM_GII    :     std_logic;                            -- Write Enable to allow the HPS to write to the MZ80B GRAM II Option RAM.
+signal IOCTL_WEN_STRAM       :     std_logic;                            -- Write Enable to allow the HPS to write to the Status Frame Buffer RAM for Green.
+signal IOCTL_WEN_MNURAM      :     std_logic;                            -- Write Enable to allow the HPS to write to the Menu Frame Buffer RAM for Green.
+signal IOCTL_WEN_CGROM       :     std_logic;
+signal IOCTL_WEN_CGRAM       :     std_logic;
+signal IOCTL_DIN_VRAM        :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_GRAM        :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_PCG         :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_CGROM       :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_CGRAM       :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_STRAM       :     std_logic_vector(23 downto 0);
+signal IOCTL_DIN_MNURAM      :     std_logic_vector(23 downto 0);
+signal IOCTL_DIN_CONFIG      :     std_logic_vector(15 downto 0);
+
+--
+-- Components
+--
+component dpram
+ generic (
+      init_file          :     string;
+      widthad_a          :     natural;
+      width_a            :     natural;
+      widthad_b          :     natural;
+      width_b            :     natural;
+      outdata_reg_a      :     string := "UNREGISTERED";
+      outdata_reg_b      :     string := "UNREGISTERED"
+  );
+  Port (
+      clock_a            : in  std_logic ;
+      clocken_a          : in  std_logic := '1';
+      address_a          : in  std_logic_vector (widthad_a-1 downto 0);
+      data_a             : in  std_logic_vector (width_a-1 downto 0);
+      wren_a             : in  std_logic;
+      q_a                : out std_logic_vector (width_a-1 downto 0);
+
+      clock_b            : in  std_logic ;
+      clocken_b          : in  std_logic := '1';
+      address_b          : in  std_logic_vector (widthad_b-1 downto 0);
+      data_b             : in  std_logic_vector (width_b-1 downto 0);
+      wren_b             : in  std_logic;
+      q_b                : out std_logic_vector (width_b-1 downto 0)
+);
+end component;
+
+begin
+
+--
+-- Instantiation
+--
+
+-- Video memory as seen by the MZ Series. This is a 1K or 2K or 2K + 2K Attribute RAM
+-- organised as 4K x 8 on the CPU side and 2K x 16 on the display side, top bits are not used for MZ80K/C/1200/A.
+--
+VRAM0 : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => VRAM_CLK,       
+    clocken_a            => VRAM_CLK_EN,
+    address_a            => VRAM_ADDR,      
+    data_a               => VRAM_DI,   
+    wren_a               => VRAM_WEN,       
+    q_a                  => VRAM_DO,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_VRAM_ADDR,
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_VRAM_DATA
+);
+
+-- Graphics frame buffer memory. This is an enhancement and allows for 320x200 or 640x200 pixel display in 8 colours. It matches
+-- the output frame buffer in size, so the contents are blended by a programmable logical operator (ie. OR) with the expanded Video
+-- Ram contents to create the output display.
+--
+GRAMG : dpram -- GREEN
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 8,
+    widthad_b            => 14,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN,
+    address_a            => GRAM_ADDR,
+    data_a               => GRAM_DI_G,
+    wren_a               => GRAM_WEN_G, 
+    q_a                  => GRAM_DO_G,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,   -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(7 downto 0)
+);
+--
+GRAMR : dpram -- RED
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 8,
+    widthad_b            => 14,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN,
+    address_a            => GRAM_ADDR,
+    data_a               => GRAM_DI_R,
+    wren_a               => GRAM_WEN_R, 
+    q_a                  => GRAM_DO_R,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,   -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(15 downto 8)
+);
+--
+GRAMB : dpram -- BLUE
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 8,
+    widthad_b            => 14,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN,
+    address_a            => GRAM_ADDR,
+    data_a               => GRAM_DI_B,
+    wren_a               => GRAM_WEN_B, 
+    q_a                  => GRAM_DO_B,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,   -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(23 downto 16)
+);
+
+-- MZ80B Graphics RAM Option I
+--
+GRAMI : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 13,
+    width_a              => 8,
+    widthad_b            => 13,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN,
+    address_a            => GRAM_ADDR(12 downto 0),
+    data_a               => GRAM_DI_GI,
+    wren_a               => GRAM_WEN_GI, 
+    q_a                  => GRAM_DO_GI,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR(12 downto 0),            -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(31 downto 24)
+);
+
+-- MZ80B Graphics RAM Option II
+--
+GRAMII : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 13,
+    width_a              => 8,
+    widthad_b            => 13,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN,
+    address_a            => GRAM_ADDR(12 downto 0),
+    data_a               => GRAM_DI_GII,
+    wren_a               => GRAM_WEN_GII, 
+    q_a                  => GRAM_DO_GII,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR(12 downto 0),           -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(39 downto 32)
+);
+
+-- Display Buffer Memory, organised in a Row x Col format, where Address = (Row * MAX_COLUMN * 8) + Col,
+-- but in real terms it is a 320x200x3 or 640x200x3 frame buffer.
+--
+FRAMEBUF0 : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 24,
+    widthad_b            => 14,
+    width_b              => 24,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => CLKBUS(CKENVIDEO),
+    address_a            => FB_ADDR,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (DESTINATION).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,
+    data_b               => XFER_MAPPED_DATA,
+    wren_b               => XFER_WEN 
+  --q_b                  =>
+);
+
+-- A small pixel mapped buffer to display status information in the border area of the frame
+-- on VGA scaled output.
+--
+STATUSBUFG : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 12,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => CLKBUS(CKENVIDEO),
+    address_a            => FB_ADDR_STATUS,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_STATUS(7 downto 0),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(11 downto 0),
+    data_b               => IOCTL_DOUT(7 downto 0),
+    wren_b               => IOCTL_WEN_STRAM, 
+    q_b                  => IOCTL_DIN_STRAM(7 downto 0)
+);
+--
+STATUSBUFR : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 12,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => CLKBUS(CKENVIDEO),
+    address_a            => FB_ADDR_STATUS,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_STATUS(15 downto 8),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(11 downto 0),
+    data_b               => IOCTL_DOUT(15 downto 8),
+    wren_b               => IOCTL_WEN_STRAM, 
+    q_b                  => IOCTL_DIN_STRAM(15 downto 8)
+);
+--
+STATUSBUFB : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 12,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => CLKBUS(CKENVIDEO),
+    address_a            => FB_ADDR_STATUS,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_STATUS(23 downto 16),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(11 downto 0),
+    data_b               => IOCTL_DOUT(23 downto 16),
+    wren_b               => IOCTL_WEN_STRAM, 
+    q_b                  => IOCTL_DIN_STRAM(23 downto 16)
+);
+--
+MENUBUFG : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 13,
+    width_a              => 8,
+    widthad_b            => 13,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => CLKBUS(CKENVIDEO),
+    address_a            => FB_ADDR_MENU,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_MENU(7 downto 0),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(12 downto 0),
+    data_b               => IOCTL_DOUT(7 downto 0),
+    wren_b               => IOCTL_WEN_MNURAM,
+    q_b                  => IOCTL_DIN_MNURAM(7 downto 0)
+);
+--
+MENUBUFR : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 13,
+    width_a              => 8,
+    widthad_b            => 13,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => CLKBUS(CKENVIDEO),
+    address_a            => FB_ADDR_MENU,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_MENU(15 downto 8),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(12 downto 0),
+    data_b               => IOCTL_DOUT(15 downto 8),
+    wren_b               => IOCTL_WEN_MNURAM,
+    q_b                  => IOCTL_DIN_MNURAM(15 downto 8)
+);
+--
+MENUBUFB : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 13,
+    width_a              => 8,
+    widthad_b            => 13,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => CLKBUS(CKENVIDEO),
+    address_a            => FB_ADDR_MENU,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_MENU(23 downto 16),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(12 downto 0),
+    data_b               => IOCTL_DOUT(23 downto 16),
+    wren_b               => IOCTL_WEN_MNURAM,
+    q_b                  => IOCTL_DIN_MNURAM(23 downto 16)
+);
+
+-- 0 = MZ80K  CGROM = 2Kbytes -> 0000:07ff
+-- 1 = MZ80C  CGROM = 2Kbytes -> 0800:0fff
+-- 2 = MZ1200 CGROM = 2Kbytes -> 1000:17ff
+-- 3 = MZ80A  CGROM = 2Kbytes -> 1800:1fff
+-- 4 = MZ700  CGROM = 4Kbytes -> 2000:2fff
+--
+CGROM0 : dpram
+GENERIC MAP (
+    init_file            => "./software/mif/combined_cgrom.mif",
+    widthad_a            => 15,
+    width_a              => 8,
+    widthad_b            => 15,
+    width_b              => 8
+) 
+PORT MAP (
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => '1',
+    address_a            => CGROM_BANK & CG_ADDR(10 downto 0),
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => CGROM_DO,
+
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(14 downto 0),
+    data_b               => IOCTL_DOUT(7 downto 0),
+    wren_b               => IOCTL_WEN_CGROM,
+    q_b                  => IOCTL_DIN_CGROM
+);
+
+CGRAM : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 12,
+    width_b              => 8
+) 
+PORT MAP (
+    clock_a              => CLKBUS(CKMASTER), 
+    clocken_a            => '1',
+    address_a            => CG_ADDR(11 downto 0),
+    data_a               => CGRAM_DI,
+    wren_a               => CGRAM_WEN,
+    q_a                  => CGRAM_DO,
+
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(11 downto 0),
+    data_b               => IOCTL_DOUT(7 downto 0),
+    wren_b               => IOCTL_WEN_CGRAM,
+    q_b                  => IOCTL_DIN_CGRAM
+);
+
+-- Clock as maximum system speed to minimise transfer time.
+--
+process( RST_n, CLKBUS(CKMASTER) )
+    variable XFER_CYCLE      : integer range 0 to 10;
+    variable XFER_ENABLED    : std_logic;                            -- Enable transfer of VRAM/GRAM to framebuffer.
+    variable XFER_PAUSE      : std_logic;                            -- Pause transfer of VRAM/GRAM to framebuffer during data display period.
+    variable XFER_SRC_COL    : integer range 0 to 80;
+    variable XFER_DST_SUBROW : integer range 0 to 7;
+begin
+    if RST_n='0' then
+        XFER_VRAM_ADDR   <= (others => '0');
+        XFER_DST_ADDR    <= (others => '0');
+        XFER_CGROM_ADDR  <= (others => '0');
+        XFER_ENABLED     := '0';
+        XFER_PAUSE       := '0';
+        XFER_SRC_COL     := 0;
+        XFER_DST_SUBROW  := 0;
+        XFER_CYCLE       := 0;
+        XFER_WEN         <= '0';
+        XFER_MAPPED_DATA <= (others => '0');
+
+    -- Copy at end of Display based on the highest clock to minimise time,
+    --
+    elsif rising_edge(CLKBUS(CKMASTER)) then
+
+        -- Every time we reach the end of the visible display area we enable copying of the VRAM and GRAM into the
+        -- display framebuffer, ready for the next frame display. This starts to occur a fixed set of rows after 
+        -- they have been displayed, initially only during the hblank period of a row, but the during the full row
+        -- in the vblank period.
+        --
+        if V_COUNT = 0 then
+            XFER_ENABLED   := '1';
+        end if;
+
+        -- During the actual data display, we pause until the start of the hblanking period.
+        --
+        if XFER_WEN = '0' and H_BLANKi = '0' and V_BLANKi = '0' then -- XFER_WEN = '0' and (((V_COUNT >= V_DSP_START and V_COUNT < V_DSP_END) and (H_COUNT >= H_DSP_START and H_COUNT < H_DSP_END)) or (H_COUNT >= H_LINE_END-1)) then
+            XFER_PAUSE      := '1';
+        else
+            XFER_PAUSE      := '0';
+        end if;
+
+        -- If we are in the active transfer window, start transfer.
+        --
+        if XFER_ENABLED = '1' and XFER_PAUSE = '0' then
+
+            -- Once we reach the end of the framebuffer, disable the copying until next frame.
+            --
+            if XFER_DST_ADDR = 16383 then
+                XFER_ENABLED := '0';
+            end if;
+
+            -- Finite state machine to implement read, map and write.
+            case (XFER_CYCLE) is
+
+                when 0 =>
+                    XFER_MAPPED_DATA <= (others => '0');
+                    XFER_CYCLE       := 1;
+
+                -- Get the source character and map via the PCG to a slice of the displayed character.
+                -- Recalculate the destination address based on this loops values.
+                when 1 =>
+                    -- Setup the PCG address based on the read character.
+                    XFER_CGROM_ADDR  <= XFER_VRAM_DATA(15) & XFER_VRAM_DATA(7 downto 0) & std_logic_vector(to_unsigned(XFER_DST_SUBROW, 3));
+                    XFER_CYCLE       := 2;
+
+                --   Graphics mode:- 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR),
+                --                     5 = GRAM Output Enable  0 = active.
+                --                     4 = VRAM Output Enable, 0 = active.
+                --                   3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect),
+                --                   1/0 = Read mode  (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+                --
+                -- Extra cycle for CGROM to latch, use time to decide which mode we are processing.
+                when 2 =>
+                    -- Check to see if VRAM is disabled, if it is, skip.
+                    --
+                    if CONFIG(VRAMDISABLE) = '0' and GRAM_MODE(4) = '0' and (CONFIG(NORMAL) = '1' or CONFIG(NORMAL80) = '1') then
+                        -- Monochrome modes?
+                        XFER_CYCLE := 4;
+
+                    elsif CONFIG(VRAMDISABLE) = '0' and GRAM_MODE(4) = '0' and (CONFIG(COLOUR) = '1' or CONFIG(COLOUR80) = '1') then
+                        -- Colour modes?
+                        XFER_CYCLE := 3;
+
+                    else
+                        -- Disabled or unrecognised mode.
+                        XFER_CYCLE := 5;
+                    end if;
+
+                -- Colour modes?
+                -- Expand and store the slice of the character with colour expansion.
+                --
+                when 3 =>
+                    if CGROM_DATA(7) = '0' then
+                        XFER_MAPPED_DATA(7)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(15)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(23)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(7)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(15)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(23)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(6) = '0' then
+                        XFER_MAPPED_DATA(6)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(14)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(22)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(6)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(14)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(22)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(5) = '0' then
+                        XFER_MAPPED_DATA(5)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(13)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(21)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(5)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(13)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(21)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(4) = '0' then
+                        XFER_MAPPED_DATA(4)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(12)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(20)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(4)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(12)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(20)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(3) = '0' then
+                        XFER_MAPPED_DATA(3)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(11)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(19)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(3)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(11)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(19)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(2) = '0' then
+                        XFER_MAPPED_DATA(2)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(10)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(18)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(2)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(10)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(18)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(1) = '0' then
+                        XFER_MAPPED_DATA(1)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(9)      <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(17)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(1)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(9)      <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(17)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(0) = '0' then
+                        XFER_MAPPED_DATA(0)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(8)      <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(16)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(0)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(8)      <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(16)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    XFER_CYCLE := 6;
+
+                -- Monochrome modes?
+                -- Expand and store the slice of the character.
+                --
+                when 4 =>
+                    if CGROM_DATA(7) = '1' then
+                        XFER_MAPPED_DATA(7)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(15) <= '1';
+                            XFER_MAPPED_DATA(23) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(6) = '1' then
+                        XFER_MAPPED_DATA(6)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(14) <= '1';
+                            XFER_MAPPED_DATA(22) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(5) = '1' then
+                        XFER_MAPPED_DATA(5)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(13) <= '1';
+                            XFER_MAPPED_DATA(21) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(4) = '1' then
+                        XFER_MAPPED_DATA(4)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(12) <= '1';
+                            XFER_MAPPED_DATA(20) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(3) = '1' then
+                        XFER_MAPPED_DATA(3)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(11) <= '1';
+                            XFER_MAPPED_DATA(19) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(2) = '1' then
+                        XFER_MAPPED_DATA(2)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(10) <= '1';
+                            XFER_MAPPED_DATA(18) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(1) = '1' then
+                        XFER_MAPPED_DATA(1)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(9)  <= '1';
+                            XFER_MAPPED_DATA(17) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(0) = '1' then
+                        XFER_MAPPED_DATA(0)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(8)  <= '1';
+                            XFER_MAPPED_DATA(16) <= '1';
+                        end if;
+                    end if;
+                    XFER_CYCLE := 5;
+
+                when 5 =>
+                    -- If invert option selected, invert green.
+                    --
+                    if (CONFIG(MZ_80B) = '1' and INVERSE_n = '0') or (CONFIG(MZ_A) = '1' and DISPLAY_INVERT = '1') then
+                        XFER_MAPPED_DATA(7 downto 0) <= not XFER_MAPPED_DATA(7 downto 0);
+                    end if;
+                    XFER_CYCLE := 6;
+
+                when 6 =>
+                    -- Graphics ram enabled?
+                    --
+                    if CONFIG(GRAMDISABLE) = '0' and GRAM_MODE(5) = '0' then
+                        -- Merge in the graphics data using defined mode.
+                        --
+                        case GRAM_MODE(7 downto 6) is
+                            when "00" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA or   reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                            when "01" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA and  reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                            when "10" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA nand reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                            when "11" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA xor  reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                        end case;
+                    end if;
+                    XFER_CYCLE := 7;
+
+                when 7 =>
+                    -- For MZ80B, if enabled, blend in the graphics memory.
+                    --
+                    if CONFIG(MZ_80B) = '1' and XFER_DST_ADDR < 8192 then
+                        if GRAM_OPT_OUT1 = '1' and GRAM_OPT_OUT2 = '1' then
+                            XFER_MAPPED_DATA(15 downto 8) <= XFER_MAPPED_DATA(15 downto 8) or reverse_vector(XFER_GRAM_DATA(31 downto 24)) or reverse_vector(XFER_GRAM_DATA(39 downto 32));
+                        elsif GRAM_OPT_OUT1 = '1' then
+                            XFER_MAPPED_DATA(15 downto 8) <= XFER_MAPPED_DATA(15 downto 8) or reverse_vector(XFER_GRAM_DATA(31 downto 24));
+                        elsif GRAM_OPT_OUT2 = '1' then
+                            XFER_MAPPED_DATA(15 downto 8) <= XFER_MAPPED_DATA(15 downto 8) or reverse_vector(XFER_GRAM_DATA(39 downto 32));
+                        end if;
+                    end if;
+                    XFER_CYCLE := 8;
+
+                -- Commence write of mapped data.
+                when 8 =>
+                    XFER_WEN   <= '1';
+                    XFER_CYCLE := 9;
+
+                -- Complete write and update address.
+                when 9 =>
+                    -- Write cycle to framebuffer finished.
+                    XFER_WEN   <= '0';
+                    XFER_CYCLE := 10;
+
+                when 10 =>
+                    -- For each source character, we generate 8 lines in the frame buffer. Thus we need to 
+                    -- process the same source row 8 times, each time incrementing the sub-row which is used
+                    -- to extract the next pixel set from the CG. This data is thus written into the destination as:-
+                    -- <Row:0,CGLine:0,0 .. MAX_COLUMN -1> <Row:0,CGLine:1,0.. MAX_COLUMN -1> .. <Row:0,CGLine:7,0.. MAX_COLUMN -1>
+                    -- ..
+                    -- <Row:24,CGLine:0,0 .. MAX_COLUMN -1><Row:24,CGLine:1,0.. MAX_COLUMN -1> .. <Row:24,CGLine:7,0.. MAX_COLUMN -1>
+                    --
+                    -- To achieve this, we keep a note of the column and sub-row, incrementing the source address until end of line
+                    -- then winding it back if we are still rendering the Characters for a given row. 
+                    -- Destination address always increments every clock cycle to take the next pixel set.
+                    --
+                    if XFER_SRC_COL < MAX_COLUMN - 1 then
+                        XFER_SRC_COL        := XFER_SRC_COL + 1;
+                        XFER_VRAM_ADDR      <= XFER_VRAM_ADDR + 1;
+                    else
+                        if XFER_DST_SUBROW < MAX_SUBROW -1 then
+                            XFER_SRC_COL    := 0;
+                            XFER_DST_SUBROW := XFER_DST_SUBROW + 1;
+                            XFER_VRAM_ADDR  <= XFER_VRAM_ADDR - (MAX_COLUMN - 1);
+                        else
+                            XFER_SRC_COL    := 0;
+                            XFER_VRAM_ADDR  <= XFER_VRAM_ADDR + 1;
+                            XFER_DST_SUBROW := 0;
+                        end if;
+                    end if;
+
+                    -- Destination address increments every tick.
+                    --
+                    XFER_DST_ADDR <= XFER_DST_ADDR + 1;
+                    XFER_CYCLE := 0;
+            end case;
+        end if;
+
+        -- On a new cycle, reset the transfer parameters.
+        --
+        if V_COUNT = V_LINE_END and H_COUNT = H_LINE_END - 1 then
+
+            -- Start of display, setup the start of VRAM for display according to machine. 
+            if CONFIG(MZ_A) = '1' then
+                XFER_VRAM_ADDR <= (OFFSET_ADDR & "000");
+            else
+                XFER_VRAM_ADDR   <= (others => '0');
+            end if;
+            XFER_DST_ADDR    <= (others => '0');
+            XFER_CGROM_ADDR  <= (others => '0');
+            XFER_SRC_COL     := 0;
+            XFER_DST_SUBROW  := 0;
+            XFER_CYCLE       := 0;
+            XFER_ENABLED     := '0';
+            XFER_WEN         <= '0';
+            XFER_MAPPED_DATA <= (others => '0');
+        end if;
+    end if;
+end process;
+
+-- Process to generate the video data signals.
+--
+process( RST_n, CLKBUS )
+begin
+    -- On reset, set the basic parameters which hold the video signal generator in reset
+    -- then load up the required parameter set and generate the video signal.
+    --
+    if RST_n = '0' then
+            H_DSP_START                  <= 0;
+            H_DSP_END                    <= 0;
+            H_DSP_WND_START              <= 0;
+            H_DSP_WND_END                <= 0;
+            H_MNU_START                  <= 0;
+            H_MNU_END                    <= 0;
+            H_HDR_START                  <= 0;
+            H_HDR_END                    <= 0;
+            H_FTR_START                  <= 0;
+            H_FTR_END                    <= 0;
+            V_DSP_START                  <= 0;
+            V_DSP_END                    <= 0;
+            V_DSP_WND_START              <= 0;
+            V_DSP_WND_END                <= 0;
+            V_MNU_START                  <= 0;
+            V_MNU_END                    <= 0;
+            V_HDR_START                  <= 0;
+            V_HDR_END                    <= 0;
+            V_FTR_START                  <= 0;
+            V_FTR_END                    <= 0;
+            MAX_COLUMN                   <= 0;
+            H_LINE_END                   <= 0;
+            V_LINE_END                   <= 0;
+            H_COUNT                      <= (others => '0');
+            V_COUNT                      <= (others => '0');
+            H_BLANKi                     <= '1';
+            V_BLANKi                     <= '1';
+            H_SYNC_ni                    <= '1';
+            V_SYNC_ni                    <= '1';
+            H_PX_CNT                     <= 0;
+            V_PX_CNT                     <= 0;
+            H_SHIFT_CNT                  <= 0;
+            H_MNU_SHIFT_CNT              <= 0;
+            VIDEOMODE_LAST               <= 0;
+            VIDEOMODE_CHANGED            <= '1';
+            FB_ADDR                      <= (others => '0');
+            FB_ADDR_STATUS               <= (others => '0');
+            FB_ADDR_MENU                 <= (others => '0');
+
+  --  elsif rising_edge(CLKBUS(CKVIDEO)) then
+    elsif rising_edge(CLKBUS(CKMASTER)) then
+    if CLKBUS(CKENVIDEO) = '1' then
+
+        -- If the video mode changes, reset the variables to the initial state. This occurs
+        -- at the end of a frame to minimise the monitor syncing incorrectly.
+        --
+        VIDEOMODE_LAST                   <= VIDEOMODE;
+        if VIDEOMODE_LAST /= VIDEOMODE then
+            VIDEOMODE_CHANGED            <= '1';
+        end if;
+        if VIDEOMODE_CHANGED = '1' then
+
+            -- Iniitialise control registers.
+            --
+            FB_ADDR                          <= (others => '0');
+            FB_ADDR_STATUS                   <= (others => '0');
+            FB_ADDR_MENU                     <= (others => '0');
+            VIDEOMODE_CHANGED                <= '0';
+
+            -- Load up configuration from the look up table based on video mode.
+            --
+            H_DSP_START                      <= FB_PARAMS(VIDEOMODE, 0);
+            H_DSP_END                        <= FB_PARAMS(VIDEOMODE, 1);
+            H_DSP_WND_START                  <= FB_PARAMS(VIDEOMODE, 2);
+            H_DSP_WND_END                    <= FB_PARAMS(VIDEOMODE, 3);
+            H_MNU_START                      <= FB_PARAMS(VIDEOMODE, 4);
+            H_MNU_END                        <= FB_PARAMS(VIDEOMODE, 5);
+            H_HDR_START                      <= FB_PARAMS(VIDEOMODE, 6);
+            H_HDR_END                        <= FB_PARAMS(VIDEOMODE, 7);
+            H_FTR_START                      <= FB_PARAMS(VIDEOMODE, 8);
+            H_FTR_END                        <= FB_PARAMS(VIDEOMODE, 9);
+            V_DSP_START                      <= FB_PARAMS(VIDEOMODE, 10);
+            V_DSP_END                        <= FB_PARAMS(VIDEOMODE, 11);
+            V_DSP_WND_START                  <= FB_PARAMS(VIDEOMODE, 12);
+            V_DSP_WND_END                    <= FB_PARAMS(VIDEOMODE, 13);
+            V_MNU_START                      <= FB_PARAMS(VIDEOMODE, 14);
+            V_MNU_END                        <= FB_PARAMS(VIDEOMODE, 15);
+            V_HDR_START                      <= FB_PARAMS(VIDEOMODE, 16);
+            V_HDR_END                        <= FB_PARAMS(VIDEOMODE, 17);
+            V_FTR_START                      <= FB_PARAMS(VIDEOMODE, 18);
+            V_FTR_END                        <= FB_PARAMS(VIDEOMODE, 19);
+            H_LINE_END                       <= FB_PARAMS(VIDEOMODE, 20);
+            V_LINE_END                       <= FB_PARAMS(VIDEOMODE, 21);
+            MAX_COLUMN                       <= FB_PARAMS(VIDEOMODE, 22);
+            H_SYNC_START                     <= FB_PARAMS(VIDEOMODE, 23);
+            H_SYNC_END                       <= FB_PARAMS(VIDEOMODE, 24);
+            V_SYNC_START                     <= FB_PARAMS(VIDEOMODE, 25);
+            V_SYNC_END                       <= FB_PARAMS(VIDEOMODE, 26);
+            H_PX                             <= FB_PARAMS(VIDEOMODE, 27);
+            V_PX                             <= FB_PARAMS(VIDEOMODE, 28);
+            --
+            H_COUNT                          <= (others => '0');
+            V_COUNT                          <= (others => '0');
+            H_BLANKi                         <= '1';
+            V_BLANKi                         <= '1';
+            H_SYNC_ni                        <= '1';
+            V_SYNC_ni                        <= '1';
+            H_PX_CNT                         <= 0;
+            V_PX_CNT                         <= 0;
+            H_SHIFT_CNT                      <= 0;
+            H_MNU_SHIFT_CNT                  <= 0;
+
+        else
+
+            -- Activate/deactivate signals according to pixel position.
+            --
+            if H_COUNT =  H_DSP_START     then H_BLANKi  <= '0'; end if;
+            --if H_COUNT =  H_LINE_END      then H_BLANKi  <= '0'; end if;
+            if H_COUNT =  H_DSP_END       then H_BLANKi  <= '1'; end if;
+            if H_COUNT =  H_SYNC_END      then H_SYNC_ni <= '1'; end if;
+            if H_COUNT =  H_SYNC_START    then H_SYNC_ni <= '0'; end if;
+            if V_COUNT =  V_DSP_START     then V_BLANKi  <= '0'; end if;
+            --if V_COUNT =  V_LINE_END      then V_BLANKi  <= '0'; end if;
+            if V_COUNT =  V_DSP_END       then V_BLANKi  <= '1'; end if;
+            if V_COUNT =  V_SYNC_START    then V_SYNC_ni <= '0'; end if;
+            if V_COUNT =  V_SYNC_END      then V_SYNC_ni <= '1'; end if;
+
+            -- If we are in the active visible area, stream the required output based on the various buffers.
+            --
+            if H_COUNT >= H_DSP_START and H_COUNT < H_DSP_END and V_COUNT >= V_DSP_START and V_COUNT < V_DSP_END then
+
+                if (V_COUNT >= V_DSP_WND_START and V_COUNT < V_DSP_WND_END) and (H_COUNT >= H_DSP_WND_START and H_COUNT < H_DSP_WND_END) then
+                    -- Update Horizontal Pixel multiplier.
+                    --
+                    if H_PX_CNT = 0 then
+
+                        H_PX_CNT             <= H_PX;
+                        H_SHIFT_CNT          <= H_SHIFT_CNT - 1;
+
+                        -- Main screen.
+                        --
+                        if H_SHIFT_CNT = 0 then -- and (V_COUNT >= V_DSP_WND_START and V_COUNT < V_DSP_WND_END) and (H_COUNT >= H_DSP_WND_START and H_COUNT < H_DSP_WND_END) then
+
+                            -- During the visible portion of the frame, data is stored in the frame buffer in bytes, 1 bit per pixel x 8 and 3 colors,
+                            -- thus 1 x 8 x 3 or 24 bit. Read out the values into shift registers to be serialised.
+                            --
+                            SR_G_DATA        <= DISPLAY_DATA( 7 downto 0);
+                            SR_R_DATA        <= DISPLAY_DATA(15 downto 8);
+                            SR_B_DATA        <= DISPLAY_DATA(23 downto 16);
+                            FB_ADDR          <= FB_ADDR + 1;
+
+                        else -- H_SHIFT_CNT /= 0 then --and H_COUNT >= H_DSP_START and H_COUNT < H_DSP_END and V_COUNT >= V_DSP_START and V_COUNT < V_DSP_END then
+                            -- During the active display area, if the shift counter is not 0 and the horizontal multiplier is equal to the setting,
+                            -- shift the data in the shift register to display the next pixel.
+                            --
+                            SR_G_DATA        <= SR_G_DATA(6 downto 0) & '0';
+                            SR_R_DATA        <= SR_R_DATA(6 downto 0) & '0';
+                            SR_B_DATA        <= SR_B_DATA(6 downto 0) & '0';
+
+                        end if;
+                    else
+                        H_PX_CNT             <= H_PX_CNT - 1;
+                    end if;
+                else
+                    -- Blank.
+                    --
+                    SR_G_DATA                <= (others => '0');
+                    SR_R_DATA                <= (others => '0');
+                    SR_B_DATA                <= (others => '0');
+                    H_PX_CNT                 <= H_PX;
+                    H_SHIFT_CNT              <= 1;
+                end if;
+
+                -- If the Status areas or the menu is enabled, create a data stream for the status/menu data to be merged with the main data.
+                --
+                if CONFIG(MENUENABLE) = '1' or CONFIG(STATUSENABLE) = '1' then
+
+                    H_MNU_SHIFT_CNT          <= H_MNU_SHIFT_CNT - 1;
+
+                    -- On each reset of the shift counter, load up Menu, Header, Footer or blank data to be serialised.
+                    --
+                    if H_MNU_SHIFT_CNT = 0 then
+
+                        -- OSD Menu
+                        --
+                        if CONFIG(MENUENABLE) = '1'
+                           and
+                           ((V_COUNT >= V_MNU_START and V_COUNT < V_MNU_END) and (H_COUNT >= H_MNU_START and H_COUNT < H_MNU_END)) then
+        
+                            -- Merge the OSD with the underlying screen data.
+                            --
+                            --for i in 0 to 7 loop
+                            --    if DISPLAY_MENU(i) = '1' and DISPLAY_MENU(MENU_FG_GREEN) = '1' then
+                            --        SR_G_MENU(i) <= '1';
+                            --    elsif DISPLAY_MENU(i) = '0' and DISPLAY_MENU(MENU_BG_GREEN) = '1' then
+                            --        SR_G_MENU(i) <= '1';
+                            --    else
+                            --        SR_G_MENU(i) <= '0';
+                            --    end if;
+                            --end loop;
+                            --for i in 0 to 7 loop
+                            --    if DISPLAY_MENU(i) = '1' and DISPLAY_MENU(MENU_FG_RED) = '1' then
+                            --        SR_R_MENU(i) <= '1';
+                            --    elsif DISPLAY_MENU(i) = '0' and DISPLAY_MENU(MENU_BG_RED) = '1' then
+                            --        SR_R_MENU(i) <= '1';
+                            --    else
+                            --        SR_R_MENU(i) <= '0';
+                            --    end if;
+                            --end loop;
+                            --for i in 0 to 7 loop
+                            --    if DISPLAY_MENU(i) = '1' and DISPLAY_MENU(MENU_FG_BLUE) = '1' then
+                            --        SR_B_MENU(i) <= '1';
+                            --    elsif DISPLAY_MENU(i) = '0' and DISPLAY_MENU(MENU_BG_BLUE) = '1' then
+                            --        SR_B_MENU(i) <= '1';
+                            --    else
+                            --        SR_B_MENU(i) <= '0';
+                            --    end if;
+                            --end loop;
+                            SR_G_MENU        <= DISPLAY_MENU( 7 downto 0);
+                            SR_R_MENU        <= DISPLAY_MENU(15 downto 8);
+                            SR_B_MENU        <= DISPLAY_MENU(23 downto 16);
+                            FB_ADDR_MENU     <= FB_ADDR_MENU + 1;
+        
+                        -- Header/Footer
+                        --
+                        elsif CONFIG(STATUSENABLE) = '1'
+                              and
+                              (((H_HDR_START /= H_HDR_END) and ((V_COUNT >= V_HDR_START and V_COUNT < V_HDR_END) and (H_COUNT >= H_HDR_START and H_COUNT < H_HDR_END)))
+                                or
+                               ((H_FTR_START /= H_FTR_END) and ((V_COUNT >= V_FTR_START and V_COUNT < V_FTR_END) and (H_COUNT >= H_FTR_START and H_COUNT < H_FTR_END)))) then
+           
+                            -- During the visible portion of the unused header/footer, read out the status frame buffer, 1 bit per pixel x 8 and 3 colours.
+                            --
+                            SR_G_MENU        <= DISPLAY_STATUS( 7 downto 0);
+                            SR_R_MENU        <= DISPLAY_STATUS(15 downto 8);
+                            SR_B_MENU        <= DISPLAY_STATUS(23 downto 16);
+                            FB_ADDR_STATUS   <= FB_ADDR_STATUS + 1;
+        
+                        -- Blank.
+                        --
+                        else
+                            SR_G_MENU        <= (others => '0');
+                            SR_R_MENU        <= (others => '0');
+                            SR_B_MENU        <= (others => '0');
+                            H_MNU_SHIFT_CNT  <= 0;
+                        end if;
+        
+                    -- Shift on each clock cycle to next active bit if not at start.
+                    --
+                    else 
+                        SR_G_MENU            <= SR_G_MENU(6 downto 0) & '0';
+                        SR_R_MENU            <= SR_R_MENU(6 downto 0) & '0';
+                        SR_B_MENU            <= SR_B_MENU(6 downto 0) & '0';
+                    end if;
+                end if;
+            else
+                H_PX_CNT                     <= 0;
+                H_SHIFT_CNT                  <= 0;
+                H_MNU_SHIFT_CNT              <= 0;
+            end if;
+
+            -- Horizontal/Vertical counters are updated each clock cycle to accurately track pixel/timing.
+            --
+            if H_COUNT = H_LINE_END then
+                H_COUNT                      <= (others => '0');
+                H_PX_CNT                     <= 0;
+
+                -- Update Vertical Pixel multiplier.
+                --
+                if V_PX_CNT = 0 then
+                    V_PX_CNT                 <= V_PX;
+                else
+                    V_PX_CNT                 <= V_PX_CNT - 1;
+                end if;
+
+                -- When we need to repeat a line due to pixel multiplying, wind back the framebuffer address to start of line.
+                --
+                if V_COUNT >= V_DSP_WND_START and V_COUNT < V_DSP_WND_END and V_PX /= 0 and V_PX_CNT > 0 then
+                    FB_ADDR                  <= FB_ADDR - MAX_COLUMN;
+                end if;
+
+                -- For VGA, expand the vertical pixels according to setting.
+                --
+                if CONFIG(MENUENABLE) = '1' and (V_COUNT >= V_MNU_START and V_COUNT < V_MNU_END) and V_PX /= 0 and V_PX_CNT > 0 then
+                    FB_ADDR_MENU             <= FB_ADDR_MENU - 32;
+                end if;
+
+                -- Once we have reached the end of the active vertical display, reset the framebuffer address.
+                --
+                if V_COUNT = V_DSP_END then
+                    FB_ADDR                  <= (others => '0');
+                    FB_ADDR_STATUS           <= (others => '0');
+                    FB_ADDR_MENU             <= (others => '0');
+                end if;
+
+                -- End of vertical line, increment to next or reset to beginning.
+                --
+                if V_COUNT = V_LINE_END then
+                    V_COUNT                  <= (others => '0');
+                    V_PX_CNT                 <= 0;
+                else
+                    V_COUNT                  <= V_COUNT + 1;
+                end if;
+            else
+                H_COUNT                      <= H_COUNT + 1;
+            end if;
+        end if;
+    end if;
+    end if;
+end process;
+
+-- Control Registers
+--
+-- MZ1200/80A: INVERT display, accessed at E014
+--             SCROLL display, accessed at E200 - E2FF, the address determines the offset.
+-- F0-F3 clocks the i8253 gate for MZ80B. (not used in this module)
+-- F4-F7 set ths MZ80B/MZ2000 graphics options. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II.
+--       Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
+--
+-- IO Range for Graphics enhancements is set by the MCTRL DISPLAY2{7:3] register.
+-- x[0|8],<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+-- x[1|9],<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
+-- x[2|A],<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
+-- x[3|B],<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
+-- x[4|C]       switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. This overrides all MZ700 page switching functions.
+-- x[5|D]       switches out the graphics ram and returns to previous state.
+--
+process( RST_n, CLKBUS(CKMASTER) )
+begin
+    if RST_n='0' then
+        DISPLAY_INVERT        <= '0';
+        OFFSET_ADDR           <= (others => '0');
+        GRAM_MODE             <= "00001100";
+        GRAM_R_FILTER         <= (others => '1');
+        GRAM_G_FILTER         <= (others => '1');
+        GRAM_B_FILTER         <= (others => '1');
+        GRAM_OPT_WRITE        <= '0';
+        GRAM_OPT_OUT1         <= '0';
+        GRAM_OPT_OUT2         <= '0';
+
+    elsif rising_edge(CLKBUS(CKMASTER)) then
+
+        if CLKBUS(CKENCPU) = '1' then
+
+            if CS_INVERT_n='0' and T80_RD_n='0' then
+                DISPLAY_INVERT    <= T80_MA(0);
+            end if;
+
+            if CS_SCROLL_n='0' and T80_RD_n='0' then
+                if CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1' then
+                    OFFSET_ADDR   <= (others => '0');
+                else
+                    OFFSET_ADDR   <= T80_A(7 downto 0);
+                end if;
+            end if;
+
+            if CS_FB_CTL_n = '0'   and T80_WR_n = '0' then
+                GRAM_MODE         <= T80_DI;
+            end if;
+
+            if CS_FB_RED_n = '0'   and T80_WR_n = '0' then
+                GRAM_R_FILTER     <= T80_DI;
+            end if;
+
+            if CS_FB_GREEN_n = '0' and T80_WR_n = '0' then
+                GRAM_G_FILTER     <= T80_DI;
+            end if;
+
+            if CS_FB_BLUE_n = '0'  and T80_WR_n = '0' then
+                GRAM_B_FILTER     <= T80_DI;
+            end if;
+
+            if CS_GRAM_OPT_n = '0' and T80_WR_n = '0' then
+                GRAM_OPT_WRITE    <= T80_DI(0);
+                GRAM_OPT_OUT1     <= T80_DI(1);
+                GRAM_OPT_OUT2     <= T80_DI(2);
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Enable Video Wait States - Original design has wait states inserted into the cycle if the CPU accesses the VRAM during display. In the updated design, the VRAM
+-- is copied into a framebuffer during the Vertical Blanking period so no wait states are needed. To keep consistency with the original design (for programs which depend on it),
+-- the wait states can be enabled by configuration.
+--
+process( T80_MREQ_n ) begin
+    if falling_edge(T80_MREQ_n) then
+        VRAM_WAIT <= H_BLANKi;
+    end if;
+end process;
+--
+-- Extend wait by 1 cycle
+process( CLKBUS(CKMASTER) ) begin
+    if rising_edge(CLKBUS(CKMASTER)) then
+        if CLKBUS(CKENCPU) = '1' then
+            WAITii_n       <= WAITi_n;
+        end if;
+    end if;
+end process;
+
+--
+-- PCG Access Registers
+--
+-- E010: PCG_DATA (byte to describe 8-pixel row of a character)
+-- E011: PCG_ADDR (offset in the PCG in 8-pixel row unit) -> up to 256/8 = 32 characters
+-- E012: PCG_CTRL
+--                bit 0-1: character selector -> (PCG_ADDR + 256*(PCG_CTRL&3)) -> address in the range of the upper 128 characters font
+--                bit 2 : font selector -> PCG_CTRL&2 == 0 -> 1st font else 2nd font
+--                bit 3 : select which font for display
+--                bit 4 : use programmable font for display
+--                bit 5 : set programmable upper font -> PCG_CTRL&20 == 0 -> fixed upper 128 characters else programmable upper 128 characters
+--                So if you want to change a character pattern (only doable in the upper 128 characters of a font), you need to:
+--                - set bit 5 to 1 : PCG_CTRL[5] = 1
+--                - set the font to select : PCG_CTRL[2] = font_number
+--                - set the first row address of the character: PCG_ADDR[0..7] = row[0..7] and PCG_CTRL[0..1] = row[8..9]
+--                - set the 8 pixels of the row in PCG_DATA
+--
+process( RST_n, CLKBUS(CKMASTER) ) begin
+    if RST_n = '0' then
+        CGRAM_ADDR                <= (others=>'0');
+        PCG_DATA                  <= (others=>'0');
+        CGRAM_WE_n                <= '1';
+
+    elsif rising_edge(CLKBUS(CKMASTER)) then
+
+        if CLKBUS(CKENCPU) = '1' then
+
+            if CS_PCG_n = '0' and T80_WR_n = '0' then
+                -- Set the PCG Data to program to RAM. 
+                if T80_A(1 downto 0) = "00" then
+                    PCG_DATA                <= T80_DI;
+                end if;
+
+                -- Set the PCG Address in RAM. 
+                if T80_A(1 downto 0) = "01" then
+                    CGRAM_ADDR(7 downto 0)  <= T80_DI;
+                end if;
+
+                -- Set the PCG Control register.
+                if T80_A(1 downto 0) = "10"  then
+                    CGRAM_ADDR(11 downto 8) <= (T80_DI(2) and CONFIG(MZ_A)) & '1' & T80_DI(1 downto 0);
+                    CGRAM_WE_n              <= not T80_DI(4);
+                    CGRAM_SEL               <= T80_DI(5);
+                end if;
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Process to allow the HPS or uC to read the configuration array.
+--
+process( IOCTL_CLK ) begin
+    if rising_edge(IOCTL_CLK) then
+        if IOCTL_ADDR(10) = '1' then
+            IOCTL_DIN_CONFIG <= "00000000000" & std_logic_vector(to_unsigned(VIDEOMODE, 5));
+        else
+            IOCTL_DIN_CONFIG <= std_logic_vector(to_unsigned(FB_PARAMS(to_integer(unsigned(IOCTL_ADDR(4 downto 0))), to_integer(unsigned(IOCTL_ADDR(9 downto 5)))), IOCTL_DIN_CONFIG'length));
+        end if;
+    end if;
+end process;
+
+--
+-- CPU / RAM signals and selects.
+--
+WAITi_n              <= '0'                                          when CS_VRAM_n = '0'          and VRAM_WAIT = '0' and H_BLANKi = '0' and (CONFIG(MZ_A) = '1' or CONFIG(MZ700) = '1')
+                        else '1';
+T80_WAIT_n           <= WAITi_n and WAITii_n                         when CONFIG(VRAMWAIT) = '1'
+                        else '1';
+T80_MA               <= "00" & T80_A(9 downto 0)                     when CONFIG(MZ_KC) = '1'
+                        else
+                        T80_A(11 downto 0);
+-- Program Character Generator RAM. E010 - Write cycle (Read cycle = reset memory swap).
+CS_PCG_n             <= '0'                                          when CS_MEM_G_n = '0'      and T80_A(10 downto 4) = "0000001"
+                        else '1';                                                                   -- D010 -> D01f
+-- Invert display register. E014/E015
+CS_INVERT_n          <= '0'                                          when CS_MEM_G_n = '0'      and CONFIG(MZ_A) = '1'        and T80_MA(11 downto 9) = "000" and T80_MA(4 downto 2) = "101"
+                        else '1';
+-- Scroll display register. E200 - E2FF
+CS_SCROLL_n          <= '0'                                          when CS_MEM_G_n = '0'      and T80_A(11 downto 8)="0010" and CONFIG(MZ_A)='1'
+                        else '1';
+-- MZ80B/MZ2000 Graphics Options Register select. F4-F7
+CS_GRAM_OPT_n        <= '0'                                          when CS_IO_G_n = '0'       and T80_A(1 downto 0) = "00"
+                        else '1';
+-- <block>0,<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR),
+--                                          5 = GRAM Output Enable, 4 = VRAM Output Enable,
+--                                        3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect),
+--                                        1/0 = Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+CS_FB_CTL_n          <= '0'                                          when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "000"
+                        else '1';
+--  01,<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
+CS_FB_RED_n          <= '0'                                          when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "001"
+                        else '1';
+--  02,<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
+CS_FB_GREEN_n        <= '0'                                          when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "010"
+                        else '1';
+--  03,<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
+CS_FB_BLUE_n         <= '0'                                          when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "011"
+                        else '1';
+
+T80_DO               <= VRAM_VIDEO_DATA                              when T80_RD_n = '0'        and CS_VRAM_n = '0'
+                        else
+                        GRAM_VIDEO_DATA                              when T80_RD_n = '0'        and CS_GRAM_n = '0'
+                        else
+                        GRAM_DO_GI                                   when T80_RD_n = '0'        and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '0'
+                        else
+                        GRAM_DO_GII                                  when T80_RD_n = '0'        and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '1'
+                        else
+                        (others=>'0');
+
+VRAM_ADDR            <= T80_MA(10 downto 0) & T80_MA(11)             when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_ADDR(10 downto 0) & IOCTL_ADDR(11);
+VRAM_DI              <= T80_DI                                       when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_DOUT(7 downto 0);
+VWEN                 <= '1'                                          when T80_WR_n='0'          and CS_VRAM_n = '0'
+                        else '0';
+VRAM_WEN             <= VWEN                                         when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_WEN_VRAM;
+VRAM_VIDEO_DATA      <= VRAM_DO                                      when IOCTL_CS_VRAM_n = '1'
+                        else
+                        (others=>'0');
+IOCTL_DIN_VRAM       <= VRAM_DO                                      when IOCTL_CS_VRAM_n = '0'
+                        else
+                        (others=>'0');
+VRAM_CLK             <= CLKBUS(CKMASTER)                             when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_CLK;
+VRAM_CLK_EN          <= CLKBUS(CKENCPU)                              when IOCTL_CS_VRAM_n = '1'
+                        else
+                        '1';
+
+-- CGROM Data to CG RAM, either ROM -> RAM copy or Z80 provides map.
+--
+CGRAM_DI             <= CGROM_DO                                     when CGRAM_SEL = '1'               -- Data from ROM
+                        else
+                        PCG_DATA                                     when CGRAM_SEL = '0'               -- Data from PCG
+                        else (others=>'0');
+CGRAM_WEN            <= not (CGRAM_WE_n or CS_PCG_n) and not T80_WR_n; 
+
+--
+-- Font select
+--
+CGROM_DATA           <= CGROM_DO                                     when CONFIG(PCGRAM)='0'
+                        else
+                        PCG_DATA                                     when CS_PCG_n='0'         and T80_A(1 downto 0)="10" and T80_WR_n='0'
+                        else
+                        CGRAM_DO                                     when CONFIG(PCGRAM)='1'
+                        else (others => '1');
+CG_ADDR              <= CGRAM_ADDR(11 downto 0)                      when CGRAM_WE_n = '0'
+                        else XFER_CGROM_ADDR;
+CGROM_BANK           <= "0000"                                       when CONFIG(MZ80K)  = '1'
+                        else
+                        "0001"                                       when CONFIG(MZ80C)  = '1'
+                        else
+                        "0010"                                       when CONFIG(MZ1200) = '1'
+                        else
+                        "0011"                                       when CONFIG(MZ80A)  = '1'
+                        else
+                        "0100"                                       when CONFIG(MZ700)  = '1'  and XFER_CGROM_ADDR(11) = '0'
+                        else
+                        "0101"                                       when CONFIG(MZ700)  = '1'  and XFER_CGROM_ADDR(11) = '1'
+                        else
+                        "0110"                                       when CONFIG(MZ800)  = '1'  and XFER_CGROM_ADDR(11) = '0'
+                        else
+                        "0111"                                       when CONFIG(MZ800)  = '1'  and XFER_CGROM_ADDR(11) = '1'
+                        else
+                        "1000"                                       when CONFIG(MZ80B)  = '1'
+                        else
+                        "1001"                                       when CONFIG(MZ2000) = '1'
+                        else
+                        "1111";
+
+
+-- As the Graphics RAM is an odd size, 16384 x 3 colour planes, it has to be in 3 seperate 16K blocks to avoid wasting memory (or having it synthesized away),
+-- thus there are 3 sets of signals, 1 per colour.
+--
+GRAM_ADDR            <= T80_A(13 downto 0)                           when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_ADDR(13 downto 0);
+                        -- direct writes when accessing individual pages.
+GRAM_DI_R            <= T80_DI                                       when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "00"
+                        else
+                        T80_DI and GRAM_R_FILTER                     when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        IOCTL_DOUT(7 downto 0)                       when IOCTL_CS_GRAM_n = '0' and IOCTL_ADDR(15 downto 14) = "00"
+                        else
+                        (others=>'0');
+                        -- direct writes when accessing individual pages.
+GRAM_DI_G            <= T80_DI                                       when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "01"
+                        else
+                        T80_DI and GRAM_G_FILTER                     when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        IOCTL_DOUT(7 downto 0)                       when IOCTL_CS_GRAM_n = '0' and IOCTL_ADDR(15 downto 14) = "01"
+                        else
+                        (others=>'0');
+                        -- direct writes when accessing individual pages.
+GRAM_DI_B            <= T80_DI                                       when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "10"
+                        else
+                        T80_DI and GRAM_B_FILTER                     when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        IOCTL_DOUT(7 downto 0)                       when IOCTL_CS_GRAM_n = '0' and IOCTL_ADDR(15 downto 14) = "10"
+                        else
+                        (others=>'0');
+GWEN_R               <= '1'                                          when T80_WR_n = '0' and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "00"
+                        else
+                        '1'                                          when T80_WR_n = '0' and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        '0';
+GRAM_WEN_R           <= GWEN_R                                       when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_R;
+GWEN_G               <= '1'                                          when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "01"
+                        else
+                        '1'                                          when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        '0';
+GRAM_WEN_G           <= GWEN_G                                       when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_G;
+GWEN_B               <= '1'                                          when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "10"
+                        else
+                        '1'                                          when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        '0';
+GRAM_WEN_B           <= GWEN_B                                       when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_B;
+
+GRAM_VIDEO_DATA      <= GRAM_DO_R                                    when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "00"
+                        else
+                        GRAM_DO_G                                    when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "01"
+                        else
+                        GRAM_DO_B                                    when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "10"
+                        else
+                        (others=>'0');
+GRAM_CLK             <= CLKBUS(CKMASTER)                             when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_CLK;
+GRAM_CLK_EN          <= CLKBUS(CKENCPU)                              when IOCTL_CS_GRAM_n = '1'
+                        else
+                        '1';
+
+-- MZ80B/MZ2000 Graphics Option RAM.
+--
+GRAM_DI_GI           <= T80_DI                                       when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_DOUT(7 downto 0)                       when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_ADDR(13) = '0'
+                        else
+                        (others=>'0');
+GRAM_DI_GII          <= T80_DI                                       when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_DOUT(7 downto 0)                       when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_ADDR(13) = '1'
+                        else
+                        (others=>'0');
+GWEN_GI              <= '1'                                          when T80_WR_n = '0' and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '0'
+                        else
+                        '0';
+GRAM_WEN_GI          <= GWEN_GI                                      when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_GI;
+GWEN_GII             <= '1'                                          when T80_WR_n='0'   and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '1'
+                        else
+                        '0';
+GRAM_WEN_GII         <= GWEN_GII                                     when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_GII;
+
+--
+-- HPS Access - match whole address, additional LE but easier to read.
+--
+IOCTL_WEN_VRAM       <= '1'                                          when IOCTL_CS_VRAM_n = '0'       and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_GRAM_R     <= '1'                                          when IOCTL_CS_GRAM_n = '0'       and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "00"
+                        else '0';
+IOCTL_WEN_GRAM_G     <= '1'                                          when IOCTL_CS_GRAM_n = '0'       and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "01"
+                        else '0';
+IOCTL_WEN_GRAM_B     <= '1'                                          when IOCTL_CS_GRAM_n = '0'       and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "10"
+                        else '0';
+IOCTL_WEN_GRAM_GI    <= '1'                                          when IOCTL_CS_GRAM_80B_n = '0'   and IOCTL_WR = '1' and IOCTL_ADDR(13) = '0'
+                        else '0';
+IOCTL_WEN_GRAM_GII   <= '1'                                          when IOCTL_CS_GRAM_80B_n = '0'   and IOCTL_WR = '1' and IOCTL_ADDR(13) = '1'
+                        else '0';
+IOCTL_WEN_CGROM      <= '1'                                          when IOCTL_CS_CGROM_n = '0'      and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_CGRAM      <= '1'                                          when IOCTL_CS_CGRAM_n = '0'      and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_STRAM      <= '1'                                          when IOCTL_CS_STRAM_n = '0'      and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_MNURAM     <= '1'                                          when IOCTL_CS_MNURAM_n = '0'     and IOCTL_WR = '1'
+                        else '0';
+IOCTL_CS_VRAM_n      <= '0'                                          when IOCTL_ADDR(24 downto 12) = "0001100000000"
+                        else '1';
+IOCTL_CS_GRAM_n      <= '0'                                          when IOCTL_ADDR(24 downto 16) = "000110001" and IOCTL_ADDR(15 downto 14) /= "11"
+                        else '1';
+IOCTL_CS_GRAM_80B_n  <= '0'                                          when IOCTL_ADDR(24 downto 14) = "00011000111"
+                        else '1';
+IOCTL_CS_CGROM_n     <= '0'                                          when IOCTL_ADDR(24 downto 17) = "00101000"
+                        else '1';
+IOCTL_CS_CGRAM_n     <= '0'                                          when IOCTL_ADDR(24 downto 17) = "00110000"
+                        else '1';
+IOCTL_CS_STRAM_n     <= '0'                                          when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0000"
+                        else '1';
+IOCTL_CS_MNURAM_n    <= '0'                                          when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0010"
+                        else '1';
+IOCTL_CS_CONFIG_n    <= '0'                                          when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0100"
+                        else '1';
+IOCTL_DIN            <= X"000000" & IOCTL_DIN_VRAM                   when IOCTL_CS_VRAM_n = '0'       and IOCTL_RD = '1'
+                        else
+                        X"000000" & IOCTL_DIN_GRAM                   when IOCTL_CS_GRAM_n = '0'       and IOCTL_RD = '1'
+                        else
+                        X"FF0000" & IOCTL_DIN_CGROM                  when IOCTL_CS_CGROM_n = '0'      and IOCTL_RD = '1'
+                        else
+                        X"000000" & IOCTL_DIN_CGRAM                  when IOCTL_CS_CGRAM_n = '0'      and IOCTL_RD = '1'
+                        else
+                        X"00" & IOCTL_DIN_STRAM(23 downto 0)         when IOCTL_CS_STRAM_n = '0'      and IOCTL_RD = '1' 
+                        else
+                        X"0000" & IOCTL_DIN_MNURAM(15 downto 0)      when IOCTL_CS_MNURAM_n = '0'     and IOCTL_RD = '1'
+                        else
+                        X"0000" & IOCTL_DIN_CONFIG                   when IOCTL_CS_CONFIG_n = '0'     and IOCTL_RD = '1'
+                        else
+                        (others=>'0');                        
+IOCTL_DIN_GRAM       <= GRAM_DO_R                                    when IOCTL_CS_GRAM_n = '0'       and IOCTL_ADDR(15 downto 14) = "00"
+                        else
+                        GRAM_DO_G                                    when IOCTL_CS_GRAM_n = '0'       and IOCTL_ADDR(15 downto 14) = "01"
+                        else
+                        GRAM_DO_B                                    when IOCTL_CS_GRAM_n = '0'       and IOCTL_ADDR(15 downto 14) = "10"
+                        else
+                        GRAM_DO_GI                                   when IOCTL_CS_GRAM_80B_n = '0'   and IOCTL_ADDR(13) = '0'
+                        else
+                        GRAM_DO_GII                                  when IOCTL_CS_GRAM_80B_n = '0'   and IOCTL_ADDR(13) = '1'
+                        else
+                        (others=>'0');
+
+-- Work out the current video mode, which is used to look up the parameters for frame generation.
+--
+VIDEOMODE            <= 0  when CONFIG(VGAMODE) = "11" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '0'
+                        else
+                        1  when CONFIG(VGAMODE) = "11" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '1'
+                        else
+                        2  when CONFIG(VGAMODE) = "11" and CONFIG(NORMAL)   = '1'
+                        else
+                        3  when CONFIG(VGAMODE) = "11" and CONFIG(NORMAL80) = '1'
+                        else
+                        4  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        5  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        6  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR)   = '1'
+                        else
+                        7  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR80) = '1' 
+                        else
+                        8  when CONFIG(VGAMODE) = "00" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '0'
+                        else
+                        10 when CONFIG(VGAMODE) = "00" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '1'
+                        else
+                        9  when CONFIG(VGAMODE) = "01" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '0'
+                        else
+                        11 when CONFIG(VGAMODE) = "01" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '1'
+                        else
+                        8  when CONFIG(VGAMODE) = "00" and CONFIG(NORMAL)   = '1'
+                        else
+                        9  when CONFIG(VGAMODE) = "01" and CONFIG(NORMAL)   = '1'
+                        else
+                        10 when CONFIG(VGAMODE) = "00" and CONFIG(NORMAL80) = '1'
+                        else
+                        11 when CONFIG(VGAMODE) = "01" and CONFIG(NORMAL80) = '1'
+                        else
+                        12 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        13 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        18 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        14 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        15 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        19 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        12 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR)   = '1'
+                        else
+                        13 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR)   = '1'
+                        else
+                        18 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR)   = '1'
+                        else
+                        14 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR80) = '1'
+                        else
+                        15 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR80) = '1'
+                        else
+                        19 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR80) = '1'
+                        else
+                        16 when CONFIG(VGAMODE) = "10" and CONFIG(NORMAL)   = '1'
+                        else
+                        17 when CONFIG(VGAMODE) = "10" and CONFIG(NORMAL80) = '1'
+                        else
+                        2;
+
+    --
+    -- Video Output Signals
+    --
+    VBLANK           <= V_BLANKi;
+    HBLANK           <= H_BLANKi;
+    VSYNC_n          <= V_SYNC_ni;
+    HSYNC_n          <= H_SYNC_ni;
+    ROUT             <= (others => SR_R_DATA(7) or SR_R_MENU(7)) when H_BLANKi='0' or VGATE_n='1'
+                        else
+                        (others => '0');
+    GOUT             <= (others => SR_G_DATA(7) or SR_G_MENU(7)) when H_BLANKi='0' or VGATE_n='1'
+                        else
+                        (others => '0');
+    BOUT             <= (others => SR_B_DATA(7) or SR_B_MENU(7)) when H_BLANKi='0' or VGATE_n='1'
+                        else
+                        (others => '0');
+
+end RTL;
diff --git a/common/video.vhd.sav b/common/video.vhd.sav
new file mode 100644
index 0000000..608e662
--- /dev/null
+++ b/common/video.vhd.sav
@@ -0,0 +1,1981 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            video.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series Video logic.
+--                  This module fully emulates the Sharp MZ Personal Computer series video display
+--                  logic plus extensions for MZ80K, MZ80C, MZ1200, MZ80A, MZ700, MZ80B & MZ2000.
+--                  
+--                  The display is capable of performing 40x25, 80x25 Mono/Colour display along with
+--                  a Programmable Character Generator, the MZ-80B/2000 Graphics Options and a bit mapped
+--                  320x200/640x200 framebuffer.                                                                                                    
+--
+--                  The design is slightly different to the original Sharp's in that I use a dual
+--                  buffer technique, ie. the original 1K/2K VRAM + ARAM and a pixel mapped displaybuffer.
+--                  During Horizontal/Vertical blanking, the VRAM+ARAM is copied and expanded into the display
+--                  buffer which is then displayed during the next display window. Part of the reasoning
+--                  was to cut down on snow/tearing on the older K/C models (but still provide the
+--                  blanking signals so any original software works) and also allow the option of
+--                  disabling the MZ80A/700 wait states.
+--
+--                  As an addition, I added a graphics framebuffer (320x200, 640x200 8 colours) 
+--                  the interface to which is, at the moment, non-standard, but as I get more details
+--                  on add on cards, I can add mapping layers so this graphics framebuffer can be used
+--                  by customised software. Pixels drawn in the graphics framebuffer can be blended into
+--                  the main display buffer via programmable logic mode (ie. XOR, OR etc).
+--
+--                  The MZ80B/2000 use a standard VRAM + CG for 40/80 character display with a Graphics
+--                  RAM option. These have been added and the output if blended into the display buffer.
+--
+--                  A lot of timing information can be found in the docs/SharpMZ_Notes.xlsx spreadsheet,
+--                  but the main info is:
+--                      MZ80K/C/1200/A (Monochrome)                
+--                      Signal    Start    End    Period    Comment
+--                      64uS 15.625KHz                
+--                      HDISPEN    0    320     40uS    
+--                      HBLANK    318    510     24uS    
+--                      BLNK        318    486     21uS    
+--                      HSYNC    393    438     5.625uS    
+--                 
+--                      16.64mS 60.10Hz                
+--                      VDISPEN    0    200     12.8mS    
+--                      VSYNC    219    223     256uS    
+--                      VBLANK    201    259     3.712mS    not VDISPEN
+--                 
+--                      MZ700 (Colour)                
+--                      Signal    Start    End    Period    Comment
+--                      64.056uS 15.611KHz                
+--                      HDISPEN    0    320     36.088uS    
+--                      HBLANK    320    567     27.968uS    
+--                      BLNK    320    548     25.7126uS    
+--                      HSYNC    400    440       4.567375uS    
+--                 
+--                      16.654mS 50.0374Hz                
+--                      VDISPEN    0    200     12.8112mS    
+--                      VSYNC    212    215     0.19216ms    
+--                      VBLANK    201    311     7.1738mS     not VDISPEN                                                                                                            
+--
+--                  A Look Up Table was added to allow for VGA display resolutions and upscaling as necessary. 
+--                  All video parameters are now stored in the LUT.
+--                                                         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018      - Initial module written.
+--                  August 2018    - Main portions written, including the display buffer.
+--                  September 2018 - Added the graphics framebuffer.
+--                                 - Reworked the transfer VRAM/GRAM -> Framebuffer logic, too conceptual
+--                                   and caused timing issues. 
+--                                   Reworked the Framebuffer display, too conceptual.
+--                                   Added MZ80B/MZ2000 logic.
+--                  October 2018   - Parameterised graphics modes via a LUT.
+--                  November 2018  - Added VGA upscaling.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+use pkgs.functions_pkg.all;
+
+entity video is
+Port (
+    RST_n                    : in  std_logic;                            -- Reset
+
+    -- Different operations modes.
+    CONFIG                   : in  std_logic_vector(CONFIG_WIDTH);
+
+    -- Clocks
+    CLKBUS                   : in  std_logic_vector(CLKBUS_WIDTH);       -- Clock signals created by clkgen module.
+
+    -- CPU Signals
+    T80_A                    : in  std_logic_vector(13 downto 0);        -- CPU Address Bus
+    T80_RD_n                 : in  std_logic;                            -- CPU Read Signal
+    T80_WR_n                 : in  std_logic;                            -- CPU Write Signal
+    T80_MREQ_n               : in  std_logic;                            -- CPU Memory Request
+    T80_BUSACK_n             : in  std_logic;                            -- CPU Bus Acknowledge
+    T80_WAIT_n               : out std_logic;                            -- CPU Wait Request
+    T80_DI                   : in  std_logic_vector(7 downto 0);         -- CPU Data Bus in
+    T80_DO                   : out std_logic_vector(7 downto 0);         -- CPU Data Bus out
+
+    -- Selects.
+    CS_VRAM_n                : in  std_logic;                            -- VRAM Select
+    CS_MEM_G_n               : in  std_logic;                            -- Memory mapped Peripherals Select
+    CS_GRAM_n                : in  std_logic;                            -- Colour GRAM Select
+    CS_GRAM_80B_n            : in  std_logic;                            -- MZ80B GRAM Select
+    CS_IO_GFB_n              : in  std_logic;                            -- Framebuffer register IO Select range.
+    CS_IO_G_n                : in  std_logic;                            -- MZ80B Graphics Options IO Select range.
+
+    -- Video Signals
+    VGATE_n                  : in  std_logic;                            -- Video Output Control
+    INVERSE_n                : in  std_logic;                            -- Invert video display.
+    CONFIG_CHAR80            : in  std_logic;                            -- 40 Char = 0, 80 Char = 1 select.
+    HBLANK                   : out std_logic;                            -- Horizontal Blanking
+    VBLANK                   : out std_logic;                            -- Vertical Blanking
+    HSYNC_n                  : out std_logic;                            -- Horizontal Sync
+    VSYNC_n                  : out std_logic;                            -- Vertical Sync
+    ROUT                     : out std_logic_vector(7 downto 0);         -- Red Output
+    GOUT                     : out std_logic_vector(7 downto 0);         -- Green Output
+    BOUT                     : out std_logic_vector(7 downto 0);         -- Green Output
+
+    -- HPS Interface
+    IOCTL_DOWNLOAD           : in  std_logic;                            -- HPS Downloading to FPGA.
+    IOCTL_UPLOAD             : in  std_logic;                            -- HPS Uploading from FPGA.
+    IOCTL_CLK                : in  std_logic;                            -- HPS I/O Clock..
+    IOCTL_WR                 : in  std_logic;                            -- HPS Write Enable to FPGA.
+    IOCTL_RD                 : in  std_logic;                            -- HPS Read Enable from FPGA.
+    IOCTL_ADDR               : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+    IOCTL_DOUT               : in  std_logic_vector(15 downto 0);        -- HPS Data to be written into FPGA.
+    IOCTL_DIN                : out std_logic_vector(15 downto 0)         -- HPS Data to be read into HPS.
+);
+end video;
+
+architecture RTL of video is
+
+type VIDEOLUT is array (integer range 0 to 19, integer range 0 to 29) of integer range 0 to 2000;
+
+-- Constants
+--
+constant MAX_SUBROW          : integer := 8;
+
+-- 
+-- Video Timings for different machines and display configuration.
+--
+constant FB_PARAMS           : VIDEOLUT := (
+
+-- Display window variables:-
+--   H_DSP_START,      H_DSP_END,H_DSP_WND_START,  H_DSP_WND_END,    H_MNU_START,      H_MNU_END,    H_HDR_START,      H_HDR_END,    H_FTR_START,      H_FTR_END,    V_DSP_START,      V_DSP_END,V_DSP_WND_START,  V_DSP_WND_END,    V_MNU_START,      V_MNU_END,    V_HDR_START,      V_HDR_END,    V_FTR_START,      V_FTR_END,     H_LINE_END,     V_LINE_END,   V_XFER_START,    MAX_COLUMNS,        H_SYNC_START,                   H_SYNC_END,               V_SYNC_START,                   V_SYNC_END,           H_PX,             V_PX      			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             511,            259,             10,        40,                320  + 73,              320  + 73  + 45,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 0  MZ80B/2000 machines have a monochrome 60Hz display  with scan of 512 x 260 for a 320x200 viewable area in 40Char mode.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1023,            259,             10,        80,               640  + 146,              640  + 146 + 90,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 1  MZ80B/2000 machines have a monochrome 60Hz display  with scan of 1024 x 260 for a 640x200 viewable area in 80Char mode.			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             511,            259,             10,        40,                320  + 73,              320  + 73  + 45,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 2  MZ80K/C/1200/A machines have a monochrome 60Hz display  with scan of 512 x 260 for a 320x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1023,            259,             10,        80,               640  + 146,              640  + 146 + 90,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 3  MZ80K/C/1200/A machines with an adapted monochrome 60Hz display  with scan of 1024 x 260 for a 640x200 viewable area.			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             567,            311,             10,        40,                320  + 80,              320  + 80  + 40,                   200 + 45,                 200 + 45 + 3,              0,               0),      -- 4  MZ700 has a colour 50Hz display  with scan of 568 x 320 for a 320x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1134,            311,             10,        80,               640  + 160,              640  + 160 + 80,                   200 + 45,                 200 + 45 + 3,              0,               0),      -- 5  MZ700 has colour 50Hz display  with scan of 1136 x 320 for a 640x200 viewable area.			
+(              0,            320,              0,            320,             32,            288,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,             511,            259,             10,        40,                320  + 73,              320  + 73  + 45,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 6  MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display  with scan of 512 x 260 for a 320x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,              0,              0,              0,              0,            200,              0,            200,             36,            164,              0,              0,              0,             0,            1023,            259,             10,        80,               640  + 146,              640  + 146 + 90,                   200 + 19,                 200 + 19 + 4,              0,               0),      -- 7  MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display  with scan of 1024 x 260 for a 640x200 viewable area.			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            847,            508,             10,        40,                 640 + 40,                640 + 40 + 64,                   480 + 1,                  480 + 1 + 3,               1,               1),      -- 8  640x480  @ 85Hz timings for 40Char mode monochrome. 			 "			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            799,            524,             10,        40,                640  + 16,              640  + 16  + 96,                   480 + 10,                 480 + 10 + 2,              1,               1),      -- 9  640x480  @ 60Hz timings for 40Char mode monochrome. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            831,            508,             10,        80,                 640 + 56,                640 + 56 + 56,                   480 + 1,                  480 + 1 + 3,               0,               1),      -- 10 640x480  @ 85Hz timings for 80Char mode monochrome. 			 "			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            799,            524,             10,        80,                640  + 16,              640  + 16  + 64,                   480 + 10,                 480 + 10 + 2,              0,               1),      -- 11 640x480  @ 60Hz timings for 80Char mode monochrome. 			 "			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            831,            508,             10,        40,                 640 + 56,                640 + 56 + 56,                   480 + 1,                  480 + 1 + 3,               1,               1),      -- 12 640x480  @ 85Hz timings for 80Char mode colour. 			 "			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            799,            524,             10,        40,                640  + 16,              640  + 16  + 64,                   480 + 10,                 480 + 10 + 2,              1,               1),      -- 13 640x480  @ 60Hz timings for 40Char mode colour. 			 "			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            831,            508,             10,        80,                 640 + 56,                640 + 56 + 56,                   480 + 1,                  480 + 1 + 3,               0,               1),      -- 14 640x480  @ 85Hz timings for 80Char mode colour. 			 "			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            799,            524,             10,        80,                640  + 16,              640  + 16  + 64,                   480 + 10,                 480 + 10 + 2,              0,               1),      -- 15 640x480  @ 60Hz timings for 80Char mode colour. 			 "			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            831,            519,             10,        40,                 640 + 24,                640 + 24 + 40,                   480 + 9,                  480 + 9 + 2,               1,               1),      -- 16 640x480  @ 75Hz timings for 40Char mode monochrome. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            831,            519,             10,        80,                 640 + 24,                640 + 24 + 40,                   480 + 9,                  480 + 9 + 2,               0,               1),      -- 17 640x480  @ 75Hz timings for 80Char mode monochrome. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            831,            519,             10,        40,                 640 + 24,                640 + 24 + 40,                   480 + 9,                  480 + 9 + 2,               1,               1),      -- 18 640x480  @ 75Hz timings for 40Char mode colour. 			
+(              0,            640,              0,            640,            192,            448,              0,            640,              0,            640,              0,            480,             40,            440,            112,            368,             10,             25,            442,            478,            831,            519,             10,        80,                 640 + 24,                640 + 24 + 40,                   480 + 9,                  480 + 9 + 2,               0,               1)       -- 19 640x480  @ 75Hz timings for 80Char mode colour. 			
+);
+
+
+--
+-- Registers
+--
+signal VIDEOMODE             :     integer range 0 to 20;
+signal VIDEOMODE_LAST        :     integer range 0 to 20;
+signal VIDEOMODE_CHANGED     :     std_logic;
+signal MAX_COLUMN            :     integer range 0 to 80;
+signal FB_ADDR               :     std_logic_vector(13 downto 0);        -- Frame buffer actual address
+signal FB_ADDR_STATUS        :     std_logic_vector(11 downto 0);        -- Status display frame buffer actual address
+signal FB_ADDR_MENU          :     std_logic_vector(11 downto 0);        -- Menu display frame buffer actual address
+signal OFFSET_ADDR           :     std_logic_vector(7 downto 0);         -- Display Offset - for MZ1200/80A machines with 2K VRAM
+signal SR_G_DATA             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Green pixels.
+signal SR_R_DATA             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Red pixels.
+signal SR_B_DATA             :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Blue pixels.
+signal SR_MNU_G_DATA         :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Menu pixels.
+signal SR_MNU_R_DATA         :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Menu pixels.
+signal SR_MNU_B_DATA         :     std_logic_vector(7 downto 0);         -- Shift Register to serialise Menu pixels.
+signal DISPLAY_DATA          :     std_logic_vector(23 downto 0);
+signal DISPLAY_DATA_STATUS   :     std_logic_vector(23 downto 0);
+signal DISPLAY_DATA_MENU     :     std_logic_vector(23 downto 0);
+signal XFER_ADDR             :     std_logic_vector(10 downto 0);
+signal XFER_SUB_ADDR         :     std_logic_vector(2 downto 0);
+signal XFER_VRAM_DATA        :     std_logic_vector(15 downto 0);
+signal XFER_GRAM_DATA        :     std_logic_vector(39 downto 0);        -- 3 x 16Kb Colour Graphics + GRAM I (MZ80B) + GRAM II (MZ80B)
+signal XFER_MAPPED_DATA      :     std_logic_vector(23 downto 0);
+signal XFER_WEN              :     std_logic;
+signal XFER_VRAM_ADDR        :     std_logic_vector(10 downto 0);
+signal XFER_DST_ADDR         :     std_logic_vector(13 downto 0);
+signal XFER_CGROM_ADDR       :     std_logic_vector(11 downto 0);
+signal CGROM_DATA            :     std_logic_vector(7 downto 0);         -- Font Data To Display
+signal DISPLAY_INVERT        :     std_logic;                            -- Invert display Mode of MZ80A/1200
+signal H_SHIFT_CNT           :     integer range 0 to 7;
+signal H_MNU_SHIFT_CNT       :     integer range 0 to 7;
+signal H_PX                  :     integer range 0 to 3;                 -- Variable to indicate if horizontal pixels should be multiplied (for conversion to alternate formats).
+signal H_PX_CNT              :     integer range 0 to 3;                 -- Variable to indicate if horizontal pixels should be multiplied (for conversion to alternate formats).
+signal V_PX                  :     integer range 0 to 3;                 -- Variable to indicate if vertical pixels should be multiplied (for conversion to alternate formats).
+signal V_PX_CNT              :     integer range 0 to 3;                 -- Variable to indicate if vertical pixels should be multiplied (for conversion to alternate formats).
+signal V_XFER_START          :     integer range 0 to 2000;
+
+--
+-- CPU/Video Access
+--
+signal VRAM_VIDEO_DATA       :     std_logic_vector(7 downto 0);         -- Display data output to CPU.
+signal VRAM_ADDR             :     std_logic_vector(11 downto 0);        -- VRAM Address.
+signal VRAM_DI               :     std_logic_vector(7 downto 0);         -- VRAM Data in.
+signal VRAM_DO               :     std_logic_vector(7 downto 0);         -- VRAM Data out.
+signal VRAM_WEN              :     std_logic;                            -- VRAM Write enable signal.
+signal VRAM_CLK              :     std_logic;                            -- Clock used to access the VRAM (CPU or IOCTL_CLK).
+signal VRAM_CLK_EN           :     std_logic;                            -- Clock enable for VRAM.
+signal GRAM_VIDEO_DATA       :     std_logic_vector(7 downto 0);         -- Graphics display data output to CPU.
+signal GRAM_ADDR             :     std_logic_vector(13 downto 0);        -- Graphics RAM Address.
+signal GRAM_DI_R             :     std_logic_vector(7 downto 0);         -- Graphics Red RAM Data.
+signal GRAM_DI_G             :     std_logic_vector(7 downto 0);         -- Graphics Green RAM Data.
+signal GRAM_DI_B             :     std_logic_vector(7 downto 0);         -- Graphics Blue RAM Data.
+signal GRAM_DI_GI            :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM I for MZ80B
+signal GRAM_DI_GII           :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM II for MZ80B
+signal GRAM_DO_R             :     std_logic_vector(7 downto 0);         -- Graphics Red RAM Data out.
+signal GRAM_DO_G             :     std_logic_vector(7 downto 0);         -- Graphics Green RAM Data out.
+signal GRAM_DO_B             :     std_logic_vector(7 downto 0);         -- Graphics Blue RAM Data out.
+signal GRAM_DO_GI            :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM I Data out for MZ80B.
+signal GRAM_DO_GII           :     std_logic_vector(7 downto 0);         -- Graphics Option GRAM II Data out for MZ80B.
+signal GRAM_WEN_R            :     std_logic;                            -- Graphics Red RAM Write enable signal.
+signal GRAM_WEN_G            :     std_logic;                            -- Graphics Green RAM Write enable signal.
+signal GRAM_WEN_B            :     std_logic;                            -- Graphics Blue RAM Write enable signal.
+signal GRAM_WEN_GI           :     std_logic;                            -- Graphics Option GRAM I Write enable signal for MZ80B.
+signal GRAM_WEN_GII          :     std_logic;                            -- Graphics Option GRAM II Write enable signal for MZ80B.
+signal GRAM_CLK              :     std_logic;                            -- Clock used to access the GRAM (CPU or IOCTL_CLK).
+signal GRAM_CLK_EN           :     std_logic;                            -- Clock enable for GRAM.
+signal GRAM_MODE             :     std_logic_vector(7 downto 0);         -- Programmable mode register to control GRAM operations.
+signal GRAM_R_FILTER         :     std_logic_vector(7 downto 0);         -- Red pixel writer filter.
+signal GRAM_G_FILTER         :     std_logic_vector(7 downto 0);         -- Green pixel writer filter.
+signal GRAM_B_FILTER         :     std_logic_vector(7 downto 0);         -- Blue pixel writer filter.
+signal GRAM_OPT_WRITE        :     std_logic;                            -- Graphics write to GRAMI (0) or GRAMII (1) for MZ80B/MZ2000
+signal GRAM_OPT_OUT1         :     std_logic;                            -- Graphics enable GRAMI output to display
+signal GRAM_OPT_OUT2         :     std_logic;                            -- Graphics enable GRAMII output to display
+signal T80_MA                :     std_logic_vector(11 downto 0);        -- CPU Address Masked according to machine model.
+signal CS_INVERT_n           :     std_logic;                            -- Chip Select to enable Inverse mode.
+signal CS_SCROLL_n           :     std_logic;                            -- Chip Select to perform a hardware scroll.
+signal CS_GRAM_OPT_n         :     std_logic;                            -- Chip Select to write the graphics options for MZ80B/MZ2000.
+signal CS_FB_CTL_n           :     std_logic;                            -- Chip Select to write to the Graphics mode register.
+signal CS_FB_RED_n           :     std_logic;                            -- Chip Select to write to the Red pixel per byte indirect write register.
+signal CS_FB_GREEN_n         :     std_logic;                            -- Chip Select to write to the Green pixel per byte indirect write register.
+signal CS_FB_BLUE_n          :     std_logic;                            -- Chip Select to write to the Blue pixel per byte indirect write register.
+signal CS_PCG_n              :     std_logic;
+signal WAITi_n               :     std_logic;                            -- Wait
+signal WAITii_n              :     std_logic;                            -- Wait(delayed)
+signal VWEN                  :     std_logic;                            -- Write enable to VRAM.
+signal GWEN_R                :     std_logic;                            -- Write enable to Red GRAM.
+signal GWEN_G                :     std_logic;                            -- Write enable to Green GRAM.
+signal GWEN_B                :     std_logic;                            -- Write enable to Blue GRAM.
+signal GWEN_GI               :     std_logic;                            -- Write enable to for GRAMI option on MZ80B/2000.
+signal GWEN_GII              :     std_logic;                            -- Write enable to for GRAMII option on MZ80B/2000.
+--
+-- Internal Signals
+--
+signal H_COUNT               :     unsigned(10 downto 0);                -- Horizontal pixel counter
+signal H_BLANKi              :     std_logic;                            -- Horizontal Blanking
+signal H_SYNC_ni             :     std_logic;                            -- Horizontal Blanking
+signal H_DSP_START           :     integer range 0 to 2047;
+signal H_DSP_END             :     integer range 0 to 2047;
+signal H_DSP_WND_START       :     integer range 0 to 2047;              -- Window within the horizontal display when data is output.
+signal H_DSP_WND_END         :     integer range 0 to 2047;
+signal H_MNU_START           :     integer range 0 to 2047;
+signal H_MNU_END             :     integer range 0 to 2047;
+signal H_HDR_START           :     integer range 0 to 2047;
+signal H_HDR_END             :     integer range 0 to 2047;
+signal H_FTR_START           :     integer range 0 to 2047;
+signal H_FTR_END             :     integer range 0 to 2047;
+signal H_SYNC_START          :     integer range 0 to 2047;
+signal H_SYNC_END            :     integer range 0 to 2047;
+signal H_LINE_END            :     integer range 0 to 2047;
+signal V_COUNT               :     unsigned(10 downto 0);                -- Vertical pixel counter
+signal V_BLANKi              :     std_logic;                            -- Vertical Blanking
+signal V_SYNC_ni             :     std_logic;                            -- Horizontal Blanking
+signal V_DSP_START           :     integer range 0 to 2047;
+signal V_DSP_END             :     integer range 0 to 2047;
+signal V_DSP_WND_START       :     integer range 0 to 2047;              -- Window within the vertical display when data is output.
+signal V_DSP_WND_END         :     integer range 0 to 2047;
+signal V_MNU_START           :     integer range 0 to 2047;
+signal V_MNU_END             :     integer range 0 to 2047;
+signal V_HDR_START           :     integer range 0 to 2047;
+signal V_HDR_END             :     integer range 0 to 2047;
+signal V_FTR_START           :     integer range 0 to 2047;
+signal V_FTR_END             :     integer range 0 to 2047;
+signal V_SYNC_START          :     integer range 0 to 2047;
+signal V_SYNC_END            :     integer range 0 to 2047;
+signal V_LINE_END            :     integer range 0 to 2047;
+signal VRAM_WAIT             :     std_logic;                            -- Horizontal Blanking Memory Access
+--
+-- CG-ROM
+--
+signal CGROM_DO              :     std_logic_vector(7 downto 0);
+signal CGROM_BANK            :     std_logic_vector(3 downto 0);
+--
+-- PCG
+--
+signal CGRAM_DO              :     std_logic_vector(7 downto 0);
+signal CG_ADDR               :     std_logic_vector(11 downto 0);
+signal CGRAM_ADDR            :     std_logic_vector(11 downto 0);
+signal PCG_DATA              :     std_logic_vector(7 downto 0);
+signal CGRAM_DI              :     std_logic_vector(7 downto 0);
+signal CGRAM_WE_n            :     std_logic;
+signal CGRAM_WEN             :     std_logic;
+signal CGRAM_SEL             :     std_logic;
+--
+-- HPS Control.
+--
+signal IOCTL_CS_VRAM_n       :     std_logic;                            -- Chip Select to allow the HPS to access the VRAM.
+signal IOCTL_CS_GRAM_n       :     std_logic;                            -- Chip Select to allow the HPS to access the GRAM.
+signal IOCTL_CS_GRAM_80B_n   :     std_logic;                            -- Chip Select to allow the HPS to access the MZ80B/2000 GRAM option memory.
+signal IOCTL_CS_CGROM_n      :     std_logic;
+signal IOCTL_CS_CGRAM_n      :     std_logic;
+signal IOCTL_CS_STRAM_G_n    :     std_logic;
+signal IOCTL_CS_STRAM_R_n    :     std_logic;
+signal IOCTL_CS_STRAM_B_n    :     std_logic;
+signal IOCTL_CS_MNURAM_G_n   :     std_logic;
+signal IOCTL_CS_MNURAM_R_n   :     std_logic;
+signal IOCTL_CS_MNURAM_B_n   :     std_logic;
+signal IOCTL_CS_CONFIG_n     :     std_logic;
+signal IOCTL_WEN_VRAM        :     std_logic;                            -- Write Enable to allow the HPS to write to VRAM.
+signal IOCTL_WEN_GRAM_R      :     std_logic;                            -- Write Enable to allow the HPS to write to the Red GRAM.
+signal IOCTL_WEN_GRAM_G      :     std_logic;                            -- Write Enable to allow the HPS to write to the Green GRAM.
+signal IOCTL_WEN_GRAM_B      :     std_logic;                            -- Write Enable to allow the HPS to write to the Blue GRAM.
+signal IOCTL_WEN_GRAM_GI     :     std_logic;                            -- Write Enable to allow the HPS to write to the MZ80B GRAM I Option RAM.
+signal IOCTL_WEN_GRAM_GII    :     std_logic;                            -- Write Enable to allow the HPS to write to the MZ80B GRAM II Option RAM.
+signal IOCTL_WEN_STRAM_G     :     std_logic;                            -- Write Enable to allow the HPS to write to the Status Frame Buffer RAM for Green.
+signal IOCTL_WEN_STRAM_R     :     std_logic;                            -- Write Enable to allow the HPS to write to the Status Frame Buffer RAM for Red.
+signal IOCTL_WEN_STRAM_B     :     std_logic;                            -- Write Enable to allow the HPS to write to the Status Frame Buffer RAM for Blue.
+signal IOCTL_WEN_MNURAM_G    :     std_logic;                            -- Write Enable to allow the HPS to write to the Menu Frame Buffer RAM for Green.
+signal IOCTL_WEN_MNURAM_R    :     std_logic;                            -- Write Enable to allow the HPS to write to the Menu Frame Buffer RAM for Red.
+signal IOCTL_WEN_MNURAM_B    :     std_logic;                            -- Write Enable to allow the HPS to write to the Menu Frame Buffer RAM for Blue.
+signal IOCTL_WEN_CGROM       :     std_logic;
+signal IOCTL_WEN_CGRAM       :     std_logic;
+signal IOCTL_DIN_VRAM        :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_GRAM        :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_PCG         :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_CGROM       :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_CGRAM       :     std_logic_vector(7 downto 0);
+signal IOCTL_DIN_STRAM_G     :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_STRAM_R     :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_STRAM_B     :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_MNURAM_G    :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_MNURAM_R    :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_MNURAM_B    :     std_logic_vector(15 downto 0);
+signal IOCTL_DIN_CONFIG      :     std_logic_vector(15 downto 0);
+
+--
+-- Components
+--
+component dpram
+ generic (
+      init_file          :     string;
+      widthad_a          :     natural;
+      width_a            :     natural;
+      widthad_b          :     natural;
+      width_b            :     natural;
+      outdata_reg_a      :     string := "UNREGISTERED";
+      outdata_reg_b      :     string := "UNREGISTERED"
+  );
+  Port (
+      clock_a            : in  std_logic ;
+      clocken_a          : in  std_logic := '1';
+      address_a          : in  std_logic_vector (widthad_a-1 downto 0);
+      data_a             : in  std_logic_vector (width_a-1 downto 0);
+      wren_a             : in  std_logic;
+      q_a                : out std_logic_vector (width_a-1 downto 0);
+
+      clock_b            : in  std_logic ;
+      clocken_b          : in  std_logic := '1';
+      address_b          : in  std_logic_vector (widthad_b-1 downto 0);
+      data_b             : in  std_logic_vector (width_b-1 downto 0);
+      wren_b             : in  std_logic;
+      q_b                : out std_logic_vector (width_b-1 downto 0)
+);
+end component;
+
+begin
+
+--
+-- Instantiation
+--
+
+-- Video memory as seen by the MZ Series. This is a 1K or 2K or 2K + 2K Attribute RAM
+-- organised as 4K x 8 on the CPU side and 2K x 16 on the display side, top bits are not used for MZ80K/C/1200/A.
+--
+VRAM0 : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => VRAM_CLK,       
+    clocken_a            => VRAM_CLK_EN, -- '1',
+    address_a            => VRAM_ADDR,      
+    data_a               => VRAM_DI,   
+    wren_a               => VRAM_WEN,       
+    q_a                  => VRAM_DO,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_VRAM_ADDR,
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_VRAM_DATA
+);
+
+-- Graphics frame buffer memory. This is an enhancement and allows for 320x200 or 640x200 pixel display in 8 colours. It matches
+-- the output frame buffer in size, so the contents are blended by a programmable logical operator (ie. OR) with the expanded Video
+-- Ram contents to create the output display.
+--
+GRAMG : dpram -- GREEN
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 8,
+    widthad_b            => 14,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN, --'1',
+    address_a            => GRAM_ADDR,
+    data_a               => GRAM_DI_G,
+    wren_a               => GRAM_WEN_G, 
+    q_a                  => GRAM_DO_G,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,   -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(7 downto 0)
+);
+--
+GRAMR : dpram -- RED
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 8,
+    widthad_b            => 14,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN, --'1',
+    address_a            => GRAM_ADDR,
+    data_a               => GRAM_DI_R,
+    wren_a               => GRAM_WEN_R, 
+    q_a                  => GRAM_DO_R,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,   -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(15 downto 8)
+);
+--
+GRAMB : dpram -- BLUE
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 8,
+    widthad_b            => 14,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN, -- '1',
+    address_a            => GRAM_ADDR,
+    data_a               => GRAM_DI_B,
+    wren_a               => GRAM_WEN_B, 
+    q_a                  => GRAM_DO_B,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,   -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(23 downto 16)
+);
+
+-- MZ80B Graphics RAM Option I
+--
+GRAMI : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 13,
+    width_a              => 8,
+    widthad_b            => 13,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN, -- '1',
+    address_a            => GRAM_ADDR(12 downto 0),
+    data_a               => GRAM_DI_GI,
+    wren_a               => GRAM_WEN_GI, 
+    q_a                  => GRAM_DO_GI,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR(12 downto 0),            -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(31 downto 24)
+);
+
+-- MZ80B Graphics RAM Option II
+--
+GRAMII : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 13,
+    width_a              => 8,
+    widthad_b            => 13,
+    width_b              => 8,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for CPU access.
+    clock_a              => GRAM_CLK,
+    clocken_a            => GRAM_CLK_EN, -- '1',
+    address_a            => GRAM_ADDR(12 downto 0),
+    data_a               => GRAM_DI_GII,
+    wren_a               => GRAM_WEN_GII, 
+    q_a                  => GRAM_DO_GII,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR(12 downto 0),           -- FB Destination address is used as GRAM is on a 1:1 mapping with FB.
+    data_b               => (others => '0'),
+    wren_b               => '0',
+    q_b                  => XFER_GRAM_DATA(39 downto 32)
+);
+
+-- Display Buffer Memory, organised in a Row x Col format, where Address = (Row * MAX_COLUMN * 8) + Col,
+-- but in real terms it is a 320x200x3 or 640x200x3 frame buffer.
+--
+FRAMEBUF0 : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 14,
+    width_a              => 24,
+    widthad_b            => 14,
+    width_b              => 24,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => '1',
+    address_a            => FB_ADDR,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA,
+
+    -- Port B used for VRAM -> DISPLAY BUFFER transfer (DESTINATION).
+    clock_b              => CLKBUS(CKMASTER),
+    clocken_b            => '1',
+    address_b            => XFER_DST_ADDR,
+    data_b               => XFER_MAPPED_DATA,
+    wren_b               => XFER_WEN 
+  --q_b                  =>
+);
+
+-- A small pixel mapped buffer to display status information in the border area of the frame
+-- on VGA scaled output.
+--
+STATUSBUFG : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKVIDEO),
+    clocken_a            => '1',
+    address_a            => FB_ADDR_STATUS,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA_STATUS(7 downto 0),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(10 downto 0),
+    data_b               => IOCTL_DOUT,
+    wren_b               => IOCTL_WEN_STRAM_G, 
+    q_b                  => IOCTL_DIN_STRAM_G
+);
+--
+STATUSBUFR : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKVIDEO),
+    clocken_a            => '1',
+    address_a            => FB_ADDR_STATUS,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA_STATUS(15 downto 8),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(10 downto 0),
+    data_b               => IOCTL_DOUT,
+    wren_b               => IOCTL_WEN_STRAM_R, 
+    q_b                  => IOCTL_DIN_STRAM_R
+);
+--
+STATUSBUFB : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKVIDEO),
+    clocken_a            => '1',
+    address_a            => FB_ADDR_STATUS,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA_STATUS(23 downto 16),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(10 downto 0),
+    data_b               => IOCTL_DOUT,
+    wren_b               => IOCTL_WEN_STRAM_B, 
+    q_b                  => IOCTL_DIN_STRAM_B
+);
+--
+MENUBUFG : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKVIDEO),
+    clocken_a            => '1',
+    address_a            => FB_ADDR_MENU,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA_MENU(7 downto 0),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(10 downto 0),
+    data_b               => IOCTL_DOUT,
+    wren_b               => IOCTL_WEN_MNURAM_G,
+    q_b                  => IOCTL_DIN_MNURAM_G
+);
+--
+MENUBUFR : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKVIDEO),
+    clocken_a            => '1',
+    address_a            => FB_ADDR_MENU,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA_MENU(15 downto 8),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(10 downto 0),
+    data_b               => IOCTL_DOUT,
+    wren_b               => IOCTL_WEN_MNURAM_R,
+    q_b                  => IOCTL_DIN_MNURAM_R
+);
+--
+MENUBUFB : dpram
+GENERIC MAP (
+    init_file            => null,
+    widthad_a            => 12,
+    width_a              => 8,
+    widthad_b            => 11,
+    width_b              => 16,
+    outdata_reg_b        => "UNREGISTERED"
+)
+PORT MAP (
+    -- Port A used for Display output.
+    clock_a              => CLKBUS(CKVIDEO),
+    clocken_a            => '1',
+    address_a            => FB_ADDR_MENU,
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => DISPLAY_DATA_MENU(23 downto 16),
+
+    -- Port B used for IOCTL access.
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(10 downto 0),
+    data_b               => IOCTL_DOUT,
+    wren_b               => IOCTL_WEN_MNURAM_B,
+    q_b                  => IOCTL_DIN_MNURAM_B
+);
+
+-- 0 = MZ80K  CGROM = 2Kbytes -> 0000:07ff
+-- 1 = MZ80C  CGROM = 2Kbytes -> 0800:0fff
+-- 2 = MZ1200 CGROM = 2Kbytes -> 1000:17ff
+-- 3 = MZ80A  CGROM = 2Kbytes -> 1800:1fff
+-- 4 = MZ700  CGROM = 4Kbytes -> 2000:2fff
+--
+CGROM0 : dpram
+GENERIC MAP (
+    init_file            => "./mif/combined_cgrom.mif",
+    widthad_a            => 15,
+    width_a              => 8,
+    widthad_b            => 15,
+    width_b              => 8
+) 
+PORT MAP (
+    clock_a              => CLKBUS(CKMASTER),
+    clocken_a            => '1',
+    address_a            => CGROM_BANK & CG_ADDR(10 downto 0),
+    data_a               => (others => '0'),
+    wren_a               => '0',
+    q_a                  => CGROM_DO,
+
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(14 downto 0),
+    data_b               => IOCTL_DOUT(7 downto 0),
+    wren_b               => IOCTL_WEN_CGROM,
+    q_b                  => IOCTL_DIN_CGROM
+);
+
+CGRAM : dpram
+GENERIC MAP (
+    init_file            => "./mif/combined_cgrom.mif",
+    widthad_a            => 15,
+    width_a              => 8,
+    widthad_b            => 15,
+    width_b              => 8
+) 
+PORT MAP (
+    clock_a              => CLKBUS(CKMASTER), 
+    clocken_a            => '1',
+    address_a            => CGROM_BANK & CG_ADDR(10 downto 0),
+    data_a               => CGRAM_DI,
+    wren_a               => CGRAM_WEN,
+    q_a                  => CGRAM_DO,
+
+    clock_b              => IOCTL_CLK,
+    clocken_b            => '1',
+    address_b            => IOCTL_ADDR(14 downto 0),
+    data_b               => IOCTL_DOUT(7 downto 0),
+    wren_b               => IOCTL_WEN_CGRAM,
+    q_b                  => IOCTL_DIN_CGRAM
+);
+
+-- Clock as maximum system speed to minimise transfer time.
+--
+process( RST_n, CLKBUS(CKMASTER) )
+    variable XFER_CYCLE      : integer range 0 to 10;
+    variable XFER_ENABLED    : std_logic;                            -- Enable transfer of VRAM/GRAM to framebuffer.
+    variable XFER_PAUSE      : std_logic;                            -- Pause transfer of VRAM/GRAM to framebuffer during data display period.
+    variable XFER_SRC_COL    : integer range 0 to 80;
+    variable XFER_DST_SUBROW : integer range 0 to 7;
+begin
+    if RST_n='0' then
+        XFER_VRAM_ADDR   <= (others => '0');
+        XFER_DST_ADDR    <= (others => '0');
+        XFER_CGROM_ADDR  <= (others => '0');
+        XFER_ENABLED     := '0';
+        XFER_PAUSE       := '0';
+        XFER_SRC_COL     := 0;
+        XFER_DST_SUBROW  := 0;
+        XFER_CYCLE       := 0;
+        XFER_WEN         <= '0';
+        XFER_MAPPED_DATA <= (others => '0');
+
+    -- Copy at end of Display based on the highest clock to minimise time,
+    --
+    elsif rising_edge(CLKBUS(CKMASTER)) then
+
+        -- Every time we reach the end of the visible display area we enable copying of the VRAM and GRAM into the
+        -- display framebuffer, ready for the next frame display. This starts to occur a fixed set of rows after 
+        -- they have been displayed, initially only during the hblank period of a row, but the during the full row
+        -- in the vblank period.
+        --
+        if V_COUNT = to_unsigned(V_XFER_START, V_COUNT'length) then
+            XFER_ENABLED   := '1';
+            --XFER_CYCLE     := 0;
+        end if;
+
+        -- During the actual data display, we pause until the start of the hblanking period.
+        --
+        if XFER_WEN = '0' and H_BLANKi = '0' and V_BLANKi = '0' then -- XFER_WEN = '0' and (((V_COUNT >= V_DSP_START and V_COUNT < V_DSP_END) and (H_COUNT >= H_DSP_START and H_COUNT < H_DSP_END)) or (H_COUNT >= H_LINE_END-1)) then
+            XFER_PAUSE      := '1';
+        else
+            XFER_PAUSE      := '0';
+        end if;
+
+        -- If we are in the active transfer window, start transfer.
+        --
+        if XFER_ENABLED = '1' and XFER_PAUSE = '0' then
+
+            -- Once we reach the end of the framebuffer, disable the copying until next frame.
+            --
+            if XFER_DST_ADDR = 16383 then
+                XFER_ENABLED := '0';
+            end if;
+
+            -- Finite state machine to implement read, map and write.
+            case (XFER_CYCLE) is
+
+                when 0 =>
+                    XFER_MAPPED_DATA <= (others => '0');
+                    XFER_CYCLE       := 1;
+
+                -- Get the source character and map via the PCG to a slice of the displayed character.
+                -- Recalculate the destination address based on this loops values.
+                when 1 =>
+                    -- Setup the PCG address based on the read character.
+                    XFER_CGROM_ADDR  <= XFER_VRAM_DATA(15) & XFER_VRAM_DATA(7 downto 0) & std_logic_vector(to_unsigned(XFER_DST_SUBROW, 3));
+                    XFER_CYCLE       := 2;
+
+                --   Graphics mode:- 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR),
+                --                     5 = GRAM Output Enable  0 = active.
+                --                     4 = VRAM Output Enable, 0 = active.
+                --                   3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect),
+                --                   1/0 = Read mode  (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+                --
+                -- Extra cycle for CGROM to latch, use time to decide which mode we are processing.
+                when 2 =>
+                    -- Check to see if VRAM is disabled, if it is, skip.
+                    --
+                    if CONFIG(VRAMDISABLE) = '0' and GRAM_MODE(4) = '0' and (CONFIG(NORMAL) = '1' or CONFIG(NORMAL80) = '1') then
+                        -- Monochrome modes?
+                        XFER_CYCLE := 4;
+
+                    elsif CONFIG(VRAMDISABLE) = '0' and GRAM_MODE(4) = '0' and (CONFIG(COLOUR) = '1' or CONFIG(COLOUR80) = '1') then
+                        -- Colour modes?
+                        XFER_CYCLE := 3;
+
+                    else
+                        -- Disabled or unrecognised mode.
+                        XFER_CYCLE := 5;
+                    end if;
+
+                -- Colour modes?
+                -- Expand and store the slice of the character with colour expansion.
+                --
+                when 3 =>
+                    if CGROM_DATA(7) = '0' then
+                        XFER_MAPPED_DATA(7)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(15)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(23)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(7)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(15)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(23)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(6) = '0' then
+                        XFER_MAPPED_DATA(6)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(14)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(22)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(6)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(14)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(22)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(5) = '0' then
+                        XFER_MAPPED_DATA(5)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(13)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(21)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(5)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(13)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(21)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(4) = '0' then
+                        XFER_MAPPED_DATA(4)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(12)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(20)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(4)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(12)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(20)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(3) = '0' then
+                        XFER_MAPPED_DATA(3)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(11)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(19)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(3)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(11)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(19)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(2) = '0' then
+                        XFER_MAPPED_DATA(2)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(10)     <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(18)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(2)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(10)     <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(18)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(1) = '0' then
+                        XFER_MAPPED_DATA(1)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(9)      <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(17)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(1)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(9)      <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(17)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    if CGROM_DATA(0) = '0' then
+                        XFER_MAPPED_DATA(0)      <= XFER_VRAM_DATA(10);
+                        XFER_MAPPED_DATA(8)      <= XFER_VRAM_DATA(9);
+                        XFER_MAPPED_DATA(16)     <= XFER_VRAM_DATA(8);
+                    else
+                        XFER_MAPPED_DATA(0)      <= XFER_VRAM_DATA(14);
+                        XFER_MAPPED_DATA(8)      <= XFER_VRAM_DATA(13);
+                        XFER_MAPPED_DATA(16)     <= XFER_VRAM_DATA(12);
+                    end if;
+                    XFER_CYCLE := 6;
+
+                -- Monochrome modes?
+                -- Expand and store the slice of the character.
+                --
+                when 4 =>
+                    if CGROM_DATA(7) = '1' then
+                        XFER_MAPPED_DATA(7)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(15) <= '1';
+                            XFER_MAPPED_DATA(23) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(6) = '1' then
+                        XFER_MAPPED_DATA(6)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(14) <= '1';
+                            XFER_MAPPED_DATA(22) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(5) = '1' then
+                        XFER_MAPPED_DATA(5)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(13) <= '1';
+                            XFER_MAPPED_DATA(21) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(4) = '1' then
+                        XFER_MAPPED_DATA(4)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(12) <= '1';
+                            XFER_MAPPED_DATA(20) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(3) = '1' then
+                        XFER_MAPPED_DATA(3)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(11) <= '1';
+                            XFER_MAPPED_DATA(19) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(2) = '1' then
+                        XFER_MAPPED_DATA(2)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(10) <= '1';
+                            XFER_MAPPED_DATA(18) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(1) = '1' then
+                        XFER_MAPPED_DATA(1)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(9)  <= '1';
+                            XFER_MAPPED_DATA(17) <= '1';
+                        end if;
+                    end if;
+                    if CGROM_DATA(0) = '1' then
+                        XFER_MAPPED_DATA(0)      <= '1';
+                        if CONFIG(MZ_KC) = '1' then
+                            XFER_MAPPED_DATA(8)  <= '1';
+                            XFER_MAPPED_DATA(16) <= '1';
+                        end if;
+                    end if;
+                    XFER_CYCLE := 5;
+
+                when 5 =>
+                    -- If invert option selected, invert green.
+                    --
+                    if (CONFIG(MZ_80B) = '1' and INVERSE_n = '0') or (CONFIG(MZ_A) = '1' and DISPLAY_INVERT = '1') then
+                        XFER_MAPPED_DATA(7 downto 0) <= not XFER_MAPPED_DATA(7 downto 0);
+                    end if;
+                    XFER_CYCLE := 6;
+
+                when 6 =>
+                    -- Graphics ram enabled?
+                    --
+                    if CONFIG(GRAMDISABLE) = '0' and GRAM_MODE(5) = '0' then
+                        -- Merge in the graphics data using defined mode.
+                        --
+                        case GRAM_MODE(7 downto 6) is
+                            when "00" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA or   reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                            when "01" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA and  reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                            when "10" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA nand reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                            when "11" =>
+                                XFER_MAPPED_DATA <= XFER_MAPPED_DATA xor  reverse_vector(XFER_GRAM_DATA(23 downto 16)) & reverse_vector(XFER_GRAM_DATA(15 downto 8)) & reverse_vector(XFER_GRAM_DATA(7 downto 0));
+                        end case;
+                    end if;
+                    XFER_CYCLE := 7;
+
+                when 7 =>
+                    -- For MZ80B, if enabled, blend in the graphics memory.
+                    --
+                    if CONFIG(MZ_80B) = '1' and XFER_DST_ADDR < 8192 then
+                        if GRAM_OPT_OUT1 = '1' and GRAM_OPT_OUT2 = '1' then
+                            XFER_MAPPED_DATA(15 downto 8) <= XFER_MAPPED_DATA(15 downto 8) or reverse_vector(XFER_GRAM_DATA(31 downto 24)) or reverse_vector(XFER_GRAM_DATA(39 downto 32));
+                        elsif GRAM_OPT_OUT1 = '1' then
+                            XFER_MAPPED_DATA(15 downto 8) <= XFER_MAPPED_DATA(15 downto 8) or reverse_vector(XFER_GRAM_DATA(31 downto 24));
+                        elsif GRAM_OPT_OUT2 = '1' then
+                            XFER_MAPPED_DATA(15 downto 8) <= XFER_MAPPED_DATA(15 downto 8) or reverse_vector(XFER_GRAM_DATA(39 downto 32));
+                        end if;
+                    end if;
+                    XFER_CYCLE := 8;
+
+                -- Commence write of mapped data.
+                when 8 =>
+                    XFER_WEN   <= '1';
+                    XFER_CYCLE := 9;
+
+                -- Complete write and update address.
+                when 9 =>
+                    -- Write cycle to framebuffer finished.
+                    XFER_WEN   <= '0';
+                    XFER_CYCLE := 10;
+
+                when 10 =>
+                    -- For each source character, we generate 8 lines in the frame buffer. Thus we need to 
+                    -- process the same source row 8 times, each time incrementing the sub-row which is used
+                    -- to extract the next pixel set from the CG. This data is thus written into the destination as:-
+                    -- <Row:0,CGLine:0,0 .. MAX_COLUMN -1> <Row:0,CGLine:1,0.. MAX_COLUMN -1> .. <Row:0,CGLine:7,0.. MAX_COLUMN -1>
+                    -- ..
+                    -- <Row:24,CGLine:0,0 .. MAX_COLUMN -1><Row:24,CGLine:1,0.. MAX_COLUMN -1> .. <Row:24,CGLine:7,0.. MAX_COLUMN -1>
+                    --
+                    -- To achieve this, we keep a note of the column and sub-row, incrementing the source address until end of line
+                    -- then winding it back if we are still rendering the Characters for a given row. 
+                    -- Destination address always increments every clock cycle to take the next pixel set.
+                    --
+                    if XFER_SRC_COL < MAX_COLUMN - 1 then
+                        XFER_SRC_COL        := XFER_SRC_COL + 1;
+                        XFER_VRAM_ADDR      <= XFER_VRAM_ADDR + 1;
+                    else
+                        if XFER_DST_SUBROW < MAX_SUBROW -1 then
+                            XFER_SRC_COL    := 0;
+                            XFER_DST_SUBROW := XFER_DST_SUBROW + 1;
+                            XFER_VRAM_ADDR  <= XFER_VRAM_ADDR - (MAX_COLUMN - 1);
+                        else
+                            XFER_SRC_COL    := 0;
+                            XFER_VRAM_ADDR  <= XFER_VRAM_ADDR + 1;
+                            XFER_DST_SUBROW := 0;
+                        end if;
+                    end if;
+
+                    -- Destination address increments every tick.
+                    --
+                    XFER_DST_ADDR <= XFER_DST_ADDR + 1;
+                    XFER_CYCLE := 0;
+            end case;
+        end if;
+
+        -- On a new cycle, reset the transfer parameters.
+        --
+        if V_COUNT = V_LINE_END and H_COUNT = H_LINE_END - 1 then
+
+            -- Start of display, setup the start of VRAM for display according to machine. 
+            if CONFIG(MZ_A) = '1' then
+                XFER_VRAM_ADDR <= (OFFSET_ADDR & "000");
+            else
+                XFER_VRAM_ADDR   <= (others => '0');
+            end if;
+            XFER_DST_ADDR    <= (others => '0');
+            XFER_CGROM_ADDR  <= (others => '0');
+            XFER_SRC_COL     := 0;
+            XFER_DST_SUBROW  := 0;
+            XFER_CYCLE       := 0;
+            XFER_ENABLED     := '0';
+            XFER_WEN         <= '0';
+            XFER_MAPPED_DATA <= (others => '0');
+        end if;
+    end if;
+end process;
+
+-- Process to generate the video data signals.
+--
+process( RST_n, CLKBUS, VIDEOMODE_CHANGED )
+begin
+    -- On reset, set the basic parameters which hold the video signal generator in reset
+    -- then load up the required parameter set and generate the video signal.
+    --
+    if RST_n = '0' then
+            H_DSP_START                  <= 0;
+            H_DSP_END                    <= 0;
+            H_DSP_WND_START              <= 0;
+            H_DSP_WND_END                <= 0;
+            H_MNU_START                  <= 0;
+            H_MNU_END                    <= 0;
+            H_HDR_START                  <= 0;
+            H_HDR_END                    <= 0;
+            H_FTR_START                  <= 0;
+            H_FTR_END                    <= 0;
+            V_DSP_START                  <= 0;
+            V_DSP_END                    <= 0;
+            V_DSP_WND_START              <= 0;
+            V_DSP_WND_END                <= 0;
+            V_MNU_START                  <= 0;
+            V_MNU_END                    <= 0;
+            V_HDR_START                  <= 0;
+            V_HDR_END                    <= 0;
+            V_FTR_START                  <= 0;
+            V_FTR_END                    <= 0;
+            MAX_COLUMN                   <= 0;
+            H_LINE_END                   <= 0;
+            V_LINE_END                   <= 0;
+            V_XFER_START                 <= 0;
+            H_COUNT                      <= (others => '0');
+            V_COUNT                      <= (others => '0');
+            H_BLANKi                     <= '1';
+            V_BLANKi                     <= '1';
+            H_SYNC_ni                    <= '1';
+            V_SYNC_ni                    <= '1';
+            H_PX_CNT                     <= 0;
+            V_PX_CNT                     <= 0;
+            H_SHIFT_CNT                  <= 0;
+            H_MNU_SHIFT_CNT              <= 0;
+            VIDEOMODE_LAST               <= 0;
+            VIDEOMODE_CHANGED            <= '1';
+            FB_ADDR                      <= (others => '0');
+            FB_ADDR_STATUS               <= (others => '0');
+            FB_ADDR_MENU                 <= (others => '0');
+
+    elsif rising_edge(CLKBUS(CKVIDEO)) then
+
+        -- If the video mode changes, reset the variables to the initial state. This occurs
+        -- at the end of a frame to minimise the monitor syncing incorrectly.
+        --
+        VIDEOMODE_LAST                   <= VIDEOMODE;
+        if VIDEOMODE_LAST /= VIDEOMODE then
+            VIDEOMODE_CHANGED            <= '1';
+        end if;
+        if VIDEOMODE_CHANGED = '1' then
+
+            -- Iniitialise control registers.
+            --
+            FB_ADDR                      <= (others => '0');
+            FB_ADDR_STATUS               <= (others => '0');
+            FB_ADDR_MENU                 <= (others => '0');
+            VIDEOMODE_CHANGED            <= '0';
+
+            -- Load up configuration from the look up table based on video mode.
+            --
+            H_DSP_START                  <= FB_PARAMS(VIDEOMODE, 0);
+            H_DSP_END                    <= FB_PARAMS(VIDEOMODE, 1);
+            H_DSP_WND_START              <= FB_PARAMS(VIDEOMODE, 2);
+            H_DSP_WND_END                <= FB_PARAMS(VIDEOMODE, 3);
+            H_MNU_START                  <= FB_PARAMS(VIDEOMODE, 4);
+            H_MNU_END                    <= FB_PARAMS(VIDEOMODE, 5);
+            H_HDR_START                  <= FB_PARAMS(VIDEOMODE, 6);
+            H_HDR_END                    <= FB_PARAMS(VIDEOMODE, 7);
+            H_FTR_START                  <= FB_PARAMS(VIDEOMODE, 8);
+            H_FTR_END                    <= FB_PARAMS(VIDEOMODE, 9);
+            V_DSP_START                  <= FB_PARAMS(VIDEOMODE, 10);
+            V_DSP_END                    <= FB_PARAMS(VIDEOMODE, 11);
+            V_DSP_WND_START              <= FB_PARAMS(VIDEOMODE, 12);
+            V_DSP_WND_END                <= FB_PARAMS(VIDEOMODE, 13);
+            V_MNU_START                  <= FB_PARAMS(VIDEOMODE, 14);
+            V_MNU_END                    <= FB_PARAMS(VIDEOMODE, 15);
+            V_HDR_START                  <= FB_PARAMS(VIDEOMODE, 16);
+            V_HDR_END                    <= FB_PARAMS(VIDEOMODE, 17);
+            V_FTR_START                  <= FB_PARAMS(VIDEOMODE, 18);
+            V_FTR_END                    <= FB_PARAMS(VIDEOMODE, 19);
+            H_LINE_END                   <= FB_PARAMS(VIDEOMODE, 20);
+            V_LINE_END                   <= FB_PARAMS(VIDEOMODE, 21);
+            V_XFER_START                 <= FB_PARAMS(VIDEOMODE, 22);
+            MAX_COLUMN                   <= FB_PARAMS(VIDEOMODE, 23);
+            H_SYNC_START                 <= FB_PARAMS(VIDEOMODE, 24);
+            H_SYNC_END                   <= FB_PARAMS(VIDEOMODE, 25);
+            V_SYNC_START                 <= FB_PARAMS(VIDEOMODE, 26);
+            V_SYNC_END                   <= FB_PARAMS(VIDEOMODE, 27);
+            H_PX                         <= FB_PARAMS(VIDEOMODE, 28);
+            V_PX                         <= FB_PARAMS(VIDEOMODE, 29);
+            --
+            H_COUNT                      <= (others => '0'); --to_unsigned(FB_PARAMS(VIDEOMODE, 16), H_COUNT'length); --  ((others => '0');
+            V_COUNT                      <= (others => '0');  --to_unsigned(FB_PARAMS(VIDEOMODE, 17), V_COUNT'length); -- (others => '0');
+            H_BLANKi                     <= '0';
+            V_BLANKi                     <= '0';
+            H_SYNC_ni                    <= '1';
+            V_SYNC_ni                    <= '1';
+            H_PX_CNT                     <= 0;
+            V_PX_CNT                     <= 0;
+            H_SHIFT_CNT                  <= 0;
+            H_MNU_SHIFT_CNT              <= 0;
+
+        else
+
+            -- Activate/deactivate signals according to pixel position.
+            --
+            if H_COUNT =  H_DSP_START     then H_BLANKi  <= '0'; end if;
+            --if H_COUNT =  H_LINE_END      then H_BLANKi  <= '0'; end if;
+            if H_COUNT =  H_DSP_END       then H_BLANKi  <= '1'; end if;
+            if H_COUNT =  H_SYNC_END      then H_SYNC_ni <= '1'; end if;
+            if H_COUNT =  H_SYNC_START    then H_SYNC_ni <= '0'; end if;
+            if V_COUNT =  V_DSP_START     then V_BLANKi  <= '0'; end if;
+            --if V_COUNT =  V_LINE_END      then V_BLANKi  <= '0'; end if;
+            if V_COUNT =  V_DSP_END       then V_BLANKi  <= '1'; end if;
+            if V_COUNT =  V_SYNC_START    then V_SYNC_ni <= '0'; end if;
+            if V_COUNT =  V_SYNC_END      then V_SYNC_ni <= '1'; end if;
+
+            -- If we are in the active visible area, stream the required output based on the various buffers.
+            --
+            if H_COUNT >= H_DSP_START and H_COUNT < H_DSP_END and V_COUNT >= V_DSP_START and V_COUNT < V_DSP_END then
+
+                -- Update Horizontal Pixel multiplier.
+                --
+                if H_PX_CNT = 0 then
+
+                    H_PX_CNT                 <= H_PX;
+                    H_SHIFT_CNT              <= H_SHIFT_CNT - 1;
+
+                    -- Main screen.
+                    --
+                    if H_SHIFT_CNT = 0 then
+                        if (V_COUNT >= V_DSP_WND_START and V_COUNT < V_DSP_WND_END) and (H_COUNT >= H_DSP_WND_START and H_COUNT < H_DSP_WND_END) then
+
+                            -- During the visible portion of the frame, data is stored in the frame buffer in bytes, 1 bit per pixel x 8 and 3 colors,
+                            -- thus 1 x 8 x 3 or 24 bit. Read out the values into shift registers to be serialised.
+                            --
+                            SR_G_DATA        <= DISPLAY_DATA(7 downto 0);
+                            SR_R_DATA        <= DISPLAY_DATA(15 downto 8);
+                            SR_B_DATA        <= DISPLAY_DATA(23 downto 16);
+                            FB_ADDR          <= FB_ADDR + 1;
+
+                        -- Border.
+                        --
+                        else
+                            -- Generate a fixed colour border, ideal for debugging.
+                            --
+                            SR_G_DATA        <= (others => '0');
+                            SR_R_DATA        <= "11111111";
+                            SR_B_DATA        <= (others => '0');
+                        end if;
+
+                    elsif H_SHIFT_CNT /= 0 and H_COUNT >= H_DSP_START and H_COUNT < H_DSP_END and V_COUNT >= V_DSP_START and V_COUNT < V_DSP_END then
+                        -- During the active display area, if the shift counter is not 0 and the horizontal multiplier is equal to the setting,
+                        -- shift the data in the shift register to display the next pixel.
+                        --
+                        SR_G_DATA            <= SR_G_DATA(6 downto 0) & '0';
+                        SR_R_DATA            <= SR_R_DATA(6 downto 0) & '0';
+                        SR_B_DATA            <= SR_B_DATA(6 downto 0) & '0';
+                    end if;
+                else
+                    H_PX_CNT                 <= H_PX_CNT - 1;
+                end if;
+
+                -- If the Status areas or the menu is enabled, create a data stream for the status/menu data to be merged with the main data.
+                --
+                if CONFIG(MENUENABLE) = '1' or CONFIG(STATUSENABLE) = '1' then
+
+                    H_MNU_SHIFT_CNT          <= H_MNU_SHIFT_CNT - 1;
+
+                    -- On each reset of the shift counter, load up Menu, Header, Footer or blank data to be serialised.
+                    --
+                    if H_MNU_SHIFT_CNT = 0 then
+
+                        -- OSD Menu
+                        --
+                        if CONFIG(MENUENABLE) = '1' and H_MNU_SHIFT_CNT = 0
+                           and
+                           ((V_COUNT >= V_MNU_START and V_COUNT < V_MNU_END) and (H_COUNT >= H_MNU_START and H_COUNT < H_MNU_END)) then
+        
+                            -- Merge the OSD with the underlying screen data.
+                            --
+                            SR_MNU_G_DATA    <= DISPLAY_DATA_MENU( 7 downto 0);
+                            SR_MNU_R_DATA    <= DISPLAY_DATA_MENU(15 downto 8);
+                            SR_MNU_B_DATA    <= DISPLAY_DATA_MENU(23 downto 16);
+                            FB_ADDR_MENU     <= FB_ADDR_MENU + 1;
+        
+                        -- Header/Footer
+                        --
+                        elsif CONFIG(STATUSENABLE) = '1' and H_MNU_SHIFT_CNT = 0
+                              and
+                              (((H_HDR_START /= H_HDR_END) and ((V_COUNT >= V_HDR_START and V_COUNT < V_HDR_END) and (H_COUNT >= H_HDR_START and H_COUNT < H_HDR_END)))
+                                or
+                               ((H_FTR_START /= H_FTR_END) and ((V_COUNT >= V_FTR_START and V_COUNT < V_FTR_END) and (H_COUNT >= H_FTR_START and H_COUNT < H_FTR_END)))) then
+           
+                            -- During the visible portion of the unused header/footer, read out the status frame buffer, 1 bit per pixel x 8 and 3 colours.
+                            --
+                            SR_MNU_G_DATA    <= DISPLAY_DATA_STATUS( 7 downto 0);
+                            SR_MNU_R_DATA    <= DISPLAY_DATA_STATUS(15 downto 8);
+                            SR_MNU_B_DATA    <= DISPLAY_DATA_STATUS(23 downto 16);
+                            FB_ADDR_STATUS   <= FB_ADDR_STATUS + 1;
+        
+                        -- Blank.
+                        --
+                        else
+                            -- Generate a fixed colour border, ideal for debugging.
+                            --
+                            SR_MNU_G_DATA    <= (others => '0');
+                            SR_MNU_R_DATA    <= (others => '0');
+                            SR_MNU_B_DATA    <= (others => '0');
+                        end if;
+        
+                    -- Shift on each clock cycle to next active bit if not at start.
+                    --
+                    elsif H_MNU_SHIFT_CNT /= 0 then
+                            SR_MNU_G_DATA    <= SR_MNU_G_DATA(6 downto 0) & '0';
+                            SR_MNU_R_DATA    <= SR_MNU_R_DATA(6 downto 0) & '0';
+                            SR_MNU_B_DATA    <= SR_MNU_B_DATA(6 downto 0) & '0';
+                    end if;
+                end if;
+            else
+                H_PX_CNT                     <= 0;
+                H_SHIFT_CNT                  <= 0;
+                H_MNU_SHIFT_CNT              <= 0;
+            end if;
+
+            -- Horizontal/Vertical counters are updated each clock cycle to accurately track pixel/timing.
+            --
+            if H_COUNT = H_LINE_END then
+                H_COUNT                      <= (others => '0');
+                H_PX_CNT                     <= 0;
+
+                -- Update Vertical Pixel multiplier.
+                --
+                if V_PX_CNT = 0 then
+                    V_PX_CNT                 <= V_PX;
+                else
+                    V_PX_CNT                 <= V_PX_CNT - 1;
+                end if;
+
+                -- When we need to repeat a line due to pixel multiplying, wind back the framebuffer address to start of line.
+                --
+                if V_COUNT >= V_DSP_WND_START and V_COUNT < V_DSP_WND_END and V_PX /= 0 and V_PX_CNT > 0 then
+                    FB_ADDR                  <= FB_ADDR - MAX_COLUMN;
+                end if;
+
+                -- For VGA, expand the vertical pixels according to setting.
+                --
+                if CONFIG(MENUENABLE) = '1' and ((V_COUNT >= V_MNU_START and V_COUNT < V_MNU_END) and (H_COUNT >= H_MNU_START and H_COUNT < H_MNU_END)) and V_PX /= 0 and V_PX_CNT > 0 then
+                    FB_ADDR_MENU             <= FB_ADDR_MENU - 32;
+                end if;
+
+                -- Once we have reached the end of the active vertical display, reset the framebuffer address.
+                --
+                if V_COUNT = V_DSP_END then
+                    FB_ADDR                  <= (others => '0');
+                    FB_ADDR_STATUS           <= (others => '0');
+                    FB_ADDR_MENU             <= (others => '0');
+                end if;
+
+                -- End of vertical line, increment to next or reset to beginning.
+                --
+                if V_COUNT = V_LINE_END then
+                    V_COUNT                  <= (others => '0');
+                    V_PX_CNT                 <= 0;
+                else
+                    V_COUNT                  <= V_COUNT + 1;
+                end if;
+            else
+                H_COUNT                      <= H_COUNT + 1;
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Control Registers
+--
+-- MZ1200/80A: INVERT display, accessed at E014
+--             SCROLL display, accessed at E200 - E2FF, the address determines the offset.
+-- F0-F3 clocks the i8253 gate for MZ80B. (not used in this module)
+-- F4-F7 set ths MZ80B/MZ2000 graphics options. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II.
+--       Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
+--
+-- IO Range for Graphics enhancements is set by the MCTRL DISPLAY2{7:3] register.
+-- x[0|8],<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+-- x[1|9],<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
+-- x[2|A],<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
+-- x[3|B],<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
+-- x[4|C]       switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. This overrides all MZ700 page switching functions.
+-- x[5|D]       switches out the graphics ram and returns to previous state.
+--
+process( RST_n, CLKBUS(CKMASTER) )
+begin
+    if RST_n='0' then
+        DISPLAY_INVERT        <= '0';
+        OFFSET_ADDR           <= (others => '0');
+        GRAM_MODE             <= "00001100";
+        GRAM_R_FILTER         <= (others => '1');
+        GRAM_G_FILTER         <= (others => '1');
+        GRAM_B_FILTER         <= (others => '1');
+        GRAM_OPT_WRITE        <= '0';
+        GRAM_OPT_OUT1         <= '0';
+        GRAM_OPT_OUT2         <= '0';
+
+    elsif rising_edge(CLKBUS(CKMASTER)) then
+
+        if CLKBUS(CKENCPU) = '1' then
+
+            if CS_INVERT_n='0' and T80_RD_n='0' then
+                DISPLAY_INVERT    <= T80_MA(0);
+            end if;
+
+            if CS_SCROLL_n='0' and T80_RD_n='0' then
+                if CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1' then
+                    OFFSET_ADDR   <= (others => '0');
+                else
+                    OFFSET_ADDR   <= T80_A(7 downto 0);
+                end if;
+            end if;
+
+            if CS_FB_CTL_n = '0'   and T80_WR_n = '0' then
+                GRAM_MODE         <= T80_DI;
+            end if;
+
+            if CS_FB_RED_n = '0'   and T80_WR_n = '0' then
+                GRAM_R_FILTER     <= T80_DI;
+            end if;
+
+            if CS_FB_GREEN_n = '0' and T80_WR_n = '0' then
+                GRAM_G_FILTER     <= T80_DI;
+            end if;
+
+            if CS_FB_BLUE_n = '0'  and T80_WR_n = '0' then
+                GRAM_B_FILTER     <= T80_DI;
+            end if;
+
+            if CS_GRAM_OPT_n = '0' and T80_WR_n = '0' then
+                GRAM_OPT_WRITE    <= T80_DI(0);
+                GRAM_OPT_OUT1     <= T80_DI(1);
+                GRAM_OPT_OUT2     <= T80_DI(2);
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Enable Video Wait States - Original design has wait states inserted into the cycle if the CPU accesses the VRAM during display. In the updated design, the VRAM
+-- is copied into a framebuffer during the Vertical Blanking period so no wait states are needed. To keep consistency with the original design (for programs which depend on it),
+-- the wait states can be enabled by configuration.
+--
+process( T80_MREQ_n ) begin
+    if falling_edge(T80_MREQ_n) then
+        VRAM_WAIT <= H_BLANKi;
+    end if;
+end process;
+--
+-- Extend wait by 1 cycle
+process( CLKBUS(CKMASTER) ) begin
+    if rising_edge(CLKBUS(CKMASTER)) then
+        if CLKBUS(CKENCPU) = '1' then
+            WAITii_n       <= WAITi_n;
+        end if;
+    end if;
+end process;
+
+--
+-- PCG Access Registers
+--
+-- E010: PCG_DATA (byte to describe 8-pixel row of a character)
+-- E011: PCG_ADDR (offset in the PCG in 8-pixel row unit) -> up to 256/8 = 32 characters
+-- E012: PCG_CTRL
+--                bit 0-1: character selector -> (PCG_ADDR + 256*(PCG_CTRL&3)) -> address in the range of the upper 128 characters font
+--                bit 2 : font selector -> PCG_CTRL&2 == 0 -> 1st font else 2nd font
+--                bit 3 : select which font for display
+--                bit 4 : use programmable font for display
+--                bit 5 : set programmable upper font -> PCG_CTRL&20 == 0 -> fixed upper 128 characters else programmable upper 128 characters
+--                So if you want to change a character pattern (only doable in the upper 128 characters of a font), you need to:
+--                - set bit 5 to 1 : PCG_CTRL[5] = 1
+--                - set the font to select : PCG_CTRL[2] = font_number
+--                - set the first row address of the character: PCG_ADDR[0..7] = row[0..7] and PCG_CTRL[0..1] = row[8..9]
+--                - set the 8 pixels of the row in PCG_DATA
+--
+process( RST_n, CLKBUS(CKMASTER) ) begin
+    if RST_n = '0' then
+        CGRAM_ADDR                <= (others=>'0');
+        PCG_DATA                  <= (others=>'0');
+        CGRAM_WE_n                <= '1';
+
+    elsif rising_edge(CLKBUS(CKMASTER)) then
+
+        if CLKBUS(CKENCPU) = '1' then
+
+            if CS_PCG_n = '0' and T80_WR_n = '0' then
+                -- Set the PCG Data to program to RAM. 
+                if T80_A(1 downto 0) = "00" then
+                    PCG_DATA                <= T80_DI;
+                end if;
+
+                -- Set the PCG Address in RAM. 
+                if T80_A(1 downto 0) = "01" then
+                    CGRAM_ADDR(7 downto 0)  <= T80_DI;
+                end if;
+
+                -- Set the PCG Control register.
+                if T80_A(1 downto 0) = "10"  then
+                    CGRAM_ADDR(11 downto 8) <= (T80_DI(2) and CONFIG(MZ_A)) & '1' & T80_DI(1 downto 0);
+                    CGRAM_WE_n              <= not T80_DI(4);
+                    CGRAM_SEL               <= T80_DI(5);
+                end if;
+            end if;
+        end if;
+    end if;
+end process;
+
+-- Process to allow the HPS or uC to read the configuration array.
+--
+process( IOCTL_CLK ) begin
+    if rising_edge(IOCTL_CLK) then
+        if IOCTL_ADDR(10) = '1' then
+            IOCTL_DIN_CONFIG <= "00000000000" & std_logic_vector(to_unsigned(VIDEOMODE, 5));
+        else
+            IOCTL_DIN_CONFIG <= std_logic_vector(to_unsigned(FB_PARAMS(to_integer(unsigned(IOCTL_ADDR(4 downto 0))), to_integer(unsigned(IOCTL_ADDR(9 downto 5)))), IOCTL_DIN_CONFIG'length));
+        end if;
+    end if;
+end process;
+
+--
+-- CPU / RAM signals and selects.
+--
+WAITi_n              <= '0'                                        when CS_VRAM_n = '0'          and VRAM_WAIT = '0' and H_BLANKi = '0' and (CONFIG(MZ_A) = '1' or CONFIG(MZ700) = '1')
+                        else '1';
+T80_WAIT_n           <= WAITi_n and WAITii_n                       when CONFIG(VRAMWAIT) = '1'
+                        else '1';
+T80_MA               <= "00" & T80_A(9 downto 0)                   when CONFIG(MZ_KC) = '1'
+                        else
+                        T80_A(11 downto 0);
+-- Program Character Generator RAM. E010 - Write cycle (Read cycle = reset memory swap).
+CS_PCG_n             <= '0'                                        when CS_MEM_G_n = '0'      and T80_A(10 downto 4) = "0000001"
+                        else '1';                                                                   -- D010 -> D01f
+-- Invert display register. E014/E015
+CS_INVERT_n          <= '0'                                        when CS_MEM_G_n = '0'      and CONFIG(MZ_A) = '1'        and T80_MA(11 downto 9) = "000" and T80_MA(4 downto 2) = "101"
+                        else '1';
+-- Scroll display register. E200 - E2FF
+CS_SCROLL_n          <= '0'                                        when CS_MEM_G_n = '0'      and T80_A(11 downto 8)="0010" and CONFIG(MZ_A)='1'
+                        else '1';
+-- MZ80B/MZ2000 Graphics Options Register select. F4-F7
+CS_GRAM_OPT_n        <= '0'                                        when CS_IO_G_n = '0'       and T80_A(1 downto 0) = "00"
+                        else '1';
+-- <block>0,<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR),
+--                                          5 = GRAM Output Enable, 4 = VRAM Output Enable,
+--                                        3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect),
+--                                        1/0 = Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+CS_FB_CTL_n          <= '0'                                        when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "000"
+                        else '1';
+--  01,<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
+CS_FB_RED_n          <= '0'                                        when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "001"
+                        else '1';
+--  02,<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
+CS_FB_GREEN_n        <= '0'                                        when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "010"
+                        else '1';
+--  03,<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
+CS_FB_BLUE_n         <= '0'                                        when CS_IO_GFB_n = '0'     and T80_A(2 downto 0) = "011"
+                        else '1';
+
+T80_DO               <= VRAM_VIDEO_DATA                            when T80_RD_n = '0'        and CS_VRAM_n = '0'
+                        else
+                        GRAM_VIDEO_DATA                            when T80_RD_n = '0'        and CS_GRAM_n = '0'
+                        else
+                        GRAM_DO_GI                                 when T80_RD_n = '0'        and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '0'
+                        else
+                        GRAM_DO_GII                                when T80_RD_n = '0'        and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '1'
+                        else
+                        (others=>'0');
+
+VRAM_ADDR            <= T80_MA(10 downto 0) & T80_MA(11)           when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_ADDR(10 downto 0) & IOCTL_ADDR(11);
+VRAM_DI              <= T80_DI                                     when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_DOUT(7 downto 0);
+VWEN                 <= '1'                                        when T80_WR_n='0'          and CS_VRAM_n = '0'
+                        else '0';
+VRAM_WEN             <= VWEN                                       when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_WEN_VRAM;
+VRAM_VIDEO_DATA      <= VRAM_DO                                    when IOCTL_CS_VRAM_n = '1'
+                        else
+                        (others=>'0');
+IOCTL_DIN_VRAM       <= VRAM_DO                                    when IOCTL_CS_VRAM_n = '0'
+                        else
+                        (others=>'0');
+VRAM_CLK             <= CLKBUS(CKMASTER)                           when IOCTL_CS_VRAM_n = '1'
+                        else
+                        IOCTL_CLK;
+VRAM_CLK_EN          <= CLKBUS(CKENCPU)                            when IOCTL_CS_VRAM_n = '1'
+                        else
+                        '1';
+
+-- CGROM Data to CG RAM, either ROM -> RAM copy or Z80 provides map.
+--
+CGRAM_DI             <= CGROM_DO                                   when CGRAM_SEL = '1'               -- Data from ROM
+                        else
+                        PCG_DATA                                   when CGRAM_SEL = '0'               -- Data from PCG
+                        else (others=>'0');
+CGRAM_WEN            <= not (CGRAM_WE_n or CS_PCG_n) and not T80_WR_n; 
+
+--
+-- Font select
+--
+CGROM_DATA           <= CGROM_DO                                   when CONFIG(PCGRAM)='0'
+                        else
+                        PCG_DATA                                   when CS_PCG_n='0'         and T80_A(1 downto 0)="10" and T80_WR_n='0'
+                        else
+                        CGRAM_DO                                   when CONFIG(PCGRAM)='1'
+                        else (others => '1');
+CG_ADDR              <= CGRAM_ADDR(11 downto 0)                    when CGRAM_WE_n = '0'
+                        else XFER_CGROM_ADDR;
+CGROM_BANK           <= "0000"                                     when CONFIG(MZ80K)  = '1'
+                        else
+                        "0001"                                     when CONFIG(MZ80C)  = '1'
+                        else
+                        "0010"                                     when CONFIG(MZ1200) = '1'
+                        else
+                        "0011"                                     when CONFIG(MZ80A)  = '1'
+                        else
+                        "0100"                                     when CONFIG(MZ700)  = '1'  and XFER_CGROM_ADDR(11) = '0'
+                        else
+                        "0101"                                     when CONFIG(MZ700)  = '1'  and XFER_CGROM_ADDR(11) = '1'
+                        else
+                        "0110"                                     when CONFIG(MZ800)  = '1'  and XFER_CGROM_ADDR(11) = '0'
+                        else
+                        "0111"                                     when CONFIG(MZ800)  = '1'  and XFER_CGROM_ADDR(11) = '1'
+                        else
+                        "1000"                                     when CONFIG(MZ80B)  = '1'
+                        else
+                        "1001"                                     when CONFIG(MZ2000) = '1'
+                        else
+                        "1111";
+
+
+-- As the Graphics RAM is an odd size, 16384 x 3 colour planes, it has to be in 3 seperate 16K blocks to avoid wasting memory (or having it synthesized away),
+-- thus there are 3 sets of signals, 1 per colour.
+--
+GRAM_ADDR            <= T80_A(13 downto 0)                         when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_ADDR(13 downto 0);
+                        -- direct writes when accessing individual pages.
+GRAM_DI_R            <= T80_DI                                     when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "00"
+                        else
+                        T80_DI and GRAM_R_FILTER                   when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        IOCTL_DOUT(7 downto 0)                     when IOCTL_CS_GRAM_n = '0' and IOCTL_ADDR(15 downto 14) = "00"
+                        else
+                        (others=>'0');
+                        -- direct writes when accessing individual pages.
+GRAM_DI_G            <= T80_DI                                     when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "01"
+                        else
+                        T80_DI and GRAM_G_FILTER                   when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        IOCTL_DOUT(7 downto 0)                     when IOCTL_CS_GRAM_n = '0' and IOCTL_ADDR(15 downto 14) = "01"
+                        else
+                        (others=>'0');
+                        -- direct writes when accessing individual pages.
+GRAM_DI_B            <= T80_DI                                     when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "10"
+                        else
+                        T80_DI and GRAM_B_FILTER                   when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        IOCTL_DOUT(7 downto 0)                     when IOCTL_CS_GRAM_n = '0' and IOCTL_ADDR(15 downto 14) = "10"
+                        else
+                        (others=>'0');
+GWEN_R               <= '1'                                        when T80_WR_n = '0' and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "00"
+                        else
+                        '1'                                        when T80_WR_n = '0' and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        '0';
+GRAM_WEN_R           <= GWEN_R                                     when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_R;
+GWEN_G               <= '1'                                        when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "01"
+                        else
+                        '1'                                        when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        '0';
+GRAM_WEN_G           <= GWEN_G                                     when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_G;
+GWEN_B               <= '1'                                        when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "10"
+                        else
+                        '1'                                        when T80_WR_n='0'   and CS_GRAM_n = '0' and GRAM_MODE(3 downto 2) = "11"
+                        else
+                        '0';
+GRAM_WEN_B           <= GWEN_B                                     when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_B;
+
+GRAM_VIDEO_DATA      <= GRAM_DO_R                                  when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "00"
+                        else
+                        GRAM_DO_G                                  when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "01"
+                        else
+                        GRAM_DO_B                                  when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "10"
+                        else
+                        (others=>'0');
+GRAM_CLK             <= CLKBUS(CKMASTER)                           when IOCTL_CS_GRAM_n = '1'
+                        else
+                        IOCTL_CLK;
+GRAM_CLK_EN          <= CLKBUS(CKENCPU)                            when IOCTL_CS_GRAM_n = '1'
+                        else
+                        '1';
+
+-- MZ80B/MZ2000 Graphics Option RAM.
+--
+GRAM_DI_GI           <= T80_DI                                     when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_DOUT(7 downto 0)                     when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_ADDR(13) = '0'
+                        else
+                        (others=>'0');
+GRAM_DI_GII          <= T80_DI                                     when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_DOUT(7 downto 0)                     when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_ADDR(13) = '1'
+                        else
+                        (others=>'0');
+GWEN_GI              <= '1'                                        when T80_WR_n = '0' and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '0'
+                        else
+                        '0';
+GRAM_WEN_GI          <= GWEN_GI                                    when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_GI;
+GWEN_GII             <= '1'                                        when T80_WR_n='0'   and CS_GRAM_80B_n = '0' and GRAM_OPT_WRITE = '1'
+                        else
+                        '0';
+GRAM_WEN_GII         <= GWEN_GII                                   when IOCTL_CS_GRAM_80B_n = '1'
+                        else
+                        IOCTL_WEN_GRAM_GII;
+
+--
+-- HPS Access - match whole address, additional LE but easier to read.
+--
+IOCTL_WEN_VRAM       <= '1'                                        when IOCTL_CS_VRAM_n = '0'     and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_GRAM_R     <= '1'                                        when IOCTL_CS_GRAM_n = '0'     and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "00"
+                        else '0';
+IOCTL_WEN_GRAM_G     <= '1'                                        when IOCTL_CS_GRAM_n = '0'     and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "01"
+                        else '0';
+IOCTL_WEN_GRAM_B     <= '1'                                        when IOCTL_CS_GRAM_n = '0'     and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "10"
+                        else '0';
+IOCTL_WEN_GRAM_GI    <= '1'                                        when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_WR = '1' and IOCTL_ADDR(13) = '0'
+                        else '0';
+IOCTL_WEN_GRAM_GII    <= '1'                                       when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_WR = '1' and IOCTL_ADDR(13) = '1'
+                        else '0';
+IOCTL_WEN_CGROM      <= '1'                                        when IOCTL_CS_CGROM_n = '0'    and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_CGRAM      <= '1'                                        when IOCTL_CS_CGRAM_n = '0'    and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_STRAM_G    <= '1'                                        when IOCTL_CS_STRAM_G_n = '0'  and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_STRAM_R    <= '1'                                        when IOCTL_CS_STRAM_R_n = '0'  and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_STRAM_B    <= '1'                                        when IOCTL_CS_STRAM_B_n = '0'  and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_MNURAM_G   <= '1'                                        when IOCTL_CS_MNURAM_G_n = '0' and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_MNURAM_R   <= '1'                                        when IOCTL_CS_MNURAM_R_n = '0' and IOCTL_WR = '1'
+                        else '0';
+IOCTL_WEN_MNURAM_B   <= '1'                                        when IOCTL_CS_MNURAM_B_n = '0' and IOCTL_WR = '1'
+                        else '0';
+IOCTL_CS_VRAM_n      <= '0'                                        when IOCTL_ADDR(24 downto 12) = "0001100000000"
+                        else '1';
+IOCTL_CS_GRAM_n      <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110001" and IOCTL_ADDR(15 downto 14) /= "11"
+                        else '1';
+IOCTL_CS_GRAM_80B_n  <= '0'                                        when IOCTL_ADDR(24 downto 14) = "00011000111"
+                        else '1';
+IOCTL_CS_CGROM_n     <= '0'                                        when IOCTL_ADDR(24 downto 17) = "00101000"
+                        else '1';
+IOCTL_CS_CGRAM_n     <= '0'                                        when IOCTL_ADDR(24 downto 17) = "00110000"
+                        else '1';
+IOCTL_CS_STRAM_G_n   <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0000"
+                        else '1';
+IOCTL_CS_STRAM_R_n   <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0001"
+                        else '1';
+IOCTL_CS_STRAM_B_n   <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0010"
+                        else '1';
+IOCTL_CS_MNURAM_G_n  <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0100"
+                        else '1';
+IOCTL_CS_MNURAM_R_n  <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0101"
+                        else '1';
+IOCTL_CS_MNURAM_B_n  <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "0110"
+                        else '1';
+IOCTL_CS_CONFIG_n    <= '0'                                        when IOCTL_ADDR(24 downto 16) = "000110010" and IOCTL_ADDR(15 downto 12) = "1000"
+                        else '1';
+IOCTL_DIN            <= X"00" & IOCTL_DIN_VRAM                     when IOCTL_CS_VRAM_n = '0'     and IOCTL_RD = '1'
+                        else
+                        X"00" & IOCTL_DIN_GRAM                     when IOCTL_CS_GRAM_n = '0'     and IOCTL_RD = '1'
+                        else
+                        X"00" & IOCTL_DIN_CGROM                    when IOCTL_CS_CGROM_n = '0'    and IOCTL_RD = '1'
+                        else
+                        X"00" & IOCTL_DIN_CGRAM                    when IOCTL_CS_CGRAM_n = '0'    and IOCTL_RD = '1'
+                        else
+                        IOCTL_DIN_STRAM_G                          when IOCTL_CS_STRAM_G_n = '0'  and IOCTL_RD = '1' 
+                        else
+                        IOCTL_DIN_STRAM_R                          when IOCTL_CS_STRAM_R_n = '0'  and IOCTL_RD = '1'
+                        else
+                        IOCTL_DIN_STRAM_B                          when IOCTL_CS_STRAM_B_n = '0'  and IOCTL_RD = '1'
+                        else
+                        IOCTL_DIN_MNURAM_G                         when IOCTL_CS_MNURAM_G_n = '0' and IOCTL_RD = '1'
+                        else
+                        IOCTL_DIN_MNURAM_R                         when IOCTL_CS_MNURAM_R_n = '0' and IOCTL_RD = '1'
+                        else
+                        IOCTL_DIN_MNURAM_B                         when IOCTL_CS_MNURAM_B_n = '0' and IOCTL_RD = '1'
+                        else
+                        IOCTL_DIN_CONFIG                           when IOCTL_CS_CONFIG_n = '0'   and IOCTL_RD = '1'
+                        else
+                        (others=>'0');                        
+IOCTL_DIN_GRAM       <= GRAM_DO_R                                  when IOCTL_CS_GRAM_n = '0'     and IOCTL_ADDR(15 downto 14) = "00"
+                        else
+                        GRAM_DO_G                                  when IOCTL_CS_GRAM_n = '0'     and IOCTL_ADDR(15 downto 14) = "01"
+                        else
+                        GRAM_DO_B                                  when IOCTL_CS_GRAM_n = '0'     and IOCTL_ADDR(15 downto 14) = "10"
+                        else
+                        GRAM_DO_GI                                 when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_ADDR(13) = '0'
+                        else
+                        GRAM_DO_GII                                when IOCTL_CS_GRAM_80B_n = '0' and IOCTL_ADDR(13) = '1'
+                        else
+                        (others=>'0');
+
+-- Work out the current video mode, which is used to look up the parameters for frame generation.
+--
+VIDEOMODE            <= 0  when CONFIG(VGAMODE) = "11" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '0'
+                        else
+                        1  when CONFIG(VGAMODE) = "11" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '1'
+                        else
+                        2  when CONFIG(VGAMODE) = "11" and CONFIG(NORMAL)   = '1'
+                        else
+                        3  when CONFIG(VGAMODE) = "11" and CONFIG(NORMAL80) = '1'
+                        else
+                        4  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        5  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        6  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR)   = '1'
+                        else
+                        7  when CONFIG(VGAMODE) = "11" and CONFIG(COLOUR80) = '1' 
+                        else
+                        8  when CONFIG(VGAMODE) = "00" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '0'
+                        else
+                        10 when CONFIG(VGAMODE) = "00" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '1'
+                        else
+                        9  when CONFIG(VGAMODE) = "01" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '0'
+                        else
+                        11 when CONFIG(VGAMODE) = "01" and CONFIG(MZ_80B)   = '1' and CONFIG_CHAR80 = '1'
+                        else
+                        8  when CONFIG(VGAMODE) = "00" and CONFIG(NORMAL)   = '1'
+                        else
+                        9  when CONFIG(VGAMODE) = "01" and CONFIG(NORMAL)   = '1'
+                        else
+                        10 when CONFIG(VGAMODE) = "00" and CONFIG(NORMAL80) = '1'
+                        else
+                        11 when CONFIG(VGAMODE) = "01" and CONFIG(NORMAL80) = '1'
+                        else
+                        12 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        13 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        18 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR)   = '1' and CONFIG(MZ700) = '1'
+                        else
+                        14 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        15 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        19 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1'
+                        else
+                        12 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR)   = '1'
+                        else
+                        13 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR)   = '1'
+                        else
+                        18 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR)   = '1'
+                        else
+                        14 when CONFIG(VGAMODE) = "00" and CONFIG(COLOUR80) = '1'
+                        else
+                        15 when CONFIG(VGAMODE) = "01" and CONFIG(COLOUR80) = '1'
+                        else
+                        19 when CONFIG(VGAMODE) = "10" and CONFIG(COLOUR80) = '1'
+                        else
+                        16 when CONFIG(VGAMODE) = "10" and CONFIG(NORMAL)   = '1'
+                        else
+                        17 when CONFIG(VGAMODE) = "10" and CONFIG(NORMAL80) = '1'
+                        else
+                        2;
+
+    --
+    -- Video Output Signals
+    --
+    VBLANK           <= V_BLANKi;
+    HBLANK           <= H_BLANKi;
+    VSYNC_n          <= V_SYNC_ni;
+    HSYNC_n          <= H_SYNC_ni;
+    ROUT             <= (others => SR_R_DATA(7) or SR_MNU_R_DATA(7)) when H_BLANKi='0' or VGATE_n='1'
+                        else
+                        (others => '0');
+    GOUT             <= (others => SR_G_DATA(7) or SR_MNU_R_DATA(7)) when H_BLANKi='0' or VGATE_n='1'
+                        else
+                        (others => '0');
+    BOUT             <= (others => SR_B_DATA(7) or SR_MNU_R_DATA(7)) when H_BLANKi='0' or VGATE_n='1'
+                        else
+                        (others => '0');
+
+end RTL;
diff --git a/common/z8420/Interrupt.vhd b/common/z8420/Interrupt.vhd
new file mode 100644
index 0000000..aeaa328
--- /dev/null
+++ b/common/z8420/Interrupt.vhd
@@ -0,0 +1,125 @@
+--
+-- Interrupt.vhd
+--
+-- Z80 Daisy-Chain Interrupt Logic for FPGA
+--
+-- Nibbles Lab. 2013-2014
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity Interrupt is
+    Port (
+        -- System Signal
+        RESET                : in  std_logic;
+        -- CPU Signals
+        DI                   : in  std_logic_vector(7 downto 0);
+        IORQ_n               : in  std_logic;                            -- same as Z80
+        RD_n                 : in  std_logic;                            -- same as Z80
+        M1_n                 : in  std_logic;                            -- same as Z80
+        IEI                  : in  std_logic;                            -- same as Z80
+        IEO                  : out std_logic;                            -- same as Z80
+        INTO_n               : out std_logic;
+        -- Control Signals
+        VECTEN               : out std_logic;
+        INTI                 : in  std_logic;
+        INTEN                : in  std_logic
+    );
+end Interrupt;
+
+architecture Behavioral of Interrupt is
+
+-----------------------------------------------------------------------------------
+-- Signals
+-----------------------------------------------------------------------------------
+
+signal IREQ                  : std_logic;
+signal IRES                  : std_logic;
+signal INTR                  : std_logic;
+signal IAUTH                 : std_logic;
+signal AUTHRES               : std_logic;
+signal IED1                  : std_logic;
+signal IED2                  : std_logic;
+signal ICB                   : std_logic;
+signal I4D                   : std_logic;
+signal FETCH                 : std_logic;
+signal INTA                  : std_logic;
+signal IENB                  : std_logic;
+signal iINT                  : std_logic;
+signal iIEO                  : std_logic;
+
+begin
+
+    --
+    -- External signals
+    --
+    INTO_n  <= iINT;
+    IEO     <= iIEO;
+
+    --
+    -- Internal signals
+    --
+    iINT    <= '0' when IEI='1' and IREQ='1' and IAUTH='0' else '1';
+    iIEO    <= not (((not IED1) and IREQ) or IAUTH or (not IEI));
+    INTA    <= ((not M1_n) and (not IORQ_n) and IEI);
+    AUTHRES <= RESET or (IEI and IED2 and I4D);
+    FETCH   <= M1_n or RD_n;
+    IRES    <= RESET or INTA;
+    INTR    <= M1_n and (INTI and INTEN);
+    VECTEN  <= '1' when INTA='1' and IEI='1' and IAUTH='1' else '0';
+
+    --
+    -- Keep Interrupt Request
+    --
+    process( IRES, INTR ) begin
+        if IRES='1' then
+            IREQ     <= '0';
+        elsif INTR'event and INTR='1' then
+            IREQ     <= '1';
+        end if;
+    end process;
+
+    --
+    -- Interrupt Authentication
+    --
+    process( AUTHRES, INTA ) begin
+        if AUTHRES='1' then
+            IAUTH    <= '0';
+        elsif INTA'event and INTA='1' then
+            IAUTH    <= IREQ;
+        end if;
+    end process;
+
+    --
+    -- Fetch 'RETI'
+    --
+    process( RESET, FETCH ) begin
+        if RESET='1' then
+            IED1     <= '0';
+            IED2     <= '0';
+            ICB      <= '0';
+            I4D      <= '0';
+        elsif FETCH'event and FETCH='1' then
+            IED2     <= IED1;
+            if DI=X"ED" and ICB='0' then
+                IED1 <= '1';
+            else
+                IED1 <= '0';
+            end if;
+            if DI=X"CB" then
+                ICB  <= '1';
+            else
+                ICB  <= '0';
+            end if;
+            if DI=X"4D" then
+                I4D  <= IEI;
+            else
+                I4D  <= '0';
+            end if;
+        end if;
+    end process;
+
+end Behavioral;
diff --git a/common/z8420/z8420.vhd b/common/z8420/z8420.vhd
new file mode 100644
index 0000000..b4d6b5c
--- /dev/null
+++ b/common/z8420/z8420.vhd
@@ -0,0 +1,246 @@
+--
+-- z8420.vhd
+--
+-- Zilog Z80PIO partiality compatible module
+-- for MZ-80B on FPGA
+--
+-- Port A : Output, mode 0 only
+-- Port B : Input, mode 0 only
+--
+-- Nibbles Lab. 2005-2014
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity z8420 is
+    Port (
+        -- System
+        RST_n                : in std_logic;                                -- Only Power On Reset
+        -- Z80 Bus Signals
+        CLK                  : in std_logic;
+        ENA                  : in std_logic;
+        BASEL                : in std_logic;
+        CDSEL                : in std_logic;
+        CE                   : in std_logic;
+        RD_n                 : in std_logic;
+        WR_n                 : in std_logic;
+        IORQ_n               : in std_logic;
+        M1_n                 : in std_logic;
+        DI                   : in std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        IEI                  : in std_logic;
+        IEO                  : out std_logic;
+        INT_n                : out std_logic;
+        -- Port
+        A                    : out std_logic_vector(7 downto 0);
+        B                    : in std_logic_vector(7 downto 0)
+    );
+end z8420;
+
+architecture Behavioral of z8420 is
+
+--
+-- Port Selecter
+--
+signal SELAD                 : std_logic;
+signal SELBD                 : std_logic;
+signal SELAC                 : std_logic;
+signal SELBC                 : std_logic;
+--
+-- Port Register
+--
+signal AREG                  : std_logic_vector(7 downto 0);             -- Output Register (Port A)
+signal DIRA                  : std_logic_vector(7 downto 0);             -- Data Direction (Port A)
+signal DDWA                  : std_logic;                                -- Prepare for Data Direction (Port A)
+signal IMWA                  : std_logic_vector(7 downto 0);             -- Interrupt Mask Word (Port A)
+signal MFA                   : std_logic;                                -- Mask Follows (Port A)
+signal VECTA                 : std_logic_vector(7 downto 0);             -- Interrupt Vector (Port A)
+signal MODEA                 : std_logic_vector(1 downto 0);             -- Mode Word (Port A)
+signal HLA                   : std_logic;                                -- High/Low (Port A)
+signal AOA                   : std_logic;                                -- AND/OR (Port A)
+signal DIRB                  : std_logic_vector(7 downto 0);             -- Data Direction (Port B)
+signal DDWB                  : std_logic;                                -- Prepare for Data Direction (Port B)
+signal IMWB                  : std_logic_vector(7 downto 0);             -- Interrupt Mask Word (Port B)
+signal MFB                   : std_logic;                                -- Mask Follows (Port B)
+signal VECTB                 : std_logic_vector(7 downto 0);             -- Interrupt Vector (Port B)
+signal MODEB                 : std_logic_vector(1 downto 0);             -- Mode Word (Port B)
+signal HLB                   : std_logic;                                -- High/Low (Port B)
+signal AOB                   : std_logic;                                -- AND/OR (Port B)
+--
+-- Interrupt
+--
+--signal VECTENA             : std_logic;
+signal EIA                   : std_logic;                                -- Interrupt Enable (Port A)
+--signal MINTA               : std_logic_vector(7 downto 0);
+--signal INTA                : std_logic;
+signal VECTENB               : std_logic;
+signal EIB                   : std_logic;                                -- Interrupt Enable (Port B)
+signal MINTB                 : std_logic_vector(7 downto 0);
+signal INTB                  : std_logic;
+
+--
+-- Components
+--
+component Interrupt is
+    Port (
+        -- System Signal
+        RESET                : in  std_logic;
+        -- CPU Signals
+        DI                   : in  std_logic_vector(7 downto 0);
+        IORQ_n               : in  std_logic;                            -- same as Z80
+        RD_n                 : in  std_logic;                            -- same as Z80
+        M1_n                 : in  std_logic;                            -- same as Z80
+        IEI                  : in  std_logic;                            -- same as Z80
+        IEO                  : out std_logic;                            -- same as Z80
+        INTO_n               : out std_logic;
+        -- Control Signals
+        VECTEN               : out std_logic;
+        INTI                 : in  std_logic;
+        INTEN                : in  std_logic
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+--  INT0 : Interrupt port map (
+--       -- System Signal
+--       RESET => RST_n,
+--       -- CPU Signals
+--       IORQ_n => IORQ_n,
+--       RD_n => RD_n,
+--       M1_n => M1_n,
+--       IEI => IEI,
+--       IEO => IEO,
+--       INTO_n => INTA_n,
+--       -- Control Signals
+--       VECTEN => VECTENA,
+--       INTI => INTA,
+--       INTEN => EIA
+--   );
+
+    INT1 : Interrupt port map (
+        -- System Signal
+        RESET                => RST_n,
+        -- CPU Signals
+        DI                   => DI,
+        IORQ_n               => IORQ_n,
+        RD_n                 => RD_n,
+        M1_n                 => M1_n,
+        IEI                  => IEI,
+        IEO                  => IEO,
+        INTO_n               => INT_n,    --INTB_n,
+        -- Control Signals
+        VECTEN               => VECTENB,
+        INTI                 => INTB,
+        INTEN                => EIB
+    );
+
+    --
+    -- Port select for Output
+    --
+    SELAD <= '1' when BASEL='0' and CDSEL='0' else '0';
+    SELBD <= '1' when BASEL='1' and CDSEL='0' else '0';
+    SELAC <= '1' when BASEL='0' and CDSEL='1' else '0';
+    SELBC <= '1' when BASEL='1' and CDSEL='1' else '0';
+
+    --
+    -- Output
+    --
+    process( RST_n, CLK, ENA ) begin
+        if RST_n='0' then
+            AREG    <= (others=>'0');
+            MODEA   <= "01";
+            DDWA    <= '0';
+            MFA     <= '0';
+            EIA     <= '0';
+--          B<=(others=>'0');
+            MODEB   <= "01";
+            DDWB    <= '0';
+            MFB     <= '0';
+            EIB     <= '0';
+        elsif CLK'event and CLK='0' then
+            if ENA = '1' then
+                if CE='0' and WR_n='0' then
+                    if SELAD='1' then
+                        AREG      <=DI;
+                    end if;
+    --              if SELBD='1' then
+    --                  B<=DI;
+    --              end if;
+                    if SELAC='1' then
+                        if DDWA='1' then
+                            DIRA  <=DI;
+                            DDWA  <='0';
+                        elsif MFA='1' then
+                            IMWA  <=DI;
+                            MFA   <='0';
+                        elsif DI(0)='0' then
+                            VECTA <=DI;
+                        elsif DI(3 downto 0)="1111" then
+                            MODEA <=DI(7 downto 6);
+                            DDWA  <=DI(7) and DI(6);
+                        elsif DI(3 downto 0)="0111" then
+                            MFA   <=DI(4);
+                            HLA   <=DI(5);
+                            AOA   <=DI(6);
+                            EIA   <=DI(7);
+                        elsif DI(3 downto 0)="0011" then
+                            EIA   <=DI(7);
+                        end if;
+                    end if;
+                    if SELBC='1' then
+                        if DDWB='1' then
+                            DIRB  <=DI;
+                            DDWB  <='0';
+                        elsif MFB='1' then
+                            IMWB  <=DI;
+                            MFB   <='0';
+                        elsif DI(0)='0' then
+                            VECTB <=DI;
+                        elsif DI(3 downto 0)="1111" then
+                            MODEB <=DI(7 downto 6);
+                            DDWB  <=DI(7) and DI(6);
+                        elsif DI(3 downto 0)="0111" then
+                            MFB   <=DI(4);
+                            HLB   <=DI(5);
+                            AOB   <=DI(6);
+                            EIB   <=DI(7);
+                        elsif DI(3 downto 0)="0011" then
+                            EIB   <=DI(7);
+                        end if;
+                    end if;
+                end if;
+             end if;
+        end if;
+    end process;
+    A<=AREG;
+
+    --
+    -- Input select
+    --
+    DO<=AREG  when RD_n='0' and CE='0' and SELAD='1' else
+         B     when RD_n='0' and CE='0' and SELBD='1' else
+--       VECTA when VECTENA='1' else
+         VECTB when VECTENB='1' else (others=>'0');
+
+    --
+    -- Interrupt select
+    --
+    INTMASK : for I in 0 to 7 generate
+--      MINTA(I)<=(A(I) xnor HLA) and (not IMWA(I)) when AOA='0' else
+--                   (A(I) xnor HLA) or IMWA(I);
+        MINTB(I)<=(B(I) xnor HLB) and (not IMWB(I)) when AOB='0' else
+                     (B(I) xnor HLB) or IMWB(I);
+    end generate INTMASK;
+--    INTA<=MINTA(7) or MINTA(6) or MINTA(5) or MINTA(4) or MINTA(3) or MINTA(2) or MINTA(1) or MINTA(0) when AOA='0' else
+--            MINTA(7) and MINTA(6) and MINTA(5) and MINTA(4) and MINTA(3) and MINTA(2) and MINTA(1) and MINTA(0);
+    INTB<=MINTB(7) or MINTB(6) or MINTB(5) or MINTB(4) or MINTB(3) or MINTB(2) or MINTB(1) or MINTB(0) when AOB='0' else
+            MINTB(7) and MINTB(6) and MINTB(5) and MINTB(4) and MINTB(3) and MINTB(2) and MINTB(1) and MINTB(0);
+
+end Behavioral;
diff --git a/emu.sv b/emu.sv
new file mode 100644
index 0000000..02530d3
--- /dev/null
+++ b/emu.sv
@@ -0,0 +1,356 @@
+//=======================================================================================================
+//
+// Name:            emu.sv
+// Created:         June 2018
+// Author(s):       Philip Smart
+// Description:     Sharp MZ series compatible logic.
+//                                                     
+//                  This module is the main bridge between the emulator (sharpmz.vhd) and the MiSTer
+//                  framework (hps_io.v/sys_top.v).
+//
+// Copyright:       (C) 2018 Sorgelig
+//                  (C) 2018 Philip Smart <philip.smart@net2net.org>
+//
+// History:         June 2018 - Initial creation.
+//
+//=======================================================================================================
+// This source file is free software: you can redistribute it and-or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//=======================================================================================================
+
+module emu
+(
+    //Master input clocks
+    input         CLK_50M,
+
+    //Async reset from top-level module.
+    //Can be used as initial reset.
+    input         RESET,
+
+    //Must be passed to hps_io module
+    inout  [44:0] HPS_BUS,
+
+    //Base video clock. Usually equals to CLK_SYS.
+    output        CLK_VIDEO,
+
+    //Multiple resolutions are supported using different CE_PIXEL rates.
+    //Must be based on CLK_VIDEO
+    output        CE_PIXEL,
+
+    //Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
+    output  [7:0] VIDEO_ARX,
+    output  [7:0] VIDEO_ARY,
+
+    // These video signals are defined in sys_top.v, via the video_mixer we output the video from the emulator onto these
+    // signals, which then get passed as follows:
+    // emu -> video_mixer -> vga_osd -> vga_out
+    output  [7:0] VGA_R,
+    output  [7:0] VGA_G,
+    output  [7:0] VGA_B,
+    output        VGA_HS,
+    output        VGA_VS,
+    output        VGA_DE,    // = ~(VBlank | HBlank)
+
+    output        LED_USER,  // 1 - ON, 0 - OFF.
+
+    // b[1]: 0 - LED status is system status OR'd with b[0]
+    //       1 - LED status is controled solely by b[0]
+    // hint: supply 2'b00 to let the system control the LED.
+    output  [1:0] LED_POWER,
+    output  [1:0] LED_DISK,
+    output  [7:0] LED_MB,
+
+    output [15:0] AUDIO_L,
+    output [15:0] AUDIO_R,
+    output        AUDIO_S, // 1 - signed audio samples, 0 - unsigned
+    output  [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
+//  input         TAPE_IN,
+
+    // SD-SPI
+    output        SD_SCK,
+    output        SD_MOSI,
+    input         SD_MISO,
+    output        SD_CS,
+    input         SD_CD,
+
+    //High latency DDR3 RAM interface
+    //Use for non-critical time purposes
+    output        DDRAM_CLK,
+    input         DDRAM_BUSY,
+    output  [7:0] DDRAM_BURSTCNT,
+    output [28:0] DDRAM_ADDR,
+    input  [63:0] DDRAM_DOUT,
+    input         DDRAM_DOUT_READY,
+    output        DDRAM_RD,
+    output [63:0] DDRAM_DIN,
+    output  [7:0] DDRAM_BE,
+    output        DDRAM_WE,
+
+    //SDRAM interface with lower latency
+//  ,output        SDRAM_CLK,
+//  output        SDRAM_CKE,
+//  output [12:0] SDRAM_A,
+//  output  [1:0] SDRAM_BA,
+//  inout  [15:0] SDRAM_DQ,
+//  output        SDRAM_DQML,
+//  output        SDRAM_DQMH,
+//  output        SDRAM_nCS,
+//  output        SDRAM_nCAS,
+//  output        SDRAM_nRAS,
+//  output        SDRAM_nWE
+    input         UART_RX,
+    output        UART_TX
+);
+
+//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
+//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
+assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
+ 
+assign LED_USER  = ioctl_download;
+assign LED_DISK  = 0;
+assign LED_POWER = 0;
+
+assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
+assign VIDEO_ARY = status[1] ? 8'd9  : 8'd3; 
+
+wire [2:0] scale = status[4:2];
+
+// Menu is handled in the MiSTer c++ program.
+//
+`include "build_id.v" 
+localparam CONF_STR =
+{
+        "SHARP MZ SERIES;;",
+        "J,Fire;",
+        "V,v1.02.",`BUILD_DATE
+};
+
+/////////////////  CLOCKS  ////////////////////////
+
+wire clk_sys;
+
+/////////////////  HPS  ///////////////////////////
+
+wire [31:0] status;
+wire  [1:0] buttons;
+
+wire [10:0] ps2_key;
+wire [24:0] ps2_mouse;
+
+wire        ioctl_download;
+wire        ioctl_upload;
+wire  [7:0] ioctl_index;
+wire        ioctl_wr;
+wire        ioctl_rd;
+wire [24:0] ioctl_addr;
+wire [15:0] ioctl_dout;
+wire [15:0] ioctl_din;
+wire        forced_scandoubler;
+
+hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io
+(
+    .clk_sys(clk_sys),
+    .HPS_BUS(HPS_BUS),
+
+    .conf_str(CONF_STR),
+
+    .buttons(buttons),
+    .status(status),
+    .forced_scandoubler(forced_scandoubler),
+
+    .ioctl_download(ioctl_download),
+    .ioctl_upload(ioctl_upload),
+    .ioctl_index(ioctl_index),
+    .ioctl_wr(ioctl_wr),
+    .ioctl_rd(ioctl_rd),
+    .ioctl_addr(ioctl_addr),
+    .ioctl_dout(ioctl_dout),
+    .ioctl_din(ioctl_din),
+    .ioctl_wait(0),
+
+    .sd_conf(0),
+    .sd_ack_conf(),
+
+    //.ps2_kbd_led_use(0),
+    //.ps2_kbd_led_status(0),
+
+    .ps2_key(ps2_key),
+    .ps2_mouse(ps2_mouse)
+
+    // unused
+    //.joystick_0(),
+    //.joystick_1(),
+    //.new_vmode(),
+    //.img_mounted(),
+    //.img_readonly(),
+    //.img_size(),
+    //.sd_lba(),
+    //.sd_rd(),
+    //.sd_wr(),
+    //.sd_ack(),
+    //.sd_buff_addr(),
+    //.sd_buff_dout(),
+    //.sd_buff_din(),
+    //.sd_buff_wr(),
+    //.ps2_kbd_clk_out(),
+    //.ps2_kbd_data_out(),
+    //.ps2_kbd_clk_in(),
+    //.ps2_kbd_data_in(),
+    //.ps2_mouse_clk_out(),
+    //.ps2_mouse_data_out(),
+    //.ps2_mouse_data_in(),
+    //.ps2_mouse_clk_in(),
+    //.joystick_analog_0(),
+    //.joystick_analog_1(),
+    //.RTC(),
+    //.TIMESTAMP()
+);
+
+/////////////////  RESET  /////////////////////////
+
+//wire reset = RESET | status[0] | buttons[1] | status[6] | ioctl_download;
+wire reset = RESET;
+wire warm_reset = status[0] | buttons[1]; //| ioctl_download;
+
+////////////////  Machine  ////////////////////////
+
+wire [7:0] audio_l_emu;
+wire [7:0] audio_r_emu;
+assign AUDIO_L = {audio_l_emu,8'd0};
+assign AUDIO_R = {audio_r_emu,8'd0};
+assign AUDIO_S = 1;
+assign AUDIO_MIX = 0;
+
+
+wire clk_video_in;
+wire [7:0] R_emu;
+wire [7:0] G_emu;
+wire [7:0] B_emu;
+wire hblank_emu;
+wire vblank_emu;
+wire hsync_emu;
+wire vsync_emu;
+
+bridge sharp_mz
+(
+        // Clocks Input to Emulator.
+        .clkmaster(CLK_50M),
+
+        // System clock.
+        .clksys(clk_sys),
+
+        // Clocks output by the emulator.
+        .clkvid(clk_video_in),
+
+        // Reset
+        .cold_reset(reset),
+        .warm_reset(warm_reset),
+
+        // LED on MB
+        .main_leds(LED_MB),
+
+        // PS2 via USB.
+        .ps2_key(ps2_key),
+
+        // VGA on IO daughter card.
+        .vga_hb_o(hblank_emu),
+        .vga_vb_o(vblank_emu),
+        .vga_hs_o(hsync_emu),
+        .vga_vs_o(vsync_emu),
+        .vga_r_o(R_emu),
+        .vga_g_o(G_emu),
+        .vga_b_o(B_emu),
+
+        // AUDIO on IO daughter card.
+        .audio_l_o(audio_l_emu),
+        .audio_r_o(audio_r_emu),
+
+        .uart_rx(UART_RX),
+        .uart_tx(UART_TX),
+        .sd_sck(SD_SCK),
+        .sd_mosi(SD_MOSI),
+        .sd_miso(SD_MISO),
+        .sd_cs(SD_CS),
+        .sd_cd(SD_CD),
+
+        // HPS Interface
+        .ioctl_download(ioctl_download),                                        // HPS Downloading to FPGA.
+        .ioctl_upload(ioctl_upload),                                            // HPS Uploading from FPGA.
+        .ioctl_clk(clk_sys),                                                    // HPS I/O Clock.
+        .ioctl_wr(ioctl_wr),                                                    // HPS Write Enable to FPGA.
+        .ioctl_rd(ioctl_rd),                                                    // HPS Read Enable from FPGA.
+        .ioctl_addr(ioctl_addr),                                                // HPS Address in FPGA to write into.
+        .ioctl_dout(ioctl_dout),                                                // HPS Data to be written into FPGA.
+        .ioctl_din(ioctl_din)                                                   // HPS Data to be read into HPS.
+);
+
+// If ce_pix is same as pixel clock, uncomment below and remove CE_PIXEL from .ce_pix_out below.
+//
+//assign CE_PIXEL=1;
+//assign CLK_VIDEO = clk_sys;
+assign CLK_VIDEO = clk_video_in;
+assign CE_PIXEL  = clk_video_in;
+
+assign VGA_R = R_emu;
+assign VGA_G = G_emu;
+assign VGA_B = B_emu;
+assign VGA_VS = vsync_emu;
+assign VGA_HS = hsync_emu;
+assign VGA_DE = ~(vblank_emu | hblank_emu);
+
+//video_mixer #(.HALF_DEPTH(0)) video_mixer
+//video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer
+//(
+//    .clk_sys(clk_sys),
+//    .ce_pix(clk_video_in),                                                      // Video pixel clock from core.
+//    //.ce_pix_out(CE_PIXEL),
+//
+//    .scanlines({scale == 4, scale == 3, scale == 2}),
+//    .scandoubler(scale || forced_scandoubler),
+//    .hq2x(scale==1),
+//
+//    .mono(0),
+//
+//    // Input signals into the mixer, originating from the emulator.
+//    .R(R_emu),
+//    .G(G_emu),
+//    .B(B_emu),
+//
+//    // Positive pulses.
+//    .HSync(hsync_emu),
+//    .VSync(vsync_emu),
+//    .HBlank(hblank_emu),
+//    .VBlank(vblank_emu),
+//
+//    .VGA_R(VGA_R),
+//    .VGA_G(VGA_G),
+//    .VGA_B(VGA_B),
+//    .VGA_VS(VGA_VS),
+//    .VGA_HS(VGA_HS),
+//    .VGA_DE(VGA_DE)
+//
+//    // Outputs of the mixer are bound to the VGA_x signals defined in the sys_top module and passed into this module as parameters.
+//    // These signals then feed the vga_osd -> vga_out modules in systop.v
+//);
+
+// Uncomment below and comment out video_mixer to pass original signal to sys_top.v. 
+// To output original signal, edit sys_top.v and comment out vga_osd and vga_out, uncomment the assign statements.
+//
+//assign VGA_R = R_emu;
+//assign VGA_G = G_emu;
+//assign VGA_B = B_emu;
+//assign VGA_HS = hsync_emu;
+//assign VGA_VS = vsync_emu;
+//assign VGA_DE = ~(vblank_emu | hblank_emu);
+
+endmodule
diff --git a/ioctl.vhd.sav b/ioctl.vhd.sav
new file mode 100644
index 0000000..302bcc4
--- /dev/null
+++ b/ioctl.vhd.sav
@@ -0,0 +1,451 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            ioctl.vhd
+-- Created:         November 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series compatible logic IO Control.
+--                                                     
+--                  This module is the IO control layer which provides io services to the emulation,
+--                  which at time of writing can come from the DE10 Nano HPS or the soft-core NEO430
+--                  microcontroller.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         November 2018 - Initial creation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity ioctl is
+  port(
+        --------------------                Clock Input                         ----------------------------     
+        clkmaster             : in  std_logic;                                  -- Master Clock(50MHz)
+        clksys                : out std_logic;                                  -- System clock.
+        clkvid                : out std_logic;                                  -- Pixel base clock of video.
+        --------------------             Reset                                  ----------------------------
+        cold_reset            : in  std_logic;
+        warm_reset            : in  std_logic;
+        --------------------                     main_leds                      ----------------------------
+        main_leds             : out std_logic_vector(7 downto 0);               -- main_leds Green[7:0]
+        --------------------                     PS2                            ----------------------------
+        ps2_key               : in  std_logic_vector(10 downto 0);              -- PS2 Key data.
+        --------------------                     VGA                            ----------------------------
+        vga_hb_o              : out std_logic;                                  -- VGA Horizontal Blank
+        vga_vb_o              : out std_logic;                                  -- VGA Vertical Blank
+        vga_hs_o              : out std_logic;                                  -- VGA H_SYNC
+        vga_vs_o              : out std_logic;                                  -- VGA V_SYNC
+        vga_r_o               : out std_logic_vector(7 downto 0);               -- VGA Red[3:0], [7:4] = 0
+        vga_g_o               : out std_logic_vector(7 downto 0);               -- VGA Green[3:0]
+        vga_b_o               : out std_logic_vector(7 downto 0);               -- VGA Blue[3:0]
+        --------------------                     AUDIO                          ------------------------------
+        audio_l_o             : out std_logic;
+        audio_r_o             : out std_logic;
+
+        uart_rx               : in  std_logic;
+        uart_tx               : out std_logic; 
+        sd_sck                : out std_logic; 
+        sd_mosi               : out std_logic; 
+        sd_miso               : in  std_logic; 
+        sd_cs                 : out std_logic;
+        sd_cd                 : out std_logic; 
+        --------------------                   HPS Interface                    ------------------------------
+        ioctl_download        : in  std_logic;                                  -- HPS Downloading to FPGA.
+        ioctl_upload          : in  std_logic;                                  -- HPS Uploading from FPGA.
+        ioctl_clk             : in  std_logic;                                  -- HPS I/O Clock.
+        ioctl_wr              : in  std_logic;                                  -- HPS Write Enable to FPGA.
+        ioctl_rd              : in  std_logic;                                  -- HPS Read Enable from FPGA.
+        ioctl_addr            : in  std_logic_vector(24 downto 0);              -- HPS Address in FPGA to write into.
+        ioctl_dout            : in  std_logic_vector(15 downto 0);              -- HPS Data to be written into FPGA.
+        ioctl_din             : out std_logic_vector(15 downto 0)               -- HPS Data to be read into HPS.
+);
+end ioctl;
+
+architecture rtl of ioctl is
+
+--
+-- Signals.
+--
+signal CON_CLKMASTER          :     std_logic;
+signal CON_CLKSYS             :     std_logic;
+signal CON_CLKVID             :     std_logic;
+signal CON_CLKNEO             :     std_logic;
+signal CON_COLD_RESET         :     std_logic;
+signal CON_WARM_RESET         :     std_logic;
+signal CON_MAIN_LEDS          :     std_logic_vector(7 downto 0);
+signal CON_PS2_KEY            :     std_logic_vector(10 downto 0);
+signal CON_VGA_HB_O           :     std_logic;
+signal CON_VGA_VB_O           :     std_logic;
+signal CON_VGA_HS_O           :     std_logic;
+signal CON_VGA_VS_O           :     std_logic;
+signal CON_VGA_R_O            :     std_logic_vector(7 downto 0);
+signal CON_VGA_G_O            :     std_logic_vector(7 downto 0);
+signal CON_VGA_B_O            :     std_logic_vector(7 downto 0);
+signal CON_AUDIO_L_O          :     std_logic;
+signal CON_AUDIO_R_O          :     std_logic;
+signal CON_IOCTL_DOWNLOAD     :     std_logic;
+signal CON_IOCTL_UPLOAD       :     std_logic;
+signal CON_IOCTL_CLK          :     std_logic;
+signal CON_IOCTL_WR           :     std_logic;
+signal CON_IOCTL_RD           :     std_logic;
+signal CON_IOCTL_ADDR         :     std_logic_vector(24 downto 0);
+signal CON_IOCTL_DOUT         :     std_logic_vector(15 downto 0);
+signal CON_IOCTL_DIN          :     std_logic_vector(15 downto 0);
+--
+-- NEO430 Signals.
+--
+signal NEO_IOCTL_DOWNLOAD     :     std_logic;
+signal NEO_IOCTL_UPLOAD       :     std_logic;
+signal NEO_IOCTL_CLK          :     std_logic;
+signal NEO_IOCTL_WR           :     std_logic;
+signal NEO_IOCTL_RD           :     std_logic;
+signal NEO_IOCTL_ADDR         :     std_logic_vector(24 downto 0);
+signal NEO_IOCTL_DOUT         :     std_logic_vector(15 downto 0);
+signal NEO_IOCTL_DIN          :     std_logic_vector(15 downto 0);
+signal NEO_IOCTL_SENSE        :     std_logic;
+signal NEO_IOCTL_SELECT       :     std_logic;
+--
+--
+--
+signal CON_UART_TX            :     std_logic;
+signal CON_UART_RX            :     std_logic;
+signal CON_SPI_SCLK           :     std_logic;
+signal CON_SPI_MOSI           :     std_logic;
+signal CON_SPI_MISO           :     std_logic;
+signal CON_SPI_CS             :     std_logic_vector(7 downto 0);
+--
+-- HPS Control.
+--
+signal MZ_IOCTL_DOWNLOAD      :     std_logic;
+signal MZ_IOCTL_UPLOAD        :     std_logic;
+signal MZ_IOCTL_CLK           :     std_logic;
+signal MZ_IOCTL_WR            :     std_logic;
+signal MZ_IOCTL_RD            :     std_logic;
+signal MZ_IOCTL_ADDR          :     std_logic_vector(24 downto 0);
+signal MZ_IOCTL_DOUT          :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_SYSROM    :     std_logic_vector(7 downto 0);
+signal MZ_IOCTL_DIN_SYSRAM    :     std_logic_vector(7 downto 0);
+signal MZ_IOCTL_DIN_VIDEO     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_MZ80C     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_MZ80B     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_MCTRL     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_CMT       :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_KEY       :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_WENROM        :     std_logic;
+signal MZ_IOCTL_WENRAM        :     std_logic;
+signal MZ_IOCTL_RENROM        :     std_logic;
+signal MZ_IOCTL_RENRAM        :     std_logic;
+
+--
+-- Components
+--
+component sharpmz
+    port (
+        --------------------                Clock Input                         ----------------------------     
+        CLKMASTER             : in  std_logic;                                  -- Master Clock(50MHz)
+        CLKSYS                : out std_logic;                                  -- System clock.
+        CLKVID                : out std_logic;                                  -- Pixel base clock of video.
+        CLKNEO                : out std_logic;                                  -- Neo processor clock.
+        --------------------             Reset                                  ----------------------------
+        COLD_RESET            : in  std_logic;
+        WARM_RESET            : in  std_logic;
+        --------------------                     main_leds                      ----------------------------
+        MAIN_LEDS             : out std_logic_vector(7 downto 0);               -- main_leds Green[7:0]
+        --------------------                     PS2                            ----------------------------
+        PS2_KEY               : in  std_logic_vector(10 downto 0);              -- PS2 Key data.
+        --------------------                     VGA                            ----------------------------
+        VGA_HB_O              : out std_logic;                                  -- VGA Horizontal Blank
+        VGA_VB_O              : out std_logic;                                  -- VGA Vertical Blank
+        VGA_HS_O              : out std_logic;                                  -- VGA H_SYNC
+        VGA_VS_O              : out std_logic;                                  -- VGA V_SYNC
+        VGA_R_O               : out std_logic_vector(7 downto 0);               -- VGA Red[3:0], [7:4] = 0
+        VGA_G_O               : out std_logic_vector(7 downto 0);               -- VGA Green[3:0]
+        VGA_B_O               : out std_logic_vector(7 downto 0);               -- VGA Blue[3:0]
+        --------------------                     AUDIO                          ------------------------------
+        AUDIO_L_O             : out std_logic;
+        AUDIO_R_O             : out std_logic;
+        --------------------                   HPS Interface                    ------------------------------
+        IOCTL_DOWNLOAD        : in  std_logic;                                  -- Downloading to FPGA.
+        IOCTL_UPLOAD          : in  std_logic;                                  -- Uploading from FPGA.
+        IOCTL_CLK             : in  std_logic;                                  -- I/O Clock.
+        IOCTL_WR              : in  std_logic;                                  -- Write Enable to FPGA.
+        IOCTL_RD              : in  std_logic;                                  -- Read Enable from FPGA.
+        IOCTL_ADDR            : in  std_logic_vector(24 downto 0);              -- Address in FPGA to write into.
+        IOCTL_DOUT            : in  std_logic_vector(15 downto 0);              -- Data to be written into FPGA.
+        IOCTL_DIN             : out std_logic_vector(15 downto 0)               -- Data to be read into HPS.
+    );
+end component;
+
+component neo430
+    generic (
+        -- general configuration --
+        CLOCK_SPEED           : natural := 100000000; -- main clock in Hz
+        IMEM_SIZE             : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
+        DMEM_SIZE             : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
+        -- additional configuration --
+        USER_CODE             : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
+        -- module configuration --
+        DADD_USE              : boolean := true; -- implement DADD instruction? (default=true)
+        MULDIV_USE            : boolean := true; -- implement multiplier/divider unit? (default=true)
+        WB32_USE              : boolean := false;-- implement WB32 unit? (default=true)
+        WDT_USE               : boolean := true; -- implement WDT? (default=true)
+        GPIO_USE              : boolean := true; -- implement GPIO unit? (default=true)
+        TIMER_USE             : boolean := true; -- implement timer? (default=true)
+        UART_USE              : boolean := true; -- implement UART? (default=true)
+        CRC_USE               : boolean := false;-- implement CRC unit? (default=true)
+        CFU_USE               : boolean := true; -- implement custom functions unit? (default=false)
+        PWM_USE               : boolean := false;-- implement PWM controller?
+        TWI_USE               : boolean := false;-- implement two wire serial interface? (default=true)
+        SPI_USE               : boolean := true; -- implement SPI? (default=true)
+        -- boot configuration --
+        BOOTLD_USE            : boolean := true; -- implement and use bootloader? (default=true)
+        IMEM_AS_ROM           : boolean := false -- implement IMEM as read-only memory? (default=false)
+   );
+    port (
+        -- global control --
+        clk_i                 : in  std_logic; -- global clock, rising edge
+        rst_i                 : in  std_logic; -- global reset, async, low-active
+        -- gpio --
+        gpio_o                : out std_logic_vector(15 downto 0); -- parallel output
+        gpio_i                : in  std_logic_vector(15 downto 0); -- parallel input
+        -- pwm channels --
+        pwm_o                 : out std_logic_vector(02 downto 0); -- pwm channels
+        -- serial com --
+        uart_txd_o            : out std_logic; -- UART send data
+        uart_rxd_i            : in  std_logic; -- UART receive data
+        spi_sclk_o            : out std_logic; -- serial clock line
+        spi_mosi_o            : out std_logic; -- serial data line out
+        spi_miso_i            : in  std_logic; -- serial data line in
+        spi_cs_o              : out std_logic_vector(07 downto 0); -- SPI CS 0..7
+        twi_sda_io            : inout std_logic; -- twi serial data line
+        twi_scl_io            : inout std_logic; -- twi serial clock line
+        -- IOCTL Bus --
+        ioctl_download        : out std_logic;                                  -- Downloading to FPGA.
+        ioctl_upload          : out std_logic;                                  -- Uploading from FPGA.
+        ioctl_clk             : out std_logic;                                  -- I/O Clock.
+        ioctl_wr              : out std_logic;                                  -- Write Enable to FPGA.
+        ioctl_rd              : out std_logic;                                  -- Read Enable from FPGA.
+        ioctl_sense           : in  std_logic;                                  -- Sense to see if HPS accessing ioctl bus.
+        ioctl_select          : out std_logic;                                  -- Enable CFU control over ioctl bus.
+        ioctl_addr            : out std_logic_vector(24 downto 0);              -- Address in FPGA to write into.
+        ioctl_dout            : out std_logic_vector(15 downto 0);              -- Data to be written into FPGA.
+        ioctl_din             : in  std_logic_vector(15 downto 0);              -- Data to be read into HPS.
+        -- 32-bit wishbone interface --
+        wb_adr_o              : out std_logic_vector(31 downto 0); -- address
+        wb_dat_i              : in  std_logic_vector(31 downto 0); -- read data
+        wb_dat_o              : out std_logic_vector(31 downto 0); -- write data
+        wb_we_o               : out std_logic; -- read/write
+        wb_sel_o              : out std_logic_vector(03 downto 0); -- byte enable
+        wb_stb_o              : out std_logic; -- strobe
+        wb_cyc_o              : out std_logic; -- valid cycle
+        wb_ack_i              : in  std_logic; -- transfer acknowledge
+        -- interrupts --
+        irq_i                 : in  std_logic; -- external interrupt request line
+        irq_ack_o             : out std_logic  -- external interrupt request acknowledge
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    SHARPMZ_0 : sharpmz
+        port map (
+            --------------------                Clock Input                         ----------------------------     
+            CLKMASTER             => CON_CLKMASTER,                                 -- Master Clock(50MHz)
+            CLKSYS                => CON_CLKSYS,                                    -- System clock.
+            CLKVID                => CON_CLKVID,                                    -- Pixel base clock of video.
+            CLKNEO                => CON_CLKNEO,                                    -- Neo Clock.
+            --------------------                                                    ----------------------------
+            COLD_RESET            => CON_COLD_RESET,
+            WARM_RESET            => CON_WARM_RESET,
+            --------------------                                                    ----------------------------
+            MAIN_LEDS             => CON_MAIN_LEDS,                                 -- main_leds Green[7:0]
+            --------------------                                                    ----------------------------
+            PS2_KEY               => CON_PS2_KEY,                                   -- PS2 Key data.
+            --------------------                                                    ----------------------------
+            VGA_HB_O              => CON_VGA_HB_O,                                  -- VGA Horizontal Blank
+            VGA_VB_O              => CON_VGA_VB_O,                                  -- VGA Vertical Blank
+            VGA_HS_O              => CON_VGA_HS_O,                                  -- VGA H_SYNC
+            VGA_VS_O              => CON_VGA_VS_O,                                  -- VGA V_SYNC
+            VGA_R_O               => CON_VGA_R_O,                                   -- VGA Red[3:0], [7:4] = 0
+            VGA_G_O               => CON_VGA_G_O,                                   -- VGA Green[3:0]
+            VGA_B_O               => CON_VGA_B_O,                                   -- VGA Blue[3:0]
+            --------------------                                                    ------------------------------
+            AUDIO_L_O             => CON_AUDIO_L_O,
+            AUDIO_R_O             => CON_AUDIO_R_O,
+            --------------------                                                    ------------------------------
+            IOCTL_DOWNLOAD        => CON_IOCTL_DOWNLOAD,                            -- Downloading to FPGA.
+            IOCTL_UPLOAD          => CON_IOCTL_UPLOAD,                              -- Uploading from FPGA.
+            IOCTL_CLK             => CON_IOCTL_CLK,                                 -- I/O Clock.
+            IOCTL_WR              => CON_IOCTL_WR,                                  -- Write Enable to FPGA.
+            IOCTL_RD              => CON_IOCTL_RD,                                  -- Read Enable from FPGA.
+            IOCTL_ADDR            => CON_IOCTL_ADDR,                                -- Address in FPGA to write into.
+            IOCTL_DOUT            => CON_IOCTL_DOUT,                                -- Data to be written into FPGA.
+            IOCTL_DIN             => CON_IOCTL_DIN                                  -- Data to be read into HPS.
+    );
+
+    -- If enabled, instantiate the local IO processor to provide IO and user interface services.
+    --
+    NEO430_ENABLE: if NEO_ENABLE = 1 generate
+      NEO430_0 : neo430
+        generic map (
+            -- general configuration --
+            CLOCK_SPEED           => 64000000,                                      -- main clock in Hz
+            IMEM_SIZE             => 48*1024,                                       -- internal IMEM size in bytes, max 48kB (default=4kB)
+            DMEM_SIZE             => 12*1024,                                       -- internal DMEM size in bytes, max 12kB (default=2kB)
+            -- additional configuration --
+            USER_CODE             => x"0000",                                       -- custom user code
+            -- module configuration --
+            DADD_USE              => true,                                          -- implement DADD instruction? (default=true)
+            MULDIV_USE            => true,                                          -- implement multiplier/divider unit? (default=true)
+            WB32_USE              => false,                                         -- implement WB32 unit? (default=true)
+            WDT_USE               => true,                                          -- implement WDT? (default=true)
+            GPIO_USE              => true,                                          -- implement GPIO unit? (default=true)
+            TIMER_USE             => true,                                          -- implement timer? (default=true)
+            UART_USE              => true,                                          -- implement UART? (default=true)
+            CRC_USE               => true,                                          -- implement CRC unit? (default=true)
+            CFU_USE               => true,                                          -- implement custom functions unit? (default=false)
+            PWM_USE               => true,                                          -- implement PWM controller?
+            TWI_USE               => true,                                          -- implement two wire serial interface? (default=true)
+            SPI_USE               => true,                                          -- implement SPI? (default=true)
+            -- boot configuration --
+            BOOTLD_USE            => true,                                          -- implement and use bootloader? (default=true)
+            IMEM_AS_ROM           => false                                          -- implement IMEM as read-only memory? (default=false)
+        )
+        port map (
+            -- global control --
+            clk_i                 => CON_CLKNEO,                                    -- global clock, rising edge
+            rst_i                 => not (CON_COLD_RESET or CON_WARM_RESET),        -- global reset, async, low-active
+            -- gpio --
+            gpio_o                => open,                                          -- parallel output
+            gpio_i                => X"0000",                                       -- parallel input
+            -- pwm channels --
+            pwm_o                 => open,                                          -- pwm channels
+            -- serial com --
+            uart_txd_o            => CON_UART_TX,                                   -- UART send data
+            uart_rxd_i            => CON_UART_RX,                                   -- UART receive data
+            spi_sclk_o            => CON_SPI_SCLK,                                  -- serial clock line
+            spi_mosi_o            => CON_SPI_MOSI,                                  -- serial data line out
+            spi_miso_i            => CON_SPI_MISO,                                  -- serial data line in
+            spi_cs_o              => CON_SPI_CS,                                    -- SPI CS 0..7
+            twi_sda_io            => 'H',                                           -- twi serial data line
+            twi_scl_io            => 'H',                                           -- twi serial clock line
+            -- IOCTL Bus --
+            ioctl_download        => NEO_IOCTL_DOWNLOAD,                            -- Downloading to FPGA.
+            ioctl_upload          => NEO_IOCTL_UPLOAD,                              -- Uploading from FPGA.
+            ioctl_clk             => NEO_IOCTL_CLK,                                 -- I/O Clock.
+            ioctl_wr              => NEO_IOCTL_WR,                                  -- Write Enable to FPGA.
+            ioctl_rd              => NEO_IOCTL_RD,                                  -- Read Enable from FPGA.
+            ioctl_sense           => NEO_IOCTL_SENSE,                               -- Sense to see if HPS accessing ioctl bus.
+            ioctl_select          => NEO_IOCTL_SELECT,                              -- Enable CFU control over ioctl bus.
+            ioctl_addr            => NEO_IOCTL_ADDR,                                -- Address in FPGA to write into.
+            ioctl_dout            => NEO_IOCTL_DOUT,                                -- Data to be written into FPGA.
+            ioctl_din             => NEO_IOCTL_DIN,                                 -- Data to be read into HPS.
+            -- 32-bit wishbone interface --
+            wb_adr_o              => open,                                          -- address
+            wb_dat_i              => (others => '0'),                               -- read data
+            wb_dat_o              => open,                                          -- write data
+            wb_we_o               => open,                                          -- read/write
+            wb_sel_o              => open,                                          -- byte enable
+            wb_stb_o              => open,                                          -- strobe
+            wb_cyc_o              => open,                                          -- valid cycle
+            wb_ack_i              => '0',                                           -- transfer acknowledge
+            -- interrupts --
+            irq_i                 => '0',                                           -- external interrupt request line
+            irq_ack_o             => open                                           -- external interrupt request acknowledge
+        );
+    end generate;
+
+    -- If the Neo430 IO Processor is disabled, set the signals to inactive.
+    --
+    NEO430_DISABLE: if NEO_ENABLE = 0 generate
+        NEO_IOCTL_DOWNLOAD        <= '0';
+        NEO_IOCTL_UPLOAD          <= '0';
+        NEO_IOCTL_CLK             <= '0';
+        NEO_IOCTL_WR              <= '0';
+        NEO_IOCTL_RD              <= '0';
+        NEO_IOCTL_ADDR            <= (others => '0');
+        NEO_IOCTL_DOUT            <= (others => '0');
+        --NEO_IOCTL_DIN             => open;
+        --NEO_IOCTL_SENSE           => open;
+        NEO_IOCTL_SELECT          <= '0';
+    end generate;
+
+    -- Assign signals from the emu onto local wires.
+    --
+    CON_CLKMASTER                 <= clkmaster; 
+    clksys                        <= CON_CLKSYS;
+    clkvid                        <= CON_CLKVID;
+    CON_COLD_RESET                <= cold_reset; 
+    CON_WARM_RESET                <= warm_reset; 
+    main_leds                     <= CON_MAIN_LEDS;
+    CON_PS2_KEY                   <= ps2_key; 
+    vga_hb_o                      <= CON_VGA_HB_O;
+    vga_vb_o                      <= CON_VGA_VB_O;
+    vga_hs_o                      <= CON_VGA_HS_O;
+    vga_vs_o                      <= CON_VGA_VS_O;
+    vga_r_o                       <= CON_VGA_R_O;
+    vga_g_o                       <= CON_VGA_G_O;
+    vga_b_o                       <= CON_VGA_B_O;
+    audio_l_o                     <= CON_AUDIO_L_O;
+    audio_r_o                     <= CON_AUDIO_R_O;
+
+    uart_tx                       <= CON_UART_TX;
+    CON_UART_RX                   <= uart_rx;
+    sd_sck                        <= CON_SPI_SCLK;
+    sd_mosi                       <= CON_SPI_MOSI;
+    CON_SPI_MISO                  <= sd_miso;
+    sd_cs                         <= CON_SPI_CS(0);
+    --
+    -- Multiplexer, default IO control to the HPS unless the NEO is enabled and selects. 
+    -- The NEO430 first senses to ensure there is no activity on the bus, then takes control
+    --
+    CON_IOCTL_DOWNLOAD            <= ioctl_download when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_DOWNLOAD; 
+    CON_IOCTL_UPLOAD              <= ioctl_upload   when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_UPLOAD; 
+    CON_IOCTL_CLK                 <= ioctl_clk      when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_CLK; 
+    CON_IOCTL_WR                  <= ioctl_wr       when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_WR; 
+    CON_IOCTL_RD                  <= ioctl_rd       when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_RD; 
+    CON_IOCTL_ADDR                <= ioctl_addr     when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_ADDR; 
+    CON_IOCTL_DOUT                <= ioctl_dout     when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_DOUT; 
+    ioctl_din                     <= CON_IOCTL_DIN  when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_DIN;
+    NEO_IOCTL_SENSE               <= ioctl_download or ioctl_upload or ioctl_wr or ioctl_rd;
+
+end rtl;
diff --git a/ioctl_neo430.vhd b/ioctl_neo430.vhd
new file mode 100644
index 0000000..bc6d0ed
--- /dev/null
+++ b/ioctl_neo430.vhd
@@ -0,0 +1,451 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            ioctl.vhd
+-- Created:         November 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series compatible logic IO Control.
+--                                                     
+--                  This module is the IO control layer which provides io services to the emulation,
+--                  which at time of writing can come from the DE10 Nano HPS or the soft-core NEO430
+--                  microcontroller.
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         November 2018 - Initial creation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity ioctl is
+  port(
+        --------------------                Clock Input                         ----------------------------     
+        clkmaster             : in  std_logic;                                  -- Master Clock(50MHz)
+        clksys                : out std_logic;                                  -- System clock.
+        clkvid                : out std_logic;                                  -- Pixel base clock of video.
+        --------------------             Reset                                  ----------------------------
+        cold_reset            : in  std_logic;
+        warm_reset            : in  std_logic;
+        --------------------                     main_leds                      ----------------------------
+        main_leds             : out std_logic_vector(7 downto 0);               -- main_leds Green[7:0]
+        --------------------                     PS2                            ----------------------------
+        ps2_key               : in  std_logic_vector(10 downto 0);              -- PS2 Key data.
+        --------------------                     VGA                            ----------------------------
+        vga_hb_o              : out std_logic;                                  -- VGA Horizontal Blank
+        vga_vb_o              : out std_logic;                                  -- VGA Vertical Blank
+        vga_hs_o              : out std_logic;                                  -- VGA H_SYNC
+        vga_vs_o              : out std_logic;                                  -- VGA V_SYNC
+        vga_r_o               : out std_logic_vector(7 downto 0);               -- VGA Red[3:0], [7:4] = 0
+        vga_g_o               : out std_logic_vector(7 downto 0);               -- VGA Green[3:0]
+        vga_b_o               : out std_logic_vector(7 downto 0);               -- VGA Blue[3:0]
+        --------------------                     AUDIO                          ------------------------------
+        audio_l_o             : out std_logic;
+        audio_r_o             : out std_logic;
+
+        uart_rx               : in  std_logic;
+        uart_tx               : out std_logic; 
+        sd_sck                : out std_logic; 
+        sd_mosi               : out std_logic; 
+        sd_miso               : in  std_logic; 
+        sd_cs                 : out std_logic;
+        sd_cd                 : out std_logic; 
+        --------------------                   HPS Interface                    ------------------------------
+        ioctl_download        : in  std_logic;                                  -- HPS Downloading to FPGA.
+        ioctl_upload          : in  std_logic;                                  -- HPS Uploading from FPGA.
+        ioctl_clk             : in  std_logic;                                  -- HPS I/O Clock.
+        ioctl_wr              : in  std_logic;                                  -- HPS Write Enable to FPGA.
+        ioctl_rd              : in  std_logic;                                  -- HPS Read Enable from FPGA.
+        ioctl_addr            : in  std_logic_vector(24 downto 0);              -- HPS Address in FPGA to write into.
+        ioctl_dout            : in  std_logic_vector(15 downto 0);              -- HPS Data to be written into FPGA.
+        ioctl_din             : out std_logic_vector(15 downto 0)               -- HPS Data to be read into HPS.
+);
+end ioctl;
+
+architecture rtl of ioctl is
+
+--
+-- Signals.
+--
+signal CON_CLKMASTER          :     std_logic;
+signal CON_CLKSYS             :     std_logic;
+signal CON_CLKVID             :     std_logic;
+signal CON_CLKNEO             :     std_logic;
+signal CON_COLD_RESET         :     std_logic;
+signal CON_WARM_RESET         :     std_logic;
+signal CON_MAIN_LEDS          :     std_logic_vector(7 downto 0);
+signal CON_PS2_KEY            :     std_logic_vector(10 downto 0);
+signal CON_VGA_HB_O           :     std_logic;
+signal CON_VGA_VB_O           :     std_logic;
+signal CON_VGA_HS_O           :     std_logic;
+signal CON_VGA_VS_O           :     std_logic;
+signal CON_VGA_R_O            :     std_logic_vector(7 downto 0);
+signal CON_VGA_G_O            :     std_logic_vector(7 downto 0);
+signal CON_VGA_B_O            :     std_logic_vector(7 downto 0);
+signal CON_AUDIO_L_O          :     std_logic;
+signal CON_AUDIO_R_O          :     std_logic;
+signal CON_IOCTL_DOWNLOAD     :     std_logic;
+signal CON_IOCTL_UPLOAD       :     std_logic;
+signal CON_IOCTL_CLK          :     std_logic;
+signal CON_IOCTL_WR           :     std_logic;
+signal CON_IOCTL_RD           :     std_logic;
+signal CON_IOCTL_ADDR         :     std_logic_vector(24 downto 0);
+signal CON_IOCTL_DOUT         :     std_logic_vector(15 downto 0);
+signal CON_IOCTL_DIN          :     std_logic_vector(15 downto 0);
+--
+-- NEO430 Signals.
+--
+signal NEO_IOCTL_DOWNLOAD     :     std_logic;
+signal NEO_IOCTL_UPLOAD       :     std_logic;
+signal NEO_IOCTL_CLK          :     std_logic;
+signal NEO_IOCTL_WR           :     std_logic;
+signal NEO_IOCTL_RD           :     std_logic;
+signal NEO_IOCTL_ADDR         :     std_logic_vector(24 downto 0);
+signal NEO_IOCTL_DOUT         :     std_logic_vector(15 downto 0);
+signal NEO_IOCTL_DIN          :     std_logic_vector(15 downto 0);
+signal NEO_IOCTL_SENSE        :     std_logic;
+signal NEO_IOCTL_SELECT       :     std_logic;
+--
+--
+--
+signal CON_UART_TX            :     std_logic;
+signal CON_UART_RX            :     std_logic;
+signal CON_SPI_SCLK           :     std_logic;
+signal CON_SPI_MOSI           :     std_logic;
+signal CON_SPI_MISO           :     std_logic;
+signal CON_SPI_CS             :     std_logic_vector(7 downto 0);
+--
+-- HPS Control.
+--
+signal MZ_IOCTL_DOWNLOAD      :     std_logic;
+signal MZ_IOCTL_UPLOAD        :     std_logic;
+signal MZ_IOCTL_CLK           :     std_logic;
+signal MZ_IOCTL_WR            :     std_logic;
+signal MZ_IOCTL_RD            :     std_logic;
+signal MZ_IOCTL_ADDR          :     std_logic_vector(24 downto 0);
+signal MZ_IOCTL_DOUT          :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_SYSROM    :     std_logic_vector(7 downto 0);
+signal MZ_IOCTL_DIN_SYSRAM    :     std_logic_vector(7 downto 0);
+signal MZ_IOCTL_DIN_VIDEO     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_MZ80C     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_MZ80B     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_MCTRL     :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_CMT       :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_DIN_KEY       :     std_logic_vector(15 downto 0);
+signal MZ_IOCTL_WENROM        :     std_logic;
+signal MZ_IOCTL_WENRAM        :     std_logic;
+signal MZ_IOCTL_RENROM        :     std_logic;
+signal MZ_IOCTL_RENRAM        :     std_logic;
+
+--
+-- Components
+--
+component sharpmz
+    port (
+        --------------------                Clock Input                         ----------------------------     
+        CLKMASTER             : in  std_logic;                                  -- Master Clock(50MHz)
+        CLKSYS                : out std_logic;                                  -- System clock.
+        CLKVID                : out std_logic;                                  -- Pixel base clock of video.
+        CLKNEO                : out std_logic;                                  -- Neo processor clock.
+        --------------------             Reset                                  ----------------------------
+        COLD_RESET            : in  std_logic;
+        WARM_RESET            : in  std_logic;
+        --------------------                     main_leds                      ----------------------------
+        MAIN_LEDS             : out std_logic_vector(7 downto 0);               -- main_leds Green[7:0]
+        --------------------                     PS2                            ----------------------------
+        PS2_KEY               : in  std_logic_vector(10 downto 0);              -- PS2 Key data.
+        --------------------                     VGA                            ----------------------------
+        VGA_HB_O              : out std_logic;                                  -- VGA Horizontal Blank
+        VGA_VB_O              : out std_logic;                                  -- VGA Vertical Blank
+        VGA_HS_O              : out std_logic;                                  -- VGA H_SYNC
+        VGA_VS_O              : out std_logic;                                  -- VGA V_SYNC
+        VGA_R_O               : out std_logic_vector(7 downto 0);               -- VGA Red[3:0], [7:4] = 0
+        VGA_G_O               : out std_logic_vector(7 downto 0);               -- VGA Green[3:0]
+        VGA_B_O               : out std_logic_vector(7 downto 0);               -- VGA Blue[3:0]
+        --------------------                     AUDIO                          ------------------------------
+        AUDIO_L_O             : out std_logic;
+        AUDIO_R_O             : out std_logic;
+        --------------------                   HPS Interface                    ------------------------------
+        IOCTL_DOWNLOAD        : in  std_logic;                                  -- Downloading to FPGA.
+        IOCTL_UPLOAD          : in  std_logic;                                  -- Uploading from FPGA.
+        IOCTL_CLK             : in  std_logic;                                  -- I/O Clock.
+        IOCTL_WR              : in  std_logic;                                  -- Write Enable to FPGA.
+        IOCTL_RD              : in  std_logic;                                  -- Read Enable from FPGA.
+        IOCTL_ADDR            : in  std_logic_vector(24 downto 0);              -- Address in FPGA to write into.
+        IOCTL_DOUT            : in  std_logic_vector(15 downto 0);              -- Data to be written into FPGA.
+        IOCTL_DIN             : out std_logic_vector(15 downto 0)               -- Data to be read into HPS.
+    );
+end component;
+
+component neo430
+    generic (
+        -- general configuration --
+        CLOCK_SPEED           : natural := 100000000; -- main clock in Hz
+        IMEM_SIZE             : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
+        DMEM_SIZE             : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
+        -- additional configuration --
+        USER_CODE             : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
+        -- module configuration --
+        DADD_USE              : boolean := true; -- implement DADD instruction? (default=true)
+        MULDIV_USE            : boolean := true; -- implement multiplier/divider unit? (default=true)
+        WB32_USE              : boolean := false;-- implement WB32 unit? (default=true)
+        WDT_USE               : boolean := true; -- implement WDT? (default=true)
+        GPIO_USE              : boolean := true; -- implement GPIO unit? (default=true)
+        TIMER_USE             : boolean := true; -- implement timer? (default=true)
+        UART_USE              : boolean := true; -- implement UART? (default=true)
+        CRC_USE               : boolean := true; -- implement CRC unit? (default=true)
+        CFU_USE               : boolean := true; -- implement custom functions unit? (default=false)
+        PWM_USE               : boolean := true; -- implement PWM controller?
+        TWI_USE               : boolean := true; -- implement two wire serial interface? (default=true)
+        SPI_USE               : boolean := true; -- implement SPI? (default=true)
+        -- boot configuration --
+        BOOTLD_USE            : boolean := true; -- implement and use bootloader? (default=true)
+        IMEM_AS_ROM           : boolean := false -- implement IMEM as read-only memory? (default=false)
+   );
+    port (
+        -- global control --
+        clk_i                 : in  std_logic; -- global clock, rising edge
+        rst_i                 : in  std_logic; -- global reset, async, low-active
+        -- gpio --
+        gpio_o                : out std_logic_vector(15 downto 0); -- parallel output
+        gpio_i                : in  std_logic_vector(15 downto 0); -- parallel input
+        -- pwm channels --
+        pwm_o                 : out std_logic_vector(02 downto 0); -- pwm channels
+        -- serial com --
+        uart_txd_o            : out std_logic; -- UART send data
+        uart_rxd_i            : in  std_logic; -- UART receive data
+        spi_sclk_o            : out std_logic; -- serial clock line
+        spi_mosi_o            : out std_logic; -- serial data line out
+        spi_miso_i            : in  std_logic; -- serial data line in
+        spi_cs_o              : out std_logic_vector(07 downto 0); -- SPI CS 0..7
+        twi_sda_io            : inout std_logic; -- twi serial data line
+        twi_scl_io            : inout std_logic; -- twi serial clock line
+        -- IOCTL Bus --
+        ioctl_download        : out std_logic;                                  -- Downloading to FPGA.
+        ioctl_upload          : out std_logic;                                  -- Uploading from FPGA.
+        ioctl_clk             : out std_logic;                                  -- I/O Clock.
+        ioctl_wr              : out std_logic;                                  -- Write Enable to FPGA.
+        ioctl_rd              : out std_logic;                                  -- Read Enable from FPGA.
+        ioctl_sense           : in  std_logic;                                  -- Sense to see if HPS accessing ioctl bus.
+        ioctl_select          : out std_logic;                                  -- Enable CFU control over ioctl bus.
+        ioctl_addr            : out std_logic_vector(24 downto 0);              -- Address in FPGA to write into.
+        ioctl_dout            : out std_logic_vector(15 downto 0);              -- Data to be written into FPGA.
+        ioctl_din             : in  std_logic_vector(15 downto 0);              -- Data to be read into HPS.
+        -- 32-bit wishbone interface --
+        wb_adr_o              : out std_logic_vector(31 downto 0); -- address
+        wb_dat_i              : in  std_logic_vector(31 downto 0); -- read data
+        wb_dat_o              : out std_logic_vector(31 downto 0); -- write data
+        wb_we_o               : out std_logic; -- read/write
+        wb_sel_o              : out std_logic_vector(03 downto 0); -- byte enable
+        wb_stb_o              : out std_logic; -- strobe
+        wb_cyc_o              : out std_logic; -- valid cycle
+        wb_ack_i              : in  std_logic; -- transfer acknowledge
+        -- interrupts --
+        irq_i                 : in  std_logic; -- external interrupt request line
+        irq_ack_o             : out std_logic  -- external interrupt request acknowledge
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    SHARPMZ_0 : sharpmz
+        port map (
+            --------------------                Clock Input                         ----------------------------     
+            CLKMASTER             => CON_CLKMASTER,                                 -- Master Clock(50MHz)
+            CLKSYS                => CON_CLKSYS,                                    -- System clock.
+            CLKVID                => CON_CLKVID,                                    -- Pixel base clock of video.
+            CLKNEO                => CON_CLKNEO,                                    -- Neo Clock.
+            --------------------                                                    ----------------------------
+            COLD_RESET            => CON_COLD_RESET,
+            WARM_RESET            => CON_WARM_RESET,
+            --------------------                                                    ----------------------------
+            MAIN_LEDS             => CON_MAIN_LEDS,                                 -- main_leds Green[7:0]
+            --------------------                                                    ----------------------------
+            PS2_KEY               => CON_PS2_KEY,                                   -- PS2 Key data.
+            --------------------                                                    ----------------------------
+            VGA_HB_O              => CON_VGA_HB_O,                                  -- VGA Horizontal Blank
+            VGA_VB_O              => CON_VGA_VB_O,                                  -- VGA Vertical Blank
+            VGA_HS_O              => CON_VGA_HS_O,                                  -- VGA H_SYNC
+            VGA_VS_O              => CON_VGA_VS_O,                                  -- VGA V_SYNC
+            VGA_R_O               => CON_VGA_R_O,                                   -- VGA Red[3:0], [7:4] = 0
+            VGA_G_O               => CON_VGA_G_O,                                   -- VGA Green[3:0]
+            VGA_B_O               => CON_VGA_B_O,                                   -- VGA Blue[3:0]
+            --------------------                                                    ------------------------------
+            AUDIO_L_O             => CON_AUDIO_L_O,
+            AUDIO_R_O             => CON_AUDIO_R_O,
+            --------------------                                                    ------------------------------
+            IOCTL_DOWNLOAD        => CON_IOCTL_DOWNLOAD,                            -- Downloading to FPGA.
+            IOCTL_UPLOAD          => CON_IOCTL_UPLOAD,                              -- Uploading from FPGA.
+            IOCTL_CLK             => CON_IOCTL_CLK,                                 -- I/O Clock.
+            IOCTL_WR              => CON_IOCTL_WR,                                  -- Write Enable to FPGA.
+            IOCTL_RD              => CON_IOCTL_RD,                                  -- Read Enable from FPGA.
+            IOCTL_ADDR            => CON_IOCTL_ADDR,                                -- Address in FPGA to write into.
+            IOCTL_DOUT            => CON_IOCTL_DOUT,                                -- Data to be written into FPGA.
+            IOCTL_DIN             => CON_IOCTL_DIN                                  -- Data to be read into HPS.
+    );
+
+    -- If enabled, instantiate the local IO processor to provide IO and user interface services.
+    --
+    NEO430_ENABLE: if NEO_ENABLE = 1 generate
+      NEO430_0 : neo430
+        generic map (
+            -- general configuration --
+            CLOCK_SPEED           => 64000000,                                      -- main clock in Hz
+            IMEM_SIZE             => 48*1024,                                       -- internal IMEM size in bytes, max 48kB (default=4kB)
+            DMEM_SIZE             => 12*1024,                                       -- internal DMEM size in bytes, max 12kB (default=2kB)
+            -- additional configuration --
+            USER_CODE             => x"0000",                                       -- custom user code
+            -- module configuration --
+            DADD_USE              => true,                                          -- implement DADD instruction? (default=true)
+            MULDIV_USE            => true,                                          -- implement multiplier/divider unit? (default=true)
+            WB32_USE              => false,                                         -- implement WB32 unit? (default=true)
+            WDT_USE               => true,                                          -- implement WDT? (default=true)
+            GPIO_USE              => true,                                          -- implement GPIO unit? (default=true)
+            TIMER_USE             => true,                                          -- implement timer? (default=true)
+            UART_USE              => true,                                          -- implement UART? (default=true)
+            CRC_USE               => false,                                         -- implement CRC unit? (default=true)
+            CFU_USE               => false,                                         -- implement custom functions unit? (default=false)
+            PWM_USE               => true,                                          -- implement PWM controller?
+            TWI_USE               => false,                                         -- implement two wire serial interface? (default=true)
+            SPI_USE               => true,                                          -- implement SPI? (default=true)
+            -- boot configuration --
+            BOOTLD_USE            => true,                                          -- implement and use bootloader? (default=true)
+            IMEM_AS_ROM           => false                                          -- implement IMEM as read-only memory? (default=false)
+        )
+        port map (
+            -- global control --
+            clk_i                 => CON_CLKNEO,                                    -- global clock, rising edge
+            rst_i                 => not (CON_COLD_RESET or CON_WARM_RESET),        -- global reset, async, low-active
+            -- gpio --
+            gpio_o                => open,                                          -- parallel output
+            gpio_i                => X"0000",                                       -- parallel input
+            -- pwm channels --
+            pwm_o                 => open,                                          -- pwm channels
+            -- serial com --
+            uart_txd_o            => CON_UART_TX,                                   -- UART send data
+            uart_rxd_i            => CON_UART_RX,                                   -- UART receive data
+            spi_sclk_o            => CON_SPI_SCLK,                                  -- serial clock line
+            spi_mosi_o            => CON_SPI_MOSI,                                  -- serial data line out
+            spi_miso_i            => CON_SPI_MISO,                                  -- serial data line in
+            spi_cs_o              => CON_SPI_CS,                                    -- SPI CS 0..7
+            twi_sda_io            => open,                                          -- twi serial data line
+            twi_scl_io            => open,                                          -- twi serial clock line
+            -- IOCTL Bus --
+            ioctl_download        => NEO_IOCTL_DOWNLOAD,                            -- Downloading to FPGA.
+            ioctl_upload          => NEO_IOCTL_UPLOAD,                              -- Uploading from FPGA.
+            ioctl_clk             => NEO_IOCTL_CLK,                                 -- I/O Clock.
+            ioctl_wr              => NEO_IOCTL_WR,                                  -- Write Enable to FPGA.
+            ioctl_rd              => NEO_IOCTL_RD,                                  -- Read Enable from FPGA.
+            ioctl_sense           => NEO_IOCTL_SENSE,                               -- Sense to see if HPS accessing ioctl bus.
+            ioctl_select          => NEO_IOCTL_SELECT,                              -- Enable CFU control over ioctl bus.
+            ioctl_addr            => NEO_IOCTL_ADDR,                                -- Address in FPGA to write into.
+            ioctl_dout            => NEO_IOCTL_DOUT,                                -- Data to be written into FPGA.
+            ioctl_din             => NEO_IOCTL_DIN,                                 -- Data to be read into HPS.
+            -- 32-bit wishbone interface --
+            wb_adr_o              => open,                                          -- address
+            wb_dat_i              => (others => '0'),                               -- read data
+            wb_dat_o              => open,                                          -- write data
+            wb_we_o               => open,                                          -- read/write
+            wb_sel_o              => open,                                          -- byte enable
+            wb_stb_o              => open,                                          -- strobe
+            wb_cyc_o              => open,                                          -- valid cycle
+            wb_ack_i              => '0',                                           -- transfer acknowledge
+            -- interrupts --
+            irq_i                 => '0',                                           -- external interrupt request line
+            irq_ack_o             => open                                           -- external interrupt request acknowledge
+        );
+    end generate;
+
+    -- If the Neo430 IO Processor is disabled, set the signals to inactive.
+    --
+    NEO430_DISABLE: if NEO_ENABLE = 0 generate
+        NEO_IOCTL_DOWNLOAD        <= '0';
+        NEO_IOCTL_UPLOAD          <= '0';
+        NEO_IOCTL_CLK             <= '0';
+        NEO_IOCTL_WR              <= '0';
+        NEO_IOCTL_RD              <= '0';
+        NEO_IOCTL_ADDR            <= (others => '0');
+        NEO_IOCTL_DOUT            <= (others => '0');
+        --NEO_IOCTL_DIN             => open;
+        --NEO_IOCTL_SENSE           => open;
+        NEO_IOCTL_SELECT          <= '0';
+    end generate;
+
+    -- Assign signals from the emu onto local wires.
+    --
+    CON_CLKMASTER                 <= clkmaster; 
+    clksys                        <= CON_CLKSYS;
+    clkvid                        <= CON_CLKVID;
+    CON_COLD_RESET                <= cold_reset; 
+    CON_WARM_RESET                <= warm_reset; 
+    main_leds                     <= CON_MAIN_LEDS;
+    CON_PS2_KEY                   <= ps2_key; 
+    vga_hb_o                      <= CON_VGA_HB_O;
+    vga_vb_o                      <= CON_VGA_VB_O;
+    vga_hs_o                      <= CON_VGA_HS_O;
+    vga_vs_o                      <= CON_VGA_VS_O;
+    vga_r_o                       <= CON_VGA_R_O;
+    vga_g_o                       <= CON_VGA_G_O;
+    vga_b_o                       <= CON_VGA_B_O;
+    audio_l_o                     <= CON_AUDIO_L_O;
+    audio_r_o                     <= CON_AUDIO_R_O;
+
+    uart_tx                       <= CON_UART_TX;
+    CON_UART_RX                   <= uart_rx;
+    sd_sck                        <= CON_SPI_SCLK;
+    sd_mosi                       <= CON_SPI_MOSI;
+    CON_SPI_MISO                  <= sd_miso;
+    sd_cs                         <= CON_SPI_CS(0);
+    --
+    -- Multiplexer, default IO control to the HPS unless the NEO is enabled and selects. 
+    -- The NEO430 first senses to ensure there is no activity on the bus, then takes control
+    --
+    CON_IOCTL_DOWNLOAD            <= ioctl_download when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_DOWNLOAD; 
+    CON_IOCTL_UPLOAD              <= ioctl_upload   when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_UPLOAD; 
+    CON_IOCTL_CLK                 <= ioctl_clk      when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_CLK; 
+    CON_IOCTL_WR                  <= ioctl_wr       when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_WR; 
+    CON_IOCTL_RD                  <= ioctl_rd       when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_RD; 
+    CON_IOCTL_ADDR                <= ioctl_addr     when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_ADDR; 
+    CON_IOCTL_DOUT                <= ioctl_dout     when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_DOUT; 
+    ioctl_din                     <= CON_IOCTL_DIN  when NEO_IOCTL_SELECT = '0'
+                                     else
+                                     NEO_IOCTL_DIN;
+    NEO_IOCTL_SENSE               <= ioctl_download or ioctl_upload or ioctl_wr or ioctl_rd;
+
+end rtl;
diff --git a/jtag.cdf b/jtag.cdf
new file mode 100644
index 0000000..4278037
--- /dev/null
+++ b/jtag.cdf
@@ -0,0 +1,13 @@
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Ign)
+		Device PartName(SOCVHPS) MfrSpec(OpMask(0));
+	P ActionCode(Cfg)
+		Device PartName(5CSEBA6U23I7) Path("output_files/") File("sharpmz-lite.sof") MfrSpec(OpMask(1));
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/jtag_uart_0.vhd b/jtag_uart_0.vhd
new file mode 100644
index 0000000..512fd36
--- /dev/null
+++ b/jtag_uart_0.vhd
@@ -0,0 +1,1392 @@
+--Legal Notice: (C)2018 Altera Corporation. All rights reserved.  Your
+--use of Altera Corporation's design tools, logic functions and other
+--software and tools, and its AMPP partner logic functions, and any
+--output files any of the foregoing (including device programming or
+--simulation files), and any associated documentation or information are
+--expressly subject to the terms and conditions of the Altera Program
+--License Subscription Agreement or other applicable license agreement,
+--including, without limitation, that your use is for the sole purpose
+--of programming logic devices manufactured by Altera and sold by Altera
+--or its authorized distributors.  Please refer to the applicable
+--agreement for further details.
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library std;
+use std.textio.all;
+
+entity jtag_uart_0_log_module is 
+        port (
+              -- inputs:
+                 signal clk : IN STD_LOGIC;
+                 signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal strobe : IN STD_LOGIC;
+                 signal valid : IN STD_LOGIC
+              );
+end entity jtag_uart_0_log_module;
+
+
+architecture europa of jtag_uart_0_log_module is
+  
+  file text_handle : TEXT ;
+                           
+  -- synthesis translate_off
+  -- purpose: convert 8 bit signal data to 8 bit string
+  FUNCTION bin_to_char(vec_to_convert : STD_LOGIC_VECTOR (7 downto 0))
+    RETURN CHARACTER IS
+    VARIABLE result: CHARACTER;
+  BEGIN
+    CASE vec_to_convert IS      -- cover basic ascii printable characters...
+      when X"0a" => result := lf; -- \n, linefeed
+      when X"0d" => result := nul; -- \r, Ctrl-M
+      when X"09" => result := ht; -- \t, Ctrl-I, TAB
+      when X"20" => result := ' ' ;
+      when X"21" => result := '!' ;
+      when X"22" => result := '"' ;
+      when X"23" => result := '#' ;
+      when X"24" => result := '$' ;
+      when X"25" => result := '%' ;
+      when X"26" => result := '&' ;
+      when X"27" => result := ''' ; -- sync ' char for hilighting txt editors
+      when X"28" => result := '(' ;
+      when X"29" => result := ')' ;
+      when X"2a" => result := '*' ;
+      when X"2b" => result := '+' ;
+      when X"2c" => result := ',' ;
+      when X"2d" => result := '-' ;
+      when X"2e" => result := '.' ;
+      when X"2f" => result := '/' ;
+      when X"30" => result := '0' ;
+      when X"31" => result := '1' ;
+      when X"32" => result := '2' ;
+      when X"33" => result := '3' ;
+      when X"34" => result := '4' ;
+      when X"35" => result := '5' ;
+      when X"36" => result := '6' ;
+      when X"37" => result := '7' ;
+      when X"38" => result := '8' ;
+      when X"39" => result := '9' ;
+      when X"3a" => result := ':' ;
+      when X"3b" => result := ';' ;
+      when X"3c" => result := '<' ;
+      when X"3d" => result := '=' ;
+      when X"3e" => result := '>' ;
+      when X"3f" => result := '?' ;
+      when X"40" => result := '@' ;
+      when X"41" => result := 'A' ;
+      when X"42" => result := 'B' ;
+      when X"43" => result := 'C' ;
+      when X"44" => result := 'D' ;
+      when X"45" => result := 'E' ;
+      when X"46" => result := 'F' ;
+      when X"47" => result := 'G' ;
+      when X"48" => result := 'H' ;
+      when X"49" => result := 'I' ;
+      when X"4a" => result := 'J' ;
+      when X"4b" => result := 'K' ;
+      when X"4c" => result := 'L' ;
+      when X"4d" => result := 'M' ;
+      when X"4e" => result := 'N' ;
+      when X"4f" => result := 'O' ;
+      when X"50" => result := 'P' ;
+      when X"51" => result := 'Q' ;
+      when X"52" => result := 'R' ;
+      when X"53" => result := 'S' ;
+      when X"54" => result := 'T' ;
+      when X"55" => result := 'U' ;
+      when X"56" => result := 'V' ;
+      when X"57" => result := 'W' ;
+      when X"58" => result := 'X' ;
+      when X"59" => result := 'Y' ;
+      when X"5a" => result := 'Z' ;
+      when X"5b" => result := '[' ;
+      when X"5c" => result := '\' ;
+      when X"5d" => result := ']' ;
+      when X"5e" => result := '^' ;
+      when X"5f" => result := '_' ;
+      when X"60" => result := '`' ;
+      when X"61" => result := 'a' ;
+      when X"62" => result := 'b' ;
+      when X"63" => result := 'c' ;
+      when X"64" => result := 'd' ;
+      when X"65" => result := 'e' ;
+      when X"66" => result := 'f' ;
+      when X"67" => result := 'g' ;
+      when X"68" => result := 'h' ;
+      when X"69" => result := 'i' ;
+      when X"6a" => result := 'j' ;
+      when X"6b" => result := 'k' ;
+      when X"6c" => result := 'l' ;
+      when X"6d" => result := 'm' ;
+      when X"6e" => result := 'n' ;
+      when X"6f" => result := 'o' ;
+      when X"70" => result := 'p' ;
+      when X"71" => result := 'q' ;
+      when X"72" => result := 'r' ;
+      when X"73" => result := 's' ;
+      when X"74" => result := 't' ;
+      when X"75" => result := 'u' ;
+      when X"76" => result := 'v' ;
+      when X"77" => result := 'w' ;
+      when X"78" => result := 'x' ;
+      when X"79" => result := 'y' ;
+      when X"7a" => result := 'z' ;
+      when X"7b" => result := '{' ;
+      when X"7c" => result := '|' ;
+      when X"7d" => result := '}' ;
+      when X"7e" => result := '~' ;
+      when X"7f" => result := '_' ;
+      WHEN others =>
+        ASSERT False REPORT "data contains a non-printable character" SEVERITY Warning;
+        result := nul;
+    END case;
+    RETURN result;
+  end bin_to_char;
+  -- synthesis translate_on
+                             
+
+begin
+
+--synthesis translate_off
+
+
+  -- purpose: simulate verilog initial function to open file in write mode
+  -- type   : combinational
+  -- inputs : initial
+  -- outputs: <none>
+  process is
+    variable initial : boolean := true; -- not initialized yet
+    variable status : file_open_status; -- status for fopen
+  begin  -- process
+    if initial = true then
+      file_open (status, text_handle, "jtag_uart_0_output_stream.dat", WRITE_MODE);
+      initial := false;                 -- done!
+    end if;
+    wait;                               -- wait forever
+  end process;
+
+  process (clk)
+    variable data_string : LINE;        -- for line buffer to file
+    variable status : file_open_status; -- status for fopen
+                        
+    variable echo_string : LINE;        -- for line buffer to screen (stdout)
+                          
+  begin  -- process clk
+    if clk'event and clk = '1' then -- sync ' chars for hilighting txt editors
+      if (valid and strobe) = '1' then
+                        
+        write (data_string,To_bitvector(data)); -- every char flushes line
+        writeline (text_handle,data_string);
+        file_close (text_handle);     -- flush buffer
+        file_open (status, text_handle, "jtag_uart_0_output_stream.dat", APPEND_MODE);
+                           
+        -- save up characters into a line to send to the screen
+        write (echo_string,bin_to_char(data));
+        if data = X"0a" or data = X"0d" then -- \n or \r will flush line
+          writeline (output,echo_string);
+        end if;
+                          
+      end if;
+    end if;
+  end process;
+                       --synthesis translate_on
+
+end europa;
+
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity jtag_uart_0_sim_scfifo_w is 
+        port (
+              -- inputs:
+                 signal clk : IN STD_LOGIC;
+                 signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal fifo_wr : IN STD_LOGIC;
+
+              -- outputs:
+                 signal fifo_FF : OUT STD_LOGIC;
+                 signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal wfifo_empty : OUT STD_LOGIC;
+                 signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+              );
+end entity jtag_uart_0_sim_scfifo_w;
+
+
+architecture europa of jtag_uart_0_sim_scfifo_w is
+--synthesis translate_off
+component jtag_uart_0_log_module is 
+           port (
+                 -- inputs:
+                    signal clk : IN STD_LOGIC;
+                    signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal strobe : IN STD_LOGIC;
+                    signal valid : IN STD_LOGIC
+                 );
+end component jtag_uart_0_log_module;
+
+--synthesis translate_on
+
+begin
+
+--synthesis translate_off
+    --jtag_uart_0_log, which is an e_log
+    jtag_uart_0_log : jtag_uart_0_log_module
+      port map(
+        clk => clk,
+        data => fifo_wdata,
+        strobe => fifo_wr,
+        valid => fifo_wr
+      );
+
+
+    wfifo_used <= A_REP(std_logic'('0'), 6);
+    r_dat <= A_REP(std_logic'('0'), 8);
+    fifo_FF <= std_logic'('0');
+    wfifo_empty <= std_logic'('1');
+--synthesis translate_on
+
+end europa;
+
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library lpm;
+use lpm.all;
+
+entity jtag_uart_0_scfifo_w is 
+        port (
+              -- inputs:
+                 signal clk : IN STD_LOGIC;
+                 signal fifo_clear : IN STD_LOGIC;
+                 signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal fifo_wr : IN STD_LOGIC;
+                 signal rd_wfifo : IN STD_LOGIC;
+
+              -- outputs:
+                 signal fifo_FF : OUT STD_LOGIC;
+                 signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal wfifo_empty : OUT STD_LOGIC;
+                 signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+              );
+end entity jtag_uart_0_scfifo_w;
+
+
+architecture europa of jtag_uart_0_scfifo_w is
+--synthesis translate_off
+component jtag_uart_0_sim_scfifo_w is 
+           port (
+                 -- inputs:
+                    signal clk : IN STD_LOGIC;
+                    signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal fifo_wr : IN STD_LOGIC;
+
+                 -- outputs:
+                    signal fifo_FF : OUT STD_LOGIC;
+                    signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal wfifo_empty : OUT STD_LOGIC;
+                    signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+                 );
+end component jtag_uart_0_sim_scfifo_w;
+
+--synthesis translate_on
+--synthesis read_comments_as_HDL on
+--  component scfifo is
+--GENERIC (
+--      lpm_hint : STRING;
+--        lpm_numwords : NATURAL;
+--        lpm_showahead : STRING;
+--        lpm_type : STRING;
+--        lpm_width : NATURAL;
+--        lpm_widthu : NATURAL;
+--        overflow_checking : STRING;
+--        underflow_checking : STRING;
+--        use_eab : STRING
+--      );
+--    PORT (
+--    signal full : OUT STD_LOGIC;
+--        signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+--        signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+--        signal empty : OUT STD_LOGIC;
+--        signal rdreq : IN STD_LOGIC;
+--        signal aclr : IN STD_LOGIC;
+--        signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+--        signal clock : IN STD_LOGIC;
+--        signal wrreq : IN STD_LOGIC
+--      );
+--  end component scfifo;
+--synthesis read_comments_as_HDL off
+                signal internal_fifo_FF :  STD_LOGIC;
+                signal internal_r_dat :  STD_LOGIC_VECTOR (7 DOWNTO 0);
+                signal internal_wfifo_empty :  STD_LOGIC;
+                signal internal_wfifo_used :  STD_LOGIC_VECTOR (5 DOWNTO 0);
+
+begin
+
+  --vhdl renameroo for output signals
+  fifo_FF <= internal_fifo_FF;
+  --vhdl renameroo for output signals
+  r_dat <= internal_r_dat;
+  --vhdl renameroo for output signals
+  wfifo_empty <= internal_wfifo_empty;
+  --vhdl renameroo for output signals
+  wfifo_used <= internal_wfifo_used;
+--synthesis translate_off
+    --the_jtag_uart_0_sim_scfifo_w, which is an e_instance
+    the_jtag_uart_0_sim_scfifo_w : jtag_uart_0_sim_scfifo_w
+      port map(
+        fifo_FF => internal_fifo_FF,
+        r_dat => internal_r_dat,
+        wfifo_empty => internal_wfifo_empty,
+        wfifo_used => internal_wfifo_used,
+        clk => clk,
+        fifo_wdata => fifo_wdata,
+        fifo_wr => fifo_wr
+      );
+
+
+--synthesis translate_on
+--synthesis read_comments_as_HDL on
+--    wfifo : scfifo
+--      generic map(
+--        lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+--        lpm_numwords => 64,
+--        lpm_showahead => "OFF",
+--        lpm_type => "scfifo",
+--        lpm_width => 8,
+--        lpm_widthu => 6,
+--        overflow_checking => "OFF",
+--        underflow_checking => "OFF",
+--        use_eab => "ON"
+--      )
+--      port map(
+--                aclr => fifo_clear,
+--                clock => clk,
+--                data => fifo_wdata,
+--                empty => internal_wfifo_empty,
+--                full => internal_fifo_FF,
+--                q => internal_r_dat,
+--                rdreq => rd_wfifo,
+--                usedw => internal_wfifo_used,
+--                wrreq => fifo_wr
+--      );
+--
+--synthesis read_comments_as_HDL off
+
+end europa;
+
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library std;
+use std.textio.all;
+
+entity jtag_uart_0_drom_module is 
+        generic (
+                 POLL_RATE : integer := 100
+                 );
+        port (
+              -- inputs:
+                 signal clk : IN STD_LOGIC;
+                 signal incr_addr : IN STD_LOGIC;
+                 signal reset_n : IN STD_LOGIC;
+
+              -- outputs:
+                 signal new_rom : OUT STD_LOGIC;
+                 signal num_bytes : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+                 signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal safe : OUT STD_LOGIC
+              );
+end entity jtag_uart_0_drom_module;
+
+
+architecture europa of jtag_uart_0_drom_module is
+                signal address :  STD_LOGIC_VECTOR (11 DOWNTO 0);
+                signal d1_pre :  STD_LOGIC;
+                signal d2_pre :  STD_LOGIC;
+                signal d3_pre :  STD_LOGIC;
+                signal d4_pre :  STD_LOGIC;
+                signal d5_pre :  STD_LOGIC;
+                signal d6_pre :  STD_LOGIC;
+                signal d7_pre :  STD_LOGIC;
+                signal d8_pre :  STD_LOGIC;
+                signal d9_pre :  STD_LOGIC;
+                TYPE mem_type is ARRAY( 2047 DOWNTO 0) of STD_LOGIC_VECTOR(7 DOWNTO 0);
+              signal mem_array : mem_type;
+                TYPE mem_type1 is ARRAY( 1 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
+              signal mutex : mem_type1;
+                signal pre :  STD_LOGIC;
+  
+          signal safe_wire : STD_LOGIC; -- deal with bogus VHDL type casting
+          signal safe_delay : STD_LOGIC; 
+          FILE mutex_handle : TEXT ;  -- open this for read and write manually.
+          -- stream can be opened simply for read...
+          FILE stream_handle : TEXT open READ_MODE is "jtag_uart_0_input_stream.dat";
+
+-- synthesis translate_off
+-- convert functions deadlifted from e_rom.pm
+
+FUNCTION convert_string_to_number(string_to_convert : STRING;
+                                  final_char_index : NATURAL := 0)
+  RETURN NATURAL IS
+  VARIABLE result: NATURAL := 0;
+  VARIABLE current_index : NATURAL := 1;
+  VARIABLE the_char : CHARACTER;
+  
+BEGIN
+  IF final_char_index = 0 THEN
+    result := 0;
+  ELSE
+    WHILE current_index <= final_char_index LOOP
+      the_char := string_to_convert(current_index);
+      IF    '0' <= the_char AND the_char <= '9' THEN
+        result := result * 16 + character'pos(the_char) - character'pos('0');
+      ELSIF 'A' <= the_char AND the_char <= 'F' THEN
+        result := result * 16 + character'pos(the_char) - character'pos('A') + 10;
+      ELSIF 'a' <= the_char AND the_char <= 'f' THEN
+        result := result * 16 + character'pos(the_char) - character'pos('a') + 10;
+      ELSE
+        report "convert_string_to_number: Ack, a formatting error!";
+      END IF;
+      current_index := current_index + 1;
+    END LOOP;
+  END IF; 
+  RETURN result;
+END convert_string_to_number;
+
+
+FUNCTION convert_string_to_std_logic(value : STRING; num_chars : INTEGER; mem_width_chars : INTEGER)
+  RETURN STD_LOGIC_VECTOR is                       
+  VARIABLE num_bits: integer := mem_width_chars * 4;
+  VARIABLE result: std_logic_vector(num_bits-1 downto 0);
+  VARIABLE curr_char : integer;
+  VARIABLE min_width : integer := mem_width_chars;
+  VARIABLE num_nibbles : integer := 0;
+  
+BEGIN
+  result := (others => '0');
+  num_nibbles := mem_width_chars;
+  IF (mem_width_chars > num_chars) THEN
+    num_nibbles := num_chars;
+  END IF;
+  
+  FOR I IN 1 TO num_nibbles LOOP
+    curr_char := num_nibbles - (I-1);
+    
+    CASE value(I) IS
+      WHEN '0' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0000";
+      WHEN '1' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0001";
+      WHEN '2' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0010";
+      WHEN '3' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0011";
+      WHEN '4' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0100";
+      WHEN '5' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0101";
+      WHEN '6' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0110";
+      WHEN '7' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "0111";
+      WHEN '8' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1000";
+      WHEN '9' =>  result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1001";
+      WHEN 'A' | 'a' => result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1010";
+      WHEN 'B' | 'b' => result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1011";
+      WHEN 'C' | 'c' => result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1100";
+      WHEN 'D' | 'd' => result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1101";
+      WHEN 'E' | 'e' => result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1110";
+      WHEN 'F' | 'f' => result((4*curr_char)-1  DOWNTO 4*(curr_char-1)) := "1111";
+      WHEN ' ' => EXIT;
+      WHEN HT  => exit;
+      WHEN others =>
+        ASSERT False
+          REPORT "function From_Hex: string """ & value & """ contains non-hex character"
+          severity Error;
+        EXIT;
+    END case;
+  END loop;
+  RETURN result;
+END convert_string_to_std_logic;
+
+-- purpose: open mutex/discard @address/convert value to std_logic_vector
+function get_mutex_val (file_name : string)
+  return STD_LOGIC_VECTOR is
+  VARIABLE result : STD_LOGIC_VECTOR (31 downto 0) := X"00000000";
+  FILE handle : TEXT ;
+  VARIABLE status : file_open_status; -- status for fopen
+  VARIABLE data_line : LINE;
+  VARIABLE the_character_from_data_line : CHARACTER;
+  VARIABLE converted_number : NATURAL := 0;
+  VARIABLE found_string_array : STRING(1 TO 128);
+  VARIABLE string_index : NATURAL := 0;
+  VARIABLE line_length : NATURAL := 0; 
+ 
+begin  -- get_mutex_val
+
+  file_open (status, handle, file_name, READ_MODE);
+  IF (status=OPEN_OK) THEN
+
+  WHILE NOT(endfile(handle)) LOOP
+    readline(handle, data_line);
+    line_length := data_line'LENGTH; -- match ' for emacs font-lock
+    
+    WHILE line_length > 0 LOOP
+      read(data_line, the_character_from_data_line);
+      -- check for the @ character indicating a new address wad
+      -- if found, ignore the line!  This is just protection
+      IF '@' = the_character_from_data_line THEN
+        exit;                           -- bail out of this line
+      end if;
+      -- process the hex address, character by character ...
+      IF NOT(' ' = the_character_from_data_line) THEN
+        string_index := string_index + 1;
+        found_string_array(string_index) := the_character_from_data_line;
+      END IF;
+      line_length := line_length - 1; 
+    end loop;                           -- read characters
+
+  end loop;                             -- read lines
+  END IF;
+  file_close (handle);
+  
+  if string_index /= 0 then
+    result := convert_string_to_std_logic(found_string_array, string_index, 8);
+  end if;
+
+  return result;
+  
+end get_mutex_val;
+
+-- purpose: emulate verilogs readmemh function (mostly)
+-- in verilog you say: $readmemh ("file", array);
+-- in VHDL, we say: array <= readmemh("file"); -- which makes more sense.
+function readmemh (file_name : string)
+  return mem_type is
+  VARIABLE result : mem_type;
+  FILE handle : TEXT ;
+  VARIABLE status : file_open_status; -- status for fopen
+  VARIABLE data_line : LINE;
+  VARIABLE b_address : BOOLEAN := FALSE; -- distinguish between addrs and data
+  VARIABLE the_character_from_data_line : CHARACTER;
+  VARIABLE converted_number : NATURAL := 0;
+  VARIABLE found_string_array : STRING(1 TO 128);
+  VARIABLE string_index : NATURAL := 0;
+  VARIABLE line_length : NATURAL := 0; 
+  VARIABLE load_address : NATURAL := 0;
+  VARIABLE mem_index : NATURAL := 0;
+begin  -- readmemh
+
+  file_open (status, handle, file_name, READ_MODE);
+
+  WHILE NOT(endfile(handle)) LOOP
+    readline(handle, data_line);
+    line_length := data_line'LENGTH; -- match ' for emacs font-lock
+    b_address := false;
+
+    WHILE line_length > 0 LOOP
+      read(data_line, the_character_from_data_line);
+      -- check for the @ character indicating a new address wad
+      -- if found, ignore the line!  This is just protection
+      IF '@' = the_character_from_data_line and not b_address then -- is addr
+        b_address := true;
+      end if;
+      -- process the hex address, character by character ...
+      IF NOT((' ' = the_character_from_data_line) or
+	     ('@' = the_character_from_data_line) or
+             (lf = the_character_from_data_line) or
+	     (cr = the_character_from_data_line)) THEN
+        string_index := string_index + 1;
+        found_string_array(string_index) := the_character_from_data_line;
+      END IF;
+      line_length := line_length - 1;
+    end loop;                           -- read characters
+
+    if b_address then
+      mem_index := convert_string_to_number(found_string_array, string_index);
+      b_address := FALSE;
+    else
+      result(mem_index) := convert_string_to_std_logic(found_string_array, string_index, 2);
+    end if;
+
+    string_index := 0;
+
+  end loop;                             -- read lines
+
+  file_close (handle);
+  
+  return result;
+  
+end readmemh;
+                           
+
+-- purpose: emulate verilogs readmemb function (mostly)
+-- in verilog you say: $readmemb ("file", array);
+-- in VHDL, we say: array <= readmemb("file"); -- which makes more sense.
+function readmemb (file_name : string)
+  return mem_type is
+  VARIABLE result : mem_type;
+  FILE handle : TEXT ;
+  VARIABLE status : file_open_status; -- status for fopen
+  VARIABLE data_line : LINE;
+  VARIABLE the_character_from_data_line : BIT_VECTOR(7 DOWNTO 0); -- '0' & '1's
+  VARIABLE line_length : NATURAL := 0; 
+  VARIABLE mem_index : NATURAL := 0;
+begin  -- readmemb
+
+  file_open (status, handle, file_name, READ_MODE);
+
+  WHILE NOT(endfile(handle)) LOOP
+    readline(handle, data_line);
+    line_length := data_line'LENGTH; -- match ' for emacs font-lock
+
+    WHILE line_length > 7 LOOP
+      read(data_line, the_character_from_data_line);
+      -- No @ characters allowed in binary/bit_vector mode
+      result(mem_index) := To_stdlogicvector(the_character_from_data_line);
+      mem_index := mem_index + 1;
+      line_length := line_length - 8;
+    end loop;                           -- read characters
+
+  end loop;                             -- read lines
+
+  file_close (handle);
+  
+  return result;
+  
+end readmemb;
+                          
+-- synthesis translate_on
+                      
+
+begin
+
+--synthesis translate_off
+    q <= mem_array(CONV_INTEGER(UNSIGNED((address))));
+    process (clk, reset_n)
+    begin
+      if reset_n = '0' then
+        d1_pre <= std_logic'('0');
+        d2_pre <= std_logic'('0');
+        d3_pre <= std_logic'('0');
+        d4_pre <= std_logic'('0');
+        d5_pre <= std_logic'('0');
+        d6_pre <= std_logic'('0');
+        d7_pre <= std_logic'('0');
+        d8_pre <= std_logic'('0');
+        d9_pre <= std_logic'('0');
+        new_rom <= std_logic'('0');
+      elsif clk'event and clk = '1' then
+        d1_pre <= pre;
+        d2_pre <= d1_pre;
+        d3_pre <= d2_pre;
+        d4_pre <= d3_pre;
+        d5_pre <= d4_pre;
+        d6_pre <= d5_pre;
+        d7_pre <= d6_pre;
+        d8_pre <= d7_pre;
+        d9_pre <= d8_pre;
+        new_rom <= d9_pre;
+      end if;
+
+    end process;
+
+
+    num_bytes <= mutex(1);
+                         
+    safe <= safe_wire;
+    safe_wire <= to_std_logic( address < mutex(1) );
+
+    process (clk, reset_n)
+    begin
+      if reset_n = '0' then
+        safe_delay <= '0';
+      elsif clk'event and clk = '1' then -- balance ' for emacs quoting
+        safe_delay <= safe_wire;
+      end if;
+    end process;
+
+    process (clk, reset_n)
+      variable poll_count : integer := POLL_RATE; -- STD_LOGIC_VECTOR (31:0);
+      variable status : file_open_status; -- status for fopen
+      variable mutex_string : LINE;  -- temp space for read/write data
+      variable stream_string : LINE;  -- temp space for read data
+      variable init_done : BOOLEAN; -- only used if non-interactive
+      variable interactive : BOOLEAN := FALSE;
+    begin
+      if reset_n /= '1' then
+        address <= "000000000000";
+        mem_array(0) <= X"00";
+        mutex(0) <= X"00000000";
+        mutex(1) <= X"00000000";
+        pre <= '0';
+        init_done := FALSE;
+      elsif clk'event and clk = '1' then -- balance ' for emacs quoting
+        pre <= '0';
+        if incr_addr = '1' and safe_wire = '1' then
+          address <= address + "000000000001";
+        end if;
+        -- blast mutex via textio after falling edge of safe
+        if mutex(0) /= X"00000000" and safe_wire = '0' and safe_delay = '1' then
+	  if interactive then           -- bash mutex
+            file_open (status, mutex_handle, "jtag_uart_0_input_mutex.dat", WRITE_MODE);
+            write (mutex_string, string'("0")); -- balance ' for emacs quoting
+            writeline (mutex_handle, mutex_string);
+            file_close (mutex_handle);
+            mutex(0) <= X"00000000";
+	  else -- non-nteractive does not bash mutex: it stops poll counter
+	    init_done := TRUE;
+          end if;
+        end if;
+        if poll_count < POLL_RATE then  -- wait
+          if not init_done then         -- stop counting if init_done is TRUE
+            poll_count := poll_count + 1;
+          end if;
+        else                            -- do the real work
+          poll_count := 0;
+          -- get mutex via textio ...
+          mutex(0) <= get_mutex_val ("jtag_uart_0_input_mutex.dat");
+          if mutex(0) /= X"00000000" and safe_wire = '0' then
+            -- read stream into array after previous stream is complete
+            mutex (1) <= mutex (0); -- save mutex value for address compare
+            -- get mem_array via textio ...
+            mem_array <= readmemb("jtag_uart_0_input_stream.dat");
+            -- prep address and pre-pulse to alert world to new contents
+            address <= "000000000000";
+            pre <= '1';
+          end if; -- poll_count
+        end if;   -- clock
+      end if;     -- reset
+    end process;
+                         --synthesis translate_on
+
+end europa;
+
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity jtag_uart_0_sim_scfifo_r is 
+        port (
+              -- inputs:
+                 signal clk : IN STD_LOGIC;
+                 signal fifo_rd : IN STD_LOGIC;
+                 signal rst_n : IN STD_LOGIC;
+
+              -- outputs:
+                 signal fifo_EF : OUT STD_LOGIC;
+                 signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal rfifo_full : OUT STD_LOGIC;
+                 signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+              );
+end entity jtag_uart_0_sim_scfifo_r;
+
+
+architecture europa of jtag_uart_0_sim_scfifo_r is
+--synthesis translate_off
+component jtag_uart_0_drom_module is 
+           generic (
+                    POLL_RATE : integer := 100
+                    );
+           port (
+                 -- inputs:
+                    signal clk : IN STD_LOGIC;
+                    signal incr_addr : IN STD_LOGIC;
+                    signal reset_n : IN STD_LOGIC;
+
+                 -- outputs:
+                    signal new_rom : OUT STD_LOGIC;
+                    signal num_bytes : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+                    signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal safe : OUT STD_LOGIC
+                 );
+end component jtag_uart_0_drom_module;
+
+--synthesis translate_on
+                signal bytes_left :  STD_LOGIC_VECTOR (31 DOWNTO 0);
+                signal fifo_rd_d :  STD_LOGIC;
+                signal internal_fifo_rdata1 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
+                signal internal_rfifo_full1 :  STD_LOGIC;
+                signal new_rom :  STD_LOGIC;
+                signal num_bytes :  STD_LOGIC_VECTOR (31 DOWNTO 0);
+                signal rfifo_entries :  STD_LOGIC_VECTOR (6 DOWNTO 0);
+                signal safe :  STD_LOGIC;
+
+begin
+
+  --vhdl renameroo for output signals
+  fifo_rdata <= internal_fifo_rdata1;
+  --vhdl renameroo for output signals
+  rfifo_full <= internal_rfifo_full1;
+--synthesis translate_off
+    --jtag_uart_0_drom, which is an e_drom
+    jtag_uart_0_drom : jtag_uart_0_drom_module
+      port map(
+        new_rom => new_rom,
+        num_bytes => num_bytes,
+        q => internal_fifo_rdata1,
+        safe => safe,
+        clk => clk,
+        incr_addr => fifo_rd_d,
+        reset_n => rst_n
+      );
+
+
+    -- Generate rfifo_entries for simulation
+    process (clk, rst_n)
+    begin
+      if rst_n = '0' then
+        bytes_left <= std_logic_vector'("00000000000000000000000000000000");
+        fifo_rd_d <= std_logic'('0');
+      elsif clk'event and clk = '1' then
+        fifo_rd_d <= fifo_rd;
+        -- decrement on read
+        if std_logic'(fifo_rd_d) = '1' then 
+          bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
+        end if;
+        -- catch new contents
+        if std_logic'(new_rom) = '1' then 
+          bytes_left <= num_bytes;
+        end if;
+      end if;
+
+    end process;
+
+    fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
+    internal_rfifo_full1 <= to_std_logic((bytes_left>std_logic_vector'("00000000000000000000000001000000")));
+    rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
+    rfifo_used <= rfifo_entries(5 DOWNTO 0);
+--synthesis translate_on
+
+end europa;
+
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library lpm;
+use lpm.all;
+
+entity jtag_uart_0_scfifo_r is 
+        port (
+              -- inputs:
+                 signal clk : IN STD_LOGIC;
+                 signal fifo_clear : IN STD_LOGIC;
+                 signal fifo_rd : IN STD_LOGIC;
+                 signal rst_n : IN STD_LOGIC;
+                 signal t_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal wr_rfifo : IN STD_LOGIC;
+
+              -- outputs:
+                 signal fifo_EF : OUT STD_LOGIC;
+                 signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                 signal rfifo_full : OUT STD_LOGIC;
+                 signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+              );
+end entity jtag_uart_0_scfifo_r;
+
+
+architecture europa of jtag_uart_0_scfifo_r is
+--synthesis translate_off
+component jtag_uart_0_sim_scfifo_r is 
+           port (
+                 -- inputs:
+                    signal clk : IN STD_LOGIC;
+                    signal fifo_rd : IN STD_LOGIC;
+                    signal rst_n : IN STD_LOGIC;
+
+                 -- outputs:
+                    signal fifo_EF : OUT STD_LOGIC;
+                    signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal rfifo_full : OUT STD_LOGIC;
+                    signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+                 );
+end component jtag_uart_0_sim_scfifo_r;
+
+--synthesis translate_on
+--synthesis read_comments_as_HDL on
+--  component scfifo is
+--GENERIC (
+--      lpm_hint : STRING;
+--        lpm_numwords : NATURAL;
+--        lpm_showahead : STRING;
+--        lpm_type : STRING;
+--        lpm_width : NATURAL;
+--        lpm_widthu : NATURAL;
+--        overflow_checking : STRING;
+--        underflow_checking : STRING;
+--        use_eab : STRING
+--      );
+--    PORT (
+--    signal full : OUT STD_LOGIC;
+--        signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+--        signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+--        signal empty : OUT STD_LOGIC;
+--        signal rdreq : IN STD_LOGIC;
+--        signal aclr : IN STD_LOGIC;
+--        signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+--        signal clock : IN STD_LOGIC;
+--        signal wrreq : IN STD_LOGIC
+--      );
+--  end component scfifo;
+--synthesis read_comments_as_HDL off
+                signal internal_fifo_EF :  STD_LOGIC;
+                signal internal_fifo_rdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
+                signal internal_rfifo_full :  STD_LOGIC;
+                signal internal_rfifo_used :  STD_LOGIC_VECTOR (5 DOWNTO 0);
+
+begin
+
+  --vhdl renameroo for output signals
+  fifo_EF <= internal_fifo_EF;
+  --vhdl renameroo for output signals
+  fifo_rdata <= internal_fifo_rdata;
+  --vhdl renameroo for output signals
+  rfifo_full <= internal_rfifo_full;
+  --vhdl renameroo for output signals
+  rfifo_used <= internal_rfifo_used;
+--synthesis translate_off
+    --the_jtag_uart_0_sim_scfifo_r, which is an e_instance
+    the_jtag_uart_0_sim_scfifo_r : jtag_uart_0_sim_scfifo_r
+      port map(
+        fifo_EF => internal_fifo_EF,
+        fifo_rdata => internal_fifo_rdata,
+        rfifo_full => internal_rfifo_full,
+        rfifo_used => internal_rfifo_used,
+        clk => clk,
+        fifo_rd => fifo_rd,
+        rst_n => rst_n
+      );
+
+
+--synthesis translate_on
+--synthesis read_comments_as_HDL on
+--    rfifo : scfifo
+--      generic map(
+--        lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+--        lpm_numwords => 64,
+--        lpm_showahead => "OFF",
+--        lpm_type => "scfifo",
+--        lpm_width => 8,
+--        lpm_widthu => 6,
+--        overflow_checking => "OFF",
+--        underflow_checking => "OFF",
+--        use_eab => "ON"
+--      )
+--      port map(
+--                aclr => fifo_clear,
+--                clock => clk,
+--                data => t_dat,
+--                empty => internal_fifo_EF,
+--                full => internal_rfifo_full,
+--                q => internal_fifo_rdata,
+--                rdreq => fifo_rd,
+--                usedw => internal_rfifo_used,
+--                wrreq => wr_rfifo
+--      );
+--
+--synthesis read_comments_as_HDL off
+
+end europa;
+
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library lpm;
+use lpm.all;
+
+entity jtag_uart_0 is 
+        port (
+              -- inputs:
+                 signal av_address : IN STD_LOGIC;
+                 signal av_chipselect : IN STD_LOGIC;
+                 signal av_read_n : IN STD_LOGIC;
+                 signal av_write_n : IN STD_LOGIC;
+                 signal av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+                 signal clk : IN STD_LOGIC;
+                 signal rst_n : IN STD_LOGIC;
+
+              -- outputs:
+                 signal av_irq : OUT STD_LOGIC;
+                 signal av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+                 signal av_waitrequest : OUT STD_LOGIC;
+                 signal dataavailable : OUT STD_LOGIC;
+                 signal readyfordata : OUT STD_LOGIC
+              );
+attribute ALTERA_ATTRIBUTE : string;
+attribute ALTERA_ATTRIBUTE of jtag_uart_0 : entity is "SUPPRESS_DA_RULE_INTERNAL=""R101,C106,D101,D103""";
+end entity jtag_uart_0;
+
+
+architecture europa of jtag_uart_0 is
+component jtag_uart_0_scfifo_w is 
+           port (
+                 -- inputs:
+                    signal clk : IN STD_LOGIC;
+                    signal fifo_clear : IN STD_LOGIC;
+                    signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal fifo_wr : IN STD_LOGIC;
+                    signal rd_wfifo : IN STD_LOGIC;
+
+                 -- outputs:
+                    signal fifo_FF : OUT STD_LOGIC;
+                    signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal wfifo_empty : OUT STD_LOGIC;
+                    signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+                 );
+end component jtag_uart_0_scfifo_w;
+
+component jtag_uart_0_scfifo_r is 
+           port (
+                 -- inputs:
+                    signal clk : IN STD_LOGIC;
+                    signal fifo_clear : IN STD_LOGIC;
+                    signal fifo_rd : IN STD_LOGIC;
+                    signal rst_n : IN STD_LOGIC;
+                    signal t_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal wr_rfifo : IN STD_LOGIC;
+
+                 -- outputs:
+                    signal fifo_EF : OUT STD_LOGIC;
+                    signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+                    signal rfifo_full : OUT STD_LOGIC;
+                    signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+                 );
+end component jtag_uart_0_scfifo_r;
+
+--synthesis read_comments_as_HDL on
+--  component alt_jtag_atlantic is
+--GENERIC (
+--      INSTANCE_ID : NATURAL;
+--        LOG2_RXFIFO_DEPTH : NATURAL;
+--        LOG2_TXFIFO_DEPTH : NATURAL;
+--        SLD_AUTO_INSTANCE_INDEX : STRING
+--      );
+--    PORT (
+--    signal t_pause : OUT STD_LOGIC;
+--        signal r_ena : OUT STD_LOGIC;
+--        signal t_ena : OUT STD_LOGIC;
+--        signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+--        signal t_dav : IN STD_LOGIC;
+--        signal rst_n : IN STD_LOGIC;
+--        signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+--        signal r_val : IN STD_LOGIC;
+--        signal clk : IN STD_LOGIC
+--      );
+--  end component alt_jtag_atlantic;
+--synthesis read_comments_as_HDL off
+                signal ac :  STD_LOGIC;
+                signal activity :  STD_LOGIC;
+                signal fifo_AE :  STD_LOGIC;
+                signal fifo_AF :  STD_LOGIC;
+                signal fifo_EF :  STD_LOGIC;
+                signal fifo_FF :  STD_LOGIC;
+                signal fifo_clear :  STD_LOGIC;
+                signal fifo_rd :  STD_LOGIC;
+                signal fifo_rdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
+                signal fifo_wdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
+                signal fifo_wr :  STD_LOGIC;
+                signal ien_AE :  STD_LOGIC;
+                signal ien_AF :  STD_LOGIC;
+                signal internal_av_waitrequest :  STD_LOGIC;
+                signal ipen_AE :  STD_LOGIC;
+                signal ipen_AF :  STD_LOGIC;
+                signal pause_irq :  STD_LOGIC;
+                signal r_dat :  STD_LOGIC_VECTOR (7 DOWNTO 0);
+                signal r_ena :  STD_LOGIC;
+                signal r_val :  STD_LOGIC;
+                signal rd_wfifo :  STD_LOGIC;
+                signal read_0 :  STD_LOGIC;
+                signal rfifo_full :  STD_LOGIC;
+                signal rfifo_used :  STD_LOGIC_VECTOR (5 DOWNTO 0);
+                signal rvalid :  STD_LOGIC;
+                signal sim_r_ena :  STD_LOGIC;
+                signal sim_t_dat :  STD_LOGIC;
+                signal sim_t_ena :  STD_LOGIC;
+                signal sim_t_pause :  STD_LOGIC;
+                signal t_dat :  STD_LOGIC_VECTOR (7 DOWNTO 0);
+                signal t_dav :  STD_LOGIC;
+                signal t_ena :  STD_LOGIC;
+                signal t_pause :  STD_LOGIC;
+                signal wfifo_empty :  STD_LOGIC;
+                signal wfifo_used :  STD_LOGIC_VECTOR (5 DOWNTO 0);
+                signal woverflow :  STD_LOGIC;
+                signal wr_rfifo :  STD_LOGIC;
+
+begin
+
+  --avalon_jtag_slave, which is an e_avalon_slave
+  rd_wfifo <= r_ena AND NOT wfifo_empty;
+  wr_rfifo <= t_ena AND NOT rfifo_full;
+  fifo_clear <= NOT rst_n;
+  --the_jtag_uart_0_scfifo_w, which is an e_instance
+  the_jtag_uart_0_scfifo_w : jtag_uart_0_scfifo_w
+    port map(
+      fifo_FF => fifo_FF,
+      r_dat => r_dat,
+      wfifo_empty => wfifo_empty,
+      wfifo_used => wfifo_used,
+      clk => clk,
+      fifo_clear => fifo_clear,
+      fifo_wdata => fifo_wdata,
+      fifo_wr => fifo_wr,
+      rd_wfifo => rd_wfifo
+    );
+
+
+  --the_jtag_uart_0_scfifo_r, which is an e_instance
+  the_jtag_uart_0_scfifo_r : jtag_uart_0_scfifo_r
+    port map(
+      fifo_EF => fifo_EF,
+      fifo_rdata => fifo_rdata,
+      rfifo_full => rfifo_full,
+      rfifo_used => rfifo_used,
+      clk => clk,
+      fifo_clear => fifo_clear,
+      fifo_rd => fifo_rd,
+      rst_n => rst_n,
+      t_dat => t_dat,
+      wr_rfifo => wr_rfifo
+    );
+
+
+  ipen_AE <= ien_AE AND fifo_AE;
+  ipen_AF <= ien_AF AND ((pause_irq OR fifo_AF));
+  av_irq <= ipen_AE OR ipen_AF;
+  activity <= t_pause OR t_ena;
+  process (clk, rst_n)
+  begin
+    if rst_n = '0' then
+      pause_irq <= std_logic'('0');
+    elsif clk'event and clk = '1' then
+      -- only if fifo is not empty...
+      if std_logic'((t_pause AND NOT fifo_EF)) = '1' then 
+        pause_irq <= std_logic'('1');
+      elsif std_logic'(read_0) = '1' then 
+        pause_irq <= std_logic'('0');
+      end if;
+    end if;
+
+  end process;
+
+  process (clk, rst_n)
+  begin
+    if rst_n = '0' then
+      r_val <= std_logic'('0');
+      t_dav <= std_logic'('1');
+    elsif clk'event and clk = '1' then
+      r_val <= r_ena AND NOT wfifo_empty;
+      t_dav <= NOT rfifo_full;
+    end if;
+
+  end process;
+
+  process (clk, rst_n)
+  begin
+    if rst_n = '0' then
+      fifo_AE <= std_logic'('0');
+      fifo_AF <= std_logic'('0');
+      fifo_wr <= std_logic'('0');
+      rvalid <= std_logic'('0');
+      read_0 <= std_logic'('0');
+      ien_AE <= std_logic'('0');
+      ien_AF <= std_logic'('0');
+      ac <= std_logic'('0');
+      woverflow <= std_logic'('0');
+      internal_av_waitrequest <= std_logic'('1');
+    elsif clk'event and clk = '1' then
+      fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used)))<=std_logic_vector'("00000000000000000000000000001000")));
+      fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (Std_Logic_Vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used)))))))<=std_logic_vector'("00000000000000000000000000001000")));
+      fifo_wr <= std_logic'('0');
+      read_0 <= std_logic'('0');
+      internal_av_waitrequest <= NOT (((av_chipselect AND ((NOT av_write_n OR NOT av_read_n))) AND internal_av_waitrequest));
+      if std_logic'(activity) = '1' then 
+        ac <= std_logic'('1');
+      end if;
+      -- write
+      if std_logic'(((av_chipselect AND NOT av_write_n) AND internal_av_waitrequest)) = '1' then 
+        -- addr 1 is control; addr 0 is data
+        if std_logic'(av_address) = '1' then 
+          ien_AF <= av_writedata(0);
+          ien_AE <= av_writedata(1);
+          if std_logic'((av_writedata(10) AND NOT activity)) = '1' then 
+            ac <= std_logic'('0');
+          end if;
+        else
+          fifo_wr <= NOT fifo_FF;
+          woverflow <= fifo_FF;
+        end if;
+      end if;
+      -- read
+      if std_logic'(((av_chipselect AND NOT av_read_n) AND internal_av_waitrequest)) = '1' then 
+        -- addr 1 is interrupt; addr 0 is data
+        if std_logic'(NOT av_address) = '1' then 
+          rvalid <= NOT fifo_EF;
+        end if;
+        read_0 <= NOT av_address;
+      end if;
+    end if;
+
+  end process;
+
+  fifo_wdata <= av_writedata(7 DOWNTO 0);
+  fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect AND NOT av_read_n) AND internal_av_waitrequest) AND NOT av_address))) = '1'), NOT fifo_EF, std_logic'('0'));
+  av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(NOT fifo_FF) & A_ToStdLogicVector(NOT fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (Std_Logic_Vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(NOT fifo_FF) & A_ToStdLogicVector(NOT fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
+  process (clk, rst_n)
+  begin
+    if rst_n = '0' then
+      readyfordata <= std_logic'('0');
+    elsif clk'event and clk = '1' then
+      readyfordata <= NOT fifo_FF;
+    end if;
+
+  end process;
+
+  --vhdl renameroo for output signals
+  av_waitrequest <= internal_av_waitrequest;
+--synthesis translate_off
+    -- Tie off Atlantic Interface signals not used for simulation
+    process (clk)
+    begin
+      if clk'event and clk = '1' then
+        sim_t_pause <= std_logic'('0');
+        sim_t_ena <= std_logic'('0');
+        sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
+        sim_r_ena <= std_logic'('0');
+      end if;
+
+    end process;
+
+    r_ena <= sim_r_ena;
+    t_ena <= sim_t_ena;
+    t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
+    t_pause <= sim_t_pause;
+    process (fifo_EF)
+    begin
+        dataavailable <= NOT fifo_EF;
+
+    end process;
+
+--synthesis translate_on
+--synthesis read_comments_as_HDL on
+--    jtag_uart_0_alt_jtag_atlantic : alt_jtag_atlantic
+--      generic map(
+--        INSTANCE_ID => 0,
+--        LOG2_RXFIFO_DEPTH => 6,
+--        LOG2_TXFIFO_DEPTH => 6,
+--        SLD_AUTO_INSTANCE_INDEX => "YES"
+--      )
+--      port map(
+--                clk => clk,
+--                r_dat => r_dat,
+--                r_ena => r_ena,
+--                r_val => r_val,
+--                rst_n => rst_n,
+--                t_dat => t_dat,
+--                t_dav => t_dav,
+--                t_ena => t_ena,
+--                t_pause => t_pause
+--      );
+--
+--    process (clk, rst_n)
+--    begin
+--      if rst_n = '0' then
+--        dataavailable <= std_logic'('0');
+--      elsif clk'event and clk = '1' then
+--        dataavailable <= NOT fifo_EF;
+--      end if;
+--
+--    end process;
+--
+--synthesis read_comments_as_HDL off
+
+end europa;
+
diff --git a/memory_hw.tcl b/memory_hw.tcl
new file mode 100644
index 0000000..510aa16
--- /dev/null
+++ b/memory_hw.tcl
@@ -0,0 +1,47 @@
+# TCL File Generated by Component Editor 17.0
+# Mon Jun 11 22:55:14 BST 2018
+# DO NOT MODIFY
+
+
+# 
+# memory "memory" v1.0
+#  2018.06.11.22:55:14
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module memory
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME memory
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME memory
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
diff --git a/mz80b/cmt.vhd b/mz80b/cmt.vhd
new file mode 100644
index 0000000..187f1c7
--- /dev/null
+++ b/mz80b/cmt.vhd
@@ -0,0 +1,294 @@
+--
+-- cmt.vhd
+--
+-- Sharp PWM Tape I/F and Pseudo-CMT module
+-- for MZ-80B/2000 on FPGA
+--
+-- Nibbles Lab. 2013-2014
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity cmt is
+    Port (
+        RST_n                : in  std_logic;                            -- Reset
+        CLK                  : in  std_logic;                            -- System Clock
+        -- Interrupt
+        INTO                 : out std_logic;                            -- Tape action interrupt
+        -- Z80 Bus
+        ZCLK                 : in  std_logic;
+--      ZA8                  : in  std_logic_vector(7 downto 0);
+--      ZIWR_x               : in  std_logic;
+--      ZDI                  : in  std_logic_vector(7 downto 0);
+--      ZDO                  : out std_logic_vector(7 downto 0);
+        -- Tape signals
+        T_END                : out std_logic;                            -- Sense CMT(Motor on/off)
+        OPEN_x               : in  std_logic;                            -- Open
+        PLAY_x               : in  std_logic;                            -- Play
+        STOP_x               : in  std_logic;                            -- Stop
+        FF_x                 : in  std_logic;                            -- Fast Foward
+        REW_x                : in  std_logic;                            -- Rewind
+        APSS_x               : in  std_logic;                            -- APSS
+        FFREW                : in  std_logic;                            -- FF/REW mode
+        FMOTOR               : in  std_logic;                            -- FF/REW start
+        FLATCH               : in  std_logic;                            -- FF/REW latch
+        WREADY               : out std_logic;                            -- Write enable
+        TREADY               : out std_logic;                            -- Tape exist
+--      EXIN                 : in std_logic;                             -- CMT IN from I/O board
+        RDATA                : out std_logic;                            -- to 8255
+        -- Status Signal
+        SCLK                 : in  std_logic;                            -- Slow Clock(31.25kHz)
+        MZMODE               : in  std_logic;                            -- Hardware Mode
+        DMODE                : in  std_logic                             -- Display Mode
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);         -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                             -- HPS Interrupt.
+    );
+end cmt;
+
+architecture RTL of cmt is
+
+--
+-- Status
+--
+signal RPLBUF                : std_logic_vector(2 downto 0);
+signal REG_PL                : std_logic;
+signal RSTBUF                : std_logic_vector(2 downto 0);
+signal REJBUF                : std_logic_vector(2 downto 0);
+signal REG_EJ                : std_logic;
+signal RREBUF                : std_logic_vector(2 downto 0);
+signal REG_RE                : std_logic;
+signal RFFBUF                : std_logic_vector(2 downto 0);
+signal REG_FF                : std_logic;
+signal RASBUF                : std_logic_vector(2 downto 0);
+signal REG_AS                : std_logic;
+signal RLTBUF                : std_logic_vector(2 downto 0);
+signal RFMBUF                : std_logic_vector(2 downto 0);
+signal REG_RE_M              : std_logic;
+signal REG_FF_M              : std_logic;
+signal TAPE                  : std_logic;
+signal WP                    : std_logic;
+signal MOTOR                 : std_logic;
+signal PBIT                  : std_logic;
+signal RBYTE                 : std_logic_vector(15 downto 0);
+signal PON                   : std_logic;
+signal APSS                  : std_logic;
+signal FA                    : std_logic;
+--
+-- Pulse Generator
+--
+signal POUT                  : std_logic;
+signal PCNT                  : std_logic_vector(10 downto 0);
+signal PBUSY                 : std_logic;
+signal PEXT                  : std_logic_vector(4 downto 0);
+----
+---- Filters
+----
+--signal CNT3 : std_logic_vector(1 downto 0);
+--signal PL_BTN : std_logic_vector(1 downto 0);
+--signal ST_BTN : std_logic_vector(1 downto 0);
+--signal T_BTN : std_logic;
+----
+---- Divider
+----
+--signal DIV : std_logic_vector(13 downto 0);
+----
+---- Registers for Z80
+----
+--signal MADR : std_logic_vector(15 downto 0);
+--signal MBYTE : std_logic_vector(15 downto 0);
+--signal MCMD : std_logic_vector(7 downto 0);
+--signal STAT : std_logic_vector(7 downto 0);
+
+--
+-- Components
+--
+begin
+    --
+    -- HPS Bus
+    --
+    process( RST_n, CLK ) begin
+        if RST_n='0' then
+            WP               <='0';
+            MOTOR            <='0';
+            TAPE             <='0';
+            REG_PL           <='0';
+            REG_EJ           <='0';
+            REG_FF           <='0';
+            REG_RE           <='0';
+            REG_AS           <='0';
+            REG_FF_M         <='0';
+            REG_RE_M         <='0';
+            PBIT             <='0';
+            PON              <='0';
+            FA               <='0';
+            PEXT             <=(others=>'0');
+        elsif CLK'event and CLK='1' then
+            -- Edge Sense
+            if MZMODE='0' then
+                RPLBUF<=RPLBUF(1 downto 0)&PLAY_x;                       -- MZ-80B
+            else
+                RPLBUF       <= RPLBUF(1 downto 0)&(not PLAY_x);         -- MZ-2000
+            end if;
+            if RPLBUF(2 downto 1)="01" then
+                REG_PL       <= TAPE;
+                REG_AS       <= '0';
+            end if;
+            if MZMODE='0' then
+                RSTBUF       <= RSTBUF(1 downto 0)&STOP_x;               -- MZ-80B
+            else
+                RSTBUF       <= RSTBUF(1 downto 0)&(not STOP_x);         -- MZ-2000
+            end if;
+            if RSTBUF(2 downto 1)="01" then
+                MOTOR        <= '0';
+                REG_AS       <= '0';
+                REG_FF       <= '0';
+                REG_RE       <= '0';
+            end if;
+            REJBUF<=REJBUF(1 downto 0)&(not OPEN_x);
+            if REJBUF(2 downto 1)="01" then
+                REG_EJ       <= '1';
+                TAPE         <= '0';
+                REG_AS       <= '0';
+                REG_FF       <= '0';
+                REG_RE       <= '0';
+            end if;
+            if MZMODE='0' then                                           -- MZ-80B
+                RLTBUF       <= RLTBUF(1 downto 0)&FLATCH;
+                if RLTBUF(2 downto 1)="01" then
+                    REG_RE_M <= not FFREW;
+                    REG_FF_M <= FFREW;
+                end if;
+                RFMBUF<=RFMBUF(1 downto 0)&FMOTOR;
+                if RFMBUF(2 downto 1)="01" then
+                    REG_RE   <= REG_RE_M and TAPE;
+                    REG_FF   <= REG_FF_M and TAPE;
+                    REG_AS   <= TAPE;
+                end if;
+            else                                                         -- MZ-2000
+                RREBUF<=RREBUF(1 downto 0)&(not REW_x);
+                if RREBUF(2 downto 1)="01" then
+                    REG_RE   <= TAPE;
+                end if;
+                RFFBUF<=RFFBUF(1 downto 0)&(not FF_x);
+                if RFFBUF(2 downto 1)="01" then
+                    REG_FF   <= TAPE;
+                end if;
+                RASBUF<=RASBUF(1 downto 0)&(not APSS_x);
+                if RASBUF(2 downto 1)="01" then
+                    REG_AS   <= TAPE;
+                end if;
+            end if;
+            -- Register
+            if IOCTL_RD='1' and IOCTL_WR='1' then
+                if IOCTL_ADDR=X"0010" and PBUSY='0' then                 -- MZ_CMT_POUT
+                    PBIT     <= IOCTL_DOUT(0);
+                    PEXT     <= "11111";
+                else
+                    PEXT     <= PEXT(3 downto 0)&'0';
+                end if;
+                if IOCTL_ADDR=X"0011" then                               -- MZ_CMT_STATUS
+                    REG_AS   <= REG_AS and (not IOCTL_DOUT(4));
+                    REG_RE   <= REG_RE and (not IOCTL_DOUT(3));
+                    REG_FF   <= REG_FF and (not IOCTL_DOUT(2));
+                    REG_PL   <= REG_PL and (not IOCTL_DOUT(1));
+                    REG_EJ   <= REG_EJ and (not IOCTL_DOUT(0));
+                end if;
+                if IOCTL_ADDR=X"0012" then                               -- MZ_CMT_COUNT
+                    RBYTE(7 downto 0)  <= IOCTL_DOUT;
+                end if;
+                if IOCTL_ADDR=X"0013" then                               -- MZ_CMT_COUNTH
+                    RBYTE(15 downto 8) <= IOCTL_DOUT;
+                end if;
+                if IOCTL_ADDR=X"0014" then                               -- MZ_CMT_CTRL
+                    FA       <= IOCTL_DOUT(4);
+                    PON      <= IOCTL_DOUT(3);
+                    WP       <= IOCTL_DOUT(2);
+                    MOTOR    <= IOCTL_DOUT(1);
+                    TAPE     <= IOCTL_DOUT(0);
+                end if;
+            else
+                PEXT         <= PEXT(3 downto 0)&'0';
+            end if;
+        end if;
+    end process;
+
+    IOCTL_DIN <= "0000000"&PBUSY                                     when IOCTL_RD='1' and IOCTL_ADDR=X"0010" else    -- MZ_CMT_POUT
+                 "000"&REG_AS&REG_RE&REG_FF&REG_PL&REG_EJ when IOCTL_RD='1' and IOCTL_ADDR=X"0011" else    -- MZ_CMT_STATUS
+                 "000"&FA&PON&WP&MOTOR&TAPE                     when IOCTL_RD='1' and IOCTL_ADDR=X"0014" else    -- MZ_CMT_CTRL
+                 "00000000";
+    APSS      <= REG_AS or FA;
+    INTO      <= REG_PL or REG_EJ or REG_RE or REG_FF;
+    WREADY    <= not WP;
+    TREADY    <= not TAPE;
+    T_END     <= not MOTOR;
+    RDATA     <= POUT or PON;
+
+    --
+    -- PWM pulse generate
+    --
+    process( RST_n, ZCLK ) begin
+        if RST_n='0' then
+            POUT  <='0';
+            PBUSY <='0';
+            PCNT  <=(others=>'0');
+        elsif ZCLK'event and ZCLK='1' then
+            if PEXT(4)='1' then
+                if PBIT='0' then
+                    PCNT <= "01010011011";    --667
+                else
+                    PCNT <= "10100110100";    --1332
+                end if;
+                POUT     <= '1';
+                PBUSY    <= '1';
+            else
+                if POUT='1' and PCNT=0 then
+                    if PBIT='0' then
+                        PCNT <= "01010011000";    --664
+                    else
+                        PCNT <= "10100110110";    --1334
+                    end if;
+                    POUT  <= '0';
+                elsif POUT='0' and PCNT=0 then
+                    PBUSY <= '0';
+                else
+                    PCNT  <= PCNT-'1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+--    --
+--    -- MZ-80B Action for Quick Access
+--    --
+--    process( reset, ZCLK ) begin
+--        if reset='1' then
+--            MADR<=(others=>'0');
+--            MBYTE<=(others=>'0');
+--            MCMD<=(others=>'0');
+--            interrupt<='1';
+--        elsif ZCLK'event and ZCLK='0' then
+--            if ZIWR_x='0' and ZA8(7 downto 3)="10001" then
+--                case ZA8(2 downto 0) is
+--                    when "000" => MADR(7 downto 0)<=ZDI; interrupt<='1';
+--                    when "001" => MADR(15 downto 8)<=ZDI; interrupt<='1';
+--                    when "010" => MBYTE(7 downto 0)<=ZDI; interrupt<='1';
+--                    when "011" => MBYTE(15 downto 8)<=ZDI; interrupt<='1';
+--                    when others => MCMD<=ZDI; interrupt<=not(ZDI(7) or ZDI(6) or ZDI(5) or ZDI(4) or ZDI(3) or ZDI(2) or ZDI(1) or ZDI(0));
+--                end case;
+--            end if;
+--        end if;
+--    end process;
+
+--    ZDO<=STAT;
+
+end RTL;
diff --git a/mz80b/fd55b.vhd b/mz80b/fd55b.vhd
new file mode 100644
index 0000000..c79ddef
--- /dev/null
+++ b/mz80b/fd55b.vhd
@@ -0,0 +1,647 @@
+--
+-- fd55b.vhd
+--
+-- Floppy Disk Drive Emulation module
+-- for MZ-80B/2000 on FPGA
+--
+-- Nibbles Lab. 2014-2015
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity fd55b is
+    generic
+    (
+        DS_SW                : std_logic_vector(4 downto 1) := "1111";
+        REG_ADDR             : std_logic_vector(15 downto 0) := "0000000000000000"
+    );
+    Port (
+        RST_n                : in  std_logic;                            -- Reset
+        CLK                  : in  std_logic;                            -- System Clock
+        -- Interrupt
+        INTO                 : out std_logic;                            -- Step Pulse interrupt
+        -- FD signals
+        FCLK                 : in  std_logic;
+        DS_n                 : in  std_logic_vector(4 downto 1);         -- Drive Select
+        HS                   : in  std_logic;                            -- Head Select
+        MOTOR_n              : in  std_logic;                            -- Motor On
+        INDEX_n              : out std_logic;                            -- Index Hole Detect
+        TRACK00              : out std_logic;                            -- Track 0
+        WPRT_n               : out std_logic;                            -- Write Protect
+        STEP_n               : in  std_logic;                            -- Head Step In/Out
+        DIREC                : in  std_logic;                            -- Head Step Direction
+        WG_n                 : in  std_logic;                            -- Write Gate
+        DTCLK                : out std_logic;                            -- Data Clock
+        FDI                  : in  std_logic_vector(7 downto 0);         -- Write Data
+        FDO                  : out std_logic_vector(7 downto 0);         -- Read Data
+        -- Buffer RAM I/F
+        BCS_n                : out std_logic;                            -- RAM Request
+        BADR                 : out std_logic_vector(22 downto 0);        -- RAM Address
+        BWR_n                : out std_logic;                            -- RAM Write Signal
+        BDI                  : in  std_logic_vector(7 downto 0);         -- Data Bus Input from RAM
+        BDO                  : out std_logic_vector(7 downto 0)          -- Data Bus Output to RAM
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);         -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                             -- HPS Interrupt.
+    );
+end fd55b;
+
+architecture RTL of fd55b is
+
+--
+-- Signals
+--
+signal DS                    : std_logic;                                -- Drive Select
+signal HS_n                  : std_logic;                                -- Side One Select
+signal DIV                   : std_logic_vector(6 downto 0);             -- Divider
+signal SS                    : std_logic;                                -- ROM Address multiplexer
+signal PC                    : std_logic_vector(4 downto 0);             -- ROM Address
+signal OP                    : std_logic_vector(7 downto 0);             -- OP code
+signal ROMOUT                : std_logic_vector(31 downto 0);            -- ROM Data
+signal TRACK                 : std_logic_vector(5 downto 0);             -- Track Number
+signal MF                    : std_logic;                                -- Modify Flag
+signal PHASE                 : std_logic;                                -- Phase of Process
+signal SSIZE                 : std_logic_vector(3 downto 0);             -- Sector Size
+signal FDOi                  : std_logic_vector(7 downto 0);             -- Output Data(internal)
+signal WP                    : std_logic;                                -- Write Protect Flag
+signal DISK                  : std_logic;                                -- Disk Exist
+signal D88                   : std_logic;                                -- D88 flag(more 16bytes)
+signal RSTBUF                : std_logic_vector(2 downto 0);             -- Step Pulse Shift Register
+signal REG_ST                : std_logic;                                -- Step Pulse Detect
+signal CS                    : std_logic;                                -- Chip Select
+signal RSEL                  : std_logic_vector(4 downto 0);             -- Register Select
+signal HSEL                  : std_logic;                                -- Register Select by Head
+signal GAP3                  : std_logic_vector(7 downto 0);             -- GAP3 length
+signal GAP4                  : std_logic_vector(15 downto 0);            -- GAP4 length
+signal BADRi                 : std_logic_vector(22 downto 0);            -- RAM Address(internal)
+signal BDOi                  : std_logic_vector(7 downto 0);             -- RAM Write Data(internal)
+signal OUTEN                 : std_logic;                                -- Drive Selected, Disk Inserted, Motor On
+---- Register set of side 0
+signal DDEN0                 : std_logic;                                -- density 0=FM,1=MFM side0
+signal COUNT0                : std_logic_vector(10 downto 0);            -- Timing Counter(Count down)
+signal PSECT0                : std_logic_vector(3 downto 0);             -- Phisical Sector Number
+signal LSECT0                : std_logic_vector(7 downto 0);             -- Logical Sector Number
+signal MAXSECT0              : std_logic_vector(3 downto 0);             -- Number of Sectors side0
+signal TRADR0                : std_logic_vector(22 downto 0);            -- Track data top address side0
+signal FDO0i                 : std_logic_vector(7 downto 0);             -- Output Data(internal)
+signal PC0                   : std_logic_vector(4 downto 0);             -- ROM Address
+signal ROMOUT0               : std_logic_vector(31 downto 0);            -- ROM Data
+signal OP0                   : std_logic_vector(7 downto 0);             -- OP code
+signal FDAT0                 : std_logic_vector(7 downto 0);             -- Format Data
+signal PHASE0                : std_logic;                                -- Phase of Process
+signal DCLK0                 : std_logic;                                -- Data Clock(internal)
+signal FIRST0                : std_logic;                                -- First Action
+signal MF0                   : std_logic;                                -- Modify Flag
+signal LSEL0                 : std_logic_vector(3 downto 0);             -- ID register select
+signal LSEC00                : std_logic_vector(7 downto 0);             -- Logical Sector Number table side0
+signal LSEC01                : std_logic_vector(7 downto 0);
+signal LSEC02                : std_logic_vector(7 downto 0);
+signal LSEC03                : std_logic_vector(7 downto 0);
+signal LSEC04                : std_logic_vector(7 downto 0);
+signal LSEC05                : std_logic_vector(7 downto 0);
+signal LSEC06                : std_logic_vector(7 downto 0);
+signal LSEC07                : std_logic_vector(7 downto 0);
+signal LSEC08                : std_logic_vector(7 downto 0);
+signal LSEC09                : std_logic_vector(7 downto 0);
+signal LSEC0A                : std_logic_vector(7 downto 0);
+signal LSEC0B                : std_logic_vector(7 downto 0);
+signal LSEC0C                : std_logic_vector(7 downto 0);
+signal LSEC0D                : std_logic_vector(7 downto 0);
+signal LSEC0E                : std_logic_vector(7 downto 0);
+signal LSEC0F                : std_logic_vector(7 downto 0);
+signal BADR0i                : std_logic_vector(22 downto 0);            -- RAM Address(internal)
+signal BDO0i                 : std_logic_vector(7 downto 0);             -- RAM Write Data(internal)
+signal INDEX0_n              : std_logic;                                -- Index Pulse(internal)
+signal IPCNT0                : std_logic_vector(2 downto 0);             -- Index Pulse Counter
+signal GAP30                 : std_logic_vector(7 downto 0);             -- GAP3 length
+signal GAP40                 : std_logic_vector(15 downto 0);            -- GAP4 length
+---- Register set of side 1
+signal DDEN1                 : std_logic;                                -- density 0=FM,1=MFM side1
+signal COUNT1                : std_logic_vector(10 downto 0);            -- Timing Counter(Count down)
+signal PSECT1                : std_logic_vector(3 downto 0);             -- Phisical Sector Number
+signal LSECT1                : std_logic_vector(7 downto 0);             -- Logical Sector Number
+signal MAXSECT1              : std_logic_vector(3 downto 0);             -- Number of Sectors side1
+signal TRADR1                : std_logic_vector(22 downto 0);            -- Track data top address side1
+signal FDO1i                 : std_logic_vector(7 downto 0);             -- Output Data(internal)
+signal PC1                   : std_logic_vector(4 downto 0);             -- ROM Address
+signal ROMOUT1               : std_logic_vector(31 downto 0);            -- ROM Data
+signal OP1                   : std_logic_vector(7 downto 0);             -- OP code
+signal FDAT1                 : std_logic_vector(7 downto 0);             -- Format Data
+signal PHASE1                : std_logic;                                -- Phase of Process
+signal DCLK1                 : std_logic;                                -- Data Clock(internal)
+signal FIRST1                : std_logic;                                -- First Action
+signal MF1                   : std_logic;                                -- Modify Flag
+signal LSEL1                 : std_logic_vector(3 downto 0);             -- ID register select
+signal LSEC10                : std_logic_vector(7 downto 0);             -- Logical Sector Number table side1
+signal LSEC11                : std_logic_vector(7 downto 0);
+signal LSEC12                : std_logic_vector(7 downto 0);
+signal LSEC13                : std_logic_vector(7 downto 0);
+signal LSEC14                : std_logic_vector(7 downto 0);
+signal LSEC15                : std_logic_vector(7 downto 0);
+signal LSEC16                : std_logic_vector(7 downto 0);
+signal LSEC17                : std_logic_vector(7 downto 0);
+signal LSEC18                : std_logic_vector(7 downto 0);
+signal LSEC19                : std_logic_vector(7 downto 0);
+signal LSEC1A                : std_logic_vector(7 downto 0);
+signal LSEC1B                : std_logic_vector(7 downto 0);
+signal LSEC1C                : std_logic_vector(7 downto 0);
+signal LSEC1D                : std_logic_vector(7 downto 0);
+signal LSEC1E                : std_logic_vector(7 downto 0);
+signal LSEC1F                : std_logic_vector(7 downto 0);
+signal BADR1i                : std_logic_vector(22 downto 0);            -- RAM Address(internal)
+signal BDO1i                 : std_logic_vector(7 downto 0);             -- RAM Write Data(internal)
+signal INDEX1_n              : std_logic;                                -- Index Pulse(internal)
+signal IPCNT1                : std_logic_vector(2 downto 0);             -- Index Pulse Counter
+signal GAP31                 : std_logic_vector(7 downto 0);             -- GAP3 length
+signal GAP41                 : std_logic_vector(15 downto 0);            -- GAP4 length
+
+begin
+
+    --
+    -- Format Direction Table
+    --
+    process( PC ) begin
+        case( PC ) is
+            -- FM
+            when "00000" => ROMOUT<="1111"&"0000"&"11111111"&"0000000000001111";
+            when "00001" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000101";
+            when "00010" => ROMOUT<="1111"&"0000"&"11111110"&"0000000000000000";
+            when "00011" => ROMOUT<="0010"&"0000"&"00000000"&"0000000000000011";
+            when "00100" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
+            when "00101" => ROMOUT<="1111"&"0000"&"11111111"&"0000000000001010";
+            when "00110" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000101";
+            when "00111" => ROMOUT<="0100"&"0000"&"11111011"&"00000"&SSIZE&"0000000";
+            when "01000" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
+            when "01001" => ROMOUT<="1100"&"0001"&"11111111"&"00000000"&GAP3;
+            when "01010" => ROMOUT<="0000"&"0000"&"11111111"&GAP4;
+            -- MFM
+            when "10000" => ROMOUT<="1111"&"0000"&"01001110"&"0000000000011111";
+            when "10001" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000001011";
+            when "10010" => ROMOUT<="1111"&"0000"&"10100001"&"0000000000000010";
+            when "10011" => ROMOUT<="1111"&"0000"&"11111110"&"0000000000000000";
+            when "10100" => ROMOUT<="0010"&"0000"&"00000000"&"0000000000000011";
+            when "10101" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
+            when "10110" => ROMOUT<="1111"&"0000"&"01001110"&"0000000000010101";
+            when "10111" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000001011";
+            when "11000" => ROMOUT<="1111"&"0000"&"10100001"&"0000000000000010";
+            when "11001" => ROMOUT<="0100"&"0000"&"11111011"&"00000"&SSIZE&"0000000";
+            when "11010" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
+            when "11011" => ROMOUT<="1100"&"0001"&"01001110"&"00000000"&GAP3;
+            when "11100" => ROMOUT<="0000"&"0000"&"01001110"&GAP4;
+            when others => ROMOUT<=(others=>'0');
+        end case;
+    end process;
+
+    --
+    -- Decode Sector size from Sector ID
+    --
+    process( SS, LSECT0(1 downto 0), LSECT1(1 downto 0) ) begin
+        case( SS ) is
+            when '0' =>
+                case( LSECT0(1 downto 0) ) is
+                    when "00"   => SSIZE<="0001";
+                    when "01"   => SSIZE<="0010";
+                    when "10"   => SSIZE<="0100";
+                    when others => SSIZE<="1000";
+                end case;
+            when others =>
+                case( LSECT1(1 downto 0) ) is
+                    when "00"   => SSIZE<="0001";
+                    when "01"   => SSIZE<="0010";
+                    when "10"   => SSIZE<="0100";
+                    when others => SSIZE<="1000";
+                end case;
+        end case;
+    end process;
+
+    --
+    -- Select GAP3/GAP4 length
+    --
+    GAP3 <= GAP30 when SS='0' else GAP31;
+    GAP4 <= GAP40 when SS='0' else GAP41;
+
+    --
+    -- FDT access
+    --
+    process( RST_n, FCLK ) begin
+        if RST_n='0' then
+            SS<='0';
+        elsif FCLK'event and FCLK='1' then
+            SS<=not SS;
+            if SS='0' then
+                ROMOUT0<=ROMOUT;
+            else
+                ROMOUT1<=ROMOUT;
+            end if;
+        end if;
+    end process;
+    PC<=PC0 when SS='0' else PC1;
+
+    --
+    -- Sector Table
+    --
+    process( PSECT0, LSEC00, LSEC01, LSEC02, LSEC03, LSEC04, LSEC05, LSEC06, LSEC07, LSEC08, LSEC09, LSEC0A, LSEC0B, LSEC0C, LSEC0D, LSEC0E, LSEC0F ) begin
+        case PSECT0 is
+            when "0000" => LSECT0<=LSEC00;
+            when "0001" => LSECT0<=LSEC01;
+            when "0010" => LSECT0<=LSEC02;
+            when "0011" => LSECT0<=LSEC03;
+            when "0100" => LSECT0<=LSEC04;
+            when "0101" => LSECT0<=LSEC05;
+            when "0110" => LSECT0<=LSEC06;
+            when "0111" => LSECT0<=LSEC07;
+            when "1000" => LSECT0<=LSEC08;
+            when "1001" => LSECT0<=LSEC09;
+            when "1010" => LSECT0<=LSEC0A;
+            when "1011" => LSECT0<=LSEC0B;
+            when "1100" => LSECT0<=LSEC0C;
+            when "1101" => LSECT0<=LSEC0D;
+            when "1110" => LSECT0<=LSEC0E;
+            when others => LSECT0<=LSEC0F;
+        end case;
+    end process;
+    process( PSECT1, LSEC10, LSEC11, LSEC12, LSEC13, LSEC14, LSEC15, LSEC16, LSEC17, LSEC18, LSEC19, LSEC1A, LSEC1B, LSEC1C, LSEC1D, LSEC1E, LSEC1F ) begin
+        case PSECT1 is
+            when "0000" => LSECT1<=LSEC10;
+            when "0001" => LSECT1<=LSEC11;
+            when "0010" => LSECT1<=LSEC12;
+            when "0011" => LSECT1<=LSEC13;
+            when "0100" => LSECT1<=LSEC14;
+            when "0101" => LSECT1<=LSEC15;
+            when "0110" => LSECT1<=LSEC16;
+            when "0111" => LSECT1<=LSEC17;
+            when "1000" => LSECT1<=LSEC18;
+            when "1001" => LSECT1<=LSEC19;
+            when "1010" => LSECT1<=LSEC1A;
+            when "1011" => LSECT1<=LSEC1B;
+            when "1100" => LSECT1<=LSEC1C;
+            when "1101" => LSECT1<=LSEC1D;
+            when "1110" => LSECT1<=LSEC1E;
+            when others => LSECT1<=LSEC1F;
+        end case;
+    end process;
+
+    --
+    -- Clock Divider
+    --
+    process( RST_n, FCLK ) begin
+        if RST_n='0' then
+            DIV<=(others=>'0');
+            DCLK0<='0';
+            DCLK1<='0';
+        elsif FCLK'event and FCLK='1' then
+            DIV<=DIV+'1';
+            if DIV(5 downto 0)="111111" then
+                if MOTOR_n='0' and (DDEN0='1' or (DDEN0='0' and DIV(6)='1')) then
+                    DCLK0<='1';
+                else
+                    DCLK0<='0';
+                end if;
+                if MOTOR_n='0' and (DDEN1='1' or (DDEN1='0' and DIV(6)='1')) then
+                    DCLK1<='1';
+                else
+                    DCLK1<='0';
+                end if;
+            else
+                DCLK0<='0';
+                DCLK1<='0';
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Track Sequencer
+    --
+    process( RST_n, FCLK ) begin
+        if RST_n='0' then
+            -- Side 0
+            PHASE0<='0';
+            COUNT0<=(others=>'0');
+            PSECT0<=(others=>'0');
+            PC0(3 downto 0)<=(others=>'0');
+            BADR0i<=(others=>'0');
+            BDO0i<=(others=>'0');
+            INDEX0_n<='1';
+            IPCNT0<=(others=>'1');
+            -- Side 1
+            PHASE1<='0';
+            COUNT1<=(others=>'0');
+            PSECT1<=(others=>'0');
+            PC1(3 downto 0)<=(others=>'0');
+            BADR1i<=(others=>'0');
+            BDO1i<=(others=>'0');
+            INDEX1_n<='1';
+            IPCNT1<=(others=>'1');
+        elsif FCLK'event and FCLK='1' then
+            -- Disk Removed
+            if DISK='0' then
+                MF0<='0';
+                MF1<='0';
+            end if;
+            -- Sequencer
+            -- Side 0
+            if DCLK0='1' then
+                PHASE0<=not PHASE0;
+                if PHASE0='0' then
+                    case OP0(7 downto 4) is
+                        when "0010" =>    -- ID
+                            case COUNT0(1 downto 0) is
+                                when "11" =>
+                                    FDO0i<="00"&TRACK;
+                                when "10" =>
+                                    FDO0i<="0000000"&LSECT0(7);
+                                when "01" =>
+                                    FDO0i<="000"&LSECT0(6 downto 2);
+                                when others =>
+                                    FDO0i<="000000"&LSECT0(1 downto 0);
+                            end case;
+                        when "0100" =>    -- DATA
+                            if FIRST0='1' then
+                                FDO0i<=FDAT0;
+                            else
+                                FDO0i<=BDI;
+                                BADR0i<=BADR0i+'1';
+                            end if;
+                        when "0000" =>    -- JMP
+                            if COUNT0="00000000000" then
+                                PC0(3 downto 0)<=OP0(3 downto 0);
+                            end if;
+                            FDO0i<=FDAT0;
+                        when "1100" =>    -- LOOP
+                            if COUNT0="00000000000" then
+                                if PSECT0=MAXSECT0 then
+                                    PSECT0<=(others=>'0');
+                                else
+                                    PC0(3 downto 0)<=OP0(3 downto 0);
+                                    PSECT0<=PSECT0+'1';
+                                end if;
+                            end if;
+                            FDO0i<=FDAT0;
+                        when others =>    -- NOP
+                            FDO0i<=FDAT0;
+                    end case;
+                else    -- PHASE='1'
+                    if COUNT0="00000000000" then
+                        OP0<=ROMOUT0(31 downto 24);
+                        FDAT0<=ROMOUT0(23 downto 16);
+                        COUNT0<=ROMOUT0(10 downto 0);
+                        FIRST0<='1';
+                        PC0(3 downto 0)<=PC0(3 downto 0)+'1';
+                        if PC0(3 downto 0)="0000" then
+                            BADR0i<=TRADR0;
+                        end if;
+                        if OP0(7 downto 4)="0100" and D88='1' then    -- DATA
+                            BADR0i<=BADR0i+"10000";
+                        end if;
+                    else
+                        FIRST0<='0';
+                        COUNT0<=COUNT0-'1';
+                        if OP0(7 downto 4)="0100" then    -- DATA
+                            if WG_n='0' and WP='0' then
+                                BDO0i<=FDI;
+                                MF0<='1';
+                            end if;
+                        end if;
+                    end if;
+                end if;
+                -- Index Pulse
+                if PC0(3 downto 0)="0000" then
+                    IPCNT0<=(others=>'0');
+                    INDEX0_n<='0';
+                else
+                    if IPCNT0="111" then
+                        INDEX0_n<='1';
+                    else
+                        IPCNT0<=IPCNT0+'1';
+                    end if;
+                end if;
+            end if;
+            -- Side 1
+            if DCLK1='1' then
+                PHASE1<=not PHASE1;
+                if PHASE1='0' then
+                    case OP1(7 downto 4) is
+                        when "0010" =>    -- ID
+                            case COUNT1(1 downto 0) is
+                                when "11" =>
+                                    FDO1i<="00"&TRACK;
+                                when "10" =>
+                                    FDO1i<="0000000"&LSECT1(7);
+                                when "01" =>
+                                    FDO1i<="000"&LSECT1(6 downto 2);
+                                when others =>
+                                    FDO1i<="000000"&LSECT1(1 downto 0);
+                            end case;
+                        when "0100" =>    -- DATA
+                            if FIRST1='1' then
+                                FDO1i<=FDAT1;
+                            else
+                                FDO1i<=BDI;
+                                BADR1i<=BADR1i+'1';
+                            end if;
+                        when "0000" =>    -- JMP
+                            if COUNT1="00000000000" then
+                                PC1(3 downto 0)<=OP1(3 downto 0);
+                            end if;
+                            FDO1i<=FDAT1;
+                        when "1100" =>    -- LOOP
+                            if COUNT1="00000000000" then
+                                if PSECT1=MAXSECT1 then
+                                    PSECT1<=(others=>'0');
+                                else
+                                    PC1(3 downto 0)<=OP1(3 downto 0);
+                                    PSECT1<=PSECT1+'1';
+                                end if;
+                            end if;
+                            FDO1i<=FDAT1;
+                        when others =>    -- NOP
+                            FDO1i<=FDAT1;
+                    end case;
+                else    -- PHASE='1'
+                    if COUNT1="00000000000" then
+                        OP1<=ROMOUT1(31 downto 24);
+                        FDAT1<=ROMOUT1(23 downto 16);
+                        COUNT1<=ROMOUT1(10 downto 0);
+                        FIRST1<='1';
+                        PC1(3 downto 0)<=PC1(3 downto 0)+'1';
+                        if PC1(3 downto 0)="0000" then
+                            BADR1i<=TRADR1;
+                        end if;
+                        if OP1(7 downto 4)="0100" and D88='1' then    -- DATA
+                            BADR1i<=BADR1i+"10000";
+                        end if;
+                    else
+                        FIRST1<='0';
+                        COUNT1<=COUNT1-'1';
+                        if OP1(7 downto 4)="0100" then    -- DATA
+                            if WG_n='0' and WP='0' then
+                                BDO1i<=FDI;
+                                MF1<='1';
+                            end if;
+                        end if;
+                    end if;
+                end if;
+                -- Index Pulse
+                if PC1(3 downto 0)="0000" then
+                    IPCNT1<=(others=>'0');
+                    INDEX1_n<='0';
+                else
+                    if IPCNT1="111" then
+                        INDEX1_n<='1';
+                    else
+                        IPCNT1<=IPCNT1+'1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    PC0(4)    <= DDEN0;
+    PC1(4)    <= DDEN1;
+    MF        <= MF0 or MF1;
+
+    DS        <= not((DS_n(1) or DS_SW(1)) and (DS_n(2) or DS_SW(2)) and (DS_n(3) or DS_SW(3)) and (DS_n(4) or DS_SW(4)));
+    OUTEN     <= '1' when DS='1' and DISK='1' and MOTOR_n='0' else '0';
+    HS_n      <= not HS;
+
+    WPRT_n    <= not WP when DS='1' and DISK='1' else '1';
+    TRACK00   <= '0' when TRACK="000000" and DS='1' else '1';
+    FDO       <= FDOi when DS='1' and DISK='1' else (others=>'0');
+    DTCLK     <= not PHASE when OUTEN='1' else '0';
+
+    --
+    -- Select Output with Head Select
+    --
+    process( HS_n, PHASE0, FDO0i, INDEX0_n, OP0, BADR0i, BDO0i, PHASE1, FDO1i, INDEX1_n, OP1, BADR1i, BDO1i ) begin
+        if HS_n='0' then
+            PHASE   <= PHASE0;
+            FDOi    <= FDO0i;
+            BADRi   <= BADR0i;
+            BDOi    <= BDO0i;
+            INDEX_n <= INDEX0_n or (not (DS and DISK));
+            OP      <= OP0;
+        else
+            PHASE   <= PHASE1;
+            FDOi    <= FDO1i;
+            BADRi   <= BADR1i;
+            BDOi    <= BDO1i;
+            INDEX_n <= INDEX1_n or (not (DS and DISK));
+            OP      <= OP1;
+        end if;
+    end process;
+
+    BCS_n <= '0' when PHASE='0' and OP(7 downto 4)="0100" and OUTEN='1' else '1';    -- DATA
+    BWR_n <= '0' when PHASE='0' and OP(7 downto 4)="0100" and WG_n='0' and WP='0' and OUTEN='1' else '1';    -- DATA
+    BADR  <= BADRi when DS='1' else (others=>'0');
+    BDO   <= BDOi when DS='1' else (others=>'0');
+
+    --
+    -- Avalon Bus
+    --
+    process( RST_n, CLK ) begin
+        if RST_n='0' then
+            DISK   <='0';
+            DDEN0  <='0';
+            DDEN1  <='0';
+            REG_ST <='0';
+            TRACK  <=(others=>'0');
+            WP     <='0';
+        elsif CLK'event and CLK='1' then
+            -- Edge Sense
+            RSTBUF             <= RSTBUF(1 downto 0)&((not STEP_n) and DS);
+            if RSTBUF(2 downto 1)="01" then
+                REG_ST         <= '1';
+            end if;
+            -- Register
+            if IOCTL_RD='1' and IOCTL_WR='1' and CS='1' then
+                case RSEL is
+                    when "00000"|"00001" =>                              -- MZ_FDx_CTRL
+                        D88    <= IOCTL_DOUT(2);
+                        WP     <= IOCTL_DOUT(1);
+                        DISK   <= IOCTL_DOUT(0);
+                    when "00010"|"00011" =>                              -- MZ_FDx_TRK
+                        TRACK  <= IOCTL_DOUT(5 downto 0);
+                    when "00100"|"00101" =>                              -- MZ_FDx_STEP
+                        REG_ST <= REG_ST and (not IOCTL_DOUT(0));
+                    when "00110"|"00111" =>                              -- MZ_FDx_HSEL
+                        HSEL   <= IOCTL_DOUT(0);
+                    when "01000" =>                                      -- MZ_FDx_ID
+                        case LSEL0 is
+                            when "0000" => LSEC00<=IOCTL_DOUT;
+                            when "0001" => LSEC01<=IOCTL_DOUT;
+                            when "0010" => LSEC02<=IOCTL_DOUT;
+                            when "0011" => LSEC03<=IOCTL_DOUT;
+                            when "0100" => LSEC04<=IOCTL_DOUT;
+                            when "0101" => LSEC05<=IOCTL_DOUT;
+                            when "0110" => LSEC06<=IOCTL_DOUT;
+                            when "0111" => LSEC07<=IOCTL_DOUT;
+                            when "1000" => LSEC08<=IOCTL_DOUT;
+                            when "1001" => LSEC09<=IOCTL_DOUT;
+                            when "1010" => LSEC0A<=IOCTL_DOUT;
+                            when "1011" => LSEC0B<=IOCTL_DOUT;
+                            when "1100" => LSEC0C<=IOCTL_DOUT;
+                            when "1101" => LSEC0D<=IOCTL_DOUT;
+                            when "1110" => LSEC0E<=IOCTL_DOUT;
+                            when others => LSEC0F<=IOCTL_DOUT;
+                        end case;
+                    when "01001" =>
+                        case LSEL1 is
+                            when "0000" => LSEC10<=IOCTL_DOUT;
+                            when "0001" => LSEC11<=IOCTL_DOUT;
+                            when "0010" => LSEC12<=IOCTL_DOUT;
+                            when "0011" => LSEC13<=IOCTL_DOUT;
+                            when "0100" => LSEC14<=IOCTL_DOUT;
+                            when "0101" => LSEC15<=IOCTL_DOUT;
+                            when "0110" => LSEC16<=IOCTL_DOUT;
+                            when "0111" => LSEC17<=IOCTL_DOUT;
+                            when "1000" => LSEC18<=IOCTL_DOUT;
+                            when "1001" => LSEC19<=IOCTL_DOUT;
+                            when "1010" => LSEC1A<=IOCTL_DOUT;
+                            when "1011" => LSEC1B<=IOCTL_DOUT;
+                            when "1100" => LSEC1C<=IOCTL_DOUT;
+                            when "1101" => LSEC1D<=IOCTL_DOUT;
+                            when "1110" => LSEC1E<=IOCTL_DOUT;
+                            when others => LSEC1F<=IOCTL_DOUT;
+                        end case;
+                    when "01010" => LSEL0                      <=IOCTL_DOUT(3 downto 0);    -- MZ_FDx_LSEL
+                    when "01011" => LSEL1                      <=IOCTL_DOUT(3 downto 0);
+                    when "01100" => DDEN0                      <=IOCTL_DOUT(0);             -- MZ_FDx_DDEN
+                    when "01101" => DDEN1                      <=IOCTL_DOUT(0);
+                    when "01110" => MAXSECT0                   <=IOCTL_DOUT(3 downto 0);    -- MZ_FDx_MAXS
+                    when "01111" => MAXSECT1                   <=IOCTL_DOUT(3 downto 0);
+                    when "10000" => TRADR0(7 downto 0)         <=IOCTL_DOUT;                -- MZ_FDx_TA0
+                    when "10010" => TRADR0(15 downto 8)        <=IOCTL_DOUT;                -- MZ_FDx_TA1
+                    when "10100" => TRADR0(22 downto 16)       <=IOCTL_DOUT(6 downto 0);    -- MZ_FDx_TA2
+                    when "10001" => TRADR1(7 downto 0)         <=IOCTL_DOUT;
+                    when "10011" => TRADR1(15 downto 8)        <=IOCTL_DOUT;
+                    when "10101" => TRADR1(22 downto 16)       <=IOCTL_DOUT(6 downto 0);
+                    when "11000" => GAP30                      <=IOCTL_DOUT;                -- MZ_FDx_G30
+                    when "11001" => GAP31                      <=IOCTL_DOUT;
+                    when "11100" => GAP40(7 downto 0)          <=IOCTL_DOUT;                -- MZ_FDx_G40
+                    when "11110" => GAP40(15 downto 8)         <=IOCTL_DOUT;                -- MZ_FDx_G41
+                    when "11101" => GAP41(7 downto 0)          <=IOCTL_DOUT;
+                    when "11111" => GAP41(15 downto 8)         <=IOCTL_DOUT;
+                    when others  =>
+                end case;
+            end if;
+        end if;
+    end process;
+
+    CS         <= '1' when IOCTL_ADDR(15 downto 4)=REG_ADDR(15 downto 4) else '0';
+    RSEL       <= IOCTL_ADDR(3 downto 0)&HSEL;
+
+    IOCTL_DIN  <= "0000"&MF&D88&WP&DISK    when IOCTL_RD='1' and CS='1' and IOCTL_ADDR(3 downto 0)="0000" else    -- MZ_FDx_CTRL
+                  "000000"&DIREC&REG_ST    when IOCTL_RD='1' and CS='1' and IOCTL_ADDR(3 downto 0)="0010" else    -- MZ_FDx_STEP
+                  "00000000";
+    INTO       <= REG_ST;
+
+end RTL;
diff --git a/mz80b/fdunit.vhd b/mz80b/fdunit.vhd
new file mode 100644
index 0000000..057fe48
--- /dev/null
+++ b/mz80b/fdunit.vhd
@@ -0,0 +1,226 @@
+--
+-- fdunit.vhd
+--
+-- Floppy Disk Drive Unit Emulation module
+-- for MZ-80B/2000 on FPGA
+--
+-- Nibbles Lab. 2014
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity fdunit is
+    Port (
+        RST_n                : in  std_logic;                            -- Reset
+        CLK                  : in  std_logic;                            -- System Clock
+        -- Interrupt
+        INTO                 : out std_logic;                            -- Step Pulse interrupt
+        -- FD signals
+        FCLK                 : in  std_logic;
+        DS_n                 : in  std_logic_vector(4 downto 1);         -- Drive Select
+        HS                   : in  std_logic;                            -- Head Select
+        MOTOR_n              : in  std_logic;                            -- Motor On
+        INDEX_n              : out std_logic;                            -- Index Hole Detect
+        TRACK00              : out std_logic;                            -- Track 0
+        WPRT_n               : out std_logic;                            -- Write Protect
+        STEP_n               : in  std_logic;                            -- Head Step In/Out
+        DIREC                : in  std_logic;                            -- Head Step Direction
+        WG_n                 : in  std_logic;                            -- Write Gate
+        DTCLK                : out std_logic;                            -- Data Clock
+        FDI                  : in  std_logic_vector(7 downto 0);         -- Write Data
+        FDO                  : out std_logic_vector(7 downto 0);         -- Read Data
+        -- Buffer RAM I/F
+        BCS_n                : out std_logic;                            -- RAM Request
+        BADR                 : out std_logic_vector(22 downto 0);        -- RAM Address
+        BWR_n                : out std_logic;                            -- RAM Write Signal
+        BDI                  : in  std_logic_vector(7 downto 0);         -- Data Bus Input from RAM
+        BDO                  : out std_logic_vector(7 downto 0)          -- Data Bus Output to RAM
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                           -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);        -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                           -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                           -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);       -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0);       -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);       -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                            -- HPS Interrupt.
+    );
+end fdunit;
+
+architecture RTL of fdunit is
+--
+-- Floppy Signals
+--
+signal RDO0                  : std_logic_vector(7 downto 0);
+signal RDO1                  : std_logic_vector(7 downto 0);
+signal IDX_0                 : std_logic;
+signal IDX_1                 : std_logic;
+signal TRK00_0               : std_logic;
+signal TRK00_1               : std_logic;
+signal WPRT_0                : std_logic;
+signal WPRT_1                : std_logic;
+signal FDO0                  : std_logic_vector(7 downto 0);
+signal FDO1                  : std_logic_vector(7 downto 0);
+signal DTCLK0                : std_logic;
+signal DTCLK1                : std_logic;
+--
+-- Control
+--
+signal INT0                  : std_logic;
+signal INT1                  : std_logic;
+--
+-- Memory Access
+--
+signal BCS0_n                : std_logic;
+signal BCS1_n                : std_logic;
+signal BADR0                 : std_logic_vector(22 downto 0);
+signal BADR1                 : std_logic_vector(22 downto 0);
+signal BWR0_n                : std_logic;
+signal BWR1_n                : std_logic;
+signal BDO0                  : std_logic_vector(7 downto 0);
+signal BDO1                  : std_logic_vector(7 downto 0);
+--
+-- Component
+--
+component fd55b
+    generic
+    (
+        DS_SW                : std_logic_vector(4 downto 1) := "1111";
+        REG_ADDR             : std_logic_vector(15 downto 0) := "0000000000000000"
+    );
+    Port (
+        RST_n                : in  std_logic;                            -- Reset
+        CLK                  : in  std_logic;                            -- System Clock
+        -- Interrupt
+        INTO                 : out std_logic;                            -- Step Pulse interrupt
+        -- FD signals
+        FCLK                 : in std_logic;
+        DS_n                 : in std_logic_vector(4 downto 1);          -- Drive Select
+        HS                   : in std_logic;                             -- Head Select
+        MOTOR_n              : in std_logic;                             -- Motor On
+        INDEX_n              : out std_logic;                            -- Index Hole Detect
+        TRACK00              : out std_logic;                            -- Track 0
+        WPRT_n               : out std_logic;                            -- Write Protect
+        STEP_n               : in std_logic;                             -- Head Step In/Out
+        DIREC                : in std_logic;                             -- Head Step Direction
+        WG_n                 : in std_logic;                             -- Write Gate
+        DTCLK                : out std_logic;                            -- Data Clock
+        FDI                  : in std_logic_vector(7 downto 0);          -- Write Data
+        FDO                  : out std_logic_vector(7 downto 0);         -- Read Data
+        -- Buffer RAM I/F
+        BCS_n                : out std_logic;                            -- RAM Request
+        BADR                 : out std_logic_vector(22 downto 0);        -- RAM Address
+        BWR_n                : out std_logic;                            -- RAM Write Signal
+        BDI                  : in std_logic_vector(7 downto 0);          -- Data Bus Input from RAM
+        BDO                  : out std_logic_vector(7 downto 0)          -- Data Bus Output to RAM
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);         -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                             -- HPS Interrupt.
+    );
+end component;
+
+begin
+
+    FDD0 : fd55b generic map (
+        DS_SW                => "1110",
+        REG_ADDR             => X"0040"
+    )
+    Port map (
+        RST_n                => RST_n,                                   -- Reset
+        CLK                  => CLK,                                     -- System Clock
+        -- Interrupt
+        INTO                 => INT0,                                    -- Step Pulse interrupt
+        -- FD signals
+        FCLK                 => FCLK,
+        DS_n                 => DS_n,                                    -- Drive Select
+        HS                   => HS,                                      -- Head Select
+        MOTOR_n              => MOTOR_n,                                 -- Motor On
+        INDEX_n              => IDX_0,                                   -- Index Hole Detect
+        TRACK00              => TRK00_0,                                 -- Track 0
+        WPRT_n               => WPRT_0,                                  -- Write Protect
+        STEP_n               => STEP_n,                                  -- Head Step In/Out
+        DIREC                => DIREC,                                   -- Head Step Direction
+        WG_n                 => WG_n,                                    -- Write Gate
+        DTCLK                => DTCLK0,                                  -- Data Clock
+        FDI                  => FDI,                                     -- Write Data
+        FDO                  => FDO0,                                    -- Read Data
+        -- Buffer RAM I/F
+        BCS_n                => BCS0_n,                                  -- RAM Request
+        BADR                 => BADR0,                                   -- RAM Address
+        BWR_n                => BWR0_n,                                  -- RAM Write Signal
+        BDI                  => BDI,                                     -- Data Bus Input from RAM
+        BDO                  => BDO0                                     -- Data Bus Output to RAM
+        -- HPS Interface
+        IOCTL_DOWNLOAD       => IOCTL_DOWNLOAD,                          -- HPS Downloading to FPGA.
+        IOCTL_INDEX          => IOCTL_INDEX,                             -- Menu index used to upload file.
+        IOCTL_WR             => IOCTL_WR,                                -- HPS Write Enable to FPGA.
+        IOCTL_RD             => IOCTL_RD,                                -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           => IOCTL_ADDR,                              -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           => IOCTL_DOUT,                              -- HPS Data to be written into FPGA.
+        IOCTL_DIN            => IOCTL_DIN,                               -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      => IOCTL_INTERRUPT                          -- HPS Interrupt.
+    );
+
+    FDD1 : fd55b generic map (
+        DS_SW                => "1101",
+        REG_ADDR             => X"0050"
+    )
+    Port map (
+        RST_n                => RST_n,                                   -- Reset
+        CLK                  => CLK,                                     -- System Clock
+        -- Interrupt
+        INTO                 => INT1,                                    -- Step Pulse interrupt
+        -- FD signals
+        FCLK                 => FCLK,
+        DS_n                 => DS_n,                                    -- Drive Select
+        HS                   => HS,                                      -- Head Select
+        MOTOR_n              => MOTOR_n,                                 -- Motor On
+        INDEX_n              => IDX_1,                                   -- Index Hole Detect
+        TRACK00              => TRK00_1,                                 -- Track 0
+        WPRT_n               => WPRT_1,                                  -- Write Protect
+        STEP_n               => STEP_n,                                  -- Head Step In/Out
+        DIREC                => DIREC,                                   -- Head Step Direction
+        WG_n                 => WG_n,                                    -- Write Gate
+        DTCLK                => DTCLK1,                                  -- Data Clock
+        FDI                  => FDI,                                     -- Write Data
+        FDO                  => FDO1,                                    -- Read Data
+        -- Buffer RAM I/F
+        BCS_n                => BCS1_n,                                  -- RAM Request
+        BADR                 => BADR1,                                   -- RAM Address
+        BWR_n                => BWR1_n,                                  -- RAM Write Signal
+        BDI                  => BDI,                                     -- Data Bus Input from RAM
+        BDO                  => BDO1                                     -- Data Bus Output to RAM
+        -- HPS Interface
+        IOCTL_DOWNLOAD       => IOCTL_DOWNLOAD,                          -- HPS Downloading to FPGA.
+        IOCTL_INDEX          => IOCTL_INDEX,                             -- Menu index used to upload file.
+        IOCTL_WR             => IOCTL_WR,                                -- HPS Write Enable to FPGA.
+        IOCTL_RD             => IOCTL_RD,                                -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           => IOCTL_ADDR,                              -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           => IOCTL_DOUT,                              -- HPS Data to be written into FPGA.
+        IOCTL_DIN            => IOCTL_DIN,                               -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      => IOCTL_INTERRUPT                          -- HPS Interrupt.
+    );
+
+    INDEX_n  <= IDX_0 and IDX_1;
+    TRACK00  <= TRK00_0 and TRK00_1;
+    WPRT_n   <= WPRT_0 and WPRT_1;
+    FDO      <= FDO0 or FDO1;
+    DTCLK    <= DTCLK0 or DTCLK1;
+    BCS_n    <= BCS0_n and BCS1_n;
+    BADR     <= BADR0 or BADR1;
+    BWR_n    <= BWR0_n and BWR1_n;
+    BDO      <= BDO0 or BDO1;
+
+    RDO      <= RDO0 or RDO1;
+    INTO     <= INT0 or INT1;
+
+end RTL;
diff --git a/mz80b/mb8876.vhd b/mz80b/mb8876.vhd
new file mode 100644
index 0000000..4e22c1a
--- /dev/null
+++ b/mz80b/mb8876.vhd
@@ -0,0 +1,834 @@
+--
+-- mb8876.vhd
+--
+-- Floppy Disk Controller partiality compatible module
+-- for MZ-80B/2000 on FPGA
+--
+-- Nibbles Lab. 2014-2015
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity mb8876 is
+    Port (
+        -- CPU Signals
+        ZCLK                 : in  std_logic;
+        MR_n                 : in  std_logic;
+        A                    : in  std_logic_vector(1 downto 0);         -- CPU Address Bus
+        RE_n                 : in  std_logic;                            -- CPU Read Signal
+        WE_n                 : in  std_logic;                            -- CPU Write Signal
+        CS_n                 : in  std_logic;                            -- CPU Chip Select
+        DALI_n               : in  std_logic_vector(7 downto 0);         -- CPU Data Bus(in)
+        DALO_n               : out std_logic_vector(7 downto 0);         -- CPU Data Bus(out)
+--      DALI                 : in std_logic_vector(7 downto 0);          -- CPU Data Bus(in)
+--      DALO                 : out std_logic_vector(7 downto 0);         -- CPU Data Bus(out)
+        -- FD signals
+        DDEN_n               : in  std_logic;                            -- Double Density
+        IP_n                 : in  std_logic;                            -- Index Pulse
+        READY                : in  std_logic;                            -- Drive Ready
+        TR00_n               : in  std_logic;                            -- Track 0
+        WPRT_n               : in  std_logic;                            -- Write Protect
+        STEP                 : out std_logic;                            -- Head Step In/Out
+        DIRC                 : out std_logic;                            -- Head Step Direction
+        WG                   : out std_logic;                            -- Write Gate
+        DTCLK                : in  std_logic;                            -- Data Clock
+        FDI                  : in  std_logic_vector(7 downto 0);         -- Read Data
+        FDO                  : out std_logic_vector(7 downto 0)          -- Write Data
+    );
+end mb8876;
+
+architecture RTL of mb8876 is
+
+signal DALI                  : std_logic_vector(7 downto 0);             -- non-inverted Data bus(input)
+signal DALO                  : std_logic_vector(7 downto 0);             -- non-inverted Data bus(output)
+signal STS                   : std_logic_vector(7 downto 0);             -- Command Register(backup for status)
+signal TRACK                 : std_logic_vector(7 downto 0);             -- Track Counter
+signal SECTOR                : std_logic_vector(7 downto 0);             -- Sector Counter
+signal GAPVAL                : std_logic_vector(7 downto 0);             -- Gap's Value
+signal FDIR                  : std_logic_vector(7 downto 0);             -- Bulk Data(pre registered)
+signal FDR                   : std_logic_vector(7 downto 0);             -- Bulk Data
+signal WDATA                 : std_logic_vector(7 downto 0);             -- Write Data
+signal BCOUNT                : std_logic_vector(9 downto 0);              -- Byte Counter
+signal DELAY                 : std_logic_vector(16 downto 0);            -- Delay Counter
+signal DCSET                 : std_logic_vector(16 downto 0);            -- Next Delay Count Number
+signal PCOUNT                : std_logic_vector(4 downto 0);             -- Step Pulse Width
+signal BUSY                  : std_logic;                                -- Busy Flag
+signal DIRC0                 : std_logic;                                -- Step Direction(current)
+signal DIRR                  : std_logic;                                -- Step Direction(registered)
+signal E_SEEK                : std_logic;                                -- Seek Error
+signal E_RNF                 : std_logic;                                -- Record Not Found Error
+signal E_RLOST               : std_logic;                                -- Lost Data Error(read)
+signal E_WLOST               : std_logic;                                -- Lost Data Error(write)
+signal IDXBUF                : std_logic_vector(2 downto 0);             -- Index Pulse Detect
+signal DTBUF                 : std_logic_vector(2 downto 0);             -- Data Enable Detect
+signal FDEN                  : std_logic;                                -- Data Enable Detected
+signal IDXC                  : std_logic_vector(2 downto 0);             -- Index Pulse Counter
+signal RDRQ                  : std_logic;                                -- Read Data Request
+signal WDRQ                  : std_logic;                                -- Write Data Request
+signal MOVING                : std_logic;                                -- Head Stepping Flag
+signal RFND0                 : std_logic;                                -- Record Found Flag(process)
+signal RFND                  : std_logic;                                -- Record Found Flag(result)
+signal TFND                  : std_logic;                                -- Track Found Flag
+signal CMPT                  : std_logic;                                -- Track Compared Flag
+signal VFLAG                 : std_logic;                                -- Record Verify Flag
+signal UFLAG                 : std_logic;                                -- Track Number Update Flag
+signal CFLAG                 : std_logic;                                -- Side Compare Flag
+signal MFLAG                 : std_logic;                                -- Multi Record Flag
+signal SFLAG                 : std_logic;                                -- Side Flag
+--
+-- State Machine
+--
+signal CUR                   : std_logic_vector(5 downto 0);
+signal NXT                   : std_logic_vector(5 downto 0);
+constant IDLE                : std_logic_vector(5 downto 0) := "000000";
+constant REST                : std_logic_vector(5 downto 0) := "000001";
+--constant REST1             : std_logic_vector(5 downto 0) := "000010";
+--constant REST2             : std_logic_vector(5 downto 0) := "000011";
+constant SEEK0               : std_logic_vector(5 downto 0) := "000100";
+constant SEEK1               : std_logic_vector(5 downto 0) := "000101";
+constant SEEK2               : std_logic_vector(5 downto 0) := "000110";
+constant STEP0               : std_logic_vector(5 downto 0) := "000111";
+constant STEP1               : std_logic_vector(5 downto 0) := "001000";
+constant STEP2               : std_logic_vector(5 downto 0) := "001001";
+constant STIN0               : std_logic_vector(5 downto 0) := "001010";
+constant STIN1               : std_logic_vector(5 downto 0) := "001011";
+constant STIN2               : std_logic_vector(5 downto 0) := "001100";
+constant STOT0               : std_logic_vector(5 downto 0) := "001101";
+constant STOT1               : std_logic_vector(5 downto 0) := "001110";
+constant STOT2               : std_logic_vector(5 downto 0) := "001111";
+constant VTRK0               : std_logic_vector(5 downto 0) := "010000";
+constant VTRK1               : std_logic_vector(5 downto 0) := "010001";
+constant VTRK_ER             : std_logic_vector(5 downto 0) := "010010";
+constant RDAT0               : std_logic_vector(5 downto 0) := "010011";
+constant RDAT1               : std_logic_vector(5 downto 0) := "010100";
+constant RDAT2               : std_logic_vector(5 downto 0) := "010101";
+constant RDAT3               : std_logic_vector(5 downto 0) := "010110";
+constant RDAT4               : std_logic_vector(5 downto 0) := "010111";
+constant RDAT5               : std_logic_vector(5 downto 0) := "011000";
+constant WDAT0               : std_logic_vector(5 downto 0) := "011001";
+constant WDAT1               : std_logic_vector(5 downto 0) := "011010";
+constant WDAT2               : std_logic_vector(5 downto 0) := "011011";
+constant WDAT3               : std_logic_vector(5 downto 0) := "011100";
+constant WDAT4               : std_logic_vector(5 downto 0) := "011101";
+constant WDAT5               : std_logic_vector(5 downto 0) := "011110";
+constant RNF_ER              : std_logic_vector(5 downto 0) := "011111";
+constant RADR0               : std_logic_vector(5 downto 0) := "100000";
+constant RADR1               : std_logic_vector(5 downto 0) := "100001";
+constant RADR2               : std_logic_vector(5 downto 0) := "100010";
+constant RADR3               : std_logic_vector(5 downto 0) := "100011";
+constant CMDQ                : std_logic_vector(5 downto 0) := "100100";
+signal CUR2                  : std_logic_vector(4 downto 0);
+signal NXT2                  : std_logic_vector(4 downto 0);
+constant HUNT                : std_logic_vector(4 downto 0) := "00000";
+constant GAP1                : std_logic_vector(4 downto 0) := "00001";
+constant SYNC1               : std_logic_vector(4 downto 0) := "00010";
+constant ADM1                : std_logic_vector(4 downto 0) := "00011";
+constant ID_TRK              : std_logic_vector(4 downto 0) := "00100";
+constant ID_HEAD             : std_logic_vector(4 downto 0) := "00101";
+constant ID_SECT             : std_logic_vector(4 downto 0) := "00110";
+constant ID_FMT              : std_logic_vector(4 downto 0) := "00111";
+constant CRC1_1              : std_logic_vector(4 downto 0) := "01000";
+constant CRC1_2              : std_logic_vector(4 downto 0) := "01001";
+constant GAP2_2              : std_logic_vector(4 downto 0) := "01010";
+constant GAP2_1              : std_logic_vector(4 downto 0) := "01011";
+constant GAP2                : std_logic_vector(4 downto 0) := "01100";
+constant SYNC2               : std_logic_vector(4 downto 0) := "01101";
+constant ADM2                : std_logic_vector(4 downto 0) := "01110";
+constant DATA                : std_logic_vector(4 downto 0) := "01111";
+constant DATA_1              : std_logic_vector(4 downto 0) := "10000";
+constant DATA_2              : std_logic_vector(4 downto 0) := "10001";
+constant DATA_3              : std_logic_vector(4 downto 0) := "10010";
+constant CRC2                : std_logic_vector(4 downto 0) := "10011";
+
+begin
+
+    --
+    -- Step pulse and Seek wait
+    --
+    process( MR_n, ZCLK ) begin
+        if MR_n='0' then
+            DELAY   <= (others=>'0');
+            PCOUNT  <= (others=>'0');
+            MOVING  <= '0';
+            STEP    <= '0';
+        elsif ZCLK'event and ZCLK='1' then
+            if DELAY="00000000000000000" then
+                if CUR=SEEK1 or CUR=STEP1 or CUR=STIN1 or CUR=STOT1 then
+                    DELAY   <= DCSET;
+                    PCOUNT  <= (others=>'1');
+                    MOVING  <= '1';
+                else
+                    MOVING  <= '0';
+                end if;
+            else
+                DELAY       <= DELAY-'1';
+                if PCOUNT="00000" then
+                    STEP    <= '0';
+                else
+                    STEP    <= '1';
+                    PCOUNT  <= PCOUNT-'1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Select Step Rate
+    --
+    process( STS(1 downto 0) ) begin
+        case STS(1 downto 0) is                -- r0,r1
+            when "00"   => DCSET<=conv_std_logic_vector(24000, 17);        -- 6ms
+            when "10"   => DCSET<=conv_std_logic_vector(48000, 17);        -- 12ms
+            when "01"   => DCSET<=conv_std_logic_vector(80000, 17);        -- 20ms
+            when others => DCSET<=conv_std_logic_vector(120000, 17);    -- 30ms
+        end case;
+    end process;
+
+    --
+    -- FD Data Sync
+    --
+    process( MR_n, ZCLK ) begin
+--    process( MR_n, DTCLK ) begin
+        if MR_n='0' then
+            FDR<=(others=>'0');
+            CUR2<=HUNT;
+            BCOUNT<=(others=>'0');
+        elsif ZCLK'event and ZCLK='1' then
+--        elsif DTCLK'event and DTCLK='1' then
+--            FDIRR<=FDIR;
+            if FDEN='1' then
+                if MOVING='1' then
+                    CUR2<=HUNT;
+                else
+                    CUR2<=NXT2;
+                end if;
+                FDR<=FDI;
+                if CUR2=ID_FMT then
+                    case FDR(1 downto 0) is
+                        when "00" => BCOUNT<="0001111101";
+                        when "01" => BCOUNT<="0011111101";
+                        when "10" => BCOUNT<="0111111101";
+                        when others => BCOUNT<="1111111101";
+                    end case;
+                end if;
+                if CUR2=DATA then
+                    BCOUNT<=BCOUNT-'1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process( CUR2, IP_n, FDI, GAPVAL, BCOUNT ) begin
+        case CUR2 is
+            when HUNT =>
+                if IP_n='0' and FDI=GAPVAL then
+                    NXT2<=GAP1;
+                else
+                    NXT2<=HUNT;
+                end if;
+            when GAP1 =>
+                if FDI=X"00" then
+                    NXT2<=SYNC1;
+                else
+                    NXT2<=GAP1;
+                end if;
+            when SYNC1 =>
+                if FDI=X"FE" then
+                    NXT2<=ADM1;
+                else
+                    NXT2<=SYNC1;
+                end if;
+            when ADM1 =>
+                NXT2<=ID_TRK;
+            when ID_TRK =>
+                NXT2<=ID_HEAD;
+            when ID_HEAD =>
+                NXT2<=ID_SECT;
+            when ID_SECT =>
+                NXT2<=ID_FMT;
+            when ID_FMT =>
+                NXT2<=CRC1_1;
+            when CRC1_1 =>
+                NXT2<=CRC1_2;
+            when CRC1_2 =>
+                NXT2<=GAP2_2;
+            when GAP2_2 =>
+                NXT2<=GAP2_1;
+            when GAP2_1 =>
+                NXT2<=GAP2;
+            when GAP2 =>
+                if FDI=X"00" then
+                    NXT2<=SYNC2;
+                else
+                    NXT2<=GAP2;
+                end if;
+            when SYNC2 =>
+                if FDI=X"FB" then
+                    NXT2<=DATA;
+                else
+                    NXT2<=SYNC2;
+                end if;
+            when DATA =>
+                if BCOUNT="0000000000" then
+                    NXT2<=DATA_1;
+                else
+                    NXT2<=DATA;
+                end if;
+            when DATA_1 =>
+                    NXT2<=DATA_2;
+            when DATA_2 =>
+                    NXT2<=DATA_3;
+            when DATA_3 =>
+                    NXT2<=CRC2;
+            when CRC2 =>
+                if FDI=GAPVAL then
+                    NXT2<=GAP1;
+                else
+                    NXT2<=CRC2;
+                end if;
+            when others =>
+                NXT2<=HUNT;
+        end case;
+    end process;
+
+    GAPVAL<=X"4E" when DDEN_n='0' else X"FF";
+
+    --
+    -- FD data sample timing
+    --
+    process( MR_n, ZCLK ) begin
+        if MR_n='0' then
+            DTBUF<=(others=>'0');
+            FDEN<='0';
+        elsif ZCLK'event and ZCLK='1' then
+            DTBUF<=DTBUF(1 downto 0)&DTCLK;
+            if DTBUF(2 downto 1)="01" then
+                FDEN<='1';
+            else
+                FDEN<='0';
+            end if;
+        end if;
+    end process;
+
+    --
+    -- DRQ
+    --
+    process( MR_n, ZCLK ) begin
+        if MR_n='0' then
+            E_RLOST<='0';
+            E_WLOST<='0';
+            RDRQ<='0';
+            WDRQ<='0';
+        elsif ZCLK'event and ZCLK='1' then
+            -- Reset
+            if CUR=RDAT0 then
+                E_RLOST<='0';
+                RDRQ<='0';
+            end if;
+            if CUR=WDAT0 then
+                E_WLOST<='0';
+                WDRQ<='0';
+            end if;
+            if CUR=CMDQ then
+                if RDRQ='1' then
+                    E_RLOST<='1';
+                end if;
+                if WDRQ='1' then
+                    E_WLOST<='1';
+                end if;
+                RDRQ<='0';
+                WDRQ<='0';
+            end if;
+            -- DRQ on (Read)
+            if (CUR=RDAT3 and (CUR2=DATA or CUR2=DATA_1 or CUR2=DATA_2)) or (CUR=RADR2 and (CUR2=ADM1 or CUR2=ID_TRK or CUR2=ID_HEAD or CUR2=ID_SECT or CUR2=ID_FMT or CUR2=CRC1_1)) then
+                if FDEN='1' then
+                    RDRQ<='1';
+                    if RDRQ='1' then
+                        E_RLOST<='1';
+                    end if;
+                end if;
+            end if;
+            -- Write
+            if CUR=WDAT3 and (CUR2=DATA or CUR2=GAP2_1 or (CUR2=SYNC2 and FDI=X"FB")) then
+                if FDEN='1' then
+                    WDRQ<='1';
+                    if WDRQ='1' then
+                        E_WLOST<='1';
+                    end if;
+                end if;
+            end if;
+            -- DRQ off
+            if CS_n='0' and A="11" then
+                if WE_n='1' then
+                    -- Read
+                    RDRQ<='0';
+                else
+                    -- Write
+                    WDRQ<='0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Index Pulse Counter with ID check
+    --
+    process( MR_n, ZCLK ) begin
+        if MR_n='0' then
+            IDXC<=(others=>'0');
+            IDXBUF<=(others=>'1');
+            RFND0<='0';
+            RFND<='0';
+            TFND<='0';
+            CMPT<='0';
+        elsif ZCLK'event and ZCLK='1' then
+            -- stand by
+            if CUR=VTRK0 then
+                TFND<='0';
+                CMPT<='0';
+            end if;
+            -- count or reset
+            IDXBUF<=IDXBUF(1 downto 0)&IP_n;
+            if CUR=RDAT0 or CUR=WDAT0 then
+                IDXC<=(others=>'0');
+            else
+                if IDXBUF(2 downto 1)="10" then
+                    IDXC<=IDXC+'1';
+                end if;
+            end if;
+            -- find and compare ID
+            if FDEN='1' then
+                if CUR2=ID_TRK then
+                    if FDR=TRACK then
+                        RFND0<='1';
+                        TFND<='1';
+                    else
+                        RFND0<='0';
+                        TFND<='0';
+                    end if;
+                    CMPT<='1';
+                end if;
+                if CUR2=ID_HEAD then
+                    if CFLAG='1' then
+                        if FDR(0)/=SFLAG then
+                            RFND0<='0';
+                        end if;
+                    end if;
+                end if;
+                if CUR2=ID_SECT then
+                    if FDR=SECTOR then
+                        if RFND0='1' then
+                            IDXC<=(others=>'0');
+                        end if;
+                    else
+                        RFND0<='0';
+                    end if;
+                end if;
+                if CUR2=GAP2_2 then
+                    RFND<=RFND0;
+                end if;
+                if CUR2=CRC2 then
+                    RFND<='0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Compatibility
+    --
+    DALI<=not DALI_n;
+    DALO_n<=not DALO when CS_n='0' and RE_n='0' else (others=>'0');
+
+    --
+    -- CPU Interface and State movement
+    --
+    process( MR_n, ZCLK ) begin
+        if MR_n='0' then
+            STS<=(others=>'0');
+            E_SEEK<='0';
+            E_RNF<='0';
+            TRACK<=(others=>'0');
+            SECTOR<=X"01";
+            WDATA<=(others=>'0');
+            CUR<=IDLE;
+            DIRR<='0';
+            FDO<=(others=>'0');
+        elsif ZCLK'event and ZCLK='1' then
+            -- Registers
+            if CS_n='0' then
+                if WE_n='0' then
+                    case A is
+                        when "00" =>
+                            if DALI(7 downto 4)="1101" then
+                                if BUSY='0' then
+                                    STS<=DALI;
+                                end if;
+                            else
+                                STS<=DALI;
+                            end if;
+                        when "01" =>
+                            if BUSY='0' then
+                                TRACK<=DALI;
+                            end if;
+                        when "10" =>
+                            if BUSY='0' then
+                                SECTOR<=DALI;
+                            end if;
+                        when others =>
+                            if CUR=WDAT3 then
+                                FDO<=DALI;
+                            else
+                                WDATA<=DALI;
+                            end if;
+                    end case;
+                end if;
+            end if;
+
+            -- State Machine
+            if CS_n='0' and WE_n='0' and A="00" and DALI(7 downto 4)="1101" then
+                CUR<=CMDQ;    -- Force Interrupt
+            else
+                CUR<=NXT;
+            end if;
+            --
+            -- Save Step Direction
+            if CUR=SEEK1 or CUR=STEP1 or CUR=STIN1 or CUR=STOT1 then
+                DIRR<=DIRC0;
+            end if;
+            -- Seek Error
+            if CUR=SEEK0 or CUR=STEP0 or CUR=STIN0 or CUR=STOT0 then
+                E_SEEK<='0';
+            end if;
+            if CUR=VTRK_ER then
+                E_SEEK<='1';
+            end if;
+            -- Restore
+            if CUR=REST then
+                TRACK<=(others=>'1');
+                WDATA<=(others=>'0');
+            end if;
+            -- Step
+            if (UFLAG='1' and (CUR=STIN1 or (CUR=STEP1 and DIRC0='1'))) or (CUR=SEEK1 and DIRC0='1') then
+                TRACK<=TRACK+'1';
+            elsif    (UFLAG='1' and (CUR=STOT1 or (CUR=STEP1 and DIRC0='0'))) or (CUR=SEEK1 and DIRC0='0') then
+                TRACK<=TRACK-'1';
+            end if;
+            if (DIRC0='0' and (CUR=SEEK2 or CUR=STEP2)) or CUR=STOT2 then
+                if TR00_n='0' then
+                    TRACK<=(others=>'0');
+                end if;
+            end if;
+            -- Multi Read/Write
+            if CUR=RDAT5 or CUR=WDAT5 then
+                SECTOR<=SECTOR+'1';
+            end if;
+            -- Record Not Found Error
+            if CUR=RDAT0 or CUR=WDAT0 then
+                E_RNF<='0';
+            end if;
+            if CUR=RNF_ER then
+                E_RNF<='1';
+            end if;
+            -- Read Address function
+            if CUR=RADR2 and CUR2=ID_TRK then
+                SECTOR<=FDR;
+            end if;
+
+        end if;
+    end process;
+
+    VFLAG<=STS(2);
+    UFLAG<=STS(4);
+    CFLAG<=STS(1);
+    MFLAG<=STS(4);
+    SFLAG<=STS(3);
+
+    --
+    -- State Machine
+    --
+    process( CUR, CS_n, WE_n, A, DALI(7 downto 4), TR00_n, VFLAG, MOVING, TRACK, WDATA, CMPT, TFND, RFND, DIRR, IDXC, MFLAG, E_RLOST , E_WLOST ) begin
+        case CUR is
+            when IDLE =>
+                if CS_n='0' and WE_n='0' and A="00" then
+                    case DALI(7 downto 4) is
+                        when "0000" => NXT<=REST;
+                        when "0001" => NXT<=SEEK0;
+                        when "0010"|"0011" => NXT<=STEP0;
+                        when "0100"|"0101" => NXT<=STIN0;
+                        when "0110"|"0111" => NXT<=STOT0;
+                        when "1000"|"1001" => NXT<=RDAT0;
+                        when "1010"|"1011" => NXT<=WDAT0;
+                        when "1100" => NXT<=RADR0;
+                        when others => NXT<=IDLE;
+                    end case;
+                else
+                    NXT<=IDLE;
+                end if;
+
+            -- TYPE I / Restore command
+            when REST =>
+                NXT<=SEEK1;
+
+            -- TYPE I / Seek command
+            when SEEK0 =>
+                if TRACK=WDATA then
+                    if VFLAG='1' then
+                        NXT<=VTRK0;
+                    else
+                        NXT<=CMDQ;
+                    end if;
+                else
+                    NXT<=SEEK1;
+                end if;
+            when SEEK1 =>
+                NXT<=SEEK2;
+            when SEEK2 =>
+                if MOVING='0' then
+                    NXT<=SEEK0;
+                else
+                    NXT<=SEEK2;
+                end if;
+
+            -- TYPE I / Step command
+            when STEP0 =>
+                if DIRR='0' and TR00_n='0' then
+                    if VFLAG='1' then
+                        NXT<=VTRK0;
+                    else
+                        NXT<=CMDQ;
+                    end if;
+                else
+                    NXT<=STEP1;
+                end if;
+            when STEP1 =>
+                NXT<=STEP2;
+            when STEP2 =>
+                if MOVING='0' then
+                    if VFLAG='1' then
+                        NXT<=VTRK0;
+                    else
+                        NXT<=CMDQ;
+                    end if;
+                else
+                    NXT<=STEP2;
+                end if;
+
+            -- TYPE I / Step In command
+            when STIN0 =>
+                NXT<=STIN1;
+            when STIN1 =>
+                NXT<=STIN2;
+            when STIN2 =>
+                if MOVING='0' then
+                    if VFLAG='1' then
+                        NXT<=VTRK0;
+                    else
+                        NXT<=CMDQ;
+                    end if;
+                else
+                    NXT<=STIN2;
+                end if;
+
+            -- TYPE I / Step Out command
+            when STOT0 =>
+                if TR00_n='0' then
+                    if VFLAG='1' then
+                        NXT<=VTRK0;
+                    else
+                        NXT<=CMDQ;
+                    end if;
+                else
+                    NXT<=STOT1;
+                end if;
+            when STOT1 =>
+                NXT<=STOT2;
+            when STOT2 =>
+                if MOVING='0' then
+                    if VFLAG='1' then
+                        NXT<=VTRK0;
+                    else
+                        NXT<=CMDQ;
+                    end if;
+                else
+                    NXT<=STOT2;
+                end if;
+
+            -- Verify Track Number(TYPE I)
+            when VTRK0 =>
+                NXT<=VTRK1;
+            when VTRK1 =>
+                if CMPT='0' then
+                    NXT<=VTRK1;
+                else
+                    if TFND='0' then
+                        NXT<=VTRK_ER;
+                    else
+                        NXT<=CMDQ;
+                    end if;
+                end if;
+            when VTRK_ER =>
+                NXT<=CMDQ;
+
+            -- TYPE II / Read Data command
+            when RDAT0 =>
+                NXT<=RDAT1;
+            when RDAT1 =>
+                if CUR2=GAP1 then
+                    NXT<=RDAT2;
+                else
+                    NXT<=RDAT1;
+                end if;
+            when RDAT2 =>
+                if RFND='1' then
+                    NXT<=RDAT3;
+                else
+                    if IDXC="0110" then
+                        NXT<=RNF_ER;
+                    else
+                        NXT<=RDAT2;
+                    end if;
+                end if;
+            when RDAT3 =>
+                if E_RLOST='1' then
+                    NXT<=CMDQ;
+                else
+                    if CUR2=CRC2 then
+                        NXT<=RDAT4;
+                    else
+                        NXT<=RDAT3;
+                    end if;
+                end if;
+            when RDAT4 =>
+                if MFLAG='0' then
+                    NXT<=CMDQ;
+                else
+                    NXT<=RDAT5;
+                end if;
+            when RDAT5 =>
+                NXT<=RDAT0;
+
+            -- TYPE II / Write Data command
+            when WDAT0 =>
+                NXT<=WDAT1;
+            when WDAT1 =>
+                if CUR2=GAP1 then
+                    NXT<=WDAT2;
+                else
+                    NXT<=WDAT1;
+                end if;
+            when WDAT2 =>
+                if RFND='1' then
+                    NXT<=WDAT3;
+                else
+                    if IDXC="0110" then
+                        NXT<=RNF_ER;
+                    else
+                        NXT<=WDAT2;
+                    end if;
+                end if;
+            when WDAT3 =>
+                if E_WLOST='1' then
+                    NXT<=CMDQ;
+                else
+                    if CUR2=CRC2 then
+                        NXT<=WDAT4;
+                    else
+                        NXT<=WDAT3;
+                    end if;
+                end if;
+            when WDAT4 =>
+                if MFLAG='0' then
+                    NXT<=CMDQ;
+                else
+                    NXT<=WDAT5;
+                end if;
+            when WDAT5 =>
+                NXT<=WDAT0;
+
+            -- Record Not Found(TYPE II)
+            when RNF_ER =>
+                NXT<=CMDQ;
+
+            -- TYPE III / Read Address command
+            when RADR0 =>
+                NXT<=RADR1;
+            when RADR1 =>
+                if CUR2=GAP1 then
+                    NXT<=RADR2;
+                else
+                    NXT<=RADR1;
+                end if;
+            when RADR2 =>
+                if E_RLOST='1' then
+                    NXT<=CMDQ;
+                else
+--                    if CUR2=CRC1_2 then
+                    if CUR2=GAP2_2 then
+--                        NXT<=RADR3;
+                        NXT<=CMDQ;
+                    else
+                        NXT<=RADR2;
+                    end if;
+                end if;
+--            when RADR3 =>
+--                NXT<=RADR0;
+
+            when CMDQ =>
+                NXT<=IDLE;
+            when others =>
+                NXT<=IDLE;
+        end case;
+    end process;
+
+    --
+    -- State Action
+    --
+    -- Busy
+    BUSY<='0' when CUR=IDLE else '1';
+    -- Step Direction
+    process( CUR, TRACK, WDATA, DIRR ) begin
+        case CUR is
+            when SEEK0|SEEK1|SEEK2 =>
+                if TRACK>WDATA then
+                    DIRC0<='0';
+                elsif TRACK<WDATA then
+                    DIRC0<='1';
+                else
+                    DIRC0<=DIRR;
+                end if;
+            when STEP0|STEP1|STEP2 =>
+                DIRC0<=DIRR;
+            when STIN0|STIN1|STIN2 =>
+                DIRC0<='1';
+            when STOT0|STOT1|STOT2 =>
+                DIRC0<='0';
+            when others=>
+                DIRC0<=DIRR;
+        end case;
+    end process;
+    -- Write Gate
+    WG<='1' when CUR=WDAT3 and (CUR2=DATA or CUR2=DATA_1 or (CUR2=SYNC2 and (FDI=X"FB" or FDR=X"FB"))) else '0';
+
+    DALO<=    -- TYPE I Status
+            (not READY)&(not WPRT_n)&'1'&E_SEEK&'0'&(not TR00_n)&(not IP_n)&BUSY when A="00" and CS_n='0' and RE_n='0' and STS(7)='0' else
+                -- TYPE II Status
+            (not READY)&"00"&E_RNF&'0'&E_RLOST&RDRQ&BUSY                         when A="00" and CS_n='0' and RE_n='0' and (STS(7 downto 5)="100" or STS(7 downto 4)="1100") else
+            (not READY)&(not WPRT_n)&'0'&E_RNF&'0'&E_WLOST&WDRQ&BUSY             when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 5)="101" else
+                -- TYPE III Status
+        --    (not READY)&"00"&E_RNF&'0'&E_RLOST&RDRQ&BUSY                       when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 4)="1100" else
+                -- TYPE IV Status
+            (not READY)&(not WPRT_n)&"100"&(not TR00_n)&(not IP_n)&'0'           when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 4)="1101" else
+                -- Registers
+            TRACK                                                                when A="01" and CS_n='0' and RE_n='0' else
+            SECTOR                                                               when A="10" and CS_n='0' and RE_n='0' else
+            FDR                                                                  when A="11" and CS_n='0' and RE_n='0' and RDRQ='1' else
+            WDATA                                                                when A="11" and CS_n='0' and RE_n='0' else
+                -- Not Access
+            "00000000";
+    DIRC<=DIRC0;
+
+end RTL;
diff --git a/mz80b/mz1e05.vhd b/mz80b/mz1e05.vhd
new file mode 100644
index 0000000..dcfb520
--- /dev/null
+++ b/mz80b/mz1e05.vhd
@@ -0,0 +1,183 @@
+--
+-- mz1e05.vhd
+--
+-- Floppy Disk Interface Emulation module
+-- for MZ-80B/2000 on FPGA
+--
+-- Nibbles Lab. 2014
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity mz1e05 is
+    Port (
+        -- CPU Signals
+        ZRST_n               : in  std_logic;
+        ZCLK                 : in  std_logic;
+        ZADR                 : in  std_logic_vector(7 downto 0);         -- CPU Address Bus(lower)
+        ZRD_n                : in  std_logic;                            -- CPU Read Signal
+        ZWR_n                : in  std_logic;                            -- CPU Write Signal
+        ZIORQ_n              : in  std_logic;                            -- CPU I/O Request
+        ZDI                  : in  std_logic_vector(7 downto 0);         -- CPU Data Bus(in)
+        ZDO                  : out std_logic_vector(7 downto 0);         -- CPU Data Bus(out)
+        SCLK                 : in  std_logic;                            -- Slow Clock
+        -- FD signals
+        DS_n                 : out std_logic_vector(4 downto 1);         -- Drive Select
+        HS                   : out std_logic;                            -- Head Select
+        MOTOR_n              : out std_logic;                            -- Motor On
+        INDEX_n              : in  std_logic;                            -- Index Hole Detect
+        TRACK00              : in  std_logic;                            -- Track 0
+        WPRT_n               : in  std_logic;                            -- Write Protect
+        STEP_n               : out std_logic;                            -- Head Step In/Out
+        DIREC                : out std_logic;                            -- Head Step Direction
+        WGATE_n              : out std_logic;                            -- Write Gate
+        DTCLK                : in  std_logic;                            -- Data Clock
+        FDI                  : in  std_logic_vector(7 downto 0);         -- Read Data
+        FDO                  : out std_logic_vector(7 downto 0)          -- Write Data
+    );
+end mz1e05;
+
+architecture RTL of mz1e05 is
+--
+-- Signals
+--
+signal CSFDC_n               : std_logic;
+signal CSDC                  : std_logic;
+signal CSDD                  : std_logic;
+signal CSDE                  : std_logic;
+signal DDEN                  : std_logic;
+signal READY                 : std_logic;
+signal STEP                  : std_logic;
+signal DIRC                  : std_logic;
+signal WG                    : std_logic;
+signal RCOUNT                : std_logic_vector(12 downto 0);
+--
+-- Component
+--
+component mb8876
+    Port (
+        -- CPU Signals
+        ZCLK                 : in  std_logic;
+        MR_n                 : in  std_logic;
+        A                    : in  std_logic_vector(1 downto 0);         -- CPU Address Bus
+        RE_n                 : in  std_logic;                            -- CPU Read Signal
+        WE_n                 : in  std_logic;                            -- CPU Write Signal
+        CS_n                 : in  std_logic;                            -- CPU Chip Select
+        DALI_n               : in  std_logic_vector(7 downto 0);         -- CPU Data Bus(in)
+        DALO_n               : out std_logic_vector(7 downto 0);         -- CPU Data Bus(out)
+--      DALI                 : in std_logic_vector(7 downto 0);          -- CPU Data Bus(in)
+--      DALO                 : out std_logic_vector(7 downto 0);         -- CPU Data Bus(out)
+        -- FD signals
+        DDEN_n               : in  std_logic;                            -- Double Density
+        IP_n                 : in  std_logic;                            -- Index Pulse
+        READY                : in  std_logic;                            -- Drive Ready
+        TR00_n               : in  std_logic;                            -- Track 0
+        WPRT_n               : in  std_logic;                            -- Write Protect
+        STEP                 : out std_logic;                            -- Head Step In/Out
+        DIRC                 : out std_logic;                            -- Head Step Direction
+        WG                   : out std_logic;                            -- Write Gate
+        DTCLK                : in  std_logic;                            -- Data Clock
+        FDI                  : in  std_logic_vector(7 downto 0);         -- Read Data
+        FDO                  : out std_logic_vector(7 downto 0)          -- Write Data
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    FDC0 : mb8876 Port map(
+        -- CPU Signals
+        ZCLK                 => ZCLK,
+        MR_n                 => ZRST_n,
+        A                    => ZADR(1 downto 0),                        -- CPU Address Bus
+        RE_n                 => ZRD_n,                                   -- CPU Read Signal
+        WE_n                 => ZWR_n,                                   -- CPU Write Signal
+        CS_n                 => CSFDC_n,                                 -- CPU Chip Select
+        DALI_n               => ZDI,                                     -- CPU Data Bus(in)
+        DALO_n               => ZDO,                                     -- CPU Data Bus(out)
+--      DALI                 => ZDI,                                     -- CPU Data Bus(in)
+--      DALO                 => ZDO,                                     -- CPU Data Bus(out)
+        -- FD signals
+        DDEN_n               => DDEN,                                    -- Double Density
+        IP_n                 => INDEX_n,                                 -- Index Pulse
+        READY                => READY,                                   -- Drive Ready
+        TR00_n               => TRACK00,                                 -- Track 0
+        WPRT_n               => WPRT_n,                                  -- Write Protect
+        STEP                 => STEP,                                    -- Head Step In/Out
+        DIRC                 => DIRC,                                    -- Head Step Direction
+        WG                   => WG,                                      -- Write Gate
+        DTCLK                => DTCLK,                                   -- Data Clock
+        FDI                  => FDI,                                     -- Read Data
+        FDO                  => FDO                                      -- Write Data
+    );
+
+    --
+    -- Registers
+    --
+    process( ZRST_n, ZCLK ) begin
+        if ZRST_n='0' then
+            MOTOR_n<='1';
+            HS<='0';
+            DS_n<="1111";
+            DDEN<='0';
+        elsif ZCLK'event and ZCLK='0' then
+            if ZWR_n='0' then
+                if CSDC='1' then
+                    MOTOR_n<=not ZDI(7);
+                    case ZDI(2 downto 0) is
+                        when "100" => DS_n<="1110";
+                        when "101" => DS_n<="1101";
+                        when "110" => DS_n<="1011";
+                        when "111" => DS_n<="0111";
+                        when others => DS_n<="1111";
+                    end case;
+                end if;
+                if CSDD='1' then
+                    HS<=not ZDI(0);
+                end if;
+                if CSDE='1' then
+                    DDEN<=ZDI(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    CSFDC_n<='0' when ZIORQ_n='0' and ZADR(7 downto 2)="110110" else '1';
+    CSDC<='1' when ZIORQ_n='0' and ZADR=X"DC" else '0';
+    CSDD<='1' when ZIORQ_n='0' and ZADR=X"DD" else '0';
+    CSDE<='1' when ZIORQ_n='0' and ZADR=X"DE" else '0';
+
+    --
+    -- Ready Signal
+    --
+    process( ZRST_n, SCLK ) begin
+        if ZRST_n='0' then
+            RCOUNT<=(others=>'0');
+            READY<='0';
+        elsif SCLK'event and SCLK='0' then
+            if INDEX_n='0' then
+                RCOUNT<=(others=>'1');
+            else
+                if RCOUNT="0000000000000" then
+                    READY<='0';
+                else
+                    RCOUNT<=RCOUNT-'1';
+                    READY<='1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- FDC signals
+    --
+    STEP_n<=not STEP;
+    DIREC<=not DIRC;
+    WGATE_n<=not WG;
+
+end RTL;
diff --git a/mz80b/mz80b.vhd b/mz80b/mz80b.vhd
new file mode 100644
index 0000000..6eb05bc
--- /dev/null
+++ b/mz80b/mz80b.vhd
@@ -0,0 +1,767 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            mz80b.vhd
+-- Created:         August 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series Business Computer:
+--                                  Models MZ-80B, MZ-2000
+--
+--                  This module is the main (top level) container for the Business MZ Computer
+--                  Emulation.
+--
+--                  The design tries to work from top-down, where components which are common 
+--                  to the Business and Personal MZ series are at the top (ie. main memory,
+--                  ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
+--                  to the machine specific modules and components. Some components are common
+--                  by their nature (ie. 8255 PIO) but these are instantiated within the lower
+--                  tree branch as their design use is less generic.
+--
+--                  The tree is as follows;-
+--
+--                                      (emu) sharpmz.vhd (mz80c)	->	mz80c.vhd
+--                                      |
+--                                      |
+--                                      |                                         -> cmt.vhd                   (common)
+--                                      |                                         -> keymatrix.vhd             (common)
+--                                      |                                         -> pll.v                     (common)
+--                                      |                                         -> clkgen.vhd                (common)
+--                                      |                                         -> T80                       (common)
+--                                      |                                         -> i8255                     (common)
+--                  sys_top.sv (emu) ->	(emu) sharpmz.vhd (hps_io) -> hps_io.sv
+--                                      |                                         -> i8254                     (common)
+--                                      |                                         -> dpram.vhd                 (common)
+--                                      |                                         -> dprom.vhd                 (common)
+--                                      |                                         -> mctrl.vhd                 (common)
+--                                      |                                         -> video.vhd                 (common)
+--                                      |
+--                                      |
+--                                      (emu) sharpmz.vhd (mz80b)	->	mz80b.vhd
+--
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         August 2018   - Initial module created.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity mz80b is
+    PORT (
+          -- Clocks
+          CLKBUS             : in  std_logic_vector(CLKBUS_WIDTH);    -- Clock signals created by clkgen module.
+
+          -- Resets.
+          COLD_RESET         : in  std_logic;
+          SYSTEM_RESET       : in  std_logic;
+          
+          -- Z80 CPU
+          T80_RST_n          : in  std_logic;
+          T80_WAIT_n         : out std_logic;
+          T80_INT_n          : out std_logic;
+          T80_NMI_n          : out std_logic;
+          T80_BUSRQ_n        : out std_logic;
+          T80_M1_n           : in  std_logic;
+          T80_MREQ_n         : in  std_logic;
+          T80_IORQ_n         : in  std_logic;
+          T80_RD_n           : in  std_logic;
+          T80_WR_n           : in  std_logic;
+          T80_RFSH_n         : in  std_logic;
+          T80_HALT_n         : in  std_logic;
+          T80_BUSAK_n        : in  std_logic;
+          T80_A16            : in  std_logic_vector(15 downto 0);
+          T80_DI             : out std_logic_vector(7 downto 0);
+          T80_DO             : in  std_logic_vector(7 downto 0);
+
+          -- Chip selects to common resources.
+          CS_ROM_n           : out std_logic;                            -- ROM Select
+          CS_RAM_n           : out std_logic;                            -- RAM Select
+          CS_VRAM_n          : out std_logic;                            -- VRAM Select
+          CS_GRAM_n          : out std_logic;                            -- Colour Graphics GRAM Select
+          CS_GRAM_80B_n      : out std_logic;                            -- MZ80B GRAM Option Select
+          CS_IO_GFB_n        : out std_logic;                            -- Graphics Framebuffer IO Select range
+          CS_IO_G_n          : out std_logic;                            -- Graphics Options IO Select range
+          CS_SWP_MEMBANK_n   : out std_logic;                            -- Move lower 32K into upper block.
+
+          -- Audio.
+          AUDIO_L            : out std_logic;
+          AUDIO_R            : out std_logic;
+
+          -- Different operations modes.
+          CONFIG             : in  std_logic_vector(CONFIG_WIDTH);
+
+          -- I/O                                                         -- I/O down to the core.
+          KEYB_SCAN          : out std_logic_vector(3 downto 0);         -- Keyboard scan lines out.
+          KEYB_DATA          : in  std_logic_vector(7 downto 0);         -- Keyboard scan data in.
+          KEYB_STALL         : out std_logic;                            -- Keyboard Stall out.
+          KEYB_BREAKDETECT   : in  std_logic;                            -- Keyboard break detect.
+
+          -- Cassette magnetic tape signals.
+          CMT_BUS_OUT        : in  std_logic_vector(CMT_BUS_OUT_WIDTH);
+          CMT_BUS_IN         : out std_logic_vector(CMT_BUS_IN_WIDTH);
+
+          -- Video signals
+          VGATE_n            : out std_logic;                            -- Video Gate enable.
+          INVERSE_n          : out std_logic;                            -- Invert video output.
+          CONFIG_CHAR80      : out std_logic;                            -- 40 Char = 0, 80 Char = 1 select.
+          HBLANK             : in  std_logic;                            -- Horizontal Blanking Signal
+          VBLANK             : in  std_logic;                            -- Vertical Blanking Signal
+
+          -- HPS Interface
+          IOCTL_DOWNLOAD     : in  std_logic;                            -- HPS Downloading to FPGA.
+          IOCTL_UPLOAD       : in  std_logic;                            -- HPS Uploading from FPGA.
+          IOCTL_CLK          : in  std_logic;                            -- HPS I/O Clock.
+          IOCTL_WR           : in  std_logic;                            -- HPS Write Enable to FPGA.
+          IOCTL_RD           : in  std_logic;                            -- HPS Read Enable from FPGA.
+          IOCTL_ADDR         : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+          IOCTL_DOUT         : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+          IOCTL_DIN          : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+          -- Debug Status Leds
+          DEBUG_STATUS_LEDS  : out std_logic_vector(111 downto 0)        -- 112 leds to display status.
+    );
+end mz80b;
+
+architecture rtl of mz80b is
+
+--
+-- Decodes, misc
+--
+signal BOOTSTRAP_n           :     std_logic;                            -- Memory select, Low = ROM 0000 - 07FF, High = RAM 0000 - 7FFF
+signal SEL_VRAM_ENABLE       :     std_logic;                            -- Enable VRAM/GRAM = 1.
+signal SEL_VRAM_HIGHADDR     :     std_logic;                            -- Select VRAM as High (D000-FFFF) address, Low (5000-7FFF)
+signal BST_n                 :     std_logic; 
+signal NST                   :     std_logic; 
+signal MZ_GRAM_ENABLE        :     std_logic;
+signal CS_VRAM_ni            :     std_logic;
+signal CS_IO_8255_n          :     std_logic;
+signal CS_IO_8254_n          :     std_logic;
+signal CS_IO_8254_RST_CLK_n  :     std_logic;
+signal CS_IO_Z80PIO_n        :     std_logic;
+signal CS_GRAM_ni            :     std_logic;
+signal CS_GRAM_80B_ni        :     std_logic;
+signal CS_IO_GRAMENABLE_n    :     std_logic;
+signal CS_IO_GRAMDISABLE_n   :     std_logic;
+signal CS_IO_GFB_ni          :     std_logic;
+signal CS_IO_G_ni            :     std_logic;
+signal CS_ROM_ni             :     std_logic;
+signal CS_RAM_ni             :     std_logic;
+signal T80_INT_ni            :     std_logic;
+signal IRQ_CMT               :     std_logic;
+signal IRQ_FDD               :     std_logic;
+--
+-- PPI
+--
+signal PPI_DO                :     std_logic_vector(7 downto 0);
+signal i8255_PA_O            :     std_logic_vector(7 downto 0);
+signal i8255_PA_OE_n         :     std_logic_vector(7 downto 0);
+signal i8255_PB_I            :     std_logic_vector(7 downto 0);
+signal i8255_PB_O            :     std_logic_vector(7 downto 0);
+signal i8255_PC_O            :     std_logic_vector(7 downto 0);
+signal i8255_PC_OE_n         :     std_logic_vector(7 downto 0);
+--
+-- PIT
+--
+signal PIT_DO                :     std_logic_vector(7 downto 0);
+--
+-- PIO
+--
+signal PIO_DO                :     std_logic_vector(7 downto 0);
+signal Z80PIO_INT_n          :     std_logic;
+signal Z80PIO_PA             :     std_logic_vector(7 downto 0);
+signal Z80PIO_PB             :     std_logic_vector(7 downto 0);
+--
+-- Clocks
+--
+signal CASCADE01             :     std_logic;
+signal CASCADE12             :     std_logic;
+--
+-- Video
+--
+signal HBLANKi               :     std_logic;
+signal VBLANKi               :     std_logic;
+signal HSYNC_ni              :     std_logic;
+signal VSYNC_ni              :     std_logic;
+signal Ri                    :     std_logic;
+signal Gi                    :     std_logic;
+signal Bi                    :     std_logic;
+signal VGATE_ni              :     std_logic;                               -- Video Outpu Enable
+signal VRAM_DO               :     std_logic_vector(7 downto 0);
+--
+-- Keyboard.
+--
+signal LED_RVS               :     std_logic;
+signal LED_GRPH              :     std_logic;
+signal LED_SHIFT_LOCK        :     std_logic;
+--
+-- Audio
+--
+signal SOUND                 :     std_logic;
+--
+-- FDD,FDC
+--
+signal DOFDC                 :     std_logic_vector(7 downto 0);
+signal DS                    :     std_logic_vector(3 downto 0);
+signal HS                    :     std_logic;
+signal MOTOR_n               :     std_logic;
+signal INDEX_n               :     std_logic;
+signal TRACK00_n             :     std_logic;
+signal WPRT_n                :     std_logic;
+signal STEP_n                :     std_logic;
+signal DIREC                 :     std_logic;
+signal FDO                   :     std_logic_vector(7 downto 0);
+signal FDI                   :     std_logic_vector(7 downto 0);
+signal WGATE_n               :     std_logic;
+signal DTCLK                 :     std_logic;
+--
+-- Debug
+--
+signal PULSECPU              :     std_logic; 
+
+
+
+--
+-- Components
+--
+component i8255
+  port (
+      RESET                : in    std_logic;
+      CLK                  : in    std_logic;
+      ENA                  : in    std_logic; -- (CPU) clk enable
+      ADDR                 : in    std_logic_vector(1 downto 0); -- A1-A0
+      DI                   : in    std_logic_vector(7 downto 0); -- D7-D0
+      DO                   : out   std_logic_vector(7 downto 0);
+      CS_n                 : in    std_logic;
+      RD_n                 : in    std_logic;
+      WR_n                 : in    std_logic;
+  
+      PA_I                 : in    std_logic_vector(7 downto 0);
+      PA_O                 : out   std_logic_vector(7 downto 0);
+      PA_O_OE_n            : out   std_logic_vector(7 downto 0);
+  
+      PB_I                 : in    std_logic_vector(7 downto 0);
+      PB_O                 : out   std_logic_vector(7 downto 0);
+      PB_O_OE_n            : out   std_logic_vector(7 downto 0);
+
+      PC_I                 : in    std_logic_vector(7 downto 0);
+      PC_O                 : out   std_logic_vector(7 downto 0);
+      PC_O_OE_n            : out   std_logic_vector(7 downto 0)
+  );
+end component;
+
+component i8254
+ Port (
+        RST                  : in  std_logic;
+        CLK                  : in  std_logic;
+        ENA                  : in  std_logic;
+        A                    : in  std_logic_vector(1 downto 0);
+        DI                   : in  std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        CS_n                 : in  std_logic;
+        WR_n                 : in  std_logic;
+        RD_n                 : in  std_logic;
+        CLK0                 : in  std_logic;
+        GATE0                : in  std_logic;
+        OUT0                 : out std_logic;
+        CLK1                 : in  std_logic;
+        GATE1                : in  std_logic;
+        OUT1                 : out std_logic;
+        CLK2                 : in  std_logic;
+        GATE2                : in  std_logic;
+        OUT2                 : out std_logic
+  );
+end component;
+
+component z8420
+    Port (
+        -- System
+        RST_n                : in  std_logic;                            -- Only Power On Reset
+        -- Z80 Bus Signals
+        CLK                  : in  std_logic;
+        ENA                  : in  std_logic;
+        BASEL                : in  std_logic;
+        CDSEL                : in  std_logic;
+        CE                   : in  std_logic;
+        RD_n                 : in  std_logic;
+        WR_n                 : in  std_logic;
+        IORQ_n               : in  std_logic;
+        M1_n                 : in  std_logic;
+        DI                   : in  std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        IEI                  : in  std_logic;
+        IEO                  : out std_logic;
+        INT_n                : out std_logic;
+        -- Port
+        A                    : out std_logic_vector(7 downto 0);
+        B                    : in std_logic_vector(7 downto 0)
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    -- 8255 Used for Tape Control and interfacing and system boot control.
+    --
+    PPI0B : i8255
+        port map (
+            RESET            => SYSTEM_RESET,
+            CLK              => CLKBUS(CKMASTER),
+            ENA              => CLKBUS(CKENCPU),
+            ADDR             => T80_A16(1 downto 0), 
+            DI               => T80_DO,
+            DO               => PPI_DO,
+            CS_n             => CS_IO_8255_n,
+            RD_n             => T80_RD_n,
+            WR_n             => T80_WR_n, 
+  
+            PA_I             => i8255_PA_O,
+            PA_O             => i8255_PA_O,
+            PA_O_OE_n        => i8255_PA_OE_n,
+  
+            PB_I             => i8255_PB_I, 
+            PB_O             => open, 
+            PB_O_OE_n        => open,
+    
+            PC_I             => i8255_PC_O,
+            PC_O             => i8255_PC_O,
+            PC_O_OE_n        => i8255_PC_OE_n
+     );
+
+    -- 8253 Timer used for the real time clock.
+    --
+    PIT0 : i8254
+      port map (
+            RST              => SYSTEM_RESET,
+            CLK              => CLKBUS(CKMASTER),
+            ENA              => CLKBUS(CKENCPU),
+            A                => T80_A16(1 downto 0),
+            DI               => T80_DO,
+            DO               => PIT_DO,
+            CS_n             => CS_IO_8254_n,
+            WR_n             => T80_WR_n,
+            RD_n             => T80_RD_n,
+            CLK0             => CLKBUS(CKRTC),
+            GATE0            => CS_IO_8254_RST_CLK_n,
+            OUT0             => CASCADE01,
+            CLK1             => CASCADE01,
+            GATE1            => CS_IO_8254_RST_CLK_n,
+            OUT1             => CASCADE12,
+            CLK2             => CASCADE12,
+            GATE2            => '1',
+            OUT2             => open
+      );
+
+    -- Z80 PIO used for keyboard, RAM and Video control.
+    --
+    PIO0 : z8420
+        port map (
+            -- System
+            RST_n            => T80_RST_n,                               -- Only Power On Reset
+            -- Z80 Bus Signals
+            CLK              => CLKBUS(CKMASTER),
+            ENA              => CLKBUS(CKENCPU),
+            BASEL            => T80_A16(1),
+            CDSEL            => T80_A16(0),
+            CE               => CS_IO_Z80PIO_n,
+            RD_n             => T80_RD_n,
+            WR_n             => T80_WR_n,
+            IORQ_n           => T80_IORQ_n,
+            M1_n             => T80_M1_n and T80_RST_n,
+            DI               => T80_DO,
+            DO               => PIO_DO,
+            IEI              => '1',
+            IEO              => open,
+            INT_n            => Z80PIO_INT_n,
+
+            A                => Z80PIO_PA,
+            B                => Z80PIO_PB
+        );
+
+    -- A1 clocked by C5, if A1 = L when C5 (SEEK) pulses high, then tape rewinds on activation of A0. If A1 is high, then 
+    -- tape will fast forward. A0, when pulsed high, activates the motor to go forward/backward.
+    -- A2 pulsed high activates the play motor.which cancels a FF/REW event.
+    -- A3 when High, stops the Play/FF/REW events.
+    -- B5 when high indicates tape drive present and ready.
+    -- C4 when Low, ejects the tape.
+    -- C6 when Low enables record, otherwise whe High enables play.
+    -- C7 is the data to write to tape.
+    -- B6 is the data read from tape.
+    -- BW ehn Low blocks recording.
+
+
+    -- PPI Port A - Output connections.
+    --
+    LED_RVS                  <= i8255_PA_O(7) when i8255_PA_OE_n(7) = '0'
+                                else '0';
+    LED_GRPH                 <= i8255_PA_O(6) when i8255_PA_OE_n(6) = '0'
+                                else '0';
+    LED_SHIFT_LOCK           <= i8255_PA_O(5) when i8255_PA_OE_n(5) = '0'
+                                else '0';
+    INVERSE_n                <= i8255_PA_O(4) when i8255_PA_OE_n(4) = '0'
+                                else '1';
+    CMT_BUS_IN(STOP)         <= i8255_PA_O(3) when i8255_PA_OE_n(3) = '0'
+                                else '0';
+    CMT_BUS_IN(PLAY)         <= i8255_PA_O(2) when i8255_PA_OE_n(2) = '0'
+                                else '0';
+    CMT_BUS_IN(DIRECTION)    <= i8255_PA_O(1) when i8255_PA_OE_n(1) = '0'
+                                else '0';
+    CMT_BUS_IN(REEL_MOTOR)   <= i8255_PA_O(0) when i8255_PA_OE_n(0) = '0'
+                                else '0';
+
+
+    -- PPI Port B - Input connections.
+    --
+    i8255_PB_I(7)            <= KEYB_BREAKDETECT;
+    i8255_PB_I(6)            <= CMT_BUS_OUT(WRITEBIT);                   -- Tape is loaded in deck when L (0).
+    i8255_PB_I(5)            <= CMT_BUS_OUT(TAPEREADY);                  -- Tape is loaded in deck when L (0).
+    i8255_PB_I(4)            <= CMT_BUS_OUT(WRITEREADY);                 -- Prohibit Write when L (0).
+    i8255_PB_I(3 downto 1)   <= (others => '1');
+    i8255_PB_I(0)            <= VBLANK;
+    
+
+    -- PPI Port C - Output connections. Feed output to input to be able to read latched value.
+    --
+    CMT_BUS_IN(READBIT)      <= i8255_PC_O(7) when i8255_PC_OE_n(7) = '0'
+                                else '0';
+    CMT_BUS_IN(WRITEENABLE)  <= i8255_PC_O(6) when i8255_PC_OE_n(6) = '0'
+                                else '0';
+    CMT_BUS_IN(SEEK)         <= i8255_PC_O(5) when i8255_PC_OE_n(5) = '0'
+                                else '0';
+    CMT_BUS_IN(EJECT)        <= i8255_PC_O(4) when i8255_PC_OE_n(4) = '0'
+                                else '0';
+    BST_n                    <= i8255_PC_O(3) when i8255_PC_OE_n(3) = '0'
+                                else '1';
+    SOUND                    <= i8255_PC_O(2) when i8255_PC_OE_n(2) = '0'
+                                else '0';
+    NST                      <= i8255_PC_O(1) when i8255_PC_OE_n(1) = '0'
+                                else '0';
+    VGATE_ni                 <= i8255_PC_O(0) when i8255_PC_OE_n(0) = '0'
+                                else '1';
+
+    -- Z80 PIO Port A - Output.
+    --
+    SEL_VRAM_ENABLE          <= Z80PIO_PA(7);
+    SEL_VRAM_HIGHADDR        <= Z80PIO_PA(6);
+    CONFIG_CHAR80            <= Z80PIO_PA(5);
+    KEYB_STALL               <= Z80PIO_PA(4);
+    KEYB_SCAN                <= Z80PIO_PA(3 downto 0);
+
+    -- Z80 PIO Port B - Input - Keyboard data.
+    --
+    Z80PIO_PB                <= KEYB_DATA;
+
+    -- Parent signals onto local wires.
+    --
+    T80_BUSRQ_n              <= '1';
+    T80_NMI_n                <= '1';
+    T80_WAIT_n               <= '1';
+
+    --
+    -- MZ-80B - Interrupts from the Z80PIO or external sources.
+    T80_INT_ni               <= '0'        when Z80PIO_INT_n = '0'
+                                else '1';
+    T80_INT_n                <= T80_INT_ni;
+
+    --
+    -- Data Bus Multiplexing, plex all the output devices onto the Z80 Data Input according to the CS.
+    --
+    T80_DI                   <= PPI_DO     when CS_IO_8255_n  ='0' and T80_RD_n = '0'                          -- Read from 8255
+                                else 
+                                PIT_DO     when CS_IO_8254_n  ='0' and T80_RD_n = '0'                          -- Read from 8254
+                                else 
+                                PIO_DO     when CS_IO_Z80PIO_n='0' and T80_RD_n = '0'                          -- Read from Z80PIO
+                                else
+                                (others=>'1');
+
+    -- HPS Bus Multiplexing for reads.
+    IOCTL_DIN                <= "00000000111111111100110010101010";                                            -- Test pattern.
+
+    --
+    -- Chip Select map.
+    --
+    -- 0000 - FFFF             : MZ80B/2000    unless portion paged out by below selects.
+    -- 5000 - 5FFF             : MZ80B         = Alternate VRAM location
+    -- 6000 - 7FFF             : MZ80B         = Alternate GRAM location
+    -- C000 - FFFF             : MZ2000        = GRAM
+    -- D000 - DFFF             : MZ80B/2000    = VRAM
+    -- E000 - FFFF             : MZ80B         = GRAM
+    --
+    --
+    -- Video RAM Select.
+    -- 5000 - 5FFF
+    -- D000 - DFFF
+    CS_VRAM_ni          <= -- D000 - DFFF
+                           '0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1'  and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "1101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
+                               else
+                           -- 5000 - 5FFF
+                           '0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1'  and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "0101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
+                               else
+                           -- D000 - DFFF
+                           '0' when CONFIG(MZ2000) = '1'                and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "1101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
+                               else '1';
+
+    -- MZ80B/2000 Graphics RAM Select.
+    --
+    CS_GRAM_80B_ni      <= -- E000 - FFFF
+                           '0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1'  and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 13) = "111"  and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
+                           else
+                           -- 6000 - 7FFF
+                           '0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1'  and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 13) = "011"  and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
+                           else
+                           -- C000 - FFFF
+                           '0' when CONFIG(MZ2000) = '1'                and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 14) = "11"   and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
+                           else '1';
+
+    -- Colour frame buffer.
+    -- C000 - FFFF
+    --
+    CS_GRAM_ni          <= '0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1'  and MZ_GRAM_ENABLE = '1'  and T80_A16(15 downto 14) = "11"   and T80_MREQ_n='0'
+                           else '1';
+
+
+    -- Boot ROM. Enabled only at startup when
+    --
+    -- 0000 -> 07FF when in IPL mode.
+    CS_ROM_ni           <= '0' when BOOTSTRAP_n = '0' and T80_A16(15 downto 11) = "00000" and T80_MREQ_n = '0'
+                           else '1';
+    --
+    CS_RAM_ni           <= '0' when BOOTSTRAP_n = '0' and T80_A16(15) = '1' and CS_VRAM_ni = '1' and CS_GRAM_ni = '1' and CS_GRAM_80B_ni = '1' and T80_MREQ_n = '0'
+                           else
+                           '0' when BOOTSTRAP_n = '1' and CS_VRAM_ni = '1' and CS_GRAM_ni = '1' and CS_GRAM_80B_ni = '1' and T80_MREQ_n = '0'
+                           else '1';
+
+    --
+    -- IO Select Map.
+    -- E0 - EF are used by the MZ80B/2000 to perform memory switching and graphics control.
+    -- F0-F3 write is used to set the gates of the 8254
+    -- F4-F7 is used to control the graphics options.
+    -- F8 is used to write the MSB of the Rom Expansion
+    -- F9 is used to write the LSB of the Rom Expansion and to read the data byte back.
+    --
+    -- IO Range for Graphics enhancements is set by the MCTRL DISPLAY2{7:3] register.
+    -- x[0|8],<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+    -- x[1|9],<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
+    -- x[2|A],<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
+    -- x[3|B],<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
+    -- x[4|C]       switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. This overrides all MZ700 page switching functions.
+    -- x[5|D]       switches out the graphics ram and returns to previous state.
+    --
+    CS_IO_8255_n        <= '0'  when T80_IORQ_n   = '0' and T80_A16(7 downto 2) = "111000"                               -- IO E0-E3 = 8255
+                           else '1';
+    CS_IO_8254_n        <= '0'  when T80_IORQ_n   = '0' and T80_A16(7 downto 2) = "111001"                               -- IO E4-E7 = 8254
+                           else '1';
+    CS_IO_Z80PIO_n      <= '0'  when T80_IORQ_n   = '0' and T80_A16(7 downto 2) = "111010"                               -- IO E8-EB = Z80PIO
+                           else '1';
+    CS_IO_8254_RST_CLK_n<= '0'  when T80_IORQ_n   = '0' and T80_A16(7 downto 2) = "111100" and T80_WR_n = '0'            -- IO F0-F3 = 8254 Clock reset.
+                           else '1';
+    CS_IO_G_ni          <= '0'  when T80_IORQ_n   = '0' and T80_A16(7 downto 2) = "111101" and T80_WR_n = '0'            -- IO Range for Graphics framebuffer register controlled by mctrl register.
+                           else '1';
+    CS_IO_GFB_ni        <= '0'  when T80_IORQ_n   = '0' and T80_A16(7 downto 3) = CONFIG(GRAMIOADDR) and T80_WR_n = '0'  -- IO Range for Graphics framebuffer register controlled by mctrl register.
+                           else '1';
+    CS_IO_GRAMENABLE_n  <= '0'  when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "100"                                  -- IO Addr base+4 sets C000 -> FFFF map to Graphics RAM.
+                           else '1';
+    CS_IO_GRAMDISABLE_n <= '0'  when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "101"                                  -- IO Addr base+5 sets C000 -> FFFF revert to previous mode.
+                           else '1';
+
+    -- Send signals to module interface.
+    --
+    CS_ROM_n            <= CS_ROM_ni;
+    CS_RAM_n            <= CS_RAM_ni;
+    CS_VRAM_n           <= CS_VRAM_ni;
+    CS_GRAM_n           <= CS_GRAM_ni;
+    CS_GRAM_80B_n       <= CS_GRAM_80B_ni;
+    CS_IO_GFB_n         <= CS_IO_GFB_ni;
+    CS_IO_G_n           <= CS_IO_G_ni;
+    CS_SWP_MEMBANK_n    <= BOOTSTRAP_n;
+    VGATE_n             <= VGATE_ni;
+
+    -- On initial reset, BOOTSTRAP_n is set active, a reset setup and hold takes place, then the processor is set running with the
+    -- IPL monitor rom at 0000-07ff. 
+    -- If NST goes High (due to the IPL setting it), then a flip flop is clocked setting BOOTSTRAP_n to inactive which places RAM
+    -- into the normal running state at 0000-7fff and the IPL monitor rom is disabled.
+    -- BOOT_RESET (external input) or BST_n when Low sets the BOOTSTRAP_n so that IPL mode is entered and the IPL monitor rom
+    -- is active at 0000. 
+    --
+    process( COLD_RESET, CONFIG(BOOT_RESET), BST_n, CLKBUS(CKMASTER), NST )
+    begin
+        -- A cold reset sets up the initial state, further resets just reset variables as needed.
+        --
+        if COLD_RESET = '1' then
+            BOOTSTRAP_n  <= '0'; 
+
+        elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
+            
+            if CLKBUS(CKENCPU) = '1' then
+
+                if CONFIG(BOOT_RESET) = '1' or BST_n = '0' then
+                    -- Only a boot reset or BST_n can set the BOOTSTRAP signal. A system reset just
+                    -- resets the cpu and peripherals.
+                    --
+                    if CONFIG(BOOT_RESET) = '1' or BST_n = '0' then
+                        BOOTSTRAP_n <= '0'; 
+                    end if;
+    
+                else 
+                    -- If the NST signal goes high, then reset the BOOTSTRAP signal. This signal can only be set
+                    -- by a reset action.
+                    --
+                    if NST = '1' then
+                        BOOTSTRAP_n <= '1'; 
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Graphics Ram - Latch wether to enable Graphics RAM page from C000 - FFFF.
+    --
+    process( SYSTEM_RESET, CLKBUS(CKMASTER), CS_IO_GRAMENABLE_n, CS_IO_GRAMDISABLE_n ) begin
+        if(SYSTEM_RESET = '1') then
+            MZ_GRAM_ENABLE <= '0';
+
+        elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                if(CS_IO_GRAMENABLE_n = '0') then
+                    MZ_GRAM_ENABLE <= '0';
+    
+                elsif(CS_IO_GRAMDISABLE_n = '0') then
+                    MZ_GRAM_ENABLE <= '0';
+    
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Audio output. Choose between generated sound and CMT pulse audio.
+    --
+    AUDIO_L    <= SOUND when CONFIG(AUDIOSRC) = '0'            -- Sound Output Left
+                  else
+                  CMT_BUS_OUT(WRITEBIT);
+    AUDIO_R    <= SOUND when CONFIG(AUDIOSRC) = '0'            -- Sound Output Right
+                  else
+                  CMT_BUS_OUT(READBIT);
+
+    -- Only enable debugging LEDS if enabled in the config package.
+    --
+    DEBUG80B: if DEBUG_ENABLE = 1 generate
+
+        -- A simple 1*cpufreq second pulse to indicate accuracy of CPU frequency for debug purposes..
+        --
+        process (SYSTEM_RESET, CLKBUS(CKMASTER))
+            variable cnt : integer range 0 to 1999999 := 0;
+        begin
+            if SYSTEM_RESET = '1' then
+                PULSECPU <= '0';
+                cnt      := 0;
+            elsif rising_edge(CLKBUS(CKMASTER)) then
+                if CLKBUS(CKENCPU) = '1' then
+                    cnt      := cnt + 1;
+                    if cnt = 0 then
+                        PULSECPU <= not PULSECPU;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        -- Debug leds.
+        --
+        DEBUG_STATUS_LEDS(0)  <= CS_VRAM_ni;
+        DEBUG_STATUS_LEDS(1)  <= CS_GRAM_ni;
+        DEBUG_STATUS_LEDS(2)  <= CS_GRAM_80B_ni;
+        DEBUG_STATUS_LEDS(3)  <= CS_IO_8255_n;
+        DEBUG_STATUS_LEDS(4)  <= CS_IO_8254_n;
+        DEBUG_STATUS_LEDS(5)  <= CS_IO_Z80PIO_n;
+        DEBUG_STATUS_LEDS(6)  <= CS_ROM_ni;
+        DEBUG_STATUS_LEDS(7)  <= CS_RAM_ni;
+        --
+        DEBUG_STATUS_LEDS(8)  <= '0';
+        DEBUG_STATUS_LEDS(9)  <= CS_IO_8254_RST_CLK_n;
+        DEBUG_STATUS_LEDS(10) <= CS_IO_GRAMENABLE_n;
+        DEBUG_STATUS_LEDS(11) <= CS_IO_GRAMDISABLE_n;
+        DEBUG_STATUS_LEDS(12) <= CS_IO_GFB_ni;
+        DEBUG_STATUS_LEDS(13) <= CS_IO_G_ni;
+        DEBUG_STATUS_LEDS(14) <= '0';
+        DEBUG_STATUS_LEDS(15) <= '0';
+        --
+        DEBUG_STATUS_LEDS(16) <= BST_n;
+        DEBUG_STATUS_LEDS(17) <= NST;
+        DEBUG_STATUS_LEDS(18) <= MZ_GRAM_ENABLE;
+        DEBUG_STATUS_LEDS(19) <= BOOTSTRAP_n;
+        DEBUG_STATUS_LEDS(20) <= SEL_VRAM_ENABLE;
+        DEBUG_STATUS_LEDS(21) <= SEL_VRAM_HIGHADDR;
+        DEBUG_STATUS_LEDS(22) <= VGATE_ni;
+        DEBUG_STATUS_LEDS(23) <= CONFIG(BOOT_RESET);
+        --
+        DEBUG_STATUS_LEDS(24) <= PULSECPU;
+        DEBUG_STATUS_LEDS(25) <= T80_INT_ni;
+        DEBUG_STATUS_LEDS(26) <= '0';
+        DEBUG_STATUS_LEDS(27) <= COLD_RESET;
+        DEBUG_STATUS_LEDS(28) <= SYSTEM_RESET;
+        DEBUG_STATUS_LEDS(29) <= '0';
+        DEBUG_STATUS_LEDS(30) <= CONFIG(BOOT_RESET);
+        DEBUG_STATUS_LEDS(31) <= BST_n;
+        --
+        DEBUG_STATUS_LEDS(32) <= LED_RVS;
+        DEBUG_STATUS_LEDS(33) <= LED_GRPH;
+        DEBUG_STATUS_LEDS(34) <= LED_SHIFT_LOCK;
+        DEBUG_STATUS_LEDS(35) <= '0';
+        DEBUG_STATUS_LEDS(36) <= '0';
+        DEBUG_STATUS_LEDS(37) <= CASCADE01;
+        DEBUG_STATUS_LEDS(38) <= CASCADE12;
+        DEBUG_STATUS_LEDS(39) <= PULSECPU;
+        --
+        DEBUG_STATUS_LEDS(40) <= i8255_PA_O(0);
+        DEBUG_STATUS_LEDS(41) <= i8255_PA_O(1);
+        DEBUG_STATUS_LEDS(42) <= i8255_PA_O(2);
+        DEBUG_STATUS_LEDS(43) <= i8255_PA_O(3);
+        DEBUG_STATUS_LEDS(44) <= i8255_PA_O(4);
+        DEBUG_STATUS_LEDS(45) <= i8255_PA_O(5);
+        DEBUG_STATUS_LEDS(46) <= i8255_PA_O(6);
+        DEBUG_STATUS_LEDS(47) <= i8255_PA_O(7);
+        --
+        DEBUG_STATUS_LEDS(48) <= i8255_PB_I(0);
+        DEBUG_STATUS_LEDS(49) <= i8255_PB_I(1);
+        DEBUG_STATUS_LEDS(50) <= i8255_PB_I(2);
+        DEBUG_STATUS_LEDS(51) <= i8255_PB_I(3);
+        DEBUG_STATUS_LEDS(52) <= i8255_PB_I(4);
+        DEBUG_STATUS_LEDS(53) <= i8255_PB_I(5);
+        DEBUG_STATUS_LEDS(54) <= i8255_PB_I(6);
+        DEBUG_STATUS_LEDS(55) <= i8255_PB_I(7);
+        --
+        DEBUG_STATUS_LEDS(56) <= i8255_PC_O(0);
+        DEBUG_STATUS_LEDS(57) <= i8255_PC_O(1);
+        DEBUG_STATUS_LEDS(58) <= i8255_PC_O(2);
+        DEBUG_STATUS_LEDS(59) <= i8255_PC_O(3);
+        DEBUG_STATUS_LEDS(60) <= i8255_PC_O(4);
+        DEBUG_STATUS_LEDS(61) <= i8255_PC_O(5);
+        DEBUG_STATUS_LEDS(62) <= i8255_PC_O(6);
+        DEBUG_STATUS_LEDS(63) <= i8255_PC_O(7);
+
+        -- LEDS 64 .. 112 are available.
+        DEBUG_STATUS_LEDS(111 downto 64) <= (others => '0');
+    end generate;
+end rtl;
diff --git a/mz80b/mz80b_dummy.vhd b/mz80b/mz80b_dummy.vhd
new file mode 100644
index 0000000..4775b63
--- /dev/null
+++ b/mz80b/mz80b_dummy.vhd
@@ -0,0 +1,169 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            mz80b.vhd
+-- Created:         August 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series Business Computer:
+--                                  Models MZ-80B, MZ-2000
+--
+--                  This module is the main (top level) container for the Business MZ Computer
+--                  Emulation.
+--
+--                  The design tries to work from top-down, where components which are common 
+--                  to the Business and Personal MZ series are at the top (ie. main memory,
+--                  ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
+--                  to the machine specific modules and components. Some components are common
+--                  by their nature (ie. 8255 PIO) but these are instantiated within the lower
+--                  tree branch as their design use is less generic.
+--
+--                  The tree is as follows;-
+--
+--                                      (emu) sharpmz.vhd (mz80c)	->	mz80c.vhd
+--                                      |
+--                                      |
+--                                      |                                         -> cmt.vhd                   (common)
+--                                      |                                         -> keymatrix.vhd             (common)
+--                                      |                                         -> pll.v                     (common)
+--                                      |                                         -> clkgen.vhd                (common)
+--                                      |                                         -> T80                       (common)
+--                                      |                                         -> i8255                     (common)
+--                  sys_top.sv (emu) ->	(emu) sharpmz.vhd (hps_io) -> hps_io.sv
+--                                      |                                         -> i8253                     (common)
+--                                      |                                         -> dpram.vhd                 (common)
+--                                      |                                         -> dprom.vhd                 (common)
+--                                      |                                         -> mctrl.vhd                 (common)
+--                                      |                                         -> video.vhd                 (common)
+--                                      |
+--                                      |
+--                                      (emu) sharpmz.vhd (mz80b)	->	mz80b.vhd (under development)
+--
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         August 2018   - Initial module created.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity mz80b is
+    PORT (
+          -- Clocks
+          CLKBUS             : in  std_logic_vector(CLKBUS_WIDTH);    -- Clock signals created by clkgen module.
+
+          -- Resets.
+          SYSTEM_RESET       : in  std_logic;
+          
+          -- Z80 CPU
+          T80_RST_n          : in  std_logic;
+          T80_CLK            : in  std_logic;
+          T80_CLKEN          : out std_logic;
+          T80_WAIT_n         : out std_logic;
+          T80_INT_n          : out std_logic;
+          T80_NMI_n          : out std_logic;
+          T80_BUSRQ_n        : out std_logic;
+          T80_M1_n           : in  std_logic;
+          T80_MREQ_n         : in  std_logic;
+          T80_IORQ_n         : in  std_logic;
+          T80_RD_n           : in  std_logic;
+          T80_WR_n           : in  std_logic;
+          T80_RFSH_n         : in  std_logic;
+          T80_HALT_n         : in  std_logic;
+          T80_BUSAK_n        : in  std_logic;
+          T80_A16            : in  std_logic_vector(15 downto 0);
+          T80_DI             : out std_logic_vector(7 downto 0);
+          T80_DO             : in  std_logic_vector(7 downto 0);
+
+          -- Chip selects to common resources.
+          CS_ROM_n           : out std_logic;                            -- ROM Select
+          CS_RAM_n           : out std_logic;                            -- RAM Select
+          CS_VRAM_n          : out std_logic;                            -- VRAM Select
+          CS_MEM_G_n         : out std_logic;                            -- Memory mapped Peripherals Select
+          CS_GRAM_n          : out std_logic;                            -- GRAM Select
+          CS_GRAM_80B_n      : out std_logic;                            -- GRAM Select
+          CS_IO_G_n          : out std_logic;                            -- Graphics FB IO Select range
+          CS_SWP_MEMBANK_n   : out std_logic;
+
+          -- Audio.
+          AUDIO_L            : out std_logic;
+          AUDIO_R            : out std_logic;
+
+          -- Different operations modes.
+          CONFIG             : in  std_logic_vector(CONFIG_WIDTH);
+
+          -- I/O                                                         -- I/O down to the core.
+          KEYB_SCAN          : out std_logic_vector(3 downto 0);         -- Keyboard scan lines out.
+          KEYB_DATA          : in  std_logic_vector(7 downto 0);         -- Keyboard scan data in.
+          KEYB_STALL         : out std_logic;                            -- Keyboard Stall out.
+
+          -- Cassette magnetic tape signals.
+          CMT_BUS_OUT        : in  std_logic_vector(CMT_BUS_OUT_WIDTH);
+          CMT_BUS_IN         : out std_logic_vector(CMT_BUS_IN_WIDTH);
+
+          -- Video signals
+          VGATE_n            : out std_logic;                            -- Video Gate enable.
+          INVERSE            : out std_logic;                            -- Invert video output.
+          CHAR80             : out std_logic;                            -- 
+          HBLANK             : in  std_logic;                            -- Horizontal Blanking Signal
+          VBLANK             : in  std_logic;                            -- Vertical Blanking Signal
+
+          -- HPS Interface
+          IOCTL_DOWNLOAD     : in  std_logic;                            -- HPS Downloading to FPGA.
+          IOCTL_UPLOAD       : in  std_logic;                            -- HPS Uploading from FPGA.
+          IOCTL_CLK          : in  std_logic;                            -- HPS I/O Clock.
+          IOCTL_WR           : in  std_logic;                            -- HPS Write Enable to FPGA.
+          IOCTL_RD           : in  std_logic;                            -- HPS Read Enable from FPGA.
+          IOCTL_ADDR         : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+          IOCTL_DOUT         : in  std_logic_vector(15 downto 0);        -- HPS Data to be written into FPGA.
+          IOCTL_DIN          : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+
+          -- Debug Status Leds
+          DEBUG_STATUS_LEDS  : out std_logic_vector(111 downto 0)        -- 112 leds to display status.
+    );
+end mz80b;
+
+architecture rtl of mz80b is
+begin
+          T80_CLKEN          <= '1';
+          T80_WAIT_n         <= '1';
+          T80_INT_n          <= '1';
+          T80_NMI_n          <= '1';
+          T80_BUSRQ_n        <= '1';
+          T80_DI             <= (others => '0');
+          CS_ROM_n           <= '1';
+          CS_RAM_n           <= '1';
+          CS_VRAM_n          <= '1';
+          CS_MEM_G_n         <= '1';
+          CS_GRAM_n          <= '1';
+          CS_GRAM_80B_n      <= '1';
+          CS_IO_G_n          <= '1';
+          CS_SWP_MEMBANK_n   <= '1';
+          AUDIO_L            <= '1';
+          AUDIO_R            <= '1';
+          VGATE_n            <= '1';
+          INVERSE            <= '0';
+          CHAR80             <= '0';
+          CMT_BUS_IN(MOTORON)<= '0';
+          CMT_BUS_IN(READBIT)<= '0';
+          IOCTL_DIN          <= (others => '0');
+          DEBUG_STATUS_LEDS  <= (others => '0');
+end rtl;
diff --git a/mz80b/mz80b_video.vhd b/mz80b/mz80b_video.vhd
new file mode 100644
index 0000000..c7a62b1
--- /dev/null
+++ b/mz80b/mz80b_video.vhd
@@ -0,0 +1,647 @@
+--
+-- mz80b_video.vhd
+--
+-- Video display signal generator
+-- for MZ-80B on FPGA
+--
+-- Nibbles Lab. 2013-2014
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity mz80b_video is
+    Port (
+        RST_n                : in  std_logic;                           -- Reset
+        BOOTM                : in  std_logic;                           -- BOOT Mode
+        -- Type of machine we are emulating.
+        MODE_MZ80B           : in  std_logic;
+        MODE_MZ2000          : in  std_logic;
+        -- Type of display to emulate.
+        DISPLAY_NORMAL       : in  std_logic;
+        DISPLAY_NIDECOM      : in  std_logic;
+        DISPLAY_GAL5         : in  std_logic;
+        DISPLAY_COLOUR       : in  std_logic;
+        -- Different operations modes.
+        CONFIG_PCGRAM        : in  std_logic;                           -- PCG Mode Switch, 0 = CGROM, 1 = CGRAM.
+        -- Clocks
+        CK16M                : in  std_logic;                           -- 15.6kHz Dot Clock(16MHz)
+        T80_CLK_n            : in  std_logic;                           -- Z80 Current Clock
+        T80_CLK              : in  std_logic;                           -- Z80 Current Clock Inverted
+        -- CPU Signals
+        T80_A                : in  std_logic_vector(13 downto 0);       -- CPU Address Bus
+        CSV_n                : in  std_logic;                           -- CPU Memory Request(VRAM)
+        CSG_n                : in  std_logic;                           -- CPU Memory Request(GRAM)
+        T80_RD_n             : in  std_logic;                           -- CPU Read Signal
+        T80_WR_n             : in  std_logic;                           -- CPU Write Signal
+        T80_MREQ_n           : in  std_logic;                           -- CPU Memory Request
+        T80_BUSACK_n         : in  std_logic;                           -- CPU Bus Acknowledge
+        T80_WAIT_n           : out std_logic;                           -- CPU Wait Request
+        T80_DI               : in  std_logic_vector(7 downto 0);        -- CPU Data Bus(in)
+        T80_DO               : out std_logic_vector(7 downto 0);        -- CPU Data Bus(out)
+        -- Graphic VRAM Access
+        GCS_n                : out std_logic;                           -- GRAM Request
+        GADR                 : out std_logic_vector(20 downto 0);       -- GRAM Address
+        GT80_WR_n            : out std_logic;                           -- GRAM Write Signal
+        GBE_n                : out std_logic_vector(3 downto 0);        -- GRAM Byte Enable
+        GDI                  : in  std_logic_vector(31 downto 0);       -- Data Bus Input from GRAM
+        GDO                  : out std_logic_vector(31 downto 0);       -- Data Bus Output to GRAM
+        -- Video Control from outside
+        INV                  : in std_logic;                            -- Reverse mode(8255 PA4)
+        VGATE                : in std_logic;                            -- Video Output Control(8255 PC0)
+        CH80                 : in std_logic;                            -- Text Character Width(Z80PIO A5)
+        -- Video Signals
+        VGATE_n              : in  std_logic;                           -- Video Output Control
+        HBLANK               : out std_logic;                           -- Horizontal Blanking
+        VBLANK               : out std_logic;                           -- Vertical Blanking
+        HSYNC_n              : out std_logic;                           -- Horizontal Sync
+        VSYNC_n              : out std_logic;                           -- Vertical Sync
+        ROUT                 : out std_logic;                           -- Red Output
+        GOUT                 : out std_logic;                           -- Green Output
+        BOUT                 : out std_logic;                           -- Green Output
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                           -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);        -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                           -- HPS Write Enable to FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);       -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0)        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);       -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                            -- HPS Interrupt.
+    );
+end mz80b_video;
+
+architecture RTL of mz80b_video is
+
+--
+-- Registers
+--
+signal DIV                   : std_logic_vector(8 downto 0);             -- Clock Divider
+signal HCOUNT                : std_logic_vector(9 downto 0);             -- Counter for Horizontal Signals
+signal VCOUNT                : std_logic_vector(8 downto 0);             -- Counter for Vertical Signals
+signal VADR                  : std_logic_vector(10 downto 0);            -- VRAM Address(selected)
+signal VADRC                 : std_logic_vector(10 downto 0);            -- VRAM Address
+signal GADRC                 : std_logic_vector(13 downto 0);            -- GRAM Address
+signal GADRi                 : std_logic_vector(13 downto 0);            -- GRAM Address(for GRAM Access)
+signal VADRL                 : std_logic_vector(10 downto 0);            -- VRAM Address(latched)
+signal SDAT                  : std_logic_vector(7 downto 0);             -- Shift Register to Display
+signal SDATB                 : std_logic_vector(7 downto 0);             -- Shift Register to Display
+signal SDATR                 : std_logic_vector(7 downto 0);             -- Shift Register to Display
+signal SDATG                 : std_logic_vector(7 downto 0);             -- Shift Register to Display
+signal S2DAT                 : std_logic_vector(7 downto 0);             -- Shift Register to Display(for 40-char)
+signal S2DAT0                : std_logic_vector(7 downto 0);             -- Shift Register to Display(for 80B)
+signal S2DAT1                : std_logic_vector(7 downto 0);             -- Shift Register to Display(for 80B)
+--
+-- CPU Access
+--
+signal MA                    : std_logic_vector(11 downto 0);            -- Masked Address
+signal CSB4_x                : std_logic;                                -- Chip Select (PIO-3039 Color Board)
+signal CSF4_x                : std_logic;                                -- Chip Select (Background Color)
+signal CSF5_x                : std_logic;                                -- Chip Select (Display Select for C-Monitor)
+signal CSF6_x                : std_logic;                                -- Chip Select (Display Select for G-Monitor)
+signal CSF7_x                : std_logic;                                -- Chip Select (GRAM Select)
+signal GCSi_x                : std_logic;                                -- Chip Select (GRAM)
+signal RCSV                  : std_logic;                                -- Chip Select (VRAM, NiosII)
+signal RCSC                  : std_logic;                                -- Chip Select (CGROM, NiosII)
+signal VWEN                  : std_logic;                                -- WR + MREQ (VRAM)
+signal RVWEN                 : std_logic;                                -- WR + CS (VRAM, NiosII)
+signal RCWEN                 : std_logic;                                -- WR + CS (CGROM, NiosII)
+signal WAITi_n               : std_logic;                                -- Wait
+signal WAITii_n              : std_logic;                                -- Wait(delayed)
+signal ZGBE_n                : std_logic_vector(3 downto 0);             -- Byte Enable by Z80 access
+--
+-- Internal Signals
+--
+signal HDISPEN               : std_logic;                                -- Display Enable for Horizontal, almost same as HBLANK
+signal HBLANKi               : std_logic;                                -- Horizontal Blanking
+signal BLNK                  : std_logic;                                -- Horizontal Blanking (for wait)
+signal XBLNK                 : std_logic;                                -- Horizontal Blanking (for wait)
+signal VDISPEN               : std_logic;                                -- Display Enable for Vertical, same as VBLANK
+signal MB                    : std_logic;                                -- Display Signal (Mono, Blue)
+signal MG                    : std_logic;                                -- Display Signal (Mono, Green)
+signal MR                    : std_logic;                                -- Display Signal (Mono, Red)
+signal BB                    : std_logic;                                -- Display Signal (Color, Blue)
+signal BG                    : std_logic;                                -- Display Signal (Color, Green)
+signal BR                    : std_logic;                                -- Display Signal (Color, Red)
+signal PBGR                  : std_logic_vector(2 downto 0);             -- Display Signal (Color)
+signal POUT                  : std_logic_vector(2 downto 0);             -- Display Signal (Color)
+signal VRAMDO                : std_logic_vector(7 downto 0);             -- Data Bus Output for VRAM
+signal DCODE                 : std_logic_vector(7 downto 0);             -- Display Code, Read From VRAM
+signal CGDAT                 : std_logic_vector(7 downto 0);             -- Font Data To Display
+signal CGADR                 : std_logic_vector(10 downto 0);            -- Font Address To Display
+signal CCOL                  : std_logic_vector(2 downto 0);             -- Character Color
+signal BCOL                  : std_logic_vector(2 downto 0);             -- Background Color
+signal CCOLi                 : std_logic_vector(2 downto 0);             -- Character Color(reg)
+signal BCOLi                 : std_logic_vector(2 downto 0);             -- Background Color(reg)
+signal GPRI                  : std_logic;
+signal GPAGE                 : std_logic_vector(2 downto 0);
+signal GPAGEi                : std_logic_vector(2 downto 0);
+signal GDISPEN               : std_logic;
+signal GDISPENi              : std_logic;
+signal GBANK                 : std_logic_vector(1 downto 0);
+signal INVi                  : std_logic;
+signal VGATEi                : std_logic;
+signal GRAMBDI               : std_logic_vector(7 downto 0);             -- Data from GRAM(Blue)
+signal GRAMRDI               : std_logic_vector(7 downto 0);             -- Data from GRAM(Red)
+signal GRAMGDI               : std_logic_vector(7 downto 0);             -- Data from GRAM(Green)
+signal CH80i                 : std_logic;
+signal CDISPEN               : std_logic;
+signal PALET0                : std_logic_vector(2 downto 0);
+signal PALET1                : std_logic_vector(2 downto 0);
+signal PALET2                : std_logic_vector(2 downto 0);
+signal PALET3                : std_logic_vector(2 downto 0);
+signal PALET4                : std_logic_vector(2 downto 0);
+signal PALET5                : std_logic_vector(2 downto 0);
+signal PALET6                : std_logic_vector(2 downto 0);
+signal PALET7                : std_logic_vector(2 downto 0);
+
+--
+-- Components
+--
+component dprom
+    GENERIC (
+          init_file          : string;
+          widthad_a          : natural;
+          width_a            : natural
+    );
+    PORT
+    (
+          address_a          : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+          clock_a            : IN STD_LOGIC ;
+          data_a             : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+          wren_a             : IN STD_LOGIC;
+          q_a                : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+          address_b          : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+          clock_b            : IN STD_LOGIC ;
+          data_b             : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+          wren_b             : IN STD_LOGIC;
+          q_b                : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+    );
+end component;
+
+component dpram
+     generic (
+          init_file          : string;
+          widthad_a          : natural;
+          width_a            : natural
+      );
+      Port (
+          clock_a            : in  std_logic ;
+          clocken_a          : in  std_logic := '1';
+          address_a          : in  std_logic_vector (widthad_a-1 downto 0);
+          data_a             : in  std_logic_vector (width_a-1 downto 0);
+          wren_a             : in  std_logic;
+          q_a                : out std_logic_vector (width_a-1 downto 0);
+
+          clock_b            : in  std_logic ;
+          clocken_b          : in  std_logic := '1';
+          address_b          : in  std_logic_vector (widthad_a-1 downto 0);
+          data_b             : in  std_logic_vector (width_a-1 downto 0);
+          wren_b             : in  std_logic;
+          q_b                : out std_logic_vector (width_a-1 downto 0)
+    );
+end component;
+
+component cgrom
+    PORT
+    (
+        data                 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+        rdaddress            : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+        rdclock              : IN STD_LOGIC ;
+        wraddress            : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+        wrclock              : IN STD_LOGIC  := '1';
+        wren                 : IN STD_LOGIC  := '0';
+        q                    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+    );
+end component;
+
+component dpram2k
+    PORT
+    (
+        address_a            : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+        address_b            : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+        clock_a              : IN STD_LOGIC  := '1';
+        clock_b              : IN STD_LOGIC ;
+        data_a               : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+        data_b               : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+        wren_a               : IN STD_LOGIC  := '0';
+        wren_b               : IN STD_LOGIC  := '0';
+        q_a                  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+        q_b                  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    VRAM0 : dpram
+    GENERIC MAP (
+        init_file            => "./roms/MZFONT.mif",
+        widthad_a            => 11,
+        width_a              => 8
+    )
+    PORT MAP (
+        clock_a              => CK8M,
+        clocken_a            => CK16M,
+        address_a            => VADR,
+        data_a               => T80_DI,
+        wren_a               => VWEN,
+        q_a                  => VRAMDO,
+
+        clock_b              => CK16M,
+        clocken_b            => IOCTL_CSVVRAM_n,
+        address_b            => IOCTL_ADDR(10 DOWNTO 0),
+        data_b               => IOCTL_DOUT(7 DOWNTO 0),
+        wren_b               => RVWEN, --IOCTL_WR,
+        q_b                  => open
+    );
+
+    CGROM0 : dprom
+    GENERIC MAP (
+        init_file            => "./roms/MZ80K_cgrom.mif",
+        widthad_a            => 11,
+        width_a              => 8
+    ) 
+    PORT MAP (
+        address_a            => CGADR,
+        clock_a              => CK16M,
+        data_a               => IOCTL_DOUT(7 DOWNTO 0),
+        wren_a               => '0',
+        q_a                  => CGDAT,
+
+        address_b            => IOCTL_ADDR(10 DOWNTO 0),
+        clock_b              => IOCTL_CSCGROM_n,
+        data_b               => IOCTL_DOUT(7 DOWNTO 0),
+        wren_b               => ROWEN,--IOCTL_WR
+        q_b                  => open
+    );
+
+    --
+    -- Blank & Sync Generation
+    --
+    process( RST_n, CK16M ) begin
+
+        if RST_n='0' then
+            HCOUNT         <= "1111111000";
+            HBLANKi        <= '0';
+            HDISPEN        <= '0';
+            BLNK           <= '0';
+            HSYNC_n        <= '1';
+            VDISPEN        <= '1';
+            VSYNC_n        <= '1';
+            GCSi_x         <= '1';
+            VADRC          <= (others=>'0');
+            GADRC          <= (others=>'0');
+            VADRL          <= (others=>'0');
+        elsif CK16M'event and CK16M='1' then
+
+            -- Counters
+            if HCOUNT=1015 then
+                --HCOUNT<=(others=>'0');
+                HCOUNT     <= "1111111000";
+                VADRC      <= VADRL;                                     -- Return to Most-Left-Column Address
+                if VCOUNT=259 then
+                    VCOUNT <= (others=>'0');
+                    VADRC  <= (others=>'0');                             -- Home Position
+                    GADRC  <= (others=>'0');                             -- Home Position
+                    VADRL  <= (others=>'0');
+                else
+                    VCOUNT <= VCOUNT+'1';
+                end if;
+            else
+                HCOUNT     <= HCOUNT+'1';
+            end if;
+
+            -- Horizontal Signals Decode
+            if HCOUNT=0 then
+                HDISPEN    <= VDISPEN;                                   -- if V-DISP is Enable then H-DISP Start
+            elsif HCOUNT=632 then
+                HBLANKi    <= '1';                                       -- H-Blank Start
+                BLNK       <= '1';
+            elsif HCOUNT=640 then
+                HDISPEN    <= '0';                                       -- H-DISP End
+            elsif HCOUNT=768 then
+                HSYNC_n    <= '0';                                       -- H-Sync Pulse Start
+            elsif HCOUNT=774 and VCOUNT(2 downto 0)="111" then
+                VADRL      <= VADRC;                                     -- Save Most-Left-Column Address
+            elsif HCOUNT=859 then
+                HSYNC_n    <= '1';                                       -- H-Sync Pulse End
+            elsif HCOUNT=992 then
+                BLNK       <= '0';
+            elsif HCOUNT=1015 then
+                HBLANKi    <= '0';                                       -- H-Blank End
+            end if;
+
+            -- VRAM Address counter(per 8dot)
+            if HBLANKi='0' then
+                if (HCOUNT(2 downto 0)="111" and CH80i='1') or (HCOUNT(3 downto 0)="1111" and CH80i='0') then
+                    VADRC  <= VADRC+'1';
+                end if;
+                if (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
+                    GADRC  <= GADRC+'1';
+                end if;
+            end if;
+
+            -- Graphics VRAM Access signal
+            if HBLANKi='0' then
+                if (HCOUNT(2 downto 0)="000" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1000" and MODE_MZ80B='1') then
+                  GCSi_x   <= '0';
+                elsif (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
+                  GCSi_x   <= '1';
+                end if;
+            else
+                GCSi_x     <= '1';
+            end if;
+
+            -- Get Font/Pattern data and Shift
+            if HCOUNT(3 downto 0)="0000" then
+                if CH80i='1' then
+                    SDAT   <= CGDAT;
+                else
+                    SDAT   <= CGDAT(7)&CGDAT(7)&CGDAT(6)&CGDAT(6)&CGDAT(5)&CGDAT(5)&CGDAT(4)&CGDAT(4);
+                    S2DAT  <= CGDAT(3)&CGDAT(3)&CGDAT(2)&CGDAT(2)&CGDAT(1)&CGDAT(1)&CGDAT(0)&CGDAT(0);
+                end if;
+                if MODE_MZ2000='1' then
+                    SDATB  <= GRAMBDI;
+                    SDATR  <= GRAMRDI;
+                    SDATG  <= GRAMGDI;
+                else
+                    SDATB  <= GRAMBDI(3)&GRAMBDI(3)&GRAMBDI(2)&GRAMBDI(2)&GRAMBDI(1)&GRAMBDI(1)&GRAMBDI(0)&GRAMBDI(0);
+                    S2DAT0 <= GRAMBDI(7)&GRAMBDI(7)&GRAMBDI(6)&GRAMBDI(6)&GRAMBDI(5)&GRAMBDI(5)&GRAMBDI(4)&GRAMBDI(4);
+                    SDATR  <= GRAMRDI(3)&GRAMRDI(3)&GRAMRDI(2)&GRAMRDI(2)&GRAMRDI(1)&GRAMRDI(1)&GRAMRDI(0)&GRAMRDI(0);
+                    S2DAT1 <= GRAMRDI(7)&GRAMRDI(7)&GRAMRDI(6)&GRAMRDI(6)&GRAMRDI(5)&GRAMRDI(5)&GRAMRDI(4)&GRAMRDI(4);
+                end if;
+            elsif HCOUNT(3 downto 0)="1000" then
+                if CH80i='1' then
+                    SDAT   <= CGDAT;
+                else
+                    SDAT   <= S2DAT;
+                end if;
+                if MODE_MZ2000='1' then
+                    SDATB  <= GRAMBDI;
+                    SDATR  <= GRAMRDI;
+                    SDATG  <= GRAMGDI;
+                else
+                    SDATB  <= S2DAT0;
+                    SDATR  <= S2DAT1;
+                end if;
+            else
+                SDAT       <= SDAT(6 downto 0)&'0';
+                SDATB      <= '0'&SDATB(7 downto 1);
+                SDATR      <= '0'&SDATR(7 downto 1);
+                SDATG      <= '0'&SDATG(7 downto 1);
+            end if;
+
+            -- Vertical Signals Decode
+            if VCOUNT=0 then
+                VDISPEN    <= '1';            -- V-DISP Start
+            elsif VCOUNT=200 then
+                VDISPEN    <= '0';            -- V-DISP End
+            elsif VCOUNT=219 then
+                VSYNC_n    <= '0';                -- V-Sync Pulse Start
+            elsif VCOUNT=223 then
+                VSYNC_n    <= '1';                -- V-Sync Pulse End
+            end if;
+
+        end if;
+
+    end process;
+
+    --
+    -- Control Registers
+    --
+    process( RST_n, T80_CLK ) begin
+        if RST_n='0' then
+            BCOLi          <= (others=>'0');
+            CCOLi          <= (others=>'1');
+            GPRI           <= '0';
+            GPAGEi         <= "000";
+            GDISPENi       <= '0';
+            CDISPEN        <= '1';
+            GBANK          <= "00";
+            PALET0         <= "000";
+            PALET1         <= "111";
+            PALET2         <= "111";
+            PALET3         <= "111";
+            PALET4         <= "111";
+            PALET5         <= "111";
+            PALET6         <= "111";
+            PALET7         <= "111";
+        elsif T80_CLK'event and T80_CLK='0' then
+            if T80_WR_n='0' then
+                if MODE_MZ2000='1' then        -- MZ-2000
+                    -- Background Color
+                    if CSF4_x='0' then
+                        BCOLi    <= T80_DI(2 downto 0);
+                    end if;
+                    -- Character Color and Priority
+                    if CSF5_x='0' then
+                        CCOLi    <= T80_DI(2 downto 0);
+                        GPRI     <= T80_DI(3);
+                    end if;
+                    -- Display Graphics and Pages
+                    if CSF6_x='0' then
+                        GPAGEi   <= T80_DI(2 downto 0);
+                        GDISPENi <= not T80_DI(3);
+                    end if;
+                    -- Select Accessable Graphic Banks
+                    if CSF7_x='0' then
+                        GBANK    <= T80_DI(1 downto 0);
+                    end if;
+                else                            -- MZ-80B
+                    -- Color Control(PIO-3039)
+                    if CSB4_x='0' then
+                        if T80_DI(6)='1' then
+                            CDISPEN <= T80_DI(7);
+                        else
+                            case T80_DI(2 downto 0) is
+                                when "000" => PALET0<=T80_DI(5 downto 3);
+                                when "001" => PALET1<=T80_DI(5 downto 3);
+                                when "010" => PALET2<=T80_DI(5 downto 3);
+                                when "011" => PALET3<=T80_DI(5 downto 3);
+                                when "100" => PALET4<=T80_DI(5 downto 3);
+                                when "101" => PALET5<=T80_DI(5 downto 3);
+                                when "110" => PALET6<=T80_DI(5 downto 3);
+                                when "111" => PALET7<=T80_DI(5 downto 3);
+                                when others => PALET0<=T80_DI(5 downto 3);
+                            end case;
+                        end if;
+                    end if;
+                    -- Select Accessable Graphic Banks and Outpu Pages
+                    if CSF4_x='0' then
+                        GBANK   <= T80_DI(0)&(not T80_DI(0));
+                        GPAGEi(1 downto 0)<=T80_DI(2 downto 1);
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Timing Conditioning and Wait
+    --
+    process( T80_MREQ_n ) begin
+        if T80_MREQ_n'event and T80_MREQ_n='0' then
+            XBLNK<=BLNK;
+        end if;
+    end process;
+
+    process( T80_CLK ) begin
+        if T80_CLK'event and T80_CLK='1' then
+            WAITii_n<=WAITi_n;
+        end if;
+    end process;
+    WAITi_n<='0' when (CSV_n='0' or CSG_n='0') and XBLNK='0' and BLNK='0' else '1';
+    T80_WAIT_n<=WAITi_n and WAITii_n;
+
+    --
+    -- Mask by Mode
+    --
+    ZGBE_n       <= "1110"                 when GBANK="01" else
+                    "1101"                 when GBANK="10" else
+                    "1011"                 when GBANK="11" else "1111";
+    GBE_n        <= ZGBE_n                 when BLNK='1' else "1000";
+    GT80_WR_n    <= T80_WR_n               when BLNK='1' else '1';
+    GCS_n        <= CSG_n                  when BLNK='1' else GCSi_x;
+    RCSV         <= '0'                    when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11010" else '1';
+    RCSC         <='0'                     when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11001" else '1';
+    VWEN         <='1'                     when T80_WR_n='0' and CSV_n='0' and BLNK='1' else '0';
+    RVWEN        <= not(IOCTL_WR='1' or RCSV);
+    RCWEN        <= not(IOCTL_WR='1' or RCSC);
+    CSB4_x       <= '0'                    when T80_A(7 downto 0)=X"B4" and T80_IORQ_n='0' else '1';
+    CSF4_x       <= '0'                    when T80_A(7 downto 0)=X"F4" and T80_IORQ_n='0' else '1';
+    CSF5_x       <= '0'                    when T80_A(7 downto 0)=X"F5" and T80_IORQ_n='0' else '1';
+    CSF6_x       <= '0'                    when T80_A(7 downto 0)=X"F6" and T80_IORQ_n='0' else '1';
+    CSF7_x       <= '0'                    when T80_A(7 downto 0)=X"F7" and T80_IORQ_n='0' else '1';
+    CCOL         <= CCOLi                  when T80_BUSACK_n='1' else "111";
+    BCOL         <= BCOLi                  when T80_BUSACK_n='1' else "000";
+    INVi         <= INV                    when BOOTM='0' and T80_BUSACK_n='1' else '1';
+    VGATEi       <= VGATE                  when BOOTM='0' and T80_BUSACK_n='1' else '0';
+    GPAGE        <= GPAGEi                 when BOOTM='0' and T80_BUSACK_n='1' else "000";
+    GDISPEN      <= '0'                    when BOOTM='1' or T80_BUSACK_n='0' else
+                    '1'                    when MODE_MZ80B='1' else GDISPENi;
+    CH80i        <= CH80                   when BOOTM='0' and T80_BUSACK_n='1' else '0';
+
+    --
+    -- Bus Select
+    --
+    VADR         <= T80_A(10 downto 0)     when CSV_n='0' and BLNK='1' else VADRC;
+    GADRi        <= T80_A(13 downto 0)     when CSG_n='0' and BLNK='1' and MODE_MZ2000='1' else
+                    '0'&T80_A(12 downto 0) when CSG_n='0' and BLNK='1' and MODE_MZ80B='1' else GADRC;
+    GADR         <= "1111101"&GADRi;    -- 0x7D0000
+    DCODE        <= T80_DI                 when CSV_n='0' and BLNK='1' and T80_WR_n='0' else VRAMDO;
+    T80_DO       <= VRAMDO                 when T80_RD_n='0' and CSV_n='0' else
+                    GDI(7 downto 0)        when T80_RD_n='0' and CSG_n='0' and GBANK="01" else
+                    GDI(15 downto 8)       when T80_RD_n='0' and CSG_n='0' and GBANK="10" else
+                    GDI(23 downto 16)      when T80_RD_n='0' and CSG_n='0' and GBANK="11" else (others=>'0');
+    CGADR        <= DCODE&VCOUNT(2 downto 0);
+    GRAMBDI      <= GDI(7 downto 0)        when GPAGE(0)='1' else (others=>'0');
+    GRAMRDI      <= GDI(15 downto 8)       when GPAGE(1)='1' else (others=>'0');
+    GRAMGDI      <= GDI(23 downto 16)      when GPAGE(2)='1' else (others=>'0');
+    GDO          <= "00000000"&T80_DI&T80_DI&T80_DI;
+
+    --
+    -- Color Decode
+    --
+    -- Monoclome Monitor
+--    MB<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
+--    MR<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
+    MB           <= '0';
+    MR           <= '0';
+    MG           <= not (SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0)))) when HDISPEN='1' and VGATEi='0' and INVi='0' else
+                    SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0))) when HDISPEN='1' and VGATEi='0' and INVi='1' else '0';
+
+    -- Color Monitor(MZ-2000)
+    process( HDISPEN, VGATEi, GPRI, SDAT(7), SDATB(0), SDATR(0), SDATG(0), CCOL, BCOL ) begin
+        if HDISPEN='1' and VGATEi='0' then
+            if SDAT(7)='0' and SDATB(0)='0' then
+                BB<=BCOL(0);
+            else
+                if GPRI='0' then
+                    if SDAT(7)='1' then
+                        BB<=CCOL(0);
+                    else
+                        BB<='1';    -- SDATB(0)='1'
+                    end if;
+                else     --GPRI='1'
+                    if SDATB(0)='1' then
+                        BB<='1';
+                    else
+                        BB<=CCOL(0);    -- SDAT(7)='1'
+                    end if;
+                end if;
+            end if;
+            if SDAT(7)='0' and SDATR(0)='0' then
+                BR<=BCOL(1);
+            else
+                if GPRI='0' then
+                    if SDAT(7)='1' then
+                        BR<=CCOL(1);
+                    else
+                        BR<='1';    -- SDATR(0)='1'
+                    end if;
+                else    --GPRI='1' then
+                    if SDATR(0)='1' then
+                        BR<='1';
+                    else
+                        BR<=CCOL(1);    -- SDAT(7)='1'
+                    end if;
+                end if;
+            end if;
+            if SDAT(7)='0' and SDATG(0)='0' then
+                BG<=BCOL(2);
+            else
+                if GPRI='0' then
+                    if SDAT(7)='1' then
+                        BG<=CCOL(2);
+                    else
+                        BG<='1';    -- SDATG(0)='1'
+                    end if;
+                else    --GPRI='1' then
+                    if SDATG(0)='1' then
+                        BG<='1';
+                    else
+                        BG<=CCOL(2);    -- SDAT(7)='1'
+                    end if;
+                end if;
+            end if;
+        else
+            BB<='0';
+            BR<='0';
+            BG<='0';
+        end if;
+    end process;
+    -- Color Monitor(PIO-3039)
+    POUT<=(SDAT(7) and CDISPEN)&SDATR(0)&SDATB(0);
+    process(POUT, PALET0, PALET1, PALET2, PALET3, PALET4, PALET5, PALET6, PALET7) begin
+        case POUT is
+            when "000" => PBGR<=PALET0;
+            when "001" => PBGR<=PALET1;
+            when "010" => PBGR<=PALET2;
+            when "011" => PBGR<=PALET3;
+            when "100" => PBGR<=PALET4;
+            when "101" => PBGR<=PALET5;
+            when "110" => PBGR<=PALET6;
+            when "111" => PBGR<=PALET7;
+            when others => PBGR<=PALET7;
+        end case;
+    end process;
+
+    --
+    -- Output
+    --
+    CK16M  <= CK16M;
+    VBLANK <= VDISPEN;
+    HBLANK <= HBLANKi;
+    ROUT   <= MR when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
+              BR when MODE_COLOUR='1' and MODE_MZ2000='1'              else PBGR(0);
+    GOUT   <= MG when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
+              BG when MODE_COLOUR='1' and MODE_MZ2000='1'              else PBGR(1);
+    BOUT   <= MB when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
+              BB when MODE_COLOUR='1' and MODE_MZ2000='1'              else PBGR(2);
+
+end RTL;
diff --git a/mz80b/mz80b_x.vhd b/mz80b/mz80b_x.vhd
new file mode 100644
index 0000000..e5adf37
--- /dev/null
+++ b/mz80b/mz80b_x.vhd
@@ -0,0 +1,854 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            mz80b.vhd
+-- Created:         August 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series Business Computer:
+--                                  Models MZ-80B, MZ-2000
+--
+--                  This module is the main (top level) container for the Business MZ Computer
+--                  Emulation.
+--
+--                  The design tries to work from top-down, where components which are common 
+--                  to the Business and Personal MZ series are at the top (ie. main memory,
+--                  ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
+--                  to the machine specific modules and components. Some components are common
+--                  by their nature (ie. 8255 PIO) but these are instantiated within the lower
+--                  tree branch as their design use is less generic.
+--
+--                  The tree is as follows;-
+--
+--                                      (emu) sharpmz.vhd (mz80c)	->	mz80c.vhd
+--                                      |                                         -> mz80c_video.vhd
+--                                      |                                         -> pcg.vhd
+--                                      |                                         -> cmt.vhd (this may move to common and be shared with mz80b)
+--                                      |                                         -> keymatrix.vhd             (common)
+--                                      |                                         -> pll.v                     (common)
+--                                      |                                         -> clkgen.vhd                (common)
+--                                      |                                         -> T80                       (common)
+--                                      |                                         -> i8255                     (common)
+--                                      |                                         -> i8253                     (common)
+--                                      |                                         -> dpram.vhd                 (common)
+--                                      |                                         -> dprom.vhd                 (common)
+--                                      |                                         -> mctrl.vhd                 (common)
+--                  sys_top.sv (emu) ->	(emu) sharpmz.vhd (hps_io) -> hps_io.sv
+--                                      |
+--                                      (emu) sharpmz.vhd (mz80b)	->	mz80b.vhd (under development)
+--
+--
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         August 2018   - Initial module created.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity mz80b is
+    PORT (
+          -- Clocks
+          CK50M              : in  std_logic;                            -- Master Clock(50MHz)
+          CK25M              : in  std_logic;                            -- VGA Clock MZ80B (25MHz)
+          CK16M              : in  std_logic;                            -- MZ80B CPU Clock (16MHz)
+          CK12M5             : in  std_logic;                            -- VGA Clock MZ80C (12.5MHz)
+          CK8M               : in  std_logic;                            -- 15.6kHz Dot Clock(8MHz)
+          CK4M               : in  std_logic;                            -- CPU Turbo Clock MZ80C (4MHz)
+          CK3M125            : in  std_logic;                            -- Music Base Clock(31.25kHz)
+          CK2M               : in  std_logic;                            -- Z80 Original Clock MZ80C
+          CLKVIDEO           : out std_logic;                            -- Base clock for video.
+
+          -- Resets.
+          COLD_RESET         : in  std_logic;
+          WARM_RESET         : in  std_logic;
+          
+          -- Z80 CPU
+          T80_RST_n          : in  std_logic;
+          T80_CLK_n          : in  std_logic;
+          T80_CLKEN          : out std_logic;
+          T80_WAIT_n         : out std_logic;
+          T80_INT_n          : out std_logic;
+          T80_NMI_n          : out std_logic;
+          T80_BUSRQ_n        : out std_logic;
+          T80_M1_n           : in  std_logic;
+          T80_MREQ_n         : in  std_logic;
+          T80_IORQ_n         : in  std_logic;
+          T80_RD_n           : in  std_logic;
+          T80_WR_n           : in  std_logic;
+          T80_RFSH_n         : in  std_logic;
+          T80_HALT_n         : in  std_logic;
+          T80_BUSAK_n        : in  std_logic;
+          T80_A16            : in  std_logic_vector(15 downto 0);
+          T80_DI             : out std_logic_vector(7 downto 0);
+          T80_DO             : in  std_logic_vector(7 downto 0);
+
+          -- Chip selects to common resources.
+          CSROM_n            : out std_logic;
+          CSRAM_n            : out std_logic;
+
+          -- Audio.
+          AUDIO_L            : out std_logic;
+          AUDIO_R            : out std_logic;
+
+          -- Video signals.
+          R                  : out std_logic;
+          G                  : out std_logic;
+          B                  : out std_logic;
+          HSYNC_n            : out std_logic;
+          VSYNC_n            : out std_logic;
+          HBLANK             : out std_logic;
+          VBLANK             : out std_logic;
+
+          -- Type of machine we are emulating.
+          MODE_MZ80K         : in  std_logic;
+          MODE_MZ80C         : in  std_logic;
+          MODE_MZ1200        : in  std_logic;
+          MODE_MZ80A         : in  std_logic;
+          MODE_MZ80B         : in  std_logic;
+          MODE_MZ2000        : in  std_logic;
+          MODE_MZ700         : in  std_logic;
+          MODE_MZ800         : in  std_logic;
+          MODE_MZ_KC         : in  std_logic;
+          MODE_MZ_A          : in  std_logic;
+          MODE_MZ_B          : in  std_logic;
+          MODE_MZ_80C        : in  std_logic;
+          MODE_MZ_80B        : in  std_logic;
+          -- Type of display to emulate.
+          DISPLAY_NORMAL     : in  std_logic;
+          DISPLAY_NIDECOM    : in  std_logic;
+          DISPLAY_GAL5       : in  std_logic;
+          DISPLAY_COLOUR     : in  std_logic;
+          -- Buttons to emulate.
+          BUTTON_PLAYSW      : in  std_logic;                            -- Tape Play Switch, 1 = Play.
+          -- Different operations modes
+          CONFIG_TURBO       : in  std_logic;                            -- CPU Speed, 0 = Normal, 1 = Turbo
+
+          -- I/O                                                         -- I/O down to the core.
+          PS2_KEY            : in  std_logic_vector(10 downto 0);
+          PS2_MOUSE          : in  std_logic_vector(24 downto 0);
+
+          -- HPS Interface
+          IOCTL_DOWNLOAD     : in  std_logic;                            -- HPS Downloading to FPGA.
+          IOCTL_INDEX        : in  std_logic_vector(7 downto 0);         -- Menu index used to upload file.
+          IOCTL_WR           : in  std_logic;                            -- HPS Write Enable to FPGA.
+          IOCTL_RD           : in  std_logic;                            -- HPS Read Enable from FPGA.
+          IOCTL_ADDR         : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+          IOCTL_DOUT         : in  std_logic_vector(15 downto 0);        -- HPS Data to be written into FPGA.
+          IOCTL_DIN          : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+          IOCTL_INTERRUPT    : out std_logic;                            -- HPS Interrupt.
+
+          -- Debug Status Leds
+          DEBUG_STATUS_LEDS  : out std_logic_vector(23 downto 0)         -- 24 leds to display status.
+    );
+end mz80b;
+
+        -- Switch
+        SW                : in std_logic_vector(9 downto 0);    --    Toggle Switch[9:0]
+        -- PS2
+        PS2_KBDAT    : in std_logic;                        --    PS2 Keyboard Data
+        PS2_KBCLK    : in std_logic;                        --    PS2 Keyboard Clock
+  );
+end mz80b_core;
+
+architecture rtl of mz80b_core is
+
+          DEBUG_STATUS_LEDS  : out std_logic_vector(23 downto 0)         -- 24 leds to display status.
+--
+-- T80
+--
+signal MREQ_n                : std_logic;
+signal IORQ_n                : std_logic;
+signal RD_n                  : std_logic;
+--signal MWR                 : std_logic;
+--signal MRD                 : std_logic;
+signal IWR                   : std_logic;
+signal ZWAIT_n               : std_logic;
+signal M1                    : std_logic;
+signal RFSH_n                : std_logic;
+signal ZDTO                  : std_logic_vector(7 downto 0);
+signal ZDTI                  : std_logic_vector(7 downto 0);
+--signal RAMCS_n             : std_logic;
+signal RAMDI                 : std_logic_vector(7 downto 0);
+signal BAK_n                 : std_logic;
+signal BREQ_n                : std_logic;
+--
+-- Clocks
+--
+signal CK4M                  : std_logic;
+signal CK16M                 : std_logic;
+signal CK25M                 : std_logic;
+signal CK3125                : std_logic;
+--signal SCLK                : std_logic;
+--signal HCLK                : std_logic;
+signal CASCADE01             : std_logic;
+signal CASCADE12             : std_logic;
+--
+-- Decodes, misc
+--
+--signal CSE_n               : std_logic;
+--signal CSE2_n              : std_logic;
+--signal BUF                 : std_logic_vector(9 downto 0);
+signal CSHSK                 : std_logic;
+signal MZMODE                : std_logic;
+signal DMODE                 : std_logic;
+signal KBEN                  : std_logic;
+signal KBDT                  : std_logic_vector(7 downto 0);
+signal BOOTM                 : std_logic;
+signal F_BTN                 : std_logic;
+signal IRQ_CMT               : std_logic;
+signal C_LEDG                : std_logic_vector(9 downto 0);
+signal IRQ_FDD               : std_logic;
+signal F_LEDG                : std_logic_vector(9 downto 0);
+--
+-- Video
+--
+signal HBLANKi               : std_logic;
+signal VBLANKi               : std_logic;
+signal HSYNC_ni              : std_logic;
+signal VSYNC_ni              : std_logic;
+signal Ri                    : std_logic;
+signal Gi                    : std_logic;
+signal Bi                    : std_logic;
+--signal VGATE               : std_logic;
+signal CSV_n                 : std_logic;
+signal CSG_n                 : std_logic;
+signal VRAMDO                : std_logic_vector(7 downto 0);
+--
+-- PPI
+--
+signal CSE0_n                : std_logic;
+signal PPI_DO                 : std_logic_vector(7 downto 0);
+signal PPIPA                 : std_logic_vector(7 downto 0);
+signal PPIPB                 : std_logic_vector(7 downto 0);
+signal PPIPC                 : std_logic_vector(7 downto 0);
+signal BST_n                 : std_logic;
+--
+-- PIT
+--
+signal CSE4_n                : std_logic;
+signal DOPIT                 : std_logic_vector(7 downto 0);
+signal RST8253_n             : std_logic;
+--
+-- PIO
+--
+signal CSE8_n                : std_logic;
+signal PIO_DO                 : std_logic_vector(7 downto 0);
+signal INT_n                 : std_logic;
+signal PIOPA                 : std_logic_vector(7 downto 0);
+signal PIOPB                 : std_logic_vector(7 downto 0);
+--
+-- FDD,FDC
+--
+signal DOFDC                 : std_logic_vector(7 downto 0);
+signal DS                    : std_logic_vector(3 downto 0);
+signal HS                    : std_logic;
+signal MOTOR_n               : std_logic;
+signal INDEX_n               : std_logic;
+signal TRACK00_n             : std_logic;
+signal WPRT_n                : std_logic;
+signal STEP_n                : std_logic;
+signal DIREC                 : std_logic;
+signal FDO                   : std_logic_vector(7 downto 0);
+signal FDI                   : std_logic_vector(7 downto 0);
+signal WGATE_n               : std_logic;
+signal DTCLK                 : std_logic;
+--
+-- for Debug
+--
+
+--
+-- Components
+--
+component i8255
+    Port (
+        RST                  : in std_logic;
+        CLK                  : in std_logic;
+        A                    : in std_logic_vector(1 downto 0);
+        CS                   : in std_logic;
+        RD                   : in std_logic;
+        WR                   : in std_logic;
+        DI                   : in std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        -- Port
+        PA                   : out std_logic_vector(7 downto 0);
+        PB                   : in std_logic_vector(7 downto 0);
+        PC                   : out std_logic_vector(7 downto 0);
+        -- Mode
+        MODE_MZ80B           : in  std_logic;
+        MODE_MZ2000          : in  std_logic
+    );
+end component;
+
+component i8253
+    Port (
+        RST                  : in  std_logic;
+        CLK_n                : in  std_logic;
+        A                    : in  std_logic_vector(1 downto 0);
+        DI                   : in  std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        CS_n                 : in  std_logic;
+        WR_n                 : in  std_logic;
+        RD_n                 : in  std_logic;
+        CLK0                 : in  std_logic;
+        GATE0                : in  std_logic;
+        OUT0                 : out std_logic;
+        CLK1                 : in  std_logic;
+        GATE1                : in  std_logic;
+        OUT1                 : out std_logic;
+        CLK2                 : in  std_logic;
+        GATE2                : in  std_logic;
+        OUT2                 : out std_logic
+    );
+end component;
+
+component z8420
+    Port (
+        -- System
+        RST_n                : in std_logic;                             -- Only Power On Reset
+        -- Z80 Bus Signals
+        CLK                  : in std_logic;
+        BASEL                : in std_logic;
+        CDSEL                : in std_logic;
+        CE                   : in std_logic;
+        RD_n                 : in std_logic;
+        WR_n                 : in std_logic;
+        IORQ_n               : in std_logic;
+        M1_n                 : in std_logic;
+        DI                   : in std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        IEI                  : in std_logic;
+        IEO                  : out std_logic;
+        INT_n                : out std_logic;
+        -- Port
+        A                    : out std_logic_vector(7 downto 0);
+        B                    : in std_logic_vector(7 downto 0);
+    );
+end component;
+
+component keymatrix
+    Port (
+        RST_n                : in  std_logic;
+        CLK                  : in  std_logic;                           -- System Clock
+        -- Operating mode of emulator
+        MZ_MODE_B            : in  std_logic;
+        -- i8255
+        PA                   : in  std_logic_vector(3 downto 0);
+        PB                   : out std_logic_vector(7 downto 0);
+        STALL                : in  std_logic;
+        -- PS/2 Keyboard Data
+        PS2_KEY              : in  std_logic_vector(10 downto 0);       -- PS2 Key data.
+        PS2_MOUSE            : in  std_logic_vector(24 downto 0);       -- PS2 Mouse data.
+        -- Type of machine we are emulating.
+        MODE_MZ80K           : in  std_logic;
+        MODE_MZ80C           : in  std_logic;
+        MODE_MZ1200          : in  std_logic;
+        MODE_MZ80A           : in  std_logic;
+        MODE_MZ80B           : in  std_logic;
+        MODE_MZ2000          : in  std_logic;
+        MODE_MZ700           : in  std_logic;
+        MODE_MZ_KC           : in  std_logic;
+        MODE_MZ_A            : in  std_logic;
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                           -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);        -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                           -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                           -- HPS Read Enable to FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);       -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0);       -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);       -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                            -- HPS Interrupt.
+    );
+end component;
+
+component mz80b_videoout
+    Port (
+        RST_n                : in  std_logic;                            -- Reset
+        BOOTM                : in  std_logic;                            -- BOOT Mode
+        -- Type of machine we are emulating.
+        MODE_MZ80B           : in  std_logic;
+        MODE_MZ2000          : in  std_logic;
+        -- Type of display to emulate.
+        DISPLAY_NORMAL       : in  std_logic;
+        DISPLAY_NIDECOM      : in  std_logic;
+        DISPLAY_GAL5         : in  std_logic;
+        DISPLAY_COLOUR       : in  std_logic;
+        -- Different operations modes.
+        CONFIG_PCGRAM        : in  std_logic;                            -- PCG Mode Switch, 0 = CGROM, 1 = CGRAM.
+        -- Clocks
+        CK16M                : in  std_logic;                            -- 15.6kHz Dot Clock(16MHz)
+        T80_CLK_n            : in  std_logic;                            -- Z80 Current Clock
+        T80_CLK              : in  std_logic;                            -- Z80 Current Clock Inverted
+        -- CPU Signals
+        T80_A                : in  std_logic_vector(13 downto 0);        -- CPU Address Bus
+        CSV_n                : in  std_logic;                            -- CPU Memory Request(VRAM)
+        CSG_n                : in  std_logic;                            -- CPU Memory Request(GRAM)
+        T80_RD_n             : in  std_logic;                            -- CPU Read Signal
+        T80_WR_n             : in  std_logic;                            -- CPU Write Signal
+        T80_MREQ_n           : in  std_logic;                            -- CPU Memory Request
+        T80_BUSACK_n         : in  std_logic;                            -- CPU Bus Acknowledge
+        T80_WAIT_n           : out std_logic;                            -- CPU Wait Request
+        T80_DI               : in  std_logic_vector(7 downto 0);         -- CPU Data Bus(in)
+        T80_DO               : out std_logic_vector(7 downto 0);         -- CPU Data Bus(out)
+        -- Video Control from outside
+        INV                  : in std_logic;                             -- Reverse mode(8255 PA4)
+        VGATE                : in std_logic;                             -- Video Output Control(8255 PC0)
+        CH80                 : in std_logic;                             -- Text Character Width(Z80PIO A5)
+        -- Video Signals
+        VGATE_n              : in  std_logic;                            -- Video Output Control
+        HBLANK               : out std_logic;                            -- Horizontal Blanking
+        VBLANK               : out std_logic;                            -- Vertical Blanking
+        HSYNC_n              : out std_logic;                            -- Horizontal Sync
+        VSYNC_n              : out std_logic;                            -- Vertical Sync
+        ROUT                 : out std_logic;                            -- Red Output
+        GOUT                 : out std_logic;                            -- Green Output
+        BOUT                 : out std_logic;                            -- Green Output
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);         -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0)         -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                             -- HPS Interrupt.
+    );
+end component;
+
+component cmt
+    Port (
+        RST_n                : in  std_logic;                            -- Reset
+        CLK                  : in  std_logic;                            -- System Clock
+        -- Interrupt
+        INTO                 : out std_logic;                            -- Tape action interrupt
+        -- Z80 Bus
+        ZCLK                 : in  std_logic;
+--      ZA8                  : in  std_logic_vector(7 downto 0);
+--      ZIWR_n               : in  std_logic;
+--      ZDI                  : in  std_logic_vector(7 downto 0);
+--      ZDO                  : out std_logic_vector(7 downto 0);
+        -- Tape signals
+        T_END                : out std_logic;                            -- Sense CMT(Motor on/off)
+        OPEN_n               : in  std_logic;                            -- Open
+        PLAY_n               : in  std_logic;                            -- Play
+        STOP_n               : in  std_logic;                            -- Stop
+        FF_n                 : in  std_logic;                            -- Fast Foward
+        REW_n                : in  std_logic;                            -- Rewind
+        APSS_n               : in  std_logic;                            -- APSS
+        FFREW                : in  std_logic;                            -- FF/REW mode
+        FMOTOR               : in  std_logic;                            -- FF/REW start
+        FLATCH               : in  std_logic;                            -- FF/REW latch
+        WREADY               : out std_logic;                            -- Write enable
+        TREADY               : out std_logic;                            -- Tape exist
+--      EXIN                 : in std_logic;                             -- CMT IN from I/O board
+        RDATA                : out std_logic;                            -- to 8255
+        -- Status Signal
+        SCLK                 : in  std_logic;                            -- Slow Clock(31.25kHz)
+        MZMODE               : in  std_logic;                            -- Hardware Mode
+        DMODE                : in  std_logic                             -- Display Mode
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);         -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                             -- HPS Interrupt.
+    );
+end component;
+
+component mz1e05
+    Port (
+        -- CPU Signals
+        ZRST_n               : in  std_logic;
+        ZCLK                 : in  std_logic;
+        ZADR                 : in  std_logic_vector(7 downto 0);         -- CPU Address Bus(lower)
+        ZRD_n                : in  std_logic;                            -- CPU Read Signal
+        ZWR_n                : in  std_logic;                            -- CPU Write Signal
+        ZIORQ_n              : in  std_logic;                            -- CPU I/O Request
+        ZDI                  : in  std_logic_vector(7 downto 0);         -- CPU Data Bus(in)
+        ZDO                  : out std_logic_vector(7 downto 0);         -- CPU Data Bus(out)
+        SCLK                 : in  std_logic;                            -- Slow Clock
+        -- FD signals
+        DS_n                 : out std_logic_vector(4 downto 1);         -- Drive Select
+        HS                   : out std_logic;                            -- Head Select
+        MOTOR_n              : out std_logic;                            -- Motor On
+        INDEX_n              : in  std_logic;                            -- Index Hole Detect
+        TRACK00              : in  std_logic;                            -- Track 0
+        WPRT_n               : in  std_logic;                            -- Write Protect
+        STEP_n               : out std_logic;                            -- Head Step In/Out
+        DIREC                : out std_logic;                            -- Head Step Direction
+        WGATE_n              : out std_logic;                            -- Write Gate
+        DTCLK                : in  std_logic;                            -- Data Clock
+        FDI                  : in  std_logic_vector(7 downto 0);         -- Read Data
+        FDO                  : out std_logic_vector(7 downto 0)          -- Write Data
+    );
+end component;
+
+-- PDS : needs buffer ram and an interface to HPS to write into buffer memory.
+--component fdunit
+--    Port (
+--        RST_n                : in  std_logic;                            -- Reset
+--        CLK                  : in  std_logic;                            -- System Clock
+--        -- Interrupt
+--        INTO                 : out std_logic;                            -- Step Pulse interrupt
+--        -- FD signals
+--        FCLK                 : in  std_logic;
+--        DS_n                 : in  std_logic_vector(4 downto 1);         -- Drive Select
+--        HS                   : in  std_logic;                            -- Head Select
+--        MOTOR_n              : in  std_logic;                            -- Motor On
+--        INDEX_n              : out std_logic;                            -- Index Hole Detect
+--        TRACK00              : out std_logic;                            -- Track 0
+--        WPRT_n               : out std_logic;                            -- Write Protect
+--        STEP_n               : in  std_logic;                            -- Head Step In/Out
+--        DIREC                : in  std_logic;                            -- Head Step Direction
+--        WG_n                 : in  std_logic;                            -- Write Gate
+--        DTCLK                : out std_logic;                            -- Data Clock
+--        FDI                  : in  std_logic_vector(7 downto 0);         -- Write Data
+--        FDO                  : out std_logic_vector(7 downto 0);         -- Read Data
+--        -- Buffer RAM I/F
+--        BCS_n                : out std_logic;                            -- RAM Request
+--        BADR                 : out std_logic_vector(22 downto 0);        -- RAM Address
+--        BWR_n                : out std_logic;                            -- RAM Write Signal
+--        BDI                  : in  std_logic_vector(7 downto 0);         -- Data Bus Input from RAM
+--        BDO                  : out std_logic_vector(7 downto 0)          -- Data Bus Output to RAM
+--        -- HPS Interface
+--        IOCTL_DOWNLOAD       : in  std_logic;                           -- HPS Downloading to FPGA.
+--        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);        -- Menu index used to upload file.
+--        IOCTL_WR             : in  std_logic;                           -- HPS Write Enable to FPGA.
+--        IOCTL_RD             : in  std_logic;                           -- HPS Read Enable from FPGA.
+--        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);       -- HPS Address in FPGA to write into.
+--        IOCTL_DOUT           : in  std_logic_vector(15 downto 0);       -- HPS Data to be written into FPGA.
+--        IOCTL_DIN            : out std_logic_vector(15 downto 0);       -- HPS Data to be read into HPS.
+--        IOCTL_INTERRUPT      : out std_logic                            -- HPS Interrupt.
+--    );
+--end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    CPU0 : T80se
+    generic map(
+        Mode                 => 0,                                       -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+        T2Write              => 1,                                       -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+        IOWait               => 1                                        -- 0 => Single cycle I/O, 1 => Std I/O cycle
+    )
+    port map (
+        RESET_n              => T80_RST_n,
+        CLK_n                => CK4M,
+        CLKEN                => '1',
+        WAIT_n               => ZWAIT_n,
+        INT_n                => INT_n,
+--        INT_n              => '1',
+        NMI_n                => '1',
+        BUSRQ_n              => BREQ_n,
+        M1_n                 => M1,
+        MREQ_n               => MREQ_n,
+        IORQ_n               => IORQ_n,
+        RD_n                 => RD_n,
+        WR_n                 => T80_WR_n,
+        RFSH_n               => RFSH_n,
+        HALT_n               => open,
+        BUSAK_n              => BAK_n,
+        A                    => T80_A16,
+        DI                   => ZDTI,
+        DO                   => ZDTO
+    );
+
+    PPI0 : i8255 port map (
+        RST                  => T80_RST,
+        CLK                  => CK4M,
+        A                    => T80_A16(1 downto 0),
+        CS                   => CSE0_n,
+        RD                   => RD_n,
+        WR                   => T80_WR_n,
+        DI                   => ZDTO,
+        DO                   => PPI_DO,
+        -- Port
+        PA                   => PPIPA,
+        PB                   => PPIPB,
+        PC                   => PPIPC,
+        -- Mode
+        MODE_MZ80B           => MODE_MZ80B,
+        MODE_MZ2000          => MODE_MZ2000
+    );
+    PPIPB(7)<=PIOPB(7);
+--    WDATA<=PPIPC(7);
+--    REC_n<=PPIPC(6);
+--    WRIT_n<=PPIPC(6);
+--    KINH<=PPIPC(5);
+--    L_FR<=PPIPC(5);
+    BST_n<=PPIPC(3);
+--    NST<=PPIPC(1);
+
+    CMT0 : cmt port map (
+        -- Interrupt
+        INTO                 => IRQ_CMT,                                 -- Tape action interrupt
+        -- Z80 Bus
+        ZCLK                 => CK4M,
+        -- Tape signals
+        T_END                => PPIPB(3),                                -- Sense CMT(Motor on/off)
+        OPEN_n               => PPIPC(4),                                -- Open
+        PLAY_n               => PPIPA(2),                                -- Play
+        STOP_n               => PPIPA(3),                                -- Stop
+        FF_n                 => PPIPA(1),                                -- Fast Foward
+        REW_n                => PPIPA(0),                                -- Rewind
+        APSS_n               => PPIPA(7),                                -- APSS
+        FFREW                => PPIPA(1),                                -- FF/REW mode
+        FMOTOR               => PPIPA(0),                                -- FF/REW start
+        FLATCH               => PPIPC(5),                                -- FF/REW latch
+        WREADY               => PPIPB(4),                                -- Write enable
+        TREADY               => PPIPB(5),                                -- Tape exist
+        RDATA                => PPIPB(6),                                -- to 8255
+        -- Status Signal
+        SCLK                 => CK3125,                                  -- Slow Clock(31.25kHz)
+        MZMODE               => MZMODE,
+        DMODE                => DMODE
+    );
+
+    PIT0 : i8253 port map (
+        RST                  => T80_RST,
+        CLK                  => CK4M,
+        A                    => T80_A16(1 downto 0),
+        DI                   => ZDTO,
+        DO                   => DOPIT,
+        CS                   => CSE4_n,
+        WR                   => T80_WR_n,
+        RD                   => RD_n,
+        CLK0                 => CK3125,
+        GATE0                => RST8253_n,
+        OUT0                 => CASCADE01,
+        CLK1                 => CASCADE01,
+        GATE1                => RST8253_n,
+        OUT1                 => CASCADE12,
+        CLK2                 => CASCADE12,
+        GATE2                => '1',
+        OUT2                 => open
+    );
+
+    PIO0 : z8420 port map (
+        -- System
+        RST_n                => T80_RST_n,                                    -- Only Power On Reset
+        -- Z80 Bus Signals
+        CLK                  => CK4M,
+        BASEL                => T80_A16(1),
+        CDSEL                => T80_A16(0),
+        CE                   => CSE8_n,
+        RD_n                 => RD_n,
+        WR_n                 => T80_WR_n,
+        IORQ_n               => IORQ_n,
+        M1_n                 => M1,
+        DI                   => ZDTO,
+        DO                   => PIO_DO,
+        IEI                  => '1',
+        IEO                  => open,
+--        INT_n              => open,
+        INT_n                => INT_n,
+        -- Port
+        A                    => PIOPA,
+        B                    => PIOPB,
+    );
+
+    KEYS : keymatrix
+        port map (
+            RST_n            => T80_RST_n,
+            CLK              => T80_CLK,                                 -- System clock.
+            -- Operating mode of emulator
+            MZ_MODE_B        => MODE_MZ_B,
+            -- i8255
+            PA               => i8255_PA_O(3 downto 0),
+            PB               => i8255_PB_I,
+            STALL            => i8255_PA_O(4),
+            -- PS/2 Keyboard Data
+            PS2_KEY          => PS2_KEY,                                 -- PS2 Key data.
+            PS2_MOUSE        => PS2_MOUSE,                               -- PS2 Mouse data.
+            -- Type of machine we are emulating.
+            MODE_MZ80K       => MODE_MZ80K,
+            MODE_MZ80C       => MODE_MZ80C,
+            MODE_MZ1200      => MODE_MZ1200,
+            MODE_MZ80A       => MODE_MZ80A,
+            MODE_MZ80B       => MODE_MZ80B,
+            MODE_MZ2000      => MODE_MZ2000,
+            MODE_MZ700       => MODE_MZ700,
+            MODE_MZ_KC       => MODE_MZ_KC,
+            MODE_MZ_A        => MODE_MZ_A,
+            -- HPS Interface
+            IOCTL_DOWNLOAD   => IOCTL_DOWNLOAD,                          -- HPS Downloading to FPGA.
+            IOCTL_INDEX      => IOCTL_INDEX,                             -- Menu index used to upload file.
+            IOCTL_WR         => IOCTL_WR,                                -- HPS Write Enable to FPGA.
+            IOCTL_RD         => IOCTL_RD,                                -- HPS Read Enable from FPGA.
+            IOCTL_ADDR       => IOCTL_ADDR,                              -- HPS Address in FPGA to write into.
+            IOCTL_DOUT       => IOCTL_DOUT,                              -- HPS Data to be written into FPGA.
+            IOCTL_DIN        => IOCTL_DIN_KEY,                           -- HPS Data to be sent to HPS.
+            IOCTL_INTERRUPT  => IOCTL_INTERRUPT                          -- Interrupt to HPS.
+        );
+
+    VIDEO0 : mz80b_videoout Port map (
+        RST                  => T80_RST_n                                -- Reset
+        MZMODE               => MZMODE,                                  -- Hardware Mode
+        DMODE                => DMODE,                                   -- Display Mode
+        -- Clocks
+        CK50M                => CK50M,                                   -- Master Clock(50MHz)
+        CK25M                => CK25M,                                   -- VGA Clock(25MHz)
+        CK16M                => CK16M,                                   -- 15.6kHz Dot Clock(16MHz)
+        CK4M                 => CK4M,                                    -- CPU/CLOCK Clock(4MHz)
+        CK3125               => CK3125,                                  -- Time Base Clock(31.25kHz)
+        -- CPU Signals
+        A                    => T80_A16(13 downto 0),                    -- CPU Address Bus
+        CSV_n                => CSV_n,                                   -- CPU Memory Request(VRAM)
+        CSG_n                => CSG_n,                                   -- CPU Memory Request(GRAM)
+        RD_n                 => RD_n,                                    -- CPU Read Signal
+        WR_n                 => T80_WR_n,                                -- CPU Write Signal
+        MREQ_n               => MREQ_n,                                  -- CPU Memory Request
+        IORQ_n               => IORQ_n,                                  -- CPU I/O Request
+        WAIT_n               => ZWAIT_n,                                 -- CPU Wait Request
+        DI                   => ZDTO,                                    -- CPU Data Bus(in)
+        DO                   => VRAMDO,                                  -- CPU Data Bus(out)
+        -- Video Control from outside
+        INV                  => PPIPA(4),                                -- Reverse mode(8255 PA4)
+        VGATE                => PPIPC(0),                                -- Video Output Control
+        CH80                 => PIOPA(5),
+        -- Video Signals
+        VGATE_n              => VGATE_n,                                 -- Video Output Control
+        HBLANK               => HBLANKi,                                 -- Horizontal Blanking
+        VBLANK               => VBLANKi,                                 -- Vertical Blanking
+        HSYNC_n              => HSYNC_ni,                                -- Horizontal Sync
+        VSYNC_n              => VSYNC_ni,                                -- Vertical Sync
+        ROUT                 => Ri,                                      -- Red Output
+        GOUT                 => Gi,                                      -- Green Output
+        BOUT                 => Bi,                                      -- Blue Output
+        HBLANK               => HBLANKi,                                 -- Horizontal Blanking
+        VBLANK               => VBLANKi,                                 -- Vertical Blanking
+        -- Control Signal
+        BOOTM                => BOOTM,                                   -- BOOT Mode
+        BACK                 => BAK_n                                    -- Z80 Bus Acknowlegde
+    );
+
+PDS :- Need BOOTM
+    
+    FDIF0 : mz1e05 Port map(
+        -- CPU Signals
+        ZRST_n               => T80_RST_n,
+        ZCLK                 => CK4M,
+        ZADR                 => T80_A16(7 downto 0),                     -- CPU Address Bus(lower)
+        ZRD_n                => RD_n,                                    -- CPU Read Signal
+        ZWR_n                => T80_WR_n,                                -- CPU Write Signal
+        ZIORQ_n              => IORQ_n,                                  -- CPU I/O Request
+        ZDI                  => ZDTO,                                    -- CPU Data Bus(in)
+        ZDO                  => DOFDC,                                   -- CPU Data Bus(out)
+        SCLK                 => CK3125,                                  -- Slow Clock
+        -- FD signals
+        DS_n                 => DS,                                      -- Drive Select
+        HS                   => HS,                                      -- Head Select
+        MOTOR_n              => MOTOR_n,                                 -- Motor On
+        INDEX_n              => INDEX_n,                                 -- Index Hole Detect
+        TRACK00              => TRACK00_n,                               -- Track 0
+        WPRT_n               => WPRT_n,                                  -- Write Protect
+        STEP_n               => STEP_n,                                  -- Head Step In/Out
+        DIREC                => DIREC,                                   -- Head Step Direction
+        WGATE_n              => WGATE_n,                                 -- Write Gate
+        DTCLK                => DTCLK,                                   -- Data Clock
+        FDI                  => FDI,                                     -- Read Data
+        FDO                  => FDO                                      -- Write Data
+    );
+
+--    FDU0 : fdunit Port map(
+--        -- Interrupt
+--        INTO                 => IRQ_FDD,                                 -- Step Pulse interrupt
+--        -- FD signals
+--        FCLK                 => CK4M,
+--        DS_n                 => DS,                                      -- Drive Select
+--        HS                   => HS,                                      -- Head Select
+--        MOTOR_n              => MOTOR_n,                                 -- Motor On
+--        INDEX_n              => INDEX_n,                                 -- Index Hole Detect
+--        TRACK00              => TRACK00_n,                               -- Track 0
+--        WPRT_n               => WPRT_n,                                  -- Write Protect
+--        STEP_n               => STEP_n,                                  -- Head Step In/Out
+--        DIREC                => DIREC,                                   -- Head Step Direction
+--        WG_n                 => WGATE_n,                                 -- Write Gate
+--        DTCLK                => DTCLK,                                   -- Data Clock
+--        FDO                  => FDI,                                     -- Read Data
+--        FDI                  => FDO,                                     -- Write Data
+--        -- Buffer RAM I/F
+--        BCS_n                => BCS_n,                                   -- RAM Request
+--        BADR                 => BADR,                                    -- RAM Address
+--        BWR_n                => BWR_n,                                   -- RAM Write Signal
+--        BDI                  => BDI,                                     -- Data Bus Input from RAM
+--        BDO                  => BDO                                      -- Data Bus Output to RAM
+--    );
+
+    --
+    -- Control Signals
+    --
+    IWR            <= IORQ_n or T80_WR_n;
+
+    --
+    -- Data Bus
+    --
+    ZDTI           <= PPI_DO or DOPIT or PIO_DO or VRAMDO or RAMDI or DOFDC;
+    RAMDI          <= T80_DO when RD_n='0' and MREQ_n='0' and CSV_n='1' and CSG_n='1' else (others=>'0');
+--              HSKDI when CSHSK='0' else T80_DO;
+
+    --
+    -- Chip Select
+    --
+    CSV_n          <= '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 12)="1101" and MREQ_n='0' and PIOPA(6)='0' else        -- $D000 - $DFFF (80B)
+                      '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 12)="0101" and MREQ_n='0' and PIOPA(6)='1' else        -- $5000 - $5FFF (80B)
+                      '0' when MZMODE='1' and PIOPA(7)='1' and T80_A16(15 downto 12)="1101" and MREQ_n='0' and PIOPA(6)='1' else '1';   -- $D000 - $DFFF (2000)
+    CSG_n          <= '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 13)="111" and MREQ_n='0' and PIOPA(6)='0' else         -- $E000 - $FFFF (80B)
+                      '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 13)="011" and MREQ_n='0' and PIOPA(6)='1' else         -- $6000 - $7FFF (80B)
+                      '0' when MZMODE='1' and PIOPA(7)='1' and T80_A16(15 downto 14)="11" and MREQ_n='0' and PIOPA(6)='0' else '1';     -- $C000 - $FFFF (2000)
+    CSHSK          <= '0' when T80_A16(7 downto 3)="10001" and IORQ_n='0' else '1';                                                     -- HandShake Port
+    CSE0_n         <= '0' when T80_A16(7 downto 2)="111000" and IORQ_n='0' else '1';                                                    -- 8255
+    CSE4_n         <= '0' when T80_A16(7 downto 2)="111001" and IORQ_n='0' else '1';                                                    -- 8253
+    CSE8_n         <= '0' when T80_A16(7 downto 2)="111010" and IORQ_n='0' else '1';                                                    -- PIO
+
+    --
+    -- Video Output.
+    --
+    HSYNC_n        <= HSYNC_ni;
+    VSYNC_n        <= VSYNC_ni;
+    R              <= Ri;
+    G              <= Gi;
+    B              <= Bi;
+    VBLANK         <= VBLANKi;
+    HBLANK         <= HBLANKi;
+    VBLANKi        <= PPIPB(0);                                -- Vertical Blanking
+
+    --
+    -- Ports
+    --
+    CSRAM_n        <= MREQ_n when CSV_n='1' and CSG_n='1' and RFSH_n='1' else '1';
+    T80_DI         <= ZDTO;
+    ZWR_n          <= T80_WR_n;
+
+    --
+    -- Misc
+    --
+    MZMODE         <= SW(9);
+    DMODE          <= SW(8);
+    T80_RST        <= not T80_RST_n;
+
+    RST8253_n      <= '0' when T80_A16(7 downto 2)="111100" and IWR='0' else '1';
+
+    GPIO1_D(15)<=PPIPC(2);    -- Sound Output
+    GPIO1_D(14)<=PPIPC(2);
+
+end rtl;
diff --git a/mz80b/old/ScanConv.vhd b/mz80b/old/ScanConv.vhd
new file mode 100644
index 0000000..c0dacc6
--- /dev/null
+++ b/mz80b/old/ScanConv.vhd
@@ -0,0 +1,133 @@
+--
+-- ScanConv.vhd
+--
+-- Up Scan Converter (15.6kHz->VGA)
+-- for MZ-80B on FPGA
+--
+-- Nibbles Lab. 2013
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity ScanConv is
+	Port (
+		CK16M : in STD_LOGIC;		-- MZ Dot Clock
+		CK25M : in STD_LOGIC;		-- VGA Dot Clock
+		RI    : in STD_LOGIC;		-- Red Input
+		GI    : in STD_LOGIC;		-- Green Input
+		BI    : in STD_LOGIC;		-- Blue Input
+		HSI   : in STD_LOGIC;		-- H-Sync Input(MZ,15.6kHz)
+		RO    : out STD_LOGIC;		-- Red Output
+		GO    : out STD_LOGIC;		-- Green Output
+		BO    : out STD_LOGIC;		-- Blue Output
+		HSO   : out STD_LOGIC);		-- H-Sync Output(VGA, 31kHz)
+end ScanConv;
+
+architecture RTL of ScanConv is
+
+--
+-- Signals
+--
+signal CTR12M5 : std_logic_vector(10 downto 0);		-- 
+--signal CLK12M5 : std_logic;								-- Divider for VGA Sync Signal
+signal TS : std_logic_vector(9 downto 0);				-- Half of Horizontal
+signal OCTR : std_logic_vector(9 downto 0);			-- Buffer Output Pointer
+signal ICTR : std_logic_vector(9 downto 0);			-- Buffer Input Pointer
+signal Hi : std_logic_vector(5 downto 0);				-- Shift Register for H-Sync Detect(VGA)
+signal Si : std_logic_vector(5 downto 0);				-- Shift Register for H-Sync Detect(15.6kHz)
+signal DO : std_logic_vector(2 downto 0);
+
+--
+-- Components
+--
+component linebuf
+	PORT
+	(
+		data			: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		rdaddress	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		rdclock		: IN STD_LOGIC ;
+		wraddress	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		wrclock		: IN STD_LOGIC  := '1';
+		wren			: IN STD_LOGIC  := '0';
+		q				: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+end component;
+
+begin
+
+	--
+	-- Instantiation
+	--
+	SBUF : linebuf PORT MAP (
+		data	 		=> RI&GI&BI,		-- Input RGB
+		rdaddress	=> OCTR,				-- Buffer Output Counter
+		rdclock	 	=> CK25M,			-- Dot Clock(VGA)
+		wraddress	=> ICTR,				-- Buffer Input Counter
+		wrclock	 	=> CK16M,			-- Dot Clock(15.6kHz)
+		wren	 		=> '1',				-- Write only
+		q	 			=> DO					-- Output RGB
+	);
+
+	--
+	-- Buffer Input
+	--
+	process( CK16M ) begin
+		if CK16M'event and CK16M='1' then
+
+			-- Filtering HSI
+			Si<=Si(4 downto 0)&HSI;
+
+			-- Counter start
+			if Si="111000" then
+				ICTR<="1110000100";	-- X"3B8";
+			else
+				ICTR<=ICTR+'1';
+			end if;
+
+		end if;
+	end process;
+
+	--
+	-- Buffer and Signal Output
+	--
+	process( CK25M ) begin
+		if CK25M'event and CK25M='1' then
+
+			-- Filtering HSI
+			Hi<=Hi(4 downto 0)&HSI;
+
+			-- Detect HSYNC
+			if Hi="111000" then
+				CTR12M5<=(others=>'0');
+				TS<=CTR12M5(10 downto 1);	-- Half of Horizontal
+				OCTR<=(others=>'0');
+			elsif OCTR=TS then
+				OCTR<=(others=>'0');
+				CTR12M5<=CTR12M5+'1';
+			else
+				OCTR<=OCTR+'1';
+				CTR12M5<=CTR12M5+'1';
+			end if;
+
+			-- Horizontal Sync genarate
+			if OCTR=0 then
+				HSO<='0';
+			elsif OCTR=96 then
+				HSO<='1';
+			end if;
+
+		end if;
+	end process;
+
+	--
+	-- Output
+	--
+	RO<=DO(2);
+	GO<=DO(1);
+	BO<=DO(0);
+
+end RTL;
+
diff --git a/mz80b/old/T80/T80.vhd b/mz80b/old/T80/T80.vhd
new file mode 100644
index 0000000..0912e3d
--- /dev/null
+++ b/mz80b/old/T80/T80.vhd
@@ -0,0 +1,1094 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+	signal XYbit_undoc          : std_logic;
+
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			XY_State    => XY_State,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write,
+			XYbit_undoc => XYbit_undoc);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+				if XYbit_undoc='1' then
+					DO <= ALU_Q;
+				end if;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			if XYbit_undoc='1' then
+				BusA <= DI_Reg;
+				BusB <= DI_Reg;
+			end if;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/mz80b/old/T80/T8080se.vhd b/mz80b/old/T80/T8080se.vhd
new file mode 100644
index 0000000..b18b47a
--- /dev/null
+++ b/mz80b/old/T80/T8080se.vhd
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT                     : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/mz80b/old/T80/T80_ALU.vhd b/mz80b/old/T80/T80_ALU.vhd
new file mode 100644
index 0000000..95c98da
--- /dev/null
+++ b/mz80b/old/T80/T80_ALU.vhd
@@ -0,0 +1,371 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
+	process (Carry_v, Carry7_v, Q_v)
+	begin
+		if(Mode=2) then
+			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
+			OverFlow_v <= Carry_v xor Carry7_v;
+		end if;
+	end process;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/mz80b/old/T80/T80_MCode.vhd b/mz80b/old/T80/T80_MCode.vhd
new file mode 100644
index 0000000..1d40210
--- /dev/null
+++ b/mz80b/old/T80/T80_MCode.vhd
@@ -0,0 +1,2029 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		XY_State                : in std_logic_vector(1 downto 0);
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic;
+		XYbit_undoc             : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+--	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_state)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+		XYbit_undoc <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  ALU_Op <= "1000";
+					  Read_To_Reg <= '1';
+					  Save_ALU <= '1';
+					end if;
+				else
+				-- R/S (IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1000";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+
+
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+					  ALU_Op <= "1001";
+					end if;
+				else
+				-- BIT b,(IX+d), undocumented
+					MCycles <= "010";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1001";
+						TStates <= "100";
+					when others => null;
+					end case;
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  ALU_Op <= "1010";
+					  Read_To_Reg <= '1';
+					  Save_ALU <= '1';
+					end if;
+				else
+				-- SET b,(IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1010";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  ALU_Op <= "1011";
+					  Read_To_Reg <= '1';
+					  Save_ALU <= '1';
+					end if;
+				else
+				-- RES b,(IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1011";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+				
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/mz80b/old/T80/T80_Pack.vhd b/mz80b/old/T80/T80_Pack.vhd
new file mode 100644
index 0000000..6904b66
--- /dev/null
+++ b/mz80b/old/T80/T80_Pack.vhd
@@ -0,0 +1,220 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		XY_State                : in  std_logic_vector(1 downto 0);
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic;
+		XYbit_undoc             : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/mz80b/old/T80/T80_Reg.vhd b/mz80b/old/T80/T80_Reg.vhd
new file mode 100644
index 0000000..1c0f263
--- /dev/null
+++ b/mz80b/old/T80/T80_Reg.vhd
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/mz80b/old/T80/T80_RegX.vhd b/mz80b/old/T80/T80_RegX.vhd
new file mode 100644
index 0000000..ebeee09
--- /dev/null
+++ b/mz80b/old/T80/T80_RegX.vhd
@@ -0,0 +1,176 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers for Xilinx Select RAM
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Removed UNISIM library and added componet declaration
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	component RAM16X1D
+		port(
+			DPO         : out std_ulogic;
+			SPO         : out std_ulogic;
+			A0          : in std_ulogic;
+			A1          : in std_ulogic;
+			A2          : in std_ulogic;
+			A3          : in std_ulogic;
+			D           : in std_ulogic;
+			DPRA0       : in std_ulogic;
+			DPRA1       : in std_ulogic;
+			DPRA2       : in std_ulogic;
+			DPRA3       : in std_ulogic;
+			WCLK        : in std_ulogic;
+			WE          : in std_ulogic);
+	end component;
+
+	signal      ENH             : std_logic;
+	signal      ENL             : std_logic;
+
+begin
+
+	ENH <= CEN and WEH;
+	ENL <= CEN and WEL;
+
+	bG1: for I in 0 to 7 generate
+	begin
+		Reg1H : RAM16X1D
+			port map(
+			DPO => DOBH(i),
+			SPO => DOAH(i),
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIH(i),
+			DPRA0 => AddrB(0),
+			DPRA1 => AddrB(1),
+			DPRA2 => AddrB(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENH);
+		Reg1L : RAM16X1D
+			port map(
+			DPO => DOBL(i),
+			SPO => DOAL(i),
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIL(i),
+			DPRA0 => AddrB(0),
+			DPRA1 => AddrB(1),
+			DPRA2 => AddrB(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENL);
+		Reg2H : RAM16X1D
+			port map(
+			DPO => DOCH(i),
+			SPO => open,
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIH(i),
+			DPRA0 => AddrC(0),
+			DPRA1 => AddrC(1),
+			DPRA2 => AddrC(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENH);
+		Reg2L : RAM16X1D
+			port map(
+			DPO => DOCL(i),
+			SPO => open,
+			A0 => AddrA(0),
+			A1 => AddrA(1),
+			A2 => AddrA(2),
+			A3 => '0',
+			D => DIL(i),
+			DPRA0 => AddrC(0),
+			DPRA1 => AddrC(1),
+			DPRA2 => AddrC(2),
+			DPRA3 => '0',
+			WCLK => Clk,
+			WE => ENL);
+	end generate;
+
+end;
diff --git a/mz80b/old/T80/T80a.vhd b/mz80b/old/T80/T80a.vhd
new file mode 100644
index 0000000..75636aa
--- /dev/null
+++ b/mz80b/old/T80/T80a.vhd
@@ -0,0 +1,262 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core, asynchronous top level
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed interrupt cycle
+--
+--      0235 : Updated for T80 interface change
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80a is
+	generic(
+		Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		D                       : inout std_logic_vector(7 downto 0)
+	);
+end T80a;
+
+architecture rtl of T80a is
+
+	signal CEN                  : std_logic;
+	signal Reset_s              : std_logic;
+	signal IntCycle_n   : std_logic;
+	signal IORQ                 : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal MREQ                 : std_logic;
+	signal MReq_Inhibit : std_logic;
+	signal Req_Inhibit  : std_logic;
+	signal RD                   : std_logic;
+	signal MREQ_n_i             : std_logic;
+	signal IORQ_n_i             : std_logic;
+	signal RD_n_i               : std_logic;
+	signal WR_n_i               : std_logic;
+	signal RFSH_n_i             : std_logic;
+	signal BUSAK_n_i    : std_logic;
+	signal A_i                  : std_logic_vector(15 downto 0);
+	signal DO                   : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector (7 downto 0);        -- Input synchroniser
+	signal Wait_s               : std_logic;
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+
+begin
+
+	CEN <= '1';
+
+	BUSAK_n <= BUSAK_n_i;
+	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
+	RD_n_i <= not RD or Req_Inhibit;
+
+	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
+	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
+	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
+	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
+	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
+	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
+	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			Reset_s <= '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			Reset_s <= '1';
+		end if;
+	end process;
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 1)
+		port map(
+			CEN => CEN,
+			M1_n => M1_n,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => RFSH_n_i,
+			HALT_n => HALT_n,
+			WAIT_n => Wait_s,
+			INT_n => INT_n,
+			NMI_n => NMI_n,
+			RESET_n => Reset_s,
+			BUSRQ_n => BUSRQ_n,
+			BUSAK_n => BUSAK_n_i,
+			CLK_n => CLK_n,
+			A => A_i,
+			DInst => D,
+			DI => DI_Reg,
+			DO => DO,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '0' then
+			Wait_s <= WAIT_n;
+			if TState = "011" and BUSAK_n_i = '1' then
+				DI_Reg <= to_x01(D);
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			WR_n_i <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			WR_n_i <= '1';
+			if TState = "001" then      -- To short for IO writes !!!!!!!!!!!!!!!!!!!
+				WR_n_i <= not Write;
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			Req_Inhibit <= '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if MCycle = "001" and TState = "010" then
+				Req_Inhibit <= '1';
+			else
+				Req_Inhibit <= '0';
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			MReq_Inhibit <= '0';
+		elsif CLK_n'event and CLK_n = '0' then
+			if MCycle = "001" and TState = "010" then
+				MReq_Inhibit <= '1';
+			else
+				MReq_Inhibit <= '0';
+			end if;
+		end if;
+	end process;
+
+	process(Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			RD <= '0';
+			IORQ_n_i <= '1';
+			MREQ <= '0';
+		elsif CLK_n'event and CLK_n = '0' then
+
+			if MCycle = "001" then
+				if TState = "001" then
+					RD <= IntCycle_n;
+					MREQ <= IntCycle_n;
+					IORQ_n_i <= IntCycle_n;
+				end if;
+				if TState = "011" then
+					RD <= '0';
+					IORQ_n_i <= '1';
+					MREQ <= '1';
+				end if;
+				if TState = "100" then
+					MREQ <= '0';
+				end if;
+			else
+				if TState = "001" and NoRead = '0' then
+					RD <= not Write;
+					IORQ_n_i <= not IORQ;
+					MREQ <= not IORQ;
+				end if;
+				if TState = "011" then
+					RD <= '0';
+					IORQ_n_i <= '1';
+					MREQ <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/mz80b/old/T80/T80se.vhd b/mz80b/old/T80/T80se.vhd
new file mode 100644
index 0000000..1b0cb9b
--- /dev/null
+++ b/mz80b/old/T80/T80se.vhd
@@ -0,0 +1,192 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0240
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0235 : First release
+--
+--      0236 : Added T2Write generic
+--
+--      0237 : Fixed T2Write with wait state
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80se is
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0;  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+		IOWait : integer := 1   -- 0 => Single cycle I/O, 1 => Std I/O cycle
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CLKEN           : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0)
+	);
+end T80se;
+
+architecture rtl of T80se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead       : std_logic;
+	signal Write        : std_logic;
+	signal IORQ         : std_logic;
+	signal DI_Reg       : std_logic_vector(7 downto 0);
+	signal MCycle       : std_logic_vector(2 downto 0);
+	signal TState       : std_logic_vector(2 downto 0);
+
+begin
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => IOWait)
+		port map(
+			CEN        => CLKEN,
+			M1_n       => M1_n,
+			IORQ       => IORQ,
+			NoRead     => NoRead,
+			Write      => Write,
+			RFSH_n     => RFSH_n,
+			HALT_n     => HALT_n,
+			WAIT_n     => Wait_n,
+			INT_n      => INT_n,
+			NMI_n      => NMI_n,
+			RESET_n    => RESET_n,
+			BUSRQ_n    => BUSRQ_n,
+			BUSAK_n    => BUSAK_n,
+			CLK_n      => CLK_n,
+			A          => A,
+			DInst      => DI,
+			DI         => DI_Reg,
+			DO         => DO,
+			MC         => MCycle,
+			TS         => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			if CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and Wait_n = '0') then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					end if;
+				end if;
+				if TState = "010" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/mz80b/old/T80/T80sed.vhd b/mz80b/old/T80/T80sed.vhd
new file mode 100644
index 0000000..0c28ec2
--- /dev/null
+++ b/mz80b/old/T80/T80sed.vhd
@@ -0,0 +1,179 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0238
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0235 : First release
+--
+--      0236 : Added T2Write generic
+--
+--      0237 : Fixed T2Write with wait state
+--
+--      0238 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80sed is
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CLKEN           : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0)
+	);
+end T80sed;
+
+architecture rtl of T80sed is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead       : std_logic;
+	signal Write        : std_logic;
+	signal IORQ         : std_logic;
+	signal DI_Reg       : std_logic_vector(7 downto 0);
+	signal MCycle       : std_logic_vector(2 downto 0);
+	signal TState       : std_logic_vector(2 downto 0);
+
+begin
+
+	u0 : T80
+		generic map(
+			Mode      => 0,
+			IOWait    => 1)
+		port map(
+			CEN        => CLKEN,
+			M1_n       => M1_n,
+			IORQ       => IORQ,
+			NoRead     => NoRead,
+			Write      => Write,
+			RFSH_n     => RFSH_n,
+			HALT_n     => HALT_n,
+			WAIT_n     => Wait_n,
+			INT_n      => INT_n,
+			NMI_n      => NMI_n,
+			RESET_n    => RESET_n,
+			BUSRQ_n    => BUSRQ_n,
+			BUSAK_n    => BUSAK_n,
+			CLK_n      => CLK_n,
+			A          => A,
+			DInst      => DI,
+			DI         => DI_Reg,
+			DO         => DO,
+			MC         => MCycle,
+			TS         => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			if CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and Wait_n = '0') then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				else
+					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+						if ((TState = "001") or (TState = "010")) and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+				end if;
+				if TState = "010" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/mz80b/old/cgrom.qip b/mz80b/old/cgrom.qip
new file mode 100644
index 0000000..b4355d1
--- /dev/null
+++ b/mz80b/old/cgrom.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cgrom.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cgrom_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cgrom.cmp"]
diff --git a/mz80b/old/cgrom.vhd b/mz80b/old/cgrom.vhd
new file mode 100644
index 0000000..980fe80
--- /dev/null
+++ b/mz80b/old/cgrom.vhd
@@ -0,0 +1,198 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: cgrom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY cgrom IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		rdclock		: IN STD_LOGIC ;
+		wraddress		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		wrclock		: IN STD_LOGIC  := '1';
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END cgrom;
+
+
+ARCHITECTURE SYN OF cgrom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_b => "NONE",
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		numwords_b => 2048,
+		operation_mode => "DUAL_PORT",
+		outdata_aclr_b => "NONE",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 11,
+		widthad_b => 11,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => wraddress,
+		clock0 => wrclock,
+		data_a => data,
+		wren_a => wren,
+		address_b => rdaddress,
+		clock1 => rdclock,
+		q_b => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "font.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
+-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+-- Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
+-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
+-- Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/mz80b/old/dpram1kr.qip b/mz80b/old/dpram1kr.qip
new file mode 100644
index 0000000..97c7842
--- /dev/null
+++ b/mz80b/old/dpram1kr.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "11.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dpram1kr.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram1kr_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram1kr.cmp"]
diff --git a/mz80b/old/dpram1kr.vhd b/mz80b/old/dpram1kr.vhd
new file mode 100644
index 0000000..df26995
--- /dev/null
+++ b/mz80b/old/dpram1kr.vhd
@@ -0,0 +1,234 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: dpram1kr.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2011 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram1kr IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclock		: IN STD_LOGIC ;
+		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wrclock		: IN STD_LOGIC  := '1';
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END dpram1kr;
+
+
+ARCHITECTURE SYN OF dpram1kr IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_b		: STRING;
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			clock1	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_b => "NONE",
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		numwords_b => 256,
+		operation_mode => "DUAL_PORT",
+		outdata_aclr_b => "NONE",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 8,
+		widthad_b => 8,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => wraddress,
+		clock0 => wrclock,
+		data_a => data,
+		wren_a => wren,
+		address_b => rdaddress,
+		clock1 => rdclock,
+		q_b => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./logic/kmap_80c.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
+-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+-- Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
+-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
+-- Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/mz80b/old/dpram2k.qip b/mz80b/old/dpram2k.qip
new file mode 100644
index 0000000..3e93936
--- /dev/null
+++ b/mz80b/old/dpram2k.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dpram2k.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram2k_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram2k.cmp"]
diff --git a/mz80b/old/dpram2k.vhd b/mz80b/old/dpram2k.vhd
new file mode 100644
index 0000000..11002b4
--- /dev/null
+++ b/mz80b/old/dpram2k.vhd
@@ -0,0 +1,270 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: dpram2k.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram2k IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END dpram2k;
+
+
+ARCHITECTURE SYN OF dpram2k IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			clock1	: IN STD_LOGIC ;
+			data_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_b	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		numwords_b => 2048,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => 11,
+		widthad_b => 11,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		clock0 => clock_a,
+		wren_a => wren_a,
+		address_b => address_b,
+		clock1 => clock_b,
+		data_b => data_b,
+		wren_b => wren_b,
+		address_a => address_a,
+		data_a => data_a,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "vramtest0.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
+-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/mz80b/old/keymatrix.vhd b/mz80b/old/keymatrix.vhd
new file mode 100644
index 0000000..c6c78cd
--- /dev/null
+++ b/mz80b/old/keymatrix.vhd
@@ -0,0 +1,203 @@
+--
+-- keymatrix.vhd
+--
+-- Convert from PS/2 key-matrix to MZ-80B/2000 key-matrix module
+-- for MZ-80B on FPGA
+--
+-- Nibbles Lab. 2005-2014
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--  Uncomment the following lines to use the declarations that are
+--  provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity keymatrix is
+	Port (
+		-- i8255/PIO
+		ZRST_x : in std_logic;
+		STROBE : in std_logic_vector(3 downto 0);
+		STALL	 : in std_logic;
+		KDATA	 : out std_logic_vector(7 downto 0);
+		-- PS/2 Keyboard Data
+		KCLK  : in std_logic;								-- Key controller base clock
+		KBEN  : in std_logic;								-- PS/2 Keyboard Data Valid
+		KBDT  : in std_logic_vector(7 downto 0);		-- PS/2 Keyboard Data
+		-- for Debug
+		LDDAT : out std_logic_vector(7 downto 0);
+		-- Avalon Bus
+		RRST_x : in std_logic;								-- NiosII Reset
+		RCLK	 : in std_logic;								-- NiosII Clock
+		RADR	 : in std_logic_vector(15 downto 0);	-- NiosII Address Bus
+		RCS_x	 : in std_logic;								-- NiosII Read Signal
+		RWE_x	 : in std_logic;								-- NiosII Write Signal
+		RDI	 : in std_logic_vector(7 downto 0);		-- NiosII Data Bus(in)
+		RDO	 : out std_logic_vector(7 downto 0)		-- NiosII Data Bus(out)
+	);
+end keymatrix;
+
+architecture Behavioral of keymatrix is
+
+--
+-- prefix flag
+--
+signal FLGF0 : std_logic;
+signal FLGE0 : std_logic;
+--
+-- MZ-series matrix registers
+--
+signal SCAN00 : std_logic_vector(7 downto 0);
+signal SCAN01 : std_logic_vector(7 downto 0);
+signal SCAN02 : std_logic_vector(7 downto 0);
+signal SCAN03 : std_logic_vector(7 downto 0);
+signal SCAN04 : std_logic_vector(7 downto 0);
+signal SCAN05 : std_logic_vector(7 downto 0);
+signal SCAN06 : std_logic_vector(7 downto 0);
+signal SCAN07 : std_logic_vector(7 downto 0);
+signal SCAN08 : std_logic_vector(7 downto 0);
+signal SCAN09 : std_logic_vector(7 downto 0);
+signal SCAN10 : std_logic_vector(7 downto 0);
+signal SCAN11 : std_logic_vector(7 downto 0);
+signal SCAN12 : std_logic_vector(7 downto 0);
+signal SCAN13 : std_logic_vector(7 downto 0);
+signal SCAN14 : std_logic_vector(7 downto 0);
+signal SCANLL : std_logic_vector(7 downto 0);
+--
+-- Key code exchange table
+--
+signal MTEN : std_logic_vector(3 downto 0);
+signal MTDT : std_logic_vector(7 downto 0);
+signal F_KBDT : std_logic_vector(7 downto 0);
+--
+-- Backdoor Access
+--
+signal RWEN : std_logic;
+signal RCSK_x : std_logic;
+
+--
+-- Components
+--
+component dpram1kr
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclock		: IN STD_LOGIC ;
+		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wrclock		: IN STD_LOGIC  := '1';
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
+
+begin
+
+	--
+	-- Instantiation
+	--
+	MAP0 : dpram1kr PORT MAP (
+		data	 => RDI,
+		rdaddress	 => F_KBDT,
+		rdclock	 => KCLK,
+		wraddress	 => RADR(7 downto 0),
+		wrclock	 => RCLK,
+		wren	 => RWEN,
+		q	 => MTDT
+	);
+
+	--
+	-- Convert
+	--
+	process( ZRST_x, KCLK ) begin
+		if ZRST_x='0' then
+			SCAN00<=(others=>'0');
+			SCAN01<=(others=>'0');
+			SCAN02<=(others=>'0');
+			SCAN03<=(others=>'0');
+			SCAN04<=(others=>'0');
+			SCAN05<=(others=>'0');
+			SCAN06<=(others=>'0');
+			SCAN07<=(others=>'0');
+			SCAN08<=(others=>'0');
+			SCAN09<=(others=>'0');
+			SCAN10<=(others=>'0');
+			SCAN11<=(others=>'0');
+			SCAN12<=(others=>'0');
+			SCAN13<=(others=>'0');
+			SCAN14<=(others=>'0');
+			FLGF0<='0';
+			FLGE0<='0';
+			MTEN<=(others=>'0');
+			F_KBDT<=(others=>'1');
+		elsif KCLK'event and KCLK='1' then
+			MTEN<=MTEN(2 downto 0)&KBEN;
+			if KBEN='1' then
+				case KBDT is
+					when X"AA" => F_KBDT<=X"EF";
+					when X"F0" => FLGF0<='1'; F_KBDT<=X"EF";
+					when X"E0" => FLGE0<='1'; F_KBDT<=X"EF";
+					when others =>  F_KBDT(6 downto 0)<=KBDT(6 downto 0); F_KBDT(7)<=FLGE0 or KBDT(7); FLGE0<='0';
+				end case;
+			end if;
+
+			if MTEN(3)='1' then
+				case MTDT(7 downto 4) is								 
+					when "0000" => SCAN00(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "0001" => SCAN01(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "0010" => SCAN02(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "0011" => SCAN03(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "0100" => SCAN04(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "0101" => SCAN05(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "0110" => SCAN06(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "0111" => SCAN07(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "1000" => SCAN08(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "1001" => SCAN09(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "1010" => SCAN10(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "1011" => SCAN11(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "1100" => SCAN12(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "1101" => SCAN13(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+					when "1110" => SCAN14(conv_integer(MTDT(2 downto 0)))<=not FLGF0;
+					when others => SCAN14(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
+				end case;
+			end if;
+		end if;
+	end process;
+
+	STROBE_L : for I in 0 to 7 generate
+		SCANLL(I)<=SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I)
+				  or SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I)
+				  or SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I);
+	end generate STROBE_L;
+
+	--
+	-- response from key access
+	--
+	KDATA<=(not SCANLL) when STALL='0' else
+			 (not SCAN00) when STROBE="0000" else
+			 (not SCAN01) when STROBE="0001" else
+			 (not SCAN02) when STROBE="0010" else
+			 (not SCAN03) when STROBE="0011" else
+			 (not SCAN04) when STROBE="0100" else
+			 (not SCAN05) when STROBE="0101" else
+			 (not SCAN06) when STROBE="0110" else
+			 (not SCAN07) when STROBE="0111" else
+			 (not SCAN08) when STROBE="1000" else
+			 (not SCAN09) when STROBE="1001" else
+			 (not SCAN10) when STROBE="1010" else
+			 (not SCAN11) when STROBE="1011" else
+			 (not SCAN12) when STROBE="1100" else
+			 (not SCAN13) when STROBE="1101" else (others=>'1');
+
+	--
+	-- NiosII access
+	--
+	RCSK_x<='0' when RADR(15 downto 8)="11000000" else '1';
+	RWEN<=not(RWE_x or RCSK_x);
+	RDO<=(others=>'0');
+
+end Behavioral;
diff --git a/mz80b/old/linebuf.qip b/mz80b/old/linebuf.qip
new file mode 100644
index 0000000..2318f1c
--- /dev/null
+++ b/mz80b/old/linebuf.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "linebuf.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf.cmp"]
diff --git a/mz80b/old/linebuf.vhd b/mz80b/old/linebuf.vhd
new file mode 100644
index 0000000..f2c2214
--- /dev/null
+++ b/mz80b/old/linebuf.vhd
@@ -0,0 +1,232 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: linebuf.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY linebuf IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		rdclock		: IN STD_LOGIC ;
+		wraddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		wrclock		: IN STD_LOGIC  := '1';
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+END linebuf;
+
+
+ARCHITECTURE SYN OF linebuf IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_b		: STRING;
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+			clock1	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(2 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_b => "NONE",
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		numwords_b => 1024,
+		operation_mode => "DUAL_PORT",
+		outdata_aclr_b => "NONE",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 10,
+		widthad_b => 10,
+		width_a => 3,
+		width_b => 3,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => wraddress,
+		clock0 => wrclock,
+		data_a => data,
+		wren_a => wren,
+		address_b => rdaddress,
+		clock1 => rdclock,
+		q_b => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "3072"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "buftest.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL "data[2..0]"
+-- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
+-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
+-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
+-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 3 0 data 0 0 3 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 3 0 @q_b 0 0 3 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/mz80b/old/mz80b.vhd b/mz80b/old/mz80b.vhd
new file mode 100644
index 0000000..e910ae2
--- /dev/null
+++ b/mz80b/old/mz80b.vhd
@@ -0,0 +1,544 @@
+--
+-- mz80b.vhd
+--
+-- SHARP MZ-80B/2000 compatible logic, top module
+-- for Altera DE0
+--
+-- Nibbles Lab. 2013-2014
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity mz80b is
+  port(
+		--------------------				Clock Input					 	----------------------	 
+		CLOCK_50		: in std_logic;								--	50 MHz
+		CLOCK_50_2	: in std_logic;								--	50 MHz
+		--------------------				Push Button						----------------------------
+		BUTTON		: in std_logic_vector(2 downto 0);		--	Pushbutton[2:0]
+		--------------------				DPDT Switch						----------------------------
+		SW				: in std_logic_vector(9 downto 0);		--	Toggle Switch[9:0]
+		--------------------				7-SEG Dispaly					----------------------------
+		HEX0_D		: out std_logic_vector(6 downto 0);		--	Seven Segment Digit 0
+		HEX0_DP		: out std_logic;								--	Seven Segment Digit DP 0
+		HEX1_D		: out std_logic_vector(6 downto 0);		--	Seven Segment Digit 1
+		HEX1_DP		: out std_logic;								--	Seven Segment Digit DP 1
+		HEX2_D		: out std_logic_vector(6 downto 0);		--	Seven Segment Digit 2
+		HEX2_DP		: out std_logic;								--	Seven Segment Digit DP 2
+		HEX3_D		: out std_logic_vector(6 downto 0);		--	Seven Segment Digit 3
+		HEX3_DP		: out std_logic;								--	Seven Segment Digit DP 3
+		--------------------						LED						----------------------------
+		LEDG			: out std_logic_vector(9 downto 0);		--	LED Green[9:0]
+		--------------------						UART						----------------------------
+		UART_TXD		: out std_logic;								--	UART Transmitter
+		UART_RXD		: in std_logic;								--	UART Receiver
+		UART_CTS		: in std_logic;								--	UART Clear To Send
+		UART_RTS		: out std_logic;								--	UART Request To Send
+		--------------------				SDRAM Interface				----------------------------
+		DRAM_DQ		: inout std_logic_vector(15 downto 0);	--	SDRAM Data bus 16 Bits
+		DRAM_ADDR	: out std_logic_vector(12 downto 0);	--	SDRAM Address bus 13 Bits
+		DRAM_LDQM	: out std_logic;								--	SDRAM Low-byte Data Mask 
+		DRAM_UDQM	: out std_logic;								--	SDRAM High-byte Data Mask
+		DRAM_WE_N	: out std_logic;								--	SDRAM Write Enable
+		DRAM_CAS_N	: out std_logic;								--	SDRAM Column Address Strobe
+		DRAM_RAS_N	: out std_logic;								--	SDRAM Row Address Strobe
+		DRAM_CS_N	: out std_logic;								--	SDRAM Chip Select
+		DRAM_BA_0	: out std_logic;								--	SDRAM Bank Address 0
+		DRAM_BA_1	: out std_logic;								--	SDRAM Bank Address 1
+		DRAM_CLK		: out std_logic;								--	SDRAM Clock
+		DRAM_CKE		: out std_logic;								--	SDRAM Clock Enable
+		--------------------				Flash Interface				----------------------------
+		FL_DQ			: inout std_logic_vector(15 downto 0);	--	FLASH Data bus 16 Bits
+--		FL_DQ15_AM1	: out std_logic;								--	FLASH Data bus Bit 15 or Address A-1
+		FL_ADDR		: out std_logic_vector(21 downto 0);	--	FLASH Address bus 22 Bits
+		FL_WE_N		: out std_logic;								--	FLASH Write Enable
+		FL_RST_N		: out std_logic;								--	FLASH Reset
+		FL_OE_N		: out std_logic;								--	FLASH Output Enable
+		FL_CE_N		: out std_logic;								--	FLASH Chip Enable
+		FL_WP_N		: out std_logic;								--	FLASH Hardware Write Protect
+		FL_BYTE_N	: out std_logic;								--	FLASH Selects 8/16-bit mode
+		FL_RY			: out std_logic;								--	FLASH Ready/Busy
+		--------------------				LCD Module 16X2				----------------------------
+		LCD_BLON		: out std_logic;								--	LCD Back Light ON/OFF
+		LCD_RW		: out std_logic;								--	LCD Read/Write Select, 0 = Write, 1 = Read
+		LCD_EN		: out std_logic;								--	LCD Enable
+		LCD_RS		: out std_logic;								--	LCD Command/Data Select, 0 = Command, 1 = Data
+		LCD_DATA		: out std_logic_vector(7 downto 0);		--	LCD Data bus 8 bits
+		--------------------				SD_Card Interface				----------------------------
+		SD_DAT0		: inout std_logic;							--	SD Card Data 0 (DO)
+		SD_DAT3		: inout std_logic;							--	SD Card Data 3 (CS)
+		SD_CMD		: out std_logic;								--	SD Card Command Signal (DI)
+		SD_CLK		: out std_logic;								--	SD Card Clock (SCLK)
+		SD_WP_N		: in std_logic;								--	SD Card Write Protect
+		--------------------						PS2						----------------------------
+		PS2_KBDAT	: in std_logic;								--	PS2 Keyboard Data
+		PS2_KBCLK	: in std_logic;								--	PS2 Keyboard Clock
+		PS2_MSDAT	: in std_logic;								--	PS2 Mouse Data
+		PS2_MSCLK	: in std_logic;								--	PS2 Mouse Clock
+		--------------------						VGA						----------------------------
+		VGA_HS		: out std_logic;								--	VGA H_SYNC
+		VGA_VS		: out std_logic;								--	VGA V_SYNC
+		VGA_R			: out std_logic_vector(3 downto 0);   	--	VGA Red[3:0]
+		VGA_G			: out std_logic_vector(3 downto 0);	 	--	VGA Green[3:0]
+		VGA_B			: out std_logic_vector(3 downto 0);  	--	VGA Blue[3:0]
+		--------------------						GPIO						------------------------------
+		GPIO0_CLKIN	: in std_logic_vector(1 downto 0);		--	GPIO Connection 0 Clock In Bus
+		GPIO0_CLKOUT: out std_logic_vector(1 downto 0);		--	GPIO Connection 0 Clock Out Bus
+		GPIO0_D		: out std_logic_vector(31 downto 0);	--	GPIO Connection 0 Data Bus
+		GPIO1_CLKIN	: in std_logic_vector(1 downto 0);		--	GPIO Connection 1 Clock In Bus
+		GPIO1_CLKOUT: out std_logic_vector(1 downto 0);		--	GPIO Connection 1 Clock Out Bus
+		GPIO1_D		: inout std_logic_vector(31 downto 0)	--	GPIO Connection 1 Data Bus
+  );
+end mz80b;
+
+architecture rtl of mz80b is
+
+--
+-- Z80
+--
+signal ZADR : std_logic_vector(22 downto 0);
+signal ZDI : std_logic_vector(7 downto 0);
+signal ZDO : std_logic_vector(7 downto 0);
+signal ZCS_x : std_logic;
+signal ZWR_x : std_logic;
+signal ZPG_x : std_logic;
+--
+-- NiosII
+--
+signal RRST_x : std_logic;								-- NiosII Reset
+signal RCLK : std_logic;								-- NiosII Clock
+signal RADR : std_logic_vector(15 downto 0);		-- NiosII Address Bus
+signal RCS_x : std_logic;								-- NiosII Read Signal
+signal RWE_x : std_logic;								-- NiosII Write Signal
+signal RDI : std_logic_vector(7 downto 0);		-- NiosII Data Bus(in)
+signal RDO : std_logic_vector(7 downto 0);		-- NiosII Data Bus(out)
+signal INTL : std_logic;								-- Interrupt Line
+signal MADR : std_logic_vector(20 downto 0);		-- Address
+signal MDI : std_logic_vector(31 downto 0);		-- Data Input(32bit)
+signal MDO : std_logic_vector(31 downto 0);		-- Data Output(32bit)
+signal MCS_x : std_logic;								-- Chip Select
+signal MWE_x : std_logic;								-- Write Enable
+signal MBEN_x : std_logic_vector(3 downto 0);	-- Byte Enable
+signal MWRQ_x : std_logic;								-- CPU Wait
+--
+-- Clock, Reset
+--
+signal PCLK : std_logic;
+signal URST : std_logic;
+signal MRST : std_logic;
+signal ARST : std_logic;
+--
+-- FD Buffer
+--
+signal BCS_x : std_logic;								-- RAM Request
+signal BADR : std_logic_vector(22 downto 0);		-- RAM Address
+signal BWR_x : std_logic;				 				-- RAM Write Signal
+signal BDI : std_logic_vector(7 downto 0);		-- Data Bus Input from RAM
+signal BDO : std_logic_vector(7 downto 0);		-- Data Bus Output to RAM
+--
+-- GRAM
+--
+signal GADR : std_logic_vector(20 downto 0);
+signal GCS_x : std_logic;
+signal GWR_x : std_logic;
+signal GBE_x : std_logic_vector(3 downto 0);
+signal GDI : std_logic_vector(31 downto 0);
+signal GDO : std_logic_vector(31 downto 0);
+--
+-- SDRAM
+--
+signal SDRAMDO : std_logic_vector(15 downto 0);
+signal SDRAMDOE : std_logic;
+--
+-- MMC/SD CARD
+--
+signal SD_CS : std_logic;
+signal SD_DEN : std_logic_vector(1 downto 0);
+signal SD_DO : std_logic;
+--
+-- Flash Memory
+--
+signal FL_ADDR0 : std_logic_vector(21 downto 0);
+signal FL_WE_Ni : std_logic_vector(0 downto 0);
+signal FL_OE_Ni : std_logic_vector(0 downto 0);
+signal FL_CE_Ni : std_logic_vector(0 downto 0);
+--
+-- Misc
+--
+signal T_LEDG : std_logic_vector(9 downto 0);
+--signal ZLEDG : std_logic_vector(9 downto 0);
+signal CNT1 : std_logic_vector(24 downto 0);
+signal CNT2 : std_logic_vector(24 downto 0);
+
+--
+-- Components
+--
+component mz80b_core
+	port(
+		-- Z80 Memory Bus
+		ZADR			: out std_logic_vector(22 downto 0);
+		ZDI			: in std_logic_vector(7 downto 0);
+		ZDO			: out std_logic_vector(7 downto 0);
+		ZCS_x			: out std_logic;
+		ZWR_x			: out std_logic;
+		ZPG_x	  		: out std_logic;
+		-- NiosII Access
+		RRST_x		: in std_logic;								-- NiosII Reset
+		RCLK			: in std_logic;								-- NiosII Clock
+		RADR			: in std_logic_vector(15 downto 0);		-- NiosII Address Bus
+		RCS_x			: in std_logic;								-- NiosII Read Signal
+		RWE_x			: in std_logic;								-- NiosII Write Signal
+		RDI			: in std_logic_vector(7 downto 0);		-- NiosII Data Bus(in)
+		RDO			: out std_logic_vector(7 downto 0);		-- NiosII Data Bus(out)
+		INTL			: out std_logic;								-- Interrupt Line
+		-- Graphic VRAM Access
+		GCS_x			: out std_logic;								-- GRAM Request
+		GADR			: out std_logic_vector(20 downto 0);	-- GRAM Address
+		GWR_x			: out std_logic;				 				-- GRAM Write Signal
+		GBE_x			: out std_logic_vector(3 downto 0);		-- GRAM Byte Enable
+		GDI			: in std_logic_vector(31 downto 0);		-- Data Bus Input from GRAM
+		GDO			: out std_logic_vector(31 downto 0);	-- Data Bus Output to GRAM
+		-- FD Buffer RAM I/F
+		BCS_x 		: out std_logic;								-- RAM Request
+		BADR 		 	: out std_logic_vector(22 downto 0);	-- RAM Address
+		BWR_x 		: out std_logic;				 				-- RAM Write Signal
+		BDI			: in std_logic_vector(7 downto 0);		-- Data Bus Input from RAM
+		BDO			: out std_logic_vector(7 downto 0);		-- Data Bus Output to RAM
+		-- Resets
+		URST_x		: out std_logic;							-- Universal Reset
+		MRST_x		: in std_logic;							-- Reset after SDRAM init.
+		ARST_x		: out std_logic;							-- All Reset
+		-- Clock Input	 
+		CLOCK_50		: in std_logic;							--	50 MHz
+		-- Push Button
+		BUTTON		: in std_logic_vector(2 downto 0);	--	Pushbutton[2:0]
+		-- Switch
+		SW				: in std_logic_vector(9 downto 0);	--	Toggle Switch[9:0]
+		-- 7-SEG Dispaly
+		HEX0_D		: out std_logic_vector(6 downto 0);	--	Seven Segment Digit 0
+		HEX0_DP		: out std_logic;							--	Seven Segment Digit DP 0
+		HEX1_D		: out std_logic_vector(6 downto 0);	--	Seven Segment Digit 1
+		HEX1_DP		: out std_logic;							--	Seven Segment Digit DP 1
+		HEX2_D		: out std_logic_vector(6 downto 0);	--	Seven Segment Digit 2
+		HEX2_DP		: out std_logic;							--	Seven Segment Digit DP 2
+		HEX3_D		: out std_logic_vector(6 downto 0);	--	Seven Segment Digit 3
+		HEX3_DP		: out std_logic;							--	Seven Segment Digit DP 3
+		-- LED
+		LEDG			: out std_logic_vector(9 downto 0);		--	LED Green[9:0]
+		-- PS2
+		PS2_KBDAT	: in std_logic;						--	PS2 Keyboard Data
+		PS2_KBCLK	: in std_logic;						--	PS2 Keyboard Clock
+		-- VGA
+		VGA_HS		: out std_logic;							--	VGA H_SYNC
+		VGA_VS		: out std_logic;							--	VGA V_SYNC
+		VGA_R			: out std_logic_vector(3 downto 0); --	VGA Red[3:0]
+		VGA_G			: out std_logic_vector(3 downto 0);	--	VGA Green[3:0]
+		VGA_B			: out std_logic_vector(3 downto 0);  	--	VGA Blue[3:0]
+		-- GPIO
+		GPIO0_CLKIN	: in std_logic_vector(1 downto 0);		--	GPIO Connection 0 Clock In Bus
+		GPIO0_CLKOUT: out std_logic_vector(1 downto 0);		--	GPIO Connection 0 Clock Out Bus
+		GPIO0_D		: out std_logic_vector(31 downto 0);	--	GPIO Connection 0 Data Bus
+		GPIO1_CLKIN	: in std_logic_vector(1 downto 0);		--	GPIO Connection 1 Clock In Bus
+		GPIO1_CLKOUT: out std_logic_vector(1 downto 0);		--	GPIO Connection 1 Clock Out Bus
+		GPIO1_D		: inout std_logic_vector(31 downto 0)	--	GPIO Connection 1 Data Bus
+	);
+end component;
+
+component mz80b_de0
+	port (
+		spi_cs_export            : out   std_logic;                                        -- export
+		cfi_tcm_address_out      : out   std_logic_vector(21 downto 0);                    -- tcm_address_out
+		cfi_tcm_read_n_out       : out   std_logic_vector(0 downto 0);                     -- tcm_read_n_out
+		cfi_tcm_write_n_out      : out   std_logic_vector(0 downto 0);                     -- tcm_write_n_out
+		cfi_tcm_data_out         : inout std_logic_vector(15 downto 0) := (others => 'X'); -- tcm_data_out
+		cfi_tcm_chipselect_n_out : out   std_logic_vector(0 downto 0);                     -- tcm_chipselect_n_out
+		spi_MISO                 : in    std_logic                     := 'X';             -- MISO
+		spi_MOSI                 : out   std_logic;                                        -- MOSI
+		spi_SCLK                 : out   std_logic;                                        -- SCLK
+		spi_SS_n                 : out   std_logic_vector(1 downto 0);                     -- SS_n
+		uart_rxd                 : in    std_logic                     := 'X';             -- rxd
+		uart_txd                 : out   std_logic;                                        -- txd
+		uart_cts_n               : in    std_logic                     := 'X';             -- cts_n
+		uart_rts_n               : out   std_logic;                                        -- rts_n
+		clkin_clk                : in    std_logic                     := 'X';             -- clk
+		mem_address              : out   std_logic_vector(20 downto 0);                    -- address
+		mem_readdata             : in    std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+		mem_writedata            : out   std_logic_vector(31 downto 0);                    -- writedata
+		mem_byteenable_n         : out   std_logic_vector(3 downto 0);                     -- byteenable_n
+		mem_chipselect_n         : out   std_logic;                                        -- chipselect_n
+		mem_write_n              : out   std_logic;                                        -- write_n
+		mem_waitrequest_n        : in    std_logic                     := 'X';             -- waitrequest_n
+		mem_reset_reset_n        : out   std_logic;                                        -- reset_n
+		reset_reset_n            : in    std_logic                     := 'X';             -- reset_n
+		reg_address              : out   std_logic_vector(15 downto 0);                    -- address
+		reg_readdata             : in    std_logic_vector(7 downto 0)  := (others => 'X'); -- readdata
+		reg_writedata            : out   std_logic_vector(7 downto 0);                     -- writedata
+		reg_chipselect_n         : out   std_logic;                                        -- chipselect_n
+		reg_write_n              : out   std_logic;                                        -- write_n
+		reg_reset_reset_n        : out   std_logic;                                        -- reset_n
+		intc_export              : in    std_logic                     := 'X'              -- export
+	);
+end component;
+
+component sdram
+	port (
+		reset			: in std_logic;								-- Reset
+		RSTOUT		: out std_logic;								-- Reset After Init. SDRAM
+		CLOCK_50		: in std_logic;								-- Clock(50MHz)
+		PCLK			: out std_logic;								-- CPU Clock
+		-- RAM access(port-A:Z80 bus)
+		AA				: in std_logic_vector(22 downto 0);		-- Address
+		DAI			: in std_logic_vector(7 downto 0);		-- Data Input(16bit)
+		DAO			: out std_logic_vector(7 downto 0);		-- Data Output(16bit)
+		CSA			: in std_logic;								-- Chip Select
+		WEA			: in std_logic;								-- Write Enable
+		PGA			: in std_logic;								-- Purge Cache
+		-- RAM access(port-B:Avalon bus bridge)
+		AB				: in std_logic_vector(20 downto 0);		-- Address
+		DBI			: in std_logic_vector(31 downto 0);		-- Data Input(32bit)
+		DBO			: out std_logic_vector(31 downto 0);	-- Data Output(32bit)
+		CSB			: in std_logic;								-- Chip Select
+		WEB			: in std_logic;								-- Write Enable
+		BEB			: in std_logic_vector(3 downto 0);		-- Byte Enable
+		WQB			: out std_logic;								-- CPU Wait
+		-- RAM access(port-C:Reserve)
+		AC				: in std_logic_vector(21 downto 0);		-- Address
+		DCI			: in std_logic_vector(15 downto 0);		-- Data Input(16bit)
+		DCO			: out std_logic_vector(15 downto 0);	-- Data Output(16bit)
+		CSC			: in std_logic;								-- Chip Select
+		WEC			: in std_logic;								-- Write Enable
+		BEC			: in std_logic_vector(1 downto 0);		-- Byte Enable
+		-- RAM access(port-D:FD Buffer Access port)
+		AD				: in std_logic_vector(22 downto 0);		-- Address
+		DDI			: in std_logic_vector(7 downto 0);		-- Data Input(16bit)
+		DDO			: out std_logic_vector(7 downto 0);		-- Data Output(16bit)
+		CSD			: in std_logic;								-- Chip Select
+		WED			: in std_logic;								-- Write Enable
+		--BED			: in std_logic_vector(1 downto 0);		-- Byte Enable
+		-- RAM access(port-E:Graphics Video Memory)
+		AE				: in std_logic_vector(20 downto 0);		-- Address
+		DEI			: in std_logic_vector(31 downto 0);		-- Data Input(32bit)
+		DEO			: out std_logic_vector(31 downto 0);	-- Data Output(32bit)
+		CSE			: in std_logic;								-- Chip Select
+		WEE			: in std_logic;								-- Write Enable
+		BEE			: in std_logic_vector(3 downto 0);		-- Byte Enable
+		-- SDRAM signal
+		MA				: out std_logic_vector(11 downto 0);	-- Address
+		MBA0			: out std_logic;								-- Bank Address 0
+		MBA1			: out std_logic;								-- Bank Address 1
+		MDI			: in std_logic_vector(15 downto 0);		-- Data Input(16bit)
+		MDO			: out std_logic_vector(15 downto 0);	-- Data Output(16bit)
+		MDOE			: out std_logic;								-- Data Output Enable
+		MLDQ			: out std_logic;								-- Lower Data Mask
+		MUDQ			: out std_logic;								-- Upper Data Mask
+		MCAS			: out std_logic;								-- Column Address Strobe
+		MRAS			: out std_logic;								-- Raw Address Strobe
+		MCS			: out std_logic;								-- Chip Select
+		MWE			: out std_logic;								-- Write Enable
+		MCKE			: out std_logic;								-- Clock Enable
+		MCLK			: out std_logic								-- SDRAM Clock
+	);
+end component;
+
+begin
+
+	--
+	-- Instantiation
+	--
+	MZ80B : mz80b_core port map(
+		-- Z80 Memory Bus
+		ZADR => ZADR,
+		ZDI => ZDI,
+		ZDO => ZDO,
+		ZCS_x =>ZCS_x,
+		ZWR_x => ZWR_x,
+		ZPG_x => ZPG_x,
+		-- NiosII Access
+		RRST_x => RRST_x,						-- NiosII Reset
+		RCLK => PCLK,							-- NiosII Clock
+		RADR => RADR,							-- NiosII Address Bus
+		RCS_x => RCS_x,						-- NiosII Read Signal
+		RWE_x => RWE_x,						-- NiosII Write Signal
+		RDI => RDO,								-- NiosII Data Bus(in)
+		RDO => RDI,								-- NiosII Data Bus(out)
+		INTL => INTL,							-- Interrupt Line
+		-- Graphic VRAM Access
+		GCS_x => GCS_x,						-- GRAM Request
+		GADR => GADR,							-- GRAM Address
+		GWR_x => GWR_x,		 				-- GRAM Write Signal
+		GBE_x => GBE_x,						-- GRAM Byte Enable
+		GDI => GDI,								-- Data Bus Input from GRAM
+		GDO => GDO,								-- Data Bus Output to GRAM
+		-- FD Buffer RAM I/F
+		BCS_x => BCS_x,						-- RAM Request
+		BADR => BADR,							-- RAM Address
+		BWR_x => BWR_x,		 				-- RAM Write Signal
+		BDI => BDI,								-- Data Bus Input from RAM
+		BDO => BDO,								-- Data Bus Output to RAM
+		-- Resets
+		URST_x => URST,						-- Universal Reset
+		MRST_x => MRST,						-- All Reset
+		ARST_x => ARST,						-- All Reset
+		-- Clock Input
+		CLOCK_50 => CLOCK_50,				--	50 MHz
+		-- Push Button
+		BUTTON => BUTTON,						--	Pushbutton[2:0]
+		-- Switch
+		SW => SW,								--	Toggle Switch[9:0]
+		-- 7-SEG Dispaly
+		HEX0_D => HEX0_D,						--	Seven Segment Digit 0
+		HEX0_DP => HEX0_DP,					--	Seven Segment Digit DP 0
+		HEX1_D => HEX1_D,						--	Seven Segment Digit 1
+		HEX1_DP => HEX1_DP,					--	Seven Segment Digit DP 1
+		HEX2_D => HEX2_D,						--	Seven Segment Digit 2
+		HEX2_DP => HEX2_DP,					--	Seven Segment Digit DP 2
+		HEX3_D => HEX3_D,						--	Seven Segment Digit 3
+		HEX3_DP => HEX3_DP,					--	Seven Segment Digit DP 3
+		-- LED
+		LEDG => T_LEDG,						--	LED Green[9:0]
+		-- PS2
+		PS2_KBDAT => PS2_KBDAT,				--	PS2 Keyboard Data
+		PS2_KBCLK => PS2_KBCLK,				--	PS2 Keyboard Clock
+		-- VGA
+		VGA_HS => VGA_HS,						-- VGA H_SYNC
+		VGA_VS => VGA_VS,						-- VGA V_SYNC
+		VGA_R => VGA_R, 						-- VGA Red[3:0]
+		VGA_G => VGA_G,						-- VGA Green[3:0]
+		VGA_B => VGA_B,  						-- VGA Blue[3:0]
+		-- GPIO
+		GPIO0_CLKIN => GPIO0_CLKIN,		--	GPIO Connection 0 Clock In Bus
+		GPIO0_CLKOUT => GPIO0_CLKOUT,		--	GPIO Connection 0 Clock Out Bus
+		GPIO0_D => GPIO0_D,					--	GPIO Connection 0 Data Bus
+		GPIO1_CLKIN => GPIO1_CLKIN,		--	GPIO Connection 1 Clock In Bus
+		GPIO1_CLKOUT => GPIO1_CLKOUT,		--	GPIO Connection 1 Clock Out Bus
+		GPIO1_D => GPIO1_D					--	GPIO Connection 1 Data Bus
+	);
+
+	SOPC0 : mz80b_de0 port map (
+		spi_cs_export            => SD_CS,						--    spi_cs.export
+		cfi_tcm_address_out      => FL_ADDR0,					--       cfi.tcm_address_out
+		cfi_tcm_read_n_out       => FL_OE_Ni,					--          .tcm_read_n_out
+		cfi_tcm_write_n_out      => FL_WE_Ni,					--          .tcm_write_n_out
+		cfi_tcm_data_out         => FL_DQ,						--          .tcm_data_out
+		cfi_tcm_chipselect_n_out => FL_CE_Ni,					--          .tcm_chipselect_n_out
+		spi_MISO                 => SD_DAT0,					--       spi.MISO
+		spi_MOSI                 => SD_DO,						--          .MOSI
+		spi_SCLK                 => SD_CLK,						--          .SCLK
+		spi_SS_n                 => SD_DEN,						--          .SS_n
+		uart_rxd                 => UART_RXD,					--      uart.rxd
+		uart_txd                 => UART_TXD,					--          .txd
+		uart_cts_n               => UART_CTS,					--          .cts_n
+		uart_rts_n               => UART_RTS,					--          .rts_n
+		clkin_clk                => PCLK,						--     clkin.clk
+		mem_address              => MADR,						--       mem.address
+		mem_readdata             => MDI,							--          .readdata
+		mem_writedata            => MDO,							--          .writedata
+		mem_byteenable_n         => MBEN_x,						--          .byteenable_n
+		mem_chipselect_n         => MCS_x,						--          .chipselect_n
+		mem_write_n              => MWE_x,						--          .write_n
+		mem_waitrequest_n        => MWRQ_x,						--          .waitrequest_n
+		mem_reset_reset_n        => open,						-- mem_reset.reset_n
+		reset_reset_n            => ARST,						--     reset.reset_n
+		reg_address              => RADR,						--       reg.address
+		reg_readdata             => RDI,							--          .readdata
+		reg_writedata            => RDO,							--          .writedata
+		reg_chipselect_n         => RCS_x,						--          .chipselect_n
+		reg_write_n              => RWE_x,						--          .write_n
+		reg_reset_reset_n        => RRST_x,						-- reg_reset.reset_n
+		intc_export              => INTL							--      intc.export
+	);
+
+	DRAM0 : sdram port map (
+		reset => URST,							-- Reset
+		RSTOUT => MRST,						-- Reset After Init. SDRAM
+		CLOCK_50 => CLOCK_50_2,				-- Clock(50MHz)
+		PCLK => PCLK,							-- CPU Clock
+		-- RAM access(port-A:Z80 Memory Bus)
+		AA => ZADR,								-- Address
+		DAI => ZDO,								-- Data Input(16bit)
+		DAO => ZDI,								-- Data Output(16bit)
+		CSA => ZCS_x,							-- Chip Select
+		WEA => ZWR_x,							-- Write Enable
+		PGA => ZPG_x,							-- Purge Cache
+		-- RAM access(port-B:Avalon Bus)
+		AB => MADR,								-- Address
+		DBI => MDO,								-- Data Input(32bit)
+		DBO => MDI,								-- Data Output(32bit)
+		CSB => MCS_x,							-- Chip Select
+		WEB => MWE_x,							-- Write Enable
+		BEB => MBEN_x,							-- Byte Enable
+		WQB => MWRQ_x,							-- CPU Wait
+		-- RAM access(port-C:Reserve)
+		AC => (others=>'1'),					-- Address
+		DCI => (others=>'0'),				-- Data Input(16bit)
+		DCO => open,							-- Data Output(16bit)
+		CSC => '1',								-- Chip Select
+		WEC => '1',								-- Write Enable
+		BEC => "11",							-- Byte Enable
+		-- RAM access(port-D:FD Buffer)
+		AD => BADR,								-- Address
+		DDI => BDO,								-- Data Input(16bit)
+		DDO => BDI,								-- Data Output(16bit)
+		CSD => BCS_x,							-- Chip Select
+		WED => BWR_x,							-- Write Enable
+		--BED => "00",							-- Byte Enable
+		-- RAM access(port-E:Graphics Video Memory)
+		AE => GADR,								-- Address
+		DEI => GDO,								-- Data Input(32bit)
+		DEO => GDI,								-- Data Output(32bit)
+		CSE => GCS_x,							-- Chip Select
+		WEE => GWR_x,							-- Write Enable
+		BEE => GBE_x,							-- Byte Enable
+		-- SDRAM signal
+		MA => DRAM_ADDR(11 downto 0),		-- Address
+		MBA0 => DRAM_BA_0,					-- Bank Address 0
+		MBA1 => DRAM_BA_1,					-- Bank Address 1
+		MDI => DRAM_DQ,						-- Data Input(16bit)
+		MDO => SDRAMDO,						-- Data Output(16bit)
+		MDOE => SDRAMDOE,						-- Data Output Enable
+		MLDQ => DRAM_LDQM,					-- Lower Data Mask
+		MUDQ => DRAM_UDQM,					-- Upper Data Mask
+		MCAS => DRAM_CAS_N,					-- Column Address Strobe
+		MRAS => DRAM_RAS_N,					-- Raw Address Strobe
+		MCS => DRAM_CS_N,						-- Chip Select
+		MWE => DRAM_WE_N,						-- Write Enable
+		MCKE => DRAM_CKE,						-- Clock Enable
+		MCLK => DRAM_CLK						-- SDRAM Clock
+	);
+
+	--
+	-- MMC/SD CARD
+	--
+	SD_CMD<=SD_DO when SD_DEN(1)='0' else '1';
+	SD_DAT3<=SD_CS;
+
+	--
+	-- SDRAM
+	--
+	DRAM_DQ<=SDRAMDO when SDRAMDOE='1' else (others=>'Z');
+
+	--
+	-- Flash Memory
+	--
+	FL_ADDR<='0'&FL_ADDR0(21 downto 1);
+	FL_RST_N<='1';	--URST;
+	FL_WP_N<='1';
+	FL_BYTE_N<='1';
+	FL_WE_N<=FL_WE_Ni(0);
+	FL_OE_N<=FL_OE_Ni(0);
+	FL_CE_N<=FL_CE_Ni(0);
+
+	--
+	-- Misc & Debug
+	--
+	LEDG<=(not SD_CS)&T_LEDG(8 downto 0);
+--	LEDG<=(not SD_CS)&"000000000";
+	--GPIO0_D(0)<=PS2_KBCLK;
+	--GPIO0_D(1)<=PS2_KBDAT;
+	--GPIO0_D(2)<=KBEN;
+	--GPIO0_D(10 downto 3)<=KBDT;
+	--GPIO0_D(11)<=ARST;
+
+end rtl;
diff --git a/mz80b/old/pll100.qip b/mz80b/old/pll100.qip
new file mode 100644
index 0000000..db23869
--- /dev/null
+++ b/mz80b/old/pll100.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll100.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll100_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll100.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll100.ppf"]
diff --git a/mz80b/old/pll100.vhd b/mz80b/old/pll100.vhd
new file mode 100644
index 0000000..135b83c
--- /dev/null
+++ b/mz80b/old/pll100.vhd
@@ -0,0 +1,446 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll100.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll100 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+END pll100;
+
+
+ARCHITECTURE SYN OF pll100 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 2,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 2,
+		clk1_phase_shift => "-1667",
+		clk2_divide_by => 5,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 2,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 1600,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 1,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll100",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.031250"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.03125000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-60.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll100.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1667"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1600"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/mz80b/old/pll50.qip b/mz80b/old/pll50.qip
new file mode 100644
index 0000000..6ad6181
--- /dev/null
+++ b/mz80b/old/pll50.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll50.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll50_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll50.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll50.ppf"]
diff --git a/mz80b/old/pll50.vhd b/mz80b/old/pll50.vhd
new file mode 100644
index 0000000..cb4d051
--- /dev/null
+++ b/mz80b/old/pll50.vhd
@@ -0,0 +1,446 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll50.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll50 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+END pll50;
+
+
+ARCHITECTURE SYN OF pll50 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 2,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 1,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 25,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 8,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 25,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 2,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 1600,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 1,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll50",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "4.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.031250"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "4.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.03125000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll50.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1600"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/mz80b/old/ps2kb.vhd b/mz80b/old/ps2kb.vhd
new file mode 100644
index 0000000..06dbf39
--- /dev/null
+++ b/mz80b/old/ps2kb.vhd
@@ -0,0 +1,77 @@
+--
+-- ps2kb.vhd
+--
+-- PS/2 Keyboard Interface module
+-- for MZ-700 on FPGA
+--
+-- Nibbles Lab. 2005
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.ALL;
+
+--  Uncomment the following lines to use the declarations that are
+--  provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ps2kb is
+    Port ( RST : in std_logic;
+    		 KCLK : in std_logic;
+    		 PS2CK : in std_logic;
+           PS2DT : in std_logic;
+           DTEN : out std_logic;
+           DATA : out std_logic_vector(7 downto 0));
+end ps2kb;
+
+architecture Behavioral of ps2kb is
+
+--
+-- PS/2 recieve data
+--
+signal KEYDT : std_logic_vector(10 downto 0);
+signal CKDT : std_logic_vector(3 downto 0);
+--
+-- Parity
+--
+signal PARITY : std_logic;
+
+begin
+
+	--
+	-- PS/2 recieve
+	--
+	process( RST, KCLK ) begin
+		if RST='0' then
+			KEYDT<=(others=>'1');
+			DATA<=(others=>'0');
+			DTEN<='0';
+		elsif KCLK'event and KCLK='1' then
+			CKDT<=CKDT(2 downto 0)&PS2CK;
+			if CKDT="0011" then
+				KEYDT<=PS2DT&KEYDT(10 downto 1);
+			end if;
+			if KEYDT(0)='0' and KEYDT(10)='1' and KEYDT(9)=not PARITY then
+				DTEN<='1';
+				DATA<=KEYDT(8 downto 1);
+				KEYDT<=(others=>'1');
+			else
+				DTEN<='0';
+			end if;
+		end if;
+	end process;
+
+	process( KEYDT(9 downto 2) )
+		variable TEMP : std_logic;
+	begin
+		TEMP:='0';
+		for I in 1 to 8 loop
+			TEMP:=TEMP xor KEYDT(I);
+		end loop;
+		PARITY<=TEMP;
+	end process;
+
+end Behavioral;
diff --git a/mz80b/old/sdram.vhd b/mz80b/old/sdram.vhd
new file mode 100644
index 0000000..0f11272
--- /dev/null
+++ b/mz80b/old/sdram.vhd
@@ -0,0 +1,755 @@
+--
+-- sdram.vhd
+--
+-- SDRAM access module with self refresh and multi ports
+-- for MZ-80C/80B on FPGA
+--
+-- Nibbles Lab. 2007-2014
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sdram is
+	port (
+		reset			: in std_logic;								-- Reset
+		RSTOUT		: out std_logic;								-- Reset After Init. SDRAM
+		CLOCK_50		: in std_logic;								-- Clock(50MHz)
+		PCLK			: out std_logic;								-- NiosII Clock(20MHz)
+		-- RAM access(port-A:Z80 bus)
+		AA				: in std_logic_vector(22 downto 0);		-- Address
+		DAI			: in std_logic_vector(7 downto 0);		-- Data Input(16bit)
+		DAO			: out std_logic_vector(7 downto 0);		-- Data Output(16bit)
+		CSA			: in std_logic;								-- Chip Select
+		WEA			: in std_logic;								-- Write Enable
+		PGA			: in std_logic;								-- Purge Cache
+		--BEA			: in std_logic_vector(1 downto 0);		-- Byte Enable
+		-- RAM access(port-B:Avalon bus bridge)
+		AB				: in std_logic_vector(20 downto 0);		-- Address
+		DBI			: in std_logic_vector(31 downto 0);		-- Data Input(32bit)
+		DBO			: out std_logic_vector(31 downto 0);	-- Data Output(32bit)
+		CSB			: in std_logic;								-- Chip Select
+		WEB			: in std_logic;								-- Write Enable
+		BEB			: in std_logic_vector(3 downto 0);		-- Byte Enable
+		WQB			: out std_logic;								-- CPU Wait
+		-- RAM access(port-C:Reserve)
+		AC				: in std_logic_vector(21 downto 0);		-- Address
+		DCI			: in std_logic_vector(15 downto 0);		-- Data Input(16bit)
+		DCO			: out std_logic_vector(15 downto 0);	-- Data Output(16bit)
+		CSC			: in std_logic;								-- Chip Select
+		WEC			: in std_logic;								-- Write Enable
+		BEC			: in std_logic_vector(1 downto 0);		-- Byte Enable
+		-- RAM access(port-D:FD Buffer Access port)
+		AD				: in std_logic_vector(22 downto 0);		-- Address
+		DDI			: in std_logic_vector(7 downto 0);		-- Data Input(16bit)
+		DDO			: out std_logic_vector(7 downto 0);	-- Data Output(16bit)
+		CSD			: in std_logic;								-- Chip Select
+		WED			: in std_logic;								-- Write Enable
+		--BED			: in std_logic_vector(1 downto 0);		-- Byte Enable
+		-- RAM access(port-E:Graphics Video Memory)
+		AE				: in std_logic_vector(20 downto 0);		-- Address
+		DEI			: in std_logic_vector(31 downto 0);		-- Data Input(32bit)
+		DEO			: out std_logic_vector(31 downto 0);	-- Data Output(32bit)
+		CSE			: in std_logic;								-- Chip Select
+		WEE			: in std_logic;								-- Write Enable
+		BEE			: in std_logic_vector(3 downto 0);		-- Byte Enable
+		-- SDRAM signal
+		MA				: out std_logic_vector(11 downto 0);	-- Address
+		MBA0			: out std_logic;								-- Bank Address 0
+		MBA1			: out std_logic;								-- Bank Address 1
+		MDI			: in std_logic_vector(15 downto 0);		-- Data Input(16bit)
+		MDO			: out std_logic_vector(15 downto 0);	-- Data Output(16bit)
+		MDOE			: out std_logic;								-- Data Output Enable
+		MLDQ			: out std_logic;								-- Lower Data Mask
+		MUDQ			: out std_logic;								-- Upper Data Mask
+		MCAS			: out std_logic;								-- Column Address Strobe
+		MRAS			: out std_logic;								-- Raw Address Strobe
+		MCS			: out std_logic;								-- Chip Select
+		MWE			: out std_logic;								-- Write Enable
+		MCKE			: out std_logic;								-- Clock Enable
+		MCLK			: out std_logic								-- SDRAM Clock
+	);
+end sdram;
+
+architecture rtl of sdram is
+
+signal A : std_logic_vector(21 downto 0);
+signal RA : std_logic_vector(21 downto 0);
+signal RD : std_logic_vector(21 downto 0);
+--signal DI : std_logic_vector(15 downto 0);
+signal WCNT : std_logic_vector(2 downto 0);
+signal CNT200 : std_logic;
+signal CNT3 : std_logic_vector(2 downto 0);
+--signal BUF    : std_logic_vector(7 downto 0);
+signal CSMA   : std_logic;			-- Masked
+signal CSMD   : std_logic;			-- Masked
+signal PGAi   : std_logic;			-- Purge Flag
+signal PGDi   : std_logic;			-- Purge Flag
+signal CSAi   : std_logic;
+signal CSAii  : std_logic_vector(3 downto 0);
+signal CSBi   : std_logic;
+signal CSBii  : std_logic_vector(3 downto 0);
+signal CSCi   : std_logic;
+signal CSCii  : std_logic_vector(3 downto 0);
+signal CSDi   : std_logic;
+signal CSDii  : std_logic_vector(3 downto 0);
+signal CSDiii : std_logic_vector(3 downto 0);
+signal CSEi   : std_logic;
+signal CSEii  : std_logic_vector(3 downto 0);
+signal REFCNT : std_logic_vector(10 downto 0);
+signal PA : std_logic;
+signal PB : std_logic;
+signal PC : std_logic;
+signal PD : std_logic;
+signal PE : std_logic;
+signal WB : std_logic;
+signal DAIR : std_logic_vector(15 downto 0);
+signal DAOR : std_logic_vector(15 downto 0);
+signal DBIR : std_logic_vector(31 downto 0);
+signal DCIR : std_logic_vector(15 downto 0);
+signal DDIR : std_logic_vector(15 downto 0);
+signal DDOR : std_logic_vector(15 downto 0);
+signal DEIR : std_logic_vector(31 downto 0);
+signal WAITB : std_logic;
+signal RDEN : std_logic;
+signal WREN : std_logic;
+signal UBEN : std_logic;
+signal LBEN : std_logic;
+signal UBEN2 : std_logic;
+signal LBEN2 : std_logic;
+signal RWAIT : std_logic;
+signal MEMCLK : std_logic;
+signal SCLK : std_logic;
+--
+-- State Machine
+--
+signal CUR : std_logic_vector(5 downto 0);						-- Current Status
+signal NXT : std_logic_vector(5 downto 0);						-- Next Status
+constant IWAIT  : std_logic_vector(5 downto 0) := "000000";	-- 200us Wait
+constant IPALL  : std_logic_vector(5 downto 0) := "000001";	-- All Bank Precharge
+constant IDLY1  : std_logic_vector(5 downto 0) := "000010";	-- Initial Delay 1
+constant IRFSH  : std_logic_vector(5 downto 0) := "000011";	-- Auto Refresh
+constant IDLY2  : std_logic_vector(5 downto 0) := "000100";	-- Initial Delay 2
+constant IDLY3  : std_logic_vector(5 downto 0) := "000101";	-- Initial Delay 3
+constant IDLY4  : std_logic_vector(5 downto 0) := "000110";	-- Initial Delay 4
+constant IDLY5  : std_logic_vector(5 downto 0) := "000111";	-- Initial Delay 5
+constant IDLY6  : std_logic_vector(5 downto 0) := "001000";	-- Initial Delay 6
+constant IMODE  : std_logic_vector(5 downto 0) := "001001";	-- Mode Register Setting
+constant RACT   : std_logic_vector(5 downto 0) := "001010";	-- Read Activate
+constant RDLY1  : std_logic_vector(5 downto 0) := "001011";	-- Read Delay 1
+constant READ   : std_logic_vector(5 downto 0) := "001100";	-- Read
+constant READ2  : std_logic_vector(5 downto 0) := "001101";	-- Read 2nd word
+constant RDLY2  : std_logic_vector(5 downto 0) := "001110";	-- Read Delay 2
+constant RDLY3  : std_logic_vector(5 downto 0) := "001111";	-- Read Delay 3
+constant RPRE   : std_logic_vector(5 downto 0) := "010000";	-- Precharge
+constant RDLY4  : std_logic_vector(5 downto 0) := "010001";	-- Read Delay 4
+constant HALT   : std_logic_vector(5 downto 0) := "010010";	--	Waiting
+constant WACT   : std_logic_vector(5 downto 0) := "010011";	-- Write Activate
+constant WDLY1  : std_logic_vector(5 downto 0) := "010100";	-- Write Delay 1
+constant WRIT   : std_logic_vector(5 downto 0) := "010101";	-- Write
+constant WRIT2  : std_logic_vector(5 downto 0) := "010110";	-- Write 2nd word
+constant WDLY2  : std_logic_vector(5 downto 0) := "010111";	-- Write Delay 2
+constant WDLY3  : std_logic_vector(5 downto 0) := "011000";	-- Write Delay 3
+constant WPRE   : std_logic_vector(5 downto 0) := "011001";	-- Precharge
+constant FRFSH  : std_logic_vector(5 downto 0) := "011010";	-- Auto Refresh
+constant FDLY1  : std_logic_vector(5 downto 0) := "011011";	-- Refresh Delay 1
+constant FDLY2  : std_logic_vector(5 downto 0) := "011100";	-- Refresh Delay 2
+constant FDLY3  : std_logic_vector(5 downto 0) := "011101";	-- Refresh Delay 3
+constant FDLY4  : std_logic_vector(5 downto 0) := "011110";	-- Refresh Delay 4
+--
+-- Components
+--
+component pll100
+	PORT
+	(
+		inclk0	: IN STD_LOGIC  := '0';
+		c0			: OUT STD_LOGIC ;
+		c1			: OUT STD_LOGIC ;
+		c2			: OUT STD_LOGIC ;
+		c3			: OUT STD_LOGIC 
+	);
+end component;
+
+begin
+
+	--
+	-- Instantiation
+	--
+	RCKGEN0 : pll100 PORT MAP (
+		inclk0	=> CLOCK_50,	-- Master Clock (50MHz) ... input
+		c0	 => MEMCLK,				-- SDRAM Controler Clock (100MHz) ... internal use
+		c1	 => MCLK,				-- SDRAM Clock (100MHz:-60deg) ... output
+		c2	 => PCLK,				-- Nios II Clock (20MHz) ... output
+		c3	 => SCLK					-- Slow Clock (31.25kHz) ... internal use/output
+	);
+
+	--
+	-- Seqence control
+	--
+	process( reset, MEMCLK ) begin
+		if reset='0' then
+			CUR<=IWAIT;			-- Start at Initial-Waiting(200us)
+		elsif MEMCLK'event and MEMCLK='1' then
+			CUR<=NXT;			-- Move to Next State
+		end if;
+	end process;
+
+	--
+	-- Arbitoration and Data Output
+	--
+	process( reset, MEMCLK ) begin
+		if reset='0' then
+			CSAi<='0';
+			CSBi<='0';
+			CSCi<='0';
+			CSDi<='0';
+			CSEi<='0';
+			CSAii<=(others=>'1');
+			CSBii<=(others=>'1');
+			CSCii<=(others=>'1');
+			CSDii<=(others=>'1');
+			CSEii<=(others=>'1');
+			PA<='0';
+			PB<='0';
+			PC<='0';
+			PD<='0';
+			PE<='0';
+			WAITB<='1';
+--			WAITD<='1';
+			RDEN<='0';
+			WREN<='0';
+			UBEN<='1';
+			LBEN<='1';
+			UBEN2<='1';
+			LBEN2<='1';
+			PGAi<='0';
+		elsif MEMCLK'event and MEMCLK='1' then
+			--
+			-- Sense CS
+			--
+			CSAii<=CSAii(2 downto 0)&CSMA;
+			if CSAii(1 downto 0)="10" then
+				CSAi<='1';
+				DAIR<=DAI&DAI;
+			end if;
+			CSBii<=CSBii(2 downto 0)&CSB;
+			if CSBii="1110" then
+				WAITB<='0';
+			end if;
+			if CSBii(1 downto 0)="10" then
+				CSBi<='1';
+				DBIR<=DBI;
+			end if;
+			CSCii<=CSCii(2 downto 0)&CSC;
+			if CSCii(1 downto 0)="10" then
+				CSCi<='1';
+				DCIR<=DCI;
+			end if;
+			CSDii<=CSDii(2 downto 0)&CSMD;
+			if CSDii(1 downto 0)="10" then
+				CSDi<='1';
+				DDIR(15 downto 8)<=DDI;
+			end if;
+			CSEii<=CSEii(2 downto 0)&CSE;
+			if CSEii(1 downto 0)="10" then
+				CSEi<='1';
+				DEIR<=DEI;
+			end if;
+
+			CSDiii<=CSDiii(2 downto 0)&CSD;
+			if CSDiii(1 downto 0)="10" and AD(0)='0' then
+				DDIR(7 downto 0)<=DDI;
+			end if;
+
+			--
+			-- Select Response Port
+			--
+			if CUR=HALT then
+				if CSAi='1' and PB='0' and PC='0' and PD='0' and PE='0' then
+					PA<='1';
+					RDEN<=WEA;
+					WREN<=not WEA;
+					UBEN<=(not AA(0)) and (not WEA);
+					LBEN<=AA(0) and (not WEA);
+					UBEN2<='1';
+					LBEN2<='1';
+				elsif CSCi='1' and PA='0' and PB='0' and PD='0' and PE='0' then
+					PC<='1';
+					RDEN<=WEC;
+					WREN<=not WEC;
+					UBEN<=BEC(1);
+					LBEN<=BEC(0);
+					UBEN2<='1';
+					LBEN2<='1';
+				elsif CSEi='1' and PA='0' and PB='0' and PC='0' and PD='0' then
+					PE<='1';
+					RDEN<=WEE;
+					WREN<=not WEE;
+					UBEN2<=BEE(3);
+					LBEN2<=BEE(2);
+					UBEN<=BEE(1);
+					LBEN<=BEE(0);
+				elsif CSDi='1' and PA='0' and PB='0' and PC='0' and PE='0' then
+					PD<='1';
+					RDEN<=WED;
+					WREN<=not WED;
+					UBEN<='0';
+					LBEN<='0';
+					UBEN2<='1';
+					LBEN2<='1';
+				elsif CSBi='1' and PA='0' and PC='0' and PD='0' and PE='0' then
+					PB<='1';
+					RDEN<=WEB;
+					WREN<=not WEB;
+					UBEN2<=BEB(3);
+					LBEN2<=BEB(2);
+					UBEN<=BEB(1);
+					LBEN<=BEB(0);
+				else
+					PA<='0'; PB<='0'; PC<='0'; PD<='0'; PE<='0';
+					RDEN<='0';
+					WREN<='0';
+					UBEN<='1';
+					LBEN<='1';
+					UBEN2<='1';
+					LBEN2<='1';
+				end if;
+			end if;
+
+			--
+			-- Deselect Port
+			--
+			if CUR=RPRE or CUR=WPRE then
+				if PA='1' then
+					PA<='0';
+					RDEN<='0';
+					WREN<='0';
+					CSAi<='0';
+				end if;
+				if PC='1' then
+					PC<='0';
+					RDEN<='0';
+					WREN<='0';
+					CSCi<='0';
+				end if;
+				if PD='1' then
+					PD<='0';
+					RDEN<='0';
+					WREN<='0';
+					CSDi<='0';
+				end if;
+			end if;
+			if CUR=RDLY4 or CUR=WPRE then
+				if PB='1' then
+					PB<='0';
+					RDEN<='0';
+					WREN<='0';
+					CSBi<='0';
+					WAITB<='1';
+				end if;
+				if PE='1' then
+					PE<='0';
+					RDEN<='0';
+					WREN<='0';
+					CSEi<='0';
+				end if;
+			end if;
+
+			--
+			-- Data Output for Processor
+			--
+			if CUR=RPRE then		-- Ready for Data Output
+				if PA='1' then
+					DAOR<=MDI;
+					RA<=A;
+					PGAi<='1';
+				elsif PB='1' then
+					DBO(15 downto 0)<=MDI;
+				elsif PC='1' then
+					DCO<=MDI;
+				elsif PD='1' then
+					DDOR<=MDI;
+					RD<=A;
+					PGDi<='1';
+				elsif PE='1' then
+					DEO(15 downto 0)<=MDI;
+				end if;
+			end if;
+			if CUR=RDLY4 then
+				if PB='1' then
+					DBO(31 downto 16)<=MDI;
+				elsif PE='1' then
+					DEO(31 downto 16)<=MDI;
+				end if;
+			end if;
+
+			--
+			-- Data Output for SDRAM
+			--
+			if CUR=WACT then
+				if PA='1' then
+					MDO<=DAIR;
+				elsif PB='1' then
+					MDO<=DBIR(15 downto 0);
+				elsif PC='1' then
+					MDO<=DCIR;
+				elsif PD='1' then
+					MDO<=DDIR;
+				elsif PE='1' then
+					MDO<=DEIR(15 downto 0);
+				end if;
+			elsif CUR=WRIT then
+				if PB='1' then
+					MDO<=DBIR(31 downto 16);
+				elsif PE='1' then
+					MDO<=DEIR(31 downto 16);
+				end if;
+			end if;
+
+			--
+			-- Purge Flag
+			--
+			if PGA='0' then
+				PGAi<='0';
+			end if;
+		end if;
+	end process;
+
+	--
+	-- Wait Control for NiosII
+	--
+	WQB<=CSB or WAITB;
+
+	--
+	-- Wait after Reset
+	--
+	process( reset, SCLK ) begin			-- SCLK=31.25kHz
+		if reset='0' then
+			WCNT<=(others=>'0');
+			CNT200<='0';
+		elsif SCLK'event and SCLK='1' then
+			if WCNT="110" then
+				CNT200<='1';
+			else
+				WCNT<=WCNT+1;
+			end if;
+		end if;
+	end process;
+
+	--
+	-- Refresh Times Counter for Initialize (8 times)
+	--
+	process( reset, MEMCLK ) begin
+		if reset='0' then
+			CNT3<=(others=>'0');
+		elsif MEMCLK'event and MEMCLK='1' then
+			if CUR=IWAIT then
+				CNT3<=(others=>'0');
+			elsif CUR=IDLY3 then
+				CNT3<=CNT3+1;
+			end if;
+		end if;
+	end process;
+
+	--
+	-- Refresh Cycle Counter
+	--
+	process( reset, MEMCLK ) begin
+		if reset='0' then
+			REFCNT<=(others=>'0');
+		elsif MEMCLK'event and MEMCLK='1' then
+			if CUR=FRFSH then				-- Enter Refresh Command
+				REFCNT<=(others=>'0');
+			else
+				REFCNT<=REFCNT+'1';
+			end if;
+		end if;
+	end process;
+
+	--
+	-- Sequencer
+	--
+	process( CUR, CNT200, CNT3, REFCNT, RDEN, WREN, PA, PB, PC, PD, PE ) begin
+		case CUR is
+			-- Initialize
+			when IWAIT =>	-- 200us Wait
+				if CNT200='1' then
+					NXT<=IPALL;
+				else
+					NXT<=IWAIT;
+				end if;
+			when IPALL =>	-- All Bank Precharge
+				NXT<=IDLY1;
+			when IDLY1 =>	-- Initial Delay 1
+				NXT<=IRFSH;
+			when IRFSH =>	-- Auto Refresh
+				NXT<=IDLY2;
+			when IDLY2 =>	-- Initial Delay 2
+				NXT<=IDLY3;
+			when IDLY3 =>	-- Initial Delay 2
+				NXT<=IDLY4;
+			when IDLY4 =>	-- Initial Delay 2
+				NXT<=IDLY5;
+			when IDLY5 =>	-- Initial Delay 2
+				NXT<=IDLY6;
+			when IDLY6 =>	-- Initial Delay 3
+				if CNT3="111" then
+					NXT<=IMODE;
+				else
+					NXT<=IDLY1;
+				end if;
+			when IMODE =>	-- Mode Register Setting
+				NXT<=HALT;
+
+			-- Read
+			when RACT  =>	-- Read Activate
+				NXT<=RDLY1;
+			when RDLY1 =>	-- Read Delay 1
+				NXT<=READ;
+			when READ   =>	-- Read once or 1st word
+				if PB='1' or PE='1' then
+					NXT<=READ2;
+				else
+					NXT<=RDLY2;
+				end if;
+			when READ2|RDLY2  =>	-- Read 2nd word / Read Delay 2
+				NXT<=RDLY3;
+			when RDLY3 =>	-- Read Delay 3
+				NXT<=RPRE;
+			when RPRE =>	-- Precharge
+				if PB='1' or PE='1' then
+					NXT<=RDLY4;
+				else
+					NXT<=HALT;
+				end if;
+			when RDLY4 =>	-- Read Delay 4
+				NXT<=HALT;
+
+			-- Waiting
+			when HALT  =>	--	Waiting
+				if REFCNT>"11000000100" then	-- Over 1540 Counts
+					NXT<=FRFSH;
+				elsif RDEN='1' then
+					NXT<=RACT;
+				elsif WREN='1' then
+					NXT<=WACT;
+				else
+					NXT<=HALT;
+				end if;
+
+			-- Write
+			when WACT  =>	-- Write Activate
+				NXT<=WDLY1;
+			when WDLY1 =>	-- Write Delay 1
+				NXT<=WRIT;
+			when WRIT   =>	-- Write once or 1st word
+				if PB='1' or PE='1' then
+					NXT<=WRIT2;
+				else
+					NXT<=WDLY2;
+				end if;
+			when WRIT2|WDLY2  =>	-- Write 2nd word / Write Delay 2
+				NXT<=WDLY3;
+			when WDLY3 =>	-- Write Delay 3
+				NXT<=WPRE;
+			when WPRE =>	-- Precharge
+				NXT<=HALT;
+
+			-- Refresh
+			when FRFSH =>	-- Auto Refresh
+				NXT<=FDLY1;
+			when FDLY1 =>	-- Refresh Delay 1
+				NXT<=FDLY2;
+			when FDLY2 =>	-- Refresh Delay 2
+				NXT<=FDLY3;
+			when FDLY3 =>	-- Refresh Delay 3
+				NXT<=FDLY4;
+			when FDLY4 =>	-- Refresh Delay 4
+				NXT<=HALT;
+
+			when others =>
+				NXT<=HALT;
+		end case;
+	end process;
+
+	--
+	-- Command operation
+	--
+	-- MA(11 downto 0)
+	process( CUR, A ) begin
+		case CUR is
+			when IMODE =>		-- Mode Register Setting
+				MA<="0010" & "0" & "011" & "0" & "000";	-- w-single,CL=3,WT=0(seq),BL=1
+				--MA<="0010" & "0" & "010" & "0" & "000";	-- w-single,CL=2,WT=0(seq),BL=1
+				--MA<="0010" & "0" & "010" & "0" & "001";	-- w-single,CL=2,WT=0(seq),BL=2
+			when RACT|WACT =>	-- Read/Write Activate
+				MA<=A(19 downto 8);
+			when IPALL =>		-- All Bank Precharge
+				MA<="010000000000";
+			when READ|WRIT =>			-- Read/Write
+				--MA(11 downto 8)<="0100";	-- auto precharge
+				MA(11 downto 8)<="0000";	-- manual precharge
+				MA(7 downto 0)<=A(7 downto 0);
+			when READ2|WRIT2 =>			-- Read/Write 2nd word
+				--MA(11 downto 8)<="0100";	-- auto precharge
+				MA(11 downto 8)<="0000";	-- manual precharge
+				MA(7 downto 0)<=A(7 downto 1)&'1';
+--			when RPRE|WPRE =>			-- Select Bank Precharge
+--				MA<="000000000000";
+			when others =>
+				MA<=(others=>'0');
+		end case;
+	end process;
+	-- LBEN/UBEN
+	process( CUR, LBEN, UBEN, LBEN2, UBEN2 ) begin
+		case CUR is
+			when READ2|RDLY2|WRIT =>	-- Read 2nd word/Read delay 2/Write
+				MLDQ<=LBEN;
+				MUDQ<=UBEN;
+			when RDLY3|WRIT2 =>			-- Read delay 3/Write 2nd word
+				MLDQ<=LBEN2;
+				MUDQ<=UBEN2;
+			when others =>
+				MLDQ<='1';
+				MUDQ<='1';
+		end case;
+	end process;
+	-- MDOE
+	process( CUR ) begin
+		case CUR is
+			when WRIT =>			-- Write
+				MDOE<='1';
+			when WRIT2 =>			-- Write 2nd word
+				MDOE<='1';
+			when others =>
+				MDOE<='0';
+		end case;
+	end process;
+	-- MWE
+	process( CUR ) begin
+		case CUR is
+			when IMODE =>		-- Mode Register Setting
+				MWE<='0';
+			when IPALL =>		-- All Bank Precharge
+				MWE<='0';
+			when WRIT =>			-- Write
+				MWE<='0';
+			when WRIT2 =>			-- Write 2nd word
+				MWE<='0';
+			when RPRE|WPRE =>			-- Select Bank Precharge
+				MWE<='0';
+			when others =>
+				MWE<='1';
+		end case;
+	end process;
+	-- MCS
+	process( CUR ) begin
+		case CUR is
+			when IMODE =>		-- Mode Register Setting
+				MCS<='0';
+			when RACT|WACT =>	-- Read/Write Activate
+				MCS<='0';
+			when IPALL =>		-- All Bank Precharge
+				MCS<='0';
+			when READ =>			-- Read
+				MCS<='0';
+			when READ2 =>			-- Read 2nd word
+				MCS<='0';
+			when WRIT =>			-- Write
+				MCS<='0';
+			when WRIT2 =>			-- Write 2nd word
+				MCS<='0';
+			when IRFSH|FRFSH =>		-- auto refresh
+				MCS<='0';
+			when RPRE|WPRE =>			-- Select Bank Precharge
+				MCS<='0';
+			when others =>
+				MCS<='1';
+		end case;
+	end process;
+	-- MRAS/MCAS
+	process( CUR ) begin
+		case CUR is
+			when IMODE =>		-- Mode Register Setting
+				MRAS<='0';
+				MCAS<='0';
+			when RACT|WACT =>	-- Read/Write Activate
+				MRAS<='0';
+				MCAS<='1';
+			when IPALL =>		-- All Bank Precharge
+				MRAS<='0';
+				MCAS<='1';
+			when READ =>			-- Read
+				MRAS<='1';
+				MCAS<='0';
+			when READ2 =>			-- Read 2nd word
+				MRAS<='1';
+				MCAS<='0';
+			when WRIT =>			-- Write
+				MRAS<='1';
+				MCAS<='0';
+			when WRIT2 =>			-- Write 2nd word
+				MRAS<='1';
+				MCAS<='0';
+			when IRFSH|FRFSH =>		-- auto refresh
+				MRAS<='0';
+				MCAS<='0';
+			when RPRE|WPRE =>			-- Select Bank Precharge
+				MRAS<='0';
+				MCAS<='1';
+			when others =>
+				MRAS<='1';
+				MCAS<='1';
+		end case;
+	end process;
+
+	--
+	-- Reset Control
+	--
+	process( reset, MEMCLK ) begin
+		if reset='0' then
+			RSTOUT<='0';
+		elsif MEMCLK'event and MEMCLK='1' then
+			if CUR=HALT then
+				RSTOUT<='1';
+			end if;
+		end if;
+	end process;
+
+	--
+	-- SDRAM ports(Fixed Signals)
+	--
+	MCKE<='1';
+	MBA0<=A(20);
+	MBA1<=A(21);
+
+	--
+	-- Ports select
+	--
+	A <=AA(22 downto 1) when PA='1' else
+		 AB&'0'			  when PB='1' else
+		 AC				  when PC='1' else
+		 AD(22 downto 1) when PD='1' else
+		 AE&'0'			  when PE='1' else (others=>'0');
+	DAO<=DAOR(15 downto 8) when AA(0)='1' else DAOR(7 downto 0);
+	CSMA<=(CSA or WEA) when RA=AA(22 downto 1) and PGAi='1' else CSA;
+	DDO<=DDOR(15 downto 8) when AD(0)='1' else DDOR(7 downto 0);
+	CSMD<=CSD when (AD(0)='0' and WED='1') or (AD(0)='1' and WED='0') else '1';
+--	process(RA, AA(22 downto 1), PGAi, CSA, WEA) begin
+--		if RA=AA(22 downto 1) then
+--			if PGAi='0' then
+--				CSMA<=CSA;
+--			else
+--				if WEA='0' then
+--					CSMA<=CSA;
+--				else
+--					CSMA<='1';
+--				end if;
+--			end if;
+--		else
+--			CSMA<=CSA;
+--		end if;
+--	end process;
+
+end rtl;
diff --git a/mz80b/old/seg7.vhd b/mz80b/old/seg7.vhd
new file mode 100644
index 0000000..d7be83f
--- /dev/null
+++ b/mz80b/old/seg7.vhd
@@ -0,0 +1,174 @@
+--
+-- 7seg.vhd
+--
+-- 4-digit 7-segment LED decorder
+-- for MZ-80B on FPGA
+--
+-- Nibbles Lab. 2013
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity seg7 is
+	Port (
+		-- 7-SEG Dispaly
+		HEX0_D  : out std_logic_vector(6 downto 0);	--	Seven Segment Digit 0
+		HEX0_DP : out std_logic;							--	Seven Segment Digit DP 0
+		HEX1_D  : out std_logic_vector(6 downto 0);	--	Seven Segment Digit 1
+		HEX1_DP : out std_logic;							--	Seven Segment Digit DP 1
+		HEX2_D  : out std_logic_vector(6 downto 0);	--	Seven Segment Digit 2
+		HEX2_DP : out std_logic;							--	Seven Segment Digit DP 2
+		HEX3_D  : out std_logic_vector(6 downto 0);	--	Seven Segment Digit 3
+		HEX3_DP : out std_logic;							--	Seven Segment Digit DP 3
+		-- Status Signal
+		MZMODE  : in std_logic;								-- Hardware Mode
+																	-- "0" .. MZ-80B
+																	-- "1" .. MZ-2000
+		DMODE   : in std_logic;								-- Display Mode
+																	-- "0" .. Green
+																	-- "1" .. Color
+		SCLK	  : in std_logic;
+		APSS	  : in std_logic;
+		FF		  : in std_logic;
+		REW	  : in std_logic;
+		NUMEN	  : in std_logic;
+		NUMBER  : in std_logic_vector(15 downto 0)
+	);
+end seg7;
+
+architecture RTL of seg7 is
+
+signal TCNT : std_logic_vector(2 downto 0) := "000";
+signal DCNT : std_logic_vector(12 downto 0) := "0000000000000";
+
+begin
+
+	HEX3_D<= "1111111" when APSS='0' and NUMEN='0' and MZMODE='0' else							-- " "
+				"0100100" when APSS='0' and NUMEN='0' and MZMODE='1' else							-- "2"
+				"1000000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"0" else		-- "0"
+				"1111001" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"1" else		-- "1"
+				"0100100" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"2" else		-- "2"
+				"0110000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"3" else		-- "3"
+				"0011001" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"4" else		-- "4"
+				"0010010" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"5" else		-- "5"
+				"0000010" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"6" else		-- "6"
+				"1011000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"7" else		-- "7"
+				"0000000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"8" else		-- "8"
+				"0010000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"9" else		-- "9"
+				"0001000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"a" else		-- "A"
+				"0000011" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"b" else		-- "b"
+				"1000110" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"c" else		-- "C"
+				"0100001" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"d" else		-- "d"
+				"0000110" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"e" else		-- "E"
+				"0001110" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"f" else		-- "F"
+				"1000111" when APSS='1' and TCNT="010" else		-- "["
+				"1100110" when APSS='1' and TCNT="011" else		-- "["
+				"1010110" when APSS='1' and TCNT="100" else		-- "["
+				"1001110" when APSS='1' and TCNT="101" else		-- "["
+				"1000110" when APSS='1' else		-- "["
+				"1111111";
+	HEX3_DP<='1';
+
+	HEX2_D<= "0000000" when APSS='0' and NUMEN='0' and MZMODE='0' else							-- "8"
+				"1000000" when APSS='0' and NUMEN='0' and MZMODE='1' and DMODE='0' else		-- "0"
+				"0100100" when APSS='0' and NUMEN='0' and MZMODE='1' and DMODE='1' else		-- "2"
+				"1000000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"0" else		-- "0"
+				"1111001" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"1" else		-- "1"
+				"0100100" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"2" else		-- "2"
+				"0110000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"3" else		-- "3"
+				"0011001" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"4" else		-- "4"
+				"0010010" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"5" else		-- "5"
+				"0000010" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"6" else		-- "6"
+				"1011000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"7" else		-- "7"
+				"0000000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"8" else		-- "8"
+				"0010000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"9" else		-- "9"
+				"0001000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"a" else		-- "A"
+				"0000011" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"b" else		-- "b"
+				"1000110" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"c" else		-- "C"
+				"0100001" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"d" else		-- "d"
+				"0000110" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"e" else		-- "E"
+				"0001110" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"f" else		-- "F"
+				"1111110" when APSS='1' and TCNT="110" else		-- "~"
+				"1110111" when APSS='1' and TCNT="001" else		-- "_"
+				"1110110" when APSS='1' else		-- "="
+				"1111111";
+	HEX2_DP<='1';
+
+	HEX1_D<= "1000000" when APSS='0' and NUMEN='0' else												-- "0"
+				"1000000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"0" else		-- "0"
+				"1111001" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"1" else		-- "1"
+				"0100100" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"2" else		-- "2"
+				"0110000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"3" else		-- "3"
+				"0011001" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"4" else		-- "4"
+				"0010010" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"5" else		-- "5"
+				"0000010" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"6" else		-- "6"
+				"1011000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"7" else		-- "7"
+				"0000000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"8" else		-- "8"
+				"0010000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"9" else		-- "9"
+				"0001000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"a" else		-- "A"
+				"0000011" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"b" else		-- "b"
+				"1000110" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"c" else		-- "C"
+				"0100001" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"d" else		-- "d"
+				"0000110" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"e" else		-- "E"
+				"0001110" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"f" else		-- "F"
+				"1111110" when APSS='1' and TCNT="001" else		-- "~"
+				"1110111" when APSS='1' and TCNT="110" else		-- "_"
+				"1110110" when APSS='1' else		-- "="
+				"1111111";
+	HEX1_DP<='1';
+
+	HEX0_D<= "0000011" when APSS='0' and NUMEN='0' and MZMODE='0' else							-- "b"
+				"1000000" when APSS='0' and NUMEN='0' and MZMODE='1' else							-- "0"
+				"1000000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"0" else		-- "0"
+				"1111001" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"1" else		-- "1"
+				"0100100" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"2" else		-- "2"
+				"0110000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"3" else		-- "3"
+				"0011001" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"4" else		-- "4"
+				"0010010" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"5" else		-- "5"
+				"0000010" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"6" else		-- "6"
+				"1011000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"7" else		-- "7"
+				"0000000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"8" else		-- "8"
+				"0010000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"9" else		-- "9"
+				"0001000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"a" else		-- "A"
+				"0000011" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"b" else		-- "b"
+				"1000110" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"c" else		-- "C"
+				"0100001" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"d" else		-- "d"
+				"0000110" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"e" else		-- "E"
+				"0001110" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"f" else		-- "F"
+				"1111000" when APSS='1' and TCNT="010" else
+				"1110100" when APSS='1' and TCNT="011" else
+				"1110010" when APSS='1' and TCNT="100" else
+				"1110001" when APSS='1' and TCNT="101" else
+				"1110000" when APSS='1' else		-- "]"
+				"1111111";
+	HEX0_DP<='0' when NUMEN='0' and DMODE='1' else '1';
+
+	process( SCLK ) begin
+		if SCLK'event and SCLK='1' then
+			if DCNT="0011100010000" then
+				DCNT<=(others=>'0');
+				if FF=REW then
+					TCNT<="000";
+				elsif FF='1' and REW='0' then
+					if TCNT="110" then
+						TCNT<="001";
+					else
+						TCNT<=TCNT+'1';
+					end if;
+				elsif REW='1' and FF='0' then
+					if TCNT(2 downto 1)="00" then
+						TCNT<="110";
+					else
+						TCNT<=TCNT-'1';
+					end if;
+				end if;
+			else
+				DCNT<=DCNT+'1';
+			end if;
+		end if;
+	end process;
+
+end RTL;
diff --git a/mz80b/sysctrl.vhd b/mz80b/sysctrl.vhd
new file mode 100644
index 0000000..dede7de
--- /dev/null
+++ b/mz80b/sysctrl.vhd
@@ -0,0 +1,195 @@
+--
+-- sysctrl.vhd
+--
+-- SHARP MZ-80B/2000 series compatible logic, system control module
+-- for Altera DE0
+--
+-- Nibbles Lab. 2014
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sysctrl is
+  port(
+        RST_n                : in  std_logic;                            -- Reset
+        CLK                  : in  std_logic;                            -- System Clock
+        -- Push Button
+        BUTTON               : in std_logic_vector(2 downto 0);          -- Pushbutton[2:0]
+        -- Switch
+        SW                   : in std_logic_vector(9 downto 0);          -- Toggle Switch[9:0]
+        -- PS/2 Keyboard Data
+        KBEN                 : in std_logic;                             -- PS/2 Keyboard Data Valid
+        KBDT                 : in std_logic_vector(7 downto 0);          -- PS/2 Keyboard Data
+        -- Interrupt
+        INTL                 : out std_logic;                            -- Interrupt Signal Output
+        I_CMT                : in std_logic;                             -- from CMT
+        I_FDD                : in std_logic;                             -- from FD unit
+        -- Others
+        URST_n               : out std_logic;                            -- Universal Reset
+        ARST_n               : out std_logic;                            -- All Reset
+        ZRST                 : out std_logic;                            -- Z80 Reset
+        CLK50                : in std_logic;                             -- 50MkHz
+        SCLK                 : in std_logic;                             -- 31.25kHz
+        ZBREQ                : out std_logic;                            -- Z80 Bus Request
+        ZBACK                : in std_logic;                             -- Z80 Bus Acknowridge
+        BST_n                : in std_logic;                             -- BOOT start request from Z80
+        BOOTM                : out std_logic;                            -- BOOT mode
+        F_BTN                : out std_logic                             -- Function Button
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_INDEX          : in  std_logic_vector(7 downto 0);         -- Menu index used to upload file.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(15 downto 0)         -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(15 downto 0);        -- HPS Data to be read into HPS.
+        IOCTL_INTERRUPT      : out std_logic                             -- HPS Interrupt.
+  );
+end sysctrl;
+
+architecture rtl of sysctrl is
+
+--
+-- Reset & Filters
+--
+signal URSTi                 : std_logic;                                -- Universal Reset
+signal BUF                   : std_logic_vector(7 downto 0) := "00000000";
+signal CNT5                  : std_logic_vector(4 downto 0);
+signal SR_BTN                : std_logic_vector(7 downto 0);
+signal ZR_BTN                : std_logic_vector(7 downto 0);
+signal F_BTNi                : std_logic;
+--
+-- Interrupt
+--
+signal IRQ_KB                : std_logic;
+signal IE_KB                 : std_logic;
+signal IKBBUF                : std_logic_vector(2 downto 0);
+signal IRQ_FB                : std_logic;
+signal IE_FB                 : std_logic;
+signal IFBBUF                : std_logic_vector(2 downto 0);
+signal IRQ_CT                : std_logic;
+signal IE_CT                 : std_logic;
+signal ICTBUF                : std_logic_vector(2 downto 0);
+signal IRQ_FD                : std_logic;
+signal IE_FD                 : std_logic;
+signal IFDBUF                : std_logic_vector(2 downto 0);
+--
+-- Control for Z80
+--
+signal ZRSTi                 : std_logic;
+signal BOOTMi                : std_logic := '1';
+
+begin
+
+    --
+    -- Avalon Bus
+    --
+    process( RST_n, CLK ) begin
+        if RST_n='0' then
+            IRQ_KB   <= '0';
+            IRQ_FB   <= '0';
+            IRQ_CT   <= '0';
+            IRQ_FD   <= '0';
+            IKBBUF   <= (others=>'0');
+            IFBBUF   <= (others=>'0');
+            ICTBUF   <= (others=>'0');
+            IFDBUF   <= (others=>'0');
+            IE_KB    <= '0';
+            IE_FB    <= '0';
+            IE_CT    <= '0';
+            IE_FD    <= '0';
+            ZBREQ    <= '1';
+            BOOTMi   <= '1';
+            ZRSTi    <= '0';
+        elsif CLK'event and CLK='1' then
+            -- Edge Sense
+            IKBBUF<=IKBBUF(1 downto 0)&(KBEN and ((not ZBACK) or BOOTMi));
+            if IKBBUF(2 downto 1)="01" then
+                IRQ_KB      <= IE_KB;
+            end if;
+            IFBBUF          <= IFBBUF(1 downto 0)&F_BTNi;
+            if IFBBUF(2 downto 1)="01" then
+                IRQ_FB      <= IE_FB;
+            end if;
+            ICTBUF          <= ICTBUF(1 downto 0)&I_CMT;
+            if ICTBUF(2 downto 1)="01" then
+                IRQ_CT      <= IE_CT;
+            end if;
+            IFDBUF          <= IFDBUF(1 downto 0)&I_FDD;
+            if IFDBUF(2 downto 1)="01" then
+                IRQ_FD      <= IE_FD;
+            end if;
+            -- Register
+            if IOCTL_RD='1' and IOCTL_WR='1' then
+                if IOCTL_ADDR=X"0005" then    -- MZ_SYS_IREQ
+                    IRQ_KB  <= IRQ_KB and (not IOCTL_DOUT(0));    -- I_KBD 0x01
+                    IRQ_FB  <= IRQ_FB and (not IOCTL_DOUT(1));    -- I_FBTN 0x02
+                    IRQ_CT  <= IRQ_CT and (not IOCTL_DOUT(2));    -- I_CMT 0x04
+                    IRQ_FD  <= IRQ_FD and (not IOCTL_DOUT(3));    -- I_FDD 0x08
+                end if;
+                if IOCTL_ADDR=X"0006" then    -- MZ_SYS_IENB
+                    IE_KB   <= IOCTL_DOUT(0);    -- I_KBD 0x01
+                    IE_FB   <= IOCTL_DOUT(1);    -- I_FBTN 0x02
+                    IE_CT   <= IOCTL_DOUT(2);    -- I_CMT 0x04
+                    IE_FD   <= IOCTL_DOUT(3);    -- I_FDD 0x08
+                end if;
+                if IOCTL_ADDR=X"0007" then    -- MZ_SYS_CTRL (Control for Z80)
+                    ZBREQ   <= IOCTL_DOUT(0);
+                    ZRSTi   <= IOCTL_DOUT(1);
+                    BOOTMi  <= IOCTL_DOUT(2);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    IOCTL_DIN <= "00000"&BUTTON                     when IOCTL_RD='1' and IOCTL_ADDR=X"0000" else    -- MZ_SYS_BUTTON
+                 SW(7 downto 0)                     when IOCTL_RD='1' and IOCTL_ADDR=X"0002" else    -- MZ_SYS_SW70
+                 "000000"&SW(9)&SW(8)               when IOCTL_RD='1' and IOCTL_ADDR=X"0003" else    -- MZ_SYS_SW98
+                 KBDT                               when IOCTL_RD='1' and IOCTL_ADDR=X"0004" else    -- MZ_SYS_KBDT
+                 "0000"&IRQ_FD&IRQ_CT&IRQ_FB&IRQ_KB when IOCTL_RD='1' and IOCTL_ADDR=X"0005" else    -- MZ_SYS_IREQ
+                 "0000"&IE_FD&IE_CT&IE_FB&IE_KB     when IOCTL_RD='1' and IOCTL_ADDR=X"0006" else    -- MZ_SYS_IENB
+                 "000000"&(not BST_n)&ZBACK         when IOCTL_RD='1' and IOCTL_ADDR=X"0007" else    -- MZ_SYS_STATUS
+                 "00000000";
+
+    INTL <= IRQ_KB or IRQ_FB or IRQ_CT or IRQ_FD;
+
+    --
+    -- Filter and Asynchronous Reset with automatic
+    --
+    URST_n <= URSTi;
+    process( CLK50 ) begin
+        if( CLK50'event and CLK50='1' ) then
+            if BUF=X"80" then
+                URSTi  <= '1';
+            else
+                BUF    <= BUF+'1';
+                URSTi  <= '0';
+            end if;
+        end if;
+    end process;
+
+    process( URSTi, SCLK ) begin
+        if URSTi='0' then
+            CNT5       <= (others=>'0');
+            SR_BTN     <= (others=>'1');
+            ZR_BTN     <= (others=>'1');
+        elsif SCLK'event and SCLK='1' then
+            if CNT5="11111" then
+                SR_BTN <= SR_BTN(6 downto 0)&(BUTTON(1) or (not BUTTON(0)));    -- only BUTTON1
+                ZR_BTN <= ZR_BTN(6 downto 0)&((not BUTTON(1)) or BUTTON(0));    -- only BUTTON0
+                CNT5   <= (others=>'0');
+            else
+                CNT5<=CNT5+'1';
+            end if;
+        end if;
+    end process;
+    F_BTNi  <= '1' when SR_BTN="00000000" else '0';
+    F_BTN   <= F_BTNi;
+    ARST_n  <= URSTi ;
+    ZRST    <= '0' when (ZR_BTN="00000000" and ZBACK='1') or ZRSTi='0' or URSTi='0' else '1';
+
+    BOOTM   <= BOOTMi;
+
+end rtl;
diff --git a/mz80c/mz80c.vhd b/mz80c/mz80c.vhd
new file mode 100644
index 0000000..af403f4
--- /dev/null
+++ b/mz80c/mz80c.vhd
@@ -0,0 +1,886 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            mz80c.vhd
+-- Created:         July 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series Personal Computer:
+--                                  Models MZ-80K, MZ-80C, MZ-1200, MZ-80A, MZ-700, MZ-800
+--
+--                  This module is the main (top level) container for the Personal MZ Computer
+--                  Emulation.
+--
+--                  The design tries to work from top-down, where components which are common 
+--                  to the Business and Personal MZ series are at the top (ie. main memory,
+--                  ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
+--                  to the machine specific modules and components. Some components are common
+--                  by their nature (ie. 8255 PIO) but these are instantiated within the lower
+--                  tree branch as their design use is less generic.
+--
+--                  The tree is as follows;-
+--
+--                                      (emu) sharpmz.vhd (mz80c)	->	mz80c.vhd
+--                                      |
+--                                      |
+--                                      |                                         -> cmt.vhd                   (common)
+--                                      |                                         -> keymatrix.vhd             (common)
+--                                      |                                         -> pll.v                     (common)
+--                                      |                                         -> clkgen.vhd                (common)
+--                                      |                                         -> T80                       (common)
+--                                      |                                         -> i8255                     (common)
+--                  sys_top.sv (emu) ->	(emu) sharpmz.vhd (hps_io) -> hps_io.sv
+--                                      |                                         -> i8254                     (common)
+--                                      |                                         -> dpram.vhd                 (common)
+--                                      |                                         -> dprom.vhd                 (common)
+--                                      |                                         -> mctrl.vhd                 (common)
+--                                      |                                         -> video.vhd                 (common)
+--                                      |
+--                                      |
+--                                      (emu) sharpmz.vhd (mz80b)	->	mz80b.vhd   
+--
+--
+--
+-- Credits:         
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2018   - Initial module written.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity mz80c is
+    PORT (
+          -- Clocks
+          CLKBUS             : in  std_logic_vector(CLKBUS_WIDTH);    -- Clock signals created by clkgen module.
+
+          -- Resets.
+          COLD_RESET         : in  std_logic;
+          SYSTEM_RESET       : in  std_logic;
+          
+          -- Z80 CPU
+          T80_RST_n          : in  std_logic;
+          T80_WAIT_n         : out std_logic;
+          T80_INT_n          : out std_logic;
+          T80_NMI_n          : out std_logic;
+          T80_BUSRQ_n        : out std_logic;
+          T80_M1_n           : in  std_logic;
+          T80_MREQ_n         : in  std_logic;
+          T80_IORQ_n         : in  std_logic;
+          T80_RD_n           : in  std_logic;
+          T80_WR_n           : in  std_logic;
+          T80_RFSH_n         : in  std_logic;
+          T80_HALT_n         : in  std_logic;
+          T80_BUSAK_n        : in  std_logic;
+          T80_A16            : in  std_logic_vector(15 downto 0);
+          T80_DI             : out std_logic_vector(7 downto 0);
+          T80_DO             : in  std_logic_vector(7 downto 0);
+
+          -- Chip selects to common resources.
+          CS_ROM_n           : out std_logic;                            -- ROM Select
+          CS_RAM_n           : out std_logic;                            -- RAM Select
+          CS_VRAM_n          : out std_logic;                            -- VRAM Select
+          CS_MEM_G_n         : out std_logic;                            -- Memory Peripherals Select
+          CS_GRAM_n          : out std_logic;                            -- GRAM Select
+          CS_IO_GFB_n        : out std_logic;                            -- Graphics Framebuffer IO Select range
+
+          -- Audio.
+          AUDIO_L            : out std_logic;
+          AUDIO_R            : out std_logic;
+
+          -- Different operations modes.
+          CONFIG             : in  std_logic_vector(CONFIG_WIDTH);
+
+          -- I/O                                                         -- I/O down to the core.
+          KEYB_SCAN          : out std_logic_vector(3 downto 0);         -- Keyboard scan lines out.
+          KEYB_DATA          : in  std_logic_vector(7 downto 0);         -- Keyboard scan data in.
+          KEYB_STALL         : out std_logic;                            -- Keyboard Stall out.
+
+          -- Cassette magnetic tape signals.
+          CMT_BUS_OUT        : in  std_logic_vector(CMT_BUS_OUT_WIDTH);
+          CMT_BUS_IN         : out std_logic_vector(CMT_BUS_IN_WIDTH);
+
+          -- Video signals
+          VGATE_n            : out std_logic;                            -- Video Gate enable.
+          HBLANK             : in  std_logic;                            -- Horizontal Blanking Signal
+          VBLANK             : in  std_logic;                            -- Vertical Blanking Signal
+
+          -- HPS Interface
+          IOCTL_DOWNLOAD     : in  std_logic;                            -- HPS Downloading to FPGA.
+          IOCTL_UPLOAD       : in  std_logic;                            -- HPS Uploading from FPGA.
+          IOCTL_CLK          : in  std_logic;                            -- HPS I/O Clock.
+          IOCTL_WR           : in  std_logic;                            -- HPS Write Enable to FPGA.
+          IOCTL_RD           : in  std_logic;                            -- HPS Read Enable from FPGA.
+          IOCTL_ADDR         : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+          IOCTL_DOUT         : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+          IOCTL_DIN          : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+          -- Debug Status Leds
+          DEBUG_STATUS_LEDS  : out std_logic_vector(111 downto 0)        -- 112 leds to display status.
+    );
+end mz80c;
+
+architecture rtl of mz80c is
+
+--
+-- Buffered output signals.
+--
+signal BLNK_n                :     std_logic;
+
+-- Parent signals.
+--
+signal MZ_RESET              :     std_logic;
+signal MZ_MEMORY_SWAP        :     std_logic;
+signal MZ_LOW_RAM_ENABLE     :     std_logic;
+signal MZ_HIGH_RAM_ENABLE    :     std_logic;
+signal MZ_HIGH_RAM_INHIBIT   :     std_logic;
+signal MZ_INHIBIT_RESET      :     std_logic;
+signal MZ_GRAM_ENABLE        :     std_logic;
+signal i8255_PA_I            :     std_logic_vector(7 downto 0);
+signal i8255_PA_O            :     std_logic_vector(7 downto 0);
+signal i8255_PA_OE_n         :     std_logic_vector(7 downto 0);
+signal i8255_PB_I            :     std_logic_vector(7 downto 0);
+signal i8255_PB_O            :     std_logic_vector(7 downto 0);
+signal i8255_PC_I            :     std_logic_vector(7 downto 0);
+signal i8255_PC_O            :     std_logic_vector(7 downto 0);
+signal i8255_PC_OE_n         :     std_logic_vector(7 downto 0);
+--
+-- System Clocks
+--
+signal MZ_RTC_CASCADE_CLK    :     std_logic;                            -- i8254 subdivision of the 31.250KHz clock creating 1s/1Hz timebase.
+--
+-- Decodes, misc
+--
+signal CS_VRAM_ni            :     std_logic;
+signal CS_E_ni               :     std_logic;
+signal CS_E0_n               :     std_logic;
+signal CS_E1_n               :     std_logic;
+signal CS_E2_n               :     std_logic;
+signal CS_ESWP_n             :     std_logic;
+signal CS_GRAM_ni            :     std_logic;
+signal DO367                 :     std_logic_vector(7 downto 0);
+signal CS_BANKSWITCH_n       :     std_logic;
+signal CS_MZ700BS_n          :     std_logic;
+signal CS_IO_E0_n            :     std_logic;
+signal CS_IO_E1_n            :     std_logic;
+signal CS_IO_E2_n            :     std_logic;
+signal CS_IO_E3_n            :     std_logic;
+signal CS_IO_E4_n            :     std_logic;
+signal CS_IO_E5_n            :     std_logic;
+signal CS_IO_E6_n            :     std_logic;
+signal CS_IO_GRAMENABLE_n    :     std_logic;
+signal CS_IO_GRAMDISABLE_n   :     std_logic;
+signal CS_IO_GFB_ni          :     std_logic;
+signal CS_ROM_ni             :     std_logic;
+signal CS_RAM_ni             :     std_logic;
+signal VGATE_ni              :     std_logic;                               -- Video Output Enable
+signal T80_IWR_n             :     std_logic;
+signal T80_INT_ni            :     std_logic;
+--
+-- PPI
+--
+signal DOPPI                 :     std_logic_vector(7 downto 0);
+signal INTMSK                :     std_logic;                               -- EISUU/KANA LED
+--
+-- PIT
+--
+signal DOPIT                 :     std_logic_vector(7 downto 0);
+signal SOUND_ENABLE          :     std_logic;
+signal SOUND_PULSE_X2        :     std_logic;
+signal SOUND                 :     std_logic;
+signal INTX                  :     std_logic;
+--
+-- CURSOR blink
+--
+signal CURSOR_RESET          :     std_logic;
+signal CURSOR_CLK            :     std_logic;
+signal CURSOR_BLINK          :     std_logic;
+signal CCOUNT                :     std_logic_vector(4 downto 0);
+--
+-- Remote
+--
+signal SNS                   :     std_logic;
+signal MTR                   :     std_logic;
+signal M_ON                  :     std_logic;
+signal SENSE0                :     std_logic;
+signal SWIN                  :     std_logic_vector(3 downto 0);
+--
+-- Debug
+--
+signal PULSECPU              :     std_logic; 
+
+--
+-- Components
+--
+component i8255
+    port (
+        RESET                : in  std_logic;
+        CLK                  : in  std_logic;
+        ENA                  : in  std_logic; -- (CPU) clk enable
+        ADDR                 : in  std_logic_vector(1 downto 0); -- A1-A0
+        DI                   : in  std_logic_vector(7 downto 0); -- D7-D0
+        DO                   : out std_logic_vector(7 downto 0);
+        CS_n                 : in  std_logic;
+        RD_n                 : in  std_logic;
+        WR_n                 : in  std_logic;
+    
+        PA_I                 : in  std_logic_vector(7 downto 0);
+        PA_O                 : out std_logic_vector(7 downto 0);
+        PA_O_OE_n            : out std_logic_vector(7 downto 0);
+    
+        PB_I                 : in  std_logic_vector(7 downto 0);
+        PB_O                 : out std_logic_vector(7 downto 0);
+        PB_O_OE_n            : out std_logic_vector(7 downto 0);
+    
+        PC_I                 : in  std_logic_vector(7 downto 0);
+        PC_O                 : out std_logic_vector(7 downto 0);
+        PC_O_OE_n            : out std_logic_vector(7 downto 0)
+    );
+end component;
+
+component i8254
+ Port (
+        RST                  : in  std_logic;
+        CLK                  : in  std_logic;
+        ENA                  : in  std_logic;
+        A                    : in  std_logic_vector(1 downto 0);
+        DI                   : in  std_logic_vector(7 downto 0);
+        DO                   : out std_logic_vector(7 downto 0);
+        CS_n                 : in  std_logic;
+        WR_n                 : in  std_logic;
+        RD_n                 : in  std_logic;
+        CLK0                 : in  std_logic;
+        GATE0                : in  std_logic;
+        OUT0                 : out std_logic;
+        CLK1                 : in  std_logic;
+        GATE1                : in  std_logic;
+        OUT1                 : out std_logic;
+        CLK2                 : in  std_logic;
+        GATE2                : in  std_logic;
+        OUT2                 : out std_logic
+  );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    -- 8255 PPI used for Tape control and interfacing, Keyboard input
+    -- and Video/Sound control.
+    --
+    PPI0A : i8255
+        port map (
+            RESET            => MZ_RESET,
+            CLK              => CLKBUS(CKMASTER),
+            ENA              => CLKBUS(CKENCPU), --'1',
+            ADDR             => T80_A16(1 downto 0), 
+            DI               => T80_DO,
+            DO               => DOPPI,
+            CS_n             => CS_E0_n,
+            RD_n             => T80_RD_n,
+            WR_n             => T80_WR_n, 
+    
+            PA_I             => i8255_PA_O,
+            PA_O             => i8255_PA_O,
+            PA_O_OE_n        => i8255_PA_OE_n,
+    
+            PB_I             => i8255_PB_I, 
+            PB_O             => open, 
+            PB_O_OE_n        => open,
+    
+            PC_I             => i8255_PC_I,
+            PC_O             => i8255_PC_O,
+            PC_O_OE_n        => i8255_PC_OE_n
+        );
+
+    -- 8253 used for real time clock and sound generation.
+    --
+    PIT0 : i8254
+      port map (
+            RST              => MZ_RESET,
+            CLK              => CLKBUS(CKMASTER),
+            ENA              => CLKBUS(CKENCPU),
+            A                => T80_A16(1 downto 0),
+            DI               => T80_DO,
+            DO               => DOPIT,
+            CS_n             => CS_E1_n,
+            WR_n             => T80_WR_n,
+            RD_n             => T80_RD_n,
+            CLK0             => CLKBUS(CKSOUND),
+            GATE0            => SOUND_ENABLE,
+            OUT0             => SOUND_PULSE_X2,
+            CLK1             => CLKBUS(CKRTC),
+            GATE1            => '1',
+            OUT1             => MZ_RTC_CASCADE_CLK,
+            CLK2             => MZ_RTC_CASCADE_CLK,
+            GATE2            => '1',
+            OUT2             => INTX
+      );
+
+    -- Parent signals onto local wires.
+    --
+    T80_BUSRQ_n              <= '1';
+    T80_NMI_n                <= '1';
+    T80_WAIT_n               <= '1';
+    MZ_RESET                 <= SYSTEM_RESET;
+
+    --
+    -- MZ-80A - Mask interrupt from 8254 if INTMSK low.
+    -- MZ-80K - Interrupt is from 8254 direct.
+    T80_INT_ni               <= '0' when ((CONFIG(MZ_A)='1' or CONFIG(MZ700) = '1') and INTX='1' and INTMSK='1') or ((CONFIG(MZ_KC)='1' and INTX='1'))
+                                else '1';
+    T80_INT_n                <= T80_INT_ni;
+
+    -- PIO and PIT signals. PIO, allow readback of output signals.
+    --
+    i8255_PC_I(7)            <= VBLANK;                                  -- V-BLANK signal
+    i8255_PC_I(6)            <= CURSOR_BLINK;                            -- Cursor Blink
+    i8255_PC_I(5)            <= CMT_BUS_OUT(WRITEBIT);                   -- MZ in from CMT out.
+    i8255_PC_I(4)            <= CMT_BUS_OUT(SENSE);                      -- CMT Read/Write status.
+    i8255_PC_I(3)            <= i8255_PC_O(3) when i8255_PC_OE_n(3) = '0'
+                                else '0';
+    i8255_PC_I(2)            <= INTMSK;                                  -- Red/Green LED MZ80K, Interrupt Mask MZ80A
+    i8255_PC_I(1)            <= i8255_PC_O(1) when i8255_PC_OE_n(1) = '0'
+                                else '0';
+    i8255_PC_I(0)            <= VGATE_ni;                                -- Video Output Enable
+    --
+    CMT_BUS_IN(REEL_MOTOR)   <= '0';
+    CMT_BUS_IN(READBIT)      <= i8255_PC_O(1) when i8255_PC_OE_n(1) = '0'
+                                else '0';                                -- Data Read Bit into CMT originating from MZ.
+    CMT_BUS_IN(STOP)         <= '0';
+    CMT_BUS_IN(PLAY)         <= i8255_PC_O(3) when i8255_PC_OE_n(3) = '0'
+                                else '0';                                -- Play motor on clock. A high pulse activates the motor.
+    CMT_BUS_IN(SEEK)         <= '0';
+    CMT_BUS_IN(DIRECTION)    <= '0';
+    CMT_BUS_IN(EJECT)        <= '1';
+    CMT_BUS_IN(WRITEENABLE)  <= '0';
+    CURSOR_RESET             <= i8255_PA_O(7) when i8255_PA_OE_n(7) = '0'
+                                else '1';
+    INTMSK                   <= i8255_PC_O(2) when i8255_PC_OE_n(2) = '0'
+                                else '1';
+    VGATE_ni                 <= i8255_PC_O(0) when i8255_PC_OE_n(0) = '0'
+                                else '1';
+    KEYB_SCAN                <= i8255_PA_O(3 downto 0) when i8255_PA_OE_n(3 downto 0) /= "1111"
+                                else "0000";                             -- Keyboard scan lines out.
+    KEYB_STALL               <= i8255_PA_O(4) when i8255_PA_OE_n(4) = '0'
+                                else '0';                                -- Keyboard Stall out.
+    i8255_PB_I               <= KEYB_DATA;                               -- Keyboard scan data in.
+
+    --
+    -- Data Bus Multiplexing, plex all the output devices onto the Z80 Data Input according to the CS.
+    --
+    T80_DI                   <= DOPPI     when CS_E0_n  ='0' and T80_RD_n = '0'                                -- Read from 8255
+                                else 
+                                DOPIT     when CS_E1_n  ='0' and T80_RD_n = '0'                                -- Read from 8254
+                                else 
+                                DO367     when CS_E2_n  ='0' and T80_RD_n = '0'                                -- Read from LS367
+                                else 
+                                (others=>'1');
+
+    -- HPS Bus Multiplexing for reads.
+    IOCTL_DIN                <= "11111111000000001100110010101010";                                                            -- Test pattern.
+
+    --
+    -- Chip Select map.
+    --
+    -- 0000 - 0FFF = CS_ROM_ni : MZ80K/A/700   = Monitor ROM or RAM (MZ80A rom swap)
+    -- 1000 - CFFF = CS_RAM_ni : MZ80K/A/700   = RAM
+    -- C000 - CFFF = CS_ROM_ni : MZ80A         = Monitor ROM (MZ80A rom swap)
+    -- D000 - D7FF = CS_VRAM_ni: MZ80K/A/700   = VRAM
+    -- D800 - DFFF = CS_VRAM_ni: MZ700         = Colour VRAM (MZ700)
+    -- E000 - E003 = CS_E0_n   : MZ80K/A/700   = 8255       
+    -- E004 - E007 = CS_E1_n   : MZ80K/A/700   = 8254
+    -- E008 - E00B = CS_E2_n   : MZ80K/A/700   = LS367
+    -- E00C - E00F = CS_ESWP_n : MZ80A         = Memory Swap (MZ80A)
+    -- E010 - E013 = CS_ESWP_n : MZ80A         = Reset Memory Swap (MZ80A)
+    -- E014        = CS_E5_n   : MZ80A/700     = Normat CRT display
+    -- E015        = CS_E6_n   : MZ80A/700     = Reverse CRT display
+    -- E200 - E2FF =           : MZ80A/700     = VRAM roll up/roll down.
+    -- E800 - EFFF =           : MZ80K/A/700   = User ROM socket or DD Eprom (MZ700)
+    -- F000 - F7FF =           : MZ80K/A/700   = Floppy Disk interface.
+    -- F800 - FFFF =           : MZ80K/A/700   = Floppy Disk interface.
+    --
+    -- C000 - CFFF
+    --CS_C_n            <= '0'  when ( (T80_A16(15 downto 12)="1100" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0')
+    --                               )
+    --                          else '1';
+
+    -- D000 - DFFF
+    CS_VRAM_ni          <= '0'  when ( (T80_A16(15 downto 12)="1101" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0')
+                                       and
+                                       ( (CONFIG(MZ_KC)='1' or CONFIG(MZ_A)='1')
+                                         or
+                                         (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='0' and MZ_HIGH_RAM_INHIBIT='0')
+                                       )
+                                     ) 
+                                else '1';
+    -- E000 - EFFF
+    CS_E_ni             <= '0'  when ( (T80_A16(15 downto 12)="1110" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0')
+                                       and
+                                       ( (CONFIG(MZ_KC)='1' or CONFIG(MZ_A)='1')
+                                         or
+                                         (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='0' and MZ_HIGH_RAM_INHIBIT='0')
+                                       )
+                                     )
+                                else '1';
+    -- Sub division E000 - E200
+    CS_E0_n             <= '0'  when CS_E_ni = '0' and T80_A16(11 downto 2) = "0000000000"                                                -- 8255
+                                else '1';
+    CS_E1_n             <= '0'  when CS_E_ni = '0' and T80_A16(11 downto 2) = "0000000001"                                                -- 8254
+                                else '1';
+    CS_E2_n             <= '0'  when CS_E_ni = '0' and T80_A16(11 downto 2) = "0000000010"                                                -- LS367
+                                else '1';
+    CS_ESWP_n           <= '0'  when CONFIG(MZ_A) = '1' and CS_E_ni = '0' and T80_RD_n = '0' and T80_A16(11 downto 5) = "0000000"         -- ROM/RAM Swap
+                                else '1';
+
+    -- F000 - FFFF
+    --CS_F_n            <= '0'  when ( (T80_A16(15 downto 12)="1111" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0')
+    --                                 and
+    --                                 ( (CONFIG(MZ_KC)='1' or CONFIG(MZ_A)='1')
+    --                                   or
+    --                                   (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='0' and MZ_HIGH_RAM_INHIBIT='0')
+    --                                 )
+    --                               )
+    --                          else '1';
+
+    -- C000 - FFFF
+    CS_GRAM_ni          <= '0'  when MZ_GRAM_ENABLE = '1' and T80_A16(15 downto 14) = "11" and T80_MREQ_n='0'
+                                else '1';
+    --
+    CS_ROM_ni           <= '0'  when ( ( (T80_A16(15 downto 12)="0000") 
+                                         and
+                                         ( (CONFIG(MZ_A)='1' and MZ_MEMORY_SWAP='0')                                                      -- 0000 -> 0FFF MZ80A ROM
+                                           or
+                                           (CONFIG(MZ_KC)='1')                                                                            -- 0000 -> 0FFF MZ80K ROM
+                                           or
+                                           (CONFIG(MZ700)='1' and MZ_LOW_RAM_ENABLE='0')                                                  -- 0000 -> 0FFF MZ700 ROM
+                                         ) 
+                                       )
+                                       or
+                                       ( (T80_A16(15 downto 12)="1100")
+                                         and
+                                         ( (CONFIG(MZ_A)='1' and MZ_GRAM_ENABLE='0' and MZ_MEMORY_SWAP='1')                               -- C000 -> CFFF MZ80A ROM memory swapped.
+                                         )
+                                       )
+                                       or
+                                       ( T80_A16(15 downto 11) = "11101"                                                                  -- E800 -> EFFF User ROM memory.
+                                         and
+                                         (CONFIG(USERROM) and CONFIG(CURRENTMACHINE)) /= "00000000"                                       -- Active machine has the user rom enabled.
+                                         and
+                                         MZ_GRAM_ENABLE = '0'                                                                             -- Graphics RAM is not enabled.
+                                         and
+                                         (MZ_HIGH_RAM_ENABLE = '0' or (MZ_HIGH_RAM_ENABLE = '1' and MZ_HIGH_RAM_INHIBIT = '1'))           -- High RAM is not enabled.
+                                       )
+                                       or
+                                       ( T80_A16(15 downto 12) = "1111"
+                                         and
+                                         (CONFIG(FDCROM) and CONFIG(CURRENTMACHINE)) /= "00000000"                                        -- Active machine has the fdc rom enabled.
+                                         and
+                                         MZ_GRAM_ENABLE = '0'                                                                             -- Graphics RAM is not enabled.
+                                         and
+                                         (MZ_HIGH_RAM_ENABLE = '0' or (MZ_HIGH_RAM_ENABLE = '1' and MZ_HIGH_RAM_INHIBIT = '1'))           -- F000 -> FFFF FDC ROM memory.
+                                       )
+                                     ) and T80_MREQ_n='0'
+                                else '1';
+    --
+    CS_RAM_ni           <= '0'  when ( ( (T80_A16(15 downto 12)="0000")
+                                         and 
+                                         ( (CONFIG(MZ_A)='1' and MZ_MEMORY_SWAP='1')                                                      -- 0000 -> 0FFF MZ80A memory swapped.
+                                           or
+                                           (CONFIG(MZ700)='1' and MZ_LOW_RAM_ENABLE='1')                                                  -- 0000 -> 0FFF MZ700 Low Ram Enabled.
+                                         )
+                                       )
+                                       or
+
+                                       (T80_A16(15 downto 12)="0001" or T80_A16(15 downto 12)="0010" or                                   -- 1000 -> 2FFF
+                                        T80_A16(15 downto 12)="0011" or T80_A16(15 downto 12)="0100" or                                   -- 3000 -> 4FFF
+                                        T80_A16(15 downto 12)="0101" or T80_A16(15 downto 12)="0110" or                                   -- 5000 -> 6FFF
+                                        T80_A16(15 downto 12)="0111" or T80_A16(15 downto 12)="1000" or                                   -- 7000 -> 8FFF
+                                        T80_A16(15 downto 12)="1001" or T80_A16(15 downto 12)="1010" or                                   -- 9000 -> AFFF
+                                        T80_A16(15 downto 12)="1011")                                                                     -- B000 -> BFFF
+                                       or
+
+                                       ( (MZ_GRAM_ENABLE = '0')
+                                         and                                                                                              -- Higher memory only available when GRAM not active.
+                                         ( ( (T80_A16(15 downto 12)="1100") 
+                                             and
+                                             ( (CONFIG(MZ_A)='1' and MZ_MEMORY_SWAP='0')                                                  -- C000 -> CFFF MZ80A memory not swapped.
+                                               or
+                                               (CONFIG(MZ_KC)='1')                                                                        -- C000 -> CFFF MZ80K
+                                               or
+                                               (CONFIG(MZ700)='1')                                                                        -- C000 -> CFFF MZ700
+                                             )
+                                           )
+                                           or
+                                           ( (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='1' and MZ_HIGH_RAM_INHIBIT='0')                   -- D000 -> FFFF MZ700 Ram Enabled.
+                                             and
+                                             ( (T80_A16(15 downto 12)="1101" or T80_A16(15 downto 12)="1110"
+                                               or
+                                                T80_A16(15 downto 12)="1111")
+                                             )
+                                           ) 
+                                         )
+                                       )
+                                     )
+                                     and T80_MREQ_n='0'
+                                else '1';
+
+    --
+    -- IO Select Map.
+    -- E0 - E6 are used by the MZ700 to perform memory bank switching.
+    --
+    -- IO Range for Graphics enhancements is set by the MCTRL DISPLAY2{7:3] register.
+    -- x[0|8],<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+    -- x[1|9],<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
+    -- x[2|A],<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
+    -- x[3|B],<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
+    -- x[4|C]       switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. This overrides all MZ700 page switching functions.
+    -- x[5|D]       switches out the graphics ram and returns to previous state.
+    --
+    CS_BANKSWITCH_n     <= '0'  when T80_IORQ_n='0'     and T80_WR_n = '0' and T80_A16(7 downto 4) = "1110"
+                                else '1';
+    CS_MZ700BS_n        <= '0'  when CONFIG(MZ700)='1'  and CS_BANKSWITCH_n = '0' and T80_A16(3) = '0'
+                                else '1';
+    CS_IO_E0_n          <= '0'  when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "000"                                 -- IO E0 = 0000 -> 0FFF RAM,       D000 -> FFFF No Action
+                                else '1';
+    CS_IO_E1_n          <= '0'  when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "001"                                 -- IO E1 = 0000 -> 0FFF No Action, D000 -> FFFF RAM
+                                else '1';
+    CS_IO_E2_n          <= '0'  when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "010"                                 -- IO E2 = 0000 -> 0FFF ROM,       D000 -> FFFF No Action
+                                else '1';
+    CS_IO_E3_n          <= '0'  when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "011"                                 -- IO E3 = 0000 -> 0FFF No Action, D000 -> FFFF VRAM + IO Ports
+                                else '1';
+    CS_IO_E4_n          <= '0'  when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "100"                                 -- IO E4 = 0000 -> 0FFF ROM,       D000 -> FFFF VRAM + IO Ports
+                                else '1';
+    CS_IO_E5_n          <= '0'  when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "101"                                 -- IO E5 = 0000 -> 0FFF No Action, D000 -> FFFF Inhibit
+                                else '1';
+    CS_IO_E6_n          <= '0'  when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "110"                                 -- IO E6 = 0000 -> 0FFF No Action, D000 -> FFFF Unlock Inhibit
+                                else '1';
+    CS_IO_GFB_ni        <= '0'  when T80_IORQ_n   = '0' and T80_A16(7 downto 3) = CONFIG(GRAMIOADDR) and T80_WR_n = '0' -- IO Range for Graphics framebuffer register controlled by mctrl register.
+                                else '1';
+    CS_IO_GRAMENABLE_n  <= '0'  when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "100"                                 -- IO Addr base+4 sets C000 -> FFFF map to Graphics RAM.
+                           else '1';
+    CS_IO_GRAMDISABLE_n <= '0'  when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "101"                                 -- IO Addr base+5 sets C000 -> FFFF revert to previous mode.
+                           else '1';
+
+    -- Send signals to module interface.
+    --
+    CS_ROM_n            <= CS_ROM_ni;
+    CS_RAM_n            <= CS_RAM_ni;
+    CS_VRAM_n           <= CS_VRAM_ni;
+    CS_MEM_G_n          <= CS_E_ni;
+    CS_GRAM_n           <= CS_GRAM_ni;
+    CS_IO_GFB_n         <= CS_IO_GFB_ni;
+
+    -- MZ80A/1200 Memory Swap - swap rom out and ram in.
+    --
+    process( MZ_RESET, CS_ESWP_n ) begin
+        if(MZ_RESET = '1') then
+            MZ_MEMORY_SWAP            <= '0';
+        elsif(CS_ESWP_n'event and CS_ESWP_n='0') then
+            if(T80_A16(4 downto 2) = "011") then
+                MZ_MEMORY_SWAP        <= '1';
+            elsif(T80_A16(4 downto 2) = "100") then
+                MZ_MEMORY_SWAP        <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- MZ700 - Latch wether to enable RAM or ROM at 0000->0FFF.
+    --
+    process( MZ_RESET, CLKBUS(CKMASTER), CS_IO_E0_n, CS_IO_E2_n, CS_IO_E4_n ) begin
+        if(MZ_RESET = '1') then
+            MZ_LOW_RAM_ENABLE         <= '0';
+
+        elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                if(CS_IO_E0_n = '0') then
+                    MZ_LOW_RAM_ENABLE <= '1';
+    
+                elsif(CS_IO_E2_n = '0') then
+                    MZ_LOW_RAM_ENABLE <= '0';
+    
+                elsif(CS_IO_E4_n = '0') then
+                    MZ_LOW_RAM_ENABLE <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- MZ700 - Latch wether to enable I/O or RAM at D000->FFFF.
+    --
+    process( MZ_RESET, CLKBUS(CKMASTER), CS_IO_E1_n, CS_IO_E3_n, CS_IO_E4_n, MZ_HIGH_RAM_INHIBIT ) begin
+        if(MZ_RESET = '1') then
+            MZ_HIGH_RAM_ENABLE        <= '0';
+            MZ_INHIBIT_RESET          <= '0';
+
+        elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                if(CS_IO_E1_n = '0' and MZ_HIGH_RAM_INHIBIT = '0') then
+                    MZ_HIGH_RAM_ENABLE  <= '1';
+    
+                elsif(CS_IO_E3_n = '0' and MZ_HIGH_RAM_INHIBIT = '0') then
+                    MZ_HIGH_RAM_ENABLE  <= '0';
+    
+                elsif(CS_IO_E4_n = '0') then
+                    MZ_HIGH_RAM_ENABLE  <= '0';
+                    MZ_INHIBIT_RESET    <= '1';
+    
+                elsif(MZ_HIGH_RAM_INHIBIT = '0' and MZ_INHIBIT_RESET = '1') then
+                    MZ_INHIBIT_RESET    <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- MZ700 - Latch wether to inhibit all functionality at D000->FFFF.
+    --
+    process( MZ_RESET, CLKBUS(CKMASTER), CS_IO_E5_n, CS_IO_E6_n, MZ_INHIBIT_RESET ) begin
+        if(MZ_RESET = '1') then
+            MZ_HIGH_RAM_INHIBIT         <= '0';
+
+        elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                if(CS_IO_E5_n = '0') then
+                    MZ_HIGH_RAM_INHIBIT <= '1';
+
+                elsif(CS_IO_E6_n = '0' or MZ_INHIBIT_RESET = '1') then
+                    MZ_HIGH_RAM_INHIBIT <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Graphics Ram - Latch wether to enable Graphics RAM page from C000 - FFFF.
+    --
+    process( MZ_RESET, CLKBUS(CKMASTER), CS_IO_GRAMENABLE_n, CS_IO_GRAMDISABLE_n ) begin
+        if(MZ_RESET = '1') then
+            MZ_GRAM_ENABLE              <= '0';
+
+        elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
+
+            if CLKBUS(CKENCPU) = '1' then
+
+                if(CS_IO_GRAMENABLE_n = '0') then
+                    MZ_GRAM_ENABLE      <= '1';
+
+                elsif(CS_IO_GRAMDISABLE_n = '0') then
+                    MZ_GRAM_ENABLE      <= '0';
+
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Cursor Base Clock  
+    --
+    process( CLKBUS(CKMASTER), T80_RST_n )
+        variable TCOUNT : std_logic_vector(15 downto 0);
+    begin
+        if T80_RST_n = '0' then
+            TCOUNT          := (others=>'0');
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
+            if CLKBUS(CKENPERIPH) = '1' then
+                if( TCOUNT = 18371 ) then
+                    TCOUNT      := (others=>'0');
+                    CURSOR_CLK  <= not CURSOR_CLK;
+                else
+                    TCOUNT      := TCOUNT + '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Cursor blink Clock
+    --
+    process( CURSOR_CLK, CURSOR_RESET ) begin
+        if( CURSOR_RESET='0' ) then
+            CCOUNT           <= (others => '0');
+        elsif( CURSOR_CLK'event and CURSOR_CLK = '1' ) then
+            if( CCOUNT = 18 ) then
+                CCOUNT       <=(others=>'0');
+                CURSOR_BLINK <= not CURSOR_BLINK;
+            else
+                CCOUNT       <= CCOUNT+'1';
+            end if;
+        end if;
+    end process;
+
+    --
+    -- Sound gate control
+    --
+    process( CLKBUS(CKMASTER), T80_WR_n, CS_E2_n, T80_RST_n ) begin
+        if( T80_RST_n = '0' ) then
+            SOUND_ENABLE     <= '0';
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
+
+            if CLKBUS(CKENPERIPH) = '1' and T80_WR_n = '0' and CS_E2_n = '0' then
+                SOUND_ENABLE <= T80_DO(0);
+            end if;
+        end if;
+    end process;
+
+    -- Audio output. Choose between generated sound and CMT pulse audio.
+    --
+    AUDIO_L    <= SOUND when CONFIG(AUDIOSRC) = '0'            -- Sound Output Left
+                  else
+                  CMT_BUS_OUT(WRITEBIT);
+    AUDIO_R    <= SOUND when CONFIG(AUDIOSRC) = '0'            -- Sound Output Right
+                  else
+                  CMT_BUS_OUT(READBIT);
+
+    -- The signal coming out of the 8254 is not a square wave and twice the frequency. The addition of a flip-flop to divide the
+    -- frequency by 2 results in a square wave of the correct audio frequency.
+    process( SOUND_PULSE_X2 ) begin
+        if( SOUND_PULSE_X2'event and SOUND_PULSE_X2 = '1' ) then
+            SOUND <= not SOUND;
+        end if;
+    end process;
+
+    -- MZ80 BLNK signal, enabled by VGATE being active and HBLANK pulsing. If HBLANK stops pulsing for more
+    -- than 32ms, then BLNK goes inactive.
+    --
+    process( CLKBUS(CKMASTER), T80_RST_n )
+        variable TCOUNT     : std_logic_vector(6 downto 0);
+        variable HBLANKLAST : std_logic;
+    begin
+        if T80_RST_n = '0' then
+            BLNK_n          <= '1';
+            TCOUNT          := (others=>'0');
+
+        elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
+
+            if CLKBUS(CKENPERIPH) = '1' then
+                -- If HBLANK goes active the first time or is retriggered, reset counter and set BLANKING active.
+                if (HBLANK = '1' and TCOUNT = 0) or (HBLANK = '1' and HBLANKLAST = '0') then
+                    TCOUNT      := "0000001";
+                    BLNK_n      <= '0';
+
+                -- If not retriggered and we get to the end of the count (32ms) then turn off the BLANKING signal.
+                elsif TCOUNT = 63 then
+                    TCOUNT      := (others=>'0');
+                    BLNK_n      <= '1';
+                else
+                    TCOUNT      := TCOUNT + '1';
+                end if;
+
+                -- Remember last state so we can retrigger.
+                HBLANKLAST := HBLANK;
+            end if;
+        end if;
+    end process;
+
+    -- Try state register read, LS124 in MZ80A, LS367 in MZZ700. On MZ700 this register also inputs the
+    -- Joystick readings, yet to be implemented.
+    --
+    DO367(0)          <= CURSOR_CLK;
+    DO367(7)          <= not HBLANK  when CONFIG(MZ700) = '1'
+                         else
+                         '1'         when CONFIG(MZ_A)  = '1' and (BLNK_n = '0' and VGATE_ni = '0')
+                         else '1';
+    DO367(6 downto 1) <= (others=>'1');
+
+    -- Video Output.
+    --
+    VGATE_n    <= VGATE_ni;
+
+    -- Only enable debugging LEDS if enabled in the config package.
+    --
+    DEBUG80B: if DEBUG_ENABLE = 1 generate
+        -- A simple 1*cpufreq second pulse to indicate accuracy of CPU frequency for debug purposes..
+        --
+        process (SYSTEM_RESET, CLKBUS(CKMASTER))
+            variable cnt : integer range 0 to 1999999 := 0;
+        begin
+            if SYSTEM_RESET = '1' then
+                PULSECPU         <= '0';
+                cnt              := 0;
+            elsif rising_edge(CLKBUS(CKMASTER)) then
+                if CLKBUS(CKENCPU) = '1' then
+                    cnt          := cnt + 1;
+                    if cnt = 0 then
+                        PULSECPU <= not PULSECPU;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        -- Debug leds.
+        --
+        DEBUG_STATUS_LEDS(0)  <= CS_VRAM_ni;
+        DEBUG_STATUS_LEDS(1)  <= CS_E_ni;
+        DEBUG_STATUS_LEDS(2)  <= CS_E0_n;
+        DEBUG_STATUS_LEDS(3)  <= CS_E1_n;
+        DEBUG_STATUS_LEDS(4)  <= CS_E2_n;
+        DEBUG_STATUS_LEDS(5)  <= CS_ESWP_n;
+        DEBUG_STATUS_LEDS(6)  <= CS_ROM_ni;
+        DEBUG_STATUS_LEDS(7)  <= CS_RAM_ni;
+        --
+        DEBUG_STATUS_LEDS(8)  <= CS_BANKSWITCH_n;
+        DEBUG_STATUS_LEDS(9)  <= CS_IO_E0_n;
+        DEBUG_STATUS_LEDS(10) <= CS_IO_E1_n;
+        DEBUG_STATUS_LEDS(11) <= CS_IO_E2_n;
+        DEBUG_STATUS_LEDS(12) <= CS_IO_E3_n;
+        DEBUG_STATUS_LEDS(13) <= CS_IO_E4_n;
+        DEBUG_STATUS_LEDS(14) <= CS_IO_E5_n;
+        DEBUG_STATUS_LEDS(15) <= CS_IO_E6_n;
+        --
+        DEBUG_STATUS_LEDS(16) <= CS_IO_GRAMENABLE_n;
+        DEBUG_STATUS_LEDS(17) <= CS_IO_GRAMDISABLE_n;
+        DEBUG_STATUS_LEDS(18) <= CS_IO_GFB_ni;
+        DEBUG_STATUS_LEDS(19) <= CS_GRAM_ni;
+        DEBUG_STATUS_LEDS(20) <= MZ_GRAM_ENABLE;
+        DEBUG_STATUS_LEDS(21) <= '0';
+        DEBUG_STATUS_LEDS(22) <= '0';
+        DEBUG_STATUS_LEDS(23) <= '0';
+        --
+        DEBUG_STATUS_LEDS(24) <= PULSECPU;
+        DEBUG_STATUS_LEDS(25) <= T80_INT_ni;
+        DEBUG_STATUS_LEDS(26) <= INTMSK;
+        DEBUG_STATUS_LEDS(27) <= MZ_MEMORY_SWAP;
+        DEBUG_STATUS_LEDS(28) <= MZ_LOW_RAM_ENABLE;
+        DEBUG_STATUS_LEDS(29) <= MZ_HIGH_RAM_ENABLE;
+        DEBUG_STATUS_LEDS(30) <= MZ_HIGH_RAM_INHIBIT;
+        DEBUG_STATUS_LEDS(31) <= MZ_INHIBIT_RESET;
+        --
+        DEBUG_STATUS_LEDS(32) <= '0';
+        DEBUG_STATUS_LEDS(33) <= '0';
+        DEBUG_STATUS_LEDS(34) <= '0';
+        DEBUG_STATUS_LEDS(35) <= '0';
+        DEBUG_STATUS_LEDS(36) <= CURSOR_BLINK;
+        DEBUG_STATUS_LEDS(37) <= SOUND_ENABLE;
+        DEBUG_STATUS_LEDS(38) <= MZ_RTC_CASCADE_CLK;
+        DEBUG_STATUS_LEDS(39) <= PULSECPU;
+        --
+        -- LEDS 40 .. 112 are available.
+        DEBUG_STATUS_LEDS(111 downto 40) <= (others => '0');
+    end generate;
+end rtl;
diff --git a/sharpmz-lite-div.qws b/sharpmz-lite-div.qws
new file mode 100644
index 0000000..c6a7544
Binary files /dev/null and b/sharpmz-lite-div.qws differ
diff --git a/sharpmz-lite-div_assignment_defaults.qdf b/sharpmz-lite-div_assignment_defaults.qdf
new file mode 100644
index 0000000..92b284a
--- /dev/null
+++ b/sharpmz-lite-div_assignment_defaults.qdf
@@ -0,0 +1,807 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
+# Date created = 17:23:05  October 20, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL Enable
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/sharpmz-lite-pll.qws b/sharpmz-lite-pll.qws
new file mode 100644
index 0000000..63563b7
Binary files /dev/null and b/sharpmz-lite-pll.qws differ
diff --git a/sharpmz-lite-pll.sdc b/sharpmz-lite-pll.sdc
new file mode 100644
index 0000000..127326e
--- /dev/null
+++ b/sharpmz-lite-pll.sdc
@@ -0,0 +1,459 @@
+## Generated SDC file "sharpmz-lite-pll.out.sdc"
+
+## Copyright (C) 2017  Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Intel Program License 
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel MegaCore Function License Agreement, or other 
+## applicable license agreement, including, without limitation, 
+## that your use is for the sole purpose of programming logic 
+## devices manufactured by Intel and sold by Intel or its 
+## authorized distributors.  Please refer to the applicable 
+## agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition"
+
+## DATE    "Tue Oct 09 16:54:46 2018"
+
+##
+## DEVICE  "5CSEBA6U23I7"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
+create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
+create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}]
+create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 5243 -divide_by 512 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 16 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 64 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 256 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 32 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 128 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 8 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 1135 -divide_by 256 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 5 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 64 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 32 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 160 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 80 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 40 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 20 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 10 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200  
+set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_ports {KEY*}] 
+set_false_path -from [get_ports {BTN_*}] 
+set_false_path -to [get_ports {LED_*}]
+set_false_path -to [get_ports {VGA_*}]
+set_false_path -to [get_ports {AUDIO_SPDIF}]
+set_false_path -to [get_ports {AUDIO_L}]
+set_false_path -to [get_ports {AUDIO_R}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+# Decouple different clock groups (to simplify routing)
+#   -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+#  -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
+set_clock_groups -asynchronous \
+   -group [get_clocks { *|h2f_user0_clk}] \
+   -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
+
diff --git a/sharpmz-lite-pll_assignment_defaults.qdf b/sharpmz-lite-pll_assignment_defaults.qdf
new file mode 100644
index 0000000..d210acb
--- /dev/null
+++ b/sharpmz-lite-pll_assignment_defaults.qdf
@@ -0,0 +1,807 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
+# Date created = 17:23:11  October 20, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL Enable
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/sharpmz-lite.out.sdc b/sharpmz-lite.out.sdc
new file mode 100644
index 0000000..aeea805
--- /dev/null
+++ b/sharpmz-lite.out.sdc
@@ -0,0 +1,204 @@
+## Generated SDC file "sharpmz-lite.out.sdc"
+
+## Copyright (C) 2017  Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Intel Program License 
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel FPGA IP License Agreement, or other applicable license
+## agreement, including, without limitation, that your use is for
+## the sole purpose of programming logic devices manufactured by
+## Intel and sold by Intel or its authorized distributors.  Please
+## refer to the applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
+
+## DATE    "Fri Nov 16 23:12:31 2018"
+
+##
+## DEVICE  "5CSEBA6U23I7"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
+create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
+create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}]
+create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+create_generated_clock -name {CK112M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 224 -divide_by 100 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+create_generated_clock -name {CK64M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 128 -divide_by 100 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] 
+create_generated_clock -name {CK32M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 64 -divide_by 100 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] 
+create_generated_clock -name {CK16M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 32 -divide_by 100 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] 
+create_generated_clock -name {CK8M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 16 -divide_by 100 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] 
+create_generated_clock -name {CK4M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 8 -divide_by 100 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[5]}] 
+create_generated_clock -name {CK2M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 4 -divide_by 100 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[6]}] 
+create_generated_clock -name {CK56M75} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 1135 -divide_by 1000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+create_generated_clock -name {CK28M375} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 5675 -divide_by 10000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] 
+create_generated_clock -name {CK25M175} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 5035 -divide_by 10000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] 
+create_generated_clock -name {CK17M734475} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 3546895 -divide_by 10000000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] 
+create_generated_clock -name {CK14M1875} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 28375 -divide_by 100000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] 
+create_generated_clock -name {CK8M867237} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 17734474 -divide_by 100000000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[5]}] 
+create_generated_clock -name {CK7M09375} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 141875 -divide_by 1000000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[6]}] 
+create_generated_clock -name {CK3M546875} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 709375 -divide_by 10000000 -master_clock {FPGA_CLK2_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[7]}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {CK56M75}] -rise_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {CK56M75}] -fall_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {CK56M75}] -rise_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {CK56M75}] -fall_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -rise_to [get_clocks {CK112M}] -setup 0.190  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -rise_to [get_clocks {CK112M}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -fall_to [get_clocks {CK112M}] -setup 0.190  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -fall_to [get_clocks {CK112M}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {CK112M}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -rise_to [get_clocks {CK112M}] -setup 0.190  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -rise_to [get_clocks {CK112M}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -fall_to [get_clocks {CK112M}] -setup 0.190  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -fall_to [get_clocks {CK112M}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {CK112M}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {CK112M}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {CK112M}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {CK112M}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {CK112M}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.060  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {CK112M}]  0.220  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}]  0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170  
+set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060  
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_ports {KEY*}] 
+set_false_path -from [get_ports {BTN_*}] 
+set_false_path -to [get_ports {LED_*}]
+set_false_path -to [get_ports {VGA_*}]
+set_false_path -to [get_ports {AUDIO_SPDIF}]
+set_false_path -to [get_ports {AUDIO_L}]
+set_false_path -to [get_ports {AUDIO_R}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/sharpmz-lite.qsf b/sharpmz-lite.qsf
new file mode 100755
index 0000000..81e2cb0
--- /dev/null
+++ b/sharpmz-lite.qsf
@@ -0,0 +1,536 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
+# Date created = 01:53:32  April 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name VERILOG_MACRO "LITE=1"
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEBA6U23I7
+set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+#set_global_assignment -name TOP_LEVEL_ENTITY emu
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
+set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
+set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE OFF
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZATION_MODE "HIGH POWER EFFORT"
+set_global_assignment -name SEED 1
+#set_global_assignment -name SDC_FILE sharpmz.sdc
+set_global_assignment -name SDC_FILE "sharpmz-lite.sdc"
+
+#============================================================
+# ADC
+#============================================================
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+#set_location_assignment PIN_U9 -to ADC_CONVST
+#set_location_assignment PIN_V10 -to ADC_SCK
+#set_location_assignment PIN_AC4 -to ADC_SDI
+#set_location_assignment PIN_AD4 -to ADC_SDO
+
+#============================================================
+# ARDUINO
+#============================================================
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
+#set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
+#set_location_assignment PIN_U14 -to ARDUINO_IO[4]
+#set_location_assignment PIN_U13 -to ARDUINO_IO[5]
+#set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
+#set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
+#set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
+#set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
+#set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
+#set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
+#set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
+#set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
+#set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
+#set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
+
+#============================================================
+# SDIO
+#============================================================
+set_location_assignment PIN_AF25 -to SDIO_DAT[0]
+set_location_assignment PIN_AF23 -to SDIO_DAT[1]
+set_location_assignment PIN_AD26 -to SDIO_DAT[2]
+set_location_assignment PIN_AF28 -to SDIO_DAT[3]
+set_location_assignment PIN_AF27 -to SDIO_CMD
+set_location_assignment PIN_AH26 -to SDIO_CLK
+set_location_assignment PIN_AH7 -to SDIO_CD
+#
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
+#
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_AE17 -to VGA_R[0]
+set_location_assignment PIN_AE20 -to VGA_R[1]
+set_location_assignment PIN_AF20 -to VGA_R[2]
+set_location_assignment PIN_AH18 -to VGA_R[3]
+set_location_assignment PIN_AH19 -to VGA_R[4]
+set_location_assignment PIN_AF21 -to VGA_R[5]
+
+set_location_assignment PIN_AE19 -to VGA_G[0]
+set_location_assignment PIN_AG15 -to VGA_G[1]
+set_location_assignment PIN_AF18 -to VGA_G[2]
+set_location_assignment PIN_AG18 -to VGA_G[3]
+set_location_assignment PIN_AG19 -to VGA_G[4]
+set_location_assignment PIN_AG20 -to VGA_G[5]
+
+set_location_assignment PIN_AG21 -to VGA_B[0]
+set_location_assignment PIN_AA20 -to VGA_B[1]
+set_location_assignment PIN_AE22 -to VGA_B[2]
+set_location_assignment PIN_AF22 -to VGA_B[3]
+set_location_assignment PIN_AH23 -to VGA_B[4]
+set_location_assignment PIN_AH21 -to VGA_B[5]
+
+set_location_assignment PIN_AH22 -to VGA_HS
+set_location_assignment PIN_AG24 -to VGA_VS
+
+set_location_assignment PIN_AH27 -to VGA_EN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
+
+#============================================================
+# AUDIO
+#============================================================
+set_location_assignment PIN_AC24 -to AUDIO_L
+set_location_assignment PIN_AE25 -to AUDIO_R
+set_location_assignment PIN_AG26 -to AUDIO_SPDIF
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
+
+#============================================================
+# SDRAM
+#============================================================
+#set_location_assignment PIN_Y11 -to SDRAM_A[0]
+#set_location_assignment PIN_AA26 -to SDRAM_A[1]
+#set_location_assignment PIN_AA13 -to SDRAM_A[2]
+#set_location_assignment PIN_AA11 -to SDRAM_A[3]
+#set_location_assignment PIN_W11 -to SDRAM_A[4]
+#set_location_assignment PIN_Y19 -to SDRAM_A[5]
+#set_location_assignment PIN_AB23 -to SDRAM_A[6]
+#set_location_assignment PIN_AC23 -to SDRAM_A[7]
+#set_location_assignment PIN_AC22 -to SDRAM_A[8]
+#set_location_assignment PIN_C12 -to SDRAM_A[9]
+#set_location_assignment PIN_AB26 -to SDRAM_A[10]
+#set_location_assignment PIN_AD17 -to SDRAM_A[11]
+#set_location_assignment PIN_D12 -to SDRAM_A[12]
+#set_location_assignment PIN_Y17 -to SDRAM_BA[0]
+#set_location_assignment PIN_AB25 -to SDRAM_BA[1]
+
+#set_location_assignment PIN_E8 -to SDRAM_DQ[0]
+#set_location_assignment PIN_V12 -to SDRAM_DQ[1]
+#set_location_assignment PIN_D11 -to SDRAM_DQ[2]
+#set_location_assignment PIN_W12 -to SDRAM_DQ[3]
+#set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
+#set_location_assignment PIN_D8 -to SDRAM_DQ[5]
+#set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
+#set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
+#set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
+#set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
+#set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
+#set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
+#set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
+#set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
+#set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
+#set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
+#set_location_assignment PIN_AG13 -to SDRAM_DQML
+#set_location_assignment PIN_AF13 -to SDRAM_DQMH
+
+#set_location_assignment PIN_AD20 -to SDRAM_CLK
+#set_location_assignment PIN_AG10 -to SDRAM_CKE
+
+#set_location_assignment PIN_AA19 -to SDRAM_nWE
+#set_location_assignment PIN_AA18 -to SDRAM_nCAS
+#set_location_assignment PIN_Y18 -to SDRAM_nCS
+#set_location_assignment PIN_W14 -to SDRAM_nRAS
+
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
+#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
+#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
+#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
+#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
+#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
+#set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+#set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
+
+#============================================================
+# I/O
+#============================================================
+set_location_assignment PIN_Y15 -to LED_USER
+set_location_assignment PIN_AA15 -to LED_HDD
+set_location_assignment PIN_AG28 -to LED_POWER
+
+set_location_assignment PIN_AH24 -to BTN_USER
+set_location_assignment PIN_AG25 -to BTN_OSD
+set_location_assignment PIN_AG23 -to BTN_RESET
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
+
+#============================================================
+# CLOCK
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+set_location_assignment PIN_V11 -to FPGA_CLK1_50
+set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_E11 -to FPGA_CLK3_50
+
+#============================================================
+# HDMI
+#============================================================
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
+#set_location_assignment PIN_U10 -to HDMI_I2C_SCL
+#set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
+#set_location_assignment PIN_T13 -to HDMI_I2S
+#set_location_assignment PIN_T11 -to HDMI_LRCLK
+#set_location_assignment PIN_U11 -to HDMI_MCLK
+#set_location_assignment PIN_T12 -to HDMI_SCLK
+#set_location_assignment PIN_AG5 -to HDMI_TX_CLK
+#set_location_assignment PIN_AD19 -to HDMI_TX_DE
+#set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
+#set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
+#set_location_assignment PIN_W8 -to HDMI_TX_D[2]
+#set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
+#set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
+#set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
+#set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
+#set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
+#set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
+#set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
+#set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
+#set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
+#set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
+#set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
+#set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
+#set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
+#set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
+#set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
+#set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
+#set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
+#set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
+#set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
+#set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
+#set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
+#set_location_assignment PIN_T8 -to HDMI_TX_HS
+#set_location_assignment PIN_AF11 -to HDMI_TX_INT
+#set_location_assignment PIN_V13 -to HDMI_TX_VS
+
+#============================================================
+# KEY
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_location_assignment PIN_AH17 -to KEY[0]
+set_location_assignment PIN_AH16 -to KEY[1]
+
+#============================================================
+# LED
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+set_location_assignment PIN_W15 -to LED[0]
+set_location_assignment PIN_AA24 -to LED[1]
+set_location_assignment PIN_V16 -to LED[2]
+set_location_assignment PIN_V15 -to LED[3]
+set_location_assignment PIN_AF26 -to LED[4]
+set_location_assignment PIN_AE26 -to LED[5]
+set_location_assignment PIN_Y16 -to LED[6]
+set_location_assignment PIN_AA23 -to LED[7]
+
+#============================================================
+# SW
+#============================================================
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+#set_location_assignment PIN_Y24 -to SW[0]
+#set_location_assignment PIN_W24 -to SW[1]
+#set_location_assignment PIN_W21 -to SW[2]
+#set_location_assignment PIN_W20 -to SW[3]
+
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
+
+set_global_assignment -name CDF_FILE jtag.cdf
+set_global_assignment -name QIP_FILE sys/sys.qip
+set_global_assignment -name VHDL_FILE jtag_uart_0.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE emu.sv
+set_global_assignment -name VHDL_FILE common/config_pkg.vhd
+set_global_assignment -name VHDL_FILE bridge.vhd
+set_global_assignment -name VHDL_FILE sharpmz.vhd
+
+#============================================================
+# Latest T80 CPU
+#============================================================
+set_global_assignment -name VHDL_FILE common/T80/T80.vhd
+set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE common/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE common/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE common/T80/T80a.vhd
+set_global_assignment -name VHDL_FILE common/T80/T80se.vhd
+set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd
+
+#============================================================
+# i8253 Programmable Interval Timer
+#============================================================
+set_global_assignment -name VHDL_FILE common/i8254/i8254_counter.vhd
+set_global_assignment -name VHDL_FILE common/i8254/i8254.vhd
+
+#============================================================
+# i8255 Programmable Peripheral Interface 
+#============================================================
+set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd
+#set_global_assignment -name VHDL_FILE mz80b/i8255/i8255.vhd
+
+#============================================================
+# MZ80C specific modules.
+#============================================================
+set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd
+
+#============================================================
+# MZ80B specific modules.
+#============================================================
+#set_global_assignment -name VHDL_FILE mz80b/mz80b_dummy.vhd
+set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd
+
+#============================================================
+# NEO430
+#============================================================
+#set_global_assignment -name VHDL_FILE neo430/neo430.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_addr_gen.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_alu.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_application_image.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_boot_rom.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_bootloader_image.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_cfu.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_control.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_cpu.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_crc.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_dmem.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_gpio.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_imem.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_muldiv.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_package.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_pwm.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_reg_file.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_sysconfig.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_timer.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_top.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_uart.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_spi.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_twi.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_wb_interface.vhd
+#set_global_assignment -name VHDL_FILE neo430/neo430_wdt.vhd
+#============================================================
+# STORM
+#============================================================
+set_global_assignment -name VHDL_FILE    storm/STORM_SoC.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/ALU.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/BARREL_SHIFTER.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/BUS_UNIT.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/CACHE.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/CORE.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/CORE_PKG.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/FLOW_CTRL.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/LOAD_STORE_UNIT.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/MC_SYS.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/MS_UNIT.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/MULTIPLY_UNIT.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/OPCODE_DECODER.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/OPERAND_UNIT.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/REG_FILE.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/STORM_TOP.vhd
+set_global_assignment -name VHDL_FILE    storm/CPU/WB_UNIT.vhd
+set_global_assignment -name VHDL_FILE    storm/components/boot_rom/rtl/BOOT_ROM_FILE.vhd
+#set_global_assignment -name VHDL_FILE    storm/components/seven_segment_controller/rtl/SEVEN_SEG_CTRL.vhd
+set_global_assignment -name VHDL_FILE    storm/components/ps2core/rtl/vhdl/ps2_wb.vhd
+set_global_assignment -name VHDL_FILE    storm/components/ps2core/rtl/vhdl/ps2.vhd
+set_global_assignment -name VHDL_FILE    storm/components/reset_protector/rtl/RST_PROTECT.vhd
+set_global_assignment -name VHDL_FILE    storm/components/timer/rtl/TIMER.vhd
+set_global_assignment -name VHDL_FILE    storm/components/io_controller/rtl/GP_IO_CTRL.vhd
+set_global_assignment -name VHDL_FILE    storm/components/vector_interrupt_controller/rtl/VIC.vhd
+set_global_assignment -name VHDL_FILE    storm/components/miniuart/rtl/vhdl/MINI_UART.vhd
+set_global_assignment -name VHDL_FILE    storm/components/miniuart/rtl/vhdl/Txunit.vhd
+set_global_assignment -name VHDL_FILE    storm/components/miniuart/rtl/vhdl/Rxunit.vhd
+set_global_assignment -name VHDL_FILE    storm/components/miniuart/rtl/vhdl/utils.vhd
+set_global_assignment -name VHDL_FILE    storm/components/i2c_controller/rtl/vhdl/i2c_master_top.vhd
+set_global_assignment -name VHDL_FILE    storm/components/i2c_controller/rtl/vhdl/i2c_master_byte_ctrl.vhd
+set_global_assignment -name VHDL_FILE    storm/components/i2c_controller/rtl/vhdl/i2c_master_bit_ctrl.vhd
+#set_global_assignment -name VHDL_FILE    storm/components/pwm_controller/rtl/PWM_CTRL.vhd
+set_global_assignment -name VHDL_FILE    storm/components/sram_memory/rtl/MEMORY.vhd
+set_global_assignment -name VHDL_FILE    storm/components/ioctl/rtl/ioctl.vhd
+set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_top.v
+set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_defines.v
+set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_clgen.v
+set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_shift.v
+set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/timescale.v
+
+#============================================================
+# PLL
+#============================================================
+set_global_assignment -name QIP_FILE common/pll.qip
+set_global_assignment -name VHDL_FILE common/clkgen.vhd
+#set_global_assignment -name QIP_FILE common/pll_1.qip
+#set_global_assignment -name QIP_FILE common/pll_2.qip
+#set_global_assignment -name QIP_FILE common/pll_4.qip
+
+#============================================================
+# Common modules
+#============================================================
+set_global_assignment -name VHDL_FILE common/dprom.vhd
+set_global_assignment -name VHDL_FILE common/clk_div.vhd
+set_global_assignment -name VHDL_FILE common/mctrl.vhd
+set_global_assignment -name VHDL_FILE common/dpram.vhd
+set_global_assignment -name VHDL_FILE common/keymatrix.vhd
+set_global_assignment -name VHDL_FILE common/video.vhd
+set_global_assignment -name VHDL_FILE common/cmt.vhd
+set_global_assignment -name VHDL_FILE common/z8420/z8420.vhd
+set_global_assignment -name VHDL_FILE common/z8420/Interrupt.vhd
+
+#============================================================
+# Functions
+#============================================================
+set_global_assignment -name VHDL_FILE common/functions.vhd
+
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
+set_global_assignment -name ALLOW_REGISTER_RETIMING ON
+
+
+set_location_assignment PIN_AA13 -to UART_TX
+set_location_assignment PIN_AA11 -to UART_RX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX
+#
+#set_location_assignment PIN_AF25 -to SPI_MISO
+#set_location_assignment PIN_AF28 -to SPI_CS[0]
+#set_location_assignment PIN_AF27 -to SPI_MOSI
+#set_location_assignment PIN_AH26 -to SPI_SCLK
+
+#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MISO
+#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_CS[0]
+#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MOSI
+#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_SCLK
+
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CS[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCLK
+#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SPI_MISO
+
+
+
+
+
+
+
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/sharpmz-lite.qws b/sharpmz-lite.qws
new file mode 100755
index 0000000..c4d26a8
Binary files /dev/null and b/sharpmz-lite.qws differ
diff --git a/sharpmz-lite.sdc b/sharpmz-lite.sdc
new file mode 100644
index 0000000..d000cc8
--- /dev/null
+++ b/sharpmz-lite.sdc
@@ -0,0 +1,206 @@
+## Generated SDC file "sharpmz-lite-div.out.sdc"
+
+## Copyright (C) 2017  Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Intel Program License 
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel MegaCore Function License Agreement, or other 
+## applicable license agreement, including, without limitation, 
+## that your use is for the sole purpose of programming logic 
+## devices manufactured by Intel and sold by Intel or its 
+## authorized distributors.  Please refer to the applicable 
+## agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition"
+
+## DATE    "Wed Oct 31 10:26:38 2018"
+
+##
+## DEVICE  "5CSEBA6U23I7"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
+create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
+create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}]
+create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+derive_pll_clocks -create_base_clocks -use_tan_name
+
+# create_generated_clock -name <name> -source <source> -divide_by <ratio: 2,4,8, ....> -duty_cycle 50.00 <generated_clk> 
+# <name> a name assigned to the generate clock to be used in TQ analysis 
+# <source> the reference to your master clock 
+# <generated_clk> in your case this is the lpm_counter port where you pick the generated clock from
+# create_generated_clock -name divclk_16mhz -divide_by 2 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[0]} 
+#set all_enabled_registers ]
+#set clock_enable_divide_by_n 4
+#set_multicycle_path -setup $clock_enable_divide_by_n -from $all_enabled_registers -to $all_enabled_registers
+#set_multicycle_path -hold  -from $all_enabled_registers -to $all_enabled_registers
+
+#create_generated_clock -name {CK96M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 192 -divide_by 100 \
+#                       -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+#create_generated_clock -name {CK64M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 128 -divide_by 100 \
+#                       -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] 
+#create_generated_clock -name {CK32M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 64 -divide_by 100 \
+#                       -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] 
+#create_generated_clock -name {CK16M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 32 -divide_by 100 \
+#                       -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] 
+#create_generated_clock -name {CK8M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 16 -divide_by 100 \
+#                       -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] 
+#create_generated_clock -name {CK4M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 8 -divide_by 100 \
+#                       -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[5]}] 
+#create_generated_clock -name {CK2M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 4 -divide_by 100 \
+#                       -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[6]}] 
+#
+#create_generated_clock -name {CK56M75} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 591146 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+#create_generated_clock -name {CK28M375} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 295573 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] 
+#create_generated_clock -name {CK14M1875} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 147786 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] 
+#create_generated_clock -name {CK7M09375} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 73893 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] 
+#create_generated_clock -name {CK3M546875} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 36947 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] 
+#
+#create_generated_clock -name {CK85M86} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 894375 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+#create_generated_clock -name {CK65M} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 67708 -divide_by 100000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}] 
+#create_generated_clock -name {CK25M175} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 26224 -divide_by 100000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}] 
+#create_generated_clock -name {CK17M734475} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 184734 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}] 
+#create_generated_clock -name {CK8M867237} \
+#                       -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
+#                       -duty_cycle 50/1 -multiply_by 92367 -divide_by 1000000 \
+#                       -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}] 
+#
+
+# {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+#create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 8 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+#create_generated_clock -name {clk_2M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -duty_cycle 50/1 -multiply_by 1 -divide_by 224 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_registers {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK2Mi}] 
+#create_generated_clock -name {clk_15611} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -duty_cycle 50/1 -multiply_by 1 -divide_by 28698 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_registers {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK15611i}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+#set_clock_groups -asynchronous -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] -group [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -group [get_clocks { }] 
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_ports {KEY*}] 
+set_false_path -from [get_ports {BTN_*}] 
+set_false_path -to [get_ports {LED_*}]
+set_false_path -to [get_ports {VGA_*}]
+set_false_path -to [get_ports {AUDIO_SPDIF}]
+set_false_path -to [get_ports {AUDIO_L}]
+set_false_path -to [get_ports {AUDIO_R}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/sharpmz-lite.srf b/sharpmz-lite.srf
new file mode 100644
index 0000000..96a7c6e
--- /dev/null
+++ b/sharpmz-lite.srf
@@ -0,0 +1,17 @@
+{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic." {  } {  } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(15): vip\|output_inst\|vid_clk could not be matched with a net" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(14): Argument <targets> is an empty collection" {  } {  } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(32): VID_CLK could not be matched with a clock" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(594): object \"VSET\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" {  } {  } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_cyclonev_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll_reconfig_core.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
diff --git a/sharpmz-lite_assignment_defaults.qdf b/sharpmz-lite_assignment_defaults.qdf
new file mode 100644
index 0000000..3420a0f
--- /dev/null
+++ b/sharpmz-lite_assignment_defaults.qdf
@@ -0,0 +1,808 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
+# Date created = 18:06:35  June 18, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL -value ENABLE
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/sharpmz.qpf b/sharpmz.qpf
new file mode 100644
index 0000000..449544c
--- /dev/null
+++ b/sharpmz.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
+# Date created = 20:18:34  October 31, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.1"
+DATE = "20:18:34  October 31, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "sharpmz-lite"
+PROJECT_REVISION = "sharpmz"
diff --git a/sharpmz.qsf b/sharpmz.qsf
new file mode 100644
index 0000000..24e1166
--- /dev/null
+++ b/sharpmz.qsf
@@ -0,0 +1,357 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
+# Date created = 01:53:32  April 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEBA6U23I7
+set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
+set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
+set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name SEED 1
+
+#============================================================
+# ADC
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+set_location_assignment PIN_U9 -to ADC_CONVST
+set_location_assignment PIN_V10 -to ADC_SCK
+set_location_assignment PIN_AC4 -to ADC_SDI
+set_location_assignment PIN_AD4 -to ADC_SDO
+
+#============================================================
+# ARDUINO
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
+set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
+set_location_assignment PIN_U14 -to ARDUINO_IO[4]
+set_location_assignment PIN_U13 -to ARDUINO_IO[5]
+set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
+set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
+set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
+set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
+set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
+set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
+set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
+set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
+set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
+
+#============================================================
+# SDIO
+#============================================================
+set_location_assignment PIN_AF25 -to SDIO_DAT[0]
+set_location_assignment PIN_AF23 -to SDIO_DAT[1]
+set_location_assignment PIN_AD26 -to SDIO_DAT[2]
+set_location_assignment PIN_AF28 -to SDIO_DAT[3]
+set_location_assignment PIN_AF27 -to SDIO_CMD
+set_location_assignment PIN_AH26 -to SDIO_CLK
+set_location_assignment PIN_AH7 -to SDIO_CD
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_AE17 -to VGA_R[0]
+set_location_assignment PIN_AE20 -to VGA_R[1]
+set_location_assignment PIN_AF20 -to VGA_R[2]
+set_location_assignment PIN_AH18 -to VGA_R[3]
+set_location_assignment PIN_AH19 -to VGA_R[4]
+set_location_assignment PIN_AF21 -to VGA_R[5]
+
+set_location_assignment PIN_AE19 -to VGA_G[0]
+set_location_assignment PIN_AG15 -to VGA_G[1]
+set_location_assignment PIN_AF18 -to VGA_G[2]
+set_location_assignment PIN_AG18 -to VGA_G[3]
+set_location_assignment PIN_AG19 -to VGA_G[4]
+set_location_assignment PIN_AG20 -to VGA_G[5]
+
+set_location_assignment PIN_AG21 -to VGA_B[0]
+set_location_assignment PIN_AA20 -to VGA_B[1]
+set_location_assignment PIN_AE22 -to VGA_B[2]
+set_location_assignment PIN_AF22 -to VGA_B[3]
+set_location_assignment PIN_AH23 -to VGA_B[4]
+set_location_assignment PIN_AH21 -to VGA_B[5]
+
+set_location_assignment PIN_AH22 -to VGA_HS
+set_location_assignment PIN_AG24 -to VGA_VS
+
+set_location_assignment PIN_AH27 -to VGA_EN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
+
+#============================================================
+# AUDIO
+#============================================================
+set_location_assignment PIN_AC24 -to AUDIO_L
+set_location_assignment PIN_AE25 -to AUDIO_R
+set_location_assignment PIN_AG26 -to AUDIO_SPDIF
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
+
+#============================================================
+# SDRAM
+#============================================================
+set_location_assignment PIN_Y11 -to SDRAM_A[0]
+set_location_assignment PIN_AA26 -to SDRAM_A[1]
+set_location_assignment PIN_AA13 -to SDRAM_A[2]
+set_location_assignment PIN_AA11 -to SDRAM_A[3]
+set_location_assignment PIN_W11 -to SDRAM_A[4]
+set_location_assignment PIN_Y19 -to SDRAM_A[5]
+set_location_assignment PIN_AB23 -to SDRAM_A[6]
+set_location_assignment PIN_AC23 -to SDRAM_A[7]
+set_location_assignment PIN_AC22 -to SDRAM_A[8]
+set_location_assignment PIN_C12 -to SDRAM_A[9]
+set_location_assignment PIN_AB26 -to SDRAM_A[10]
+set_location_assignment PIN_AD17 -to SDRAM_A[11]
+set_location_assignment PIN_D12 -to SDRAM_A[12]
+set_location_assignment PIN_Y17 -to SDRAM_BA[0]
+set_location_assignment PIN_AB25 -to SDRAM_BA[1]
+
+set_location_assignment PIN_E8 -to SDRAM_DQ[0]
+set_location_assignment PIN_V12 -to SDRAM_DQ[1]
+set_location_assignment PIN_D11 -to SDRAM_DQ[2]
+set_location_assignment PIN_W12 -to SDRAM_DQ[3]
+set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
+set_location_assignment PIN_D8 -to SDRAM_DQ[5]
+set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
+set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
+set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
+set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
+set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
+set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
+set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
+set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
+set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
+set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
+set_location_assignment PIN_AG13 -to SDRAM_DQML
+set_location_assignment PIN_AF13 -to SDRAM_DQMH
+
+set_location_assignment PIN_AD20 -to SDRAM_CLK
+set_location_assignment PIN_AG10 -to SDRAM_CKE
+
+set_location_assignment PIN_AA19 -to SDRAM_nWE
+set_location_assignment PIN_AA18 -to SDRAM_nCAS
+set_location_assignment PIN_Y18 -to SDRAM_nCS
+set_location_assignment PIN_W14 -to SDRAM_nRAS
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
+
+#============================================================
+# I/O
+#============================================================
+set_location_assignment PIN_Y15 -to LED_USER
+set_location_assignment PIN_AA15 -to LED_HDD
+set_location_assignment PIN_AG28 -to LED_POWER
+
+set_location_assignment PIN_AH24 -to BTN_USER
+set_location_assignment PIN_AG25 -to BTN_OSD
+set_location_assignment PIN_AG23 -to BTN_RESET
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
+
+#============================================================
+# CLOCK
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+set_location_assignment PIN_V11 -to FPGA_CLK1_50
+set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_E11 -to FPGA_CLK3_50
+
+#============================================================
+# HDMI
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
+set_location_assignment PIN_U10 -to HDMI_I2C_SCL
+set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
+set_location_assignment PIN_T13 -to HDMI_I2S
+set_location_assignment PIN_T11 -to HDMI_LRCLK
+set_location_assignment PIN_U11 -to HDMI_MCLK
+set_location_assignment PIN_T12 -to HDMI_SCLK
+set_location_assignment PIN_AG5 -to HDMI_TX_CLK
+set_location_assignment PIN_AD19 -to HDMI_TX_DE
+set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
+set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
+set_location_assignment PIN_W8 -to HDMI_TX_D[2]
+set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
+set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
+set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
+set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
+set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
+set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
+set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
+set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
+set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
+set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
+set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
+set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
+set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
+set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
+set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
+set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
+set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
+set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
+set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
+set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
+set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
+set_location_assignment PIN_T8 -to HDMI_TX_HS
+set_location_assignment PIN_AF11 -to HDMI_TX_INT
+set_location_assignment PIN_V13 -to HDMI_TX_VS
+
+#============================================================
+# KEY
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_location_assignment PIN_AH17 -to KEY[0]
+set_location_assignment PIN_AH16 -to KEY[1]
+
+#============================================================
+# LED
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+set_location_assignment PIN_W15 -to LED[0]
+set_location_assignment PIN_AA24 -to LED[1]
+set_location_assignment PIN_V16 -to LED[2]
+set_location_assignment PIN_V15 -to LED[3]
+set_location_assignment PIN_AF26 -to LED[4]
+set_location_assignment PIN_AE26 -to LED[5]
+set_location_assignment PIN_Y16 -to LED[6]
+set_location_assignment PIN_AA23 -to LED[7]
+
+#============================================================
+# SW
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_location_assignment PIN_Y24 -to SW[0]
+set_location_assignment PIN_W24 -to SW[1]
+set_location_assignment PIN_W21 -to SW[2]
+set_location_assignment PIN_W20 -to SW[3]
+
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
+
+set_global_assignment -name CDF_FILE jtag.cdf
+set_global_assignment -name QIP_FILE sys/sys.qip
+set_global_assignment -name QSYS_FILE sys/vip.qsys
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/sharpmz.sdc b/sharpmz.sdc
new file mode 100644
index 0000000..ca89e11
--- /dev/null
+++ b/sharpmz.sdc
@@ -0,0 +1,198 @@
+## SDC file "sharpmz.sdc"
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+#create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
+#create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
+#create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
+#create_clock -name {MCLK} -period 10.000 -waveform { 0.000 5.000 } [get_ports {SDRAM_CLK}]
+#create_clock -name {SDCLK} -period 100.000 -waveform { 0.000 50.000 } [get_ports {SDIO_CLK}]
+#create_clock -name {VMCLK} -period 10.000 -waveform { 0.000 5.000 } 
+
+#create_clock -name {CK32Mi} -period 31.250 -waveform { 0.000 15.625 }
+#create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+#                       -name HDMI_CLK [get_ports HDMI_TX_CLK]
+
+#create_generated_clock -source [get_pins -compatibility_mode {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK32Mi}] -name CK32Mi
+#create_generated_clock -source {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK8Mi} -name CK8Mi
+#create_generated_clock -source [get_pins -compatibility_mode {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|pll:PLLMAIN|pll_0002:pll_inst|altera_pll:altera_pll_i|outclk_wire[0]}] -name {CK32Mi} -period 31.250 
+#-waveform { 0.000 15.625 }
+
+
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[0]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[0]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[1]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[1]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[2]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[2]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[3]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[3]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[4]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[4]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[5]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[5]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[6]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[6]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[7]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[7]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[8]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[8]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[9]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[9]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[10]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[10]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[11]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[11]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[12]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[12]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[13]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[13]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[14]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[14]}]
+#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}]  6.000 [get_ports {SDRAM_DQ[15]}]
+#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}]  0.000 [get_ports {SDRAM_DQ[15]}]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[0]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[1]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[2]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[3]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[4]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[5]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[6]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[7]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[8]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[9]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_A[10]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_nCAS}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_nCS}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[0]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[1]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[2]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[3]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[4]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[5]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[6]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[7]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[8]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[9]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[10]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[11]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[12]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[13]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[14]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQ[15]}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQML}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_nRAS}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_DQMH}]
+#set_output_delay -add_delay  -clock [get_clocks {MCLK}]  0.000 [get_ports {SDRAM_nWE}]
+#set_output_delay -add_delay  -clock [get_clocks {SDCLK}]  0.000 [get_ports {SDIO_CMD}]
+#set_output_delay -add_delay  -clock [get_clocks {SDCLK}]  0.000 [get_ports {SDIO_DAT[3]}]
+#set_output_delay -add_delay  -clock [get_clocks {altera_reserved_tck}]  0.000 [get_ports {altera_reserved_tdo}]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] 
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
+#set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
+#set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
+#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] 
+#set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
+#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
+#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|*resetlatch}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[33]}]
+#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[0]}]
+#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_error}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[34]}]
+#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|*MonDReg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
+#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|*jdo*}]
+#set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|ir*}]
+#set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go}]
+#set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_writedata_d1*|*}] -to [get_registers *]
+#set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_nativeaddress_d1*|*}] -to [get_registers *]
+#set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
+#set_false_path -from [get_keepers -nocase {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/sharpmz.tl b/sharpmz.tl
new file mode 100644
index 0000000..f456e92
--- /dev/null
+++ b/sharpmz.tl
@@ -0,0 +1,371 @@
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+# Quartus Prime: Generate Tcl File for Project
+# File: sharpmz.tcl
+# Generated on: Wed Jun 20 13:50:16 2018
+
+# Load Quartus Prime Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+	if {[string compare $quartus(project) "sharpmz"]} {
+		puts "Project sharpmz is not open"
+		set make_assignments 0
+	}
+} else {
+	# Only open if not already open
+	if {[project_exists sharpmz]} {
+		project_open -revision sharpmz-lite sharpmz
+	} else {
+		project_new -revision sharpmz-lite sharpmz
+	}
+	set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+	set_global_assignment -name VERILOG_MACRO "LITE=1"
+	set_global_assignment -name FAMILY "Cyclone V"
+	set_global_assignment -name DEVICE 5CSEBA6U23I7
+	set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
+	set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
+	set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
+	set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
+	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+	set_global_assignment -name GENERATE_RBF_FILE ON
+	set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+	set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+	set_global_assignment -name SAVE_DISK_SPACE OFF
+	set_global_assignment -name SMART_RECOMPILE ON
+	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+	set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+	set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+	set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+	set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+	set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+	set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+	set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+	set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+	set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+	set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+	set_global_assignment -name SEED 1
+	set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
+	set_global_assignment -name CDF_FILE jtag.cdf
+	set_global_assignment -name QIP_FILE sys/sys.qip
+	set_global_assignment -name VHDL_FILE jtag_uart_0.vhd
+	set_global_assignment -name SYSTEMVERILOG_FILE sharpmz.sv
+	set_global_assignment -name VHDL_FILE mz80c/T80/T80_Reg.vhd
+	set_global_assignment -name VHDL_FILE mz80c/T80/T80_Pack.vhd
+	set_global_assignment -name VHDL_FILE mz80c/T80/T80_MCode.vhd
+	set_global_assignment -name VHDL_FILE mz80c/T80/T80_ALU.vhd
+	set_global_assignment -name VHDL_FILE mz80c/T80/T80.vhd
+	set_global_assignment -name VHDL_FILE mz80c/T80/T80s.vhd
+	set_global_assignment -name VHDL_FILE mz80c/cmt.vhd
+	set_global_assignment -name VHDL_FILE mz80c/counter0.vhd
+	set_global_assignment -name VHDL_FILE mz80c/counter1.vhd
+	set_global_assignment -name VHDL_FILE mz80c/counter2.vhd
+	set_global_assignment -name VHDL_FILE mz80c/dpram64k.vhd
+	set_global_assignment -name VHDL_FILE mz80c/dpram.vhd
+	set_global_assignment -name VHDL_FILE mz80c/i8253.vhd
+	set_global_assignment -name VHDL_FILE mz80c/i8255.vhd
+	set_global_assignment -name VHDL_FILE mz80c/keymatrix.vhd
+	set_global_assignment -name VHDL_FILE mz80c/ls367.vhd
+	set_global_assignment -name VHDL_FILE mz80c/mctrl.vhd
+	set_global_assignment -name VHDL_FILE mz80c/sharpmz.vhd
+	set_global_assignment -name VHDL_FILE mz80c/pcg.vhd
+	set_global_assignment -name VERILOG_FILE mz80c/pll_mz80c.v
+	set_global_assignment -name VERILOG_FILE mz80c/pll_mz80c_1.v
+	set_global_assignment -name VHDL_FILE mz80c/ps2kb.vhd
+	set_global_assignment -name VHDL_FILE mz80c/ScanConv.vhd
+	set_global_assignment -name VHDL_FILE mz80c/dprom.vhd
+	set_global_assignment -name VHDL_FILE mz80c/videoout.vhd
+	set_global_assignment -name VHDL_FILE mz80c/clk_div.vhd
+	set_global_assignment -name VHDL_FILE mz80c/clkgen.vhd
+	set_global_assignment -name VHDL_FILE mz80c/mrom.vhd
+	set_global_assignment -name VHDL_FILE mz80c/ram1k.vhd
+	set_global_assignment -name QIP_FILE mz80c/linebuf.qip
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+	set_location_assignment PIN_U9 -to ADC_CONVST
+	set_location_assignment PIN_V10 -to ADC_SCK
+	set_location_assignment PIN_AC4 -to ADC_SDI
+	set_location_assignment PIN_AD4 -to ADC_SDO
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
+	set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
+	set_location_assignment PIN_U14 -to ARDUINO_IO[4]
+	set_location_assignment PIN_U13 -to ARDUINO_IO[5]
+	set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
+	set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
+	set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
+	set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
+	set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
+	set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
+	set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
+	set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
+	set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
+	set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
+	set_location_assignment PIN_AF25 -to SDIO_DAT[0]
+	set_location_assignment PIN_AF23 -to SDIO_DAT[1]
+	set_location_assignment PIN_AD26 -to SDIO_DAT[2]
+	set_location_assignment PIN_AF28 -to SDIO_DAT[3]
+	set_location_assignment PIN_AF27 -to SDIO_CMD
+	set_location_assignment PIN_AH26 -to SDIO_CLK
+	set_location_assignment PIN_AH7 -to SDIO_CD
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
+	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
+	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
+	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
+	set_location_assignment PIN_AE17 -to VGA_R[0]
+	set_location_assignment PIN_AE20 -to VGA_R[1]
+	set_location_assignment PIN_AF20 -to VGA_R[2]
+	set_location_assignment PIN_AH18 -to VGA_R[3]
+	set_location_assignment PIN_AH19 -to VGA_R[4]
+	set_location_assignment PIN_AF21 -to VGA_R[5]
+	set_location_assignment PIN_AE19 -to VGA_G[0]
+	set_location_assignment PIN_AG15 -to VGA_G[1]
+	set_location_assignment PIN_AF18 -to VGA_G[2]
+	set_location_assignment PIN_AG18 -to VGA_G[3]
+	set_location_assignment PIN_AG19 -to VGA_G[4]
+	set_location_assignment PIN_AG20 -to VGA_G[5]
+	set_location_assignment PIN_AG21 -to VGA_B[0]
+	set_location_assignment PIN_AA20 -to VGA_B[1]
+	set_location_assignment PIN_AE22 -to VGA_B[2]
+	set_location_assignment PIN_AF22 -to VGA_B[3]
+	set_location_assignment PIN_AH23 -to VGA_B[4]
+	set_location_assignment PIN_AH21 -to VGA_B[5]
+	set_location_assignment PIN_AH22 -to VGA_HS
+	set_location_assignment PIN_AG24 -to VGA_VS
+	set_location_assignment PIN_AH27 -to VGA_EN
+	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
+	set_location_assignment PIN_AC24 -to AUDIO_L
+	set_location_assignment PIN_AE25 -to AUDIO_R
+	set_location_assignment PIN_AG26 -to AUDIO_SPDIF
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
+	set_location_assignment PIN_Y11 -to SDRAM_A[0]
+	set_location_assignment PIN_AA26 -to SDRAM_A[1]
+	set_location_assignment PIN_AA13 -to SDRAM_A[2]
+	set_location_assignment PIN_AA11 -to SDRAM_A[3]
+	set_location_assignment PIN_W11 -to SDRAM_A[4]
+	set_location_assignment PIN_Y19 -to SDRAM_A[5]
+	set_location_assignment PIN_AB23 -to SDRAM_A[6]
+	set_location_assignment PIN_AC23 -to SDRAM_A[7]
+	set_location_assignment PIN_AC22 -to SDRAM_A[8]
+	set_location_assignment PIN_C12 -to SDRAM_A[9]
+	set_location_assignment PIN_AB26 -to SDRAM_A[10]
+	set_location_assignment PIN_AD17 -to SDRAM_A[11]
+	set_location_assignment PIN_D12 -to SDRAM_A[12]
+	set_location_assignment PIN_Y17 -to SDRAM_BA[0]
+	set_location_assignment PIN_AB25 -to SDRAM_BA[1]
+	set_location_assignment PIN_E8 -to SDRAM_DQ[0]
+	set_location_assignment PIN_V12 -to SDRAM_DQ[1]
+	set_location_assignment PIN_D11 -to SDRAM_DQ[2]
+	set_location_assignment PIN_W12 -to SDRAM_DQ[3]
+	set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
+	set_location_assignment PIN_D8 -to SDRAM_DQ[5]
+	set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
+	set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
+	set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
+	set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
+	set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
+	set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
+	set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
+	set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
+	set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
+	set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
+	set_location_assignment PIN_AG13 -to SDRAM_DQML
+	set_location_assignment PIN_AF13 -to SDRAM_DQMH
+	set_location_assignment PIN_AD20 -to SDRAM_CLK
+	set_location_assignment PIN_AG10 -to SDRAM_CKE
+	set_location_assignment PIN_AA19 -to SDRAM_nWE
+	set_location_assignment PIN_AA18 -to SDRAM_nCAS
+	set_location_assignment PIN_Y18 -to SDRAM_nCS
+	set_location_assignment PIN_W14 -to SDRAM_nRAS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+	set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
+	set_location_assignment PIN_Y15 -to LED_USER
+	set_location_assignment PIN_AA15 -to LED_HDD
+	set_location_assignment PIN_AG28 -to LED_POWER
+	set_location_assignment PIN_AH24 -to BTN_USER
+	set_location_assignment PIN_AG25 -to BTN_OSD
+	set_location_assignment PIN_AG23 -to BTN_RESET
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
+	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+	set_location_assignment PIN_V11 -to FPGA_CLK1_50
+	set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+	set_location_assignment PIN_E11 -to FPGA_CLK3_50
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
+	set_location_assignment PIN_U10 -to HDMI_I2C_SCL
+	set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
+	set_location_assignment PIN_T13 -to HDMI_I2S
+	set_location_assignment PIN_T11 -to HDMI_LRCLK
+	set_location_assignment PIN_U11 -to HDMI_MCLK
+	set_location_assignment PIN_T12 -to HDMI_SCLK
+	set_location_assignment PIN_AG5 -to HDMI_TX_CLK
+	set_location_assignment PIN_AD19 -to HDMI_TX_DE
+	set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
+	set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
+	set_location_assignment PIN_W8 -to HDMI_TX_D[2]
+	set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
+	set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
+	set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
+	set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
+	set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
+	set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
+	set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
+	set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
+	set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
+	set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
+	set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
+	set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
+	set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
+	set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
+	set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
+	set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
+	set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
+	set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
+	set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
+	set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
+	set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
+	set_location_assignment PIN_T8 -to HDMI_TX_HS
+	set_location_assignment PIN_AF11 -to HDMI_TX_INT
+	set_location_assignment PIN_V13 -to HDMI_TX_VS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+	set_location_assignment PIN_AH17 -to KEY[0]
+	set_location_assignment PIN_AH16 -to KEY[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+	set_location_assignment PIN_W15 -to LED[0]
+	set_location_assignment PIN_AA24 -to LED[1]
+	set_location_assignment PIN_V16 -to LED[2]
+	set_location_assignment PIN_V15 -to LED[3]
+	set_location_assignment PIN_AF26 -to LED[4]
+	set_location_assignment PIN_AE26 -to LED[5]
+	set_location_assignment PIN_Y16 -to LED[6]
+	set_location_assignment PIN_AA23 -to LED[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+	set_location_assignment PIN_Y24 -to SW[0]
+	set_location_assignment PIN_W24 -to SW[1]
+	set_location_assignment PIN_W21 -to SW[2]
+	set_location_assignment PIN_W20 -to SW[3]
+	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# Including default assignments
+	set_global_assignment -name REVISION_TYPE BASE -family "Cyclone V"
+	set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS OFF -family "Cyclone V"
+	set_global_assignment -name TIMEQUEST_CCPP_TRADEOFF_TOLERANCE 0 -family "Cyclone V"
+	set_global_assignment -name TDC_CCPP_TRADEOFF_TOLERANCE 30 -family "Cyclone V"
+	set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -family "Cyclone V"
+	set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+	set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -family "Cyclone V"
+	set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+	set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ON -family "Cyclone V"
+	set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" -family "Cyclone V"
+	set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -family "Cyclone V"
+	set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -family "Cyclone V"
+	set_global_assignment -name AUTO_DELAY_CHAINS ON -family "Cyclone V"
+	set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON -family "Cyclone V"
+	set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ -family "Cyclone V"
+	set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION ON -family "Cyclone V"
+	set_global_assignment -name ENABLE_OCT_DONE OFF -family "Cyclone V"
+
+	# Commit assignments
+	export_assignments
+
+	# Close project
+	if {$need_to_close_project} {
+		project_close
+	}
+}
diff --git a/sharpmz.vhd b/sharpmz.vhd
new file mode 100644
index 0000000..f0d3b24
--- /dev/null
+++ b/sharpmz.vhd
@@ -0,0 +1,1636 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            sharpmz.vhd
+-- Created:         June 2018
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ series compatible logic.
+--                                                     
+--                  This module is the main (top level) container for the Emulation.
+--
+--                  The design tries to work from top-down, where components which are common 
+--                  to the Business and Personal MZ series are at the top (ie. main memory,
+--                  ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
+--                  to the machine specific modules and components. Some components are common
+--                  by their nature (ie. 8255 PIO) but these are instantiated within the lower
+--                  tree branch as their design use is less generic.
+--
+--                  The tree is as follows;-
+--
+--                                      (emu) sharpmz.vhd (mz80c)	->	mz80c.vhd
+--                                      |
+--                                      |
+--                                      |                                         -> cmt.vhd                   (common)
+--                                      |                                         -> keymatrix.vhd             (common)
+--                                      |                                         -> pll.v                     (common)
+--                                      |                                         -> clkgen.vhd                (common)
+--                                      |                                         -> T80                       (common)
+--                                      |                                         -> i8255                     (common)
+--                  sys_top.sv (emu) ->	(emu) sharpmz.vhd (hps_io) -> hps_io.sv
+--                                      |                                         -> i8253                     (common)
+--                                      |                                         -> dpram.vhd                 (common)
+--                                      |                                         -> dprom.vhd                 (common)
+--                                      |                                         -> mctrl.vhd                 (common)
+--                                      |                                         -> video.vhd                 (common)
+--                                      |
+--                                      |
+--                                      (emu) sharpmz.vhd (mz80b)	->	mz80b.vhd
+--
+--                  The idea of the design is to keep the emulation as independent of the HPS
+--                  as possible (so it works standalone), only needing the HPS to set control registers,
+--                  load tape ram and overlay the menu system. This in theory should allow easier
+--                  porting if someone wants to port this emulator to another platform or even
+--                  target an non-HPS Cyclone chip and instantiate another CPU as the menu control.
+--
+--                  As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used
+--                  by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory (or the
+--                  external SDRAM) depending on wether I decide to cache entire Floppy Disks as per the CMT
+--                  unit.
+--
+-- Credits:         Credit to Nibbles Lab. 2012-2016, as I was originally going to port his mz80c_de0 emulator
+--                  based on a Terasic DE0 board. He used external memory and an instantiated NIOSII CPU
+--                  to provide a menu/control system. Some snippets of his code, such as the keyboard matrix
+--                  have been re-used in this emulation.
+-- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         June 2018 - Initial creation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use pkgs.config_pkg.all;
+use pkgs.clkgen_pkg.all;
+use pkgs.mctrl_pkg.all;
+
+entity sharpmz is
+  port(
+        --------------------                Clock Input                         ----------------------------     
+        CLKMASTER             : in     std_logic;                               -- Master Clock(50MHz)
+        CLKSYS                : out    std_logic;                               -- System clock.
+        CLKVID                : out    std_logic;                               -- Pixel base clock of video.
+        CLKIOP                : out    std_logic;                               -- IO Processor Clock.
+        --------------------                Reset                               ----------------------------
+        COLD_RESET            : in     std_logic;
+        WARM_RESET            : in     std_logic;
+        --------------------                        main_leds                   ----------------------------
+        MAIN_LEDS             : out    std_logic_vector(7 downto 0);            -- main_leds Green[7:0]
+        --------------------                        PS2                         ----------------------------
+        PS2_KEY               : in     std_logic_vector(10 downto 0);           -- PS2 Key data.
+        --------------------                        VGA                         ----------------------------
+        VGA_HB_O              : out    std_logic;                               -- VGA Horizontal Blank
+        VGA_VB_O              : out    std_logic;                               -- VGA Vertical Blank
+        VGA_HS_O              : out    std_logic;                               -- VGA H_SYNC
+        VGA_VS_O              : out    std_logic;                               -- VGA V_SYNC
+        VGA_R_O               : out    std_logic_vector(7 downto 0);            -- VGA Red[3:0], [7:4] = 0
+        VGA_G_O               : out    std_logic_vector(7 downto 0);            -- VGA Green[3:0]
+        VGA_B_O               : out    std_logic_vector(7 downto 0);            -- VGA Blue[3:0]
+        --------------------                        AUDIO                       ------------------------------
+        AUDIO_L_O             : out    std_logic;
+        AUDIO_R_O             : out    std_logic;
+        --------------------                      HPS Interface                 ------------------------------
+        IOCTL_DOWNLOAD        : in     std_logic;                               -- Downloading to FPGA.
+        IOCTL_UPLOAD          : in     std_logic;                               -- Uploading from FPGA.
+        IOCTL_CLK             : in     std_logic;                               -- I/O Clock.
+        IOCTL_WR              : in     std_logic;                               -- Write Enable to FPGA.
+        IOCTL_RD              : in     std_logic;                               -- Read Enable from FPGA.
+        IOCTL_ADDR            : in     std_logic_vector(24 downto 0);           -- Address in FPGA to write into.
+        IOCTL_DOUT            : in     std_logic_vector(31 downto 0);           -- Data to be written into FPGA.
+        IOCTL_DIN             : out    std_logic_vector(31 downto 0)            -- Data to be read into HPS.
+);
+end sharpmz;
+
+architecture rtl of sharpmz is
+
+-- Parent signals brought out onto wires.
+--
+signal MZ_PS2_KEY            :     std_logic_vector(10 downto 0);
+--
+-- Keyboard
+--
+signal MZ_KEYB_SCAN          :     std_logic_vector(3 downto 0);
+signal MZ_KEYB_DATA          :     std_logic_vector(7 downto 0);
+signal MZ_KEYB_STALL         :     std_logic;
+signal MZ_KEYB_BREAKDETECT   :     std_logic;
+--
+-- Master Control signals and configuration.
+--
+signal MZ_SYSTEM_RESET       :     std_logic;
+signal MZ_MEMWR              :     std_logic;
+--
+-- Signal BUS's
+--
+signal CLKBUS                :     std_logic_vector(CLKBUS_WIDTH);
+signal CONFIG                :     std_logic_vector(CONFIG_WIDTH);
+signal DEBUG                 :     std_logic_vector(DEBUG_WIDTH);
+signal MZ_CMT_BUS_OUT        :     std_logic_vector(CMT_BUS_OUT_WIDTH);
+--
+-- HPS Control.
+--
+signal MZ_IOCTL_DOWNLOAD     :     std_logic;
+signal MZ_IOCTL_UPLOAD       :     std_logic;
+signal MZ_IOCTL_CLK          :     std_logic;
+signal MZ_IOCTL_WR           :     std_logic;
+signal MZ_IOCTL_RD           :     std_logic;
+signal MZ_IOCTL_ADDR         :     std_logic_vector(24 downto 0);
+signal MZ_IOCTL_DOUT         :     std_logic_vector(31 downto 0);
+signal MZ_IOCTL_DIN_SYSROM   :     std_logic_vector(7 downto 0);
+signal MZ_IOCTL_DIN_SYSRAM   :     std_logic_vector(7 downto 0);
+signal MZ_IOCTL_DIN_VIDEO    :     std_logic_vector(31 downto 0);
+signal MZ_IOCTL_DIN_MZ80C    :     std_logic_vector(31 downto 0);
+signal MZ_IOCTL_DIN_MZ80B    :     std_logic_vector(31 downto 0);
+signal MZ_IOCTL_DIN_MCTRL    :     std_logic_vector(31 downto 0);
+signal MZ_IOCTL_DIN_CMT      :     std_logic_vector(31 downto 0);
+signal MZ_IOCTL_DIN_KEY      :     std_logic_vector(31 downto 0);
+signal MZ_IOCTL_WENROM       :     std_logic;
+signal MZ_IOCTL_WENRAM       :     std_logic;
+signal MZ_IOCTL_RENROM       :     std_logic;
+signal MZ_IOCTL_RENRAM       :     std_logic;
+--
+-- T80 for MZ80C
+--
+signal MZ80C_BUSRQ_n         :     std_logic;
+signal MZ80C_MWR_n           :     std_logic;
+signal MZ80C_MRD_n           :     std_logic;
+signal MZ80C_IWR_n           :     std_logic;
+signal MZ80C_WAIT_n          :     std_logic;
+signal MZ80C_INT_n           :     std_logic;
+signal MZ80C_DI              :     std_logic_vector(7 downto 0);
+signal MZ80C_NMI_n           :     std_logic;
+--
+-- Tape Control 
+--
+signal MZ80C_CMT_BUS_IN      :     std_logic_vector(CMT_BUS_IN_WIDTH);
+--
+-- Keyboard
+--
+signal MZ80C_KEYB_SCAN       :     std_logic_vector(3 downto 0);
+signal MZ80C_KEYB_STALL      :     std_logic;
+--
+-- Video 
+--
+signal MZ_R                  :     std_logic_vector(7 downto 0);
+signal MZ_B                  :     std_logic_vector(7 downto 0);
+signal MZ_G                  :     std_logic_vector(7 downto 0);
+signal MZ_VGATE_n            :     std_logic;
+signal MZ_DISPLAY_INVERT_n   :     std_logic;
+signal MZ_DISPLAY_CHAR80     :     std_logic;
+signal MZ_HSYNC_n            :     std_logic;
+signal MZ_VSYNC_n            :     std_logic;
+signal MZ_HBLANK             :     std_logic;
+signal MZ_VBLANK             :     std_logic;
+--
+-- Selects for MZ80C.
+--
+signal MZ80C_CS_ROM_n        :     std_logic;
+signal MZ80C_CS_RAM_n        :     std_logic;
+signal MZ80C_CS_VRAM_n       :     std_logic;
+signal MZ80C_CS_MEM_G_n      :     std_logic;
+signal MZ80C_CS_GRAM_n       :     std_logic;
+signal MZ80C_CS_GRAM_80B_n   :     std_logic;
+signal MZ80C_CS_IO_GFB_n     :     std_logic;
+--
+-- Audio for MZ80C
+--
+signal MZ80C_AUDIO_L         :     std_logic;
+signal MZ80C_AUDIO_R         :     std_logic;
+--
+-- Video signals for MZ80C
+--
+signal MZ80C_VGATE_n         :     std_logic;
+--
+-- Debug for MZ80C
+--
+signal MZ80C_DEBUG_LEDS      :     std_logic_vector(111 downto 0);
+--
+-- T80 for MZ80B
+--
+signal MZ80B_BUSRQ_n         :     std_logic;
+signal MZ80B_MWR_n           :     std_logic;
+signal MZ80B_MRD_n           :     std_logic;
+signal MZ80B_IWR_n           :     std_logic;
+signal MZ80B_WAIT_n          :     std_logic;
+signal MZ80B_INT_n           :     std_logic;
+signal MZ80B_DI              :     std_logic_vector(7 downto 0);
+signal MZ80B_NMI_n           :     std_logic;
+--
+-- Selects for MZ80B.
+--
+signal MZ80B_CS_ROM_n        :     std_logic;
+signal MZ80B_CS_RAM_n        :     std_logic;
+signal MZ80B_CS_VRAM_n       :     std_logic;
+signal MZ80B_CS_GRAM_n       :     std_logic;
+signal MZ80B_CS_IO_GFB_n     :     std_logic;
+signal MZ80B_CS_IO_G_n       :     std_logic;
+--
+-- Audio for MZ80B
+--
+signal MZ80B_AUDIO_L         :     std_logic;
+signal MZ80B_AUDIO_R         :     std_logic;
+--
+-- Video signals for MZ80B
+--
+signal MZ80B_VGATE_n         :     std_logic;
+--
+-- Tape Control 
+--
+signal MZ80B_CMT_BUS_IN      :     std_logic_vector(CMT_BUS_IN_WIDTH);
+--
+-- Keyboard
+--
+signal MZ80B_KEYB_SCAN       :     std_logic_vector(3 downto 0);
+signal MZ80B_KEYB_STALL      :     std_logic;
+--
+-- Debug for MZ80B
+--
+signal MZ80B_DEBUG_LEDS      :     std_logic_vector(111 downto 0);
+--
+-- T80
+--
+signal T80_RST_n             :     std_logic;
+signal T80_MREQ_n            :     std_logic;
+signal T80_BUSRQ_n           :     std_logic;
+signal T80_IORQ_n            :     std_logic;
+signal T80_WR_n              :     std_logic;
+signal T80_RD_n              :     std_logic;
+signal T80_WAIT_n            :     std_logic;
+signal T80_M1_n              :     std_logic;
+signal T80_RFSH_n            :     std_logic;
+signal T80_A16               :     std_logic_vector(15 downto 0);
+signal T80_INT_n             :     std_logic;
+signal T80_DO                :     std_logic_vector(7 downto 0);
+signal T80_DI                :     std_logic_vector(7 downto 0);
+signal T80_BUSAK_n           :     std_logic;
+signal T80_NMI_n             :     std_logic;
+signal T80_HALT_n            :     std_logic;
+--
+-- Decodes, control, misc
+--
+signal WENSYSRAM             :     std_logic;
+--
+-- Monitor ROM
+--
+signal SYSROM_DO             :     std_logic_vector(7 downto 0);
+signal MZ_CS_ROM_n           :     std_logic;
+signal MROM_BANK             :     std_logic_vector(5 downto 0);
+--
+-- Static RAM
+--
+signal SYSRAM_DO             :     std_logic_vector(7 downto 0);
+signal MZ_CS_RAM_n           :     std_logic;
+signal MZ_SYSMEM_A16         :     std_logic_vector(15 downto 0);
+signal MZ_SWP_MEM_BANK_n     :     std_logic;
+--
+-- Graphics RAM control signals.
+--
+signal VRAM_DO               :     std_logic_vector(7 downto 0);
+signal MZ_CS_VRAM_n          :     std_logic;
+signal MZ_CS_MEM_G_n         :     std_logic;
+signal MZ_CS_GRAM_n          :     std_logic;
+signal MZ_CS_GRAM_80B_n      :     std_logic;
+signal MZ_CS_IO_GFB_n        :     std_logic;
+signal MZ_CS_IO_G_n          :     std_logic;
+signal VIDEO_WAIT_n          :     std_logic;
+--
+-- Tape Control 
+--
+signal MZ_CMT_BUS_IN         :     std_logic_vector(CMT_BUS_IN_WIDTH);
+signal MZ_CMT_DEBUG_LEDS     :     std_logic_vector(31 downto 0);
+--
+-- Debug and internal process signals.
+--
+signal debug_counter         :     integer range 0 to 13       := 0;
+signal flip_counter          :     integer range 0 to 10000000 := 0;
+signal block_flip            :     integer range 0 to 800000   := 0;
+signal bank_flip             :     integer range 0 to 10000000 := 0;
+
+--
+-- Components
+--
+component clkgen
+    Port (
+          RST                : in  std_logic;                            -- Reset
+
+          -- Clocks
+          CKBASE             : in  std_logic;                            -- Base system main clock.
+          CLKBUS             : out std_logic_vector(CLKBUS_WIDTH);       -- Clock signals created by this module.
+
+          -- Different operations modes.
+          CONFIG             : in  std_logic_vector(CONFIG_WIDTH);        
+
+          -- Debug modes.
+          DEBUG              : in  std_logic_vector(DEBUG_WIDTH) 
+    );
+end component;
+
+component T80se
+    generic (
+          Mode               :     integer := 0;                         -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+          T2Write            :     integer := 1;                         -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+          IOWait             :     integer := 1                          -- 0 => Single cycle I/O, 1 => Std I/O cycle
+    );
+    Port (
+          RESET_n            : in  std_logic;
+          CLK_n              : in  std_logic;                            -- NB. Clock is high active.
+          CLKEN              : in  std_logic;
+          WAIT_n             : in  std_logic;
+          INT_n              : in  std_logic;
+          NMI_n              : in  std_logic;
+          BUSRQ_n            : in  std_logic;
+          M1_n               : out std_logic;
+          MREQ_n             : out std_logic;
+          IORQ_n             : out std_logic;
+          RD_n               : out std_logic;
+          WR_n               : out std_logic;
+          RFSH_n             : out std_logic;
+          HALT_n             : out std_logic;
+          BUSAK_n            : out std_logic;
+          A                  : out std_logic_vector(15 downto 0);
+          DI                 : in  std_logic_vector(7 downto 0);
+          DO                 : out std_logic_vector(7 downto 0)
+    );
+end component;
+
+component dpram
+    generic (
+          init_file          : string;
+          widthad_a          : natural;
+          width_a            : natural;
+          widthad_b          : natural;
+          width_b            : natural;
+          outdata_reg_a      : string := "UNREGISTERED";
+          outdata_reg_b      : string := "UNREGISTERED"
+    );
+    Port (
+          clock_a            : in  std_logic  := '1';
+          clocken_a          : in  std_logic  := '1';
+          address_a          : in  std_logic_vector (widthad_a-1 downto 0);
+          data_a             : in  std_logic_vector (width_a-1 downto 0);
+          wren_a             : in  std_logic  := '0';
+          q_a                : out std_logic_vector (width_a-1 downto 0);
+
+          clock_b            : in  std_logic;
+          clocken_b          : in  std_logic  := '1';
+          address_b          : in  std_logic_vector (widthad_b-1 downto 0);
+          data_b             : in  std_logic_vector (width_b-1 downto 0);
+          wren_b             : in  std_logic  := '0';
+          q_b                : out std_logic_vector (width_b-1 downto 0)
+      );
+end component;
+
+component mctrl
+    Port (
+          -- Clock signals used by this module.
+          CLKBUS             : in  std_logic_vector(CLKBUS_WIDTH);
+
+          -- Reset's
+          COLD_RESET         : in  std_logic;
+          WARM_RESET         : in  std_logic;
+          SYSTEM_RESET       : out std_logic;
+
+          -- HPS Interface
+          IOCTL_CLK          : in  std_logic;                            -- HPS I/O Clock
+          IOCTL_WR           : in  std_logic;                            -- HPS Write Enable to FPGA.
+          IOCTL_RD           : in  std_logic;                            -- HPS Read Enable from FPGA.
+          IOCTL_ADDR         : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+          IOCTL_DOUT         : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+          IOCTL_DIN          : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+          -- Different operations modes.
+          CONFIG             : out std_logic_vector(CONFIG_WIDTH);
+
+          -- Cassette magnetic tape signals.
+          CMT_BUS_OUT        : in  std_logic_vector(CMT_BUS_OUT_WIDTH);
+          CMT_BUS_IN         : in  std_logic_vector(CMT_BUS_IN_WIDTH);
+
+          -- MZ80B series can dynamically change the video frequency to attain 40/80 character display.
+          CONFIG_CHAR80      : in  std_logic;
+
+          -- Debug modes.
+          DEBUG              : out std_logic_vector(DEBUG_WIDTH) 
+    );
+end component;
+
+component video is
+    Port (
+        RST_n                : in  std_logic;                            -- Reset
+
+        -- Different operations modes.
+        CONFIG               : in  std_logic_vector(CONFIG_WIDTH);
+
+        -- Clocks
+        CLKBUS               : in  std_logic_vector(CLKBUS_WIDTH);       -- Clock signals created by clkgen module.
+
+        -- CPU Signals
+        T80_A                : in  std_logic_vector(13 downto 0);        -- CPU Address Bus
+        T80_RD_n             : in  std_logic;                            -- CPU Read Signal
+        T80_WR_n             : in  std_logic;                            -- CPU Write Signal
+        T80_MREQ_n           : in  std_logic;                            -- CPU Memory Request
+        T80_BUSACK_n         : in  std_logic;                            -- CPU Bus Acknowledge
+        T80_WAIT_n           : out std_logic;                            -- CPU Wait Request
+        T80_DI               : in  std_logic_vector(7 downto 0);         -- CPU Data Bus in
+        T80_DO               : out std_logic_vector(7 downto 0);         -- CPU Data Bus out
+
+        -- Selects.
+        CS_VRAM_n            : in  std_logic;                            -- VRAM Select
+        CS_MEM_G_n           : in  std_logic;                            -- Peripherals Select
+        CS_GRAM_n            : in  std_logic;                            -- Colour GRAM Select
+        CS_GRAM_80B_n        : in  std_logic;                            -- MZ80B GRAM Select
+        CS_IO_GFB_n          : in  std_logic;                            -- Graphics FB IO Select range
+        CS_IO_G_n            : in  std_logic;                            -- Graphics Options IO Select range
+
+        -- Video Signals
+        VGATE_n              : in  std_logic;                            -- Video Output Control
+        INVERSE_n            : in  std_logic;                            -- Invert video display.
+        CONFIG_CHAR80        : in  std_logic;                            -- 40 Char = 0, 80 Char = 1 select.
+        HBLANK               : out std_logic;                            -- Horizontal Blanking
+        VBLANK               : out std_logic;                            -- Vertical Blanking
+        HSYNC_n              : out std_logic;                            -- Horizontal Sync
+        VSYNC_n              : out std_logic;                            -- Vertical Sync
+        ROUT                 : out std_logic_vector(7 downto 0);         -- Red Output
+        GOUT                 : out std_logic_vector(7 downto 0);         -- Green Output
+        BOUT                 : out std_logic_vector(7 downto 0);         -- Green Output
+
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_UPLOAD         : in  std_logic;                            -- HPS Uploading from FPGA.
+        IOCTL_CLK            : in  std_logic;                            -- HPS I/O Clock.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable to FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(31 downto 0)         -- HPS Data to be read into HPS.
+    );
+end component;
+
+component keymatrix
+    Port (
+        RST_n                : in  std_logic;
+
+        -- i8255
+        PA                   : in  std_logic_vector(3 downto 0);
+        PB                   : out std_logic_vector(7 downto 0);
+        STALL                : in  std_logic;
+        BREAKDETECT          : out std_logic;
+
+        -- PS/2 Keyboard Data
+        PS2_KEY              : in  std_logic_vector(10 downto 0);        -- PS2 Key data.
+
+        -- Different operations modes.
+        CONFIG               : in  std_logic_vector(CONFIG_WIDTH);
+
+        -- Clock signals created by this module.
+        CLKBUS               : in  std_logic_vector(CLKBUS_WIDTH);
+
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_UPLOAD         : in  std_logic;                            -- HPS Uploading from FPGA.
+        IOCTL_CLK            : in  std_logic;                            -- HPS I/O Clock.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable to FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(31 downto 0)         -- HPS Data to be read into HPS.
+    );
+end component;
+
+component cmt
+    Port (
+        -- HPS Bus
+        RST                  : in  std_logic;
+
+        -- Clock signals created by this module.
+        CLKBUS               : in  std_logic_vector(CLKBUS_WIDTH);
+
+        -- Different operations modes.
+        CONFIG               : in  std_logic_vector(CONFIG_WIDTH);
+
+        -- Cassette magnetic tape signals.
+        CMT_BUS_OUT          : out std_logic_vector(CMT_BUS_OUT_WIDTH);
+        CMT_BUS_IN           : in  std_logic_vector(CMT_BUS_IN_WIDTH);
+
+        -- HPS Interface
+        IOCTL_DOWNLOAD       : in  std_logic;                            -- HPS Downloading to FPGA.
+        IOCTL_UPLOAD         : in  std_logic;                            -- HPS Uploading from FPGA.
+        IOCTL_CLK            : in  std_logic;                            -- HPS I/O Clock.
+        IOCTL_WR             : in  std_logic;                            -- HPS Write Enable to FPGA.
+        IOCTL_RD             : in  std_logic;                            -- HPS Read Enable from FPGA.
+        IOCTL_ADDR           : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+        IOCTL_DOUT           : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+        IOCTL_DIN            : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+        -- Debug Status Leds
+        DEBUG_STATUS_LEDS    : out std_logic_vector(31 downto 0)         -- 24 leds to display cmt internal status.
+    );
+end component;
+
+component mz80c
+    PORT (
+          -- Clocks
+          CLKBUS             : in  std_logic_vector(CLKBUS_WIDTH);    -- Clock signals created by this module.
+
+          -- Resets.
+          COLD_RESET         : in  std_logic;
+          SYSTEM_RESET       : in  std_logic;
+          
+          -- Z80 CPU
+          T80_RST_n          : in  std_logic;
+          T80_WAIT_n         : out std_logic;
+          T80_INT_n          : out std_logic;
+          T80_NMI_n          : out std_logic;
+          T80_BUSRQ_n        : out std_logic;
+          T80_M1_n           : in  std_logic;
+          T80_MREQ_n         : in  std_logic;
+          T80_IORQ_n         : in  std_logic;
+          T80_RD_n           : in  std_logic;
+          T80_WR_n           : in  std_logic;
+          T80_RFSH_n         : in  std_logic;
+          T80_HALT_n         : in  std_logic;
+          T80_BUSAK_n        : in  std_logic;
+          T80_A16            : in  std_logic_vector(15 downto 0);
+          T80_DI             : out std_logic_vector(7 downto 0);
+          T80_DO             : in  std_logic_vector(7 downto 0);
+
+          -- Chip selects to common resources.
+          CS_ROM_n           : out std_logic;
+          CS_RAM_n           : out std_logic;
+          CS_VRAM_n          : out std_logic;                            -- VRAM Select
+          CS_MEM_G_n         : out std_logic;                            -- Memory mapped Peripherals Select
+          CS_GRAM_n          : out std_logic;                            -- Colour GRAM Select
+          CS_IO_GFB_n        : out std_logic;                            -- Graphics FB IO Select range
+
+          -- Audio.
+          AUDIO_L            : out std_logic;
+          AUDIO_R            : out std_logic;
+
+          -- Different operations modes.
+          CONFIG             : in  std_logic_vector(CONFIG_WIDTH);
+
+          -- I/O                                                         -- I/O down to the core.
+          KEYB_SCAN          : out std_logic_vector(3 downto 0);         -- Keyboard scan lines out.
+          KEYB_DATA          : in  std_logic_vector(7 downto 0);         -- Keyboard scan data in.
+          KEYB_STALL         : out std_logic;                            -- Keyboard Stall out.
+
+          -- Cassette magnetic tape signals.
+          CMT_BUS_OUT        : in  std_logic_vector(CMT_BUS_OUT_WIDTH);
+          CMT_BUS_IN         : out std_logic_vector(CMT_BUS_IN_WIDTH);
+
+          -- Video
+          VGATE_n            : out std_logic;
+          HBLANK             : in  std_logic;                            -- Horizontal Blanking Signal
+          VBLANK             : in  std_logic;                            -- Vertical Blanking Signal          
+
+          -- HPS Interface
+          IOCTL_DOWNLOAD     : in  std_logic;                            -- HPS Downloading to FPGA.
+          IOCTL_UPLOAD       : in  std_logic;                            -- HPS Uploading from FPGA.
+          IOCTL_CLK          : in  std_logic;                            -- HPS I/O Clock
+          IOCTL_WR           : in  std_logic;                            -- HPS Write Enable to FPGA.
+          IOCTL_RD           : in  std_logic;                            -- HPS Read Enable from FPGA.
+          IOCTL_ADDR         : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+          IOCTL_DOUT         : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+          IOCTL_DIN          : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+          -- Debug Status Leds
+          DEBUG_STATUS_LEDS  : out std_logic_vector(111 downto 0)        -- 112 leds to display status.
+    );
+end component;
+
+component mz80b
+    PORT (
+          -- Clocks
+          CLKBUS             : in  std_logic_vector(CLKBUS_WIDTH);    -- Clock signals created by this module.
+
+          -- Resets.
+          COLD_RESET         : in  std_logic;
+          SYSTEM_RESET       : in  std_logic;
+          
+          -- Z80 CPU
+          T80_RST_n          : in  std_logic;
+          T80_WAIT_n         : out std_logic;
+          T80_INT_n          : out std_logic;
+          T80_NMI_n          : out std_logic;
+          T80_BUSRQ_n        : out std_logic;
+          T80_M1_n           : in  std_logic;
+          T80_MREQ_n         : in  std_logic;
+          T80_IORQ_n         : in  std_logic;
+          T80_RD_n           : in  std_logic;
+          T80_WR_n           : in  std_logic;
+          T80_RFSH_n         : in  std_logic;
+          T80_HALT_n         : in  std_logic;
+          T80_BUSAK_n        : in  std_logic;
+          T80_A16            : in  std_logic_vector(15 downto 0);
+          T80_DI             : out std_logic_vector(7 downto 0);
+          T80_DO             : in  std_logic_vector(7 downto 0);
+
+          -- Chip selects to common resources.
+          CS_ROM_n           : out std_logic;
+          CS_RAM_n           : out std_logic;
+          CS_VRAM_n          : out std_logic;                            -- VRAM Select
+          CS_GRAM_n          : out std_logic;                            -- Colour GRAM Select
+          CS_GRAM_80B_n      : out std_logic;                            -- MZ80B GRAM Select
+          CS_IO_GFB_n        : out std_logic;                            -- Graphics FB IO Select range
+          CS_IO_G_n          : out std_logic;                            -- Graphics Options IO Select range
+          CS_SWP_MEMBANK_n   : out std_logic;                            -- Move lower 32K into upper block.
+
+          -- Audio.
+          AUDIO_L            : out std_logic;
+          AUDIO_R            : out std_logic;
+
+          -- Different operations modes.
+          CONFIG             : in  std_logic_vector(CONFIG_WIDTH);
+
+          -- I/O                                                         -- I/O down to the core.
+          KEYB_SCAN          : out std_logic_vector(3 downto 0);         -- Keyboard scan lines out.
+          KEYB_DATA          : in  std_logic_vector(7 downto 0);         -- Keyboard scan data in.
+          KEYB_STALL         : out std_logic;                            -- Keyboard Stall out.
+          KEYB_BREAKDETECT   : in  std_logic;                            -- Keyboard break detect.
+
+          -- Cassette magnetic tape signals.
+          CMT_BUS_OUT        : in  std_logic_vector(CMT_BUS_OUT_WIDTH);
+          CMT_BUS_IN         : out std_logic_vector(CMT_BUS_IN_WIDTH);
+
+          -- Video
+          VGATE_n            : out std_logic;
+          INVERSE_n          : out std_logic;                            -- Invert video display.
+          CONFIG_CHAR80      : out std_logic;                            -- 40 Char = 0, 80 Char = 1 select.
+          HBLANK             : in  std_logic;                            -- Horizontal Blanking Signal
+          VBLANK             : in  std_logic;                            -- Vertical Blanking Signal
+
+          -- HPS Interface
+          IOCTL_DOWNLOAD     : in  std_logic;                            -- HPS Downloading to FPGA.
+          IOCTL_UPLOAD       : in  std_logic;                            -- HPS Uploading from FPGA.
+          IOCTL_CLK          : in  std_logic;                            -- HPS I/O Clock
+          IOCTL_WR           : in  std_logic;                            -- HPS Write Enable to FPGA.
+          IOCTL_RD           : in  std_logic;                            -- HPS Read Enable from FPGA.
+          IOCTL_ADDR         : in  std_logic_vector(24 downto 0);        -- HPS Address in FPGA to write into.
+          IOCTL_DOUT         : in  std_logic_vector(31 downto 0);        -- HPS Data to be written into FPGA.
+          IOCTL_DIN          : out std_logic_vector(31 downto 0);        -- HPS Data to be read into HPS.
+
+          -- Debug Status Leds
+          DEBUG_STATUS_LEDS  : out std_logic_vector(111 downto 0)        -- 112 leds to display status.
+    );
+end component;
+
+begin
+
+    --
+    -- Instantiation
+    --
+    CLKGEN0 :  clkgen port map (
+            RST              => cold_reset,                              -- Reset
+
+            -- Clocks
+            CKBASE           => CLKMASTER,                               -- Input clocks from top level.
+            CLKBUS           => CLKBUS,                                  -- Clock signals created by this module.
+
+            -- Different operations modes.
+            CONFIG           => CONFIG,
+
+            -- Debug modes.
+            DEBUG            => DEBUG
+    );
+
+    CPU0 : T80se
+        generic map (
+            Mode             => 0,                                       -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+            T2Write          => 1,                                       -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+            IOWait           => 1                                        -- 0 => Single cycle I/O, 1 => Std I/O cycle
+        )
+        port map (
+            RESET_n          => T80_RST_n,                               -- Reset signal.
+            CLK_n            => CLKBUS(CKMASTER),                        -- T80se uses positive level clock.
+            CLKEN            => CLKBUS(CKENCPU),                         -- Pulse the master clock at the required CPU frequency.
+            WAIT_n           => T80_WAIT_n,                              -- WAIT_n signal into the CPU to prolong a memory cycle.
+            INT_n            => T80_INT_n,                               -- INT_n signal for maskable interrupts.
+            NMI_n            => T80_NMI_n,                               -- NMI_n non maskable interrupt input.
+            BUSRQ_n          => T80_BUSRQ_n,                             -- BUSRQ_n signal to request CPU go into tristate and relinquish bus.
+            M1_n             => T80_M1_n,                                -- M1_n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
+            MREQ_n           => T80_MREQ_n,                              -- MREQ_n signal indicates that the address bus holds a valid address for reading or writing memory.
+            IORQ_n           => T80_IORQ_n,                              -- IORQ_n signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
+            RD_n             => T80_RD_n,                                -- RD_n signal indicates that data is ready to be read from a memory or I/O device to the CPU.
+            WR_n             => T80_WR_n,                                -- WR_n signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
+            RFSH_n           => T80_RFSH_n,                              -- RFSH_n signal to indicate dynamic memory refresh can take place.
+            HALT_n           => T80_HALT_n,                              -- HALT_n signal indicates that the CPU has executed a "HALT" instruction.
+            BUSAK_n          => T80_BUSAK_n,                             -- BUSAK_n signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
+            A                => T80_A16,                                 -- 16 bit address lines.
+            DI               => T80_DI,                                  -- 8 bit data input bus.
+            DO               => T80_DO                                   -- 8 bit data output bus.
+        );
+
+    -- MZ80 System RAM
+    -- 
+    SYSRAM : dpram
+        generic map (
+            init_file        => "./software/mif/combined_mainmemory.mif",
+            widthad_a        => 16,
+            width_a          => 8,
+            widthad_b        => 16,
+            width_b          => 8,
+            outdata_reg_a    => "UNREGISTERED",
+            outdata_reg_b    => "UNREGISTERED"
+        )
+        port map (
+            clock_a          => CLKBUS(CKMASTER), --CLKBUS(CKMEM), 
+            clocken_a        => CLKBUS(CKENCPU), --'1',
+            address_a        => MZ_SYSMEM_A16,
+            data_a           => T80_DO,
+            wren_a           => WENSYSRAM,                               -- Pulse width controlled according to Master Clock.
+            q_a              => SYSRAM_DO,
+
+            clock_b          => MZ_IOCTL_CLK,
+            clocken_b        => '1',
+            address_b        => MZ_IOCTL_ADDR(15 downto 0),
+            data_b           => MZ_IOCTL_DOUT(7 downto 0),
+            wren_b           => MZ_IOCTL_WENRAM,
+            q_b              => MZ_IOCTL_DIN_SYSRAM
+        );
+
+    -- MZ Monitor ROM
+    -- 0  =         80K MROM 4KBytes -> 0000:0fff 0000 bytes padding
+    -- 1  =  80x25  80K MROM 4KBytes -> 1000:1fff 0000 bytes padding
+    -- 2  =         80C MROM 4KBytes -> 2000:2fff 0000 bytes padding
+    -- 3  =  80x25  80C MROM 4KBytes -> 3000:3fff 0000 bytes padding
+    -- 4  =        1200 MROM 4KBytes -> 4000:4fff 0000 bytes padding
+    -- 5  =  80x25 1200 MROM 4KBytes -> 5000:5fff 0000 bytes padding
+    -- 6  =         80A MROM 4KBytes -> 6000:6fff 0000 bytes padding
+    -- 7  =  80x25  80A MROM 4KBytes -> 7000:7fff 0000 bytes padding
+    -- 8  =         700 MROM 4KBytes -> 8000:8fff 0000 bytes padding
+    -- 9  =  80x25  700 MROM 4KBytes -> 9000:9fff 0000 bytes padding
+    -- 10 =         80B MROM 2KBytes -> a000:afff 0800 bytes padding
+    -- 11 =  80x25  80B MROM 2KBytes -> b000:bfff 0800 bytes padding
+    -- 
+    --SYSROM : dprom
+    SYSROM : dpram
+        generic map (
+            init_file        => "./software/mif/combined_mrom.mif",
+            widthad_a        => 17,
+            width_a          => 8,
+            widthad_b        => 17,
+            width_b          => 8,
+            outdata_reg_a    => "UNREGISTERED",
+            outdata_reg_b    => "UNREGISTERED"
+        )
+        port map (
+            clock_a          => CLKBUS(CKMASTER), -- CLKBUS(CKMEM),
+            clocken_a        => CLKBUS(CKENCPU), --'1',
+            address_a        => MROM_BANK & T80_A16(10 downto 0),
+            data_a           => T80_DO,
+            wren_a           => '0',                                     -- Block writes from Z80 to ROM.
+            q_a              => SYSROM_DO,
+
+            clock_b          => MZ_IOCTL_CLK,
+            clocken_b        => '1',
+            address_b        => MZ_IOCTL_ADDR(16 downto 0),
+            data_b           => MZ_IOCTL_DOUT(7 downto 0),
+            wren_b           => MZ_IOCTL_WENROM,
+            q_b              => MZ_IOCTL_DIN_SYSROM
+        );
+
+    CTRL0 : mctrl
+        port map (
+            -- Clock
+            CLKBUS           => CLKBUS,
+
+            -- Reset's
+            COLD_RESET       => cold_reset,
+            WARM_RESET       => warm_reset,
+            SYSTEM_RESET     => MZ_SYSTEM_RESET,
+
+            -- HPS Interface
+            IOCTL_CLK        => MZ_IOCTL_CLK,                            -- HPS I/O Clock
+            IOCTL_WR         => MZ_IOCTL_WR,
+            IOCTL_RD         => MZ_IOCTL_RD,
+            IOCTL_ADDR       => MZ_IOCTL_ADDR,
+            IOCTL_DOUT       => MZ_IOCTL_DOUT,
+            IOCTL_DIN        => MZ_IOCTL_DIN_MCTRL,
+
+            -- Different operations modes.
+            CONFIG           => CONFIG,
+
+            -- Cassette magnetic tape signals.
+            CMT_BUS_OUT      => MZ_CMT_BUS_OUT,
+            CMT_BUS_IN       => MZ_CMT_BUS_IN,
+
+            -- MZ80B series can dynamically change the video frequency to attain 40/80 character display.
+            CONFIG_CHAR80    => MZ_DISPLAY_CHAR80,
+
+            -- Debug modes.
+            DEBUG            => DEBUG
+        );
+
+    VIDEO0 : video
+        port map (
+            RST_n            => T80_RST_n,                               -- Reset
+
+            -- Different operations modes.
+            CONFIG           => CONFIG,
+
+            -- Clocks
+            CLKBUS           => CLKBUS,                                  -- Clock signals created by clkgen module.
+
+            -- CPU Signals
+            T80_A            => T80_A16(13 downto 0),                    -- CPU Address Bus
+            T80_RD_n         => T80_RD_n,                                -- CPU Read Signal
+            T80_WR_n         => T80_WR_n,                                -- CPU Write Signal
+            T80_MREQ_n       => T80_MREQ_n,                              -- CPU Memory Request
+            T80_BUSACK_n     => T80_BUSAK_n,                             -- CPU Bus Acknowledge
+            T80_WAIT_n       => VIDEO_WAIT_n,                            -- Wait Request to CPU from Video circuitry.
+            T80_DI           => T80_DO,                                  -- CPU Data Bus(in)
+            T80_DO           => VRAM_DO,                                 -- CPU Data Bus(out)
+
+            -- Selects.
+            CS_VRAM_n        => MZ_CS_VRAM_n,                            -- VRAM Select
+            CS_MEM_G_n       => MZ_CS_MEM_G_n,                           -- Peripherals Select
+            CS_GRAM_n        => MZ_CS_GRAM_n,                            -- Colour GRAM Select
+            CS_GRAM_80B_n    => MZ_CS_GRAM_80B_n,                        -- MZ80B GRAM Select
+            CS_IO_GFB_n      => MZ_CS_IO_GFB_n,                          -- Graphics FB IO Select range
+            CS_IO_G_n        => MZ_CS_IO_G_n,                            -- Graphics Options IO Select range
+
+            -- Video Signals
+            VGATE_n          => MZ_VGATE_n,                              -- Video Output Control
+            INVERSE_n        => MZ_DISPLAY_INVERT_n,                     -- Invert video output.
+            CONFIG_CHAR80    => MZ_DISPLAY_CHAR80,                       -- 40 Char = 0, 80 Char = 1 select.
+            HBLANK           => MZ_HBLANK,                               -- Horizontal Blanking
+            VBLANK           => MZ_VBLANK,                               -- Vertical Blanking
+            HSYNC_n          => MZ_HSYNC_n,                              -- Horizontal Sync
+            VSYNC_n          => MZ_VSYNC_n,                              -- Vertical Sync
+            ROUT             => MZ_R,                                    -- Red Output
+            GOUT             => MZ_G,                                    -- Green Output
+            BOUT             => MZ_B,                                    -- Blue Output
+
+            -- HPS Interface
+            IOCTL_DOWNLOAD   => MZ_IOCTL_DOWNLOAD,
+            IOCTL_UPLOAD     => MZ_IOCTL_UPLOAD,
+            IOCTL_CLK        => MZ_IOCTL_CLK,                            -- HPS I/O Clock.
+            IOCTL_WR         => MZ_IOCTL_WR,                             -- HPS Write Enable to FPGA.
+            IOCTL_RD         => MZ_IOCTL_RD,                             -- HPS Read Enable to FPGA.
+            IOCTL_ADDR       => MZ_IOCTL_ADDR,                           -- HPS Address in FPGA to write into.
+            IOCTL_DOUT       => MZ_IOCTL_DOUT,                           -- HPS Data to be written into FPGA.
+            IOCTL_DIN        => MZ_IOCTL_DIN_VIDEO                       -- HPS Data to be sent to HPS.
+        );
+
+    TAPE0 : cmt
+        port map (
+            RST              => MZ_SYSTEM_RESET,
+
+            -- Clock signals needed by this module.
+            CLKBUS           => CLKBUS,
+
+            -- Different operations modes.
+            CONFIG           => CONFIG,
+
+            -- Cassette magnetic tape signals.
+            CMT_BUS_OUT      => MZ_CMT_BUS_OUT,                          -- Output is fed from CMT into MCTRL and MZ..
+            CMT_BUS_IN       => MZ_CMT_BUS_IN,                           -- Input is fed from MCTRL/MZ into CMT.
+
+            -- HPS Interface
+            IOCTL_DOWNLOAD   => MZ_IOCTL_DOWNLOAD,                       -- HPS Downloading to FPGA.
+            IOCTL_UPLOAD     => MZ_IOCTL_UPLOAD,                         -- HPS Uploading from FPGA.
+            IOCTL_CLK        => MZ_IOCTL_CLK,                            -- HPS I/O Clock.
+            IOCTL_WR         => MZ_IOCTL_WR,                             -- HPS Write Enable to FPGA.
+            IOCTL_RD         => MZ_IOCTL_RD,                             -- HPS Read Enable from FPGA.
+            IOCTL_ADDR       => MZ_IOCTL_ADDR,                           -- HPS Address in FPGA to write into.
+            IOCTL_DOUT       => MZ_IOCTL_DOUT,                           -- HPS Data to be written into FPGA.
+            IOCTL_DIN        => MZ_IOCTL_DIN_CMT,                        -- HPS Data to be sent to HPS.
+
+            -- Debug Status Leds
+            DEBUG_STATUS_LEDS=> MZ_CMT_DEBUG_LEDS(31 downto 0)           -- 24 leds to display cmt internal status.
+        );
+
+    KEYS : keymatrix
+        port map (
+            RST_n            => T80_RST_n,
+
+            -- i8255
+            PA               => MZ_KEYB_SCAN,
+            PB               => MZ_KEYB_DATA,
+            STALL            => MZ_KEYB_STALL,
+            BREAKDETECT      => MZ_KEYB_BREAKDETECT,
+
+            -- PS/2 Keyboard Data
+            PS2_KEY          => MZ_PS2_KEY,                              -- PS2 Key data.
+
+            -- Different operations modes.
+            CONFIG           => CONFIG,
+
+            -- Clock signals created by this module.
+            CLKBUS           => CLKBUS,
+
+            -- HPS Interface
+            IOCTL_DOWNLOAD   => MZ_IOCTL_DOWNLOAD,                       -- HPS Downloading to FPGA.
+            IOCTL_UPLOAD     => MZ_IOCTL_UPLOAD,                         -- HPS Uploading from FPGA.
+            IOCTL_CLK        => MZ_IOCTL_CLK,                            -- HPS I/O Clock.
+            IOCTL_WR         => MZ_IOCTL_WR,                             -- HPS Write Enable to FPGA.
+            IOCTL_RD         => MZ_IOCTL_RD,                             -- HPS Read Enable from FPGA.
+            IOCTL_ADDR       => MZ_IOCTL_ADDR,                           -- HPS Address in FPGA to write into.
+            IOCTL_DOUT       => MZ_IOCTL_DOUT,                           -- HPS Data to be written into FPGA.
+            IOCTL_DIN        => MZ_IOCTL_DIN_KEY                         -- HPS Data to be sent to HPS.
+        );
+
+    MZ80HW : mz80c
+        port map (
+            -- Clocks
+            CLKBUS           => CLKBUS,                                  -- Clock signals created by this module.
+
+            -- Resets.
+            COLD_RESET       => cold_reset,                              -- Cold reset, one time reset on power up.
+            SYSTEM_RESET     => MZ_SYSTEM_RESET,                         -- Reset generated by system based on Cold/Warm or trigger.
+
+            -- Z80 CPU
+            T80_RST_n        => T80_RST_n,
+            T80_WAIT_n       => MZ80C_WAIT_n,
+            T80_INT_n        => MZ80C_INT_n,
+            T80_NMI_n        => MZ80C_NMI_n,
+            T80_BUSRQ_n      => MZ80C_BUSRQ_n,
+            T80_M1_n         => T80_M1_n,
+            T80_MREQ_n       => T80_MREQ_n,
+            T80_IORQ_n       => T80_IORQ_n,
+            T80_RD_n         => T80_RD_n,
+            T80_WR_n         => T80_WR_n,
+            T80_RFSH_n       => T80_RFSH_n,                              --RFSH_n
+            T80_HALT_n       => T80_HALT_n,
+            T80_BUSAK_n      => T80_BUSAK_n,
+            T80_A16          => T80_A16,
+            T80_DI           => MZ80C_DI,
+            T80_DO           => T80_DO,
+
+            -- Chip selects to common resources.
+            CS_ROM_n         => MZ80C_CS_ROM_n,
+            CS_RAM_n         => MZ80C_CS_RAM_n,
+            CS_VRAM_n        => MZ80C_CS_VRAM_n,                         -- VRAM Select
+            CS_MEM_G_n       => MZ80C_CS_MEM_G_n,                        -- Memory mapped Peripherals Select
+            CS_GRAM_n        => MZ80C_CS_GRAM_n,                         -- Colour GRAM Select
+            CS_IO_GFB_n      => MZ80C_CS_IO_GFB_n,                       -- Graphics FB IO Select range
+
+            -- Audio.
+            AUDIO_L          => MZ80C_AUDIO_L,
+            AUDIO_R          => MZ80C_AUDIO_R,
+
+            -- Different operations modes.
+            CONFIG           => CONFIG,
+
+            -- Keyboard.
+            KEYB_SCAN        => MZ80C_KEYB_SCAN,                         -- Keyboard scan lines out.
+            KEYB_DATA        => MZ_KEYB_DATA,                            -- Keyboard scan data in.
+            KEYB_STALL       => MZ80C_KEYB_STALL,                        -- Keyboard Stall out.
+
+            -- CMT status signals.
+            CMT_BUS_OUT      => MZ_CMT_BUS_OUT,
+            CMT_BUS_IN       => MZ80C_CMT_BUS_IN,
+
+            -- Video signals.
+            VGATE_n          => MZ80C_VGATE_n,
+            HBLANK           => MZ_HBLANK,
+            VBLANK           => MZ_VBLANK,
+
+            -- HPS Interface
+            IOCTL_DOWNLOAD   => MZ_IOCTL_DOWNLOAD,                    
+            IOCTL_UPLOAD     => MZ_IOCTL_UPLOAD,                    
+            IOCTL_CLK        => MZ_IOCTL_CLK,                            -- HPS I/O Clock
+            IOCTL_WR         => MZ_IOCTL_WR,
+            IOCTL_RD         => MZ_IOCTL_RD,
+            IOCTL_ADDR       => MZ_IOCTL_ADDR,
+            IOCTL_DOUT       => MZ_IOCTL_DOUT,
+            IOCTL_DIN        => MZ_IOCTL_DIN_MZ80C,
+
+            -- Debug Status Leds
+            DEBUG_STATUS_LEDS=> MZ80C_DEBUG_LEDS
+    );
+
+    MZ80BHW : mz80b
+        port map (
+            -- Clocks
+            CLKBUS           => CLKBUS,                                  -- Clock signals created by this module.
+
+            -- Resets.
+            COLD_RESET       => cold_reset,                              -- Cold reset, one time reset on power up.
+            SYSTEM_RESET     => MZ_SYSTEM_RESET,                         -- Reset generated by system based on Cold/Warm or trigger.
+
+            -- Z80 CPU
+            T80_RST_n        => T80_RST_n,
+            T80_WAIT_n       => MZ80B_WAIT_n,
+            T80_INT_n        => MZ80B_INT_n,
+            T80_NMI_n        => MZ80B_NMI_n,
+            T80_BUSRQ_n      => MZ80B_BUSRQ_n,
+            T80_M1_n         => T80_M1_n,
+            T80_MREQ_n       => T80_MREQ_n,
+            T80_IORQ_n       => T80_IORQ_n,
+            T80_RD_n         => T80_RD_n,
+            T80_WR_n         => T80_WR_n,
+            T80_RFSH_n       => T80_RFSH_n,                              --RFSH_n
+            T80_HALT_n       => T80_HALT_n,
+            T80_BUSAK_n      => T80_BUSAK_n,
+            T80_A16          => T80_A16,
+            T80_DI           => MZ80B_DI,
+            T80_DO           => T80_DO,
+
+            -- Chip selects to common resources.
+            CS_ROM_n         => MZ80B_CS_ROM_n,
+            CS_RAM_n         => MZ80B_CS_RAM_n,
+            CS_VRAM_n        => MZ80B_CS_VRAM_n,                         -- VRAM Select
+            CS_GRAM_n        => MZ80B_CS_GRAM_n,                         -- Colour GRAM Select
+            CS_GRAM_80B_n    => MZ_CS_GRAM_80B_n,                        -- MZ80B GRAM Select
+            CS_IO_GFB_n      => MZ80B_CS_IO_GFB_n,                       -- Graphics FB IO Select range
+            CS_IO_G_n        => MZ80B_CS_IO_G_n,                         -- Graphics Options IO Select range
+            CS_SWP_MEMBANK_n => MZ_SWP_MEM_BANK_n,                       -- Swap lower 32K memory bank into upper 32k block.
+
+            -- Audio.
+            AUDIO_L          => MZ80B_AUDIO_L,
+            AUDIO_R          => MZ80B_AUDIO_R,
+
+            -- Different operations modes.
+            CONFIG           => CONFIG,
+
+            -- Keyboard.
+            KEYB_SCAN        => MZ80B_KEYB_SCAN,                         -- Keyboard scan lines out.
+            KEYB_DATA        => MZ_KEYB_DATA,                            -- Keyboard scan data in.
+            KEYB_STALL       => MZ80B_KEYB_STALL,                        -- Keyboard Stall out.
+            KEYB_BREAKDETECT => MZ_KEYB_BREAKDETECT,                     -- Keyboard detects a break.
+
+            -- CMT status signals.
+            CMT_BUS_OUT      => MZ_CMT_BUS_OUT,
+            CMT_BUS_IN       => MZ80B_CMT_BUS_IN,
+
+            -- Video signals.
+            VGATE_n          => MZ80B_VGATE_n,
+            INVERSE_n        => MZ_DISPLAY_INVERT_n,                     -- Invert video output.
+            CONFIG_CHAR80    => MZ_DISPLAY_CHAR80,                       -- 40 Char = 0, 80 Char = 1 select.
+            HBLANK           => MZ_HBLANK,
+            VBLANK           => MZ_VBLANK,
+
+            -- HPS Interface
+            IOCTL_DOWNLOAD   => MZ_IOCTL_DOWNLOAD,                    
+            IOCTL_UPLOAD     => MZ_IOCTL_UPLOAD,                    
+            IOCTL_CLK        => MZ_IOCTL_CLK,                            -- HPS I/O Clock
+            IOCTL_WR         => MZ_IOCTL_WR,
+            IOCTL_RD         => MZ_IOCTL_RD,
+            IOCTL_ADDR       => MZ_IOCTL_ADDR,
+            IOCTL_DOUT       => MZ_IOCTL_DOUT,
+            IOCTL_DIN        => MZ_IOCTL_DIN_MZ80B,
+
+            -- Debug Status Leds
+            DEBUG_STATUS_LEDS=> MZ80B_DEBUG_LEDS
+    );
+
+    -- Clocks.
+    --
+    CLKSYS                   <= CLKBUS(CKMASTER);                       -- HPS clock.
+    CLKVID                   <= CLKBUS(CKVIDEO);                        -- Video pixel clock output.
+    CLKIOP                   <= CLKBUS(CKIOP);                          -- IO Processor Clock.
+
+    -- Multiplexer -> Signals to enabled hardware.
+    --
+    T80_WAIT_n               <= VIDEO_WAIT_n      when VIDEO_WAIT_n = '0'     else MZ80C_WAIT_n      when CONFIG(MZ_80C) = '1'   else MZ80B_WAIT_n;
+    T80_INT_n                <= MZ80C_INT_n       when CONFIG(MZ_80C) = '1'   else MZ80B_INT_n;
+    T80_NMI_n                <= MZ80C_NMI_n       when CONFIG(MZ_80C) = '1'   else MZ80B_NMI_n;
+    T80_BUSRQ_n              <= MZ80C_BUSRQ_n     when CONFIG(MZ_80C) = '1'   else MZ80B_BUSRQ_n;
+    T80_DI                   <= SYSRAM_DO         when MZ_CS_RAM_n ='0' and T80_RD_n = '0'                    -- Read from System RAM
+                                else 
+                                SYSROM_DO         when MZ_CS_ROM_n ='0' and T80_RD_n = '0'                    -- Read from System ROM        
+                                else 
+                                VRAM_DO           when (MZ_CS_VRAM_n ='0' or MZ_CS_GRAM_n = '0' or MZ_CS_GRAM_80B_n = '0') and T80_RD_n = '0' -- Read from Graphics/Video RAM.
+                                else 
+                                MZ80C_DI          when CONFIG(MZ_80C) = '1'  
+                                else
+                                MZ80B_DI          when CONFIG(MZ_80B) = '1'
+                                else
+                                (others=>'1');                                                                -- Float the bus as high when not driven.
+    MZ_SYSMEM_A16            <= T80_A16           when CONFIG(MZ_80C) = '1'   else T80_A16           when CONFIG(MZ_80B) = '1' and MZ_SWP_MEM_BANK_n = '1' else '0' & T80_A16(14 downto 0);
+    MZ_CS_ROM_n              <= MZ80C_CS_ROM_n    when CONFIG(MZ_80C) = '1'   else MZ80B_CS_ROM_n;
+    MZ_CS_RAM_n              <= MZ80C_CS_RAM_n    when CONFIG(MZ_80C) = '1'   else MZ80B_CS_RAM_n;
+    MZ_CS_VRAM_n             <= MZ80C_CS_VRAM_n   when CONFIG(MZ_80C) = '1'   else MZ80B_CS_VRAM_n;
+    MZ_CS_MEM_G_n            <= MZ80C_CS_MEM_G_n  when CONFIG(MZ_80C) = '1'   else '1';
+    MZ_CS_GRAM_n             <= MZ80C_CS_GRAM_n   when CONFIG(MZ_80C) = '1'   else MZ80B_CS_GRAM_n;
+    MZ_CS_IO_GFB_n           <= MZ80C_CS_IO_GFB_n when CONFIG(MZ_80C) = '1'   else MZ80B_CS_IO_GFB_n;
+    MZ_CS_IO_G_n             <= '1'               when CONFIG(MZ_80C) = '1'   else MZ80B_CS_IO_G_n;
+    audio_l_o                <= MZ80C_AUDIO_L     when CONFIG(MZ_80C) = '1'   else MZ80B_AUDIO_L;
+    audio_r_o                <= MZ80C_AUDIO_R     when CONFIG(MZ_80C) = '1'   else MZ80B_AUDIO_R;
+    MZ_VGATE_n               <= MZ80C_VGATE_n     when CONFIG(MZ_80C) = '1'   else MZ80B_VGATE_n;
+    MZ_CMT_BUS_IN            <= MZ80C_CMT_BUS_IN  when CONFIG(MZ_80C) = '1'   else MZ80B_CMT_BUS_IN;
+
+    MZ_KEYB_SCAN             <= MZ80C_KEYB_SCAN   when CONFIG(MZ_80C) = '1'   else MZ80B_KEYB_SCAN;
+    MZ_KEYB_STALL            <= MZ80C_KEYB_STALL  when CONFIG(MZ_80C) = '1'   else MZ80B_KEYB_STALL;
+
+    -- VGA output in original format or upscaled.
+    --
+    VGA_HS_O                 <= not MZ_HSYNC_n;
+    VGA_VS_O                 <= not MZ_VSYNC_n;
+    VGA_R_O                  <= MZ_R;
+    VGA_G_O                  <= MZ_G;
+    VGA_B_O                  <= MZ_B;
+    VGA_VB_O                 <= MZ_VBLANK;
+    VGA_HB_O                 <= MZ_HBLANK;
+
+    -- Parent signals onto local wires.
+    --
+    MZ_PS2_KEY               <= ps2_key;
+    MZ_IOCTL_DOWNLOAD        <= ioctl_download;
+    MZ_IOCTL_UPLOAD          <= ioctl_upload;
+    MZ_IOCTL_CLK             <= ioctl_clk;
+    MZ_IOCTL_WR              <= ioctl_wr;
+    MZ_IOCTL_RD              <= ioctl_rd;
+    MZ_IOCTL_ADDR            <= ioctl_addr;
+    MZ_IOCTL_DOUT            <= ioctl_dout;
+    IOCTL_DIN                <= X"000000" & MZ_IOCTL_DIN_SYSROM when MZ_IOCTL_RENROM = '1'                               -- System ROM
+                                else
+                                X"000000" & MZ_IOCTL_DIN_SYSRAM when MZ_IOCTL_RENRAM = '1'                               -- System RAM
+                                else
+                                MZ_IOCTL_DIN_VIDEO          when IOCTL_ADDR(24 downto 20) = "00011"                  -- Video RAM
+                                else
+                                MZ_IOCTL_DIN_VIDEO          when IOCTL_ADDR(24 downto 20) = "00110"                  -- PCG
+                                else
+                                MZ_IOCTL_DIN_VIDEO          when IOCTL_ADDR(24 downto 20) = "00101"                  -- CGROM
+                                else
+                                MZ_IOCTL_DIN_MCTRL          when IOCTL_ADDR(24)           = '1'                      -- MCTRL Registers
+                                else
+                                MZ_IOCTL_DIN_CMT            when IOCTL_ADDR(24 downto 20) = "00100"                  -- CMT
+                                else                               
+                                MZ_IOCTL_DIN_KEY            when IOCTL_ADDR(24 downto 20) = "00010"                  -- Key Matrix
+                                else
+                                MZ_IOCTL_DIN_MZ80C          when CONFIG(MZ_80C) = '1'                                -- MZ80C memory.
+                                else
+                                MZ_IOCTL_DIN_MZ80B          when CONFIG(MZ_80B) = '1'                                -- MZ80B memory.
+                                else
+                                (others=>'0');
+
+    --
+    -- Control Signals
+    --
+    T80_RST_n                <= not MZ_SYSTEM_RESET;
+    --
+    MZ_MEMWR                 <= not T80_WR_n;
+    WENSYSRAM                <= MZ_MEMWR when MZ_CS_RAM_n = '0'                                          -- Write enable to System RAM
+                                else '0';
+    MZ_IOCTL_WENROM          <= '1'   when MZ_IOCTL_ADDR(24 downto 20) = "00000" and MZ_IOCTL_WR = '1'   -- Write enable from HPS to ROM.
+                                else '0';
+    MZ_IOCTL_WENRAM          <= '1'   when MZ_IOCTL_ADDR(24 downto 20) = "00001" and MZ_IOCTL_WR = '1'   -- Write enable from HPS to RAM.
+                                else '0';
+    MZ_IOCTL_RENROM          <= '1'   when MZ_IOCTL_ADDR(24 downto 20) = "00000" and MZ_IOCTL_RD = '1'   -- Read enable from ROM to HPS.
+                                else '0';
+    MZ_IOCTL_RENRAM          <= '1'   when MZ_IOCTL_ADDR(24 downto 20) = "00001" and MZ_IOCTL_RD = '1'   -- Read enable from RAM to HPS.
+                                else '0';
+
+    -- System ROM. 128K split up into chunks which are enabled according to the running machine. The ROM can be accessed by the
+    -- HPS via the IOCTL bus and updated as necessary.
+    --
+    --                                         16    15   14   13   12   11            16     15   14   13   12   11
+    -- K   4096    0         4095    0000000    0    0    0    0    0    0    0000FFF    0    0    0    0    0    1
+    --     4096    4096      8191    0001000    0    0    0    0    1    0    0001FFF    0    0    0    0    1    1
+    --     2048    8192     10239    0002000    0    0    0    1    0    0    00027FF    0    0    0    1    0    0
+    --     2048    10240    12287    0002800    0    0    0    1    0    1    0002FFF    0    0    0    1    0    1
+    --     2048    12288    14335    0003000    0    0    0    1    1    0    00037FF    0    0    0    1    1    0
+    -- C   4096    14336    18431    0003800    0    0    0    1    1    1    00047FF    0    0    1    0    0    0
+    --     4096    18432    22527    0004800    0    0    1    0    0    1    00057FF    0    0    1    0    1    0
+    --     2048    22528    22527    0005800    0    0    1    0    1    1    0005FFF    0    0    1    0    1    1
+    --     2048    22528    24575    0006000    0    0    1    1    0    0    00067FF    0    0    1    1    0    0
+    --     2048    24576    26623    0006800    0    0    1    1    0    1    0006FFF    0    0    1    1    0    1
+    -- 12  4096    18432    22527    0007000    0    0    1    1    1    0    0007FFF    0    0    1    1    1    1
+    --     4096    22528    26623    0008000    0    1    0    0    0    0    0008FFF    0    1    0    0    0    1
+    --     2048    26624    28671    0009000    0    1    0    0    1    0    00097FF    0    1    0    0    1    0
+    --     2048    28672    30719    0009800    0    1    0    0    1    1    0009FFF    0    1    0    0    1    1
+    --     2048    30720    32767    000A000    0    1    0    1    0    0    000A7FF    0    1    0    1    0    0
+    -- A   4096    22528    26623    000A800    0    1    0    1    0    1    000B7FF    0    1    0    1    1    0
+    --     4096    26624    30719    000B800    0    1    0    1    1    1    000C7FF    0    1    1    0    0    0
+    --     2048    30720    32767    000C800    0    1    1    0    0    1    000CFFF    0    1    1    0    0    1
+    --     2048    32768    34815    000D000    0    1    1    0    1    0    000D7FF    0    1    1    0    1    0
+    --     2048    34816    36863    000D800    0    1    1    0    1    1    000DFFF    0    1    1    0    1    1
+    -- 7   4096    26624    30719    000E000    0    1    1    1    0    0    000EFFF    0    1    1    1    0    1
+    --     4096    30720    34815    000F000    0    1    1    1    1    0    000FFFF    0    1    1    1    1    1
+    --     2048    34816    36863    0010000    1    0    0    0    0    0    00107FF    1    0    0    0    0    0
+    --     2048    36864    38911    0010800    1    0    0    0    0    1    0010FFF    1    0    0    0    0    1
+    --     2048    38912    40959    0011000    1    0    0    0    1    0    00117FF    1    0    0    0    1    0
+    -- 8   4096    30720    34815    0011800    1    0    0    0    1    1    00127FF    1    0    0    1    0    0
+    --     4096    34816    38911    0012800    1    0    0    1    0    1    00137FF    1    0    0    1    1    0
+    --     2048    38912    40959    0013800    1    0    0    1    1    1    0013FFF    1    0    0    1    1    1
+    --     2048    40960    43007    0014000    1    0    1    0    0    0    00147FF    1    0    1    0    0    0
+    --     2048    43008    45055    0014800    1    0    1    0    0    1    0014FFF    1    0    1    0    0    1
+    -- B   2048    34816    36863    0015000    1    0    1    0    1    0    00157FF    1    0    1    0    1    0
+    --     2048    36864    38911    0015800    1    0    1    0    1    1    0015FFF    1    0    1    0    1    1
+    --     2048    38912    40959    0016000    1    0    1    1    0    0    00167FF    1    0    1    1    0    0
+    --     2048    40960    43007    0016800    1    0    1    1    0    1    0016FFF    1    0    1    1    0    1
+    --     2048    43008    45055    0017000    1    0    1    1    1    0    00177FF    1    0    1    1    1    0
+    -- 20  2048    36864    38911    0017800    1    0    1    1    1    1    0017FFF    1    0    1    1    1    1
+    --     2048    38912    40959    0018000    1    1    0    0    0    0    00187FF    1    1    0    0    0    0
+    --     2048    40960    43007    0018800    1    1    0    0    0    1    0018FFF    1    1    0    0    0    1
+    --     2048    43008    45055    0019000    1    1    0    0    1    0    00197FF    1    1    0    0    1    0
+    --     2048    45056    47103    0019800    1    1    0    0    1    1    0019FFF    1    1    0    0    1    1
+    --
+    MROM_BANK                <= "00000" & T80_A16(11)     when CONFIG(MZ80K)                 = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "00001" & T80_A16(11)     when CONFIG(MZ80K)                 = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "000100"                  when CONFIG(MZ80K)                 = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "000101"                  when CONFIG(MZ80K)                 = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "000110"                  when CONFIG(MZ80K)                 = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                "000111"                  when CONFIG(pkgs.mctrl_pkg.MZ80C)  = '1' and T80_A16(11) = '0'                 and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "001000"                  when CONFIG(pkgs.mctrl_pkg.MZ80C)  = '1' and T80_A16(11) = '1'                 and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "001001"                  when CONFIG(pkgs.mctrl_pkg.MZ80C)  = '1' and T80_A16(11) = '0'                 and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "001010"                  when CONFIG(pkgs.mctrl_pkg.MZ80C)  = '1' and T80_A16(11) = '1'                 and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "001011"                  when CONFIG(pkgs.mctrl_pkg.MZ80C)  = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "001100"                  when CONFIG(pkgs.mctrl_pkg.MZ80C)  = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "001101"                  when CONFIG(pkgs.mctrl_pkg.MZ80C)  = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                "00111" & T80_A16(11)     when CONFIG(MZ1200)                = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "01000" & T80_A16(11)     when CONFIG(MZ1200)                = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "010010"                  when CONFIG(MZ1200)                = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "010011"                  when CONFIG(MZ1200)                = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "010100"                  when CONFIG(MZ1200)                = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                "010101"                  when CONFIG(MZ80A)                 = '1' and T80_A16(11) = '0'                 and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "010110"                  when CONFIG(MZ80A)                 = '1' and T80_A16(11) = '1'                 and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "010111"                  when CONFIG(MZ80A)                 = '1' and T80_A16(11) = '0'                 and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "011000"                  when CONFIG(MZ80A)                 = '1' and T80_A16(11) = '1'                 and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "011001"                  when CONFIG(MZ80A)                 = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "011010"                  when CONFIG(MZ80A)                 = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "011011"                  when CONFIG(MZ80A)                 = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                "01110" & T80_A16(11)     when CONFIG(MZ700)                 = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "01111" & T80_A16(11)     when CONFIG(MZ700)                 = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "100000"                  when CONFIG(MZ700)                 = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "100001"                  when CONFIG(MZ700)                 = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "100010"                  when CONFIG(MZ700)                 = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                "100011"                  when CONFIG(MZ800)                 = '1' and T80_A16(11) = '0'                 and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "100100"                  when CONFIG(MZ800)                 = '1' and T80_A16(11) = '1'                 and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "100101"                  when CONFIG(MZ800)                 = '1' and T80_A16(11) = '0'                 and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "100110"                  when CONFIG(MZ800)                 = '1' and T80_A16(11) = '1'                 and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "100111"                  when CONFIG(MZ800)                 = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "101000"                  when CONFIG(MZ800)                 = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "101001"                  when CONFIG(MZ800)                 = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                -- MZ80/2000 Series have different rom requirements.
+                                "101010"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "101011"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "101100"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "101101"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "101110"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                "101111"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0')
+                                else
+                                "110000"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1')
+                                else
+                                "110001"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and T80_A16(15 downto 11) = "11101"
+                                else
+                                "110010"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and T80_A16(15 downto 11) = "11110"
+                                else
+                                "110011"                  when CONFIG(pkgs.mctrl_pkg.MZ80B)  = '1' and T80_A16(15 downto 11) = "11111"
+                                else
+                                "000000"; -- Default to K ROM.
+
+    -- Debug: Every 5 seconds, change the mb led bank to show a set of values (0 -> 7), bank indicated by 1 second of a bank number.
+    --
+    DEBUG0: if DEBUG_ENABLE = 1 generate
+        process( MZ_SYSTEM_RESET, CLKBUS(CKMASTER), DEBUG) begin
+            if MZ_SYSTEM_RESET = '1'  then
+                debug_counter <= 0;
+                flip_counter  <= 0;
+    
+            elsif rising_edge(CLKBUS(CKMASTER)) then
+
+                if CLKBUS(CKENLEDS) = '1' then
+        
+                    -- If debug mode is enabled, enable use of sequencer.
+                    --
+                    if DEBUG(ENABLED) = '1' then
+        
+                        -- If LEDS are switched on, run the sample sequencer.
+                        --
+                        if DEBUG(LEDS_ON) = '1' then
+            
+                            -- The changing of the values displayed depends on the sample frequency as this drives the process.
+                            case DEBUG(SMPFREQ) is
+                                when "0000" =>  -- CMT/CPU frequency - default to 1s/5s @ 2MHz.
+                                    block_flip <= 250000;
+                                    bank_flip  <= 10000000;
+                                when "0001" =>  -- 1MHz
+                                    block_flip <= 800000;
+                                    bank_flip  <= 5000000;
+                                when "0010" =>  -- 100KHz
+                                    block_flip <= 80000;
+                                    bank_flip  <= 500000;
+                                when "0011" =>  -- 10KHz
+                                    block_flip <= 8000;
+                                    bank_flip  <= 50000;
+                                when "0100" =>  -- 5KHz
+                                    block_flip <= 4000;
+                                    bank_flip  <= 25000;
+                                when "0101" =>  -- 1KHz
+                                    block_flip <= 800;
+                                    bank_flip  <= 5000;
+                                when "0110" =>  -- 500Hz
+                                    block_flip <= 400;
+                                    bank_flip  <= 2500;
+                                when "0111" =>  -- 100Hz
+                                    block_flip <= 80;
+                                    bank_flip  <= 500;
+                                when "1000" =>  -- 50Hz
+                                    block_flip <= 40;
+                                    bank_flip  <= 250;
+                                when "1001" =>  -- 10Hz
+                                    block_flip <= 8;
+                                    bank_flip  <= 50;
+                                when "1010" =>  -- 5Hz
+                                    block_flip <= 4;
+                                    bank_flip  <= 25;
+                                when "1011" =>  -- 2Hz
+                                    block_flip <= 1;
+                                    bank_flip  <= 10;
+                                when "1100" =>  -- 1Hz
+                                    block_flip <= 1;
+                                    bank_flip  <= 5;
+                                when "1101" =>  -- 0.5Hz
+                                    block_flip <= 1;
+                                    bank_flip  <= 5;
+                                when "1110" =>  -- 0.2Hz
+                                    block_flip <= 1;
+                                    bank_flip  <= 2;
+                                when "1111" =>  -- 0.1Hz
+                                    block_flip <= 1;
+                                    bank_flip  <= 1;
+                            end case;
+                
+                            -- If a subbank has been provided, we dont cycle through the blocks in the bank,
+                            -- just fix on the given subbank.
+                            --
+                            case DEBUG(LEDS_SUBBANK) is
+                                when "001" => debug_counter <= 1;
+                                when "010" => debug_counter <= 3;
+                                when "011" => debug_counter <= 5;
+                                when "100" => debug_counter <= 7;
+                                when "101" => debug_counter <= 9;
+                                when "110" => debug_counter <= 11;
+                                when "111" => debug_counter <= 13;
+                                when "000" =>
+                                    flip_counter <= flip_counter + 1;
+                                    if(flip_counter = block_flip-1 and (debug_counter mod 2) = 0) then
+                                        flip_counter <= 0;
+                                        debug_counter <= debug_counter + 1;
+                                    elsif(flip_counter = bank_flip-1) then
+                                        flip_counter <= 0;
+                                        debug_counter <= debug_counter + 1;
+                                    end if;
+                            end case;
+                
+                            -- Bank 0 : T80 Signals
+                            if( DEBUG(LEDS_BANK) = "000") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "00010000";                     
+                                    when 1 => main_leds(7 downto 0) <= T80_A16(7 downto 0);            -- Address Bus A0->A7
+                                    when 2 => main_leds(7 downto 0) <= "00010001";                     
+                                    when 3 => main_leds(7 downto 0) <= T80_A16(15 downto 8);           -- Address Bus A8->A15
+                                    when 4 => main_leds(7 downto 0) <= "00010010";                     
+                                    when 5 => main_leds(7 downto 0) <= T80_DI(7 downto 0);             -- Data Bus D0->D7
+                                    when 6 => main_leds(7 downto 0) <= "00010011";                     
+                                    when 7 => main_leds(0)          <= T80_RST_n;                      -- T80 signals
+                                              main_leds(1)          <= T80_WAIT_n;
+                                              main_leds(2)          <= T80_INT_n; 
+                                              main_leds(3)          <= T80_BUSRQ_n;
+                                              main_leds(4)          <= T80_M1_n;
+                                              main_leds(5)          <= T80_IORQ_n;
+                                              main_leds(6)          <= T80_RD_n;                              
+                                              main_leds(7)          <= T80_WR_n;
+                                    when 8 => main_leds(7 downto 0) <= "00010100";                     
+                                    when 10=> main_leds(7 downto 0) <= "00010101";                     
+                                    when 12=> main_leds(7 downto 0) <= "00010110";                     
+                                    when others => main_leds        <= "00010111";
+                                end case;
+                
+                            -- Bank 1 : Video, Keyboard and CMT
+                            elsif( DEBUG(LEDS_BANK) = "001") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "00110000";                     
+                                    when 1 => main_leds(0)          <= MZ_VBLANK;                      -- Video signals
+                                              main_leds(1)          <= MZ_HBLANK;                      -- Video signals
+                                              main_leds(2)          <= '0';
+                                              main_leds(3)          <= MZ_HSYNC_n;
+                                              main_leds(4)          <= MZ_VSYNC_n;
+                                              main_leds(5)          <= MZ_R(7);
+                                              main_leds(6)          <= MZ_G(7);
+                                              main_leds(7)          <= MZ_B(7);
+                                    when 2 => main_leds(7 downto 0) <= "00110001";                     
+                                    when 3 => main_leds(0)          <= MZ_PS2_KEY(0);                  -- PS2 Keyboard Data
+                                              main_leds(1)          <= MZ_PS2_KEY(1);
+                                              main_leds(2)          <= MZ_PS2_KEY(2);
+                                              main_leds(3)          <= MZ_PS2_KEY(3);
+                                              main_leds(4)          <= MZ_PS2_KEY(4);
+                                              main_leds(5)          <= MZ_PS2_KEY(5);
+                                              main_leds(6)          <= MZ_PS2_KEY(6);
+                                              main_leds(7)          <= MZ_PS2_KEY(7);
+                                    when 4 => main_leds(7 downto 0) <= "00110010";                     
+                                    when 5 => main_leds(0)          <= MZ_PS2_KEY(9);
+                                              main_leds(1)          <= MZ_PS2_KEY(10);
+                                              main_leds(2)          <= MZ_CS_ROM_n;
+                                              main_leds(3)          <= MZ_CS_RAM_n;
+                                              main_leds(4)          <= WENSYSRAM;
+                                              main_leds(7 downto 5) <= CONFIG(TURBO);
+                                    when 6 => main_leds(7 downto 0) <= "00111011";                     
+                                    when 7 => main_leds             <= MZ_CMT_DEBUG_LEDS(7 downto 0);
+                                    when 8 => main_leds(7 downto 0) <= "00111100";                     
+                                    when 9 => main_leds             <= MZ_CMT_DEBUG_LEDS(15 downto 8);
+                                    when 10=> main_leds(7 downto 0) <= "00111101";                     
+                                    when 11=> main_leds             <= MZ_CMT_DEBUG_LEDS(23 downto 16);
+                                    when 12=> main_leds(7 downto 0) <= "00111110";                     
+                                    when 13=> main_leds             <= MZ_CMT_DEBUG_LEDS(31 downto 24);
+                                    when others => main_leds        <= "00110111";
+                                end case;
+                
+                            -- Bank 2: IOCTL
+                            elsif( DEBUG(LEDS_BANK) = "010") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "01010000";                    
+                                    when 1 => main_leds             <= MZ_IOCTL_ADDR(23 downto 16);
+                                    when 2 => main_leds(7 downto 0) <= "01010001";                     
+                                    when 3 => main_leds             <= MZ_IOCTL_ADDR(15 downto 8);
+                                    when 4 => main_leds(7 downto 0) <= "01010010";                     
+                                    when 5 => main_leds             <= MZ_IOCTL_ADDR(7 downto 0);
+                                    when 6 => main_leds(7 downto 0) <= "01010011";                    
+                                    when 7 => main_leds(0)          <= MZ_IOCTL_RD;
+                                              main_leds(1)          <= MZ_IOCTL_WR;
+                                              main_leds(2)          <= MZ_IOCTL_DOWNLOAD;
+                                              main_leds(3)          <= MZ_IOCTL_UPLOAD;
+                                              main_leds(4)          <= MZ_IOCTL_WENROM;
+                                              main_leds(5)          <= MZ_IOCTL_WENRAM;
+                                              main_leds(6)          <= MZ_IOCTL_RENROM;
+                                              main_leds(7)          <= MZ_IOCTL_RENRAM;
+                                    when 8 => main_leds(7 downto 0) <= "01010100";                     
+                                    when 10=> main_leds(7 downto 0) <= "01010101";                     
+                                    when 12=> main_leds(7 downto 0) <= "01010110";                     
+                                    when others => main_leds        <= "01010111";
+                                end case;
+                
+                            -- Bank 3 : Config
+                            elsif( DEBUG(LEDS_BANK) = "011") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "01110000";                    
+                                    when 1 => main_leds(0)          <= CONFIG(MZ80K);                  -- Mode of operation.
+                                              main_leds(1)          <= CONFIG(pkgs.mctrl_pkg.MZ80C);
+                                              main_leds(2)          <= CONFIG(MZ1200);
+                                              main_leds(3)          <= CONFIG(MZ80A);
+                                              main_leds(4)          <= CONFIG(pkgs.mctrl_pkg.MZ80B);
+                                              main_leds(5)          <= CONFIG(MZ2000);
+                                              main_leds(6)          <= CONFIG(MZ700);
+                                              main_leds(7)          <= CONFIG(MZ800);
+                                    when 2 => main_leds(7 downto 0) <= "01110001";                     
+                                    when 3 => main_leds(0)          <= CONFIG(MZ_KC);
+                                              main_leds(1)          <= CONFIG(MZ_A);
+                                              main_leds(2)          <= CONFIG(pkgs.mctrl_pkg.MZ_B);
+                                              main_leds(3)          <= CONFIG(MZ_80B);
+                                              main_leds(4)          <= CONFIG(MZ_80C);
+                                              main_leds(5)          <= CONFIG(NORMAL);
+                                              main_leds(6)          <= CONFIG(NORMAL80);
+                                              main_leds(7)          <= CONFIG(COLOUR);
+                                    when 4 => main_leds(7 downto 0) <= "01110010";                     
+                                    when 5 => main_leds(0)          <= CONFIG(AUDIOSRC);
+                                              main_leds(3 downto 1) <= CONFIG(TURBO);
+                                              main_leds(6 downto 4) <= CONFIG(FASTTAPE);
+                                              main_leds(7)          <= CONFIG(PCGRAM);
+                                    when 6 => main_leds(7 downto 0) <= "01110011";                    
+                                    when 7 => main_leds(3 downto 0) <= CONFIG(CPUSPEED);
+                                              main_leds(6 downto 4) <= CONFIG(VIDSPEED);
+                                              main_leds(7)          <= '0';
+                                    when 8 => main_leds(7 downto 0) <= "01110100";                     
+                                    when 9 => main_leds(1 downto 0) <= CONFIG(PERSPEED);
+                                              main_leds(3 downto 2) <= CONFIG(RTCSPEED);
+                                              main_leds(5 downto 4) <= CONFIG(SNDSPEED);
+                                              main_leds(7 downto 6) <= CONFIG(BUTTONS);
+                                    when 10=> main_leds(7 downto 0) <= "01110101";                     
+                                    when 11=> main_leds             <= "00000000";
+                                    when 12=> main_leds(7 downto 0) <= "01110110";                     
+                                    when 13=> main_leds             <= "00000000";
+                                    when others => main_leds        <= "01110111";
+                                end case;
+                                
+                
+                            -- Bank 4 & 5: MZ80C Debug Leds
+                            elsif( DEBUG(LEDS_BANK) = "100") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "10010000";                    
+                                    when 1 => main_leds             <= MZ80C_DEBUG_LEDS(7 downto 0);
+                                    when 2 => main_leds(7 downto 0) <= "10010001";                     
+                                    when 3 => main_leds             <= MZ80C_DEBUG_LEDS(15 downto 8);
+                                    when 4 => main_leds(7 downto 0) <= "10010010";                     
+                                    when 5 => main_leds             <= MZ80C_DEBUG_LEDS(23 downto 16);
+                                    when 6 => main_leds(7 downto 0) <= "10010011";                     
+                                    when 7 => main_leds             <= MZ80C_DEBUG_LEDS(31 downto 24);
+                                    when 8 => main_leds(7 downto 0) <= "10010100";                     
+                                    when 9 => main_leds             <= MZ80C_DEBUG_LEDS(39 downto 32);
+                                    when 10=> main_leds(7 downto 0) <= "10010101";                     
+                                    when 11=> main_leds             <= MZ80C_DEBUG_LEDS(47 downto 40);
+                                    when 12=> main_leds(7 downto 0) <= "10010110";                     
+                                    when 13=> main_leds             <= MZ80C_DEBUG_LEDS(55 downto 48);
+                                    when others => main_leds        <= "10010111";
+                                end case;
+                            elsif( DEBUG(LEDS_BANK) = "101") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "10110000";                    
+                                    when 1 => main_leds             <= MZ80C_DEBUG_LEDS(63 downto 56);
+                                    when 2 => main_leds(7 downto 0) <= "10110001";
+                                    when 3 => main_leds             <= MZ80C_DEBUG_LEDS(71 downto 64);
+                                    when 4 => main_leds(7 downto 0) <= "10110010";                     
+                                    when 5 => main_leds             <= MZ80C_DEBUG_LEDS(79 downto 72);
+                                    when 6 => main_leds(7 downto 0) <= "10110011";                     
+                                    when 7 => main_leds             <= MZ80C_DEBUG_LEDS(87 downto 80);
+                                    when 8 => main_leds(7 downto 0) <= "10110100";                     
+                                    when 9 => main_leds             <= MZ80C_DEBUG_LEDS(95 downto 88);
+                                    when 10=> main_leds(7 downto 0) <= "10110101";                     
+                                    when 11=> main_leds             <= MZ80C_DEBUG_LEDS(103 downto 96);
+                                    when 12=> main_leds(7 downto 0) <= "10110110";                     
+                                    when 13=> main_leds             <= MZ80C_DEBUG_LEDS(111 downto 104);
+                                    when others => main_leds        <= "10110111";
+                                end case;
+                
+                            -- Bank 6 & 7 : MZ80B Debug Leds
+                            elsif( DEBUG(LEDS_BANK) = "110") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "11010000";                    
+                                    when 1 => main_leds             <= MZ80B_DEBUG_LEDS(7 downto 0);
+                                    when 2 => main_leds(7 downto 0) <= "11010001";                     
+                                    when 3 => main_leds             <= MZ80B_DEBUG_LEDS(15 downto 8);
+                                    when 4 => main_leds(7 downto 0) <= "11010010";                     
+                                    when 5 => main_leds             <= MZ80B_DEBUG_LEDS(23 downto 16);
+                                    when 6 => main_leds(7 downto 0) <= "11010011";                     
+                                    when 7 => main_leds             <= MZ80B_DEBUG_LEDS(31 downto 24);
+                                    when 8 => main_leds(7 downto 0) <= "11010100";                     
+                                    when 9 => main_leds             <= MZ80B_DEBUG_LEDS(39 downto 32);
+                                    when 10=> main_leds(7 downto 0) <= "11010101";                     
+                                    when 11=> main_leds             <= MZ80B_DEBUG_LEDS(47 downto 40);
+                                    when 12=> main_leds(7 downto 0) <= "11010110";                     
+                                    when 13=> main_leds             <= MZ80B_DEBUG_LEDS(55 downto 48);
+                                    when others => main_leds        <= "11010111";
+                                end case;
+                            elsif( DEBUG(LEDS_BANK) = "111") then
+                                case debug_counter is
+                                    when 0 => main_leds(7 downto 0) <= "11110000";                    
+                                    when 1 => main_leds             <= MZ80B_DEBUG_LEDS(63 downto 56);
+                                    when 2 => main_leds(7 downto 0) <= "11110001";                     
+                                    when 3 => main_leds             <= MZ80B_DEBUG_LEDS(71 downto 64);
+                                    when 4 => main_leds(7 downto 0) <= "11110010";                     
+                                    when 5 => main_leds             <= MZ80B_DEBUG_LEDS(79 downto 72);
+                                    when 6 => main_leds(7 downto 0) <= "11110011";                     
+                                    when 7 => main_leds             <= MZ80B_DEBUG_LEDS(87 downto 80);
+                                    when 8 => main_leds(7 downto 0) <= "11110100";                     
+                                    when 9 => main_leds             <= MZ80B_DEBUG_LEDS(95 downto 88);
+                                    when 10=> main_leds(7 downto 0) <= "11110101";                     
+                                    when 11=> main_leds             <= MZ80B_DEBUG_LEDS(103 downto 96);
+                                    when 12=> main_leds(7 downto 0) <= "11110110";                     
+                                    when 13=> main_leds             <= MZ80B_DEBUG_LEDS(111 downto 104);
+                                    when others => main_leds        <= "11110111";
+                                end case;
+                            end if;
+                        end if;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+    DEBUG1: if DEBUG_ENABLE = 0 generate
+        main_leds   <= (others => '0');
+    end generate;
+end rtl;
diff --git a/sharpmz_assignment_defaults.qdf b/sharpmz_assignment_defaults.qdf
new file mode 100644
index 0000000..c9c4c19
--- /dev/null
+++ b/sharpmz_assignment_defaults.qdf
@@ -0,0 +1,807 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
+# Date created = 18:26:55  June 18, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL Enable
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/software/asm/.sharpmz-test.asm.swo b/software/asm/.sharpmz-test.asm.swo
new file mode 100644
index 0000000..b5b1aa7
Binary files /dev/null and b/software/asm/.sharpmz-test.asm.swo differ
diff --git a/software/asm/1Z-013A.asm b/software/asm/1Z-013A.asm
new file mode 100644
index 0000000..235e5a3
--- /dev/null
+++ b/software/asm/1Z-013A.asm
@@ -0,0 +1,3281 @@
+        ; MONITOR PROGRAM 1Z-013A 
+        ;    (MZ700) FOR PAL 
+        ;      REV. 83.4.7
+        ; Tuesday, 02 of June 1998 at 10:02 PM
+        ; Tuesday, 09 of June 1998 at 07:17 AM
+; Configurable parameters. These are set in the wrapper file, ie monitor_SA1510.asm
+;
+;COLW:   EQU     40                      ; Width of the display screen (ie. columns).
+;ROW:    EQU     25                      ; Number of rows on display screen.
+;SCRNSZ: EQU     COLW * ROW              ; Total size, in bytes, of the screen display area.
+
+        ORG     0000h        ; 0000h Entrypoint 
+MONIT:  JP      START                                                    ; MONITOR ON
+GETL:   JP      QGETL                                                    ; GET LINE (END "CR")
+LETNL:  JP      QLTNL                                                    ; NEW LINE
+NL:     JP      QNL                                                      ;
+PRNTS:  JP      QPRTS                                                    ; PRINT SPACE
+PRNTT:  JP      QPRTT                                                    ; PRINT TAB
+PRNT:   JP      QPRNT                                                    ; 1 CHARACTER PRINT
+MSG:    JP      QMSG                                                     ; 1 LINE PRINT (END "0DH")
+MSGX:   JP      QMSGX                                                    ; RST 18H
+GETKY:  JP      QGET                                                     ; GET KEY
+BRKEY:  JP      QBRK                                                     ; GET BREAK
+WRINF:  JP      QWRI                                                     ; WRITE INFORMATION
+WRDAT:  JP      QWRD                                                     ; WRITE DATA
+RDINF:  JP      QRDI                                                     ; READ INFORMATION
+RDDAT:  JP      QRDD                                                     ; READ DATA
+VERFY:  JP      QVRFY                                                    ; VERIFYING CMT
+MELDY:  JP      QMLDY                                                    ; RST 30H
+TIMST:  JP      QTMST                                                    ; TIME SET
+        NOP
+        NOP
+        JP      1038H                                                    ; INTERRUPT ROUTINE (8253)
+TIMRD:  JP      QTMRD                                                    ; TIME READ
+BELL:   JP      QBEL                                                     ; BELL ON
+XTEMP:  JP      QTEMP                                                    ; TEMPO SET (1 - 7)
+MSTA:   JP      MLDST                                                    ; MELODY START
+MSTP:   JP      MLDSP                                                    ; MELODY STOP
+
+START:  LD      SP,SPV                                                   ; STACK SET (10F0H)
+        IM      1                                                        ; IM 1 SET
+        CALL    QMODE                                                    ; 8255 MODE SET
+        CALL    QBRK                                                     ; CTRL ?
+        JR      NC,ST0
+        CP      20H                                                      ; KEY IS CTRL KEY
+        JR      NZ,ST0
+CMY0:   OUT     (0E1H),A                                                 ; D000-FFFFH IS DRAM
+        LD      DE,0FFF0H                                                ; TRANS. ADR.
+        LD      HL,DMCP                                                  ; MEMORY CHANG PROGRAM
+        LD      BC,05H                                                   ; BYTE SIZE
+        LDIR    
+        JP      0FFF0H                                                   ; JUMP $FFF0
+
+DMCP:   OUT     (0E0H),A                                                 ; 0000H-0FFFH IS DRAM
+        JP      0000H
+
+ST0:    LD      B,0FFH                                                   ; BUFFER CLEAR
+        LD      HL,NAME                                                  ; 10F1H-11F0H CLEAR
+        CALL    QCLER
+        LD      A,16H                                                    ; LASTER CLR.
+        CALL    PRNT
+        LD      A,71H                                                    ; BACK:BLUE CHA.:WRITE
+        LD      HL,0D800H                                                ; COLOR ADDRESS
+        CALL    NCLR8
+        LD      HL,TIMIN                                                 ; INTERRUPT JUMP ROUTINE
+        LD      A,0C3H
+        LD      (1038H),A
+        LD      (1039H),HL
+        LD      A,04H                                                    ; NORMAL TEMPO
+        LD      (TEMPW),A
+        CALL    MLDSP                                                    ; MELODY STOP
+        CALL    NL
+        LD      DE,MSGQ3                                                 ; ** MONITOR 1Z-013A **
+        RST     18H                                                      ; CALL MGX
+        CALL    QBEL
+SS:     LD      A,01H
+        LD      (SWRK),A                                                 ; KEY IN SILENT
+        LD      HL,0E800H                                                ; USR ROM?
+        LD      (HL),A                                                   ; ROM CHECK
+        JR      FD2
+
+ST1:    CALL    NL
+        LD      A,2AH                                                    ; "*" PRINT
+        CALL    PRNT
+        LD      DE,BUFER                                                 ; GET LINE WORK (11A3H)
+        CALL    GETL
+ST2:    LD      A,(DE)
+        INC     DE
+        CP      0DH
+        JR      Z,ST1
+        CP      'J'                                                      ; JUMP
+        JR      Z,GOTO
+        CP      'L'                                                      ; LOAD PROGRAM
+        JR      Z,LOAD
+        CP      'F'                                                      ; FLOPPY ACCESS
+        JR      Z,FD
+        CP      'B'                                                      ; KEY IN BELL
+        JR      Z,SG
+        CP      '#'                                                      ; CHANG MEMORY
+        JR      Z,CMY0
+        CP      'P'                                                      ; PRINTER TEST
+        JR      Z,PTEST
+        CP      'M'                                                      ; MEMORY CORRECTION
+        JP      Z,MCOR
+        CP      'S'                                                      ; SAVE DATA
+        JP      Z,SAVE
+        CP      'V'                                                      ; VERIFYING DATA
+        JP      Z,VRFY
+        CP      'D'                                                      ; DUMP DATA
+        JP      Z,DUMP
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        JR      ST2                                                      ; NO COMMAND
+
+        ;    JUMP COMMAND
+
+GOTO:   CALL    HEXIY
+        JP      (HL)
+
+        ;    KEY SOUND ON/OFF
+
+SG:     LD      A,(SWRK)                                                 ; D0=SOUND WORK
+        RRA     
+        CCF                                                              ; CHANGE MODE
+        RLA     
+        JR      SS+2
+
+        ;    FLOPPY
+
+FD:     LD      HL,0F000H                                                ; FLOPPY I/O CHECK
+FD2:    LD      A,(HL)
+        OR      A
+        JR      NZ,ST1
+FD1:    JP      (HL)
+
+        ;    ERROR (LOADING)
+
+QER:    CP      02H                                                      ; A=02H : BREAK IN
+        JR      Z,ST1
+        LD      DE,MSGE1                                                 ; CHECK SUM ERROR
+        RST     18H                                                      ; CALL MSGX
+L010F:    JR      ST1
+
+        ;    LOAD COMMAND
+
+LOAD:      CALL    QRDI
+        JR      C,QER
+LOA0:   CALL    NL
+        LD      DE,MSGQ2                                                 ; LOADING
+        RST     18H                                                      ; CALL MSGX
+        LD      DE,NAME                                                  ; FILE NAME
+        RST     18H                                                      ; CALL MSGX
+        CALL    QRDD
+        JR      C,QER
+        LD      HL,(EXADR)                                               ; EXECUTE ADDRESS
+        LD      A,H
+        CP      12H                                                      ; EXECUTE CHECK
+        JR      C,L010F
+        JP      (HL)
+
+        ;    GETLINE AND BREAK IN CHECK
+        ;
+        ;    EXIT BREAK IN THEN JUMP (ST1)
+        ;    ACC=TOP OF LINE DATA
+
+BGETL:  EX      (SP),HL
+        POP     BC                                                       ; STACK LOAD
+        LD      DE,BUFER                                                 ; MONITOR GETLINE BUFF
+        CALL    GETL
+        LD      A,(DE)
+        CP      1BH                                                      ; BREAK CODE
+        JR      Z,L010F                                                  ; JP Z,ST1
+        JP      (HL)
+
+        ;    ASCII TO HEX CONVERT
+        ;    INPUT (DE)=ASCII
+        ;    CY=1 THEN JUMP (ST1)
+
+HEXIY:  EX      (SP),IY
+        POP     AF
+        CALL    HLHEX
+        JR      C,L010F                                                  ; JP C,ST1
+        JP      (IY)
+
+MSGE1:    DB    "CHECK SUM ER.\r"
+
+        ;    PLOTTER PRINTER TEST COMMAND
+        ;    (DPG23)
+        ;    &=CONTROL COMMANDS GROUP
+        ;    C=PEN CHANGE
+        ;    G=GRAPH MODE
+        ;    S=80 CHA. IN 1 LINE
+        ;    L=40 CHA. IN 1 LINE
+        ;    T=PLOTTER TEST
+        ;    IN (DE)=PRINT DATA
+
+PTEST:  LD      A,(DE)
+        CP      '&'
+        JR      NZ,PTST1
+PTST0:  INC     DE
+        LD      A,(DE)
+        CP      'L'                                                      ; 40 IN 1 LINE
+        JR      Z,PLPT
+        CP      'S'                                                      ; 80 IN 1 LINE
+        JR      Z,PPLPT
+        CP      'C'                                                      ; PEN CHANGE
+        JR      Z,PEN
+        CP      'G'                                                      ; GRAPH MODE
+        JR      Z,PLOT
+        CP      'T'                                                      ; TEST
+        JR      Z,PTRN
+PTST1:  CALL    PMSG                                                     ; PLOT MESSAGE
+        JP      ST1
+
+PLPT:   LD      DE,LLPT                                                  ; 01-09-09-0B-0D
+        JR      PTST1
+
+PPLPT:  LD      DE,SLPT                                                  ; 01-09-09-09-0D
+        JR      PTST1
+
+PTRN:   LD      A,04H                                                    ; TEST PATTERN
+        JR      PLOT+2
+
+PLOT:   LD      A,02H                                                    ; GRAPH CODE
+    CALL    LPRNT
+        JR      PTST0
+
+PEN:    LD      A,1DH                                                    ; 1 CHANGE CODE (TEXT MODE)
+        JR      PLOT+2
+
+        ;    1CHA. PRINT TO $LPT
+        ;    IN: ACC PRINT DATA
+
+LPRNT:  LD      C,0                                                      ; RDA TEST (READY? RDA=0)
+        LD      B,A                                                      ; PRINT DATA STORE
+        CALL    RDA
+        LD      A,B
+        OUT     (0FFH),A                                                 ; DATA OUT 
+        LD      A,80H                                                    ; RDP HIGH
+        OUT     (0FEH),A
+        LD      C,01H                                                    ; RDA TEST
+        CALL    RDA
+    XOR     A                                                            ; RDP LOW
+        OUT     (0FEH),A
+        RET     
+
+        ;    $LPT MSG
+        ;    IN: DE DATA LOW ADDRESS
+        ;    0DH MSG END
+
+PMSG:   PUSH    DE
+        PUSH    BC
+        PUSH    AF
+PMSG1:  LD      A,(DE)                                                   ; ACC=DATA
+        CALL    LPRNT
+        LD      A,(DE)
+        INC     DE
+        CP      0DH                                                      ; END?
+        JR      NZ,PMSG1
+        POP     AF
+        POP     BC
+        POP     DE
+        RET     
+
+        ;    RDA CHECK
+        ;    BRKEY IN TO MONITOR RETURN
+        ;    IN: C RDA CODE
+
+RDA:    IN      A,(0FEH)
+        AND     0DH                                                      ; RDA ONLY
+        CP      C
+        RET     Z
+        CALL    BRKEY
+        JR      NZ,RDA
+        LD      SP,SPV
+        JP      ST1
+
+        ;    MELODY
+        ;    DE=DATA LOW ADDRESS
+        ;    EXIT CF=1 BREAK
+        ;         CF=0 OK
+
+QMLDY:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      A,02H
+        LD      (OCTV),A
+        LD      B,01H
+MLD1:   LD      A,(DE)
+        CP      0DH                                                      ; CR
+        JR      Z,MLD4
+        CP      0C8H                                                     ; END MARK
+        JR      Z,MLD4
+        CP      0CFH                                                     ; UNDER OCTAVE
+        JR      Z,MLD2
+        CP      2DH                                                      ; "-" 
+        JR      Z,MLD2
+        CP      2BH                                                      ; "+"
+        JR      Z,MLD3
+        CP      0D7H                                                     ; UPPER OCTAVE
+        JR      Z,MLD3
+        CP      23H                                                      ; "#" HANON
+        LD      HL,MTBL
+        JR      NZ,L01F5
+        LD      HL,MNTBL
+        INC     DE
+L01F5:    CALL    ONPU                                                   ; ONTYO SET
+        JR      C,MLD1
+        CALL    RYTHM
+        JR      C,MLD5
+        CALL    MLDST                                                    ; MELODY START
+        LD      B,C
+        JR      MLD1
+
+MLD2:   LD      A,3
+L0207:    LD      (OCTV),A
+        INC     DE
+        JR      MLD1
+
+MLD3:   LD      A,01H
+        JR      L0207
+
+MLD4:   CALL    RYTHM
+MLD5:   PUSH    AF
+        CALL    MLDSP
+        POP     AF
+        JP      RET3
+
+        ;    ONPU TO RATIO CONV
+        ;    EXIT (RATIO)=RATIO VALUE
+        ;    C=ONTYO*TEMPO
+
+ONPU:   PUSH    BC
+        LD      B,8
+ONP1:   LD      A,(DE)
+L0220:    CP      (HL)
+        JR      Z,ONP2
+        INC     HL
+        INC     HL
+        INC     HL
+        DJNZ    L0220
+        SCF     
+        INC     DE
+        POP     BC
+        RET     
+
+ONP2:   INC     HL
+        PUSH    DE
+        LD      E,(HL)
+        INC     HL
+        LD      D,(HL)
+        EX      DE,HL
+        LD      A,H
+        OR      A
+        JR      Z,L023F
+        LD      A,(OCTV)                                                 ; 11A0H OCTAVE WORK
+L0239:  DEC     A
+        JR      Z,L023F
+        ADD     HL,HL
+        JR      L0239
+
+L023F:  LD      (RATIO),HL                                               ; 11A1H ONPU RATIO
+        LD      HL,OCTV
+        LD      (HL),02H
+        DEC     HL
+        POP     DE
+        INC     DE
+        LD      A,(DE)
+        LD      B,A
+        AND     0F0H                                                     ; ONTYO ?
+        CP      30H
+        JR      Z,L0255
+        LD      A,(HL)                                                   ; HL=ONTYO
+        JR      L025A
+
+L0255:  INC     DE
+        LD      A,B
+        AND     0FH
+        LD      (HL),A                                                   ; HL=ONTYO
+L025A:  LD      HL,OPTBL
+        ADD     A,L
+        LD      L,A
+        LD      C,(HL)
+        LD      A,(TEMPW)
+        LD      B,A
+        XOR     A
+ONP3:   ADD     A,C
+        DJNZ    ONP3
+        POP     BC
+        LD      C,A
+        XOR     A
+        RET     
+
+MTBL:    DB    "C"
+    DW    0846H
+    DB    "D"
+    DW    075FH
+    DB    "E"
+    DW    0691H
+    DB    "F"
+    DW    0633H
+    DB    "G"
+    DW    0586H
+    DB    "A"
+    DW    04ECH
+    DB    "B"
+    DW    0464H
+    DB    "R"
+    DW    0000H
+MNTBL:    DB    "C"                                                      ; #C
+    DW    07CFH
+    DB    "D"                                                            ; #D
+    DW    06F5H
+    DB    "E"                                                            ; #E
+    DW    0633H
+    DB    "F"                                                            ; #F
+    DW    05DAH
+    DB    "G"                                                            ; #G
+    DW    0537H
+    DB    "A"                                                            ; #A
+    DW    04A5H
+    DB    "B"                                                            ; #B
+    DW    0423H
+    DB    "R"                                                            ; #R
+    DW    0000H
+OPTBL:    DB    01H
+    DB    02H
+    DB    03H
+    DB    04H
+    DB    06H
+    DB    08H
+    DB    0CH
+    DB    10H
+    DB    18H
+    DB    20H
+
+        ;    INCREMENT DE REG.
+
+P4DE:   INC     DE
+    INC    DE
+        INC     DE
+        INC     DE
+        RET     
+
+        ;    MELODY START & STOP
+
+MLDST:  LD      HL,(RATIO)
+        LD      A,H
+        OR      A
+        JR      Z,MLDSP
+        PUSH    DE
+        EX      DE,HL
+        LD      HL,CONT0
+        LD      (HL),E
+        LD      (HL),D
+        LD      A,01H
+        POP     DE
+        JR      MLDS1
+
+MLDSP:  LD      A,36H                                                    ; MODE SET (8253 C0)
+        LD      (CONTF),A                                                ; E007H
+        XOR     A
+MLDS1:  LD      (SUNDG),A                                                ; E008H
+        RET                                                              ; TEHRO SET
+
+        ;    RHYTHM
+        ;    B=COUNT DATA
+        ;    IN
+        ;    EXIT CF=1 BREAK
+        ;         CF=0 OK
+
+RYTHM:  LD      HL,KEYPA                                                 ; E000H
+        LD      (HL),0F8H
+        INC     HL
+        LD      A,(HL)
+        AND     81H                                                      ; BREAK IN CHECK
+        JR      NZ,L02D5
+        SCF     
+        RET     
+
+L02D5:  LD      A,(TEMP)                                                 ; E008H
+        RRCA                                                             ; TEMPO OUT
+        JR      C,L02D5
+L02DB:  LD      A,(TEMP)
+        RRCA    
+        JR      NC,L02DB
+        DJNZ    L02D5
+        XOR     A
+        RET     
+
+        ;    TEMPO SET
+        ;    ACC=VALUE (1-7)
+
+QTEMP:  PUSH    AF
+        PUSH    BC
+        AND     0FH
+        LD      B,A
+        LD      A,8
+        SUB     B
+        LD      (TEMPW),A
+        POP     BC
+        POP     AF
+        RET     
+
+        ;    CRT MANAGEMENT
+        ;    EXIT HL:DSPXY H=Y,L=X
+        ;    DE:MANG ADR. (ON DSPXY)
+        ;    A :MANG DATA
+        ;    CY:MANG=1
+
+PMANG:  LD      HL,MANG                                                  ; CRT MANG POINTER
+        LD      A,(1172H)                                                ; DSPXY+1
+        ADD     A,L
+        LD      L,A
+        LD      A,(HL)
+        INC     HL
+        RL      (HL)
+        OR      (HL)
+        RR      (HL)
+        RRCA    
+        EX      DE,HL
+        LD      HL,(DSPXY)
+        RET     
+
+        ;    TIME SET
+        ;    ACC=0 : AM
+        ;       =1 : PM
+        ;    DE=SEC: BINARY
+
+QTMST:  DI      
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      (AMPM),A                                                 ; AMPM DATA
+        LD      A,0F0H
+        LD      (TIMFG),A                                                ; TIME FLAG
+        LD      HL,0A8C0H                                                ; 12 HOURS (43200 SECONDS)
+        XOR     A
+        SBC     HL,DE                                                    ; COUNT DATA = 12H-IN DATA
+        PUSH    HL
+        NOP     
+        EX      DE,HL
+        LD      HL,CONTF                                                 ; E007H
+        LD      (HL),74H                                                 ; C1
+        LD      (HL),0B0H                                                ; C2
+        DEC     HL                                                       ; CONT2
+        LD      (HL),E                                                   ; E006H
+        LD      (HL),D
+        DEC     HL                                                       ; CONT1
+        LD      (HL),0AH                                                 ; E005H STROBE 640,6�SECONDS COUNT2
+        LD      (HL),0
+        INC     HL
+        INC     HL                                                       ; CONTF
+        LD      (HL),80H                                                 ; E007H
+        DEC     HL                                                       ; CONT2
+QTMS1:  LD      C,(HL)                                                   ; E006H
+        LD      A,(HL)
+        CP      D
+        JR      NZ,QTMS1
+        LD      A,C
+        CP      E
+        JR      NZ,QTMS1
+        DEC     HL                                                       ; E005H
+        NOP     
+        NOP     
+        NOP     
+        LD      (HL),0FBH                                                ; 1 SECOND (15611HZ) E005H
+        LD      (HL),3CH
+        INC     HL
+        POP     DE
+QTMS2:  LD      C,(HL)                                                   ; E006H
+        LD      A,(HL)
+        CP      D
+        JR      NZ,QTMS2
+        LD      A,C
+        CP      E
+        JR      NZ,QTMS2
+        POP     HL
+        POP     DE
+        POP     BC
+        EI      
+        RET     
+
+        ;    BELL DATA
+        ;    
+QBELD:    DB    0D7H
+    DB    "A0"
+    DB    0DH
+        NOP     
+        NOP     
+
+        ;    TIME READ
+        ;    EXIT ACC=0 :AM
+        ;            =1 :PM
+        ;         DE=SEC. BINARY
+
+QTMRD:  PUSH    HL
+        LD      HL,CONTF
+        LD      (HL),80H                                                 ; E007H C2
+        DEC     HL                                                       ; CONT2
+        DI      
+        LD      E,(HL)
+        LD      D,(HL)                                                   ; e006H C2 MODE0
+        EI      
+L0363:  LD      A,E
+        OR      D
+        JR      Z,QTMR1
+        XOR     A
+        LD      HL,0A8C0H                                                ; 12 HOURS
+        SBC     HL,DE
+        JR      C,QTMR2
+        EX      DE,HL
+        LD      A,(AMPM)
+        POP     HL
+        RET     
+
+QTMR1:  LD      DE,0A8C0H
+L0378:  LD      A,(AMPM)
+        XOR     01H
+        POP     HL
+        RET     
+
+QTMR2:  DI      
+        LD      HL,CONT2
+        LD      A,(HL)
+        CPL     
+        LD      E,A
+        LD      A,(HL)
+        CPL     
+        LD      D,A
+        EI      
+        INC     DE
+        JR      L0378
+
+        ;    TIME INTERRUPT
+
+TIMIN:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,AMPM
+        LD      A,(HL)
+        XOR     01H
+        LD      (HL),A
+        LD      HL,CONTF
+        LD      (HL),80H                                                 ; CONT2
+        DEC     HL
+        PUSH    HL
+        LD      E,(HL)
+        LD      D,(HL)
+        LD      HL,0A8C0H
+        ADD     HL,DE
+        DEC     HL
+        DEC     HL
+        EX      DE,HL
+        POP     HL
+        LD      (HL),E
+        LD      (HL),D
+        POP     HL
+        POP     DE
+        POP     BC
+        POP     AF
+        EI      
+        RET     
+
+        ;    SPACE PRINT AND DISP ACC
+        ;    INPUT:HL=DISP. ADR.
+
+SPHEX:  CALL    QPRTS                                                    ; SPACE PRINT
+        LD      A,(HL)
+        CALL    PRTHX                                                    ; DSP OF ACC (ASCII)
+        LD      A,(HL)
+        RET     
+
+        ;    (ASCII PRINT) FOR HL
+
+PRTHL:  LD      A,H
+        CALL    PRTHX
+        LD      A,L
+        JR      PRTHX
+
+        NOP     
+        NOP     
+
+        ;    (ASCII PRINT) FOR ACC
+
+PRTHX:  PUSH    AF
+        RRCA    
+        RRCA    
+        RRCA    
+        RRCA    
+        CALL    ASC
+        CALL    PRNT
+        POP     AF
+        CALL    ASC
+        JP      PRNT
+
+        ;    80 CHA. 1 LINE CODE (DATA)
+
+SLPT:    DB    01H                                                       ; TEXT MODE
+    DB    09H
+    DB    09H
+    DB    09H
+    DB    0DH
+
+        ;    HEXADECIMAL TO ASCII
+        ;    IN  : ACC (D3-D0)=HEXADECIMAL
+        ;    EXIT: ACC = ASCII
+ASC:    AND     0FH
+        CP      0AH
+        JR      C,NOADD
+        ADD     A,07H
+NOADD:  ADD     A,30H
+        RET     
+
+        ;    ASCII TO HEXADECIMAL
+        ;    IN  : ACC = ASCII
+        ;    EXIT: ACC = HEXADECIMAL
+        ;          CY  = 1 ERROR
+
+HEXJ:   SUB     30H
+        RET     C                                                        ; <0
+        CP      0AH
+        CCF     
+        RET     NC                                                       ; 0-9
+        SUB     07H
+        CP      10H
+        CCF     
+        RET     C
+        CP      0AH
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+HEX:    JR      HEXJ
+
+        ;    PRESS PLAY MESSAGE
+
+MSGN1:    DW    207FH
+MSGN2:    DB    "PLAY\r"
+MSGN3:    DW    207FH
+    DB    "RECORD.\r"                                                    ; PRESS RECORD
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    4 ASCII TO (HL)
+        ;    IN  DE=DATA LOW ADDRESS
+        ;    EXIT CF=0 : OK
+        ;           =1 : OUT
+
+HLHEX:  PUSH    DE
+        CALL    L2HEX
+        JR      C,L041D
+        LD      H,A
+        CALL    L2HEX
+        JR      C,L041D
+        LD      L,A
+L041D:  POP     DE
+        RET     
+
+        ;    2 ASCII TO (ACC)
+        ;    IN  DE=DATA LOW ADRRESS
+        ;    EXIT CF=0 : OK
+        ;           =1 : OUT
+
+L2HEX:  PUSH    BC
+        LD      A,(DE)
+        INC     DE
+        CALL    HEX
+        JR      C,L0434
+        RRCA    
+        RRCA    
+        RRCA    
+        RRCA    
+        LD      C,A
+        LD      A,(DE)
+        INC     DE
+        CALL    HEX
+        JR      C,L0434
+        OR      C
+L0434:  POP     BC
+        RET     
+
+        ;    WRITE INFORMATION
+
+QWRI:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D7H                                                   ; "W"
+        LD      E,0CCH                                                   ; "L"
+        LD      HL,IBUFE                                                 ; 10F0H
+        LD      BC,80H                                                   ; WRITE BYTE SIZE
+WRI1:   CALL    CKSUM                                                    ; CHECK SUM
+        CALL    MOTOR                                                    ; MOTOR ON
+        JR      C,WRI3
+        LD      A,E
+        CP      0CCH                                                     ; "L"
+        JR      NZ,WRI2
+        CALL    NL
+        PUSH    DE
+        LD      DE,MSGN7                                                 ; WRITING
+        RST     18H                                                      ; CALL MSGX
+        LD      DE,NAME                                                  ; FILE NAME
+        RST     18H                                                      ; CALL MSGX
+        POP     DE
+WRI2:   CALL    GAP
+        CALL    WTAPE
+WRI3:   JP      RET2
+
+MSGN7:    DB    "WRITING \r"
+
+        ;    40 CHA. IN 1 LINE CODE (DATA)
+
+LLPT:    DB    01H                                                       ; TEXT MODE
+    DB    09H
+    DB    09H
+    DB    0BH
+    DB    0DH
+
+        ;    WRITE DATA
+        ;    EXIT CF=0 : OK
+        ;           =1 : BREAK
+
+QWRD:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D7H                                                   ; "W"
+        LD      E,53H                                                    ; "S"
+L047D:  LD      BC,(SIZE)                                                ; WRITE DATA BYTE SIZE
+        LD      HL,(DTADR)                                               ; WRITE DATA ADDRESS
+        LD      A,B
+        OR      C
+        JR      Z,RET1
+        JR      WRI1
+
+        ;    TAPE WRITE
+        ;    BC=BYTE SIZE
+        ;    HL=DATA LOW ADDRESS
+        ;    EXIT CF=0 : OK
+        ;           =1 : BREAK
+
+WTAPE:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,02H
+        LD      A,0F8H                                                   ; 88H WOULD BE BETTER!!
+        LD      (KEYPA),A                                                ; E000H
+WTAP1:  LD      A,(HL)
+        CALL    WBYTE                                                    ; 1 BYTE WRITE
+        LD      A,(KEYPB)                                                ; E001H
+        AND     81H                                                      ; SHIFT & BREAK
+        JP      NZ,WTAP2
+        LD      A,02H                                                    ; BREAK IN CODE
+        SCF     
+        JR      WTAP3
+
+WTAP2:  INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JP      NZ,WTAP1
+        LD      HL,(SUMDT)                                               ; SUM DATA SET
+        LD      A,H
+        CALL    WBYTE
+        LD      A,L
+        CALL    WBYTE
+        CALL    LONG
+        DEC     D
+        JP      NZ,L04C2
+        OR      A
+        JP      WTAP3
+
+L04C2:  LD      B,0
+L04C4:  CALL    SHORT
+        DEC     B
+        JP      NZ,L04C4
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+        JP      WTAP1
+
+WTAP3:
+RET1:   POP     HL
+        POP     BC
+        POP     DE
+        RET     
+
+    DB    2FH
+    DB    4EH
+
+        ;    READ INFORMATION (FROM $CMT)
+        ;    EXIT ACC=0: OK CF=0
+        ;            =1: ER CF=1
+        ;            =2: BREAK CF=1
+
+QRDI:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D2H                                                   ; "R"
+        LD      E,0CCH                                                   ; "L"
+        LD      BC,80H
+        LD      HL,IBUFE
+RD1:    CALL    MOTOR
+        JP      C,RTP6
+        CALL    TMARK
+        JP      C,RTP6
+        CALL    RTAPE
+        JP      RTP4
+
+        ;    READ DATA (FROM $CMT)
+        ;    EXIT SAME UP
+
+QRDD:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D2H                                                   ; "R"
+        LD      E,53H                                                    ; "S"
+        LD      BC,(SIZE)
+        LD      HL,(DTADR)
+        LD      A,B
+        OR      C
+        JP      Z,RTP4
+        JR      RD1
+
+        ;    READ TAPE
+        ;    IN  BC=SIZE
+        ;        DE=LOAD ADDRESS
+        ;    EXIT ACC=0 : OK CF=0
+        ;            =1 : ER   =1
+        ;            =2 : BREAK=1
+ 
+RTAPE:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      H,02H                                                    ; TWICE WRITE
+RTP1:   LD      BC,KEYPB
+        LD      DE,CSTR
+RTP2:   CALL    EDGE                                                     ; 1-->0 EDGE DETECT
+        JR      C,RTP6
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)                                                   ; DATA (1 BIT) READ
+        AND     20H
+        JP      Z,RTP2
+        LD      D,H
+        LD      HL,0
+        LD      (SUMDT),HL
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+RTP3:   CALL    RBYTE                                                    ; 1 BYTE READ
+        JR      C,RTP6
+        LD      (HL),A
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,RTP3
+        LD      HL,(SUMDT)                                               ; CHECK SUM
+        CALL    RBYTE                                                    ; CHECK SUM DATA
+        JR      C,RTP6
+        LD      E,A
+        CALL    RBYTE                                                    ; CHECK SUM DATA
+        JR      C,RTP6
+        CP      L
+        JR      NZ,RTP5
+        LD      A,E
+        CP      H
+        JR      NZ,RTP5
+RTP8:   XOR     A
+RTP4:
+RET2:   POP     HL
+        POP     BC
+        POP     DE
+        CALL    MSTOP
+        PUSH    AF
+        LD      A,(TIMFG)                                                ; INT. CHECK
+        CP      0F0H
+        JR      NZ,L0563
+        EI      
+L0563:  POP     AF
+        RET     
+
+RTP5:   DEC     D
+        JR      Z,RTP7
+        LD      H,D
+        CALL    GAPCK
+        JR      RTP1
+
+RTP7:   LD      A,01H
+        JR      RTP9
+
+RTP6:   LD      A,02H
+RTP9:   SCF     
+        JR      RTP4
+
+        ;    BELL
+
+QBEL:   PUSH    DE
+        LD      DE,QBELD
+        RST     30H                                                      ; CALL MELODY
+        POP     DE
+        RET     
+
+        ;    FLASHING AND KEYIN
+        ;    EXIT: ACC INPUT KEY DATA (DSP.CODE)
+        ;    H=F0H THEN NO KEYIN (Z FLAG)
+
+FLKEY:  CALL    QFLAS
+        CALL    QKEY
+        CP      0F0H
+        RET     
+
+        NOP     
+
+        ;    VERIFY (FROM $CMT)
+        ;    EXIT ACC=0 : OK CF=0
+        ;            =1 : ER CF=1
+        ;            =2 : BREAK CF=1
+
+QVRFY:  DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      BC,(SIZE)
+        LD      HL,(DTADR)
+        LD      D,0D2H                                                   ; "R"
+        LD      E,53H                                                    ; "S"
+        LD      A,B
+        OR      C
+        JR      Z,RTP4                                                   ; END
+        CALL    CKSUM
+        CALL    MOTOR
+        JR      C,RTP6                                                   ; BRK
+        CALL    TMARK                                                    ; TAPE MARK DETECT
+        JR      C,RTP6                                                   ; BRK
+        CALL    TVRFY
+        JR      RTP4
+
+        ;    DATA VERIFY
+        ;    BC=SIZE
+        ;    HL=DATA LOW ADDRESS
+        ;    CSMDT=CHECK SUM
+        ;    EXIT ACC=0 : OK  CF=0
+        ;            =1 : ER    =1
+        ;            =2 : BREAK =1
+
+TVRFY:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      H,02H                                                    ; COMPARE TWICE
+TVF1:   LD      BC,KEYPB
+        LD      DE,CSTR
+TVF2:   CALL    EDGE
+        JP      C,RTP6                                                   ; BRK
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JP      Z,TVF2
+        LD      D,H
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+        ;    COMPARE TAPE DATA AND STORAGE
+TVF3:   CALL    RBYTE
+        JR      C,RTP6                                                   ; BRK
+        CP      (HL)
+        JR      NZ,RTP7                                                  ; ERROR, NOT EQUAL
+        INC     HL                                                       ; STORAGE ADDRESS + 1
+        DEC     BC                                                       ; SIZE - 1
+        LD      A,B
+        OR      C
+        JR      NZ,TVF3
+        ;    COMPARE CHECK SUM (1199H/CSMDT) AND TAPE
+        LD      HL,(CSMDT)
+        CALL    RBYTE
+        CP      H
+        JR      NZ,RTP7                                                  ; ERROR, NOT EQUAL
+        CALL    RBYTE
+        CP      L
+        JR      NZ,RTP7                                                  ; ERROR, NOT EQUAL
+        DEC     D                                                        ; NUMBER OF COMPARES (2) - 1
+        JP      Z,RTP8                                                   ; OK, 2 COMPARES
+        LD      H,D                                                      ; (-->05C7H), SAVE NUMBER OF COMPARES
+        JR      TVF1                                                     ; NEXT COMPARE
+
+        ;    FLASHING DATA LOAD
+
+QLOAD:  PUSH    AF
+        LD      A,(FLASH)
+        CALL    QPONT
+        LD      (HL),A
+        POP     AF
+        RET     
+
+        ;    NEW LINE AND PRINT HL REG (ASCII)
+
+NLPHL:  CALL    NL
+        CALL    PRTHL
+        RET     
+
+        ;    EDGE (TAPE DATA EDGE DETECT)
+        ;    BC=KEYPB (E001H)
+        ;    DE=CSTR  (E002H)
+        ;    EXIT CF=0 OK   CF=1 BREAK
+
+EDGE:   LD      A,0F8H                                                   ; BREAK KEY IN (88H WOULD BE BETTER!!) 
+        LD      (KEYPA),A
+        NOP     
+EDG1:   LD      A,(BC)
+        AND     81H                                                      ; SHIFT & BREAK
+        JR      NZ,L060E
+        SCF     
+        RET     
+
+L060E:  LD      A,(DE)
+        AND     20H
+        JR      NZ,EDG1                                                  ; CSTR D5 = 0
+EDG2:   LD      A,(BC)                                                   ; 8
+        AND     81H                                                      ; 9
+        JR      NZ,L061A                                                 ; 10/14
+        SCF     
+        RET     
+
+L061A:  LD      A,(DE)                                                   ; 8
+        AND     20H                                                      ; 9
+        JR      Z,EDG2                                                   ; CSTR D5 = 1  10/14
+        RET                                                              ; 11
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        ;    1 BYTE READ
+        ;    EXIT SUMDT=STORE
+        ;    CF=1 : BREAK
+        ;    CF=0 : DATA=ACC
+
+RBYTE:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,0800H                                                 ; 8 BITS
+        LD      BC,KEYPB                                                 ; KEY DATA E001H
+        LD      DE,CSTR                                                  ; $TAPE DATA E002H
+RBY1:   CALL    EDGE                                                     ; 41 OR 101
+        JP      C,RBY3                                                   ; 13 (SHIFT & BREAK)
+        CALL    DLY3                                                     ; 20+18*63+33
+        LD      A,(DE)                                                   ; DATA READ :8
+        AND     20H
+        JP      Z,RBY2                                                   ; 0
+        PUSH    HL
+        LD      HL,(SUMDT)
+        INC     HL                                                       ; CHECK SUM                                ; COUNT HIGH BITS ON TAPE
+        LD      (SUMDT),HL
+        POP     HL
+        SCF     
+RBY2:   LD      A,L                                                      ; BUILD CHAR
+        RLA     
+        LD      L,A
+        DEC     H                                                        ; BITCOUNT-1
+        JP      NZ,RBY1
+        CALL    EDGE
+        LD      A,L                                                      ; CHAR READ
+RBY3:   POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+
+        ;    TAPE MARK DETECT
+        ;    E=@L@ : INFORMATION
+        ;     =@S@ : DATA
+        ;    EXIT CF=0 OK
+        ;           =1 BREAK
+
+TMARK:  CALL    GAPCK
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,2828H
+        LD      A,E
+        CP      0CCH                                                     ; "L"
+        JR      Z,L066C
+        LD      HL,1414H
+L066C:  LD      (TMCNT),HL
+        LD      BC,KEYPB
+        LD      DE,CSTR
+TM1:    LD      HL,(TMCNT)
+TM2:    CALL    EDGE
+        JR      C,TM4
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JR      Z,TM1
+        DEC     H
+        JR      NZ,TM2
+TM3:    CALL    EDGE
+        JR      C,TM4
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JR      NZ,TM1
+        DEC     L
+        JR      NZ,TM3
+        CALL    EDGE
+TM4:
+RET3:   POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+        ;    MOTOR ON
+        ;    IN  D=@W@ :WRITE
+        ;         =@R@ :READ
+        ;    EXIT CF=0 OK
+        ;           =1 BREAK
+        ;
+        ; If the button is pressed, 
+
+MOTOR:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      B,0AH                                                    ; Pulse motor upto 10 times if sense is low. Each pulse flips on->off or off->on
+MOT1:   LD      A,(CSTR)                                                 ; Check sense, if low then pulse motor to switch it on.
+        AND     10H
+        JR      Z,MOT4                                                   ; If NZ (bit PC4 is high), then wait a bit and return, motor running.
+                                                                         ; If Z then pulse the motor on circuit.
+MOT2:   LD      B,0FFH                                                   ; 2 SEC DELAY 
+L06AD:  CALL    DLY12                                                    ; 7 MSEC DELAY
+        JR      L06B4                                                    ; MOTOR ENTRY ADJUST
+
+        JR      MOTOR                                                    ; ORG 06B2H
+
+L06B4:  DJNZ    L06AD
+        XOR     A
+MOT7:   JR      RET3
+
+MOT4:   LD      A,06H                                                    ;  
+        LD      HL,CSTPT                                                 ; 8255 Control register
+        LD      (HL),A                                                   ; Set PC3 low
+        INC     A
+        LD      (HL),A                                                   ; Set PC3 high
+        DJNZ    MOT1                                                     ; Check to see if sense now active.
+        CALL    NL                                                       ; Sense not active so play button hasnt been pressed.
+        LD      A,D                                                      ; Determine if we are Loading or Saving, display correct message.
+        CP      0D7H                                                     ; "W"
+        JR      Z,MOT8
+        LD      DE,MSGN1                                                 ; PLAY MARK
+        JR      MOT9
+
+MOT8:   LD      DE,MSGN3                                                 ; "RECORD."
+        RST     18H                                                      ; CALL MSGX
+        LD      DE,MSGN2                                                 ; "PLAY"
+MOT9:   RST     18H                                                      ; CALL MSGX
+MOT5:   LD      A,(CSTR)                                                 ; Check sense input and wait until it is high.
+        AND     10H
+        JR      NZ,MOT2
+        CALL    QBRK                                                     ; If sense is low, check for User Key Break entry.
+        JR      NZ,MOT5
+        SCF     
+        JR      MOT7   
+
+        ;    INITIAL MESSAGE
+
+MSGQ3:    DB    "**  MONITOR 1Z-013A  **\r"
+    NOP
+
+        ;    MOTOR STOP
+
+MSTOP:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        LD      B,0AH
+MST1:   LD      A,(CSTR)
+        AND     10H
+        JR      Z,MST3
+        LD      A,06H
+        LD      (CSTPT),A
+        INC     A
+        LD      (CSTPT),A
+        DJNZ    MST1
+MST3:   JP      QRSTR1
+
+        ;    CHECK SUM
+        ;    IN   BC=SIZE
+        ;         HL=DATA ADDRESS
+        ;    EXIT SUMDT=STORE
+        ;         CSMDT=STORE
+
+CKSUM:  PUSH    BC
+        PUSH    DE
+L071C:  PUSH    HL
+        LD      DE,0
+CKS1:   LD      A,B
+        OR      C
+        JR      NZ,CKS2
+        EX      DE,HL
+L0725:  LD      (SUMDT),HL                                               ; NUMBER OF HIGHBITS IN DATA
+        LD      (CSMDT),HL
+        POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+CKS2:   LD      A,(HL)
+        PUSH    BC
+        LD      B,8
+CKS3:   RLCA    
+        JR      NC,L0737
+        INC     DE
+L0737:  DJNZ    CKS3
+L0739:  POP     BC
+        INC     HL
+        DEC     BC
+        JR      CKS1
+
+        ;    MODE SET OF KEYPORT
+
+QMODE:  LD      HL,KEYPF
+        LD      (HL),8AH                                                 ; 10001010 CTRL WORD MODE0
+        LD      (HL),07H                                                 ; PC3=1 M-ON
+        LD      (HL),05H                                                 ; PC2=1 INTMSK
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    107 MICRO SEC DELAY
+
+DLY1:   LD      A,15H                                                    ; 18*21+20
+L075B:  DEC     A
+        JP      NZ,L075B
+        RET     
+
+DLY2:   LD      A,13H                                                    ; 18*19+20
+L0762:  DEC     A
+        JP      NZ,L0762
+        RET     
+
+        ;    1 BYTE WRITE
+
+WBYTE:  PUSH    BC
+        LD      B,8
+        CALL    LONG
+WBY1:   RLCA    
+        CALL    C,LONG
+        CALL    NC,SHORT
+        DEC     B
+        JP      NZ,WBY1
+        POP     BC
+        RET     
+
+        ;    GAP + TAPEMARK
+        ;    E=@L@ LONG GAP
+        ;     =@s@ SHORT GAP
+
+GAP:    PUSH    BC
+        PUSH    DE
+        LD      A,E
+        LD      BC,55F0H
+        LD      DE,2828H
+        CP      0CCH                                                     ; "L"
+        JP      Z,GAP1
+        LD      BC,2AF8H
+        LD      DE,1414H
+GAP1:   CALL    SHORT
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,GAP1
+GAP2:   CALL    LONG
+        DEC     D
+        JR      NZ,GAP2
+GAP3:   CALL    SHORT
+        DEC     E
+        JR      NZ,GAP3
+        CALL    LONG
+        POP     DE
+        POP     BC
+        RET     
+
+        ;    MEMORY CORRECTION
+        ;    COMMAND "M"
+
+MCOR:   CALL    HEXIY                                                    ; CORRECTION ADDRESS
+MCR1:   CALL    NLPHL                                                    ; CORRECTION ADDRESS PRINT
+        CALL    SPHEX                                                    ; ACC-->ASCII DISP.
+        CALL    QPRTS                                                    ; SPACE PRINT
+        CALL    BGETL                                                    ; GET DATA & CHECK DATA
+        CALL    HLHEX                                                    ; HL<--ASCII(DE)
+        JR      C,MCR3
+        CALL    P4DE                                                     ; (INC DE)*4
+        INC     DE
+        CALL    L2HEX                                                    ; DATA CHECK
+        JR      C,MCR1
+        CP      (HL)
+        JR      NZ,MCR1
+        INC     DE
+        LD      A,(DE)
+        CP      0DH                                                      ; NOT CORRECTION ?
+        JR      Z,MCR2
+        CALL    L2HEX                                                    ; ACC<--HL(ASCII)
+        JR      C,MCR1
+        LD      (HL),A                                                   ; DATA CORRECT
+MCR2:   INC     HL
+        JR      MCR1
+
+MCR3:   LD      H,B                                                      ; MEMORY ADDRESS
+        LD      L,C
+        JR      MCR1
+
+    DB    "(HL)"
+    DB    0F1H
+    DB    9EH
+    DB    "SUB ("
+
+        ;    GET 1 LINE STATEMENT *
+        ;    DE=DATA STORE LOW ADDRESS
+        ;    (END=CR)
+
+QGETL:  PUSH    AF
+        PUSH    BC
+        PUSH    HL
+        PUSH    DE
+GETL1:  CALL    QQKEY                                                    ; ENTRY KEY
+AUTO3:  PUSH    AF                                                       ; IN KEY DATA SAVE
+        LD      B,A
+        LD      A,(SWRK)                                                 ; BELL WORK
+        RRCA    
+        CALL    NC,QBEL                                                  ; ENTRY BELL
+        LD      A,B
+        LD      HL,KANAF                                                 ; KANA & GRAPH FLAGS
+        AND     0F0H
+        CP      0C0H
+        POP     DE                                                       ; EREG=FLAGREG
+        LD      A,B
+        JR      NZ,GETL2                                                 ; NOT C0H
+        CP      0CDH                                                     ; CR
+        JR      Z,GETL3
+        CP      0CBH                                                     ; BREAK
+        JP      Z,GETLC
+        CP      0CFH                                                     ; NIKO MARK WH.
+        JR      Z,GETL2
+        CP      0C7H                                                     ; CRT EDITION
+        JR      NC,GETL5                                                 ; <=C7H
+        RR      E                                                        ; >C7H & CFLAG, CY ? GRAPHIC MODE,CURS.DISPL.
+        LD      A,B
+        JR      NC,GETL5
+GETL2:  CALL    QDSP                                                     ; DISPL.
+        JR      GETL1
+
+GETL5:  CALL    QDPCT                                                    ; CRT CONTROL
+        JR      GETL1
+
+        ;    BREAK IN
+
+GETLC:  POP     HL
+        PUSH    HL
+        LD      (HL),1BH                                                 ; BREAK CODE
+        INC     HL
+        LD      (HL),0DH
+        JR      GETLR
+
+        ;    GETLA
+
+GETLA:  RRCA                                                             ; CY<--D7
+        JR      NC,GETL6
+        JR      GETLB
+
+        ;    DELAY 7 MSEC AND SWEP
+
+DSWEP:  CALL    DLY12
+        CALL    QSWEP
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+GETL3:  CALL    PMANG                                                    ; CR
+        LD      B,COLW                                                   ; 1 LINE
+        JR      NC,GETLA
+        DEC     H                                                        ; BEFORE LINE
+GETLB:  LD      B,COLW*2                                                 ; 2 LINE
+GETL6:  LD      L,0
+        CALL    QPNT1
+        POP     DE                                                       ; STORE TOP ADDRESS
+        PUSH    DE
+GETLZ:  LD      A,(HL)
+        CALL    QDACN
+        LD      (DE),A
+        INC     HL
+        INC     DE
+        DJNZ    GETLZ
+        EX      DE,HL
+GETLU:  LD      (HL),0DH
+        DEC     HL
+        LD      A,(HL)
+        CP      20H                                                      ; SPACE THEN CR
+
+        ;    CR AND NEW LINE
+
+        JR      Z,GETLU
+
+        ;    NEW LINE RETURN
+
+GETLR:  CALL    QLTNL
+        POP     DE
+        POP     HL
+        POP     BC
+        POP     AF
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    MESSAGE PRINT
+        ;    DE PRINT DATA LOW ADDRESS
+        ;    END=CR
+
+QMSG:   PUSH    AF
+        PUSH    BC
+        PUSH    DE
+MSG1:   LD      A,(DE)
+        CP      0DH                                                      ; CR
+        JR      Z,MSGX2
+        CALL    QPRNT
+        INC     DE
+        JR      MSG1
+
+        ;    ALL PRINT MESSAGE
+
+QMSGX:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+MSGX1:  LD      A,(DE)
+        CP      0DH
+MSGX2:  JP      Z,QRSTR1
+        CALL    QADCN
+        CALL    PRNT3
+        INC     DE
+        JR      MSGX1
+
+        ;    TOP OF KEYTBLS
+
+QKYSM:  LD      DE,KTBLS                                                 ; SHIFT ALSO
+        JR      QKY5
+
+        ;    BREAK CODE IN
+
+NBRK:   LD      A,0CBH                                                   ; BREAK CODE
+        OR      A
+        JR      QKY1
+
+        ;    GETKEY
+        ;    NO ECHO BACK
+        ;    EXIT ACC=ASCII CODE
+
+QGET:   CALL    QKEY                                                     ; KEY IN (DISPLAY CODE)
+        SUB     0F0H                                                     ; NOT KEYIN CODE
+        RET     Z
+        ADD     A,0F0H
+        JP      QDACN                                                    ; DISPLAY TO ASCII CODE
+
+        NOP     
+        NOP     
+
+        ;    1 KEY INPUT
+        ;    IN   B=KEY MODE (SHIFT, CTRL, BREAK)
+        ;         C=KEY DATA (COLUMN & ROW)
+        ;    EXIT ACC=DISPLAY CODE
+        ;         IF NO KEY  ACC=F0H
+        ;         IF CY=1 THEN ATTRIBUTE ON
+        ;                      (SMALL, HIRAKANA)
+
+QKEY:   PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        CALL    DSWEP                                                    ; DELAY AND KEY SWEP
+        LD      A,B
+        RLCA    
+        JR      C,QKY2
+        LD      A,0F0H                                                   ; SHIFT OR CTRL HERE
+QKY1:   POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+QKY2:   LD      DE,KTBL                                                  ; NORMAL KEY TABLE
+        LD      A,B
+        CP      88H                                                      ; BREAK IN (SHIFT & BRK)
+        JR      Z,NBRK
+        LD      H,0                                                      ; HL=ROW & COLUMN
+        LD      L,C
+        BIT     5,A                                                      ; CTRL CHECK
+        JR      NZ,L08F7                                                 ; YES, CTRL
+        LD      A,(KANAF)                                                ; 0=NR., 1=GRAPH
+        RRCA    
+        JP      C,QKYGRP                                                 ; GRAPH MODE
+        LD      A,B                                                      ; CTRL KEY CHECK
+        RLA     
+        RLA     
+        JR      C,QKYSM
+        JR      QKY5
+
+L08F7:  LD      DE,KTBLC                                                 ; CONTROL KEY TABLE
+QKY5:   ADD     HL,DE                                                    ; TABLE
+QKY55:  LD      A,(HL)
+        JR      QKY1
+
+QKYGRP: BIT     6,B
+        JR      Z,QKYGRS
+        LD      DE,KTBLG
+        ADD     HL,DE
+        SCF     
+        JR      QKY55
+
+QKYGRS: LD      DE,KTBLGS
+        JR      QKY5
+
+        ;    NEWLINE
+
+QLTNL:  XOR     A
+        LD      (DPRNT),A                                                ; ROW POINTER
+        LD      A,0CDH                                                   ; CR
+        JR      PRNT5
+
+        NOP     
+        NOP     
+
+QNL:    LD      A,(DPRNT)
+        OR      A
+        RET     Z
+        JR      QLTNL
+
+        NOP     
+
+        ;    PRINT SPACE
+
+QPRTS:  LD      A,20H
+        JR      QPRNT
+
+        ;    PRINT TAB
+
+QPRTT:  CALL    PRNTS
+        LD      A,(DPRNT)
+        OR      A
+        RET     Z
+L092C:  SUB     10
+        JR      C,QPRTT
+        JR      NZ,L092C
+        NOP     
+        NOP     
+        NOP     
+
+        ;    PRINT
+        ;    IN ACC=PRINT DATA (ASCII)
+
+QPRNT:  CP      0DH                                                      ; CR
+        JR      Z,QLTNL
+        PUSH    BC
+        LD      C,A
+        LD      B,A
+        CALL    QPRT
+        LD      A,B
+        POP     BC
+        RET     
+
+MSGOK:    DB    "OK!\r"
+
+        ;    PRINT ROUTINE
+        ;    1 CHARACTER
+        ;    INPUT:C=ASCII DATA (QDSP+QDPCT)
+
+QPRT:    LD    A,C 
+        CALL    QADCN                                                    ; ASCII TO DSPLAY
+        LD      C,A
+        CP      0F0H
+        RET     Z                                                        ; ZERO=ILLEGAL DATA
+        AND     0F0H                                                     ; MSD CHECK
+        CP      0C0H
+        LD      A,C
+        JR      NZ,PRNT3
+        CP      0C7H
+        JR      NC,PRNT3                                                 ; CRT EDITOR
+PRNT5:  CALL    QDPCT
+        CP      0C3H                                                     ; "->"
+        JR      Z,PRNT4
+        CP      0C5H                                                     ; HOME
+        JR      Z,PRNT2
+        CP      0C6H                                                     ; CLR
+        RET     NZ
+PRNT2:  XOR     A
+L0968:  LD      (DPRNT),A
+        RET     
+
+PRNT3:  CALL    QDSP
+PRNT4:  LD      A,(DPRNT)                                                ; TAB POINT+1
+        INC     A
+        CP      COLW*2
+        JR      C,L0968
+        SUB     COLW*2
+        JR      L0968
+
+        ;    FLASHING BYPASS 1
+
+FLAS1:  LD      A,(FLASH)
+        JR      FLAS2
+
+        ;    BREAK SUBROUTINE BYPASS 1
+        ;    CTRL OR NOT KEY
+
+QBRK2:  BIT     5,A                                                      ; NOT OR CTRL
+        JR      Z,QBRK3                                                  ; CTRL
+        OR      A                                                        ; NOTKEY A=7FH
+        RET     
+
+QBRK3:  LD      A,20H                                                    ; CTRL D5=1
+        OR      A                                                        ; ZERO FLG CLR
+        SCF     
+        RET     
+
+MSGSV:    DB    "FILENAME? "
+    DB    0DH
+
+        ;    DLY 7 MSEC
+DLY12:  PUSH    BC
+        LD      B,15H
+L0999:  CALL    DLY3
+        DJNZ    L0999
+        POP     BC
+        RET     
+
+        ;    LOADING MESSAGE
+
+MSGQ2:    DB    "LOADING \r"
+
+        ;    DELAY FOR LONG PULSE
+
+DLY4:   LD      A,59H                                                    ; 18*89+20
+L09AB:  DEC     A
+        JP      NZ,L09AB
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+
+        ;    KEY BOARD SEARCH
+        ;    & DISPLAY CODE CONVERSION
+        ;    EXIT A=DISPLAY CODE
+        ;         CY=GRAPH MODE
+        ;    WITH CURSOR DISPLAY
+
+QQKEY:  PUSH    HL
+        CALL    QSAVE
+KSL1:   CALL    FLKEY                                                    ; KEY
+        JR      NZ,KSL1                                                  ; KEY IN THEN JUMP
+KSL2:   CALL    FLKEY
+        JR      Z,KSL2                                                   ; NOT KEY IN THEN JUMP
+        LD      H,A
+        CALL    DLY12                                                    ; DELAY CHATTER
+        CALL    QKEY
+        PUSH    AF
+        CP      H                                                        ; CHATTER CHECK
+        POP     HL
+        JR      NZ,KSL2
+        PUSH    HL
+        POP     AF                                                       ; IN KEY DATA
+        CALL    QLOAD                                                    ; FLASHING DATA LOAD
+        POP     HL
+        RET     
+
+        ;    CLEAR 2
+
+NCLR08: XOR     A                                                        ; CY FLAG
+NCLR8:  LD      BC,0800H
+CLEAR:  PUSH    DE                                                       ; BC=CLR BYTE SIZE, A=CLR DATA
+        LD      D,A
+CLEAR1: LD      (HL),D
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,CLEAR1
+        POP     DE
+        RET     
+
+        ;    FLASHING 2
+
+QFLS:   PUSH    AF
+        PUSH    HL
+        LD      A,(KEYPC)
+        RLCA    
+        RLCA    
+        JR      C,FLAS1
+        LD      A,(FLSDT)
+FLAS2:  CALL    QPONT                                                    ; DISPLAY POSITION
+        LD      (HL),A
+        POP     HL
+        POP     AF
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+QFLAS:  JR      QFLS
+
+        ;    SHORT AND LONG PULSE FOR 1 BIT WRITE
+
+SHORT:  PUSH    AF                                                       ; 12
+        LD      A,03H                                                    ; 9
+        LD      (CSTPT),A                                                ; E003H PC3=1:16
+        CALL    DLY1                                                     ; 20+18*21+20
+        CALL    DLY1                                                     ; 20+18*21+20
+        LD      A,02H                                                    ; 9
+        LD      (CSTPT),A                                                ; E003H PC3=0:16
+        CALL    DLY1                                                     ; 20+18*21+20
+        CALL    DLY1                                                     ; 20+18*21+20
+        POP     AF                                                       ; 11
+        RET                                                              ; 11
+
+LONG:   PUSH    AF                                                       ; 11
+        LD      A,03H                                                    ; 9
+        LD      (CSTPT),A                                                ; 16
+        CALL    DLY4                                                     ; 20+18*89+20
+        LD      A,02H                                                    ; 9
+        LD      (CSTPT),A                                                ; 16
+        CALL    DLY4                                                     ; 20+18*89+20
+        POP     AF                                                       ; 11
+        RET                                                              ; 11
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    BREAK KEY CHECK
+        ;    AND SHIFT, CTRL KEY CHECK
+        ;    EXIT BREAK ON : ZERO=1
+        ;               OFF: ZERO=0
+        ;         NO KEY   : CY  =0
+        ;         KEY IN   : CY  =1
+        ;          A D6=1  : SHIFT ON
+        ;              =0  :       OFF
+        ;            D5=1  : CTRL ON
+        ;              =0  :      OFF
+        ;        D4=1  : SHIFT+CNT ON
+        ;          =0  :           OFF
+
+QBRK:   LD      A,0F8H                                                   ; LINE 8SWEEP
+        LD      (KEYPA),A
+        NOP     
+        LD      A,(KEYPB)
+        OR      A
+        RRA     
+        JP      C,QBRK2                                                  ; SHIFT ?
+        RLA     
+        RLA     
+        JR      NC,QBRK1                                                 ; BREAK ?
+        LD      A,40H                                                    ; SHIFT D6=1
+        SCF     
+        RET     
+
+QBRK1:  XOR     A                                                        ; SHIFT ?
+        RET     
+
+        ;    320 U SEC DELAY
+
+DLY3:   LD      A,3FH                                                    ; 18*63+33
+        JP      L0762                                                    ; JP DLY2+2
+
+        NOP     
+
+        ;    KEY BOARD SWEEP
+        ;    EXIT B,D7=0  NO DATA
+        ;             =1  DATA
+        ;           D6=0  SHIFT OFF
+        ;         =1  SHIFT ON
+        ;           D5=0  CTRL OFF
+        ;         =1  CTRL ON
+        ;           D4=0  SHIFT+CTRL OFF
+        ;         =1  SHIFT+CTRL ON
+        ;         C   = ROW & COLUMN
+        ;        7 6 5 4 3 2 1 0
+        ;        * * ^ ^ ^ < < <
+
+QSWEP:  PUSH    DE
+        PUSH    HL
+        XOR     A
+        LD      B,0F8H
+        LD      D,A
+        CALL    QBRK
+        JR      NZ,SWEP6
+        LD      D,88H                                                    ; BREAK ON
+        JR      SWEP9
+
+SWEP6:  JR      NC,SWEP0
+        LD      D,A
+        JR      SWEP0
+
+SWEP01: SET     7,D
+SWEP0:  DEC     B
+        LD      A,B
+        LD      (KEYPA),A
+        CP      0EFH                                                     ; MAP SWEEP END ?
+        JR      NZ,SWEP3
+        CP      0F8H                                                     ; BREAK KEY ROW
+        JR      Z,SWEP0
+SWEP9:  LD      B,D
+        POP     HL
+        POP     DE
+        RET     
+
+SWEP3:  LD      A,(KEYPB)
+        CPL     
+        OR      A
+        JR      Z,SWEP0
+        LD      E,A
+SWEP2:  LD      H,8
+        LD      A,B
+        AND     0FH
+        RLCA    
+        RLCA    
+        RLCA    
+        LD      C,A
+        LD      A,E
+L0A89:  DEC     H
+        RRCA    
+        JR      NC,L0A89
+        LD      A,H
+        ADD     A,C
+        LD      C,A
+        JR      SWEP01
+        ;
+        ;
+        ;   ASCII TO DISPLAY CODE TABL
+        ;
+ATBL:    
+        ;  00 - 0F
+    DB    0F0H                                                           ; ^ @
+    DB    0F0H                                                           ; ^ A
+    DB    0F0H                                                           ; ^ B
+    DB    0F3H                                                           ; ^ C
+    DB    0F0H                                                           ; ^ D
+    DB    0F5H                                                           ; ^ E
+    DB    0F0H                                                           ; ^ F
+    DB    0F0H                                                           ; ^ G
+    DB    0F0H                                                           ; ^ H
+    DB    0F0H                                                           ; ^ I
+    DB    0F0H                                                           ; ^ J
+    DB    0F0H                                                           ; ^ K
+    DB    0F0H                                                           ; ^ L
+    DB    0F0H                                                           ; ^ M
+    DB    0F0H                                                           ; ^ N
+    DB    0F0H                                                           ; ^ O
+        ;  10 - 1F
+    DB    0F0H                                                           ; ^ P
+    DB    0C1H                                                           ; ^ Q CUR. DOWN
+    DB    0C2H                                                           ; ^ R CUR. UP
+    DB    0C3H                                                           ; ^ S CUR. RIGHT
+    DB    0C4H                                                           ; ^ T CUR. LEFT
+    DB    0C5H                                                           ; ^ U HOME
+    DB    0C6H                                                           ; ^ V CLEAR
+    DB    0F0H                                                           ; ^ W
+    DB    0F0H                                                           ; ^ X
+    DB    0F0H                                                           ; ^ Y
+    DB    0F0H                                                           ; ^ Z SEP.
+    DB    0F0H                                                           ; ^ [
+    DB    0F0H                                                           ; ^ \
+    DB    0F0H                                                           ; ^ ]
+    DB    0F0H                                                           ; ^ ^
+    DB    0F0H                                                           ; ^ -
+        ;  20 - 2F
+    DB    00H                                                            ; SPACE
+    DB    61H                                                            ; !
+    DB    62H                                                            ; "
+    DB    63H                                                            ; #
+    DB    64H                                                            ; $
+    DB    65H                                                            ; %
+    DB    66H                                                            ; &
+    DB    67H                                                            ; '
+    DB    68H                                                            ; (
+    DB    69H                                                            ; )
+    DB    6BH                                                            ; *
+    DB    6AH                                                            ; +
+    DB    2FH                                                            ; ,
+    DB    2AH                                                            ; -
+    DB    2EH                                                            ; .
+    DB    2DH                                                            ; /
+        ;  30 - 3F
+    DB    20H                                                            ; 0
+    DB    21H                                                            ; 1
+    DB    22H                                                            ; 2
+    DB    23H                                                            ; 3
+    DB    24H                                                            ; 4
+    DB    25H                                                            ; 5
+    DB    26H                                                            ; 6
+    DB    27H                                                            ; 7
+    DB    28H                                                            ; 8
+    DB    29H                                                            ; 9
+    DB    4FH                                                            ; :
+    DB    2CH                                                            ;         ;
+    DB    51H                                                            ; <
+    DB    2BH                                                            ; =
+    DB    57H                                                            ; >
+    DB    49H                                                            ; ?
+        ;  40 - 4F
+    DB    55H                                                            ; @
+    DB    01H                                                            ; A
+    DB    02H                                                            ; B
+    DB    03H                                                            ; C
+    DB    04H                                                            ; D
+    DB    05H                                                            ; E
+    DB    06H                                                            ; F
+    DB    07H                                                            ; G
+    DB    08H                                                            ; H
+    DB    09H                                                            ; I
+    DB    0AH                                                            ; J
+    DB    0BH                                                            ; K
+    DB    0CH                                                            ; L
+    DB    0DH                                                            ; M
+    DB    0EH                                                            ; N
+    DB    0FH                                                            ; O
+        ;  50 - 5F
+    DB    10H                                                            ; P
+    DB    11H                                                            ; Q
+    DB    12H                                                            ; R
+    DB    13H                                                            ; S
+    DB    14H                                                            ; T
+    DB    15H                                                            ; U
+    DB    16H                                                            ; V
+    DB    17H                                                            ; W
+    DB    18H                                                            ; X
+    DB    19H                                                            ; Y
+    DB    1AH                                                            ; Z
+    DB    52H                                                            ; [
+    DB    59H                                                            ; \
+    DB    54H                                                            ; ]
+    DB    50H                                                            ; 
+    DB    45H                                                            ; 
+        ;  60 - 6F
+    DB    0C7H                                                           ; UFO
+    DB    0C8H
+    DB    0C9H
+    DB    0CAH
+    DB    0CBH
+    DB    0CCH
+    DB    0CDH
+    DB    0CEH
+    DB    0CFH
+    DB    0DFH
+    DB    0E7H
+    DB    0E8H
+    DB    0E5H
+    DB    0E9H
+    DB    0ECH
+    DB    0EDH
+        ;  70 - 7F
+    DB    0D0H
+    DB    0D1H
+    DB    0D2H
+    DB    0D3H
+    DB    0D4H
+    DB    0D5H
+    DB    0D6H
+    DB    0D7H
+    DB    0D8H
+    DB    0D9H
+    DB    0DAH
+    DB    0DBH
+    DB    0DCH
+    DB    0DDH
+    DB    0DEH
+    DB    0C0H
+        ;  80 - 8F
+    DB    80H                                                            ; }
+    DB    0BDH
+    DB    9DH
+    DB    0B1H
+    DB    0B5H
+    DB    0B9H
+    DB    0B4H
+    DB    9EH
+    DB    0B2H
+    DB    0B6H
+    DB    0BAH
+    DB    0BEH
+    DB    9FH
+    DB    0B3H
+    DB    0B7H
+    DB    0BBH
+        ;  90 - 9F
+    DB    0BFH                                                           ; _
+    DB    0A3H
+    DB    85H
+    DB    0A4H                                                           ; `
+    DB    0A5H                                                           ; ~
+    DB    0A6H
+    DB    94H
+    DB    87H
+    DB    88H
+    DB    9CH
+    DB    82H
+    DB    98H
+    DB    84H
+    DB    92H
+    DB    90H
+    DB    83H
+        ;  A0 - AF
+    DB    91H
+    DB    81H
+    DB    9AH
+    DB    97H
+    DB    93H
+    DB    95H
+    DB    89H
+    DB    0A1H
+    DB    0AFH
+    DB    8BH
+    DB    86H
+    DB    96H
+    DB    0A2H
+    DB    0ABH
+    DB    0AAH
+    DB    8AH
+        ;  B0 - BF
+    DB    8EH
+    DB    0B0H
+    DB    0ADH
+    DB    8DH
+    DB    0A7H
+    DB    0A8H
+    DB    0A9H
+    DB    8FH
+    DB    8CH
+    DB    0AEH
+    DB    0ACH
+    DB    9BH
+    DB    0A0H
+    DB    99H
+    DB    0BCH                                                           ; {
+    DB    0B8H
+        ;  C0 - CF
+    DB    40H
+    DB    3BH
+    DB    3AH
+    DB    70H
+    DB    3CH
+    DB    71H
+    DB    5AH
+    DB    3DH
+    DB    43H
+    DB    56H
+    DB    3FH
+    DB    1EH
+    DB    4AH
+    DB    1CH
+    DB    5DH
+    DB    3EH
+        ;  D0 - DF
+    DB    5CH
+    DB    1FH
+    DB    5FH
+    DB    5EH
+    DB    37H
+    DB    7BH
+    DB    7FH
+    DB    36H
+    DB    7AH
+    DB    7EH
+    DB    33H
+    DB    4BH
+    DB    4CH
+    DB    1DH
+    DB    6CH
+    DB    5BH
+        ;  E0 - EF
+    DB    78H
+    DB    41H
+    DB    35H
+    DB    34H
+    DB    74H
+    DB    30H
+    DB    38H
+    DB    75H
+    DB    39H
+    DB    4DH
+    DB    6FH
+    DB    6EH
+    DB    32H
+    DB    77H
+    DB    76H
+    DB    72H
+        ;  F0 - FF
+    DB    73H
+    DB    47H
+    DB    7CH
+    DB    53H
+    DB    31H
+    DB    4EH
+    DB    6DH
+    DB    48H
+    DB    46H
+    DB    7DH
+    DB    44H
+    DB    1BH
+    DB    58H
+    DB    79H
+    DB    42H
+    DB    60H
+
+        ;    FLASHING DATA SAVE
+
+QSAVE:  LD      HL,FLSDT
+        LD      (HL),0EFH                                                ; NORMAL CURSOR
+        LD      A,(KANAF)
+        RRCA    
+        JR      C,L0BA0                                                  ; GRAPH MODE
+        RRCA    
+        JR      NC,SV0                                                   ; NORMAL MODE
+L0BA0:  LD      (HL),0FFH                                                ; GRAPH CURSOR
+SV0:    LD      A,(HL)
+        PUSH    AF
+        CALL    QPONT                                                    ; FLASHING POSITION
+        LD      A,(HL)
+        LD      (FLASH),A
+        POP     AF
+        LD      (HL),A
+        XOR     A
+        LD      HL,KEYPA
+L0BB1:  LD      (HL),A
+        CPL                                                              ; OH NO! UNUSED BITS WERE TOUCHED TOO!!!
+        LD      (HL),A
+        RET     
+
+SV1:    LD      (HL),43H                                                 ; KANA CURSOR
+        JR      SV0
+
+        ;    ASCII TO DISPLAY CODE CONVERT
+        ;    IN ACC:ASCII
+        ;    EXIT ACC:DISPLAY CODE
+
+QADCN:  PUSH    BC
+        PUSH    HL
+        LD      HL,ATBL
+        LD      C,A
+        LD      B,0
+        ADD     HL,BC
+        LD      A,(HL)
+        JR      DACN3
+
+VRNS:    DB    "V1.0A\r"                                                 ; VERSION MANAGEMENT
+        NOP     
+        NOP     
+        NOP     
+
+        ;    DISPLAY CODE TO ASCII CONVERSION
+        ;    IN ACC=DISPLAY CODE
+        ;    EXIT ACC=ASCII
+
+QDACN:  PUSH    BC
+        PUSH    HL
+        PUSH    DE
+        LD      HL,ATBL
+        LD      D,H
+        LD      E,L
+        LD      BC,0100H
+        CPIR    
+        JR      Z,DACN1
+        LD      A,0F0H
+DACN2:  POP     DE
+DACN3:  POP     HL
+        POP     BC
+        RET     
+
+DACN1:  OR      A
+        DEC     HL
+        SBC     HL,DE
+        LD      A,L
+        JR      DACN2
+
+        ;
+        ;
+        ;   KEY MATRIX TO DISPLAY CODE TABL
+        ;
+KTBL:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0CAH                                                           ; GRAPH
+    DB    58H                                                            ; 
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    2CH                                                            ;         ;
+    DB    4FH                                                            ; :
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    19H                                                            ; Y
+    DB    1AH                                                            ; Z
+    DB    55H                                                            ; @
+    DB    52H                                                            ; [
+    DB    54H                                                            ; ]
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+        ;S2   10 - 17
+    DB    11H                                                            ; Q
+    DB    12H                                                            ; R
+    DB    13H                                                            ; S
+    DB    14H                                                            ; T
+    DB    15H                                                            ; U
+    DB    16H                                                            ; V
+    DB    17H                                                            ; W
+    DB    18H                                                            ; X
+        ;S3   18 - 1F
+    DB    09H                                                            ; I
+    DB    0AH                                                            ; J
+    DB    0BH                                                            ; K
+    DB    0CH                                                            ; L
+    DB    0DH                                                            ; M
+    DB    0EH                                                            ; N
+    DB    0FH                                                            ; O
+    DB    10H                                                            ; P
+        ;S4   20 - 27
+    DB    01H                                                            ; A
+    DB    02H                                                            ; B
+    DB    03H                                                            ; C
+    DB    04H                                                            ; D
+    DB    05H                                                            ; E
+    DB    06H                                                            ; F
+    DB    07H                                                            ; G
+    DB    08H                                                            ; H
+        ;S5   28 - 2F
+    DB    21H                                                            ; 1
+    DB    22H                                                            ; 2
+    DB    23H                                                            ; 3
+    DB    24H                                                            ; 4
+    DB    25H                                                            ; 5
+    DB    26H                                                            ; 6
+    DB    27H                                                            ; 7
+    DB    28H                                                            ; 8
+        ;S6   30 - 37
+    DB    59H                                                            ; \
+    DB    50H                                                            ; 
+    DB    2AH                                                            ; -
+    DB    00H                                                            ; SPACE
+    DB    20H                                                            ; 0
+    DB    29H                                                            ; 9
+    DB    2FH                                                            ; ,
+    DB    2EH                                                            ; .
+        ;S7   38 - 3F
+    DB    0C8H                                                           ; INST.
+    DB    0C7H                                                           ; DEL.
+    DB    0C2H                                                           ; CURSOR UP
+    DB    0C1H                                                           ; CURSOR DOWN
+    DB    0C3H                                                           ; CURSOR RIGHT
+    DB    0C4H                                                           ; CURSOR LEFT
+    DB    49H                                                            ; ?
+    DB    2DH                                                            ; /
+        ;
+        ;
+        ;   KTBL SHIFT ON
+        ;
+KTBLS:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0CAH                                                           ; GRAPH
+    DB    1BH                                                            ; POND
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    6AH                                                            ; +
+    DB    6BH                                                            ; *
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    99H                                                            ; y
+    DB    9AH                                                            ; z
+    DB    0A4H                                                           ; `
+    DB    0BCH                                                           ; {
+    DB    40H                                                            ; }
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+        ;S2   10 - 17
+    DB    91H                                                            ; q
+    DB    92H                                                            ; r
+    DB    93H                                                            ; s
+    DB    94H                                                            ; t
+    DB    95H                                                            ; u
+    DB    96H                                                            ; v
+    DB    97H                                                            ; w
+    DB    98H                                                            ; x
+        ;S3   18 - 1F
+    DB    89H                                                            ; i
+    DB    8AH                                                            ; j
+    DB    8BH                                                            ; k
+    DB    8CH                                                            ; l
+    DB    8DH                                                            ; m
+    DB    8EH                                                            ; n
+    DB    8FH                                                            ; o
+    DB    90H                                                            ; p
+        ;S4   20 - 27
+    DB    81H                                                            ; a
+    DB    82H                                                            ; b
+    DB    83H                                                            ; c
+    DB    84H                                                            ; d
+    DB    85H                                                            ; e
+    DB    86H                                                            ; f
+    DB    87H                                                            ; g
+    DB    88H                                                            ; h
+        ;S5   28 - 2F
+    DB    61H                                                            ; !
+    DB    62H                                                            ; "
+    DB    63H                                                            ; #
+    DB    64H                                                            ; $
+    DB    65H                                                            ; %
+    DB    66H                                                            ; &
+    DB    67H                                                            ; '
+    DB    68H                                                            ; (
+        ;S6   30 - 37
+    DB    80H                                                            ; \
+    DB    0A5H                                                           ; POND MARK
+    DB    2BH                                                            ; YEN
+    DB    00H                                                            ; SPACE
+    DB    60H                                                            ; �
+    DB    69H                                                            ; )
+    DB    51H                                                            ; <
+    DB    57H                                                            ; >
+        ;S7   38 - 3F
+    DB    0C6H                                                           ; CLR
+    DB    0C5H                                                           ; HOME
+    DB    0C2H                                                           ; CURSOR UP
+    DB    0C1H                                                           ; CURSOR DOWN
+    DB    0C3H                                                           ; CURSOR RIGHT
+    DB    0C4H                                                           ; CURSOR LEFT
+    DB    5AH                                                            ;
+    DB    45H                                                            ;
+        ;
+        ;
+        ;   GRAPHIC
+        ;
+KTBLGS:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0F0H                                                           ; GRAPH BUT NULL
+    DB    0E5H                                                           ; #
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    42H                                                            ; #        ;
+    DB    0B6H                                                           ; #:
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    75H                                                            ; #Y
+    DB    76H                                                            ; #Z
+    DB    0B2H                                                           ; #@
+    DB    0D8H                                                           ; #[
+    DB    4EH                                                            ; #]
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+        ;S2   10 - 17
+    DB    3CH                                                            ; #Q
+    DB    30H                                                            ; #R
+    DB    44H                                                            ; #S
+    DB    71H                                                            ; #T
+    DB    79H                                                            ; #U
+    DB    0DAH                                                           ; #V
+    DB    38H                                                            ; #W
+    DB    6DH                                                            ; #X
+        ;S3   18 - 1F
+    DB    7DH                                                            ; #I
+    DB    5CH                                                            ; #J
+    DB    5BH                                                            ; #K
+    DB    0B4H                                                           ; #L
+    DB    1CH                                                            ; #M
+    DB    32H                                                            ; #N
+    DB    0B0H                                                           ; #O
+    DB    0D6H                                                           ; #P
+        ;S4   20 - 27
+    DB    53H                                                            ; #A
+    DB    6FH                                                            ; #B
+    DB    0DEH                                                           ; #C
+    DB    47H                                                            ; #D
+    DB    34H                                                            ; #E
+    DB    4AH                                                            ; #F
+    DB    4BH                                                            ; #G
+    DB    72H                                                            ; #H
+        ;S5   28 - 2F
+    DB    37H                                                            ; #1
+    DB    3EH                                                            ; #2
+    DB    7FH                                                            ; #3
+    DB    7BH                                                            ; #4
+    DB    3AH                                                            ; #5
+    DB    5EH                                                            ; #6
+    DB    1FH                                                            ; #7
+    DB    0BDH                                                           ; #8
+        ;S6   30 - 37
+    DB    0D4H                                                           ; #YEN
+    DB    9EH                                                            ; #+
+    DB    0D2H                                                           ; #-
+    DB    00H                                                            ; SPACE
+    DB    9CH                                                            ; #0
+    DB    0A1H                                                           ; #9
+    DB    0CAH                                                           ; #,
+    DB    0B8H                                                           ; #.
+        ;S7   38 - 3F
+    DB    0C8H                                                           ; INST
+    DB    0C7H                                                           ; DEL.
+    DB    0C2H                                                           ; CURSOR UP
+    DB    0C1H                                                           ; CURSOR DOWN
+    DB    0C3H                                                           ; CURSOR RIGHT
+    DB    0C4H                                                           ; CURSOR LEFT
+    DB    0BAH                                                           ; #?
+    DB    0DBH                                                           ; #/
+        ;
+        ;
+        ;   CONTROL CODE
+        ;
+KTBLC:
+        ;S0   00 - 07
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H                                                           ; ^
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+        ;S1   08 - 0F
+    DB    0F0H                                                           ; ^Y E3
+    DB    5AH                                                            ; ^Z E4 (CHECKER)
+    DB    0F0H                                                           ; ^@
+    DB    0F0H                                                           ; ^[ EB/E5
+    DB    0F0H                                                           ; ^] EA/E7 
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+        ;S2   10 - 17
+    DB    0C1H                                                           ; ^Q
+    DB    0C2H                                                           ; ^R
+    DB    0C3H                                                           ; ^S
+    DB    0C4H                                                           ; ^T
+    DB    0C5H                                                           ; ^U
+    DB    0C6H                                                           ; ^V
+    DB    0F0H                                                           ; ^W E1
+    DB    0F0H                                                           ; ^X E2
+        ;S3   18 - 1F
+    DB    0F0H                                                           ; ^I F9
+    DB    0F0H                                                           ; ^J FA
+    DB    0F0H                                                           ; ^K FB
+    DB    0F0H                                                           ; ^L FC
+    DB    0F0H                                                           ; ^M CD
+    DB    0F0H                                                           ; ^N FE
+    DB    0F0H                                                           ; ^O FF
+    DB    0F0H                                                           ; ^P E0
+        ;S4   20 - 27
+    DB    0F0H                                                           ; ^A F1
+    DB    0F0H                                                           ; ^B F2
+    DB    0F0H                                                           ; ^C F3
+    DB    0F0H                                                           ; ^D F4
+    DB    0F0H                                                           ; ^E F5
+    DB    0F0H                                                           ; ^F F6
+    DB    0F0H                                                           ; ^G F7
+    DB    0F0H                                                           ; ^H F8
+        ;S5   28 - 2F
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+        ;S6   30 - 37 (ERROR? 7 VALUES ONLY!!)
+    DB    0F0H                                                           ; ^YEN E6
+    DB    0F0H                                                           ; ^    EF
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H                                                           ; ^,
+    DB    0F0H
+        ;S7   38 - 3F
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H                                                           ; ^/ EE
+        ;
+        ;
+        ;   KANA
+        ;
+KTBLG:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0F0H                                                           ; GRAPH BUT NULL
+    DB    0CFH                                                           ; NIKO WH.
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    0B5H                                                           ; MO
+    DB    4DH                                                            ; DAKU TEN
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    35H                                                            ; HA
+    DB    77H                                                            ; TA
+    DB    0D7H                                                           ; WA
+    DB    0B3H                                                           ; YO
+    DB    0B7H                                                           ; HANDAKU
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+        ;S2   10 - 17
+    DB    7CH                                                            ; KA
+    DB    70H                                                            ; KE
+    DB    41H                                                            ; SHI
+    DB    31H                                                            ; KO
+    DB    39H                                                            ; HI
+    DB    0A6H                                                           ; TE
+    DB    78H                                                            ; KI
+    DB    0DDH                                                           ; CHI
+        ;S3   18 - 1F
+    DB    3DH                                                            ; FU
+    DB    5DH                                                            ; MI
+    DB    6CH                                                            ; MU
+    DB    56H                                                            ; ME
+    DB    1DH                                                            ; RHI
+    DB    33H                                                            ; RA
+    DB    0D5H                                                           ; HE
+    DB    0B1H                                                           ; HO
+        ;S4   20 - 27
+    DB    46H                                                            ; SA
+    DB    6EH                                                            ; TO
+    DB    0D9H                                                           ; THU
+    DB    48H                                                            ; SU
+    DB    74H                                                            ; KU
+    DB    43H                                                            ; SE
+    DB    4CH                                                            ; SO
+    DB    73H                                                            ; MA
+        ;S5   28 - 2F
+    DB    3FH                                                            ; A
+    DB    36H                                                            ; I
+    DB    7EH                                                            ; U
+    DB    3BH                                                            ; E
+    DB    7AH                                                            ; O
+    DB    1EH                                                            ; NA
+    DB    5FH                                                            ; NI
+    DB    0A2H                                                           ; NU
+        ;S6   30 - 37
+    DB    0D3H                                                           ; YO
+    DB    9FH                                                            ; YU
+    DB    0D1H                                                           ; YA
+    DB    00H                                                            ; SPACE
+    DB    9DH                                                            ; NO
+    DB    0A3H                                                           ; NE
+    DB    0D0H                                                           ; RU
+    DB    0B9H                                                           ; RE
+        ;S7   38 - 3F
+    DB    0C6H                                                           ; ?CLR
+    DB    0C5H                                                           ; ?HOME
+    DB    0C2H                                                           ; ?CURSOR UP
+    DB    0C1H                                                           ; ?CURSOR DOWN
+    DB    0C3H                                                           ; ?CURSOR RIGHT
+    DB    0C4H                                                           ; ?CURSOR LEFT 
+    DB    0BBH                                                           ; DASH
+    DB    0BEH                                                           ; RO
+
+        ;    MEMORY DUMP COMMAND "D"
+
+DUMP:   CALL    HEXIY                                                    ; START ADDRESS
+        CALL    P4DE
+        PUSH    HL
+        CALL    HLHEX                                                    ; END ADDRESS
+        POP     DE
+        JR      C,DUM1                                                   ; DATA ERROR THEN
+L0D36:  EX      DE,HL
+DUM3:   LD      B,08H                                                    ; DISPLAY 8 BYTES
+        LD      C,23                                                     ; CHANGE PRINT BIAS
+        CALL    NLPHL                                                    ; NEWLINE PRINT
+DUM2:   CALL    SPHEX                                                    ; SPACE PRINT + ACC PRINT
+        INC     HL
+        PUSH    AF
+        LD      A,(DSPXY)                                                ; DISPLAY POINT
+        ADD     A,C
+        LD      (DSPXY),A                                                ; X AXIS=X+CREG
+        POP     AF
+        CP      20H
+        JR      NC,L0D51
+        LD      A,2EH                                                    ; "."
+L0D51:  CALL    QADCN                                                    ; ASCII TO DISPLAY CODE
+        CALL    PRNT3
+        LD      A,(DSPXY)
+        INC     C
+        SUB     C                                                        ; ASCII DISPLAY POSITION
+        LD      (DSPXY),A
+        DEC     C
+        DEC     C
+        DEC     C
+        PUSH    HL
+        SBC     HL,DE
+        POP     HL
+        JR      Z,L0D85
+        LD      A,0F8H
+        LD      (KEYPA),A
+        NOP     
+        LD      A,(KEYPB)
+        CP      0FEH                                                     ; SHIFT KEY ?
+        JR      NZ,L0D78
+        CALL    QBLNK                                                    ; 64MSEC DELAY
+L0D78:  DJNZ    DUM2
+L0D7A:  CALL    QKEY                                                     ; STOP DISPLAY
+        OR      A
+        JR      Z,L0D7A                                                  ; SPACE KEY THEN STOP
+        CALL    QBRK                                                     ; BREAK IN ?
+        JR      NZ,DUM3
+L0D85:  JP      ST1                                                      ; COMMAND IN !
+
+DUM1:   LD      HL,160                                                   ; 20*8 BYTES
+        ADD     HL,DE
+        JR      L0D36
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    V-BLANK CHECK
+
+QBLNK:  PUSH    AF
+L0DA7:  LD      A,(KEYPC)                                                ; V-BLANK
+        RLCA    
+        JR      NC,L0DA7
+L0DAD:  LD      A,(KEYPC)                                                ; 64
+        RLCA                                                             ;
+        JR      C,L0DAD                                                  ; MSEC
+        POP     AF
+        RET     
+        ;    DISPLAY ON POINTER
+        ;    ACC=DISPLAY CODE
+        ;    EXCEPT F0H
+
+QDSP:   PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+DSP01:  CALL    QPONT                                                    ; DISPLAY POSITION
+        LD      (HL),A
+        LD      HL,(DSPXY)
+        LD      A,L
+        CP      COLW-1
+        JR      NZ,DSP04
+        CALL    PMANG
+        JR      C,DSP04
+        EX      DE,HL
+        LD      (HL),1                                                   ; LOGICAL 1ST COLUMN
+        INC     HL
+        LD      (HL),0                                                   ; LOGICAL 2ND COLUMN
+DSP04:  LD      A,0C3H                                                   ; CURSL
+        JR      L0DE0
+
+        ;    GRAPHIC STATUS CHECK
+
+GRSTAS: LD      A,(KANAF)
+        CP      01H
+        LD      A,0CAH
+        RET     
+
+        ;    DISPLAY CONTROL
+        ;    ACC=CONTROL CODE
+
+QDPCT:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+L0DE0:  LD      B,A
+        AND     0F0H
+        CP      0C0H
+        JR      NZ,CURS5
+        XOR     B
+        RLCA    
+        LD      C,A
+        LD      B,0
+        LD      HL,CTBL                                                  ; PAGE MODE1
+        ADD     HL,BC
+        LD      E,(HL)
+        INC     HL
+        LD      D,(HL)
+        LD      HL,(DSPXY)
+        EX      DE,HL
+        JP      (HL)
+
+CURSD:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,H
+        CP      24
+        JR      Z,CURS4
+        INC     H
+CURS1:  
+CURS3:    LD      (DSPXY),HL
+CURS5:  JP      QRSTR
+
+CURSU:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,H
+        OR      A
+        JR      Z,CURS5
+        DEC     H
+CURSU1: JR      CURS3
+
+CURSR:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,L
+        CP      COLW-1
+        JR      NC,CURS2
+        INC     L
+        JR      CURS3
+
+CURS2:  LD      L,0
+        INC     H
+        LD      A,H
+        CP      25
+        JR      C,CURS1
+        LD      H,24
+        LD      (DSPXY),HL
+CURS4:  JR      SCROL
+
+CURSL:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,L
+        OR      A
+        JR      Z,L0E2D
+        DEC     L
+        JR      CURS3
+
+L0E2D:  LD      L,COLW-1
+        DEC     H
+        JP      P,CURSU1
+        LD      H,0
+        LD      (DSPXY),HL
+        JR      CURS5
+
+CLRS:   LD      HL,MANG
+        LD      B,27
+        CALL    QCLER
+        LD      HL,0D000H                                                ; SCRN TOP
+        CALL    NCLR08
+        LD      A,71H                                                    ; COLOR DATA
+        CALL    NCLR8                                                    ; D800H-DFFFH CLEAR
+HOME:   LD      HL,0                                                     ; DSPXY:0 X=0,Y=0
+        JR      CURS3
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    CR
+
+CR:     CALL    PMANG
+        RRCA    
+        JR      NC,CURS2
+        LD      L,0
+        INC     H
+        CP      24
+        JR      Z,CR1
+        INC     H
+        JR      CURS1
+
+CR1:    LD      (DSPXY),HL
+
+        ;    SCROLL
+
+SCROL:  LD      BC,SCRNSZ - COLW
+        LD      DE,SCRN                                                  ; TOP OF $CRT ADDRESS
+        LD      HL,SCRN+COLW                                               ; COLUMN
+        PUSH    BC                                                       ; 1000 STORE
+        LDIR    
+        POP     BC
+        PUSH    DE
+        LD      DE,SCRN + 800H                                           ; COLOR RAM SCROLL
+        LD      HL,SCRN + 800H + COLW                                    ; SCROLL TOP + 1 LINE
+        LDIR    
+        LD      B,COLW                                                   ; ONE LINE
+        EX      DE,HL
+        LD      A,71H                                                    ; COLOR RAM INITIAL DATA
+        CALL    QDINT
+        POP     HL
+        LD      B,COLW
+        CALL    QCLER                                                    ; LAST LINE CLEAR
+        LD      BC,ROW + 1                                               ; ROW NUMBER+1
+        LD      DE,MANG                                                  ; LOGICAL MANAGEMENT
+        LD      HL,MANG+1
+        LDIR    
+        LD      (HL),0
+        LD      A,(MANG)
+        OR      A
+        JR      Z,QRSTR
+        LD      HL,DSPXY+1
+        DEC     (HL)
+        JR      SCROL
+
+        ;    CONTROL CODE TABLE
+
+CTBL:   DW    SCROL                                                     ; SCROLLING 10H
+        DW    CURSD                                                     ; CURSOR DOWN 11H
+        DW    CURSU                                                     ; CURSOR UP 12H
+        DW    CURSR                                                     ; CURSOR RIGHT 13H
+        DW    CURSL                                                     ; CURSOR LEFT 14H
+        DW    HOME                                                      ; 15H
+        DW    CLRS                                                      ; 16H
+        DW    DEL                                                       ; 17H
+        DW    INST                                                      ; 18H
+        DW    ALPHA                                                     ; 19H
+        DW    KANA                                                      ; GRAPHIC 1AH
+        DW    QRSTR                                                     ; 1BH
+        DW    QRSTR                                                     ; 1CH
+        DW    CR                                                        ; 1DH
+        DW    QRSTR                                                     ; 1EH
+        DW    QRSTR                                                     ; 1FH
+
+        ;    INST BYPASS
+
+INST2:    SET    3,H                                                     ; COLOR RAM
+    LD    A,(HL)                                                         ; FROM
+    INC    HL
+    LD      (HL),A                                                       ; TO
+        DEC     HL                                                       ; ADDRESS ADJUST
+        RES     3,H
+        LDD                                                              ; CHANGE TRNS.
+        LD      A,C
+        OR      B                                                        ; BC=0 ?
+        JR      NZ,INST2
+        EX      DE,HL
+        LD      (HL),0
+        SET     3,H                                                      ; COLOR RAM
+        LD      (HL),71H
+        JR      QRSTR
+
+ALPHA:  XOR     A
+ALPH1:  LD      (KANAF),A
+
+        ;    RESTORE
+
+QRSTR:  POP     HL
+QRSTR1: POP     DE
+        POP     BC
+        POP     AF
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+KANA:   CALL    GRSTAS
+        JP      Z,DSP01                                                  ; NOT GRAPH KEY THEN JUMP
+        LD      A,01H
+        JR      ALPH1
+
+DEL:    EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,H                                                      ; HOME ?
+        OR      L
+        JR      Z,QRSTR
+        LD      A,L
+        OR      A
+        JR      NZ,DEL1                                                  ; LEFT SIDE ?
+        CALL    PMANG
+        JR      C,DEL1
+        CALL    QPONT
+        DEC     HL
+        LD      (HL),0
+        JR      L0F33                                                    ; JUMP CURSL
+
+DEL1:   CALL    PMANG
+        RRCA    
+        LD      A,COLW
+        JR      NC,L0F17
+        RLCA                                                             ; ACC=80
+L0F17:  SUB     L
+        LD      B,A                                                      ; TRNS. BYTE
+        CALL    QPONT
+DEL2:   LD      A,(HL)                                                   ; CHANGE FROM ADDRESS
+        DEC     HL
+        LD      (HL),A                                                   ; TO
+        INC     HL
+        SET     3,H                                                      ; COLOR RAM
+        LD      A,(HL)
+        DEC     HL
+        LD      (HL),A
+        RES     3,H                                                      ; CHANGE
+        INC     HL
+        INC     HL                                                       ; NEXT
+        DJNZ    DEL2
+        DEC     HL                                                       ; ADDRESS ADJUST
+        LD      (HL),0
+        SET     3,H
+        LD      HL,71H                                                   ; BLUE + WHITE
+L0F33:  LD      A,0C4H                                                   ; JP CURSL
+        JP      L0DE0
+
+INST:   CALL    PMANG
+        RRCA    
+        LD      L,COLW - 1
+        LD      A,L
+        JR      NC,L0F42
+        INC     H
+L0F42:  CALL    QPNT1
+        PUSH    HL
+        LD      HL,(DSPXY)
+        JR      NC,L0F4D
+        LD      A,(COLW*2) - 1
+L0F4D:  SUB     L
+        LD      B,0
+        LD      C,A
+        POP     DE
+        JR      Z,QRSTR
+        LD      A,(DE)
+        OR      A
+        JR      NZ,QRSTR
+        LD      H,D                                                      ; HL<-DE
+        LD      L,E
+        DEC     HL
+        JP      INST2                                                    ; JUMP NEXT (BYPASS)
+
+        ;    PROGRAM SAVE
+        ;    COMMAND "S"
+
+SAVE:   CALL    HEXIY                                                    ; START ADDRESS
+        LD      (DTADR),HL                                               ; DATA ADDRESS BUFFER
+        LD      B,H
+        LD      C,L
+        CALL    P4DE
+        CALL    HEXIY                                                    ; END ADDRESS
+        SBC     HL,BC                                                    ; BYTE SIZE
+        INC     HL
+        LD      (SIZE),HL                                                ; BYTE SIZE BUFFER
+        CALL    P4DE
+        CALL    HEXIY                                                    ; EXECUTE ADDRESS
+        LD      (EXADR),HL                                               ; BUFFER
+        CALL    NL
+        LD      DE,MSGSV                                                 ; SAVED FILENAME
+        RST     18H                                                      ; CALL MSGX
+        CALL    BGETL                                                    ; FILENAME INPUT
+        CALL    P4DE
+        CALL    P4DE
+        LD      HL,NAME                                                  ; NAME BUFFER
+SAV1:   INC     DE
+        LD      A,(DE)
+        LD      (HL),A                                                   ; FILENAME TRANS.
+        INC     HL
+        CP      0DH                                                      ; END CODE
+        JR      NZ,SAV1
+        LD      A,01H                                                    ; ATTRIBUTE: OBJECT CODE
+        LD      (ATRB),A
+        CALL    QWRI
+        JP      C,QER                                                    ; WRITE ERROR
+        CALL    QWRD                                                     ; DATA
+        JP      C,QER
+        CALL    NL
+        LD      DE,MSGOK                                                 ; OK MESSAGE
+        RST     18H                                                      ; CALL MSGX
+        JP      ST1
+
+        ;    COMPUTE POINT ADDRESS
+        ;    HL=SCREEN COORDINATE
+        ;    EXIT HL=POINT ADDRESS ON SCREEN
+
+QPONT:  LD      HL,(DSPXY)
+QPNT1:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        POP     BC
+        LD      DE,COLW                                                ; 40
+        LD      HL,SCRN-COLW
+QPNT2:  ADD     HL,DE
+        DEC     B
+        JP      P,QPNT2
+        LD      B,0
+        ADD     HL,BC
+        POP     DE
+        POP     BC
+        POP     AF
+        RET     
+
+        ;    VERIFYING COMMAND "V"
+
+VRFY:   CALL    QVRFY
+        JP      C,QER
+        LD      DE,MSGOK
+        RST     18H
+        JP      ST1
+
+        ;    CLER
+        ;    B=SIZE
+        ;    HL=LOW ADDRESS
+
+QCLER:  XOR     A
+        JR      QDINT
+
+QCLRFF: LD      A,0FFH
+QDINT:  LD      (HL),A
+        INC     HL
+        DJNZ    QDINT
+        RET     
+
+        ;    GAP CHECK
+
+GAPCK:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      BC,KEYPB
+        LD      DE,CSTR
+GAPCK1: LD      H,100
+GAPCK2: CALL    EDGE
+        JR      C,GAPCK3
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JR      NZ,GAPCK1
+        DEC     H
+        JR      NZ,GAPCK2
+GAPCK3: JP      RET3
+
+        ;    MONITOR WORK AREA
+        ;    (MZ700)
+
+        ORG     10F0H
+SPV:
+IBUFE:                                                                   ; TAPE BUFFER (128 BYTES)
+ATRB:   DS      virtual 1                                                ; ATTRIBUTE
+NAME:   DS      virtual 17                                               ; FILE NAME
+SIZE:   DS      virtual 2                                                ; BYTESIZE
+DTADR:  DS      virtual 2                                                ; DATA ADDRESS
+EXADR:  DS      virtual 2                                                ; EXECUTION ADDRESS
+COMNT:  DS      virtual 104                                              ; COMMENT
+KANAF:  DS      virtual 1                                                ; KANA FLAG (01=GRAPHIC MODE)
+DSPXY:  DS      virtual 2                                                ; DISPLAY COORDINATES
+MANG:   DS      virtual 27                                               ; COLUMN MANAGEMENT
+FLASH:  DS      virtual 1                                                ; FLASHING DATA
+FLPST:  DS      virtual 2                                                ; FLASHING POSITION
+FLSST:  DS      virtual 1                                                ; FLASHING STATUS
+FLSDT:  DS      virtual 1                                                ; CURSOR DATA
+STRGF:  DS      virtual 1                                                ; STRING FLAG
+DPRNT:  DS      virtual 1                                                ; TAB COUNTER
+TMCNT:  DS      virtual 2                                                ; TAPE MARK COUNTER
+SUMDT:  DS      virtual 2                                                ; CHECK SUM DATA
+CSMDT:  DS      virtual 2                                                ; FOR COMPARE SUM DATA
+AMPM:   DS      virtual 1                                                ; AMPM DATA
+TIMFG:  DS      virtual 1                                                ; TIME FLAG
+SWRK:   DS      virtual 1                                                ; KEY SOUND FLAG
+TEMPW:  DS      virtual 1                                                ; TEMPO WORK
+ONTYO:  DS      virtual 1                                                ; ONTYO WORK
+OCTV:   DS      virtual 1                                                ; OCTAVE WORK
+RATIO:  DS      virtual 2                                                ; ONPU RATIO
+BUFER:  DS      virtual 81                                               ; GET LINE BUFFER
+
+        ;    EQU TABLE I/O REPORT
+
+KEYPA:  EQU     0E000H
+KEYPB:  EQU     0E001H
+KEYPC:  EQU     0E002H
+KEYPF:  EQU     0E003H
+CSTR:   EQU     0E002H
+CSTPT:  EQU     0E003H
+CONT0:  EQU     0E004H
+CONT1:  EQU     0E005H
+CONT2:  EQU     0E006H
+CONTF:  EQU     0E007H
+SUNDG:  EQU     0E008H
+TEMP:   EQU     0E008H
+        ;    MONITOR WORK AREA
+
+SCRN:   EQU    0D000H
+KANST:  EQU    0E003H                                                  ; KANA STATUS REPORT
+
+
diff --git a/software/asm/1Z-013A_80c.asm b/software/asm/1Z-013A_80c.asm
new file mode 100644
index 0000000..8c72138
--- /dev/null
+++ b/software/asm/1Z-013A_80c.asm
@@ -0,0 +1,3274 @@
+        ; MONITOR PROGRAM 1Z-013A 
+        ;    (MZ700) FOR PAL 
+        ;      REV. 83.4.7
+        ; Tuesday, 02 of June 1998 at 10:02 PM
+        ; Tuesday, 09 of June 1998 at 07:17 AM
+
+        ORG     0000h        ; 0000h Entrypoint 
+
+MONIT:  JP      START                                                    ; MONITOR ON
+GETL:   JP      QGETL                                                    ; GET LINE (END "CR")
+LETNL:  JP      QLTNL                                                    ; NEW LINE
+NL:     JP      QNL                                                      ;
+PRNTS:  JP      QPRTS                                                    ; PRINT SPACE
+PRNTT:  JP      QPRTT                                                    ; PRINT TAB
+PRNT:   JP      QPRNT                                                    ; 1 CHARACTER PRINT
+MSG:    JP      QMSG                                                     ; 1 LINE PRINT (END "0DH")
+MSGX:   JP      QMSGX                                                    ; RST 18H
+GETKY:  JP      QGET                                                     ; GET KEY
+BRKEY:  JP      QBRK                                                     ; GET BREAK
+WRINF:  JP      QWRI                                                     ; WRITE INFORMATION
+WRDAT:  JP      QWRD                                                     ; WRITE DATA
+RDINF:  JP      QRDI                                                     ; READ INFORMATION
+RDDAT:  JP      QRDD                                                     ; READ DATA
+VERFY:  JP      QVRFY                                                    ; VERIFYING CMT
+MELDY:  JP      QMLDY                                                    ; RST 30H
+TIMST:  JP      QTMST                                                    ; TIME SET
+        NOP
+        NOP
+        JP      1038H                                                    ; INTERRUPT ROUTINE (8253)
+TIMRD:  JP      QTMRD                                                    ; TIME READ
+BELL:   JP      QBEL                                                     ; BELL ON
+XTEMP:  JP      QTEMP                                                    ; TEMPO SET (1 - 7)
+MSTA:   JP      MLDST                                                    ; MELODY START
+MSTP:   JP      MLDSP                                                    ; MELODY STOP
+
+START:  LD      SP,SPV                                                   ; STACK SET (10F0H)
+        IM      1                                                        ; IM 1 SET
+        CALL    QMODE                                                    ; 8255 MODE SET
+        CALL    QBRK                                                     ; CTRL ?
+        JR      NC,ST0
+        CP      20H                                                      ; KEY IS CTRL KEY
+        JR      NZ,ST0
+CMY0:   OUT     (0E1H),A                                                 ; D000-FFFFH IS DRAM
+        LD      DE,0FFF0H                                                ; TRANS. ADR.
+        LD      HL,DMCP                                                  ; MEMORY CHANG PROGRAM
+        LD      BC,05H                                                   ; BYTE SIZE
+        LDIR    
+        JP      0FFF0H                                                   ; JUMP $FFF0
+
+DMCP:   OUT     (0E0H),A                                                 ; 0000H-0FFFH IS DRAM
+        JP      0000H
+
+ST0:    LD      B,0FFH                                                   ; BUFFER CLEAR
+        LD      HL,NAME                                                  ; 10F1H-11F0H CLEAR
+        CALL    QCLER
+        LD      A,16H                                                    ; LASTER CLR.
+        CALL    PRNT
+        LD      A,71H                                                    ; BACK:BLUE CHA.:WRITE
+        LD      HL,0D800H                                                ; COLOR ADDRESS
+        CALL    NCLR8
+        LD      HL,TIMIN                                                 ; INTERRUPT JUMP ROUTINE
+        LD      A,0C3H
+        LD      (1038H),A
+        LD      (1039H),HL
+        LD      A,04H                                                    ; NORMAL TEMPO
+        LD      (TEMPW),A
+        CALL    MLDSP                                                    ; MELODY STOP
+        CALL    NL
+        LD      DE,MSGQ3                                                 ; ** MONITOR 1Z-013A **
+        RST     18H                                                      ; CALL MGX
+        CALL    QBEL
+SS:     LD      A,01H
+        LD      (SWRK),A                                                 ; KEY IN SILENT
+        LD      HL,0E800H                                                ; USR ROM?
+        LD      (HL),A                                                   ; ROM CHECK
+        JR      FD2
+
+ST1:    CALL    NL
+        LD      A,2AH                                                    ; "*" PRINT
+        CALL    PRNT
+        LD      DE,BUFER                                                 ; GET LINE WORK (11A3H)
+        CALL    GETL
+ST2:    LD      A,(DE)
+        INC     DE
+        CP      0DH
+        JR      Z,ST1
+        CP      'J'                                                      ; JUMP
+        JR      Z,GOTO
+        CP      'L'                                                      ; LOAD PROGRAM
+        JR      Z,LOAD
+        CP      'F'                                                      ; FLOPPY ACCESS
+        JR      Z,FD
+        CP      'B'                                                      ; KEY IN BELL
+        JR      Z,SG
+        CP      '#'                                                      ; CHANG MEMORY
+        JR      Z,CMY0
+        CP      'P'                                                      ; PRINTER TEST
+        JR      Z,PTEST
+        CP      'M'                                                      ; MEMORY CORRECTION
+        JP      Z,MCOR
+        CP      'S'                                                      ; SAVE DATA
+        JP      Z,SAVE
+        CP      'V'                                                      ; VERIFYING DATA
+        JP      Z,VRFY
+        CP      'D'                                                      ; DUMP DATA
+        JP      Z,DUMP
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        JR      ST2                                                      ; NO COMMAND
+
+        ;    JUMP COMMAND
+
+GOTO:   CALL    HEXIY
+        JP      (HL)
+
+        ;    KEY SOUND ON/OFF
+
+SG:     LD      A,(SWRK)                                                 ; D0=SOUND WORK
+        RRA     
+        CCF                                                              ; CHANGE MODE
+        RLA     
+        JR      SS+2
+
+        ;    FLOPPY
+
+FD:     LD      HL,0F000H                                                ; FLOPPY I/O CHECK
+FD2:    LD      A,(HL)
+        OR      A
+        JR      NZ,ST1
+FD1:    JP      (HL)
+
+        ;    ERROR (LOADING)
+
+QER:    CP      02H                                                      ; A=02H : BREAK IN
+        JR      Z,ST1
+        LD      DE,MSGE1                                                 ; CHECK SUM ERROR
+        RST     18H                                                      ; CALL MSGX
+L010F:    JR      ST1
+
+        ;    LOAD COMMAND
+
+LOAD:      CALL    QRDI
+        JR      C,QER
+LOA0:   CALL    NL
+        LD      DE,MSGQ2                                                 ; LOADING
+        RST     18H                                                      ; CALL MSGX
+        LD      DE,NAME                                                  ; FILE NAME
+        RST     18H                                                      ; CALL MSGX
+        CALL    QRDD
+        JR      C,QER
+        LD      HL,(EXADR)                                               ; EXECUTE ADDRESS
+        LD      A,H
+        CP      12H                                                      ; EXECUTE CHECK
+        JR      C,L010F
+        JP      (HL)
+
+        ;    GETLINE AND BREAK IN CHECK
+        ;
+        ;    EXIT BREAK IN THEN JUMP (ST1)
+        ;    ACC=TOP OF LINE DATA
+
+BGETL:  EX      (SP),HL
+        POP     BC                                                       ; STACK LOAD
+        LD      DE,BUFER                                                 ; MONITOR GETLINE BUFF
+        CALL    GETL
+        LD      A,(DE)
+        CP      1BH                                                      ; BREAK CODE
+        JR      Z,L010F                                                  ; JP Z,ST1
+        JP      (HL)
+
+        ;    ASCII TO HEX CONVERT
+        ;    INPUT (DE)=ASCII
+        ;    CY=1 THEN JUMP (ST1)
+
+HEXIY:  EX      (SP),IY
+        POP     AF
+        CALL    HLHEX
+        JR      C,L010F                                                  ; JP C,ST1
+        JP      (IY)
+
+MSGE1:    DB    "CHECK SUM ER.\r"
+
+        ;    PLOTTER PRINTER TEST COMMAND
+        ;    (DPG23)
+        ;    &=CONTROL COMMANDS GROUP
+        ;    C=PEN CHANGE
+        ;    G=GRAPH MODE
+        ;    S=80 CHA. IN 1 LINE
+        ;    L=40 CHA. IN 1 LINE
+        ;    T=PLOTTER TEST
+        ;    IN (DE)=PRINT DATA
+
+PTEST:  LD      A,(DE)
+        CP      '&'
+        JR      NZ,PTST1
+PTST0:  INC     DE
+        LD      A,(DE)
+        CP      'L'                                                      ; 40 IN 1 LINE
+        JR      Z,PLPT
+        CP      'S'                                                      ; 80 IN 1 LINE
+        JR      Z,PPLPT
+        CP      'C'                                                      ; PEN CHANGE
+        JR      Z,PEN
+        CP      'G'                                                      ; GRAPH MODE
+        JR      Z,PLOT
+        CP      'T'                                                      ; TEST
+        JR      Z,PTRN
+PTST1:  CALL    PMSG                                                     ; PLOT MESSAGE
+        JP      ST1
+
+PLPT:   LD      DE,LLPT                                                  ; 01-09-09-0B-0D
+        JR      PTST1
+
+PPLPT:  LD      DE,SLPT                                                  ; 01-09-09-09-0D
+        JR      PTST1
+
+PTRN:   LD      A,04H                                                    ; TEST PATTERN
+        JR      PLOT+2
+
+PLOT:   LD      A,02H                                                    ; GRAPH CODE
+    CALL    LPRNT
+        JR      PTST0
+
+PEN:    LD      A,1DH                                                    ; 1 CHANGE CODE (TEXT MODE)
+        JR      PLOT+2
+
+        ;    1CHA. PRINT TO $LPT
+        ;    IN: ACC PRINT DATA
+
+LPRNT:  LD      C,0                                                      ; RDA TEST (READY? RDA=0)
+        LD      B,A                                                      ; PRINT DATA STORE
+        CALL    RDA
+        LD      A,B
+        OUT     (0FFH),A                                                 ; DATA OUT 
+        LD      A,80H                                                    ; RDP HIGH
+        OUT     (0FEH),A
+        LD      C,01H                                                    ; RDA TEST
+        CALL    RDA
+    XOR     A                                                            ; RDP LOW
+        OUT     (0FEH),A
+        RET     
+
+        ;    $LPT MSG
+        ;    IN: DE DATA LOW ADDRESS
+        ;    0DH MSG END
+
+PMSG:   PUSH    DE
+        PUSH    BC
+        PUSH    AF
+PMSG1:  LD      A,(DE)                                                   ; ACC=DATA
+        CALL    LPRNT
+        LD      A,(DE)
+        INC     DE
+        CP      0DH                                                      ; END?
+        JR      NZ,PMSG1
+        POP     AF
+        POP     BC
+        POP     DE
+        RET     
+
+        ;    RDA CHECK
+        ;    BRKEY IN TO MONITOR RETURN
+        ;    IN: C RDA CODE
+
+RDA:    IN      A,(0FEH)
+        AND     0DH                                                      ; RDA ONLY
+        CP      C
+        RET     Z
+        CALL    BRKEY
+        JR      NZ,RDA
+        LD      SP,SPV
+        JP      ST1
+
+        ;    MELODY
+        ;    DE=DATA LOW ADDRESS
+        ;    EXIT CF=1 BREAK
+        ;         CF=0 OK
+
+QMLDY:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      A,02H
+        LD      (OCTV),A
+        LD      B,01H
+MLD1:   LD      A,(DE)
+        CP      0DH                                                      ; CR
+        JR      Z,MLD4
+        CP      0C8H                                                     ; END MARK
+        JR      Z,MLD4
+        CP      0CFH                                                     ; UNDER OCTAVE
+        JR      Z,MLD2
+        CP      2DH                                                      ; "-" 
+        JR      Z,MLD2
+        CP      2BH                                                      ; "+"
+        JR      Z,MLD3
+        CP      0D7H                                                     ; UPPER OCTAVE
+        JR      Z,MLD3
+        CP      23H                                                      ; "#" HANON
+        LD      HL,MTBL
+        JR      NZ,L01F5
+        LD      HL,MNTBL
+        INC     DE
+L01F5:    CALL    ONPU                                                   ; ONTYO SET
+        JR      C,MLD1
+        CALL    RYTHM
+        JR      C,MLD5
+        CALL    MLDST                                                    ; MELODY START
+        LD      B,C
+        JR      MLD1
+
+MLD2:   LD      A,3
+L0207:    LD      (OCTV),A
+        INC     DE
+        JR      MLD1
+
+MLD3:   LD      A,01H
+        JR      L0207
+
+MLD4:   CALL    RYTHM
+MLD5:   PUSH    AF
+        CALL    MLDSP
+        POP     AF
+        JP      RET3
+
+        ;    ONPU TO RATIO CONV
+        ;    EXIT (RATIO)=RATIO VALUE
+        ;    C=ONTYO*TEMPO
+
+ONPU:   PUSH    BC
+        LD      B,8
+ONP1:   LD      A,(DE)
+L0220:    CP      (HL)
+        JR      Z,ONP2
+        INC     HL
+        INC     HL
+        INC     HL
+        DJNZ    L0220
+        SCF     
+        INC     DE
+        POP     BC
+        RET     
+
+ONP2:   INC     HL
+        PUSH    DE
+        LD      E,(HL)
+        INC     HL
+        LD      D,(HL)
+        EX      DE,HL
+        LD      A,H
+        OR      A
+        JR      Z,L023F
+        LD      A,(OCTV)                                                 ; 11A0H OCTAVE WORK
+L0239:  DEC     A
+        JR      Z,L023F
+        ADD     HL,HL
+        JR      L0239
+
+L023F:  LD      (RATIO),HL                                               ; 11A1H ONPU RATIO
+        LD      HL,OCTV
+        LD      (HL),02H
+        DEC     HL
+        POP     DE
+        INC     DE
+        LD      A,(DE)
+        LD      B,A
+        AND     0F0H                                                     ; ONTYO ?
+        CP      30H
+        JR      Z,L0255
+        LD      A,(HL)                                                   ; HL=ONTYO
+        JR      L025A
+
+L0255:  INC     DE
+        LD      A,B
+        AND     0FH
+        LD      (HL),A                                                   ; HL=ONTYO
+L025A:  LD      HL,OPTBL
+        ADD     A,L
+        LD      L,A
+        LD      C,(HL)
+        LD      A,(TEMPW)
+        LD      B,A
+        XOR     A
+ONP3:   ADD     A,C
+        DJNZ    ONP3
+        POP     BC
+        LD      C,A
+        XOR     A
+        RET     
+
+MTBL:    DB    "C"
+    DW    0846H
+    DB    "D"
+    DW    075FH
+    DB    "E"
+    DW    0691H
+    DB    "F"
+    DW    0633H
+    DB    "G"
+    DW    0586H
+    DB    "A"
+    DW    04ECH
+    DB    "B"
+    DW    0464H
+    DB    "R"
+    DW    0000H
+MNTBL:    DB    "C"                                                      ; #C
+    DW    07CFH
+    DB    "D"                                                            ; #D
+    DW    06F5H
+    DB    "E"                                                            ; #E
+    DW    0633H
+    DB    "F"                                                            ; #F
+    DW    05DAH
+    DB    "G"                                                            ; #G
+    DW    0537H
+    DB    "A"                                                            ; #A
+    DW    04A5H
+    DB    "B"                                                            ; #B
+    DW    0423H
+    DB    "R"                                                            ; #R
+    DW    0000H
+OPTBL:    DB    01H
+    DB    02H
+    DB    03H
+    DB    04H
+    DB    06H
+    DB    08H
+    DB    0CH
+    DB    10H
+    DB    18H
+    DB    20H
+
+        ;    INCREMENT DE REG.
+
+P4DE:   INC     DE
+    INC    DE
+        INC     DE
+        INC     DE
+        RET     
+
+        ;    MELODY START & STOP
+
+MLDST:  LD      HL,(RATIO)
+        LD      A,H
+        OR      A
+        JR      Z,MLDSP
+        PUSH    DE
+        EX      DE,HL
+        LD      HL,CONT0
+        LD      (HL),E
+        LD      (HL),D
+        LD      A,01H
+        POP     DE
+        JR      MLDS1
+
+MLDSP:  LD      A,36H                                                    ; MODE SET (8253 C0)
+        LD      (CONTF),A                                                ; E007H
+        XOR     A
+MLDS1:  LD      (SUNDG),A                                                ; E008H
+        RET                                                              ; TEHRO SET
+
+        ;    RHYTHM
+        ;    B=COUNT DATA
+        ;    IN
+        ;    EXIT CF=1 BREAK
+        ;         CF=0 OK
+
+RYTHM:  LD      HL,KEYPA                                                 ; E000H
+        LD      (HL),0F8H
+        INC     HL
+        LD      A,(HL)
+        AND     81H                                                      ; BREAK IN CHECK
+        JR      NZ,L02D5
+        SCF     
+        RET     
+
+L02D5:  LD      A,(TEMP)                                                 ; E008H
+        RRCA                                                             ; TEMPO OUT
+        JR      C,L02D5
+L02DB:  LD      A,(TEMP)
+        RRCA    
+        JR      NC,L02DB
+        DJNZ    L02D5
+        XOR     A
+        RET     
+
+        ;    TEMPO SET
+        ;    ACC=VALUE (1-7)
+
+QTEMP:  PUSH    AF
+        PUSH    BC
+        AND     0FH
+        LD      B,A
+        LD      A,8
+        SUB     B
+        LD      (TEMPW),A
+        POP     BC
+        POP     AF
+        RET     
+
+        ;    CRT MANAGEMENT
+        ;    EXIT HL:DSPXY H=Y,L=X
+        ;    DE:MANG ADR. (ON DSPXY)
+        ;    A :MANG DATA
+        ;    CY:MANG=1
+
+PMANG:  LD      HL,MANG                                                  ; CRT MANG POINTER
+        LD      A,(1172H)                                                ; DSPXY+1
+        ADD     A,L
+        LD      L,A
+        LD      A,(HL)
+        INC     HL
+        RL      (HL)
+        OR      (HL)
+        RR      (HL)
+        RRCA    
+        EX      DE,HL
+        LD      HL,(DSPXY)
+        RET     
+
+        ;    TIME SET
+        ;    ACC=0 : AM
+        ;       =1 : PM
+        ;    DE=SEC: BINARY
+
+QTMST:  DI      
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      (AMPM),A                                                 ; AMPM DATA
+        LD      A,0F0H
+        LD      (TIMFG),A                                                ; TIME FLAG
+        LD      HL,0A8C0H                                                ; 12 HOURS (43200 SECONDS)
+        XOR     A
+        SBC     HL,DE                                                    ; COUNT DATA = 12H-IN DATA
+        PUSH    HL
+        NOP     
+        EX      DE,HL
+        LD      HL,CONTF                                                 ; E007H
+        LD      (HL),74H                                                 ; C1
+        LD      (HL),0B0H                                                ; C2
+        DEC     HL                                                       ; CONT2
+        LD      (HL),E                                                   ; E006H
+        LD      (HL),D
+        DEC     HL                                                       ; CONT1
+        LD      (HL),0AH                                                 ; E005H STROBE 640,6�SECONDS COUNT2
+        LD      (HL),0
+        INC     HL
+        INC     HL                                                       ; CONTF
+        LD      (HL),80H                                                 ; E007H
+        DEC     HL                                                       ; CONT2
+QTMS1:  LD      C,(HL)                                                   ; E006H
+        LD      A,(HL)
+        CP      D
+        JR      NZ,QTMS1
+        LD      A,C
+        CP      E
+        JR      NZ,QTMS1
+        DEC     HL                                                       ; E005H
+        NOP     
+        NOP     
+        NOP     
+        LD      (HL),0FBH                                                ; 1 SECOND (15611HZ) E005H
+        LD      (HL),3CH
+        INC     HL
+        POP     DE
+QTMS2:  LD      C,(HL)                                                   ; E006H
+        LD      A,(HL)
+        CP      D
+        JR      NZ,QTMS2
+        LD      A,C
+        CP      E
+        JR      NZ,QTMS2
+        POP     HL
+        POP     DE
+        POP     BC
+        EI      
+        RET     
+
+        ;    BELL DATA
+        ;    
+QBELD:    DB    0D7H
+    DB    "A0"
+    DB    0DH
+        NOP     
+        NOP     
+
+        ;    TIME READ
+        ;    EXIT ACC=0 :AM
+        ;            =1 :PM
+        ;         DE=SEC. BINARY
+
+QTMRD:  PUSH    HL
+        LD      HL,CONTF
+        LD      (HL),80H                                                 ; E007H C2
+        DEC     HL                                                       ; CONT2
+        DI      
+        LD      E,(HL)
+        LD      D,(HL)                                                   ; e006H C2 MODE0
+        EI      
+L0363:  LD      A,E
+        OR      D
+        JR      Z,QTMR1
+        XOR     A
+        LD      HL,0A8C0H                                                ; 12 HOURS
+        SBC     HL,DE
+        JR      C,QTMR2
+        EX      DE,HL
+        LD      A,(AMPM)
+        POP     HL
+        RET     
+
+QTMR1:  LD      DE,0A8C0H
+L0378:  LD      A,(AMPM)
+        XOR     01H
+        POP     HL
+        RET     
+
+QTMR2:  DI      
+        LD      HL,CONT2
+        LD      A,(HL)
+        CPL     
+        LD      E,A
+        LD      A,(HL)
+        CPL     
+        LD      D,A
+        EI      
+        INC     DE
+        JR      L0378
+
+        ;    TIME INTERRUPT
+
+TIMIN:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,AMPM
+        LD      A,(HL)
+        XOR     01H
+        LD      (HL),A
+        LD      HL,CONTF
+        LD      (HL),80H                                                 ; CONT2
+        DEC     HL
+        PUSH    HL
+        LD      E,(HL)
+        LD      D,(HL)
+        LD      HL,0A8C0H
+        ADD     HL,DE
+        DEC     HL
+        DEC     HL
+        EX      DE,HL
+        POP     HL
+        LD      (HL),E
+        LD      (HL),D
+        POP     HL
+        POP     DE
+        POP     BC
+        POP     AF
+        EI      
+        RET     
+
+        ;    SPACE PRINT AND DISP ACC
+        ;    INPUT:HL=DISP. ADR.
+
+SPHEX:  CALL    QPRTS                                                    ; SPACE PRINT
+        LD      A,(HL)
+        CALL    PRTHX                                                    ; DSP OF ACC (ASCII)
+        LD      A,(HL)
+        RET     
+
+        ;    (ASCII PRINT) FOR HL
+
+PRTHL:  LD      A,H
+        CALL    PRTHX
+        LD      A,L
+        JR      PRTHX
+
+        NOP     
+        NOP     
+
+        ;    (ASCII PRINT) FOR ACC
+
+PRTHX:  PUSH    AF
+        RRCA    
+        RRCA    
+        RRCA    
+        RRCA    
+        CALL    ASC
+        CALL    PRNT
+        POP     AF
+        CALL    ASC
+        JP      PRNT
+
+        ;    80 CHA. 1 LINE CODE (DATA)
+
+SLPT:    DB    01H                                                       ; TEXT MODE
+    DB    09H
+    DB    09H
+    DB    09H
+    DB    0DH
+
+        ;    HEXADECIMAL TO ASCII
+        ;    IN  : ACC (D3-D0)=HEXADECIMAL
+        ;    EXIT: ACC = ASCII
+ASC:    AND     0FH
+        CP      0AH
+        JR      C,NOADD
+        ADD     A,07H
+NOADD:  ADD     A,30H
+        RET     
+
+        ;    ASCII TO HEXADECIMAL
+        ;    IN  : ACC = ASCII
+        ;    EXIT: ACC = HEXADECIMAL
+        ;          CY  = 1 ERROR
+
+HEXJ:   SUB     30H
+        RET     C                                                        ; <0
+        CP      0AH
+        CCF     
+        RET     NC                                                       ; 0-9
+        SUB     07H
+        CP      10H
+        CCF     
+        RET     C
+        CP      0AH
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+HEX:    JR      HEXJ
+
+        ;    PRESS PLAY MESSAGE
+
+MSGN1:    DW    207FH
+MSGN2:    DB    "PLAY\r"
+MSGN3:    DW    207FH
+    DB    "RECORD.\r"                                                    ; PRESS RECORD
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    4 ASCII TO (HL)
+        ;    IN  DE=DATA LOW ADDRESS
+        ;    EXIT CF=0 : OK
+        ;           =1 : OUT
+
+HLHEX:  PUSH    DE
+        CALL    L2HEX
+        JR      C,L041D
+        LD      H,A
+        CALL    L2HEX
+        JR      C,L041D
+        LD      L,A
+L041D:  POP     DE
+        RET     
+
+        ;    2 ASCII TO (ACC)
+        ;    IN  DE=DATA LOW ADRRESS
+        ;    EXIT CF=0 : OK
+        ;           =1 : OUT
+
+L2HEX:  PUSH    BC
+        LD      A,(DE)
+        INC     DE
+        CALL    HEX
+        JR      C,L0434
+        RRCA    
+        RRCA    
+        RRCA    
+        RRCA    
+        LD      C,A
+        LD      A,(DE)
+        INC     DE
+        CALL    HEX
+        JR      C,L0434
+        OR      C
+L0434:  POP     BC
+        RET     
+
+        ;    WRITE INFORMATION
+
+QWRI:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D7H                                                   ; "W"
+        LD      E,0CCH                                                   ; "L"
+        LD      HL,IBUFE                                                 ; 10F0H
+        LD      BC,80H                                                   ; WRITE BYTE SIZE
+WRI1:   CALL    CKSUM                                                    ; CHECK SUM
+        CALL    MOTOR                                                    ; MOTOR ON
+        JR      C,WRI3
+        LD      A,E
+        CP      0CCH                                                     ; "L"
+        JR      NZ,WRI2
+        CALL    NL
+        PUSH    DE
+        LD      DE,MSGN7                                                 ; WRITING
+        RST     18H                                                      ; CALL MSGX
+        LD      DE,NAME                                                  ; FILE NAME
+        RST     18H                                                      ; CALL MSGX
+        POP     DE
+WRI2:   CALL    GAP
+        CALL    WTAPE
+WRI3:   JP      RET2
+
+MSGN7:    DB    "WRITING \r"
+
+        ;    40 CHA. IN 1 LINE CODE (DATA)
+
+LLPT:    DB    01H                                                       ; TEXT MODE
+    DB    09H
+    DB    09H
+    DB    0BH
+    DB    0DH
+
+        ;    WRITE DATA
+        ;    EXIT CF=0 : OK
+        ;           =1 : BREAK
+
+QWRD:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D7H                                                   ; "W"
+        LD      E,53H                                                    ; "S"
+L047D:  LD      BC,(SIZE)                                                ; WRITE DATA BYTE SIZE
+        LD      HL,(DTADR)                                               ; WRITE DATA ADDRESS
+        LD      A,B
+        OR      C
+        JR      Z,RET1
+        JR      WRI1
+
+        ;    TAPE WRITE
+        ;    BC=BYTE SIZE
+        ;    HL=DATA LOW ADDRESS
+        ;    EXIT CF=0 : OK
+        ;           =1 : BREAK
+
+WTAPE:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,02H
+        LD      A,0F8H                                                   ; 88H WOULD BE BETTER!!
+        LD      (KEYPA),A                                                ; E000H
+WTAP1:  LD      A,(HL)
+        CALL    WBYTE                                                    ; 1 BYTE WRITE
+        LD      A,(KEYPB)                                                ; E001H
+        AND     81H                                                      ; SHIFT & BREAK
+        JP      NZ,WTAP2
+        LD      A,02H                                                    ; BREAK IN CODE
+        SCF     
+        JR      WTAP3
+
+WTAP2:  INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JP      NZ,WTAP1
+        LD      HL,(SUMDT)                                               ; SUM DATA SET
+        LD      A,H
+        CALL    WBYTE
+        LD      A,L
+        CALL    WBYTE
+        CALL    LONG
+        DEC     D
+        JP      NZ,L04C2
+        OR      A
+        JP      WTAP3
+
+L04C2:  LD      B,0
+L04C4:  CALL    SHORT
+        DEC     B
+        JP      NZ,L04C4
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+        JP      WTAP1
+
+WTAP3:
+RET1:   POP     HL
+        POP     BC
+        POP     DE
+        RET     
+
+    DB    2FH
+    DB    4EH
+
+        ;    READ INFORMATION (FROM $CMT)
+        ;    EXIT ACC=0: OK CF=0
+        ;            =1: ER CF=1
+        ;            =2: BREAK CF=1
+
+QRDI:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D2H                                                   ; "R"
+        LD      E,0CCH                                                   ; "L"
+        LD      BC,80H
+        LD      HL,IBUFE
+RD1:    CALL    MOTOR
+        JP      C,RTP6
+        CALL    TMARK
+        JP      C,RTP6
+        CALL    RTAPE
+        JP      RTP4
+
+        ;    READ DATA (FROM $CMT)
+        ;    EXIT SAME UP
+
+QRDD:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D2H                                                   ; "R"
+        LD      E,53H                                                    ; "S"
+        LD      BC,(SIZE)
+        LD      HL,(DTADR)
+        LD      A,B
+        OR      C
+        JP      Z,RTP4
+        JR      RD1
+
+        ;    READ TAPE
+        ;    IN  BC=SIZE
+        ;        DE=LOAD ADDRESS
+        ;    EXIT ACC=0 : OK CF=0
+        ;            =1 : ER   =1
+        ;            =2 : BREAK=1
+ 
+RTAPE:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      H,02H                                                    ; TWICE WRITE
+RTP1:   LD      BC,KEYPB
+        LD      DE,CSTR
+RTP2:   CALL    EDGE                                                     ; 1-->0 EDGE DETECT
+        JR      C,RTP6
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)                                                   ; DATA (1 BIT) READ
+        AND     20H
+        JP      Z,RTP2
+        LD      D,H
+        LD      HL,0
+        LD      (SUMDT),HL
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+RTP3:   CALL    RBYTE                                                    ; 1 BYTE READ
+        JR      C,RTP6
+        LD      (HL),A
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,RTP3
+        LD      HL,(SUMDT)                                               ; CHECK SUM
+        CALL    RBYTE                                                    ; CHECK SUM DATA
+        JR      C,RTP6
+        LD      E,A
+        CALL    RBYTE                                                    ; CHECK SUM DATA
+        JR      C,RTP6
+        CP      L
+        JR      NZ,RTP5
+        LD      A,E
+        CP      H
+        JR      NZ,RTP5
+RTP8:   XOR     A
+RTP4:
+RET2:   POP     HL
+        POP     BC
+        POP     DE
+        CALL    MSTOP
+        PUSH    AF
+        LD      A,(TIMFG)                                                ; INT. CHECK
+        CP      0F0H
+        JR      NZ,L0563
+        EI      
+L0563:  POP     AF
+        RET     
+
+RTP5:   DEC     D
+        JR      Z,RTP7
+        LD      H,D
+        CALL    GAPCK
+        JR      RTP1
+
+RTP7:   LD      A,01H
+        JR      RTP9
+
+RTP6:   LD      A,02H
+RTP9:   SCF     
+        JR      RTP4
+
+        ;    BELL
+
+QBEL:   PUSH    DE
+        LD      DE,QBELD
+        RST     30H                                                      ; CALL MELODY
+        POP     DE
+        RET     
+
+        ;    FLASHING AND KEYIN
+        ;    EXIT: ACC INPUT KEY DATA (DSP.CODE)
+        ;    H=F0H THEN NO KEYIN (Z FLAG)
+
+FLKEY:  CALL    QFLAS
+        CALL    QKEY
+        CP      0F0H
+        RET     
+
+        NOP     
+
+        ;    VERIFY (FROM $CMT)
+        ;    EXIT ACC=0 : OK CF=0
+        ;            =1 : ER CF=1
+        ;            =2 : BREAK CF=1
+
+QVRFY:  DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      BC,(SIZE)
+        LD      HL,(DTADR)
+        LD      D,0D2H                                                   ; "R"
+        LD      E,53H                                                    ; "S"
+        LD      A,B
+        OR      C
+        JR      Z,RTP4                                                   ; END
+        CALL    CKSUM
+        CALL    MOTOR
+        JR      C,RTP6                                                   ; BRK
+        CALL    TMARK                                                    ; TAPE MARK DETECT
+        JR      C,RTP6                                                   ; BRK
+        CALL    TVRFY
+        JR      RTP4
+
+        ;    DATA VERIFY
+        ;    BC=SIZE
+        ;    HL=DATA LOW ADDRESS
+        ;    CSMDT=CHECK SUM
+        ;    EXIT ACC=0 : OK  CF=0
+        ;            =1 : ER    =1
+        ;            =2 : BREAK =1
+
+TVRFY:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      H,02H                                                    ; COMPARE TWICE
+TVF1:   LD      BC,KEYPB
+        LD      DE,CSTR
+TVF2:   CALL    EDGE
+        JP      C,RTP6                                                   ; BRK
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JP      Z,TVF2
+        LD      D,H
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+        ;    COMPARE TAPE DATA AND STORAGE
+TVF3:   CALL    RBYTE
+        JR      C,RTP6                                                   ; BRK
+        CP      (HL)
+        JR      NZ,RTP7                                                  ; ERROR, NOT EQUAL
+        INC     HL                                                       ; STORAGE ADDRESS + 1
+        DEC     BC                                                       ; SIZE - 1
+        LD      A,B
+        OR      C
+        JR      NZ,TVF3
+        ;    COMPARE CHECK SUM (1199H/CSMDT) AND TAPE
+        LD      HL,(CSMDT)
+        CALL    RBYTE
+        CP      H
+        JR      NZ,RTP7                                                  ; ERROR, NOT EQUAL
+        CALL    RBYTE
+        CP      L
+        JR      NZ,RTP7                                                  ; ERROR, NOT EQUAL
+        DEC     D                                                        ; NUMBER OF COMPARES (2) - 1
+        JP      Z,RTP8                                                   ; OK, 2 COMPARES
+        LD      H,D                                                      ; (-->05C7H), SAVE NUMBER OF COMPARES
+        JR      TVF1                                                     ; NEXT COMPARE
+
+        ;    FLASHING DATA LOAD
+
+QLOAD:  PUSH    AF
+        LD      A,(FLASH)
+        CALL    QPONT
+        LD      (HL),A
+        POP     AF
+        RET     
+
+        ;    NEW LINE AND PRINT HL REG (ASCII)
+
+NLPHL:  CALL    NL
+        CALL    PRTHL
+        RET     
+
+        ;    EDGE (TAPE DATA EDGE DETECT)
+        ;    BC=KEYPB (E001H)
+        ;    DE=CSTR  (E002H)
+        ;    EXIT CF=0 OK   CF=1 BREAK
+
+EDGE:   LD      A,0F8H                                                   ; BREAK KEY IN (88H WOULD BE BETTER!!) 
+        LD      (KEYPA),A
+        NOP     
+EDG1:   LD      A,(BC)
+        AND     81H                                                      ; SHIFT & BREAK
+        JR      NZ,L060E
+        SCF     
+        RET     
+
+L060E:  LD      A,(DE)
+        AND     20H
+        JR      NZ,EDG1                                                  ; CSTR D5 = 0
+EDG2:   LD      A,(BC)                                                   ; 8
+        AND     81H                                                      ; 9
+        JR      NZ,L061A                                                 ; 10/14
+        SCF     
+        RET     
+
+L061A:  LD      A,(DE)                                                   ; 8
+        AND     20H                                                      ; 9
+        JR      Z,EDG2                                                   ; CSTR D5 = 1  10/14
+        RET                                                              ; 11
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        ;    1 BYTE READ
+        ;    EXIT SUMDT=STORE
+        ;    CF=1 : BREAK
+        ;    CF=0 : DATA=ACC
+
+RBYTE:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,0800H                                                 ; 8 BITS
+        LD      BC,KEYPB                                                 ; KEY DATA E001H
+        LD      DE,CSTR                                                  ; $TAPE DATA E002H
+RBY1:   CALL    EDGE                                                     ; 41 OR 101
+        JP      C,RBY3                                                   ; 13 (SHIFT & BREAK)
+        CALL    DLY3                                                     ; 20+18*63+33
+        LD      A,(DE)                                                   ; DATA READ :8
+        AND     20H
+        JP      Z,RBY2                                                   ; 0
+        PUSH    HL
+        LD      HL,(SUMDT)
+        INC     HL                                                       ; CHECK SUM                                ; COUNT HIGH BITS ON TAPE
+        LD      (SUMDT),HL
+        POP     HL
+        SCF     
+RBY2:   LD      A,L                                                      ; BUILD CHAR
+        RLA     
+        LD      L,A
+        DEC     H                                                        ; BITCOUNT-1
+        JP      NZ,RBY1
+        CALL    EDGE
+        LD      A,L                                                      ; CHAR READ
+RBY3:   POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+
+        ;    TAPE MARK DETECT
+        ;    E=@L@ : INFORMATION
+        ;     =@S@ : DATA
+        ;    EXIT CF=0 OK
+        ;           =1 BREAK
+
+TMARK:  CALL    GAPCK
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,2828H
+        LD      A,E
+        CP      0CCH                                                     ; "L"
+        JR      Z,L066C
+        LD      HL,1414H
+L066C:  LD      (TMCNT),HL
+        LD      BC,KEYPB
+        LD      DE,CSTR
+TM1:    LD      HL,(TMCNT)
+TM2:    CALL    EDGE
+        JR      C,TM4
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JR      Z,TM1
+        DEC     H
+        JR      NZ,TM2
+TM3:    CALL    EDGE
+        JR      C,TM4
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JR      NZ,TM1
+        DEC     L
+        JR      NZ,TM3
+        CALL    EDGE
+TM4:
+RET3:   POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+        ;    MOTOR ON
+        ;    IN  D=@W@ :WRITE
+        ;         =@R@ :READ
+        ;    EXIT CF=0 OK
+        ;           =1 BREAK
+        ;
+        ; If the button is pressed, 
+
+MOTOR:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      B,0AH                                                    ; Pulse motor upto 10 times if sense is low. Each pulse flips on->off or off->on
+MOT1:   LD      A,(CSTR)                                                 ; Check sense, if low then pulse motor to switch it on.
+        AND     10H
+        JR      Z,MOT4                                                   ; If NZ (bit PC4 is high), then wait a bit and return, motor running.
+                                                                         ; If Z then pulse the motor on circuit.
+MOT2:   LD      B,0FFH                                                   ; 2 SEC DELAY 
+L06AD:  CALL    DLY12                                                    ; 7 MSEC DELAY
+        JR      L06B4                                                    ; MOTOR ENTRY ADJUST
+
+        JR      MOTOR                                                    ; ORG 06B2H
+
+L06B4:  DJNZ    L06AD
+        XOR     A
+MOT7:   JR      RET3
+
+MOT4:   LD      A,06H                                                    ;  
+        LD      HL,CSTPT                                                 ; 8255 Control register
+        LD      (HL),A                                                   ; Set PC3 low
+        INC     A
+        LD      (HL),A                                                   ; Set PC3 high
+        DJNZ    MOT1                                                     ; Check to see if sense now active.
+        CALL    NL                                                       ; Sense not active so play button hasnt been pressed.
+        LD      A,D                                                      ; Determine if we are Loading or Saving, display correct message.
+        CP      0D7H                                                     ; "W"
+        JR      Z,MOT8
+        LD      DE,MSGN1                                                 ; PLAY MARK
+        JR      MOT9
+
+MOT8:   LD      DE,MSGN3                                                 ; "RECORD."
+        RST     18H                                                      ; CALL MSGX
+        LD      DE,MSGN2                                                 ; "PLAY"
+MOT9:   RST     18H                                                      ; CALL MSGX
+MOT5:   LD      A,(CSTR)                                                 ; Check sense input and wait until it is high.
+        AND     10H
+        JR      NZ,MOT2
+        CALL    QBRK                                                     ; If sense is low, check for User Key Break entry.
+        JR      NZ,MOT5
+        SCF     
+        JR      MOT7   
+
+        ;    INITIAL MESSAGE
+
+MSGQ3:    DB    "**  MONITOR 1Z-013A  **\r"
+    NOP
+
+        ;    MOTOR STOP
+
+MSTOP:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        LD      B,0AH
+MST1:   LD      A,(CSTR)
+        AND     10H
+        JR      Z,MST3
+        LD      A,06H
+        LD      (CSTPT),A
+        INC     A
+        LD      (CSTPT),A
+        DJNZ    MST1
+MST3:   JP      QRSTR1
+
+        ;    CHECK SUM
+        ;    IN   BC=SIZE
+        ;         HL=DATA ADDRESS
+        ;    EXIT SUMDT=STORE
+        ;         CSMDT=STORE
+
+CKSUM:  PUSH    BC
+        PUSH    DE
+L071C:  PUSH    HL
+        LD      DE,0
+CKS1:   LD      A,B
+        OR      C
+        JR      NZ,CKS2
+        EX      DE,HL
+L0725:  LD      (SUMDT),HL                                               ; NUMBER OF HIGHBITS IN DATA
+        LD      (CSMDT),HL
+        POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+CKS2:   LD      A,(HL)
+        PUSH    BC
+        LD      B,8
+CKS3:   RLCA    
+        JR      NC,L0737
+        INC     DE
+L0737:  DJNZ    CKS3
+L0739:  POP     BC
+        INC     HL
+        DEC     BC
+        JR      CKS1
+
+        ;    MODE SET OF KEYPORT
+
+QMODE:  LD      HL,KEYPF
+        LD      (HL),8AH                                                 ; 10001010 CTRL WORD MODE0
+        LD      (HL),07H                                                 ; PC3=1 M-ON
+        LD      (HL),05H                                                 ; PC2=1 INTMSK
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    107 MICRO SEC DELAY
+
+DLY1:   LD      A,15H                                                    ; 18*21+20
+L075B:  DEC     A
+        JP      NZ,L075B
+        RET     
+
+DLY2:   LD      A,13H                                                    ; 18*19+20
+L0762:  DEC     A
+        JP      NZ,L0762
+        RET     
+
+        ;    1 BYTE WRITE
+
+WBYTE:  PUSH    BC
+        LD      B,8
+        CALL    LONG
+WBY1:   RLCA    
+        CALL    C,LONG
+        CALL    NC,SHORT
+        DEC     B
+        JP      NZ,WBY1
+        POP     BC
+        RET     
+
+        ;    GAP + TAPEMARK
+        ;    E=@L@ LONG GAP
+        ;     =@s@ SHORT GAP
+
+GAP:    PUSH    BC
+        PUSH    DE
+        LD      A,E
+        LD      BC,55F0H
+        LD      DE,2828H
+        CP      0CCH                                                     ; "L"
+        JP      Z,GAP1
+        LD      BC,2AF8H
+        LD      DE,1414H
+GAP1:   CALL    SHORT
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,GAP1
+GAP2:   CALL    LONG
+        DEC     D
+        JR      NZ,GAP2
+GAP3:   CALL    SHORT
+        DEC     E
+        JR      NZ,GAP3
+        CALL    LONG
+        POP     DE
+        POP     BC
+        RET     
+
+        ;    MEMORY CORRECTION
+        ;    COMMAND "M"
+
+MCOR:   CALL    HEXIY                                                    ; CORRECTION ADDRESS
+MCR1:   CALL    NLPHL                                                    ; CORRECTION ADDRESS PRINT
+        CALL    SPHEX                                                    ; ACC-->ASCII DISP.
+        CALL    QPRTS                                                    ; SPACE PRINT
+        CALL    BGETL                                                    ; GET DATA & CHECK DATA
+        CALL    HLHEX                                                    ; HL<--ASCII(DE)
+        JR      C,MCR3
+        CALL    P4DE                                                     ; (INC DE)*4
+        INC     DE
+        CALL    L2HEX                                                    ; DATA CHECK
+        JR      C,MCR1
+        CP      (HL)
+        JR      NZ,MCR1
+        INC     DE
+        LD      A,(DE)
+        CP      0DH                                                      ; NOT CORRECTION ?
+        JR      Z,MCR2
+        CALL    L2HEX                                                    ; ACC<--HL(ASCII)
+        JR      C,MCR1
+        LD      (HL),A                                                   ; DATA CORRECT
+MCR2:   INC     HL
+        JR      MCR1
+
+MCR3:   LD      H,B                                                      ; MEMORY ADDRESS
+        LD      L,C
+        JR      MCR1
+
+    DB    "(HL)"
+    DB    0F1H
+    DB    9EH
+    DB    "SUB ("
+
+        ;    GET 1 LINE STATEMENT *
+        ;    DE=DATA STORE LOW ADDRESS
+        ;    (END=CR)
+
+QGETL:  PUSH    AF
+        PUSH    BC
+        PUSH    HL
+        PUSH    DE
+GETL1:  CALL    QQKEY                                                    ; ENTRY KEY
+AUTO3:  PUSH    AF                                                       ; IN KEY DATA SAVE
+        LD      B,A
+        LD      A,(SWRK)                                                 ; BELL WORK
+        RRCA    
+        CALL    NC,QBEL                                                  ; ENTRY BELL
+        LD      A,B
+        LD      HL,KANAF                                                 ; KANA & GRAPH FLAGS
+        AND     0F0H
+        CP      0C0H
+        POP     DE                                                       ; EREG=FLAGREG
+        LD      A,B
+        JR      NZ,GETL2                                                 ; NOT C0H
+        CP      0CDH                                                     ; CR
+        JR      Z,GETL3
+        CP      0CBH                                                     ; BREAK
+        JP      Z,GETLC
+        CP      0CFH                                                     ; NIKO MARK WH.
+        JR      Z,GETL2
+        CP      0C7H                                                     ; CRT EDITION
+        JR      NC,GETL5                                                 ; <=C7H
+        RR      E                                                        ; >C7H & CFLAG, CY ? GRAPHIC MODE,CURS.DISPL.
+        LD      A,B
+        JR      NC,GETL5
+GETL2:  CALL    QDSP                                                     ; DISPL.
+        JR      GETL1
+
+GETL5:  CALL    QDPCT                                                    ; CRT CONTROL
+        JR      GETL1
+
+        ;    BREAK IN
+
+GETLC:  POP     HL
+        PUSH    HL
+        LD      (HL),1BH                                                 ; BREAK CODE
+        INC     HL
+        LD      (HL),0DH
+        JR      GETLR
+
+        ;    GETLA
+
+GETLA:  RRCA                                                             ; CY<--D7
+        JR      NC,GETL6
+        JR      GETLB
+
+        ;    DELAY 7 MSEC AND SWEP
+
+DSWEP:  CALL    DLY12
+        CALL    QSWEP
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+GETL3:  CALL    PMANG                                                    ; CR
+        LD      B,80                                                     ; 1 LINE
+        JR      NC,GETLA
+        DEC     H                                                        ; BEFORE LINE
+GETLB:  LD      B,160                                                    ; 2 LINE
+GETL6:  LD      L,0
+        CALL    QPNT1
+        POP     DE                                                       ; STORE TOP ADDRESS
+        PUSH    DE
+GETLZ:  LD      A,(HL)
+        CALL    QDACN
+        LD      (DE),A
+        INC     HL
+        INC     DE
+        DJNZ    GETLZ
+        EX      DE,HL
+GETLU:  LD      (HL),0DH
+        DEC     HL
+        LD      A,(HL)
+        CP      20H                                                      ; SPACE THEN CR
+
+        ;    CR AND NEW LINE
+
+        JR      Z,GETLU
+
+        ;    NEW LINE RETURN
+
+GETLR:  CALL    QLTNL
+        POP     DE
+        POP     HL
+        POP     BC
+        POP     AF
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    MESSAGE PRINT
+        ;    DE PRINT DATA LOW ADDRESS
+        ;    END=CR
+
+QMSG:   PUSH    AF
+        PUSH    BC
+        PUSH    DE
+MSG1:   LD      A,(DE)
+        CP      0DH                                                      ; CR
+        JR      Z,MSGX2
+        CALL    QPRNT
+        INC     DE
+        JR      MSG1
+
+        ;    ALL PRINT MESSAGE
+
+QMSGX:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+MSGX1:  LD      A,(DE)
+        CP      0DH
+MSGX2:  JP      Z,QRSTR1
+        CALL    QADCN
+        CALL    PRNT3
+        INC     DE
+        JR      MSGX1
+
+        ;    TOP OF KEYTBLS
+
+QKYSM:  LD      DE,KTBLS                                                 ; SHIFT ALSO
+        JR      QKY5
+
+        ;    BREAK CODE IN
+
+NBRK:   LD      A,0CBH                                                   ; BREAK CODE
+        OR      A
+        JR      QKY1
+
+        ;    GETKEY
+        ;    NO ECHO BACK
+        ;    EXIT ACC=ASCII CODE
+
+QGET:   CALL    QKEY                                                     ; KEY IN (DISPLAY CODE)
+        SUB     0F0H                                                     ; NOT KEYIN CODE
+        RET     Z
+        ADD     A,0F0H
+        JP      QDACN                                                    ; DISPLAY TO ASCII CODE
+
+        NOP     
+        NOP     
+
+        ;    1 KEY INPUT
+        ;    IN   B=KEY MODE (SHIFT, CTRL, BREAK)
+        ;         C=KEY DATA (COLUMN & ROW)
+        ;    EXIT ACC=DISPLAY CODE
+        ;         IF NO KEY  ACC=F0H
+        ;         IF CY=1 THEN ATTRIBUTE ON
+        ;                      (SMALL, HIRAKANA)
+
+QKEY:   PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        CALL    DSWEP                                                    ; DELAY AND KEY SWEP
+        LD      A,B
+        RLCA    
+        JR      C,QKY2
+        LD      A,0F0H                                                   ; SHIFT OR CTRL HERE
+QKY1:   POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+QKY2:   LD      DE,KTBL                                                  ; NORMAL KEY TABLE
+        LD      A,B
+        CP      88H                                                      ; BREAK IN (SHIFT & BRK)
+        JR      Z,NBRK
+        LD      H,0                                                      ; HL=ROW & COLUMN
+        LD      L,C
+        BIT     5,A                                                      ; CTRL CHECK
+        JR      NZ,L08F7                                                 ; YES, CTRL
+        LD      A,(KANAF)                                                ; 0=NR., 1=GRAPH
+        RRCA    
+        JP      C,QKYGRP                                                 ; GRAPH MODE
+        LD      A,B                                                      ; CTRL KEY CHECK
+        RLA     
+        RLA     
+        JR      C,QKYSM
+        JR      QKY5
+
+L08F7:  LD      DE,KTBLC                                                 ; CONTROL KEY TABLE
+QKY5:   ADD     HL,DE                                                    ; TABLE
+QKY55:  LD      A,(HL)
+        JR      QKY1
+
+QKYGRP: BIT     6,B
+        JR      Z,QKYGRS
+        LD      DE,KTBLG
+        ADD     HL,DE
+        SCF     
+        JR      QKY55
+
+QKYGRS: LD      DE,KTBLGS
+        JR      QKY5
+
+        ;    NEWLINE
+
+QLTNL:  XOR     A
+        LD      (DPRNT),A                                                ; ROW POINTER
+        LD      A,0CDH                                                   ; CR
+        JR      PRNT5
+
+        NOP     
+        NOP     
+
+QNL:    LD      A,(DPRNT)
+        OR      A
+        RET     Z
+        JR      QLTNL
+
+        NOP     
+
+        ;    PRINT SPACE
+
+QPRTS:  LD      A,20H
+        JR      QPRNT
+
+        ;    PRINT TAB
+
+QPRTT:  CALL    PRNTS
+        LD      A,(DPRNT)
+        OR      A
+        RET     Z
+L092C:  SUB     10
+        JR      C,QPRTT
+        JR      NZ,L092C
+        NOP     
+        NOP     
+        NOP     
+
+        ;    PRINT
+        ;    IN ACC=PRINT DATA (ASCII)
+
+QPRNT:  CP      0DH                                                      ; CR
+        JR      Z,QLTNL
+        PUSH    BC
+        LD      C,A
+        LD      B,A
+        CALL    QPRT
+        LD      A,B
+        POP     BC
+        RET     
+
+MSGOK:    DB    "OK!\r"
+
+        ;    PRINT ROUTINE
+        ;    1 CHARACTER
+        ;    INPUT:C=ASCII DATA (QDSP+QDPCT)
+
+QPRT:    LD    A,C 
+        CALL    QADCN                                                    ; ASCII TO DSPLAY
+        LD      C,A
+        CP      0F0H
+        RET     Z                                                        ; ZERO=ILLEGAL DATA
+        AND     0F0H                                                     ; MSD CHECK
+        CP      0C0H
+        LD      A,C
+        JR      NZ,PRNT3
+        CP      0C7H
+        JR      NC,PRNT3                                                 ; CRT EDITOR
+PRNT5:  CALL    QDPCT
+        CP      0C3H                                                     ; "->"
+        JR      Z,PRNT4
+        CP      0C5H                                                     ; HOME
+        JR      Z,PRNT2
+        CP      0C6H                                                     ; CLR
+        RET     NZ
+PRNT2:  XOR     A
+L0968:  LD      (DPRNT),A
+        RET     
+
+PRNT3:  CALL    QDSP
+PRNT4:  LD      A,(DPRNT)                                                ; TAB POINT+1
+        INC     A
+        CP      80
+        JR      C,L0968
+        SUB     80
+        JR      L0968
+
+        ;    FLASHING BYPASS 1
+
+FLAS1:  LD      A,(FLASH)
+        JR      FLAS2
+
+        ;    BREAK SUBROUTINE BYPASS 1
+        ;    CTRL OR NOT KEY
+
+QBRK2:  BIT     5,A                                                      ; NOT OR CTRL
+        JR      Z,QBRK3                                                  ; CTRL
+        OR      A                                                        ; NOTKEY A=7FH
+        RET     
+
+QBRK3:  LD      A,20H                                                    ; CTRL D5=1
+        OR      A                                                        ; ZERO FLG CLR
+        SCF     
+        RET     
+
+MSGSV:    DB    "FILENAME? "
+    DB    0DH
+
+        ;    DLY 7 MSEC
+DLY12:  PUSH    BC
+        LD      B,15H
+L0999:  CALL    DLY3
+        DJNZ    L0999
+        POP     BC
+        RET     
+
+        ;    LOADING MESSAGE
+
+MSGQ2:    DB    "LOADING \r"
+
+        ;    DELAY FOR LONG PULSE
+
+DLY4:   LD      A,59H                                                    ; 18*89+20
+L09AB:  DEC     A
+        JP      NZ,L09AB
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+
+        ;    KEY BOARD SEARCH
+        ;    & DISPLAY CODE CONVERSION
+        ;    EXIT A=DISPLAY CODE
+        ;         CY=GRAPH MODE
+        ;    WITH CURSOR DISPLAY
+
+QQKEY:  PUSH    HL
+        CALL    QSAVE
+KSL1:   CALL    FLKEY                                                    ; KEY
+        JR      NZ,KSL1                                                  ; KEY IN THEN JUMP
+KSL2:   CALL    FLKEY
+        JR      Z,KSL2                                                   ; NOT KEY IN THEN JUMP
+        LD      H,A
+        CALL    DLY12                                                    ; DELAY CHATTER
+        CALL    QKEY
+        PUSH    AF
+        CP      H                                                        ; CHATTER CHECK
+        POP     HL
+        JR      NZ,KSL2
+        PUSH    HL
+        POP     AF                                                       ; IN KEY DATA
+        CALL    QLOAD                                                    ; FLASHING DATA LOAD
+        POP     HL
+        RET     
+
+        ;    CLEAR 2
+
+NCLR08: XOR     A                                                        ; CY FLAG
+NCLR8:  LD      BC,0800H
+CLEAR:  PUSH    DE                                                       ; BC=CLR BYTE SIZE, A=CLR DATA
+        LD      D,A
+CLEAR1: LD      (HL),D
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,CLEAR1
+        POP     DE
+        RET     
+
+        ;    FLASHING 2
+
+QFLS:   PUSH    AF
+        PUSH    HL
+        LD      A,(KEYPC)
+        RLCA    
+        RLCA    
+        JR      C,FLAS1
+        LD      A,(FLSDT)
+FLAS2:  CALL    QPONT                                                    ; DISPLAY POSITION
+        LD      (HL),A
+        POP     HL
+        POP     AF
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+QFLAS:  JR      QFLS
+
+        ;    SHORT AND LONG PULSE FOR 1 BIT WRITE
+
+SHORT:  PUSH    AF                                                       ; 12
+        LD      A,03H                                                    ; 9
+        LD      (CSTPT),A                                                ; E003H PC3=1:16
+        CALL    DLY1                                                     ; 20+18*21+20
+        CALL    DLY1                                                     ; 20+18*21+20
+        LD      A,02H                                                    ; 9
+        LD      (CSTPT),A                                                ; E003H PC3=0:16
+        CALL    DLY1                                                     ; 20+18*21+20
+        CALL    DLY1                                                     ; 20+18*21+20
+        POP     AF                                                       ; 11
+        RET                                                              ; 11
+
+LONG:   PUSH    AF                                                       ; 11
+        LD      A,03H                                                    ; 9
+        LD      (CSTPT),A                                                ; 16
+        CALL    DLY4                                                     ; 20+18*89+20
+        LD      A,02H                                                    ; 9
+        LD      (CSTPT),A                                                ; 16
+        CALL    DLY4                                                     ; 20+18*89+20
+        POP     AF                                                       ; 11
+        RET                                                              ; 11
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    BREAK KEY CHECK
+        ;    AND SHIFT, CTRL KEY CHECK
+        ;    EXIT BREAK ON : ZERO=1
+        ;               OFF: ZERO=0
+        ;         NO KEY   : CY  =0
+        ;         KEY IN   : CY  =1
+        ;          A D6=1  : SHIFT ON
+        ;              =0  :       OFF
+        ;            D5=1  : CTRL ON
+        ;              =0  :      OFF
+        ;        D4=1  : SHIFT+CNT ON
+        ;          =0  :           OFF
+
+QBRK:   LD      A,0F8H                                                   ; LINE 8SWEEP
+        LD      (KEYPA),A
+        NOP     
+        LD      A,(KEYPB)
+        OR      A
+        RRA     
+        JP      C,QBRK2                                                  ; SHIFT ?
+        RLA     
+        RLA     
+        JR      NC,QBRK1                                                 ; BREAK ?
+        LD      A,40H                                                    ; SHIFT D6=1
+        SCF     
+        RET     
+
+QBRK1:  XOR     A                                                        ; SHIFT ?
+        RET     
+
+        ;    320 U SEC DELAY
+
+DLY3:   LD      A,3FH                                                    ; 18*63+33
+        JP      L0762                                                    ; JP DLY2+2
+
+        NOP     
+
+        ;    KEY BOARD SWEEP
+        ;    EXIT B,D7=0  NO DATA
+        ;             =1  DATA
+        ;           D6=0  SHIFT OFF
+        ;         =1  SHIFT ON
+        ;           D5=0  CTRL OFF
+        ;         =1  CTRL ON
+        ;           D4=0  SHIFT+CTRL OFF
+        ;         =1  SHIFT+CTRL ON
+        ;         C   = ROW & COLUMN
+        ;        7 6 5 4 3 2 1 0
+        ;        * * ^ ^ ^ < < <
+
+QSWEP:  PUSH    DE
+        PUSH    HL
+        XOR     A
+        LD      B,0F8H
+        LD      D,A
+        CALL    QBRK
+        JR      NZ,SWEP6
+        LD      D,88H                                                    ; BREAK ON
+        JR      SWEP9
+
+SWEP6:  JR      NC,SWEP0
+        LD      D,A
+        JR      SWEP0
+
+SWEP01: SET     7,D
+SWEP0:  DEC     B
+        LD      A,B
+        LD      (KEYPA),A
+        CP      0EFH                                                     ; MAP SWEEP END ?
+        JR      NZ,SWEP3
+        CP      0F8H                                                     ; BREAK KEY ROW
+        JR      Z,SWEP0
+SWEP9:  LD      B,D
+        POP     HL
+        POP     DE
+        RET     
+
+SWEP3:  LD      A,(KEYPB)
+        CPL     
+        OR      A
+        JR      Z,SWEP0
+        LD      E,A
+SWEP2:  LD      H,8
+        LD      A,B
+        AND     0FH
+        RLCA    
+        RLCA    
+        RLCA    
+        LD      C,A
+        LD      A,E
+L0A89:  DEC     H
+        RRCA    
+        JR      NC,L0A89
+        LD      A,H
+        ADD     A,C
+        LD      C,A
+        JR      SWEP01
+        ;
+        ;
+        ;   ASCII TO DISPLAY CODE TABL
+        ;
+ATBL:    
+        ;  00 - 0F
+    DB    0F0H                                                           ; ^ @
+    DB    0F0H                                                           ; ^ A
+    DB    0F0H                                                           ; ^ B
+    DB    0F3H                                                           ; ^ C
+    DB    0F0H                                                           ; ^ D
+    DB    0F5H                                                           ; ^ E
+    DB    0F0H                                                           ; ^ F
+    DB    0F0H                                                           ; ^ G
+    DB    0F0H                                                           ; ^ H
+    DB    0F0H                                                           ; ^ I
+    DB    0F0H                                                           ; ^ J
+    DB    0F0H                                                           ; ^ K
+    DB    0F0H                                                           ; ^ L
+    DB    0F0H                                                           ; ^ M
+    DB    0F0H                                                           ; ^ N
+    DB    0F0H                                                           ; ^ O
+        ;  10 - 1F
+    DB    0F0H                                                           ; ^ P
+    DB    0C1H                                                           ; ^ Q CUR. DOWN
+    DB    0C2H                                                           ; ^ R CUR. UP
+    DB    0C3H                                                           ; ^ S CUR. RIGHT
+    DB    0C4H                                                           ; ^ T CUR. LEFT
+    DB    0C5H                                                           ; ^ U HOME
+    DB    0C6H                                                           ; ^ V CLEAR
+    DB    0F0H                                                           ; ^ W
+    DB    0F0H                                                           ; ^ X
+    DB    0F0H                                                           ; ^ Y
+    DB    0F0H                                                           ; ^ Z SEP.
+    DB    0F0H                                                           ; ^ [
+    DB    0F0H                                                           ; ^ \
+    DB    0F0H                                                           ; ^ ]
+    DB    0F0H                                                           ; ^ ^
+    DB    0F0H                                                           ; ^ -
+        ;  20 - 2F
+    DB    00H                                                            ; SPACE
+    DB    61H                                                            ; !
+    DB    62H                                                            ; "
+    DB    63H                                                            ; #
+    DB    64H                                                            ; $
+    DB    65H                                                            ; %
+    DB    66H                                                            ; &
+    DB    67H                                                            ; '
+    DB    68H                                                            ; (
+    DB    69H                                                            ; )
+    DB    6BH                                                            ; *
+    DB    6AH                                                            ; +
+    DB    2FH                                                            ; ,
+    DB    2AH                                                            ; -
+    DB    2EH                                                            ; .
+    DB    2DH                                                            ; /
+        ;  30 - 3F
+    DB    20H                                                            ; 0
+    DB    21H                                                            ; 1
+    DB    22H                                                            ; 2
+    DB    23H                                                            ; 3
+    DB    24H                                                            ; 4
+    DB    25H                                                            ; 5
+    DB    26H                                                            ; 6
+    DB    27H                                                            ; 7
+    DB    28H                                                            ; 8
+    DB    29H                                                            ; 9
+    DB    4FH                                                            ; :
+    DB    2CH                                                            ;         ;
+    DB    51H                                                            ; <
+    DB    2BH                                                            ; =
+    DB    57H                                                            ; >
+    DB    49H                                                            ; ?
+        ;  40 - 4F
+    DB    55H                                                            ; @
+    DB    01H                                                            ; A
+    DB    02H                                                            ; B
+    DB    03H                                                            ; C
+    DB    04H                                                            ; D
+    DB    05H                                                            ; E
+    DB    06H                                                            ; F
+    DB    07H                                                            ; G
+    DB    08H                                                            ; H
+    DB    09H                                                            ; I
+    DB    0AH                                                            ; J
+    DB    0BH                                                            ; K
+    DB    0CH                                                            ; L
+    DB    0DH                                                            ; M
+    DB    0EH                                                            ; N
+    DB    0FH                                                            ; O
+        ;  50 - 5F
+    DB    10H                                                            ; P
+    DB    11H                                                            ; Q
+    DB    12H                                                            ; R
+    DB    13H                                                            ; S
+    DB    14H                                                            ; T
+    DB    15H                                                            ; U
+    DB    16H                                                            ; V
+    DB    17H                                                            ; W
+    DB    18H                                                            ; X
+    DB    19H                                                            ; Y
+    DB    1AH                                                            ; Z
+    DB    52H                                                            ; [
+    DB    59H                                                            ; \
+    DB    54H                                                            ; ]
+    DB    50H                                                            ; 
+    DB    45H                                                            ; 
+        ;  60 - 6F
+    DB    0C7H                                                           ; UFO
+    DB    0C8H
+    DB    0C9H
+    DB    0CAH
+    DB    0CBH
+    DB    0CCH
+    DB    0CDH
+    DB    0CEH
+    DB    0CFH
+    DB    0DFH
+    DB    0E7H
+    DB    0E8H
+    DB    0E5H
+    DB    0E9H
+    DB    0ECH
+    DB    0EDH
+        ;  70 - 7F
+    DB    0D0H
+    DB    0D1H
+    DB    0D2H
+    DB    0D3H
+    DB    0D4H
+    DB    0D5H
+    DB    0D6H
+    DB    0D7H
+    DB    0D8H
+    DB    0D9H
+    DB    0DAH
+    DB    0DBH
+    DB    0DCH
+    DB    0DDH
+    DB    0DEH
+    DB    0C0H
+        ;  80 - 8F
+    DB    80H                                                            ; }
+    DB    0BDH
+    DB    9DH
+    DB    0B1H
+    DB    0B5H
+    DB    0B9H
+    DB    0B4H
+    DB    9EH
+    DB    0B2H
+    DB    0B6H
+    DB    0BAH
+    DB    0BEH
+    DB    9FH
+    DB    0B3H
+    DB    0B7H
+    DB    0BBH
+        ;  90 - 9F
+    DB    0BFH                                                           ; _
+    DB    0A3H
+    DB    85H
+    DB    0A4H                                                           ; `
+    DB    0A5H                                                           ; ~
+    DB    0A6H
+    DB    94H
+    DB    87H
+    DB    88H
+    DB    9CH
+    DB    82H
+    DB    98H
+    DB    84H
+    DB    92H
+    DB    90H
+    DB    83H
+        ;  A0 - AF
+    DB    91H
+    DB    81H
+    DB    9AH
+    DB    97H
+    DB    93H
+    DB    95H
+    DB    89H
+    DB    0A1H
+    DB    0AFH
+    DB    8BH
+    DB    86H
+    DB    96H
+    DB    0A2H
+    DB    0ABH
+    DB    0AAH
+    DB    8AH
+        ;  B0 - BF
+    DB    8EH
+    DB    0B0H
+    DB    0ADH
+    DB    8DH
+    DB    0A7H
+    DB    0A8H
+    DB    0A9H
+    DB    8FH
+    DB    8CH
+    DB    0AEH
+    DB    0ACH
+    DB    9BH
+    DB    0A0H
+    DB    99H
+    DB    0BCH                                                           ; {
+    DB    0B8H
+        ;  C0 - CF
+    DB    40H
+    DB    3BH
+    DB    3AH
+    DB    70H
+    DB    3CH
+    DB    71H
+    DB    5AH
+    DB    3DH
+    DB    43H
+    DB    56H
+    DB    3FH
+    DB    1EH
+    DB    4AH
+    DB    1CH
+    DB    5DH
+    DB    3EH
+        ;  D0 - DF
+    DB    5CH
+    DB    1FH
+    DB    5FH
+    DB    5EH
+    DB    37H
+    DB    7BH
+    DB    7FH
+    DB    36H
+    DB    7AH
+    DB    7EH
+    DB    33H
+    DB    4BH
+    DB    4CH
+    DB    1DH
+    DB    6CH
+    DB    5BH
+        ;  E0 - EF
+    DB    78H
+    DB    41H
+    DB    35H
+    DB    34H
+    DB    74H
+    DB    30H
+    DB    38H
+    DB    75H
+    DB    39H
+    DB    4DH
+    DB    6FH
+    DB    6EH
+    DB    32H
+    DB    77H
+    DB    76H
+    DB    72H
+        ;  F0 - FF
+    DB    73H
+    DB    47H
+    DB    7CH
+    DB    53H
+    DB    31H
+    DB    4EH
+    DB    6DH
+    DB    48H
+    DB    46H
+    DB    7DH
+    DB    44H
+    DB    1BH
+    DB    58H
+    DB    79H
+    DB    42H
+    DB    60H
+
+        ;    FLASHING DATA SAVE
+
+QSAVE:  LD      HL,FLSDT
+        LD      (HL),0EFH                                                ; NORMAL CURSOR
+        LD      A,(KANAF)
+        RRCA    
+        JR      C,L0BA0                                                  ; GRAPH MODE
+        RRCA    
+        JR      NC,SV0                                                   ; NORMAL MODE
+L0BA0:  LD      (HL),0FFH                                                ; GRAPH CURSOR
+SV0:    LD      A,(HL)
+        PUSH    AF
+        CALL    QPONT                                                    ; FLASHING POSITION
+        LD      A,(HL)
+        LD      (FLASH),A
+        POP     AF
+        LD      (HL),A
+        XOR     A
+        LD      HL,KEYPA
+L0BB1:  LD      (HL),A
+        CPL                                                              ; OH NO! UNUSED BITS WERE TOUCHED TOO!!!
+        LD      (HL),A
+        RET     
+
+SV1:    LD      (HL),43H                                                 ; KANA CURSOR
+        JR      SV0
+
+        ;    ASCII TO DISPLAY CODE CONVERT
+        ;    IN ACC:ASCII
+        ;    EXIT ACC:DISPLAY CODE
+
+QADCN:  PUSH    BC
+        PUSH    HL
+        LD      HL,ATBL
+        LD      C,A
+        LD      B,0
+        ADD     HL,BC
+        LD      A,(HL)
+        JR      DACN3
+
+VRNS:    DB    "V1.0A\r"                                                 ; VERSION MANAGEMENT
+        NOP     
+        NOP     
+        NOP     
+
+        ;    DISPLAY CODE TO ASCII CONVERSION
+        ;    IN ACC=DISPLAY CODE
+        ;    EXIT ACC=ASCII
+
+QDACN:  PUSH    BC
+        PUSH    HL
+        PUSH    DE
+        LD      HL,ATBL
+        LD      D,H
+        LD      E,L
+        LD      BC,0100H
+        CPIR    
+        JR      Z,DACN1
+        LD      A,0F0H
+DACN2:  POP     DE
+DACN3:  POP     HL
+        POP     BC
+        RET     
+
+DACN1:  OR      A
+        DEC     HL
+        SBC     HL,DE
+        LD      A,L
+        JR      DACN2
+
+        ;
+        ;
+        ;   KEY MATRIX TO DISPLAY CODE TABL
+        ;
+KTBL:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0CAH                                                           ; GRAPH
+    DB    58H                                                            ; 
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    2CH                                                            ;         ;
+    DB    4FH                                                            ; :
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    19H                                                            ; Y
+    DB    1AH                                                            ; Z
+    DB    55H                                                            ; @
+    DB    52H                                                            ; [
+    DB    54H                                                            ; ]
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+        ;S2   10 - 17
+    DB    11H                                                            ; Q
+    DB    12H                                                            ; R
+    DB    13H                                                            ; S
+    DB    14H                                                            ; T
+    DB    15H                                                            ; U
+    DB    16H                                                            ; V
+    DB    17H                                                            ; W
+    DB    18H                                                            ; X
+        ;S3   18 - 1F
+    DB    09H                                                            ; I
+    DB    0AH                                                            ; J
+    DB    0BH                                                            ; K
+    DB    0CH                                                            ; L
+    DB    0DH                                                            ; M
+    DB    0EH                                                            ; N
+    DB    0FH                                                            ; O
+    DB    10H                                                            ; P
+        ;S4   20 - 27
+    DB    01H                                                            ; A
+    DB    02H                                                            ; B
+    DB    03H                                                            ; C
+    DB    04H                                                            ; D
+    DB    05H                                                            ; E
+    DB    06H                                                            ; F
+    DB    07H                                                            ; G
+    DB    08H                                                            ; H
+        ;S5   28 - 2F
+    DB    21H                                                            ; 1
+    DB    22H                                                            ; 2
+    DB    23H                                                            ; 3
+    DB    24H                                                            ; 4
+    DB    25H                                                            ; 5
+    DB    26H                                                            ; 6
+    DB    27H                                                            ; 7
+    DB    28H                                                            ; 8
+        ;S6   30 - 37
+    DB    59H                                                            ; \
+    DB    50H                                                            ; 
+    DB    2AH                                                            ; -
+    DB    00H                                                            ; SPACE
+    DB    20H                                                            ; 0
+    DB    29H                                                            ; 9
+    DB    2FH                                                            ; ,
+    DB    2EH                                                            ; .
+        ;S7   38 - 3F
+    DB    0C8H                                                           ; INST.
+    DB    0C7H                                                           ; DEL.
+    DB    0C2H                                                           ; CURSOR UP
+    DB    0C1H                                                           ; CURSOR DOWN
+    DB    0C3H                                                           ; CURSOR RIGHT
+    DB    0C4H                                                           ; CURSOR LEFT
+    DB    49H                                                            ; ?
+    DB    2DH                                                            ; /
+        ;
+        ;
+        ;   KTBL SHIFT ON
+        ;
+KTBLS:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0CAH                                                           ; GRAPH
+    DB    1BH                                                            ; POND
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    6AH                                                            ; +
+    DB    6BH                                                            ; *
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    99H                                                            ; y
+    DB    9AH                                                            ; z
+    DB    0A4H                                                           ; `
+    DB    0BCH                                                           ; {
+    DB    40H                                                            ; }
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+    DB    0F0H                                                           ; NULL
+        ;S2   10 - 17
+    DB    91H                                                            ; q
+    DB    92H                                                            ; r
+    DB    93H                                                            ; s
+    DB    94H                                                            ; t
+    DB    95H                                                            ; u
+    DB    96H                                                            ; v
+    DB    97H                                                            ; w
+    DB    98H                                                            ; x
+        ;S3   18 - 1F
+    DB    89H                                                            ; i
+    DB    8AH                                                            ; j
+    DB    8BH                                                            ; k
+    DB    8CH                                                            ; l
+    DB    8DH                                                            ; m
+    DB    8EH                                                            ; n
+    DB    8FH                                                            ; o
+    DB    90H                                                            ; p
+        ;S4   20 - 27
+    DB    81H                                                            ; a
+    DB    82H                                                            ; b
+    DB    83H                                                            ; c
+    DB    84H                                                            ; d
+    DB    85H                                                            ; e
+    DB    86H                                                            ; f
+    DB    87H                                                            ; g
+    DB    88H                                                            ; h
+        ;S5   28 - 2F
+    DB    61H                                                            ; !
+    DB    62H                                                            ; "
+    DB    63H                                                            ; #
+    DB    64H                                                            ; $
+    DB    65H                                                            ; %
+    DB    66H                                                            ; &
+    DB    67H                                                            ; '
+    DB    68H                                                            ; (
+        ;S6   30 - 37
+    DB    80H                                                            ; \
+    DB    0A5H                                                           ; POND MARK
+    DB    2BH                                                            ; YEN
+    DB    00H                                                            ; SPACE
+    DB    60H                                                            ; �
+    DB    69H                                                            ; )
+    DB    51H                                                            ; <
+    DB    57H                                                            ; >
+        ;S7   38 - 3F
+    DB    0C6H                                                           ; CLR
+    DB    0C5H                                                           ; HOME
+    DB    0C2H                                                           ; CURSOR UP
+    DB    0C1H                                                           ; CURSOR DOWN
+    DB    0C3H                                                           ; CURSOR RIGHT
+    DB    0C4H                                                           ; CURSOR LEFT
+    DB    5AH                                                            ;
+    DB    45H                                                            ;
+        ;
+        ;
+        ;   GRAPHIC
+        ;
+KTBLGS:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0F0H                                                           ; GRAPH BUT NULL
+    DB    0E5H                                                           ; #
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    42H                                                            ; #        ;
+    DB    0B6H                                                           ; #:
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    75H                                                            ; #Y
+    DB    76H                                                            ; #Z
+    DB    0B2H                                                           ; #@
+    DB    0D8H                                                           ; #[
+    DB    4EH                                                            ; #]
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+        ;S2   10 - 17
+    DB    3CH                                                            ; #Q
+    DB    30H                                                            ; #R
+    DB    44H                                                            ; #S
+    DB    71H                                                            ; #T
+    DB    79H                                                            ; #U
+    DB    0DAH                                                           ; #V
+    DB    38H                                                            ; #W
+    DB    6DH                                                            ; #X
+        ;S3   18 - 1F
+    DB    7DH                                                            ; #I
+    DB    5CH                                                            ; #J
+    DB    5BH                                                            ; #K
+    DB    0B4H                                                           ; #L
+    DB    1CH                                                            ; #M
+    DB    32H                                                            ; #N
+    DB    0B0H                                                           ; #O
+    DB    0D6H                                                           ; #P
+        ;S4   20 - 27
+    DB    53H                                                            ; #A
+    DB    6FH                                                            ; #B
+    DB    0DEH                                                           ; #C
+    DB    47H                                                            ; #D
+    DB    34H                                                            ; #E
+    DB    4AH                                                            ; #F
+    DB    4BH                                                            ; #G
+    DB    72H                                                            ; #H
+        ;S5   28 - 2F
+    DB    37H                                                            ; #1
+    DB    3EH                                                            ; #2
+    DB    7FH                                                            ; #3
+    DB    7BH                                                            ; #4
+    DB    3AH                                                            ; #5
+    DB    5EH                                                            ; #6
+    DB    1FH                                                            ; #7
+    DB    0BDH                                                           ; #8
+        ;S6   30 - 37
+    DB    0D4H                                                           ; #YEN
+    DB    9EH                                                            ; #+
+    DB    0D2H                                                           ; #-
+    DB    00H                                                            ; SPACE
+    DB    9CH                                                            ; #0
+    DB    0A1H                                                           ; #9
+    DB    0CAH                                                           ; #,
+    DB    0B8H                                                           ; #.
+        ;S7   38 - 3F
+    DB    0C8H                                                           ; INST
+    DB    0C7H                                                           ; DEL.
+    DB    0C2H                                                           ; CURSOR UP
+    DB    0C1H                                                           ; CURSOR DOWN
+    DB    0C3H                                                           ; CURSOR RIGHT
+    DB    0C4H                                                           ; CURSOR LEFT
+    DB    0BAH                                                           ; #?
+    DB    0DBH                                                           ; #/
+        ;
+        ;
+        ;   CONTROL CODE
+        ;
+KTBLC:
+        ;S0   00 - 07
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H                                                           ; ^
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+        ;S1   08 - 0F
+    DB    0F0H                                                           ; ^Y E3
+    DB    5AH                                                            ; ^Z E4 (CHECKER)
+    DB    0F0H                                                           ; ^@
+    DB    0F0H                                                           ; ^[ EB/E5
+    DB    0F0H                                                           ; ^] EA/E7 
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+    DB    0F0H                                                           ; #NULL
+        ;S2   10 - 17
+    DB    0C1H                                                           ; ^Q
+    DB    0C2H                                                           ; ^R
+    DB    0C3H                                                           ; ^S
+    DB    0C4H                                                           ; ^T
+    DB    0C5H                                                           ; ^U
+    DB    0C6H                                                           ; ^V
+    DB    0F0H                                                           ; ^W E1
+    DB    0F0H                                                           ; ^X E2
+        ;S3   18 - 1F
+    DB    0F0H                                                           ; ^I F9
+    DB    0F0H                                                           ; ^J FA
+    DB    0F0H                                                           ; ^K FB
+    DB    0F0H                                                           ; ^L FC
+    DB    0F0H                                                           ; ^M CD
+    DB    0F0H                                                           ; ^N FE
+    DB    0F0H                                                           ; ^O FF
+    DB    0F0H                                                           ; ^P E0
+        ;S4   20 - 27
+    DB    0F0H                                                           ; ^A F1
+    DB    0F0H                                                           ; ^B F2
+    DB    0F0H                                                           ; ^C F3
+    DB    0F0H                                                           ; ^D F4
+    DB    0F0H                                                           ; ^E F5
+    DB    0F0H                                                           ; ^F F6
+    DB    0F0H                                                           ; ^G F7
+    DB    0F0H                                                           ; ^H F8
+        ;S5   28 - 2F
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+        ;S6   30 - 37 (ERROR? 7 VALUES ONLY!!)
+    DB    0F0H                                                           ; ^YEN E6
+    DB    0F0H                                                           ; ^    EF
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H                                                           ; ^,
+    DB    0F0H
+        ;S7   38 - 3F
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H                                                           ; ^/ EE
+        ;
+        ;
+        ;   KANA
+        ;
+KTBLG:
+        ;S0   00 - 07
+    DB    0BFH                                                           ; SPARE
+    DB    0F0H                                                           ; GRAPH BUT NULL
+    DB    0CFH                                                           ; NIKO WH.
+    DB    0C9H                                                           ; ALPHA
+    DB    0F0H                                                           ; NO
+    DB    0B5H                                                           ; MO
+    DB    4DH                                                            ; DAKU TEN
+    DB    0CDH                                                           ; CR
+        ;S1   08 - 0F
+    DB    35H                                                            ; HA
+    DB    77H                                                            ; TA
+    DB    0D7H                                                           ; WA
+    DB    0B3H                                                           ; YO
+    DB    0B7H                                                           ; HANDAKU
+    DB    0F0H
+    DB    0F0H
+    DB    0F0H
+        ;S2   10 - 17
+    DB    7CH                                                            ; KA
+    DB    70H                                                            ; KE
+    DB    41H                                                            ; SHI
+    DB    31H                                                            ; KO
+    DB    39H                                                            ; HI
+    DB    0A6H                                                           ; TE
+    DB    78H                                                            ; KI
+    DB    0DDH                                                           ; CHI
+        ;S3   18 - 1F
+    DB    3DH                                                            ; FU
+    DB    5DH                                                            ; MI
+    DB    6CH                                                            ; MU
+    DB    56H                                                            ; ME
+    DB    1DH                                                            ; RHI
+    DB    33H                                                            ; RA
+    DB    0D5H                                                           ; HE
+    DB    0B1H                                                           ; HO
+        ;S4   20 - 27
+    DB    46H                                                            ; SA
+    DB    6EH                                                            ; TO
+    DB    0D9H                                                           ; THU
+    DB    48H                                                            ; SU
+    DB    74H                                                            ; KU
+    DB    43H                                                            ; SE
+    DB    4CH                                                            ; SO
+    DB    73H                                                            ; MA
+        ;S5   28 - 2F
+    DB    3FH                                                            ; A
+    DB    36H                                                            ; I
+    DB    7EH                                                            ; U
+    DB    3BH                                                            ; E
+    DB    7AH                                                            ; O
+    DB    1EH                                                            ; NA
+    DB    5FH                                                            ; NI
+    DB    0A2H                                                           ; NU
+        ;S6   30 - 37
+    DB    0D3H                                                           ; YO
+    DB    9FH                                                            ; YU
+    DB    0D1H                                                           ; YA
+    DB    00H                                                            ; SPACE
+    DB    9DH                                                            ; NO
+    DB    0A3H                                                           ; NE
+    DB    0D0H                                                           ; RU
+    DB    0B9H                                                           ; RE
+        ;S7   38 - 3F
+    DB    0C6H                                                           ; ?CLR
+    DB    0C5H                                                           ; ?HOME
+    DB    0C2H                                                           ; ?CURSOR UP
+    DB    0C1H                                                           ; ?CURSOR DOWN
+    DB    0C3H                                                           ; ?CURSOR RIGHT
+    DB    0C4H                                                           ; ?CURSOR LEFT 
+    DB    0BBH                                                           ; DASH
+    DB    0BEH                                                           ; RO
+
+        ;    MEMORY DUMP COMMAND "D"
+
+DUMP:   CALL    HEXIY                                                    ; START ADDRESS
+        CALL    P4DE
+        PUSH    HL
+        CALL    HLHEX                                                    ; END ADDRESS
+        POP     DE
+        JR      C,DUM1                                                   ; DATA ERROR THEN
+L0D36:  EX      DE,HL
+DUM3:   LD      B,08H                                                    ; DISPLAY 8 BYTES
+        LD      C,23                                                     ; CHANGE PRINT BIAS
+        CALL    NLPHL                                                    ; NEWLINE PRINT
+DUM2:   CALL    SPHEX                                                    ; SPACE PRINT + ACC PRINT
+        INC     HL
+        PUSH    AF
+        LD      A,(DSPXY)                                                ; DISPLAY POINT
+        ADD     A,C
+        LD      (DSPXY),A                                                ; X AXIS=X+CREG
+        POP     AF
+        CP      20H
+        JR      NC,L0D51
+        LD      A,2EH                                                    ; "."
+L0D51:  CALL    QADCN                                                    ; ASCII TO DISPLAY CODE
+        CALL    PRNT3
+        LD      A,(DSPXY)
+        INC     C
+        SUB     C                                                        ; ASCII DISPLAY POSITION
+        LD      (DSPXY),A
+        DEC     C
+        DEC     C
+        DEC     C
+        PUSH    HL
+        SBC     HL,DE
+        POP     HL
+        JR      Z,L0D85
+        LD      A,0F8H
+        LD      (KEYPA),A
+        NOP     
+        LD      A,(KEYPB)
+        CP      0FEH                                                     ; SHIFT KEY ?
+        JR      NZ,L0D78
+        CALL    QBLNK                                                    ; 64MSEC DELAY
+L0D78:  DJNZ    DUM2
+L0D7A:  CALL    QKEY                                                     ; STOP DISPLAY
+        OR      A
+        JR      Z,L0D7A                                                  ; SPACE KEY THEN STOP
+        CALL    QBRK                                                     ; BREAK IN ?
+        JR      NZ,DUM3
+L0D85:  JP      ST1                                                      ; COMMAND IN !
+
+DUM1:   LD      HL,160                                                   ; 20*8 BYTES
+        ADD     HL,DE
+        JR      L0D36
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    V-BLANK CHECK
+
+QBLNK:  PUSH    AF
+L0DA7:  LD      A,(KEYPC)                                                ; V-BLANK
+        RLCA    
+        JR      NC,L0DA7
+L0DAD:  LD      A,(KEYPC)                                                ; 64
+        RLCA                                                             ;
+        JR      C,L0DAD                                                  ; MSEC
+        POP     AF
+        RET     
+        ;    DISPLAY ON POINTER
+        ;    ACC=DISPLAY CODE
+        ;    EXCEPT F0H
+
+QDSP:   PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+DSP01:  CALL    QPONT                                                    ; DISPLAY POSITION
+        LD      (HL),A
+        LD      HL,(DSPXY)
+        LD      A,L
+        CP      79
+        JR      NZ,DSP04
+        CALL    PMANG
+        JR      C,DSP04
+        EX      DE,HL
+        LD      (HL),1                                                   ; LOGICAL 1ST COLUMN
+        INC     HL
+        LD      (HL),0                                                   ; LOGICAL 2ND COLUMN
+DSP04:  LD      A,0C3H                                                   ; CURSL
+        JR      L0DE0
+
+        ;    GRAPHIC STATUS CHECK
+
+GRSTAS: LD      A,(KANAF)
+        CP      01H
+        LD      A,0CAH
+        RET     
+
+        ;    DISPLAY CONTROL
+        ;    ACC=CONTROL CODE
+
+QDPCT:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+L0DE0:  LD      B,A
+        AND     0F0H
+        CP      0C0H
+        JR      NZ,CURS5
+        XOR     B
+        RLCA    
+        LD      C,A
+        LD      B,0
+        LD      HL,CTBL                                                  ; PAGE MODE1
+        ADD     HL,BC
+        LD      E,(HL)
+        INC     HL
+        LD      D,(HL)
+        LD      HL,(DSPXY)
+        EX      DE,HL
+        JP      (HL)
+
+CURSD:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,H
+        CP      24
+        JR      Z,CURS4
+        INC     H
+CURS1:  
+CURS3:    LD      (DSPXY),HL
+CURS5:  JP      QRSTR
+
+CURSU:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,H
+        OR      A
+        JR      Z,CURS5
+        DEC     H
+CURSU1: JR      CURS3
+
+CURSR:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,L
+        CP      79
+        JR      NC,CURS2
+        INC     L
+        JR      CURS3
+
+CURS2:  LD      L,0
+        INC     H
+        LD      A,H
+        CP      25
+        JR      C,CURS1
+        LD      H,24
+        LD      (DSPXY),HL
+CURS4:  JR      SCROL
+
+CURSL:  EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,L
+        OR      A
+        JR      Z,L0E2D
+        DEC     L
+        JR      CURS3
+
+L0E2D:  LD      L,79
+        DEC     H
+        JP      P,CURSU1
+        LD      H,0
+        LD      (DSPXY),HL
+        JR      CURS5
+
+CLRS:   LD      HL,MANG
+        LD      B,27
+        CALL    QCLER
+        LD      HL,0D000H                                                ; SCRN TOP
+        CALL    NCLR08
+        LD      A,71H                                                    ; COLOR DATA
+        CALL    NCLR8                                                    ; D800H-DFFFH CLEAR
+HOME:   LD      HL,0                                                     ; DSPXY:0 X=0,Y=0
+        JR      CURS3
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+        ;    CR
+
+CR:     CALL    PMANG
+        RRCA    
+        JR      NC,CURS2
+        LD      L,0
+        INC     H
+        CP      24
+        JR      Z,CR1
+        INC     H
+        JR      CURS1
+
+CR1:    LD      (DSPXY),HL
+
+        ;    SCROLL
+
+SCROL:  LD      BC,2000 - 80                                             ; Scroll all lines except top.
+        LD      DE,SCRN                                                  ; TOP OF $CRT ADDRESS
+        LD      HL,SCRN+80                                               ; COLUMN
+        PUSH    BC                                                       ; 1000 STORE
+        LDIR    
+        POP     BC
+        PUSH    DE
+        LD      DE,SCRN+800H                                             ; COLOR RAM SCROLL
+        LD      HL,SCRN+850H                                             ; SCROLL TOP + 80
+        LDIR    
+        LD      B,80                                                     ; ONE LINE
+        EX      DE,HL
+        LD      A,71H                                                    ; COLOR RAM INITIAL DATA
+        CALL    QDINT
+        POP     HL
+        LD      B,80
+        CALL    QCLER                                                    ; LAST LINE CLEAR
+        LD      BC,26                                                    ; ROW NUMBER+1
+        LD      DE,MANG                                                  ; LOGICAL MANAGEMENT
+        LD      HL,MANG+1
+        LDIR    
+        LD      (HL),0
+        LD      A,(MANG)
+        OR      A
+        JR      Z,QRSTR
+        LD      HL,DSPXY+1
+        DEC     (HL)
+        JR      SCROL
+
+        ;    CONTROL CODE TABLE
+
+CTBL:   DW    SCROL                                                     ; SCROLLING 10H
+        DW    CURSD                                                     ; CURSOR DOWN 11H
+        DW    CURSU                                                     ; CURSOR UP 12H
+        DW    CURSR                                                     ; CURSOR RIGHT 13H
+        DW    CURSL                                                     ; CURSOR LEFT 14H
+        DW    HOME                                                      ; 15H
+        DW    CLRS                                                      ; 16H
+        DW    DEL                                                       ; 17H
+        DW    INST                                                      ; 18H
+        DW    ALPHA                                                     ; 19H
+        DW    KANA                                                      ; GRAPHIC 1AH
+        DW    QRSTR                                                     ; 1BH
+        DW    QRSTR                                                     ; 1CH
+        DW    CR                                                        ; 1DH
+        DW    QRSTR                                                     ; 1EH
+        DW    QRSTR                                                     ; 1FH
+
+        ;    INST BYPASS
+
+INST2:    SET    3,H                                                     ; COLOR RAM
+    LD    A,(HL)                                                         ; FROM
+    INC    HL
+    LD      (HL),A                                                       ; TO
+        DEC     HL                                                       ; ADDRESS ADJUST
+        RES     3,H
+        LDD                                                              ; CHANGE TRNS.
+        LD      A,C
+        OR      B                                                        ; BC=0 ?
+        JR      NZ,INST2
+        EX      DE,HL
+        LD      (HL),0
+        SET     3,H                                                      ; COLOR RAM
+        LD      (HL),71H
+        JR      QRSTR
+
+ALPHA:  XOR     A
+ALPH1:  LD      (KANAF),A
+
+        ;    RESTORE
+
+QRSTR:  POP     HL
+QRSTR1: POP     DE
+        POP     BC
+        POP     AF
+        RET     
+
+        NOP     
+        NOP     
+        NOP     
+        NOP     
+
+KANA:   CALL    GRSTAS
+        JP      Z,DSP01                                                  ; NOT GRAPH KEY THEN JUMP
+        LD      A,01H
+        JR      ALPH1
+
+DEL:    EX      DE,HL                                                    ; LD HL,(DSPXY)
+        LD      A,H                                                      ; HOME ?
+        OR      L
+        JR      Z,QRSTR
+        LD      A,L
+        OR      A
+        JR      NZ,DEL1                                                  ; LEFT SIDE ?
+        CALL    PMANG
+        JR      C,DEL1
+        CALL    QPONT
+        DEC     HL
+        LD      (HL),0
+        JR      L0F33                                                    ; JUMP CURSL
+
+DEL1:   CALL    PMANG
+        RRCA    
+        LD      A,80
+        JR      NC,L0F17
+        RLCA                                                             ; ACC=80
+L0F17:  SUB     L
+        LD      B,A                                                      ; TRNS. BYTE
+        CALL    QPONT
+DEL2:   LD      A,(HL)                                                   ; CHANGE FROM ADDRESS
+        DEC     HL
+        LD      (HL),A                                                   ; TO
+        INC     HL
+        SET     3,H                                                      ; COLOR RAM
+        LD      A,(HL)
+        DEC     HL
+        LD      (HL),A
+        RES     3,H                                                      ; CHANGE
+        INC     HL
+        INC     HL                                                       ; NEXT
+        DJNZ    DEL2
+        DEC     HL                                                       ; ADDRESS ADJUST
+        LD      (HL),0
+        SET     3,H
+        LD      HL,71H                                                   ; BLUE + WHITE
+L0F33:  LD      A,0C4H                                                   ; JP CURSL
+        JP      L0DE0
+
+INST:   CALL    PMANG
+        RRCA    
+        LD      L,79
+        LD      A,L
+        JR      NC,L0F42
+        INC     H
+L0F42:  CALL    QPNT1
+        PUSH    HL
+        LD      HL,(DSPXY)
+        JR      NC,L0F4D
+        LD      A,79
+L0F4D:  SUB     L
+        LD      B,0
+        LD      C,A
+        POP     DE
+        JR      Z,QRSTR
+        LD      A,(DE)
+        OR      A
+        JR      NZ,QRSTR
+        LD      H,D                                                      ; HL<-DE
+        LD      L,E
+        DEC     HL
+        JP      INST2                                                    ; JUMP NEXT (BYPASS)
+
+        ;    PROGRAM SAVE
+        ;    COMMAND "S"
+
+SAVE:   CALL    HEXIY                                                    ; START ADDRESS
+        LD      (DTADR),HL                                               ; DATA ADDRESS BUFFER
+        LD      B,H
+        LD      C,L
+        CALL    P4DE
+        CALL    HEXIY                                                    ; END ADDRESS
+        SBC     HL,BC                                                    ; BYTE SIZE
+        INC     HL
+        LD      (SIZE),HL                                                ; BYTE SIZE BUFFER
+        CALL    P4DE
+        CALL    HEXIY                                                    ; EXECUTE ADDRESS
+        LD      (EXADR),HL                                               ; BUFFER
+        CALL    NL
+        LD      DE,MSGSV                                                 ; SAVED FILENAME
+        RST     18H                                                      ; CALL MSGX
+        CALL    BGETL                                                    ; FILENAME INPUT
+        CALL    P4DE
+        CALL    P4DE
+        LD      HL,NAME                                                  ; NAME BUFFER
+SAV1:   INC     DE
+        LD      A,(DE)
+        LD      (HL),A                                                   ; FILENAME TRANS.
+        INC     HL
+        CP      0DH                                                      ; END CODE
+        JR      NZ,SAV1
+        LD      A,01H                                                    ; ATTRIBUTE: OBJECT CODE
+        LD      (ATRB),A
+        CALL    QWRI
+        JP      C,QER                                                    ; WRITE ERROR
+        CALL    QWRD                                                     ; DATA
+        JP      C,QER
+        CALL    NL
+        LD      DE,MSGOK                                                 ; OK MESSAGE
+        RST     18H                                                      ; CALL MSGX
+        JP      ST1
+
+        ;    COMPUTE POINT ADDRESS
+        ;    HL=SCREEN COORDINATE
+        ;    EXIT HL=POINT ADDRESS ON SCREEN
+
+QPONT:  LD      HL,(DSPXY)
+QPNT1:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        POP     BC
+        LD      DE,0050H                                                 ; 80
+        LD      HL,SCRN-80
+QPNT2:  ADD     HL,DE
+        DEC     B
+        JP      P,QPNT2
+        LD      B,0
+        ADD     HL,BC
+        POP     DE
+        POP     BC
+        POP     AF
+        RET     
+
+        ;    VERIFYING COMMAND "V"
+
+VRFY:   CALL    QVRFY
+        JP      C,QER
+        LD      DE,MSGOK
+        RST     18H
+        JP      ST1
+
+        ;    CLER
+        ;    B=SIZE
+        ;    HL=LOW ADDRESS
+
+QCLER:  XOR     A
+        JR      QDINT
+
+QCLRFF: LD      A,0FFH
+QDINT:  LD      (HL),A
+        INC     HL
+        DJNZ    QDINT
+        RET     
+
+        ;    GAP CHECK
+
+GAPCK:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      BC,KEYPB
+        LD      DE,CSTR
+GAPCK1: LD      H,100
+GAPCK2: CALL    EDGE
+        JR      C,GAPCK3
+        CALL    DLY3                                                     ; CALL DLY2*3
+        LD      A,(DE)
+        AND     20H
+        JR      NZ,GAPCK1
+        DEC     H
+        JR      NZ,GAPCK2
+GAPCK3: JP      RET3
+
+        ;    MONITOR WORK AREA
+        ;    (MZ700)
+
+        ORG     10F0H
+SPV:
+IBUFE:                                                                   ; TAPE BUFFER (128 BYTES)
+ATRB:   DS      virtual 1                                                ; ATTRIBUTE
+NAME:   DS      virtual 17                                               ; FILE NAME
+SIZE:   DS      virtual 2                                                ; BYTESIZE
+DTADR:  DS      virtual 2                                                ; DATA ADDRESS
+EXADR:  DS      virtual 2                                                ; EXECUTION ADDRESS
+COMNT:  DS      virtual 104                                              ; COMMENT
+KANAF:  DS      virtual 1                                                ; KANA FLAG (01=GRAPHIC MODE)
+DSPXY:  DS      virtual 2                                                ; DISPLAY COORDINATES
+MANG:   DS      virtual 27                                               ; COLUMN MANAGEMENT
+FLASH:  DS      virtual 1                                                ; FLASHING DATA
+FLPST:  DS      virtual 2                                                ; FLASHING POSITION
+FLSST:  DS      virtual 1                                                ; FLASHING STATUS
+FLSDT:  DS      virtual 1                                                ; CURSOR DATA
+STRGF:  DS      virtual 1                                                ; STRING FLAG
+DPRNT:  DS      virtual 1                                                ; TAB COUNTER
+TMCNT:  DS      virtual 2                                                ; TAPE MARK COUNTER
+SUMDT:  DS      virtual 2                                                ; CHECK SUM DATA
+CSMDT:  DS      virtual 2                                                ; FOR COMPARE SUM DATA
+AMPM:   DS      virtual 1                                                ; AMPM DATA
+TIMFG:  DS      virtual 1                                                ; TIME FLAG
+SWRK:   DS      virtual 1                                                ; KEY SOUND FLAG
+TEMPW:  DS      virtual 1                                                ; TEMPO WORK
+ONTYO:  DS      virtual 1                                                ; ONTYO WORK
+OCTV:   DS      virtual 1                                                ; OCTAVE WORK
+RATIO:  DS      virtual 2                                                ; ONPU RATIO
+BUFER:  DS      virtual 81                                               ; GET LINE BUFFER
+
+        ;    EQU TABLE I/O REPORT
+
+KEYPA:  EQU     0E000H
+KEYPB:  EQU     0E001H
+KEYPC:  EQU     0E002H
+KEYPF:  EQU     0E003H
+CSTR:   EQU     0E002H
+CSTPT:  EQU     0E003H
+CONT0:  EQU     0E004H
+CONT1:  EQU     0E005H
+CONT2:  EQU     0E006H
+CONTF:  EQU     0E007H
+SUNDG:  EQU     0E008H
+TEMP:   EQU     0E008H
+SCRN:   EQU     0D000H
+KANST:  EQU     0E003H                                                   ; KANA STATUS REPORT
+
diff --git a/software/asm/IPL.asm b/software/asm/IPL.asm
new file mode 100644
index 0000000..dacf307
--- /dev/null
+++ b/software/asm/IPL.asm
@@ -0,0 +1,897 @@
+        ORG    0000H
+        ;****************************************************************
+        ;
+        ; Personal Computer
+        ;    MZ-80B
+        ;
+        ;    Initial Program Loader
+        ;****************************************************************
+        ;
+        JR      START
+        ;
+        ; NST RESET
+        ;
+NST:    LD      A,03H
+        OUT     (PPICTL),A                           ;Set PC1 NST=1
+        ;
+START:  LD      A,82H                                ;8255 A=OUT B=IN C=OUT
+        OUT     (PPICTL),A
+        LD      A,0FH                                ;PIO A=OUT
+        OUT     (PIOCTLA),A
+        LD      A,0CFH                               ;PIO B=IN
+        OUT     (PIOCTLB),A
+        LD      A,0FFH
+        OUT     (PIOCTLB),A
+        LD      A,58H                                ;BST=1 NST=0 OPEN=1 WRITE=1
+        OUT     (PPIC),A
+        LD      A,12H
+        OUT     (PPIA),A
+        XOR     A
+        OUT     (GRPHCTL),A                          ;Set Graphics VRAM to default, input to GRPH I, no output.
+        LD      SP,0FFE0H
+        LD      HL,0D000H
+        LD      A,0B3H
+        OUT     (PIOA),A
+CLEAR:  LD      (HL),00H                            ;DISPLAY CLEAR
+        INC     HL
+        LD      A,H
+        OR      L
+        JR      NZ,CLEAR
+        LD      A,13H
+        OUT     (PIOA),A
+        XOR     A
+        LD      (DRINO),A    
+        LD      (MTFG),A
+KEYIN:  CALL    KEYS1
+        BIT     3,A                                  ;C - Cassette.
+        JR      Z,CMT
+        BIT     0,A                                  ;/ - Boot external rom.
+        JP      Z,EXROMT
+        JR      NKIN                                 ;No selection, so standard startup, try FDC then CMT.
+        ;
+KEYS1:  LD      B,14H                                ;Preserve A4-A7, set A4 to prevent all strobes low, the select line 5 (0-4).
+KEYS:   IN      A,(PIOA)
+        AND     0F0H
+        OR      B
+        OUT     (PIOA),A
+        IN      A,(PIOB)                             ;Read the strobed key.
+        RET     
+        ;
+        ;
+NKIN:   CALL    FDCC
+        JP      Z,FD
+        JR      CMT
+        ;
+FDCC:   LD      A,0A5H
+        LD      B,A
+        OUT     (0D9H),A
+        CALL    DLY80U
+        IN      A,(0D9H)
+        CP      B
+        RET     
+        ;
+        ;                                       ;
+        ;  CMT CONTROL                          ;
+        ;                                       ;
+        ;
+CMT:    CALL    MSTOP
+        CALL    DEL6
+        CALL    KYEMES
+        CALL    ?RDI
+        JR      C,ST1
+        CALL    LDMSG
+        LD      HL,NAME
+        LD      E,010H
+        LD      C,010H
+        CALL    DISP2
+        LD      A,(ATRB)
+        CP      01H
+        JR      NZ,MISMCH
+        CALL    ?RDD
+ST1:    PUSH    AF
+        CALL    DEL6
+        CALL    REW
+        POP     AF
+        JP      C,TRYAG
+        JP      NST
+                  ;
+MISMCH: LD      HL,MES16
+        LD      E,0AH
+        LD      C,0FH
+        CALL    DISP
+        CALL    MSTOP
+        SCF     
+        JR      ST1
+        ;
+        ;READ INFORMATION
+        ;      CF=1:ERROR
+RDINF:
+?RDI:   DI      
+        LD      D,04H
+        LD      BC,0080H
+        LD      HL,IBUFE
+RD1:    CALL    MOTOR
+        JR      C,STPEIR
+        CALL    TMARK
+        JR      C,STPEIR
+        CALL    RTAPE
+        JR      C,STPEIR
+RET2S:  BIT     3,D
+        JR      Z,EIRTN
+STPEIR: CALL    MSTOP
+EIRTN:  EI      
+        RET     
+        ;
+        ;
+        ;READ DATA
+RDDAT:
+?RDD:   DI      
+        LD      D,08H
+        LD      BC,(SIZE)
+        LD      HL,8000H
+        JR      RD1
+        ;
+        ;
+        ;READ TAPE
+        ;      BC=SIZE
+        ;      DE=LOAD ADDRSS
+RTAPE:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      H,02H
+RTP2:   CALL    SPDIN
+        JR      C,TRTN1                                ;BREAK
+        JR      Z,RTP2
+        LD      D,H
+        LD      HL,0000H
+        LD      (SUMDT),HL
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+RTP3:   CALL    RBYTE
+        JR      C,TRTN1
+        LD      (HL),A
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,RTP3
+        LD      HL,(SUMDT)
+        CALL    RBYTE
+        JR      C,TRTN1
+        LD      E,A
+        CALL    RBYTE
+        JR      C,TRTN1
+        CP      L
+        JR      NZ,RTP5
+        LD      A,E
+        CP      H
+        JR      Z,TRTN1
+RTP5:   DEC     D
+        JR      Z,RTP6
+        LD      H,D
+        JR      RTP2
+RTP6:   CALL    BOOTER
+        SCF     
+TRTN1:  POP     HL
+        POP     BC
+        POP     DE
+        RET     
+        ;EDGE
+EDGE:   IN      A,(PPIB)
+        CPL     
+        RLCA    
+        RET     C                                ;BREAK
+        RLCA    
+        JR      NC,EDGE                                ;WAIT ON LOW
+EDGE1:  IN      A,(PPIB)
+        CPL     
+        RLCA    
+        RET     C                                ;BREAK
+        RLCA    
+        JR      C,EDGE1                                ;WAIT ON HIGH
+        RET     
+        ; 1 BYTE READ
+        ;      DATA=A
+        ;      SUMDT STORE
+RBYTE:  PUSH    HL
+        LD      HL,0800H                            ; 8 BITS
+RBY1:   CALL    SPDIN
+        JR      C,RBY3                                ;BREAK
+        JR      Z,RBY2                                ;BIT=0
+        PUSH    HL
+        LD      HL,(SUMDT)                            ;CHECKSUM
+        INC     HL
+        LD      (SUMDT),HL
+        POP     HL
+        SCF     
+RBY2:   RL      L
+        DEC     H
+        JR      NZ,RBY1
+        CALL    EDGE
+        LD      A,L
+RBY3:   POP     HL
+        RET     
+        ;TAPE MARK DETECT
+        ;      E=L:INFORMATION
+        ;      E=S:DATA
+TMARK:  PUSH    HL
+        LD      HL,1414H
+        BIT     3,D
+        JR      NZ,TM0
+        ADD     HL,HL
+TM0:    LD      (TMCNT),HL
+TM1:    LD      HL,(TMCNT)
+TM2:    CALL    SPDIN
+        JR      C,RBY3
+        JR      Z,TM1
+        DEC     H
+        JR      NZ,TM2
+TM3:    CALL    SPDIN
+        JR      C,RBY3
+        JR      NZ,TM1
+        DEC     L
+        JR      NZ,TM3
+        CALL    EDGE
+        JR      RBY3
+        ;READ 1 BIT
+SPDIN:  CALL    EDGE                                ;WAIT ON HIGH
+        RET     C                                ;BREAK
+
+        CALL    DLY2
+        IN      A,(PPIB)                            ;READ BIT
+        AND     40H
+        RET     
+        ;
+        ;
+        ;MOTOR ON
+MOTOR:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        IN      A,(PPIB)
+        AND     20H
+        JR      Z,MOTRD
+        LD      HL,MES6
+        LD      E,0AH
+        LD      C,0EH
+        CALL    DISP
+        CALL    OPEN
+MOT1:   IN      A,(PIOB)
+        CPL     
+        RLCA    
+        JR      C,MOTR
+        IN      A,(PPIB)
+        AND     20H
+        JR      NZ,MOT1
+        CALL    KYEMES
+        CALL    DEL1M
+MOTRD:  CALL    PLAY
+MOTR:   POP     HL
+        POP     BC
+        POP     DE
+        RET     
+        ;
+        ;
+        ;MOTOR STOP
+MSTOP:  LD      A,0DH
+        OUT     (PPICTL),A                            ;Set PC6 - READ MODE
+        LD      A,1AH
+        OUT     (PPIA),A
+        CALL    DEL6
+        JR      BLK3
+        ;EJECT
+OPEN:   LD      A,08H                                 ;Reset PC4 - EJECT activate
+        OUT     (PPICTL),A
+        CALL    DEL6
+        LD      A,09H
+        OUT     (PPICTL),A                            ;Set PC4 - Deactivate EJECT
+        RET     
+        ;
+        ;
+KYEMES: LD      HL,MES3
+        LD      E,04H
+        LD      C,1CH
+        CALL    DISP
+        RET     
+        ;
+        ;PLAY
+PLAY:   CALL    FR
+        CALL    DEL6
+        LD      A,16H
+        OUT     (PPIA),A
+        JR      BLK3
+BLK1:   CALL    DEL6
+        CALL    BLK3
+        LD      A,13H
+BLK2:   OUT     (PPIA),A
+BLK3:   LD      A,12H
+        OUT     (PPIA),A
+        RET     
+        ;
+        ;
+FR:     LD      A,12H
+FR1:    OUT     (PPIA),A
+        CALL    DEL6
+        LD      A,0BH
+        OUT     (PPICTL),A                            ;Set PC5
+        CALL    DEL6
+        LD      A,0AH
+        OUT     (PPICTL),A                            ;Reset PC5
+        RET     
+
+RRW:    LD      A,010H
+        JR      FR1
+        ;REWIND
+REW:    CALL    RRW
+        JR      BLK1
+        ;
+        ;TIMING DEL
+DM1:    PUSH    AF
+L0211:  XOR     A
+L0212:  DEC     A
+        JR      NZ,L0212
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,L0211
+        POP     AF
+        POP     BC
+        RET     
+
+DEL6:   PUSH    BC
+        LD      BC,00E9H                            ;233D
+        JR      DM1
+DEL1M:  PUSH    BC
+        LD      BC,060FH                            ;1551D
+        JR      DM1
+        ;
+        ;TAPE DELAY TIMING
+        ;
+        ;
+DLY2:   LD      A,31H
+L022B:  DEC     A
+        JP      NZ,L022B
+        RET     
+        ;
+        ;
+        ;
+        ;
+        ;
+LDMSG:  LD      HL,MES1
+        LD      E,00H
+        LD      C,0EH
+        JR      DISP
+        ;
+DISP2:  LD      A,93H
+        OUT     (PIOA),A
+        JR      DISP1
+                    ;
+BOOTER: LD      HL,MES8
+        LD      E,0AH
+        LD      C,0DH
+        ;
+DISP:   LD      A,93H
+        OUT     (PIOA),A
+        EXX     
+        LD      HL,0D000H
+DISP3:  LD      (HL),00H
+        INC     HL
+        LD      A,H
+        OR      L
+        JR      NZ,DISP3
+        EXX     
+DISP1:  XOR     A
+        LD      B,A
+        LD      D,0D0H
+        LDIR    
+        LD      A,13H
+        OUT     (PIOA),A
+        RET     
+        ;
+        ;
+MES1:   DB    "IPL is loading"
+MES3:   DB    "IPL is looking for a program"
+MES6:   DB    "Make ready CMT"
+MES8:   DB    "Loading error"
+MES9:   DB    "Make ready FD"
+MES10:  DB    "Press F or C"
+MES11:  DB    "F:Floppy diskette"
+MES12:  DB    "C:Cassette tape"
+MES13:  DB    "Drive No? (1-4)"
+MES14:  DB    "This diskette is not master"
+MES15:  DB    "Pressing S key starts the CMT"
+MES16:  DB    "File mode error"
+                    ;
+IPLMC:  DB    01H
+        DB    "IPLPRO"
+        ;
+        ;
+        ;FD
+FD:     LD      IX,IBADR1
+        XOR     A
+        LD      (0CF1EH),A
+        LD      (0CF1FH),A
+        LD      IY,0FFE0H
+        LD      HL,0100H
+        LD      (IY+2),L
+        LD      (IY+3),H
+        CALL    BREAD                                ;INFORMATION INPUT
+        LD      HL,0CF00H                            ;MASTER CHECK
+        LD      DE,IPLMC
+        LD      B,06H
+MCHECK: LD      C,(HL)
+        LD      A,(DE)
+        CP      C
+        JP      NZ,NMASTE
+        INC     HL
+        INC     DE
+        DJNZ    MCHECK
+        CALL    LDMSG
+        LD      HL,0CF07H
+        LD      E,010H
+        LD      C,0AH
+        CALL    DISP2
+        LD      IX,IBADR2
+        LD      HL,(0CF14H)
+        LD      (IY+2),L
+        LD      (IY+3),H
+        CALL    BREAD
+        CALL    MOFF
+        JP      NST
+        ;
+        ;
+NODISK: LD      HL,MES9
+        LD      E,0AH
+        LD      C,0DH
+        CALL    DISP
+        JP      ERR1
+        ;
+        ; READY CHECK
+        ;
+READY:  LD      A,(MTFG)
+        RRCA    
+        CALL    NC,MTON
+        LD      A,(DRINO)                            ;DRIVE NO GET
+        OR      84H
+        OUT     (DM),A                                ;DRIVE SELECT MOTON
+        XOR     A
+        CALL    DLY60M
+        LD      HL,0000H
+REDY0:  DEC     HL
+        LD      A,H
+        OR      L
+        JR      Z,NODISK
+        IN      A,(CR)                                ;STATUS GET
+        CPL     
+        RLCA    
+        JR      C,REDY0
+        LD      A,(DRINO)
+        LD      C,A
+        LD      HL,CLBF0
+        LD      B,00H
+        ADD     HL,BC
+        BIT     0,(HL)
+        RET     NZ
+        CALL    RCLB
+        SET     0,(HL)
+        RET     
+        ;
+        ; MOTOR ON
+                  ;
+MTON:   LD      A,80H
+        OUT     (DM),A
+        LD      B,0AH                                ;1SEC DELAY
+MTD1:   LD      HL,3C19H
+MTD2:   DEC     HL
+        LD      A,L
+        OR      H
+        JR      NZ,MTD2
+        DJNZ    MTD1
+        LD      A,01H
+        LD      (MTFG),A
+        RET     
+        ;
+        ;SEEK TREATMENT
+        ;
+SEEK:   LD      A,1BH
+        CPL     
+        OUT     (CR),A
+        CALL    BUSY
+        CALL    DLY60M
+        IN      A,(CR)
+        CPL     
+        AND     99H
+        RET     
+        ;
+        ;MOTOR OFF
+        ;
+MOFF:   CALL    DLY1M
+        XOR     A
+        OUT     (DM),A
+        LD      (CLBF0),A
+        LD      (CLBF1),A
+        LD      (CLBF2),A
+        LD      (CLBF3),A
+        LD      (MTFG),A
+        RET     
+        ;
+        ;RECALIBRATION
+        ;
+RCLB:   PUSH    HL
+        LD      A,0BH
+        CPL     
+        OUT     (CR),A
+        CALL    BUSY
+        CALL    DLY60M
+        IN      A,(CR)
+        CPL     
+        AND     85H
+        XOR     04H
+        POP     HL
+        RET     Z
+        JP      ERR
+        ;
+        ;BUSY AND WAIT
+        ;
+BUSY:   PUSH    DE
+        PUSH    HL
+        CALL    DLY80U
+        LD      E,07H
+BUSY2:  LD      HL,0000H
+BUSY0:  DEC     HL
+        LD      A,H
+        OR      L
+        JR      Z,BUSY1
+        IN      A,(CR)
+        CPL     
+        RRCA    
+        JR      C,BUSY0
+        POP     HL
+        POP     DE
+        RET
+        ;
+BUSY1:  DEC     E
+        JR      NZ,BUSY2
+        JP      ERR
+        ;
+        ;DATA CHECK
+        ;
+CONVRT: LD      B,00H
+        LD      DE,0010H
+        LD      HL,(0CF1EH)
+        XOR     A
+TRANS:  SBC     HL,DE
+        JR      C,TRANS1
+        INC     B
+        JR      TRANS
+TRANS1: ADD     HL,DE
+        LD      H,B
+        INC     L
+        LD      (IY+4),H
+        LD      (IY+5),L
+DCHK:   LD      A,(DRINO)
+        CP      04H
+        JR      NC,DTCK1
+        LD      A,(IY+4)
+        CP      46H                                ;70D
+        JR      NC,DTCK1
+        LD      A,(IY+5)
+        OR      A
+        JR      Z,DTCK1
+        CP      11H                                ;17D
+        JR      NC,DTCK1
+        LD      A,(IY+2)
+        OR      (IY+3)
+        RET     NZ
+DTCK1:  JP      ERR
+        ;
+        ;SEQUENTIAL READ
+        ;
+BREAD:  DI      
+        CALL    CONVRT
+        LD      A,0AH
+        LD      (RETRY),A
+READ1:  CALL    READY
+        LD      D,(IY+3)
+        LD      A,(IY+2)
+        OR      A
+        JR      Z,RE0
+        INC     D
+RE0:    LD      A,(IY+5)
+        LD      (IY+1),A
+        LD      A,(IY+4)
+        LD      (IY+0),A
+        PUSH    IX
+        POP     HL
+RE8:    SRL     A
+        CPL     
+        OUT     (DR),A
+        JR      NC,RE1
+        LD      A,01H
+        JR      RE2
+RE1:    LD      A,00H
+RE2:    CPL     
+        OUT     (HS),A
+        CALL    SEEK
+        JR      NZ,REE
+        LD      C,0DBH
+        LD      A,(IY+0)
+        SRL     A
+        CPL     
+        OUT     (TR),A
+        LD      A,(IY+1)
+        CPL     
+        OUT     (SCR),A
+        EXX     
+        LD      HL,RE3
+        PUSH    HL
+        EXX     
+        LD      A,94H
+        CPL     
+        OUT     (CR),A
+        CALL    WAIT
+RE6:    LD      B,00H
+RE4:    IN      A,(CR)
+        RRCA    
+        RET     C
+        RRCA    
+        JR      C,RE4
+        INI     
+        JR      NZ,RE4
+        INC     (IY+1)
+        LD      A,(IY+1)
+        CP      11H                                ;17D
+        JR      Z,RETS
+        DEC     D
+        JR      NZ,RE6
+        JR      RE5
+RETS:   DEC     D
+RE5:    LD      A,0D8H                                ;FORCE INTERRUPT
+        CPL     
+        OUT     (CR),A
+        CALL    BUSY
+RE3:    IN      A,(CR)
+        CPL     
+        AND     0FFH
+        JR      NZ,REE
+        EXX     
+        POP     HL
+        EXX     
+        LD      A,(IY+1)
+        CP      11H                                ;17D
+        JR      NZ,REX
+        LD      A,01H
+        LD      (IY+1),A
+        INC     (IY+0)
+REX:    LD      A,D
+        OR      A
+        JR      NZ,RE7
+        LD      A,80H
+        OUT     (DM),A
+        RET     
+RE7:    LD      A,(IY+0)
+        JR      RE8
+REE:    LD      A,(RETRY)
+        DEC     A
+        LD      (RETRY),A
+        JR      Z,ERR
+        CALL    RCLB
+        JP      READ1
+        ;
+        ; WAIT AND BUSY OFF
+        ;
+WAIT:   PUSH    DE
+        PUSH    HL
+        CALL    DLY80U
+        LD      E,08H
+WAIT2:  LD      HL,0000H
+WAIT0:  DEC     HL
+        LD      A,H
+        OR      L
+        JR      Z,WAIT1
+        IN      A,(CR)
+        CPL     
+        RRCA    
+        JR      NC,WAIT0
+        POP     HL
+        POP     DE
+        RET     
+WAIT1:  DEC     E
+        JR      NZ,WAIT2
+        JR      ERR
+                  ;
+NMASTE: LD      HL,MES14
+        LD      E,07H
+        LD      C,1BH                                ;27D
+        CALL    DISP
+        JR      ERR1
+        ;
+        ;                                                 ;
+        ;   ERRROR OR BREAK                               ;
+        ;                                                 ;
+        ;
+ERR:    CALL    BOOTER
+ERR1:   CALL    MOFF
+TRYAG2: LD      SP,0FFE0H
+        ;
+        ;TRYAG
+        ;
+TRYAG:  CALL    FDCC
+        JR      NZ,TRYAG3
+        LD      HL,MES10
+        LD      E,5AH
+        LD      C,0CH                                ;12D
+        CALL    DISP2
+        LD      E,0ABH
+        LD      C,11H                                ;17D
+        CALL    DISP2
+        LD      E,0D3H
+        LD      C,0FH                                ;15D
+        CALL    DISP2
+TRYAG1: CALL    KEYS1
+        BIT     3,A
+        JP      Z,CMT
+        BIT     6,A
+        JR      Z,DNO
+        JR      TRYAG1
+DNO:    LD      HL,MES13                            ;DRIVE NO SELECT
+        LD      E,0AH
+        LD      C,0FH
+        CALL    DISP
+DNO10:  LD      D,12H
+        CALL    DNO0
+        JR      NC,DNO3
+        LD      D,18H
+        CALL    DNO0
+        JR      NC,DNO3
+        JR      DNO10
+DNO3:   LD      A,B
+        LD      (DRINO),A
+        JP      FD
+        ;
+TRYAG3: LD      HL,MES15
+        LD      E,54H
+        LD      C,1DH                                ;29D
+        CALL    DISP2
+TRYAG4: LD      B,06H
+TRYAG5: CALL    KEYS
+        BIT     3,A
+        JP      Z,CMT
+        JR      TRYAG5
+        ;
+DNO0:   IN      A,(PIOA)
+        AND     0F0H
+        OR      D
+        OUT     (PIOA),A
+        IN      A,(PIOB)
+        LD      B,00H
+        LD      C,04H
+        RRCA    
+DNO1:   RRCA    
+        RET     NC
+        INC     B
+        DEC     C
+        JR      NZ,DNO1
+        RET     
+        ;
+        ;  TIME DELAY (1M &60M &80U )
+        ;
+DLY80U: PUSH    DE
+        LD      DE,000DH                            ;13D
+        JP      DLYT
+DLY1M:  PUSH    DE
+        LD      DE,0082H                            ;130D
+        JP      DLYT
+DLY60M: PUSH    DE
+        LD      DE,1A2CH                            ;6700D
+DLYT:   DEC     DE
+        LD      A,E
+        OR      D
+        JR      NZ,DLYT
+        POP     DE
+        RET     
+        ;
+        ;
+        ;                                             ;
+        ;   INTRAM EXROM                              ;
+        ;                                             ;
+        ;
+EXROMT: LD      HL,8000H
+        LD      IX,EROM1
+        JR      SEROMA
+EROM1:  IN      A,(0F9H)
+        CP      00H
+        JP      NZ,NKIN
+        LD      IX,EROM2
+ERMT1:  JR      SEROMA
+EROM2:  IN      A,(0F9H)
+        LD      (HL),A
+        INC     HL
+        LD      A,L
+        OR      H
+        JR      NZ,ERMT1
+        OUT     (0F8H),A
+        JP      NST
+        ;
+SEROMA: LD      A,H
+        OUT     (0F8H),A
+        LD      A,L
+        OUT     (0F9H),A
+        LD      D,04H
+SEROMD: DEC     D
+        JR      NZ,SEROMD
+        JP      (IX)
+
+;----------------------------------------------------------
+; Variables/Work area
+;----------------------------------------------------------
+
+IBUFE:  EQU    0CF00H
+ATRB:   EQU    0CF00H
+NAME:   EQU    0CF01H
+SIZE:   EQU    0CF12H
+DTADR:  EQU    0CF14H
+SUMDT:  EQU    0FFE0H
+TMCNT:  EQU    0FFE2H
+        ;
+        ;
+        ;INPUT BUFFER ADDRESS
+        ;
+IBADR1: EQU    0CF00H
+IBADR2: EQU    8000H
+        ;
+        ;   SUBROUTINE WORK
+        ;
+NTRACK: EQU    0FFE0H
+NSECT:  EQU    0FFE1H
+BSIZE:  EQU    0FFE2H
+STTR:   EQU    0FFE4H
+STSE:   EQU    0FFE5H
+MTFG:   EQU    0FFE6H
+CLBF0:  EQU    0FFE7H
+CLBF1:  EQU    0FFE8H
+CLBF2:  EQU    0FFE9H
+CLBF3:  EQU    0FFEAH
+RETRY:  EQU    0FFEBH
+DRINO:  EQU    0FFECH
+
+        ;
+        ;
+        ;
+        ;
+        ;
+        ;  MFM MINIFLOPPY CONTROL
+        ;
+        ;
+        ;
+        ;  CASE OF DISK INITIALIZE
+        ;     DRIVE NO=DRINO (0-3)
+        ;
+        ;  CASE OF SEQUENTIAL READ
+        ;     DRIVE NO=DRINO (0-3)
+        ;     BYTE SIZE     =IY+2,3
+        ;     ADDRESS       =IX+0,1
+        ;     NEXT TRACK    =IY+0
+        ;     NEXT SECTOR   =IY+1
+        ;     START TRACK   =IY+4
+        ;     START SECTOR  =IY+5
+        ;
+        ;
+        ; I/O PORT ADDRESS
+        ;
+CR:     EQU    0D8H                                ;STATUS/COMMAND PORT
+TR:     EQU    0D9H                                ;TRACK REG PORT
+SCR:    EQU    0DAH                                ;SECTOR REG PORT
+DR:     EQU    0DBH                                ;DATA REG PORT
+DM:     EQU    0DCH                                ;MOTOR/DRIVE PORT
+HS:     EQU    0DDH                                ;HEAD SIDE SELECT PORT
+PPIA:   EQU    0E0H
+PPIB:   EQU    0E1H
+PPIC:   EQU    0E2H
+PPICTL: EQU    0E3H
+PIOA:   EQU    0E8H
+PIOCTLA:EQU    0E9H
+PIOB:   EQU    0EAH
+PIOCTLB:EQU    0EBH
+GRPHCTL:EQU    0F4H
diff --git a/software/asm/IPL.obj b/software/asm/IPL.obj
new file mode 100644
index 0000000..f46fa39
Binary files /dev/null and b/software/asm/IPL.obj differ
diff --git a/software/asm/IPL.sym b/software/asm/IPL.sym
new file mode 100644
index 0000000..42a7332
--- /dev/null
+++ b/software/asm/IPL.sym
@@ -0,0 +1,140 @@
+?RDD: equ 0CFH
+?RDI: equ 0AEH
+BLK1: equ 1E5H
+BLK2: equ 1EDH
+BLK3: equ 1EFH
+BOOTER: equ 23FH
+BREAD: equ 47AH
+BUSY: equ 421H
+BUSY0: equ 42BH
+BUSY1: equ 439H
+BUSY2: equ 428H
+CLEAR: equ 2BH
+CMT: equ 6BH
+CONVRT: equ 43FH
+DCHK: equ 458H
+DEL1M: equ 223H
+DEL6: equ 21DH
+DISP: equ 246H
+DISP1: equ 256H
+DISP2: equ 239H
+DISP3: equ 24EH
+DLY1M: equ 5DDH
+DLY2: equ 229H
+DLY60M: equ 5E4H
+DLY80U: equ 5D6H
+DLYT: equ 5E8H
+DM1: equ 210H
+DNO: equ 58AH
+DNO0: equ 5C1H
+DNO1: equ 5CFH
+DNO10: equ 594H
+DNO3: equ 5A4H
+DTCK1: equ 477H
+EDGE: equ 121H
+EDGE1: equ 129H
+EIRTN: equ 0CDH
+ERMT1: equ 603H
+EROM1: equ 5F8H
+EROM2: equ 605H
+ERR: equ 556H
+ERR1: equ 559H
+EXROMT: equ 5EFH
+FD: equ 33CH
+FDCC: equ 5FH
+FR: equ 1F4H
+FR1: equ 1F6H
+IPLMC: equ 335H
+KEYIN: equ 3DH
+KEYS: equ 4DH
+KEYS1: equ 4BH
+KYEMES: equ 1CEH
+L0211: equ 211H
+L0212: equ 212H
+L022B: equ 22BH
+LDMSG: equ 230H
+MCHECK: equ 35FH
+MES1: equ 261H
+MES10: equ 2B3H
+MES11: equ 2BFH
+MES12: equ 2D0H
+MES13: equ 2DFH
+MES14: equ 2EEH
+MES15: equ 309H
+MES16: equ 326H
+MES3: equ 26FH
+MES6: equ 28BH
+MES8: equ 299H
+MES9: equ 2A6H
+MISMCH: equ 9EH
+MOFF: equ 3F3H
+MOT1: equ 19CH
+MOTOR: equ 186H
+MOTR: equ 1B1H
+MOTRD: equ 1AEH
+MSTOP: equ 1B5H
+MTD1: equ 3D2H
+MTD2: equ 3D5H
+MTON: equ 3CCH
+NKIN: equ 57H
+NMASTE: equ 54AH
+NODISK: equ 38CH
+NST: equ 2H
+OPEN: equ 1C2H
+PLAY: equ 1D9H
+RBY1: equ 136H
+RBY2: equ 147H
+RBY3: equ 150H
+RBYTE: equ 132H
+RCLB: equ 409H
+RD1: equ 0B7H
+RDDAT: equ 0CFH
+RDINF: equ 0AEH
+RE0: equ 490H
+RE1: equ 4AAH
+RE2: equ 4ACH
+RE3: equ 4F7H
+RE4: equ 4D4H
+RE5: equ 4EFH
+RE6: equ 4D2H
+RE7: equ 519H
+RE8: equ 49FH
+READ1: equ 483H
+READY: equ 399H
+REDY0: equ 3AEH
+REE: equ 51EH
+RET2S: equ 0C6H
+RETS: equ 4EEH
+REW: equ 20BH
+REX: equ 510H
+RRW: equ 207H
+RTAPE: equ 0DBH
+RTP2: equ 0E0H
+RTP3: equ 0F2H
+RTP5: equ 113H
+RTP6: equ 119H
+SEEK: equ 3E2H
+SEROMA: equ 612H
+SEROMD: equ 61AH
+SPDIN: equ 17AH
+ST1: equ 90H
+START: equ 6H
+STPEIR: equ 0CAH
+TM0: equ 15BH
+TM1: equ 15EH
+TM2: equ 161H
+TM3: equ 16BH
+TMARK: equ 152H
+TRANS: equ 448H
+TRANS1: equ 44FH
+TRTN1: equ 11DH
+TRYAG: equ 55FH
+TRYAG1: equ 57CH
+TRYAG2: equ 55CH
+TRYAG3: equ 5ABH
+TRYAG4: equ 5B5H
+TRYAG5: equ 5B7H
+WAIT: equ 52DH
+WAIT0: equ 537H
+WAIT1: equ 545H
+WAIT2: equ 534H
diff --git a/software/asm/MZ700.LST b/software/asm/MZ700.LST
new file mode 100644
index 0000000..20cec33
--- /dev/null
+++ b/software/asm/MZ700.LST
@@ -0,0 +1,5170 @@
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 1 - 9.6.1998 9:06:29
+
+
+      1/       0 :                      ; MONITOR PROGRAM 1Z-013A 
+      2/       0 :                      ;    (MZ700) FOR PAL 
+      3/       0 :                      ;      REV. 83.4.7
+      4/       0 :                      ; Tuesday, 02 of June 1998 at 10:02 PM
+      5/       0 :                      ; Tuesday, 09 of June 1998 at 07:17 AM
+      6/       0 :                      	CPU	Z80
+      7/       0 :                      	org	0000h 			; 0000h Entrypoint 
+      8/       0 :  C3 4A 00            MONIT:  JP      START		; MONITOR ON
+      9/       3 :  C3 E6 07            GETL:   JP      QGETL		; GET LINE (END "CR")
+     10/       6 :  C3 0E 09            LETNL:  JP      QLTNL		; NEW LINE
+     11/       9 :  C3 18 09            NL:     JP      QNL		;
+     12/       C :  C3 20 09            PRNTS:  JP      QPRTS		; PRINT SPACE
+     13/       F :  C3 24 09            PRNTT:  JP      QPRTT		; PRINT TAB
+     14/      12 :  C3 35 09            PRNT:   JP      QPRNT		; 1 CHARACTER PRINT
+     15/      15 :  C3 93 08            MSG:    JP      QMSG		; 1 LINE PRINT (END "0DH")
+     16/      18 :  C3 A1 08            MSGX:   JP      QMSGX		; RST 18H
+     17/      1B :  C3 BD 08            GETKY:  JP      QGET		; GET KEY
+     18/      1E :  C3 32 0A            BRKEY:  JP      QBRK		; GET BREAK
+     19/      21 :  C3 36 04            WRINF:  JP      QWRI		; WRITE INFORMATION
+     20/      24 :  C3 75 04            WRDAT:  JP      QWRD		; WRITE DATA
+     21/      27 :  C3 D8 04            RDINF:  JP      QRDI		; READ INFORMATION
+     22/      2A :  C3 F8 04            RDDAT:  JP      QRDD		; READ DATA
+     23/      2D :  C3 88 05            VERFY:  JP      QVRFY		; VERIFYING CMT
+     24/      30 :  C3 C7 01            MELDY:  JP      QMLDY		; RST 30H
+     25/      33 :  C3 08 03            TIMST:  JP      QTMST		; TIME SET
+     26/      36 :  00                          NOP
+     27/      37 :  00                          NOP
+     28/      38 :  C3 38 10                    JP      1038H		; INTERRUPT ROUTINE (8253)
+     29/      3B :  C3 58 03            TIMRD:  JP      QTMRD		; TIME READ
+     30/      3E :  C3 77 05            BELL:   JP      QBEL		; BELL ON
+     31/      41 :  C3 E5 02            XTEMP:  JP      QTEMP		; TEMPO SET (1 - 7)
+     32/      44 :  C3 AB 02            MSTA:   JP      MLDST		; MELODY START
+     33/      47 :  C3 BE 02            MSTP:   JP      MLDSP		; MELODY STOP
+     34/      4A :                      
+     35/      4A :  31 F0 10            START:  LD      SP,SPV		; STACK SET (10F0H)
+     36/      4D :  ED 56                       IM      1		; IM 1 SET
+     37/      4F :  CD 3E 07                    CALL    QMODE		; 8255 MODE SET
+     38/      52 :  CD 32 0A                    CALL    QBRK		; CTRL ?
+     39/      55 :  30 19                       JR      NC,ST0
+     40/      57 :  FE 20                       CP      20H		; KEY IS CTRL KEY
+     41/      59 :  20 15                       JR      NZ,ST0
+     42/      5B :  D3 E1               CMY0:   OUT     (0E1H),A		; D000-FFFFH IS DRAM
+     43/      5D :  11 F0 FF                    LD      DE,0FFF0H	; TRANS. ADR.
+     44/      60 :  21 6B 00                    LD      HL,DMCP		; MEMORY CHANG PROGRAM
+     45/      63 :  01 05 00                    LD      BC,05H		; BYTE SIZE
+     46/      66 :  ED B0                       LDIR    
+     47/      68 :  C3 F0 FF                    JP      0FFF0H		; JUMP $FFF0
+     48/      6B :                      
+     49/      6B :  D3 E0               DMCP:   OUT     (0E0H),A		; 0000H-0FFFH IS DRAM
+     50/      6D :  C3 00 00                    JP      0000H
+     51/      70 :                      
+     52/      70 :  06 FF               ST0:    LD      B,0FFH		; BUFFER CLEAR
+     53/      72 :  21 F1 10                    LD      HL,NAME		; 10F1H-11F0H CLEAR
+     54/      75 :  CD D8 0F                    CALL    QCLER
+     55/      78 :  3E 16                       LD      A,16H		; LASTER CLR.
+     56/      7A :  CD 12 00                    CALL    PRNT
+     57/      7D :  3E 71                       LD      A,71H		; BACK:BLUE CHA.:WRITE
+     58/      7F :  21 00 D8                    LD      HL,0D800H	; COLOR ADDRESS
+     59/      82 :  CD D5 09                    CALL    NCLR8
+     60/      85 :  21 8D 03                    LD      HL,TIMIN	; INTERRUPT JUMP ROUTINE
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 2 - 9.6.1998 9:06:29
+
+
+     61/      88 :  3E C3                       LD      A,0C3H
+     62/      8A :  32 38 10                    LD      (1038H),A
+     63/      8D :  22 39 10                    LD      (1039H),HL
+     64/      90 :  3E 04                       LD      A,04H		; NORMAL TEMPO
+     65/      92 :  32 9E 11                    LD      (TEMPW),A
+     66/      95 :  CD BE 02                    CALL    MLDSP		; MELODY STOP
+     67/      98 :  CD 09 00                    CALL    NL
+     68/      9B :  11 E7 06                    LD      DE,MSGQ3	; ** MONITOR 1Z-013A **
+     69/      9E :  DF                          RST     18H		; CALL MGX
+     70/      9F :  CD 77 05                    CALL    QBEL
+     71/      A2 :  3E 01               SS:     LD      A,01H
+     72/      A4 :  32 9D 11                    LD      (SWRK),A	; KEY IN SILENT
+     73/      A7 :  21 00 E8                    LD      HL,0E800H	; USR ROM?
+     74/      AA :  77                          LD      (HL),A		; ROM CHECK
+     75/      AB :  18 55                       JR      FD2
+     76/      AD :                      
+     77/      AD :  CD 09 00            ST1:    CALL    NL
+     78/      B0 :  3E 2A                       LD      A,2AH		; "*" PRINT
+     79/      B2 :  CD 12 00                    CALL    PRNT
+     80/      B5 :  11 A3 11                    LD      DE,BUFER	; GET LINE WORK (11A3H)
+     81/      B8 :  CD 03 00                    CALL    GETL
+     82/      BB :  1A                  ST2:    LD      A,(DE)
+     83/      BC :  13                          INC     DE
+     84/      BD :  FE 0D                       CP      0DH
+     85/      BF :  28 EC                       JR      Z,ST1
+     86/      C1 :  FE 4A                       CP      'J'		; JUMP
+     87/      C3 :  28 2E                       JR      Z,GOTO
+     88/      C5 :  FE 4C                       CP      'L'		; LOAD PROGRAM
+     89/      C7 :  28 48                       JR      Z,LOAD
+     90/      C9 :  FE 46                       CP      'F'		; FLOPPY ACCESS
+     91/      CB :  28 32                       JR      Z,FD
+     92/      CD :  FE 42                       CP      'B'		; KEY IN BELL
+     93/      CF :  28 26                       JR      Z,SG
+     94/      D1 :  FE 23                       CP      '#'		; CHANG MEMORY
+     95/      D3 :  28 86                       JR      Z,CMY0
+     96/      D5 :  FE 50                       CP      'P'		; PRINTER TEST
+     97/      D7 :  28 7C                       JR      Z,PTEST
+     98/      D9 :  FE 4D                       CP      'M'		; MEMORY CORRECTION
+     99/      DB :  CA A8 07                    JP      Z,MCOR
+    100/      DE :  FE 53                       CP      'S'		; SAVE DATA
+    101/      E0 :  CA 5E 0F                    JP      Z,SAVE
+    102/      E3 :  FE 56                       CP      'V'		; VERIFYING DATA
+    103/      E5 :  CA CB 0F                    JP      Z,VRFY
+    104/      E8 :  FE 44                       CP      'D'		; DUMP DATA
+    105/      EA :  CA 29 0D                    JP      Z,DUMP
+    106/      ED :  00                          NOP     
+    107/      EE :  00                          NOP     
+    108/      EF :  00                          NOP     
+    109/      F0 :  00                          NOP     
+    110/      F1 :  18 C8                       JR      ST2		; NO COMMAND
+    111/      F3 :                      
+    112/      F3 :                      ;	JUMP COMMAND
+    113/      F3 :                      
+    114/      F3 :  CD 3D 01            GOTO:   CALL    HEXIY
+    115/      F6 :  E9                          JP      (HL)
+    116/      F7 :                      
+    117/      F7 :                      ;	KEY SOUND ON/OFF
+    118/      F7 :                      
+    119/      F7 :  3A 9D 11            SG:     LD      A,(SWRK)	; D0=SOUND WORK
+    120/      FA :  1F                          RRA     
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 3 - 9.6.1998 9:06:29
+
+
+    121/      FB :  3F                          CCF     		; CHANGE MODE
+    122/      FC :  17                          RLA     
+    123/      FD :  18 A5                       JR      SS+2
+    124/      FF :                      
+    125/      FF :                      ;	FLOPPY
+    126/      FF :                      
+    127/      FF :  21 00 F0            FD:     LD      HL,0F000H	; FLOPPY I/O CHECK
+    128/     102 :  7E                  FD2:    LD      A,(HL)
+    129/     103 :  B7                          OR      A
+    130/     104 :  20 A7                       JR      NZ,ST1
+    131/     106 :  E9                  FD1:    JP      (HL)
+    132/     107 :                      
+    133/     107 :                      ;	ERROR (LOADING)
+    134/     107 :                      
+    135/     107 :  FE 02               QER:    CP      02H		; A=02H : BREAK IN
+    136/     109 :  28 A2                       JR      Z,ST1
+    137/     10B :  11 47 01                    LD      DE,MSGE1	; CHECK SUM ERROR
+    138/     10E :  DF                          RST     18H		; CALL MSGX
+    139/     10F :  18 9C               L010F:	JR      ST1
+    140/     111 :                      
+    141/     111 :                      ;	LOAD COMMAND
+    142/     111 :                      
+    143/     111 :  CD D8 04            LOAD:  	CALL    QRDI
+    144/     114 :  38 F1                       JR      C,QER
+    145/     116 :  CD 09 00            LOA0:   CALL    NL
+    146/     119 :  11 A0 09                    LD      DE,MSGQ2	; LOADING
+    147/     11C :  DF                          RST     18H		; CALL MSGX
+    148/     11D :  11 F1 10                    LD      DE,NAME		; FILE NAME
+    149/     120 :  DF                          RST     18H		; CALL MSGX
+    150/     121 :  CD F8 04                    CALL    QRDD
+    151/     124 :  38 E1                       JR      C,QER
+    152/     126 :  2A 06 11                    LD      HL,(EXADR)	; EXECUTE ADDRESS
+    153/     129 :  7C                          LD      A,H
+    154/     12A :  FE 12                       CP      12H		; EXECUTE CHECK
+    155/     12C :  38 E1                       JR      C,L010F
+    156/     12E :  E9                          JP      (HL)
+    157/     12F :                      
+    158/     12F :                      ;	GETLINE AND BREAK IN CHECK
+    159/     12F :                      ;
+    160/     12F :                      ;	EXIT BREAK IN THEN JUMP (ST1)
+    161/     12F :                      ;	ACC=TOP OF LINE DATA
+    162/     12F :                      
+    163/     12F :  E3                  BGETL:  EX      (SP),HL
+    164/     130 :  C1                          POP     BC		; STACK LOAD
+    165/     131 :  11 A3 11                    LD      DE,BUFER	; MONITOR GETLINE BUFF
+    166/     134 :  CD 03 00                    CALL    GETL
+    167/     137 :  1A                          LD      A,(DE)
+    168/     138 :  FE 1B                       CP      1BH		; BREAK CODE
+    169/     13A :  28 D3                       JR      Z,L010F		; JP Z,ST1
+    170/     13C :  E9                          JP      (HL)
+    171/     13D :                      
+    172/     13D :                      ;	ASCII TO HEX CONVERT
+    173/     13D :                      ;	INPUT (DE)=ASCII
+    174/     13D :                      ;	CY=1 THEN JUMP (ST1)
+    175/     13D :                      
+    176/     13D :  FD E3               HEXIY:  EX      (SP),IY
+    177/     13F :  F1                          POP     AF
+    178/     140 :  CD 10 04                    CALL    HLHEX
+    179/     143 :  38 CA                       JR      C,L010F		; JP C,ST1
+    180/     145 :  FD E9                       JP      (IY)
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 4 - 9.6.1998 9:06:29
+
+
+    181/     147 :                      
+    182/     147 :  43 48 45 43 4B 20   MSGE1:	DB	"CHECK SUM ER.\r"
+                    53 55 4D 20 45 52 
+                    2E 0D 
+    183/     155 :                      
+    184/     155 :                      ;	PLOTTER PRINTER TEST COMMAND
+    185/     155 :                      ;	(DPG23)
+    186/     155 :                      ;	&=CONTROL COMMANDS GROUP
+    187/     155 :                      ;	C=PEN CHANGE
+    188/     155 :                      ;	G=GRAPH MODE
+    189/     155 :                      ;	S=80 CHA. IN 1 LINE
+    190/     155 :                      ;	L=40 CHA. IN 1 LINE
+    191/     155 :                      ;	T=PLOTTER TEST
+    192/     155 :                      ;	IN (DE)=PRINT DATA
+    193/     155 :                      
+    194/     155 :  1A                  PTEST:  LD      A,(DE)
+    195/     156 :  FE 26                       CP      '&'
+    196/     158 :  20 16                       JR      NZ,PTST1
+    197/     15A :  13                  PTST0:  INC     DE
+    198/     15B :  1A                          LD      A,(DE)
+    199/     15C :  FE 4C                       CP      'L'		; 40 IN 1 LINE
+    200/     15E :  28 16                       JR      Z,PLPT
+    201/     160 :  FE 53                       CP      'S'		; 80 IN 1 LINE
+    202/     162 :  28 17                       JR      Z,PPLPT
+    203/     164 :  FE 43                       CP      'C'		; PEN CHANGE
+    204/     166 :  28 23                       JR      Z,PEN
+    205/     168 :  FE 47                       CP      'G'		; GRAPH MODE
+    206/     16A :  28 18                       JR      Z,PLOT
+    207/     16C :  FE 54                       CP      'T'		; TEST
+    208/     16E :  28 10                       JR      Z,PTRN
+    209/     170 :  CD A5 01            PTST1:  CALL    PMSG		; PLOT MESSAGE
+    210/     173 :  C3 AD 00                    JP      ST1
+    211/     176 :                      
+    212/     176 :  11 70 04            PLPT:   LD      DE,LLPT		; 01-09-09-0B-0D
+    213/     179 :  18 F5                       JR      PTST1
+    214/     17B :                      
+    215/     17B :  11 D5 03            PPLPT:  LD      DE,SLPT		; 01-09-09-09-0D
+    216/     17E :  18 F0                       JR      PTST1
+    217/     180 :                      
+    218/     180 :  3E 04               PTRN:   LD      A,04H		; TEST PATTERN
+    219/     182 :  18 02                       JR      PLOT+2
+    220/     184 :                      
+    221/     184 :  3E 02               PLOT:   LD      A,02H		; GRAPH CODE
+    222/     186 :  CD 8F 01            	CALL    LPRNT
+    223/     189 :  18 CF                       JR      PTST0
+    224/     18B :                      
+    225/     18B :  3E 1D               PEN:    LD      A,1DH		; 1 CHANGE CODE (TEXT MODE)
+    226/     18D :  18 F7                       JR      PLOT+2
+    227/     18F :                      
+    228/     18F :                      ;	1CHA. PRINT TO $LPT
+    229/     18F :                      ;	IN: ACC PRINT DATA
+    230/     18F :                      
+    231/     18F :  0E 00               LPRNT:  LD      C,0		; RDA TEST (READY? RDA=0)
+    232/     191 :  47                          LD      B,A		; PRINT DATA STORE
+    233/     192 :  CD B6 01                    CALL    RDA
+    234/     195 :  78                          LD      A,B
+    235/     196 :  D3 FF                       OUT     (0FFH),A		; DATA OUT 
+    236/     198 :  3E 80                       LD      A,80H		; RDP HIGH
+    237/     19A :  D3 FE                       OUT     (0FEH),A
+    238/     19C :  0E 01                       LD      C,01H		; RDA TEST
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 5 - 9.6.1998 9:06:29
+
+
+    239/     19E :  CD B6 01                    CALL    RDA
+    240/     1A1 :  AF                  	XOR     A		; RDP LOW
+    241/     1A2 :  D3 FE                       OUT     (0FEH),A
+    242/     1A4 :  C9                          RET     
+    243/     1A5 :                      
+    244/     1A5 :                      ;	$LPT MSG
+    245/     1A5 :                      ;	IN: DE DATA LOW ADDRESS
+    246/     1A5 :                      ;	0DH MSG END
+    247/     1A5 :                      
+    248/     1A5 :  D5                  PMSG:   PUSH    DE
+    249/     1A6 :  C5                          PUSH    BC
+    250/     1A7 :  F5                          PUSH    AF
+    251/     1A8 :  1A                  PMSG1:  LD      A,(DE)		; ACC=DATA
+    252/     1A9 :  CD 8F 01                    CALL    LPRNT
+    253/     1AC :  1A                          LD      A,(DE)
+    254/     1AD :  13                          INC     DE
+    255/     1AE :  FE 0D                       CP      0DH		; END?
+    256/     1B0 :  20 F6                       JR      NZ,PMSG1
+    257/     1B2 :  F1                          POP     AF
+    258/     1B3 :  C1                          POP     BC
+    259/     1B4 :  D1                          POP     DE
+    260/     1B5 :  C9                          RET     
+    261/     1B6 :                      
+    262/     1B6 :                      ;	RDA CHECK
+    263/     1B6 :                      ;	BRKEY IN TO MONITOR RETURN
+    264/     1B6 :                      ;	IN: C RDA CODE
+    265/     1B6 :                      
+    266/     1B6 :  DB FE               RDA:    IN      A,(0FEH)
+    267/     1B8 :  E6 0D                       AND     0DH		; RDA ONLY
+    268/     1BA :  B9                          CP      C
+    269/     1BB :  C8                          RET     Z
+    270/     1BC :  CD 1E 00                    CALL    BRKEY
+    271/     1BF :  20 F5                       JR      NZ,RDA
+    272/     1C1 :  31 F0 10                    LD      SP,SPV
+    273/     1C4 :  C3 AD 00                    JP      ST1
+    274/     1C7 :                      
+    275/     1C7 :                      ;	MELODY
+    276/     1C7 :                      ;	DE=DATA LOW ADDRESS
+    277/     1C7 :                      ;	EXIT CF=1 BREAK
+    278/     1C7 :                      ;	     CF=0 OK
+    279/     1C7 :                      
+    280/     1C7 :  C5                  QMLDY:  PUSH    BC
+    281/     1C8 :  D5                          PUSH    DE
+    282/     1C9 :  E5                          PUSH    HL
+    283/     1CA :  3E 02                       LD      A,02H
+    284/     1CC :  32 A0 11                    LD      (OCTV),A
+    285/     1CF :  06 01                       LD      B,01H
+    286/     1D1 :  1A                  MLD1:   LD      A,(DE)
+    287/     1D2 :  FE 0D                       CP      0DH		; CR
+    288/     1D4 :  28 3B                       JR      Z,MLD4
+    289/     1D6 :  FE C8                       CP      0C8H		; END MARK
+    290/     1D8 :  28 37                       JR      Z,MLD4
+    291/     1DA :  FE CF                       CP      0CFH		; UNDER OCTAVE
+    292/     1DC :  28 27                       JR      Z,MLD2
+    293/     1DE :  FE 2D                       CP      2DH		; "-" 
+    294/     1E0 :  28 23                       JR      Z,MLD2
+    295/     1E2 :  FE 2B                       CP      2BH		; "+"
+    296/     1E4 :  28 27                       JR      Z,MLD3
+    297/     1E6 :  FE D7                       CP      0D7H		; UPPER OCTAVE
+    298/     1E8 :  28 23                       JR      Z,MLD3
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 6 - 9.6.1998 9:06:29
+
+
+    299/     1EA :  FE 23                       CP      23H		; "#" HANON
+    300/     1EC :  21 6C 02                    LD      HL,MTBL
+    301/     1EF :  20 04                       JR      NZ,L01F5
+    302/     1F1 :  21 84 02                    LD      HL,MNTBL
+    303/     1F4 :  13                          INC     DE
+    304/     1F5 :  CD 1C 02            L01F5:	CALL    ONPU		; ONTYO SET
+    305/     1F8 :  38 D7                       JR      C,MLD1
+    306/     1FA :  CD C8 02                    CALL    RYTHM
+    307/     1FD :  38 15                       JR      C,MLD5
+    308/     1FF :  CD AB 02                    CALL    MLDST		; MELODY START
+    309/     202 :  41                          LD      B,C
+    310/     203 :  18 CC                       JR      MLD1
+    311/     205 :                      
+    312/     205 :  3E 03               MLD2:   LD      A,3
+    313/     207 :  32 A0 11            L0207:	LD      (OCTV),A
+    314/     20A :  13                          INC     DE
+    315/     20B :  18 C4                       JR      MLD1
+    316/     20D :                      
+    317/     20D :  3E 01               MLD3:   LD      A,01H
+    318/     20F :  18 F6                       JR      L0207
+    319/     211 :                      
+    320/     211 :  CD C8 02            MLD4:   CALL    RYTHM
+    321/     214 :  F5                  MLD5:   PUSH    AF
+    322/     215 :  CD BE 02                    CALL    MLDSP
+    323/     218 :  F1                          POP     AF
+    324/     219 :  C3 9B 06                    JP      RET3
+    325/     21C :                      
+    326/     21C :                      ;	ONPU TO RATIO CONV
+    327/     21C :                      ;	EXIT (RATIO)=RATIO VALUE
+    328/     21C :                      ;	C=ONTYO*TEMPO
+    329/     21C :                      
+    330/     21C :  C5                  ONPU:   PUSH    BC
+    331/     21D :  06 08                       LD      B,8
+    332/     21F :  1A                  ONP1:   LD      A,(DE)
+    333/     220 :  BE                  L0220:	CP      (HL)
+    334/     221 :  28 09                       JR      Z,ONP2
+    335/     223 :  23                          INC     HL
+    336/     224 :  23                          INC     HL
+    337/     225 :  23                          INC     HL
+    338/     226 :  10 F8                       DJNZ    L0220
+    339/     228 :  37                          SCF     
+    340/     229 :  13                          INC     DE
+    341/     22A :  C1                          POP     BC
+    342/     22B :  C9                          RET     
+    343/     22C :                      
+    344/     22C :  23                  ONP2:   INC     HL
+    345/     22D :  D5                          PUSH    DE
+    346/     22E :  5E                          LD      E,(HL)
+    347/     22F :  23                          INC     HL
+    348/     230 :  56                          LD      D,(HL)
+    349/     231 :  EB                          EX      DE,HL
+    350/     232 :  7C                          LD      A,H
+    351/     233 :  B7                          OR      A
+    352/     234 :  28 09                       JR      Z,L023F
+    353/     236 :  3A A0 11                    LD      A,(OCTV)	; 11A0H OCTAVE WORK
+    354/     239 :  3D                  L0239:  DEC     A
+    355/     23A :  28 03                       JR      Z,L023F
+    356/     23C :  29                          ADD     HL,HL
+    357/     23D :  18 FA                       JR      L0239
+    358/     23F :                      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 7 - 9.6.1998 9:06:29
+
+
+    359/     23F :  22 A1 11            L023F:  LD      (RATIO),HL	; 11A1H ONPU RATIO
+    360/     242 :  21 A0 11                    LD      HL,OCTV
+    361/     245 :  36 02                       LD      (HL),02H
+    362/     247 :  2B                          DEC     HL
+    363/     248 :  D1                          POP     DE
+    364/     249 :  13                          INC     DE
+    365/     24A :  1A                          LD      A,(DE)
+    366/     24B :  47                          LD      B,A
+    367/     24C :  E6 F0                       AND     0F0H		; ONTYO ?
+    368/     24E :  FE 30                       CP      30H
+    369/     250 :  28 03                       JR      Z,L0255
+    370/     252 :  7E                          LD      A,(HL)		; HL=ONTYO
+    371/     253 :  18 05                       JR      L025A
+    372/     255 :                      
+    373/     255 :  13                  L0255:  INC     DE
+    374/     256 :  78                          LD      A,B
+    375/     257 :  E6 0F                       AND     0FH
+    376/     259 :  77                          LD      (HL),A		; HL=ONTYO
+    377/     25A :  21 9C 02            L025A:  LD      HL,OPTBL
+    378/     25D :  85                          ADD     A,L
+    379/     25E :  6F                          LD      L,A
+    380/     25F :  4E                          LD      C,(HL)
+    381/     260 :  3A 9E 11                    LD      A,(TEMPW)
+    382/     263 :  47                          LD      B,A
+    383/     264 :  AF                          XOR     A
+    384/     265 :  81                  ONP3:   ADD     A,C
+    385/     266 :  10 FD                       DJNZ    ONP3
+    386/     268 :  C1                          POP     BC
+    387/     269 :  4F                          LD      C,A
+    388/     26A :  AF                          XOR     A
+    389/     26B :  C9                          RET     
+    390/     26C :                      
+    391/     26C :  43                  MTBL:	DB	"C"
+    392/     26D :  46 08               	DW	0846H
+    393/     26F :  44                  	DB	"D"
+    394/     270 :  5F 07               	DW	075FH
+    395/     272 :  45                  	DB	"E"
+    396/     273 :  91 06               	DW	0691H
+    397/     275 :  46                  	DB	"F"
+    398/     276 :  33 06               	DW	0633H
+    399/     278 :  47                  	DB	"G"
+    400/     279 :  86 05               	DW	0586H
+    401/     27B :  41                  	DB	"A"
+    402/     27C :  EC 04               	DW	04ECH
+    403/     27E :  42                  	DB	"B"
+    404/     27F :  64 04               	DW	0464H
+    405/     281 :  52                  	DB	"R"
+    406/     282 :  00 00               	DW	0000H
+    407/     284 :  43                  MNTBL:	DB	"C"		; #C
+    408/     285 :  CF 07               	DW	07CFH
+    409/     287 :  44                  	DB	"D"		; #D
+    410/     288 :  F5 06               	DW	06F5H
+    411/     28A :  45                  	DB	"E"		; #E
+    412/     28B :  33 06               	DW	0633H
+    413/     28D :  46                  	DB	"F"		; #F
+    414/     28E :  DA 05               	DW	05DAH
+    415/     290 :  47                  	DB	"G"		; #G
+    416/     291 :  37 05               	DW	0537H
+    417/     293 :  41                  	DB	"A"		; #A
+    418/     294 :  A5 04               	DW	04A5H
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 8 - 9.6.1998 9:06:29
+
+
+    419/     296 :  42                  	DB	"B"		; #B
+    420/     297 :  23 04               	DW	0423H
+    421/     299 :  52                  	DB	"R"		; #R
+    422/     29A :  00 00               	DW	0000H
+    423/     29C :  01                  OPTBL:	DB	01H
+    424/     29D :  02                  	DB	02H
+    425/     29E :  03                  	DB	03H
+    426/     29F :  04                  	DB	04H
+    427/     2A0 :  06                  	DB	06H
+    428/     2A1 :  08                  	DB	08H
+    429/     2A2 :  0C                  	DB	0CH
+    430/     2A3 :  10                  	DB	10H
+    431/     2A4 :  18                  	DB	18H
+    432/     2A5 :  20                  	DB	20H
+    433/     2A6 :                      
+    434/     2A6 :                      ;	INCREMENT DE REG.
+    435/     2A6 :                      
+    436/     2A6 :  13                  P4DE:   INC     DE
+    437/     2A7 :  13                  	INC	DE
+    438/     2A8 :  13                          INC     DE
+    439/     2A9 :  13                          INC     DE
+    440/     2AA :  C9                          RET     
+    441/     2AB :                      
+    442/     2AB :                      ;	MELODY START & STOP
+    443/     2AB :                      
+    444/     2AB :  2A A1 11            MLDST:  LD      HL,(RATIO)
+    445/     2AE :  7C                          LD      A,H
+    446/     2AF :  B7                          OR      A
+    447/     2B0 :  28 0C                       JR      Z,MLDSP
+    448/     2B2 :  D5                          PUSH    DE
+    449/     2B3 :  EB                          EX      DE,HL
+    450/     2B4 :  21 04 E0                    LD      HL,CONT0
+    451/     2B7 :  73                          LD      (HL),E
+    452/     2B8 :  72                          LD      (HL),D
+    453/     2B9 :  3E 01                       LD      A,01H
+    454/     2BB :  D1                          POP     DE
+    455/     2BC :  18 06                       JR      MLDS1
+    456/     2BE :                      
+    457/     2BE :  3E 36               MLDSP:  LD      A,36H		; MODE SET (8253 C0)
+    458/     2C0 :  32 07 E0                    LD      (CONTF),A	; E007H
+    459/     2C3 :  AF                          XOR     A
+    460/     2C4 :  32 08 E0            MLDS1:  LD      (SUNDG),A	; E008H
+    461/     2C7 :  C9                          RET     		; TEHRO SET
+    462/     2C8 :                      
+    463/     2C8 :                      ;	RHYTHM
+    464/     2C8 :                      ;	B=COUNT DATA
+    465/     2C8 :                      ;	IN
+    466/     2C8 :                      ;	EXIT CF=1 BREAK
+    467/     2C8 :                      ;	     CF=0 OK
+    468/     2C8 :                      
+    469/     2C8 :  21 00 E0            RYTHM:  LD      HL,KEYPA	; E000H
+    470/     2CB :  36 F8                       LD      (HL),0F8H
+    471/     2CD :  23                          INC     HL
+    472/     2CE :  7E                          LD      A,(HL)
+    473/     2CF :  E6 81                       AND     81H		; BREAK IN CHECK
+    474/     2D1 :  20 02                       JR      NZ,L02D5
+    475/     2D3 :  37                          SCF     
+    476/     2D4 :  C9                          RET     
+    477/     2D5 :                      
+    478/     2D5 :  3A 08 E0            L02D5:  LD      A,(TEMP)	; E008H
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 9 - 9.6.1998 9:06:29
+
+
+    479/     2D8 :  0F                          RRCA    		; TEMPO OUT
+    480/     2D9 :  38 FA                       JR      C,L02D5
+    481/     2DB :  3A 08 E0            L02DB:  LD      A,(TEMP)
+    482/     2DE :  0F                          RRCA    
+    483/     2DF :  30 FA                       JR      NC,L02DB
+    484/     2E1 :  10 F2                       DJNZ    L02D5
+    485/     2E3 :  AF                          XOR     A
+    486/     2E4 :  C9                          RET     
+    487/     2E5 :                      
+    488/     2E5 :                      ;	TEMPO SET
+    489/     2E5 :                      ;	ACC=VALUE (1-7)
+    490/     2E5 :                      
+    491/     2E5 :  F5                  QTEMP:  PUSH    AF
+    492/     2E6 :  C5                          PUSH    BC
+    493/     2E7 :  E6 0F                       AND     0FH
+    494/     2E9 :  47                          LD      B,A
+    495/     2EA :  3E 08                       LD      A,8
+    496/     2EC :  90                          SUB     B
+    497/     2ED :  32 9E 11                    LD      (TEMPW),A
+    498/     2F0 :  C1                          POP     BC
+    499/     2F1 :  F1                          POP     AF
+    500/     2F2 :  C9                          RET     
+    501/     2F3 :                      
+    502/     2F3 :                      ;	CRT MANAGEMENT
+    503/     2F3 :                      ;	EXIT HL:DSPXY H=Y,L=X
+    504/     2F3 :                      ;	DE:MANG ADR. (ON DSPXY)
+    505/     2F3 :                      ;	A :MANG DATA
+    506/     2F3 :                      ;	CY:MANG=1
+    507/     2F3 :                      
+    508/     2F3 :  21 73 11            PMANG:  LD      HL,MANG		; CRT MANG POINTER
+    509/     2F6 :  3A 72 11                    LD      A,(1172H)	; DSPXY+1
+    510/     2F9 :  85                          ADD     A,L
+    511/     2FA :  6F                          LD      L,A
+    512/     2FB :  7E                          LD      A,(HL)
+    513/     2FC :  23                          INC     HL
+    514/     2FD :  CB 16                       RL      (HL)
+    515/     2FF :  B6                          OR      (HL)
+    516/     300 :  CB 1E                       RR      (HL)
+    517/     302 :  0F                          RRCA    
+    518/     303 :  EB                          EX      DE,HL
+    519/     304 :  2A 71 11                    LD      HL,(DSPXY)
+    520/     307 :  C9                          RET     
+    521/     308 :                      
+    522/     308 :                      ;	TIME SET
+    523/     308 :                      ;	ACC=0 : AM
+    524/     308 :                      ;	   =1 : PM
+    525/     308 :                      ;	DE=SEC: BINARY
+    526/     308 :                      
+    527/     308 :  F3                  QTMST:  DI      
+    528/     309 :  C5                          PUSH    BC
+    529/     30A :  D5                          PUSH    DE
+    530/     30B :  E5                          PUSH    HL
+    531/     30C :  32 9B 11                    LD      (AMPM),A	; AMPM DATA
+    532/     30F :  3E F0                       LD      A,0F0H
+    533/     311 :  32 9C 11                    LD      (TIMFG),A	; TIME FLAG
+    534/     314 :  21 C0 A8                    LD      HL,0A8C0H	; 12 HOURS (43200 SECONDS)
+    535/     317 :  AF                          XOR     A
+    536/     318 :  ED 52                       SBC     HL,DE		; COUNT DATA = 12H-IN DATA
+    537/     31A :  E5                          PUSH    HL
+    538/     31B :  00                          NOP     
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 10 - 9.6.1998 9:06:29
+
+
+    539/     31C :  EB                          EX      DE,HL
+    540/     31D :  21 07 E0                    LD      HL,CONTF	; E007H
+    541/     320 :  36 74                       LD      (HL),74H	; C1
+    542/     322 :  36 B0                       LD      (HL),0B0H	; C2
+    543/     324 :  2B                          DEC     HL		; CONT2
+    544/     325 :  73                          LD      (HL),E		; E006H
+    545/     326 :  72                          LD      (HL),D
+    546/     327 :  2B                          DEC     HL		; CONT1
+    547/     328 :  36 0A                       LD      (HL),0AH	; E005H STROBE 640,6�SECONDS COUNT2
+    548/     32A :  36 00                       LD      (HL),0
+    549/     32C :  23                          INC     HL
+    550/     32D :  23                          INC     HL		; CONTF
+    551/     32E :  36 80                       LD      (HL),80H	; E007H
+    552/     330 :  2B                          DEC     HL		; CONT2
+    553/     331 :  4E                  QTMS1:  LD      C,(HL)		; E006H
+    554/     332 :  7E                          LD      A,(HL)
+    555/     333 :  BA                          CP      D
+    556/     334 :  20 FB                       JR      NZ,QTMS1
+    557/     336 :  79                          LD      A,C
+    558/     337 :  BB                          CP      E
+    559/     338 :  20 F7                       JR      NZ,QTMS1
+    560/     33A :  2B                          DEC     HL		; E005H
+    561/     33B :  00                          NOP     
+    562/     33C :  00                          NOP     
+    563/     33D :  00                          NOP     
+    564/     33E :  36 FB                       LD      (HL),0FBH	; 1 SECOND (15611HZ) E005H
+    565/     340 :  36 3C                       LD      (HL),3CH
+    566/     342 :  23                          INC     HL
+    567/     343 :  D1                          POP     DE
+    568/     344 :  4E                  QTMS2:  LD      C,(HL)		; E006H
+    569/     345 :  7E                          LD      A,(HL)
+    570/     346 :  BA                          CP      D
+    571/     347 :  20 FB                       JR      NZ,QTMS2
+    572/     349 :  79                          LD      A,C
+    573/     34A :  BB                          CP      E
+    574/     34B :  20 F7                       JR      NZ,QTMS2
+    575/     34D :  E1                          POP     HL
+    576/     34E :  D1                          POP     DE
+    577/     34F :  C1                          POP     BC
+    578/     350 :  FB                          EI      
+    579/     351 :  C9                          RET     
+    580/     352 :                      
+    581/     352 :                      ;	BELL DATA
+    582/     352 :                      ;	
+    583/     352 :  D7                  QBELD:	DB	0D7H
+    584/     353 :  41 30               	DB	"A0"
+    585/     355 :  0D                  	DB	0DH
+    586/     356 :  00                          NOP     
+    587/     357 :  00                          NOP     
+    588/     358 :                      
+    589/     358 :                      ;	TIME READ
+    590/     358 :                      ;	EXIT ACC=0 :AM
+    591/     358 :                      ;	        =1 :PM
+    592/     358 :                      ;	     DE=SEC. BINARY
+    593/     358 :                      
+    594/     358 :  E5                  QTMRD:  PUSH    HL
+    595/     359 :  21 07 E0                    LD      HL,CONTF
+    596/     35C :  36 80                       LD      (HL),80H	; E007H C2
+    597/     35E :  2B                          DEC     HL		; CONT2
+    598/     35F :  F3                          DI      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 11 - 9.6.1998 9:06:29
+
+
+    599/     360 :  5E                          LD      E,(HL)
+    600/     361 :  56                          LD      D,(HL)		; e006H C2 MODE0
+    601/     362 :  FB                          EI      
+    602/     363 :  7B                  L0363:  LD      A,E
+    603/     364 :  B2                          OR      D
+    604/     365 :  28 0E                       JR      Z,QTMR1
+    605/     367 :  AF                          XOR     A
+    606/     368 :  21 C0 A8                    LD      HL,0A8C0H	; 12 HOURS
+    607/     36B :  ED 52                       SBC     HL,DE
+    608/     36D :  38 10                       JR      C,QTMR2
+    609/     36F :  EB                          EX      DE,HL
+    610/     370 :  3A 9B 11                    LD      A,(AMPM)
+    611/     373 :  E1                          POP     HL
+    612/     374 :  C9                          RET     
+    613/     375 :                      
+    614/     375 :  11 C0 A8            QTMR1:  LD      DE,0A8C0H
+    615/     378 :  3A 9B 11            L0378:  LD      A,(AMPM)
+    616/     37B :  EE 01                       XOR     01H
+    617/     37D :  E1                          POP     HL
+    618/     37E :  C9                          RET     
+    619/     37F :                      
+    620/     37F :  F3                  QTMR2:  DI      
+    621/     380 :  21 06 E0                    LD      HL,CONT2
+    622/     383 :  7E                          LD      A,(HL)
+    623/     384 :  2F                          CPL     
+    624/     385 :  5F                          LD      E,A
+    625/     386 :  7E                          LD      A,(HL)
+    626/     387 :  2F                          CPL     
+    627/     388 :  57                          LD      D,A
+    628/     389 :  FB                          EI      
+    629/     38A :  13                          INC     DE
+    630/     38B :  18 EB                       JR      L0378
+    631/     38D :                      
+    632/     38D :                      ;	TIME INTERRUPT
+    633/     38D :                      
+    634/     38D :  F5                  TIMIN:  PUSH    AF
+    635/     38E :  C5                          PUSH    BC
+    636/     38F :  D5                          PUSH    DE
+    637/     390 :  E5                          PUSH    HL
+    638/     391 :  21 9B 11                    LD      HL,AMPM
+    639/     394 :  7E                          LD      A,(HL)
+    640/     395 :  EE 01                       XOR     01H
+    641/     397 :  77                          LD      (HL),A
+    642/     398 :  21 07 E0                    LD      HL,CONTF
+    643/     39B :  36 80                       LD      (HL),80H	; CONT2
+    644/     39D :  2B                          DEC     HL
+    645/     39E :  E5                          PUSH    HL
+    646/     39F :  5E                          LD      E,(HL)
+    647/     3A0 :  56                          LD      D,(HL)
+    648/     3A1 :  21 C0 A8                    LD      HL,0A8C0H
+    649/     3A4 :  19                          ADD     HL,DE
+    650/     3A5 :  2B                          DEC     HL
+    651/     3A6 :  2B                          DEC     HL
+    652/     3A7 :  EB                          EX      DE,HL
+    653/     3A8 :  E1                          POP     HL
+    654/     3A9 :  73                          LD      (HL),E
+    655/     3AA :  72                          LD      (HL),D
+    656/     3AB :  E1                          POP     HL
+    657/     3AC :  D1                          POP     DE
+    658/     3AD :  C1                          POP     BC
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 12 - 9.6.1998 9:06:29
+
+
+    659/     3AE :  F1                          POP     AF
+    660/     3AF :  FB                          EI      
+    661/     3B0 :  C9                          RET     
+    662/     3B1 :                      
+    663/     3B1 :                      ;	SPACE PRINT AND DISP ACC
+    664/     3B1 :                      ;	INPUT:HL=DISP. ADR.
+    665/     3B1 :                      
+    666/     3B1 :  CD 20 09            SPHEX:  CALL    QPRTS		; SPACE PRINT
+    667/     3B4 :  7E                          LD      A,(HL)
+    668/     3B5 :  CD C3 03                    CALL    PRTHX		; DSP OF ACC (ASCII)
+    669/     3B8 :  7E                          LD      A,(HL)
+    670/     3B9 :  C9                          RET     
+    671/     3BA :                      
+    672/     3BA :                      ;	(ASCII PRINT) FOR HL
+    673/     3BA :                      
+    674/     3BA :  7C                  PRTHL:  LD      A,H
+    675/     3BB :  CD C3 03                    CALL    PRTHX
+    676/     3BE :  7D                          LD      A,L
+    677/     3BF :  18 02                       JR      PRTHX
+    678/     3C1 :                      
+    679/     3C1 :  00                          NOP     
+    680/     3C2 :  00                          NOP     
+    681/     3C3 :                      
+    682/     3C3 :                      ;	(ASCII PRINT) FOR ACC
+    683/     3C3 :                      
+    684/     3C3 :  F5                  PRTHX:  PUSH    AF
+    685/     3C4 :  0F                          RRCA    
+    686/     3C5 :  0F                          RRCA    
+    687/     3C6 :  0F                          RRCA    
+    688/     3C7 :  0F                          RRCA    
+    689/     3C8 :  CD DA 03                    CALL    ASC
+    690/     3CB :  CD 12 00                    CALL    PRNT
+    691/     3CE :  F1                          POP     AF
+    692/     3CF :  CD DA 03                    CALL    ASC
+    693/     3D2 :  C3 12 00                    JP      PRNT
+    694/     3D5 :                      
+    695/     3D5 :                      ;	80 CHA. 1 LINE CODE (DATA)
+    696/     3D5 :                      
+    697/     3D5 :  01                  SLPT:	DB	01H		; TEXT MODE
+    698/     3D6 :  09                  	DB	09H
+    699/     3D7 :  09                  	DB	09H
+    700/     3D8 :  09                  	DB	09H
+    701/     3D9 :  0D                  	DB	0DH
+    702/     3DA :                      
+    703/     3DA :                      ;	HEXADECIMAL TO ASCII
+    704/     3DA :                      ;	IN  : ACC (D3-D0)=HEXADECIMAL
+    705/     3DA :                      ;	EXIT: ACC = ASCII
+    706/     3DA :  E6 0F               ASC:    AND     0FH
+    707/     3DC :  FE 0A                       CP      0AH
+    708/     3DE :  38 02                       JR      C,NOADD
+    709/     3E0 :  C6 07                       ADD     A,07H
+    710/     3E2 :  C6 30               NOADD:  ADD     A,30H
+    711/     3E4 :  C9                          RET     
+    712/     3E5 :                      
+    713/     3E5 :                      ;	ASCII TO HEXADECIMAL
+    714/     3E5 :                      ;	IN  : ACC = ASCII
+    715/     3E5 :                      ;	EXIT: ACC = HEXADECIMAL
+    716/     3E5 :                      ;	      CY  = 1 ERROR
+    717/     3E5 :                      
+    718/     3E5 :  D6 30               HEXJ:   SUB     30H
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 13 - 9.6.1998 9:06:29
+
+
+    719/     3E7 :  D8                          RET     C		; <0
+    720/     3E8 :  FE 0A                       CP      0AH
+    721/     3EA :  3F                          CCF     
+    722/     3EB :  D0                          RET     NC		; 0-9
+    723/     3EC :  D6 07                       SUB     07H
+    724/     3EE :  FE 10                       CP      10H
+    725/     3F0 :  3F                          CCF     
+    726/     3F1 :  D8                          RET     C
+    727/     3F2 :  FE 0A                       CP      0AH
+    728/     3F4 :  C9                          RET     
+    729/     3F5 :                      
+    730/     3F5 :  00                          NOP     
+    731/     3F6 :  00                          NOP     
+    732/     3F7 :  00                          NOP     
+    733/     3F8 :  00                          NOP     
+    734/     3F9 :                      
+    735/     3F9 :  18 EA               HEX:    JR      HEXJ
+    736/     3FB :                      
+    737/     3FB :                      ;	PRESS PLAY MESSAGE
+    738/     3FB :                      
+    739/     3FB :  7F 20               MSGN1:	DW	207FH
+    740/     3FD :  50 4C 41 59 0D      MSGN2:	DB	"PLAY\r"
+    741/     402 :  7F 20               MSGN3:	DW	207FH
+    742/     404 :  52 45 43 4F 52 44   	DB	"RECORD.\r"	; PRESS RECORD
+                    2E 0D 
+    743/     40C :                      
+    744/     40C :  00                          NOP     
+    745/     40D :  00                          NOP     
+    746/     40E :  00                          NOP     
+    747/     40F :  00                          NOP     
+    748/     410 :                      
+    749/     410 :                      ;	4 ASCII TO (HL)
+    750/     410 :                      ;	IN  DE=DATA LOW ADDRESS
+    751/     410 :                      ;	EXIT CF=0 : OK
+    752/     410 :                      ;	       =1 : OUT
+    753/     410 :                      
+    754/     410 :  D5                  HLHEX:  PUSH    DE
+    755/     411 :  CD 1F 04                    CALL    L2HEX
+    756/     414 :  38 07                       JR      C,L041D
+    757/     416 :  67                          LD      H,A
+    758/     417 :  CD 1F 04                    CALL    L2HEX
+    759/     41A :  38 01                       JR      C,L041D
+    760/     41C :  6F                          LD      L,A
+    761/     41D :  D1                  L041D:  POP     DE
+    762/     41E :  C9                          RET     
+    763/     41F :                      
+    764/     41F :                      ;	2 ASCII TO (ACC)
+    765/     41F :                      ;	IN  DE=DATA LOW ADRRESS
+    766/     41F :                      ;	EXIT CF=0 : OK
+    767/     41F :                      ;	       =1 : OUT
+    768/     41F :                      
+    769/     41F :  C5                  L2HEX:  PUSH    BC
+    770/     420 :  1A                          LD      A,(DE)
+    771/     421 :  13                          INC     DE
+    772/     422 :  CD F9 03                    CALL    HEX
+    773/     425 :  38 0D                       JR      C,L0434
+    774/     427 :  0F                          RRCA    
+    775/     428 :  0F                          RRCA    
+    776/     429 :  0F                          RRCA    
+    777/     42A :  0F                          RRCA    
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 14 - 9.6.1998 9:06:29
+
+
+    778/     42B :  4F                          LD      C,A
+    779/     42C :  1A                          LD      A,(DE)
+    780/     42D :  13                          INC     DE
+    781/     42E :  CD F9 03                    CALL    HEX
+    782/     431 :  38 01                       JR      C,L0434
+    783/     433 :  B1                          OR      C
+    784/     434 :  C1                  L0434:  POP     BC
+    785/     435 :  C9                          RET     
+    786/     436 :                      
+    787/     436 :                      ;	WRITE INFORMATION
+    788/     436 :                      
+    789/     436 :  F3                  QWRI:   DI      
+    790/     437 :  D5                          PUSH    DE
+    791/     438 :  C5                          PUSH    BC
+    792/     439 :  E5                          PUSH    HL
+    793/     43A :  16 D7                       LD      D,0D7H		; "W"
+    794/     43C :  1E CC                       LD      E,0CCH		; "L"
+    795/     43E :  21 F0 10                    LD      HL,IBUFE	; 10F0H
+    796/     441 :  01 80 00                    LD      BC,80H		; WRITE BYTE SIZE
+    797/     444 :  CD 1A 07            WRI1:   CALL    CKSUM		; CHECK SUM
+    798/     447 :  CD 9F 06                    CALL    MOTOR		; MOTOR ON
+    799/     44A :  38 18                       JR      C,WRI3
+    800/     44C :  7B                          LD      A,E
+    801/     44D :  FE CC                       CP      0CCH		; "L"
+    802/     44F :  20 0D                       JR      NZ,WRI2
+    803/     451 :  CD 09 00                    CALL    NL
+    804/     454 :  D5                          PUSH    DE
+    805/     455 :  11 67 04                    LD      DE,MSGN7	; WRITING
+    806/     458 :  DF                          RST     18H		; CALL MSGX
+    807/     459 :  11 F1 10                    LD      DE,NAME		; FILE NAME
+    808/     45C :  DF                          RST     18H		; CALL MSGX
+    809/     45D :  D1                          POP     DE
+    810/     45E :  CD 7A 07            WRI2:   CALL    GAP
+    811/     461 :  CD 8A 04                    CALL    WTAPE
+    812/     464 :  C3 54 05            WRI3:   JP      RET2
+    813/     467 :                      
+    814/     467 :  57 52 49 54 49 4E   MSGN7:	DB	"WRITING \r"
+                    47 20 0D 
+    815/     470 :                      
+    816/     470 :                      ;	40 CHA. IN 1 LINE CODE (DATA)
+    817/     470 :                      
+    818/     470 :  01                  LLPT:	DB	01H		; TEXT MODE
+    819/     471 :  09                  	DB	09H
+    820/     472 :  09                  	DB	09H
+    821/     473 :  0B                  	DB	0BH
+    822/     474 :  0D                  	DB	0DH
+    823/     475 :                      
+    824/     475 :                      ;	WRITE DATA
+    825/     475 :                      ;	EXIT CF=0 : OK
+    826/     475 :                      ;	       =1 : BREAK
+    827/     475 :                      
+    828/     475 :  F3                  QWRD:   DI      
+    829/     476 :  D5                          PUSH    DE
+    830/     477 :  C5                          PUSH    BC
+    831/     478 :  E5                          PUSH    HL
+    832/     479 :  16 D7                       LD      D,0D7H		; "W"
+    833/     47B :  1E 53                       LD      E,53H		; "S"
+    834/     47D :  ED 4B 02 11         L047D:  LD      BC,(SIZE)	; WRITE DATA BYTE SIZE
+    835/     481 :  2A 04 11                    LD      HL,(DTADR)	; WRITE DATA ADDRESS
+    836/     484 :  78                          LD      A,B
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 15 - 9.6.1998 9:06:29
+
+
+    837/     485 :  B1                          OR      C
+    838/     486 :  28 4A                       JR      Z,RET1
+    839/     488 :  18 BA                       JR      WRI1
+    840/     48A :                      
+    841/     48A :                      ;	TAPE WRITE
+    842/     48A :                      ;	BC=BYTE SIZE
+    843/     48A :                      ;	HL=DATA LOW ADDRESS
+    844/     48A :                      ;	EXIT CF=0 : OK
+    845/     48A :                      ;	       =1 : BREAK
+    846/     48A :                      
+    847/     48A :  D5                  WTAPE:  PUSH    DE
+    848/     48B :  C5                          PUSH    BC
+    849/     48C :  E5                          PUSH    HL
+    850/     48D :  16 02                       LD      D,02H
+    851/     48F :  3E F8                       LD      A,0F8H		; 88H WOULD BE BETTER!!
+    852/     491 :  32 00 E0                    LD      (KEYPA),A	; E000H
+    853/     494 :  7E                  WTAP1:  LD      A,(HL)
+    854/     495 :  CD 67 07                    CALL    WBYTE		; 1 BYTE WRITE
+    855/     498 :  3A 01 E0                    LD      A,(KEYPB)	; E001H
+    856/     49B :  E6 81                       AND     81H		; SHIFT & BREAK
+    857/     49D :  C2 A5 04                    JP      NZ,WTAP2
+    858/     4A0 :  3E 02                       LD      A,02H		; BREAK IN CODE
+    859/     4A2 :  37                          SCF     
+    860/     4A3 :  18 2D                       JR      WTAP3
+    861/     4A5 :                      
+    862/     4A5 :  23                  WTAP2:  INC     HL
+    863/     4A6 :  0B                          DEC     BC
+    864/     4A7 :  78                          LD      A,B
+    865/     4A8 :  B1                          OR      C
+    866/     4A9 :  C2 94 04                    JP      NZ,WTAP1
+    867/     4AC :  2A 97 11                    LD      HL,(SUMDT)	; SUM DATA SET
+    868/     4AF :  7C                          LD      A,H
+    869/     4B0 :  CD 67 07                    CALL    WBYTE
+    870/     4B3 :  7D                          LD      A,L
+    871/     4B4 :  CD 67 07                    CALL    WBYTE
+    872/     4B7 :  CD 1A 0A                    CALL    LONG
+    873/     4BA :  15                          DEC     D
+    874/     4BB :  C2 C2 04                    JP      NZ,L04C2
+    875/     4BE :  B7                          OR      A
+    876/     4BF :  C3 D2 04                    JP      WTAP3
+    877/     4C2 :                      
+    878/     4C2 :  06 00               L04C2:  LD      B,0
+    879/     4C4 :  CD 01 0A            L04C4:  CALL    SHORT
+    880/     4C7 :  05                          DEC     B
+    881/     4C8 :  C2 C4 04                    JP      NZ,L04C4
+    882/     4CB :  E1                          POP     HL
+    883/     4CC :  C1                          POP     BC
+    884/     4CD :  C5                          PUSH    BC
+    885/     4CE :  E5                          PUSH    HL
+    886/     4CF :  C3 94 04                    JP      WTAP1
+    887/     4D2 :                      
+    888/     4D2 :                      WTAP3:
+    889/     4D2 :  E1                  RET1:   POP     HL
+    890/     4D3 :  C1                          POP     BC
+    891/     4D4 :  D1                          POP     DE
+    892/     4D5 :  C9                          RET     
+    893/     4D6 :                      
+    894/     4D6 :  2F                  	DB	2FH
+    895/     4D7 :  4E                  	DB	4EH
+    896/     4D8 :                      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 16 - 9.6.1998 9:06:29
+
+
+    897/     4D8 :                      ;	READ INFORMATION (FROM $CMT)
+    898/     4D8 :                      ;	EXIT ACC=0: OK CF=0
+    899/     4D8 :                      ;	        =1: ER CF=1
+    900/     4D8 :                      ;	        =2: BREAK CF=1
+    901/     4D8 :                      
+    902/     4D8 :  F3                  QRDI:   DI      
+    903/     4D9 :  D5                          PUSH    DE
+    904/     4DA :  C5                          PUSH    BC
+    905/     4DB :  E5                          PUSH    HL
+    906/     4DC :  16 D2                       LD      D,0D2H		; "R"
+    907/     4DE :  1E CC                       LD      E,0CCH		; "L"
+    908/     4E0 :  01 80 00                    LD      BC,80H
+    909/     4E3 :  21 F0 10                    LD      HL,IBUFE
+    910/     4E6 :  CD 9F 06            RD1:    CALL    MOTOR
+    911/     4E9 :  DA 72 05                    JP      C,RTP6
+    912/     4EC :  CD 5B 06                    CALL    TMARK
+    913/     4EF :  DA 72 05                    JP      C,RTP6
+    914/     4F2 :  CD 0E 05                    CALL    RTAPE
+    915/     4F5 :  C3 54 05                    JP      RTP4
+    916/     4F8 :                      
+    917/     4F8 :                      ;	READ DATA (FROM $CMT)
+    918/     4F8 :                      ;	EXIT SAME UP
+    919/     4F8 :                      
+    920/     4F8 :  F3                  QRDD:   DI      
+    921/     4F9 :  D5                          PUSH    DE
+    922/     4FA :  C5                          PUSH    BC
+    923/     4FB :  E5                          PUSH    HL
+    924/     4FC :  16 D2                       LD      D,0D2H		; "R"
+    925/     4FE :  1E 53                       LD      E,53H		; "S"
+    926/     500 :  ED 4B 02 11                 LD      BC,(SIZE)
+    927/     504 :  2A 04 11                    LD      HL,(DTADR)
+    928/     507 :  78                          LD      A,B
+    929/     508 :  B1                          OR      C
+    930/     509 :  CA 54 05                    JP      Z,RTP4
+    931/     50C :  18 D8                       JR      RD1
+    932/     50E :                      
+    933/     50E :                      ;	READ TAPE
+    934/     50E :                      ;	IN  BC=SIZE
+    935/     50E :                      ;	    DE=LOAD ADDRESS
+    936/     50E :                      ;	EXIT ACC=0 : OK CF=0
+    937/     50E :                      ;	        =1 : ER   =1
+    938/     50E :                      ;	        =2 : BREAK=1
+    939/     50E :                       
+    940/     50E :  D5                  RTAPE:  PUSH    DE
+    941/     50F :  C5                          PUSH    BC
+    942/     510 :  E5                          PUSH    HL
+    943/     511 :  26 02                       LD      H,02H		; TWICE WRITE
+    944/     513 :  01 01 E0            RTP1:   LD      BC,KEYPB
+    945/     516 :  11 02 E0                    LD      DE,CSTR
+    946/     519 :  CD 01 06            RTP2:   CALL    EDGE		; 1-->0 EDGE DETECT
+    947/     51C :  38 54                       JR      C,RTP6
+    948/     51E :  CD 4A 0A                    CALL    DLY3		; CALL DLY2*3
+    949/     521 :  1A                          LD      A,(DE)		; DATA (1 BIT) READ
+    950/     522 :  E6 20                       AND     20H
+    951/     524 :  CA 19 05                    JP      Z,RTP2
+    952/     527 :  54                          LD      D,H
+    953/     528 :  21 00 00                    LD      HL,0
+    954/     52B :  22 97 11                    LD      (SUMDT),HL
+    955/     52E :  E1                          POP     HL
+    956/     52F :  C1                          POP     BC
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 17 - 9.6.1998 9:06:29
+
+
+    957/     530 :  C5                          PUSH    BC
+    958/     531 :  E5                          PUSH    HL
+    959/     532 :  CD 24 06            RTP3:   CALL    RBYTE		; 1 BYTE READ
+    960/     535 :  38 3B                       JR      C,RTP6
+    961/     537 :  77                          LD      (HL),A
+    962/     538 :  23                          INC     HL
+    963/     539 :  0B                          DEC     BC
+    964/     53A :  78                          LD      A,B
+    965/     53B :  B1                          OR      C
+    966/     53C :  20 F4                       JR      NZ,RTP3
+    967/     53E :  2A 97 11                    LD      HL,(SUMDT)	; CHECK SUM
+    968/     541 :  CD 24 06                    CALL    RBYTE		; CHECK SUM DATA
+    969/     544 :  38 2C                       JR      C,RTP6
+    970/     546 :  5F                          LD      E,A
+    971/     547 :  CD 24 06                    CALL    RBYTE		; CHECK SUM DATA
+    972/     54A :  38 26                       JR      C,RTP6
+    973/     54C :  BD                          CP      L
+    974/     54D :  20 16                       JR      NZ,RTP5
+    975/     54F :  7B                          LD      A,E
+    976/     550 :  BC                          CP      H
+    977/     551 :  20 12                       JR      NZ,RTP5
+    978/     553 :  AF                  RTP8:   XOR     A
+    979/     554 :                      RTP4:
+    980/     554 :  E1                  RET2:   POP     HL
+    981/     555 :  C1                          POP     BC
+    982/     556 :  D1                          POP     DE
+    983/     557 :  CD 00 07                    CALL    MSTOP
+    984/     55A :  F5                          PUSH    AF
+    985/     55B :  3A 9C 11                    LD      A,(TIMFG)	; INT. CHECK
+    986/     55E :  FE F0                       CP      0F0H
+    987/     560 :  20 01                       JR      NZ,L0563
+    988/     562 :  FB                          EI      
+    989/     563 :  F1                  L0563:  POP     AF
+    990/     564 :  C9                          RET     
+    991/     565 :                      
+    992/     565 :  15                  RTP5:   DEC     D
+    993/     566 :  28 06                       JR      Z,RTP7
+    994/     568 :  62                          LD      H,D
+    995/     569 :  CD E2 0F                    CALL    GAPCK
+    996/     56C :  18 A5                       JR      RTP1
+    997/     56E :                      
+    998/     56E :  3E 01               RTP7:   LD      A,01H
+    999/     570 :  18 02                       JR      RTP9
+   1000/     572 :                      
+   1001/     572 :  3E 02               RTP6:   LD      A,02H
+   1002/     574 :  37                  RTP9:   SCF     
+   1003/     575 :  18 DD                       JR      RTP4
+   1004/     577 :                      
+   1005/     577 :                      ;	BELL
+   1006/     577 :                      
+   1007/     577 :  D5                  QBEL:   PUSH    DE
+   1008/     578 :  11 52 03                    LD      DE,QBELD
+   1009/     57B :  F7                          RST     30H		; CALL MELODY
+   1010/     57C :  D1                          POP     DE
+   1011/     57D :  C9                          RET     
+   1012/     57E :                      
+   1013/     57E :                      ;	FLASHING AND KEYIN
+   1014/     57E :                      ;	EXIT: ACC INPUT KEY DATA (DSP.CODE)
+   1015/     57E :                      ;	H=F0H THEN NO KEYIN (Z FLAG)
+   1016/     57E :                      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 18 - 9.6.1998 9:06:29
+
+
+   1017/     57E :  CD FF 09            FLKEY:  CALL    QFLAS
+   1018/     581 :  CD CA 08                    CALL    QKEY
+   1019/     584 :  FE F0                       CP      0F0H
+   1020/     586 :  C9                          RET     
+   1021/     587 :                      
+   1022/     587 :  00                          NOP     
+   1023/     588 :                      
+   1024/     588 :                      ;	VERIFY (FROM $CMT)
+   1025/     588 :                      ;	EXIT ACC=0 : OK CF=0
+   1026/     588 :                      ;	        =1 : ER CF=1
+   1027/     588 :                      ;	        =2 : BREAK CF=1
+   1028/     588 :                      
+   1029/     588 :  F3                  QVRFY:  DI      
+   1030/     589 :  D5                          PUSH    DE
+   1031/     58A :  C5                          PUSH    BC
+   1032/     58B :  E5                          PUSH    HL
+   1033/     58C :  ED 4B 02 11                 LD      BC,(SIZE)
+   1034/     590 :  2A 04 11                    LD      HL,(DTADR)
+   1035/     593 :  16 D2                       LD      D,0D2H		; "R"
+   1036/     595 :  1E 53                       LD      E,53H		; "S"
+   1037/     597 :  78                          LD      A,B
+   1038/     598 :  B1                          OR      C
+   1039/     599 :  28 B9                       JR      Z,RTP4		; END
+   1040/     59B :  CD 1A 07                    CALL    CKSUM
+   1041/     59E :  CD 9F 06                    CALL    MOTOR
+   1042/     5A1 :  38 CF                       JR      C,RTP6		; BRK
+   1043/     5A3 :  CD 5B 06                    CALL    TMARK		; TAPE MARK DETECT
+   1044/     5A6 :  38 CA                       JR      C,RTP6		; BRK
+   1045/     5A8 :  CD AD 05                    CALL    TVRFY
+   1046/     5AB :  18 A7                       JR      RTP4
+   1047/     5AD :                      
+   1048/     5AD :                      ;	DATA VERIFY
+   1049/     5AD :                      ;	BC=SIZE
+   1050/     5AD :                      ;	HL=DATA LOW ADDRESS
+   1051/     5AD :                      ;	CSMDT=CHECK SUM
+   1052/     5AD :                      ;	EXIT ACC=0 : OK  CF=0
+   1053/     5AD :                      ;	        =1 : ER    =1
+   1054/     5AD :                      ;	        =2 : BREAK =1
+   1055/     5AD :                      
+   1056/     5AD :  D5                  TVRFY:  PUSH    DE
+   1057/     5AE :  C5                          PUSH    BC
+   1058/     5AF :  E5                          PUSH    HL
+   1059/     5B0 :  26 02                       LD      H,02H		; COMPARE TWICE
+   1060/     5B2 :  01 01 E0            TVF1:   LD      BC,KEYPB
+   1061/     5B5 :  11 02 E0                    LD      DE,CSTR
+   1062/     5B8 :  CD 01 06            TVF2:   CALL    EDGE
+   1063/     5BB :  DA 72 05                    JP      C,RTP6		; BRK
+   1064/     5BE :  CD 4A 0A                    CALL    DLY3		; CALL DLY2*3
+   1065/     5C1 :  1A                          LD      A,(DE)
+   1066/     5C2 :  E6 20                       AND     20H
+   1067/     5C4 :  CA B8 05                    JP      Z,TVF2
+   1068/     5C7 :  54                          LD      D,H
+   1069/     5C8 :  E1                          POP     HL
+   1070/     5C9 :  C1                          POP     BC
+   1071/     5CA :  C5                          PUSH    BC
+   1072/     5CB :  E5                          PUSH    HL
+   1073/     5CC :                      ;	COMPARE TAPE DATA AND STORAGE
+   1074/     5CC :  CD 24 06            TVF3:   CALL    RBYTE
+   1075/     5CF :  38 A1                       JR      C,RTP6		; BRK
+   1076/     5D1 :  BE                          CP      (HL)
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 19 - 9.6.1998 9:06:29
+
+
+   1077/     5D2 :  20 9A                       JR      NZ,RTP7		; ERROR, NOT EQUAL
+   1078/     5D4 :  23                          INC     HL		; STORAGE ADDRESS + 1
+   1079/     5D5 :  0B                          DEC     BC		; SIZE - 1
+   1080/     5D6 :  78                          LD      A,B
+   1081/     5D7 :  B1                          OR      C
+   1082/     5D8 :  20 F2                       JR      NZ,TVF3
+   1083/     5DA :                      ;	COMPARE CHECK SUM (1199H/CSMDT) AND TAPE
+   1084/     5DA :  2A 99 11                    LD      HL,(CSMDT)
+   1085/     5DD :  CD 24 06                    CALL    RBYTE
+   1086/     5E0 :  BC                          CP      H
+   1087/     5E1 :  20 8B                       JR      NZ,RTP7		; ERROR, NOT EQUAL
+   1088/     5E3 :  CD 24 06                    CALL    RBYTE
+   1089/     5E6 :  BD                          CP      L
+   1090/     5E7 :  20 85                       JR      NZ,RTP7		; ERROR, NOT EQUAL
+   1091/     5E9 :  15                          DEC     D		; NUMBER OF COMPARES (2) - 1
+   1092/     5EA :  CA 53 05                    JP      Z,RTP8		; OK, 2 COMPARES
+   1093/     5ED :  62                          LD      H,D		; (-->05C7H), SAVE NUMBER OF COMPARES
+   1094/     5EE :  18 C2                       JR      TVF1		; NEXT COMPARE
+   1095/     5F0 :                      
+   1096/     5F0 :                      ;	FLASHING DATA LOAD
+   1097/     5F0 :                      
+   1098/     5F0 :  F5                  QLOAD:  PUSH    AF
+   1099/     5F1 :  3A 8E 11                    LD      A,(FLASH)
+   1100/     5F4 :  CD B1 0F                    CALL    QPONT
+   1101/     5F7 :  77                          LD      (HL),A
+   1102/     5F8 :  F1                          POP     AF
+   1103/     5F9 :  C9                          RET     
+   1104/     5FA :                      
+   1105/     5FA :                      ;	NEW LINE AND PRINT HL REG (ASCII)
+   1106/     5FA :                      
+   1107/     5FA :  CD 09 00            NLPHL:  CALL    NL
+   1108/     5FD :  CD BA 03                    CALL    PRTHL
+   1109/     600 :  C9                          RET     
+   1110/     601 :                      
+   1111/     601 :                      ;	EDGE (TAPE DATA EDGE DETECT)
+   1112/     601 :                      ;	BC=KEYPB (E001H)
+   1113/     601 :                      ;	DE=CSTR  (E002H)
+   1114/     601 :                      ;	EXIT CF=0 OK   CF=1 BREAK
+   1115/     601 :                      
+   1116/     601 :  3E F8               EDGE:   LD      A,0F8H		; BREAK KEY IN (88H WOULD BE BETTER!!) 
+   1117/     603 :  32 00 E0                    LD      (KEYPA),A
+   1118/     606 :  00                          NOP     
+   1119/     607 :  0A                  EDG1:   LD      A,(BC)
+   1120/     608 :  E6 81                       AND     81H		; SHIFT & BREAK
+   1121/     60A :  20 02                       JR      NZ,L060E
+   1122/     60C :  37                          SCF     
+   1123/     60D :  C9                          RET     
+   1124/     60E :                      
+   1125/     60E :  1A                  L060E:  LD      A,(DE)
+   1126/     60F :  E6 20                       AND     20H
+   1127/     611 :  20 F4                       JR      NZ,EDG1		; CSTR D5 = 0
+   1128/     613 :  0A                  EDG2:   LD      A,(BC)		; 8
+   1129/     614 :  E6 81                       AND     81H		; 9
+   1130/     616 :  20 02                       JR      NZ,L061A	; 10/14
+   1131/     618 :  37                          SCF     
+   1132/     619 :  C9                          RET     
+   1133/     61A :                      
+   1134/     61A :  1A                  L061A:  LD      A,(DE)		; 8
+   1135/     61B :  E6 20                       AND     20H		; 9
+   1136/     61D :  28 F4                       JR      Z,EDG2		; CSTR D5 = 1  10/14
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 20 - 9.6.1998 9:06:29
+
+
+   1137/     61F :  C9                          RET     		; 11
+   1138/     620 :                      
+   1139/     620 :  00                          NOP     
+   1140/     621 :  00                          NOP     
+   1141/     622 :  00                          NOP     
+   1142/     623 :  00                          NOP     
+   1143/     624 :                      ;	1 BYTE READ
+   1144/     624 :                      ;	EXIT SUMDT=STORE
+   1145/     624 :                      ;	CF=1 : BREAK
+   1146/     624 :                      ;	CF=0 : DATA=ACC
+   1147/     624 :                      
+   1148/     624 :  C5                  RBYTE:  PUSH    BC
+   1149/     625 :  D5                          PUSH    DE
+   1150/     626 :  E5                          PUSH    HL
+   1151/     627 :  21 00 08                    LD      HL,0800H	; 8 BITS
+   1152/     62A :  01 01 E0                    LD      BC,KEYPB	; KEY DATA E001H
+   1153/     62D :  11 02 E0                    LD      DE,CSTR		; $TAPE DATA E002H
+   1154/     630 :  CD 01 06            RBY1:   CALL    EDGE		; 41 OR 101
+   1155/     633 :  DA 54 06                    JP      C,RBY3		; 13 (SHIFT & BREAK)
+   1156/     636 :  CD 4A 0A                    CALL    DLY3		; 20+18*63+33
+   1157/     639 :  1A                          LD      A,(DE)		; DATA READ :8
+   1158/     63A :  E6 20                       AND     20H
+   1159/     63C :  CA 49 06                    JP      Z,RBY2		; 0
+   1160/     63F :  E5                          PUSH    HL
+   1161/     640 :  2A 97 11                    LD      HL,(SUMDT)
+   1162/     643 :  23                          INC     HL		; CHECK SUM; COUNT HIGH BITS ON TAPE
+   1163/     644 :  22 97 11                    LD      (SUMDT),HL
+   1164/     647 :  E1                          POP     HL
+   1165/     648 :  37                          SCF     
+   1166/     649 :  7D                  RBY2:   LD      A,L		; BUILD CHAR
+   1167/     64A :  17                          RLA     
+   1168/     64B :  6F                          LD      L,A
+   1169/     64C :  25                          DEC     H		; BITCOUNT-1
+   1170/     64D :  C2 30 06                    JP      NZ,RBY1
+   1171/     650 :  CD 01 06                    CALL    EDGE
+   1172/     653 :  7D                          LD      A,L		; CHAR READ
+   1173/     654 :  E1                  RBY3:   POP     HL
+   1174/     655 :  D1                          POP     DE
+   1175/     656 :  C1                          POP     BC
+   1176/     657 :  C9                          RET     
+   1177/     658 :                      
+   1178/     658 :  00                          NOP     
+   1179/     659 :  00                          NOP     
+   1180/     65A :  00                          NOP     
+   1181/     65B :                      
+   1182/     65B :                      ;	TAPE MARK DETECT
+   1183/     65B :                      ;	E=@L@ : INFORMATION
+   1184/     65B :                      ;	 =@S@ : DATA
+   1185/     65B :                      ;	EXIT CF=0 OK
+   1186/     65B :                      ;	       =1 BREAK
+   1187/     65B :                      
+   1188/     65B :  CD E2 0F            TMARK:  CALL    GAPCK
+   1189/     65E :  C5                          PUSH    BC
+   1190/     65F :  D5                          PUSH    DE
+   1191/     660 :  E5                          PUSH    HL
+   1192/     661 :  21 28 28                    LD      HL,2828H
+   1193/     664 :  7B                          LD      A,E
+   1194/     665 :  FE CC                       CP      0CCH		; "L"
+   1195/     667 :  28 03                       JR      Z,L066C
+   1196/     669 :  21 14 14                    LD      HL,1414H
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 21 - 9.6.1998 9:06:29
+
+
+   1197/     66C :  22 95 11            L066C:  LD      (TMCNT),HL
+   1198/     66F :  01 01 E0                    LD      BC,KEYPB
+   1199/     672 :  11 02 E0                    LD      DE,CSTR
+   1200/     675 :  2A 95 11            TM1:    LD      HL,(TMCNT)
+   1201/     678 :  CD 01 06            TM2:    CALL    EDGE
+   1202/     67B :  38 1E                       JR      C,TM4
+   1203/     67D :  CD 4A 0A                    CALL    DLY3		; CALL DLY2*3
+   1204/     680 :  1A                          LD      A,(DE)
+   1205/     681 :  E6 20                       AND     20H
+   1206/     683 :  28 F0                       JR      Z,TM1
+   1207/     685 :  25                          DEC     H
+   1208/     686 :  20 F0                       JR      NZ,TM2
+   1209/     688 :  CD 01 06            TM3:    CALL    EDGE
+   1210/     68B :  38 0E                       JR      C,TM4
+   1211/     68D :  CD 4A 0A                    CALL    DLY3		; CALL DLY2*3
+   1212/     690 :  1A                          LD      A,(DE)
+   1213/     691 :  E6 20                       AND     20H
+   1214/     693 :  20 E0                       JR      NZ,TM1
+   1215/     695 :  2D                          DEC     L
+   1216/     696 :  20 F0                       JR      NZ,TM3
+   1217/     698 :  CD 01 06                    CALL    EDGE
+   1218/     69B :                      TM4:
+   1219/     69B :  E1                  RET3:   POP     HL
+   1220/     69C :  D1                          POP     DE
+   1221/     69D :  C1                          POP     BC
+   1222/     69E :  C9                          RET     
+   1223/     69F :                      
+   1224/     69F :                      ;	MOTOR ON
+   1225/     69F :                      ;	IN  D=@W@ :WRITE
+   1226/     69F :                      ;	     =@R@ :READ
+   1227/     69F :                      ;	EXIT CF=0 OK
+   1228/     69F :                      ;	       =1 BREAK
+   1229/     69F :                      
+   1230/     69F :  C5                  MOTOR:  PUSH    BC
+   1231/     6A0 :  D5                          PUSH    DE
+   1232/     6A1 :  E5                          PUSH    HL
+   1233/     6A2 :  06 0A                       LD      B,0AH
+   1234/     6A4 :  3A 02 E0            MOT1:   LD      A,(CSTR)
+   1235/     6A7 :  E6 10                       AND     10H
+   1236/     6A9 :  28 0E                       JR      Z,MOT4
+   1237/     6AB :  06 FF               MOT2:   LD      B,0FFH		; 2 SEC DELAY
+   1238/     6AD :  CD 96 09            L06AD:  CALL    DLY12		; 7 MSEC DELAY
+   1239/     6B0 :  18 02                       JR      L06B4		; MOTOR ENTRY ADJUST
+   1240/     6B2 :                      
+   1241/     6B2 :  18 EB                       JR      MOTOR		; ORG 06B2H
+   1242/     6B4 :                      
+   1243/     6B4 :  10 F7               L06B4:  DJNZ    L06AD
+   1244/     6B6 :  AF                          XOR     A
+   1245/     6B7 :  18 E2               MOT7:   JR      RET3
+   1246/     6B9 :                      
+   1247/     6B9 :  3E 06               MOT4:   LD      A,06H
+   1248/     6BB :  21 03 E0                    LD      HL,CSTPT
+   1249/     6BE :  77                          LD      (HL),A
+   1250/     6BF :  3C                          INC     A
+   1251/     6C0 :  77                          LD      (HL),A
+   1252/     6C1 :  10 E1                       DJNZ    MOT1
+   1253/     6C3 :  CD 09 00                    CALL    NL
+   1254/     6C6 :  7A                          LD      A,D
+   1255/     6C7 :  FE D7                       CP      0D7H		; "W"
+   1256/     6C9 :  28 05                       JR      Z,MOT8
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 22 - 9.6.1998 9:06:29
+
+
+   1257/     6CB :  11 FB 03                    LD      DE,MSGN1	; PLAY MARK
+   1258/     6CE :  18 07                       JR      MOT9
+   1259/     6D0 :                      
+   1260/     6D0 :  11 02 04            MOT8:   LD      DE,MSGN3	; "RECORD."
+   1261/     6D3 :  DF                          RST     18H		; CALL MSGX
+   1262/     6D4 :  11 FD 03                    LD      DE,MSGN2	; "PLAY"
+   1263/     6D7 :  DF                  MOT9:   RST     18H		; CALL MSGX
+   1264/     6D8 :  3A 02 E0            MOT5:   LD      A,(CSTR)
+   1265/     6DB :  E6 10                       AND     10H
+   1266/     6DD :  20 CC                       JR      NZ,MOT2
+   1267/     6DF :  CD 32 0A                    CALL    QBRK
+   1268/     6E2 :  20 F4                       JR      NZ,MOT5
+   1269/     6E4 :  37                          SCF     
+   1270/     6E5 :  18 D0                       JR      MOT7   
+   1271/     6E7 :                      
+   1272/     6E7 :                      ;	INITIAL MESSAGE
+   1273/     6E7 :                      
+   1274/     6E7 :  2A 2A 20 20 4D 4F   MSGQ3:	DB	"**  MONITOR 1Z-013A  **\r"
+                    4E 49 54 4F 52 20 
+                    31 5A 2D 30 31 33 
+                    41 20 20 2A 2A 0D 
+   1275/     6FF :  00                  	NOP
+   1276/     700 :                      
+   1277/     700 :                      ;	MOTOR STOP
+   1278/     700 :                      
+   1279/     700 :  F5                  MSTOP:  PUSH    AF
+   1280/     701 :  C5                          PUSH    BC
+   1281/     702 :  D5                          PUSH    DE
+   1282/     703 :  06 0A                       LD      B,0AH
+   1283/     705 :  3A 02 E0            MST1:   LD      A,(CSTR)
+   1284/     708 :  E6 10                       AND     10H
+   1285/     70A :  28 0B                       JR      Z,MST3
+   1286/     70C :  3E 06                       LD      A,06H
+   1287/     70E :  32 03 E0                    LD      (CSTPT),A
+   1288/     711 :  3C                          INC     A
+   1289/     712 :  32 03 E0                    LD      (CSTPT),A
+   1290/     715 :  10 EE                       DJNZ    MST1
+   1291/     717 :  C3 E6 0E            MST3:   JP      QRSTR1
+   1292/     71A :                      
+   1293/     71A :                      ;	CHECK SUM
+   1294/     71A :                      ;	IN   BC=SIZE
+   1295/     71A :                      ;	     HL=DATA ADDRESS
+   1296/     71A :                      ;	EXIT SUMDT=STORE
+   1297/     71A :                      ;	     CSMDT=STORE
+   1298/     71A :                      
+   1299/     71A :  C5                  CKSUM:  PUSH    BC
+   1300/     71B :  D5                          PUSH    DE
+   1301/     71C :  E5                  L071C:  PUSH    HL
+   1302/     71D :  11 00 00                    LD      DE,0
+   1303/     720 :  78                  CKS1:   LD      A,B
+   1304/     721 :  B1                          OR      C
+   1305/     722 :  20 0B                       JR      NZ,CKS2
+   1306/     724 :  EB                          EX      DE,HL
+   1307/     725 :  22 97 11            L0725:  LD      (SUMDT),HL	; NUMBER OF HIGHBITS IN DATA
+   1308/     728 :  22 99 11                    LD      (CSMDT),HL
+   1309/     72B :  E1                          POP     HL
+   1310/     72C :  D1                          POP     DE
+   1311/     72D :  C1                          POP     BC
+   1312/     72E :  C9                          RET     
+   1313/     72F :                      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 23 - 9.6.1998 9:06:29
+
+
+   1314/     72F :  7E                  CKS2:   LD      A,(HL)
+   1315/     730 :  C5                          PUSH    BC
+   1316/     731 :  06 08                       LD      B,8
+   1317/     733 :  07                  CKS3:   RLCA    
+   1318/     734 :  30 01                       JR      NC,L0737
+   1319/     736 :  13                          INC     DE
+   1320/     737 :  10 FA               L0737:  DJNZ    CKS3
+   1321/     739 :  C1                  L0739:  POP     BC
+   1322/     73A :  23                          INC     HL
+   1323/     73B :  0B                          DEC     BC
+   1324/     73C :  18 E2                       JR      CKS1
+   1325/     73E :                      
+   1326/     73E :                      ;	MODE SET OF KEYPORT
+   1327/     73E :                      
+   1328/     73E :  21 03 E0            QMODE:  LD      HL,KEYPF
+   1329/     741 :  36 8A                       LD      (HL),8AH	; 10001010 CTRL WORD MODE0
+   1330/     743 :  36 07                       LD      (HL),07H	; PC3=1 M-ON
+   1331/     745 :  36 05                       LD      (HL),05H	; PC2=1 INTMSK
+   1332/     747 :  C9                          RET     
+   1333/     748 :                      
+   1334/     748 :  00                          NOP     
+   1335/     749 :  00                          NOP     
+   1336/     74A :  00                          NOP     
+   1337/     74B :  00                          NOP     
+   1338/     74C :  00                          NOP     
+   1339/     74D :  00                          NOP     
+   1340/     74E :  00                          NOP     
+   1341/     74F :  00                          NOP     
+   1342/     750 :  00                          NOP     
+   1343/     751 :  00                          NOP     
+   1344/     752 :  00                          NOP     
+   1345/     753 :  00                          NOP     
+   1346/     754 :  00                          NOP     
+   1347/     755 :  00                          NOP     
+   1348/     756 :  00                          NOP     
+   1349/     757 :  00                          NOP     
+   1350/     758 :  00                          NOP     
+   1351/     759 :                      
+   1352/     759 :                      ;	107 MICRO SEC DELAY
+   1353/     759 :                      
+   1354/     759 :  3E 15               DLY1:   LD      A,15H		; 18*21+20
+   1355/     75B :  3D                  L075B:  DEC     A
+   1356/     75C :  C2 5B 07                    JP      NZ,L075B
+   1357/     75F :  C9                          RET     
+   1358/     760 :                      
+   1359/     760 :  3E 13               DLY2:   LD      A,13H		; 18*19+20
+   1360/     762 :  3D                  L0762:  DEC     A
+   1361/     763 :  C2 62 07                    JP      NZ,L0762
+   1362/     766 :  C9                          RET     
+   1363/     767 :                      
+   1364/     767 :                      ;	1 BYTE WRITE
+   1365/     767 :                      
+   1366/     767 :  C5                  WBYTE:  PUSH    BC
+   1367/     768 :  06 08                       LD      B,8
+   1368/     76A :  CD 1A 0A                    CALL    LONG
+   1369/     76D :  07                  WBY1:   RLCA    
+   1370/     76E :  DC 1A 0A                    CALL    C,LONG
+   1371/     771 :  D4 01 0A                    CALL    NC,SHORT
+   1372/     774 :  05                          DEC     B
+   1373/     775 :  C2 6D 07                    JP      NZ,WBY1
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 24 - 9.6.1998 9:06:29
+
+
+   1374/     778 :  C1                          POP     BC
+   1375/     779 :  C9                          RET     
+   1376/     77A :                      
+   1377/     77A :                      ;	GAP + TAPEMARK
+   1378/     77A :                      ;	E=@L@ LONG GAP
+   1379/     77A :                      ;	 =@s@ SHORT GAP
+   1380/     77A :                      
+   1381/     77A :  C5                  GAP:    PUSH    BC
+   1382/     77B :  D5                          PUSH    DE
+   1383/     77C :  7B                          LD      A,E
+   1384/     77D :  01 F0 55                    LD      BC,55F0H
+   1385/     780 :  11 28 28                    LD      DE,2828H
+   1386/     783 :  FE CC                       CP      0CCH		; "L"
+   1387/     785 :  CA 8E 07                    JP      Z,GAP1
+   1388/     788 :  01 F8 2A                    LD      BC,2AF8H
+   1389/     78B :  11 14 14                    LD      DE,1414H
+   1390/     78E :  CD 01 0A            GAP1:   CALL    SHORT
+   1391/     791 :  0B                          DEC     BC
+   1392/     792 :  78                          LD      A,B
+   1393/     793 :  B1                          OR      C
+   1394/     794 :  20 F8                       JR      NZ,GAP1
+   1395/     796 :  CD 1A 0A            GAP2:   CALL    LONG
+   1396/     799 :  15                          DEC     D
+   1397/     79A :  20 FA                       JR      NZ,GAP2
+   1398/     79C :  CD 01 0A            GAP3:   CALL    SHORT
+   1399/     79F :  1D                          DEC     E
+   1400/     7A0 :  20 FA                       JR      NZ,GAP3
+   1401/     7A2 :  CD 1A 0A                    CALL    LONG
+   1402/     7A5 :  D1                          POP     DE
+   1403/     7A6 :  C1                          POP     BC
+   1404/     7A7 :  C9                          RET     
+   1405/     7A8 :                      
+   1406/     7A8 :                      ;	MEMORY CORRECTION
+   1407/     7A8 :                      ;	COMMAND "M"
+   1408/     7A8 :                      
+   1409/     7A8 :  CD 3D 01            MCOR:   CALL    HEXIY		; CORRECTION ADDRESS
+   1410/     7AB :  CD FA 05            MCR1:   CALL    NLPHL		; CORRECTION ADDRESS PRINT
+   1411/     7AE :  CD B1 03                    CALL    SPHEX		; ACC-->ASCII DISP.
+   1412/     7B1 :  CD 20 09                    CALL    QPRTS		; SPACE PRINT
+   1413/     7B4 :  CD 2F 01                    CALL    BGETL		; GET DATA & CHECK DATA
+   1414/     7B7 :  CD 10 04                    CALL    HLHEX		; HL<--ASCII(DE)
+   1415/     7BA :  38 1B                       JR      C,MCR3
+   1416/     7BC :  CD A6 02                    CALL    P4DE		; (INC DE)*4
+   1417/     7BF :  13                          INC     DE
+   1418/     7C0 :  CD 1F 04                    CALL    L2HEX		; DATA CHECK
+   1419/     7C3 :  38 E6                       JR      C,MCR1
+   1420/     7C5 :  BE                          CP      (HL)
+   1421/     7C6 :  20 E3                       JR      NZ,MCR1
+   1422/     7C8 :  13                          INC     DE
+   1423/     7C9 :  1A                          LD      A,(DE)
+   1424/     7CA :  FE 0D                       CP      0DH		; NOT CORRECTION ?
+   1425/     7CC :  28 06                       JR      Z,MCR2
+   1426/     7CE :  CD 1F 04                    CALL    L2HEX		; ACC<--HL(ASCII)
+   1427/     7D1 :  38 D8                       JR      C,MCR1
+   1428/     7D3 :  77                          LD      (HL),A		; DATA CORRECT
+   1429/     7D4 :  23                  MCR2:   INC     HL
+   1430/     7D5 :  18 D4                       JR      MCR1
+   1431/     7D7 :                      
+   1432/     7D7 :  60                  MCR3:   LD      H,B		; MEMORY ADDRESS
+   1433/     7D8 :  69                          LD      L,C
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 25 - 9.6.1998 9:06:29
+
+
+   1434/     7D9 :  18 D0                       JR      MCR1
+   1435/     7DB :                      
+   1436/     7DB :  28 48 4C 29         	DB	"(HL)"
+   1437/     7DF :  F1                  	DB	0F1H
+   1438/     7E0 :  9E                  	DB	9EH
+   1439/     7E1 :  53 55 42 20 28      	DB	"SUB ("
+   1440/     7E6 :                      
+   1441/     7E6 :                      ;	GET 1 LINE STATEMENT *
+   1442/     7E6 :                      ;	DE=DATA STORE LOW ADDRESS
+   1443/     7E6 :                      ;	(END=CR)
+   1444/     7E6 :                      
+   1445/     7E6 :  F5                  QGETL:  PUSH    AF
+   1446/     7E7 :  C5                          PUSH    BC
+   1447/     7E8 :  E5                          PUSH    HL
+   1448/     7E9 :  D5                          PUSH    DE
+   1449/     7EA :  CD B3 09            GETL1:  CALL    QQKEY		; ENTRY KEY
+   1450/     7ED :  F5                  AUTO3:  PUSH    AF		; IN KEY DATA SAVE
+   1451/     7EE :  47                          LD      B,A
+   1452/     7EF :  3A 9D 11                    LD      A,(SWRK)	; BELL WORK
+   1453/     7F2 :  0F                          RRCA    
+   1454/     7F3 :  D4 77 05                    CALL    NC,QBEL		; ENTRY BELL
+   1455/     7F6 :  78                          LD      A,B
+   1456/     7F7 :  21 70 11                    LD      HL,KANAF	; KANA & GRAPH FLAGS
+   1457/     7FA :  E6 F0                       AND     0F0H
+   1458/     7FC :  FE C0                       CP      0C0H
+   1459/     7FE :  D1                          POP     DE		; EREG=FLAGREG
+   1460/     7FF :  78                          LD      A,B
+   1461/     800 :  20 16                       JR      NZ,GETL2	; NOT C0H
+   1462/     802 :  FE CD                       CP      0CDH		; CR
+   1463/     804 :  28 55                       JR      Z,GETL3
+   1464/     806 :  FE CB                       CP      0CBH		; BREAK
+   1465/     808 :  CA 22 08                    JP      Z,GETLC
+   1466/     80B :  FE CF                       CP      0CFH		; NIKO MARK WH.
+   1467/     80D :  28 09                       JR      Z,GETL2
+   1468/     80F :  FE C7                       CP      0C7H		; CRT EDITION
+   1469/     811 :  30 0A                       JR      NC,GETL5	; <=C7H
+   1470/     813 :  CB 1B                       RR      E		; >C7H & CFLAG, CY ? GRAPHIC MODE,CURS.DISPL.
+   1471/     815 :  78                          LD      A,B
+   1472/     816 :  30 05                       JR      NC,GETL5
+   1473/     818 :  CD B5 0D            GETL2:  CALL    QDSP		; DISPL.
+   1474/     81B :  18 CD                       JR      GETL1
+   1475/     81D :                      
+   1476/     81D :  CD DC 0D            GETL5:  CALL    QDPCT		; CRT CONTROL
+   1477/     820 :  18 C8                       JR      GETL1
+   1478/     822 :                      
+   1479/     822 :                      ;	BREAK IN
+   1480/     822 :                      
+   1481/     822 :  E1                  GETLC:  POP     HL
+   1482/     823 :  E5                          PUSH    HL
+   1483/     824 :  36 1B                       LD      (HL),1BH	; BREAK CODE
+   1484/     826 :  23                          INC     HL
+   1485/     827 :  36 0D                       LD      (HL),0DH
+   1486/     829 :  18 53                       JR      GETLR
+   1487/     82B :                      
+   1488/     82B :                      ;	GETLA
+   1489/     82B :                      
+   1490/     82B :  0F                  GETLA:  RRCA    		; CY<--D7
+   1491/     82C :  30 37                       JR      NC,GETL6
+   1492/     82E :  18 33                       JR      GETLB
+   1493/     830 :                      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 26 - 9.6.1998 9:06:29
+
+
+   1494/     830 :                      ;	DELAY 7 MSEC AND SWEP
+   1495/     830 :                      
+   1496/     830 :  CD 96 09            DSWEP:  CALL    DLY12
+   1497/     833 :  CD 50 0A                    CALL    QSWEP
+   1498/     836 :  C9                          RET     
+   1499/     837 :                      
+   1500/     837 :  00                          NOP     
+   1501/     838 :  00                          NOP     
+   1502/     839 :  00                          NOP     
+   1503/     83A :  00                          NOP     
+   1504/     83B :  00                          NOP     
+   1505/     83C :  00                          NOP     
+   1506/     83D :  00                          NOP     
+   1507/     83E :  00                          NOP     
+   1508/     83F :  00                          NOP     
+   1509/     840 :  00                          NOP     
+   1510/     841 :  00                          NOP     
+   1511/     842 :  00                          NOP     
+   1512/     843 :  00                          NOP     
+   1513/     844 :  00                          NOP     
+   1514/     845 :  00                          NOP     
+   1515/     846 :  00                          NOP     
+   1516/     847 :  00                          NOP     
+   1517/     848 :  00                          NOP     
+   1518/     849 :  00                          NOP     
+   1519/     84A :  00                          NOP     
+   1520/     84B :  00                          NOP     
+   1521/     84C :  00                          NOP     
+   1522/     84D :  00                          NOP     
+   1523/     84E :  00                          NOP     
+   1524/     84F :  00                          NOP     
+   1525/     850 :  00                          NOP     
+   1526/     851 :  00                          NOP     
+   1527/     852 :  00                          NOP     
+   1528/     853 :  00                          NOP     
+   1529/     854 :  00                          NOP     
+   1530/     855 :  00                          NOP     
+   1531/     856 :  00                          NOP     
+   1532/     857 :  00                          NOP     
+   1533/     858 :  00                          NOP     
+   1534/     859 :  00                          NOP     
+   1535/     85A :  00                          NOP     
+   1536/     85B :                      
+   1537/     85B :  CD F3 02            GETL3:  CALL    PMANG		; CR
+   1538/     85E :  06 28                       LD      B,40		; 1 LINE
+   1539/     860 :  30 C9                       JR      NC,GETLA
+   1540/     862 :  25                          DEC     H		; BEFORE LINE
+   1541/     863 :  06 50               GETLB:  LD      B,80		; 2 LINE
+   1542/     865 :  2E 00               GETL6:  LD      L,0
+   1543/     867 :  CD B4 0F                    CALL    QPNT1
+   1544/     86A :  D1                          POP     DE		; STORE TOP ADDRESS
+   1545/     86B :  D5                          PUSH    DE
+   1546/     86C :  7E                  GETLZ:  LD      A,(HL)
+   1547/     86D :  CD CE 0B                    CALL    QDACN
+   1548/     870 :  12                          LD      (DE),A
+   1549/     871 :  23                          INC     HL
+   1550/     872 :  13                          INC     DE
+   1551/     873 :  10 F7                       DJNZ    GETLZ
+   1552/     875 :  EB                          EX      DE,HL
+   1553/     876 :  36 0D               GETLU:  LD      (HL),0DH
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 27 - 9.6.1998 9:06:29
+
+
+   1554/     878 :  2B                          DEC     HL
+   1555/     879 :  7E                          LD      A,(HL)
+   1556/     87A :  FE 20                       CP      20H		; SPACE THEN CR
+   1557/     87C :                      
+   1558/     87C :                      ;	CR AND NEW LINE
+   1559/     87C :                      
+   1560/     87C :  28 F8                       JR      Z,GETLU
+   1561/     87E :                      
+   1562/     87E :                      ;	NEW LINE RETURN
+   1563/     87E :                      
+   1564/     87E :  CD 0E 09            GETLR:  CALL    QLTNL
+   1565/     881 :  D1                          POP     DE
+   1566/     882 :  E1                          POP     HL
+   1567/     883 :  C1                          POP     BC
+   1568/     884 :  F1                          POP     AF
+   1569/     885 :  C9                          RET     
+   1570/     886 :                      
+   1571/     886 :  00                          NOP     
+   1572/     887 :  00                          NOP     
+   1573/     888 :  00                          NOP     
+   1574/     889 :  00                          NOP     
+   1575/     88A :  00                          NOP     
+   1576/     88B :  00                          NOP     
+   1577/     88C :  00                          NOP     
+   1578/     88D :  00                          NOP     
+   1579/     88E :  00                          NOP     
+   1580/     88F :  00                          NOP     
+   1581/     890 :  00                          NOP     
+   1582/     891 :  00                          NOP     
+   1583/     892 :  00                          NOP     
+   1584/     893 :                      
+   1585/     893 :                      ;	MESSAGE PRINT
+   1586/     893 :                      ;	DE PRINT DATA LOW ADDRESS
+   1587/     893 :                      ;	END=CR
+   1588/     893 :                      
+   1589/     893 :  F5                  QMSG:   PUSH    AF
+   1590/     894 :  C5                          PUSH    BC
+   1591/     895 :  D5                          PUSH    DE
+   1592/     896 :  1A                  MSG1:   LD      A,(DE)
+   1593/     897 :  FE 0D                       CP      0DH		; CR
+   1594/     899 :  28 0C                       JR      Z,MSGX2
+   1595/     89B :  CD 35 09                    CALL    QPRNT
+   1596/     89E :  13                          INC     DE
+   1597/     89F :  18 F5                       JR      MSG1
+   1598/     8A1 :                      
+   1599/     8A1 :                      ;	ALL PRINT MESSAGE
+   1600/     8A1 :                      
+   1601/     8A1 :  F5                  QMSGX:  PUSH    AF
+   1602/     8A2 :  C5                          PUSH    BC
+   1603/     8A3 :  D5                          PUSH    DE
+   1604/     8A4 :  1A                  MSGX1:  LD      A,(DE)
+   1605/     8A5 :  FE 0D                       CP      0DH
+   1606/     8A7 :  CA E6 0E            MSGX2:  JP      Z,QRSTR1
+   1607/     8AA :  CD B9 0B                    CALL    QADCN
+   1608/     8AD :  CD 6C 09                    CALL    PRNT3
+   1609/     8B0 :  13                          INC     DE
+   1610/     8B1 :  18 F1                       JR      MSGX1
+   1611/     8B3 :                      
+   1612/     8B3 :                      ;	TOP OF KEYTBLS
+   1613/     8B3 :                      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 28 - 9.6.1998 9:06:30
+
+
+   1614/     8B3 :  11 2A 0C            QKYSM:  LD      DE,KTBLS	; SHIFT ALSO
+   1615/     8B6 :  18 42                       JR      QKY5
+   1616/     8B8 :                      
+   1617/     8B8 :                      ;	BREAK CODE IN
+   1618/     8B8 :                      
+   1619/     8B8 :  3E CB               NBRK:   LD      A,0CBH		; BREAK CODE
+   1620/     8BA :  B7                          OR      A
+   1621/     8BB :  18 19                       JR      QKY1
+   1622/     8BD :                      
+   1623/     8BD :                      ;	GETKEY
+   1624/     8BD :                      ;	NO ECHO BACK
+   1625/     8BD :                      ;	EXIT ACC=ASCII CODE
+   1626/     8BD :                      
+   1627/     8BD :  CD CA 08            QGET:   CALL    QKEY		; KEY IN (DISPLAY CODE)
+   1628/     8C0 :  D6 F0                       SUB     0F0H		; NOT KEYIN CODE
+   1629/     8C2 :  C8                          RET     Z
+   1630/     8C3 :  C6 F0                       ADD     A,0F0H
+   1631/     8C5 :  C3 CE 0B                    JP      QDACN		; DISPLAY TO ASCII CODE
+   1632/     8C8 :                      
+   1633/     8C8 :  00                          NOP     
+   1634/     8C9 :  00                          NOP     
+   1635/     8CA :                      
+   1636/     8CA :                      ;	1 KEY INPUT
+   1637/     8CA :                      ;	IN   B=KEY MODE (SHIFT, CTRL, BREAK)
+   1638/     8CA :                      ;	     C=KEY DATA (COLUMN & ROW)
+   1639/     8CA :                      ;	EXIT ACC=DISPLAY CODE
+   1640/     8CA :                      ;	     IF NO KEY  ACC=F0H
+   1641/     8CA :                      ;	     IF CY=1 THEN ATTRIBUTE ON
+   1642/     8CA :                      ;	                  (SMALL, HIRAKANA)
+   1643/     8CA :                      
+   1644/     8CA :  C5                  QKEY:   PUSH    BC
+   1645/     8CB :  D5                          PUSH    DE
+   1646/     8CC :  E5                          PUSH    HL
+   1647/     8CD :  CD 30 08                    CALL    DSWEP		; DELAY AND KEY SWEP
+   1648/     8D0 :  78                          LD      A,B
+   1649/     8D1 :  07                          RLCA    
+   1650/     8D2 :  38 06                       JR      C,QKY2
+   1651/     8D4 :  3E F0                       LD      A,0F0H		; SHIFT OR CTRL HERE
+   1652/     8D6 :  E1                  QKY1:   POP     HL
+   1653/     8D7 :  D1                          POP     DE
+   1654/     8D8 :  C1                          POP     BC
+   1655/     8D9 :  C9                          RET     
+   1656/     8DA :                      
+   1657/     8DA :  11 EA 0B            QKY2:   LD      DE,KTBL		; NORMAL KEY TABLE
+   1658/     8DD :  78                          LD      A,B
+   1659/     8DE :  FE 88                       CP      88H		; BREAK IN (SHIFT & BRK)
+   1660/     8E0 :  28 D6                       JR      Z,NBRK
+   1661/     8E2 :  26 00                       LD      H,0		; HL=ROW & COLUMN
+   1662/     8E4 :  69                          LD      L,C
+   1663/     8E5 :  CB 6F                       BIT     5,A		; CTRL CHECK
+   1664/     8E7 :  20 0E                       JR      NZ,L08F7	; YES, CTRL
+   1665/     8E9 :  3A 70 11                    LD      A,(KANAF)	; 0=NR., 1=GRAPH
+   1666/     8EC :  0F                          RRCA    
+   1667/     8ED :  DA FE 08                    JP      C,QKYGRP	; GRAPH MODE
+   1668/     8F0 :  78                          LD      A,B		; CTRL KEY CHECK
+   1669/     8F1 :  17                          RLA     
+   1670/     8F2 :  17                          RLA     
+   1671/     8F3 :  38 BE                       JR      C,QKYSM
+   1672/     8F5 :  18 03                       JR      QKY5
+   1673/     8F7 :                      
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 29 - 9.6.1998 9:06:30
+
+
+   1674/     8F7 :  11 AA 0C            L08F7:  LD      DE,KTBLC	; CONTROL KEY TABLE
+   1675/     8FA :  19                  QKY5:   ADD     HL,DE		; TABLE
+   1676/     8FB :  7E                  QKY55:  LD      A,(HL)
+   1677/     8FC :  18 D8                       JR      QKY1
+   1678/     8FE :                      
+   1679/     8FE :  CB 70               QKYGRP: BIT     6,B
+   1680/     900 :  28 07                       JR      Z,QKYGRS
+   1681/     902 :  11 E9 0C                    LD      DE,KTBLG
+   1682/     905 :  19                          ADD     HL,DE
+   1683/     906 :  37                          SCF     
+   1684/     907 :  18 F2                       JR      QKY55
+   1685/     909 :                      
+   1686/     909 :  11 6A 0C            QKYGRS: LD      DE,KTBLGS
+   1687/     90C :  18 EC                       JR      QKY5
+   1688/     90E :                      
+   1689/     90E :                      ;	NEWLINE
+   1690/     90E :                      
+   1691/     90E :  AF                  QLTNL:  XOR     A
+   1692/     90F :  32 94 11                    LD      (DPRNT),A	; ROW POINTER
+   1693/     912 :  3E CD                       LD      A,0CDH		; CR
+   1694/     914 :  18 43                       JR      PRNT5
+   1695/     916 :                      
+   1696/     916 :  00                          NOP     
+   1697/     917 :  00                          NOP     
+   1698/     918 :                      
+   1699/     918 :  3A 94 11            QNL:    LD      A,(DPRNT)
+   1700/     91B :  B7                          OR      A
+   1701/     91C :  C8                          RET     Z
+   1702/     91D :  18 EF                       JR      QLTNL
+   1703/     91F :                      
+   1704/     91F :  00                          NOP     
+   1705/     920 :                      
+   1706/     920 :                      ;	PRINT SPACE
+   1707/     920 :                      
+   1708/     920 :  3E 20               QPRTS:  LD      A,20H
+   1709/     922 :  18 11                       JR      QPRNT
+   1710/     924 :                      
+   1711/     924 :                      ;	PRINT TAB
+   1712/     924 :                      
+   1713/     924 :  CD 0C 00            QPRTT:  CALL    PRNTS
+   1714/     927 :  3A 94 11                    LD      A,(DPRNT)
+   1715/     92A :  B7                          OR      A
+   1716/     92B :  C8                          RET     Z
+   1717/     92C :  D6 0A               L092C:  SUB     10
+   1718/     92E :  38 F4                       JR      C,QPRTT
+   1719/     930 :  20 FA                       JR      NZ,L092C
+   1720/     932 :  00                          NOP     
+   1721/     933 :  00                          NOP     
+   1722/     934 :  00                          NOP     
+   1723/     935 :                      
+   1724/     935 :                      ;	PRINT
+   1725/     935 :                      ;	IN ACC=PRINT DATA (ASCII)
+   1726/     935 :                      
+   1727/     935 :  FE 0D               QPRNT:  CP      0DH		; CR
+   1728/     937 :  28 D5                       JR      Z,QLTNL
+   1729/     939 :  C5                          PUSH    BC
+   1730/     93A :  4F                          LD      C,A
+   1731/     93B :  47                          LD      B,A
+   1732/     93C :  CD 46 09                    CALL    QPRT
+   1733/     93F :  78                          LD      A,B
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 30 - 9.6.1998 9:06:30
+
+
+   1734/     940 :  C1                          POP     BC
+   1735/     941 :  C9                          RET     
+   1736/     942 :                      
+   1737/     942 :  4F 4B 21 0D         MSGOK:	DB	"OK!\r"
+   1738/     946 :                      
+   1739/     946 :                      ;	PRINT ROUTINE
+   1740/     946 :                      ;	1 CHARACTER
+   1741/     946 :                      ;	INPUT:C=ASCII DATA (QDSP+QDPCT)
+   1742/     946 :                      
+   1743/     946 :  79                  QPRT:	LD	A,C 
+   1744/     947 :  CD B9 0B                    CALL    QADCN		; ASCII TO DSPLAY
+   1745/     94A :  4F                          LD      C,A
+   1746/     94B :  FE F0                       CP      0F0H
+   1747/     94D :  C8                          RET     Z		; ZERO=ILLEGAL DATA
+   1748/     94E :  E6 F0                       AND     0F0H		; MSD CHECK
+   1749/     950 :  FE C0                       CP      0C0H
+   1750/     952 :  79                          LD      A,C
+   1751/     953 :  20 17                       JR      NZ,PRNT3
+   1752/     955 :  FE C7                       CP      0C7H
+   1753/     957 :  30 13                       JR      NC,PRNT3	; CRT EDITOR
+   1754/     959 :  CD DC 0D            PRNT5:  CALL    QDPCT
+   1755/     95C :  FE C3                       CP      0C3H		; "->"
+   1756/     95E :  28 0F                       JR      Z,PRNT4
+   1757/     960 :  FE C5                       CP      0C5H		; HOME
+   1758/     962 :  28 03                       JR      Z,PRNT2
+   1759/     964 :  FE C6                       CP      0C6H		; CLR
+   1760/     966 :  C0                          RET     NZ
+   1761/     967 :  AF                  PRNT2:  XOR     A
+   1762/     968 :  32 94 11            L0968:  LD      (DPRNT),A
+   1763/     96B :  C9                          RET     
+   1764/     96C :                      
+   1765/     96C :  CD B5 0D            PRNT3:  CALL    QDSP
+   1766/     96F :  3A 94 11            PRNT4:  LD      A,(DPRNT)	; TAB POINT+1
+   1767/     972 :  3C                          INC     A
+   1768/     973 :  FE 50                       CP      80
+   1769/     975 :  38 F1                       JR      C,L0968
+   1770/     977 :  D6 50                       SUB     80
+   1771/     979 :  18 ED                       JR      L0968
+   1772/     97B :                      
+   1773/     97B :                      ;	FLASHING BYPASS 1
+   1774/     97B :                      
+   1775/     97B :  3A 8E 11            FLAS1:  LD      A,(FLASH)
+   1776/     97E :  18 6F                       JR      FLAS2
+   1777/     980 :                      
+   1778/     980 :                      ;	BREAK SUBROUTINE BYPASS 1
+   1779/     980 :                      ;	CTRL OR NOT KEY
+   1780/     980 :                      
+   1781/     980 :  CB 6F               QBRK2:  BIT     5,A		; NOT OR CTRL
+   1782/     982 :  28 02                       JR      Z,QBRK3		; CTRL
+   1783/     984 :  B7                          OR      A		; NOTKEY A=7FH
+   1784/     985 :  C9                          RET     
+   1785/     986 :                      
+   1786/     986 :  3E 20               QBRK3:  LD      A,20H		; CTRL D5=1
+   1787/     988 :  B7                          OR      A		; ZERO FLG CLR
+   1788/     989 :  37                          SCF     
+   1789/     98A :  C9                          RET     
+   1790/     98B :                      
+   1791/     98B :  46 49 4C 45 4E 41   MSGSV:	DB	"FILENAME? "
+                    4D 45 3F 20 
+   1792/     995 :  0D                  	DB	0DH
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 31 - 9.6.1998 9:06:30
+
+
+   1793/     996 :                      
+   1794/     996 :                      ;	DLY 7 MSEC
+   1795/     996 :  C5                  DLY12:  PUSH    BC
+   1796/     997 :  06 15                       LD      B,15H
+   1797/     999 :  CD 4A 0A            L0999:  CALL    DLY3
+   1798/     99C :  10 FB                       DJNZ    L0999
+   1799/     99E :  C1                          POP     BC
+   1800/     99F :  C9                          RET     
+   1801/     9A0 :                      
+   1802/     9A0 :                      ;	LOADING MESSAGE
+   1803/     9A0 :                      
+   1804/     9A0 :  4C 4F 41 44 49 4E   MSGQ2:	DB	"LOADING \r"
+                    47 20 0D 
+   1805/     9A9 :                      
+   1806/     9A9 :                      ;	DELAY FOR LONG PULSE
+   1807/     9A9 :                      
+   1808/     9A9 :  3E 59               DLY4:   LD      A,59H		; 18*89+20
+   1809/     9AB :  3D                  L09AB:  DEC     A
+   1810/     9AC :  C2 AB 09                    JP      NZ,L09AB
+   1811/     9AF :  C9                          RET     
+   1812/     9B0 :                      
+   1813/     9B0 :  00                          NOP     
+   1814/     9B1 :  00                          NOP     
+   1815/     9B2 :  00                          NOP     
+   1816/     9B3 :                      
+   1817/     9B3 :                      ;	KEY BOARD SEARCH
+   1818/     9B3 :                      ;	& DISPLAY CODE CONVERSION
+   1819/     9B3 :                      ;	EXIT A=DISPLAY CODE
+   1820/     9B3 :                      ;	     CY=GRAPH MODE
+   1821/     9B3 :                      ;	WITH CURSOR DISPLAY
+   1822/     9B3 :                      
+   1823/     9B3 :  E5                  QQKEY:  PUSH    HL
+   1824/     9B4 :  CD 92 0B                    CALL    QSAVE
+   1825/     9B7 :  CD 7E 05            KSL1:   CALL    FLKEY		; KEY
+   1826/     9BA :  20 FB                       JR      NZ,KSL1		; KEY IN THEN JUMP
+   1827/     9BC :  CD 7E 05            KSL2:   CALL    FLKEY
+   1828/     9BF :  28 FB                       JR      Z,KSL2		; NOT KEY IN THEN JUMP
+   1829/     9C1 :  67                          LD      H,A
+   1830/     9C2 :  CD 96 09                    CALL    DLY12		; DELAY CHATTER
+   1831/     9C5 :  CD CA 08                    CALL    QKEY
+   1832/     9C8 :  F5                          PUSH    AF
+   1833/     9C9 :  BC                          CP      H		; CHATTER CHECK
+   1834/     9CA :  E1                          POP     HL
+   1835/     9CB :  20 EF                       JR      NZ,KSL2
+   1836/     9CD :  E5                          PUSH    HL
+   1837/     9CE :  F1                          POP     AF		; IN KEY DATA
+   1838/     9CF :  CD F0 05                    CALL    QLOAD		; FLASHING DATA LOAD
+   1839/     9D2 :  E1                          POP     HL
+   1840/     9D3 :  C9                          RET     
+   1841/     9D4 :                      
+   1842/     9D4 :                      ;	CLEAR 2
+   1843/     9D4 :                      
+   1844/     9D4 :  AF                  NCLR08: XOR     A		; CY FLAG
+   1845/     9D5 :  01 00 08            NCLR8:  LD      BC,0800H
+   1846/     9D8 :  D5                  CLEAR:  PUSH    DE		; BC=CLR BYTE SIZE, A=CLR DATA
+   1847/     9D9 :  57                          LD      D,A
+   1848/     9DA :  72                  CLEAR1: LD      (HL),D
+   1849/     9DB :  23                          INC     HL
+   1850/     9DC :  0B                          DEC     BC
+   1851/     9DD :  78                          LD      A,B
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 32 - 9.6.1998 9:06:30
+
+
+   1852/     9DE :  B1                          OR      C
+   1853/     9DF :  20 F9                       JR      NZ,CLEAR1
+   1854/     9E1 :  D1                          POP     DE
+   1855/     9E2 :  C9                          RET     
+   1856/     9E3 :                      
+   1857/     9E3 :                      ;	FLASHING 2
+   1858/     9E3 :                      
+   1859/     9E3 :  F5                  QFLS:   PUSH    AF
+   1860/     9E4 :  E5                          PUSH    HL
+   1861/     9E5 :  3A 02 E0                    LD      A,(KEYPC)
+   1862/     9E8 :  07                          RLCA    
+   1863/     9E9 :  07                          RLCA    
+   1864/     9EA :  38 8F                       JR      C,FLAS1
+   1865/     9EC :  3A 92 11                    LD      A,(FLSDT)
+   1866/     9EF :  CD B1 0F            FLAS2:  CALL    QPONT		; DISPLAY POSITION
+   1867/     9F2 :  77                          LD      (HL),A
+   1868/     9F3 :  E1                          POP     HL
+   1869/     9F4 :  F1                          POP     AF
+   1870/     9F5 :  C9                          RET     
+   1871/     9F6 :                      
+   1872/     9F6 :  00                          NOP     
+   1873/     9F7 :  00                          NOP     
+   1874/     9F8 :  00                          NOP     
+   1875/     9F9 :  00                          NOP     
+   1876/     9FA :  00                          NOP     
+   1877/     9FB :  00                          NOP     
+   1878/     9FC :  00                          NOP     
+   1879/     9FD :  00                          NOP     
+   1880/     9FE :  00                          NOP     
+   1881/     9FF :                      
+   1882/     9FF :  18 E2               QFLAS:  JR      QFLS
+   1883/     A01 :                      
+   1884/     A01 :                      ;	SHORT AND LONG PULSE FOR 1 BIT WRITE
+   1885/     A01 :                      
+   1886/     A01 :  F5                  SHORT:  PUSH    AF		; 12
+   1887/     A02 :  3E 03                       LD      A,03H		; 9
+   1888/     A04 :  32 03 E0                    LD      (CSTPT),A	; E003H PC3=1:16
+   1889/     A07 :  CD 59 07                    CALL    DLY1		; 20+18*21+20
+   1890/     A0A :  CD 59 07                    CALL    DLY1		; 20+18*21+20
+   1891/     A0D :  3E 02                       LD      A,02H		; 9
+   1892/     A0F :  32 03 E0                    LD      (CSTPT),A	; E003H PC3=0:16
+   1893/     A12 :  CD 59 07                    CALL    DLY1		; 20+18*21+20
+   1894/     A15 :  CD 59 07                    CALL    DLY1		; 20+18*21+20
+   1895/     A18 :  F1                          POP     AF		; 11
+   1896/     A19 :  C9                          RET     		; 11
+   1897/     A1A :                      
+   1898/     A1A :  F5                  LONG:   PUSH    AF		; 11
+   1899/     A1B :  3E 03                       LD      A,03H		; 9
+   1900/     A1D :  32 03 E0                    LD      (CSTPT),A	; 16
+   1901/     A20 :  CD A9 09                    CALL    DLY4		; 20+18*89+20
+   1902/     A23 :  3E 02                       LD      A,02H		; 9
+   1903/     A25 :  32 03 E0                    LD      (CSTPT),A	; 16
+   1904/     A28 :  CD A9 09                    CALL    DLY4		; 20+18*89+20
+   1905/     A2B :  F1                          POP     AF		; 11
+   1906/     A2C :  C9                          RET     		; 11
+   1907/     A2D :                      
+   1908/     A2D :  00                          NOP     
+   1909/     A2E :  00                          NOP     
+   1910/     A2F :  00                          NOP     
+   1911/     A30 :  00                          NOP     
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 33 - 9.6.1998 9:06:30
+
+
+   1912/     A31 :  00                          NOP     
+   1913/     A32 :                      
+   1914/     A32 :                      ;	BREAK KEY CHECK
+   1915/     A32 :                      ;	AND SHIFT, CTRL KEY CHECK
+   1916/     A32 :                      ;	EXIT BREAK ON : ZERO=1
+   1917/     A32 :                      ;	           OFF: ZERO=0
+   1918/     A32 :                      ;	     NO KEY   : CY  =0
+   1919/     A32 :                      ;	     KEY IN   : CY  =1
+   1920/     A32 :                      ;	      A D6=1  : SHIFT ON
+   1921/     A32 :                      ;	          =0  :       OFF
+   1922/     A32 :                      ;	        D5=1  : CTRL ON
+   1923/     A32 :                      ;	          =0  :      OFF
+   1924/     A32 :                      ;		D4=1  : SHIFT+CNT ON
+   1925/     A32 :                      ;		  =0  :           OFF
+   1926/     A32 :                      
+   1927/     A32 :  3E F8               QBRK:   LD      A,0F8H		; LINE 8SWEEP
+   1928/     A34 :  32 00 E0                    LD      (KEYPA),A
+   1929/     A37 :  00                          NOP     
+   1930/     A38 :  3A 01 E0                    LD      A,(KEYPB)
+   1931/     A3B :  B7                          OR      A
+   1932/     A3C :  1F                          RRA     
+   1933/     A3D :  DA 80 09                    JP      C,QBRK2		; SHIFT ?
+   1934/     A40 :  17                          RLA     
+   1935/     A41 :  17                          RLA     
+   1936/     A42 :  30 04                       JR      NC,QBRK1	; BREAK ?
+   1937/     A44 :  3E 40                       LD      A,40H		; SHIFT D6=1
+   1938/     A46 :  37                          SCF     
+   1939/     A47 :  C9                          RET     
+   1940/     A48 :                      
+   1941/     A48 :  AF                  QBRK1:  XOR     A		; SHIFT ?
+   1942/     A49 :  C9                          RET     
+   1943/     A4A :                      
+   1944/     A4A :                      ;	320 U SEC DELAY
+   1945/     A4A :                      
+   1946/     A4A :  3E 3F               DLY3:   LD      A,3FH		; 18*63+33
+   1947/     A4C :  C3 62 07                    JP      L0762		; JP DLY2+2
+   1948/     A4F :                      
+   1949/     A4F :  00                          NOP     
+   1950/     A50 :                      
+   1951/     A50 :                      ;	KEY BOARD SWEEP
+   1952/     A50 :                      ;	EXIT B,D7=0  NO DATA
+   1953/     A50 :                      ;	         =1  DATA
+   1954/     A50 :                      ;	       D6=0  SHIFT OFF
+   1955/     A50 :                      ;		 =1  SHIFT ON
+   1956/     A50 :                      ;	       D5=0  CTRL OFF
+   1957/     A50 :                      ;		 =1  CTRL ON
+   1958/     A50 :                      ;	       D4=0  SHIFT+CTRL OFF
+   1959/     A50 :                      ;		 =1  SHIFT+CTRL ON
+   1960/     A50 :                      ;	     C   = ROW & COLUMN
+   1961/     A50 :                      ;		7 6 5 4 3 2 1 0
+   1962/     A50 :                      ;		* * ^ ^ ^ < < <
+   1963/     A50 :                      
+   1964/     A50 :  D5                  QSWEP:  PUSH    DE
+   1965/     A51 :  E5                          PUSH    HL
+   1966/     A52 :  AF                          XOR     A
+   1967/     A53 :  06 F8                       LD      B,0F8H
+   1968/     A55 :  57                          LD      D,A
+   1969/     A56 :  CD 32 0A                    CALL    QBRK
+   1970/     A59 :  20 04                       JR      NZ,SWEP6
+   1971/     A5B :  16 88                       LD      D,88H		; BREAK ON
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 34 - 9.6.1998 9:06:30
+
+
+   1972/     A5D :  18 14                       JR      SWEP9
+   1973/     A5F :                      
+   1974/     A5F :  30 05               SWEP6:  JR      NC,SWEP0
+   1975/     A61 :  57                          LD      D,A
+   1976/     A62 :  18 02                       JR      SWEP0
+   1977/     A64 :                      
+   1978/     A64 :  CB FA               SWEP01: SET     7,D
+   1979/     A66 :  05                  SWEP0:  DEC     B
+   1980/     A67 :  78                          LD      A,B
+   1981/     A68 :  32 00 E0                    LD      (KEYPA),A
+   1982/     A6B :  FE EF                       CP      0EFH		; MAP SWEEP END ?
+   1983/     A6D :  20 08                       JR      NZ,SWEP3
+   1984/     A6F :  FE F8                       CP      0F8H		; BREAK KEY ROW
+   1985/     A71 :  28 F3                       JR      Z,SWEP0
+   1986/     A73 :  42                  SWEP9:  LD      B,D
+   1987/     A74 :  E1                          POP     HL
+   1988/     A75 :  D1                          POP     DE
+   1989/     A76 :  C9                          RET     
+   1990/     A77 :                      
+   1991/     A77 :  3A 01 E0            SWEP3:  LD      A,(KEYPB)
+   1992/     A7A :  2F                          CPL     
+   1993/     A7B :  B7                          OR      A
+   1994/     A7C :  28 E8                       JR      Z,SWEP0
+   1995/     A7E :  5F                          LD      E,A
+   1996/     A7F :  26 08               SWEP2:  LD      H,8
+   1997/     A81 :  78                          LD      A,B
+   1998/     A82 :  E6 0F                       AND     0FH
+   1999/     A84 :  07                          RLCA    
+   2000/     A85 :  07                          RLCA    
+   2001/     A86 :  07                          RLCA    
+   2002/     A87 :  4F                          LD      C,A
+   2003/     A88 :  7B                          LD      A,E
+   2004/     A89 :  25                  L0A89:  DEC     H
+   2005/     A8A :  0F                          RRCA    
+   2006/     A8B :  30 FC                       JR      NC,L0A89
+   2007/     A8D :  7C                          LD      A,H
+   2008/     A8E :  81                          ADD     A,C
+   2009/     A8F :  4F                          LD      C,A
+   2010/     A90 :  18 D2                       JR      SWEP01
+   2011/     A92 :                      ;
+   2012/     A92 :                      ;
+   2013/     A92 :                      ;   ASCII TO DISPLAY CODE TABL
+   2014/     A92 :                      ;
+   2015/     A92 :                      ATBL:	
+   2016/     A92 :                      ;  00 - 0F
+   2017/     A92 :  F0                  	DB	0F0H		; ^ @
+   2018/     A93 :  F0                  	DB	0F0H		; ^ A
+   2019/     A94 :  F0                  	DB	0F0H		; ^ B
+   2020/     A95 :  F3                  	DB	0F3H		; ^ C
+   2021/     A96 :  F0                  	DB	0F0H		; ^ D
+   2022/     A97 :  F5                  	DB	0F5H		; ^ E
+   2023/     A98 :  F0                  	DB	0F0H		; ^ F
+   2024/     A99 :  F0                  	DB	0F0H		; ^ G
+   2025/     A9A :  F0                  	DB	0F0H		; ^ H
+   2026/     A9B :  F0                  	DB	0F0H		; ^ I
+   2027/     A9C :  F0                  	DB	0F0H		; ^ J
+   2028/     A9D :  F0                  	DB	0F0H		; ^ K
+   2029/     A9E :  F0                  	DB	0F0H		; ^ L
+   2030/     A9F :  F0                  	DB	0F0H		; ^ M
+   2031/     AA0 :  F0                  	DB	0F0H		; ^ N
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 35 - 9.6.1998 9:06:30
+
+
+   2032/     AA1 :  F0                  	DB	0F0H		; ^ O
+   2033/     AA2 :                      ;  10 - 1F
+   2034/     AA2 :  F0                  	DB	0F0H		; ^ P
+   2035/     AA3 :  C1                  	DB	0C1H		; ^ Q CUR. DOWN
+   2036/     AA4 :  C2                  	DB	0C2H		; ^ R CUR. UP
+   2037/     AA5 :  C3                  	DB	0C3H		; ^ S CUR. RIGHT
+   2038/     AA6 :  C4                  	DB	0C4H		; ^ T CUR. LEFT
+   2039/     AA7 :  C5                  	DB	0C5H		; ^ U HOME
+   2040/     AA8 :  C6                  	DB	0C6H		; ^ V CLEAR
+   2041/     AA9 :  F0                  	DB	0F0H		; ^ W
+   2042/     AAA :  F0                  	DB	0F0H		; ^ X
+   2043/     AAB :  F0                  	DB	0F0H		; ^ Y
+   2044/     AAC :  F0                  	DB	0F0H		; ^ Z SEP.
+   2045/     AAD :  F0                  	DB	0F0H		; ^ [
+   2046/     AAE :  F0                  	DB	0F0H		; ^ \
+   2047/     AAF :  F0                  	DB	0F0H		; ^ ]
+   2048/     AB0 :  F0                  	DB	0F0H		; ^ ^
+   2049/     AB1 :  F0                  	DB	0F0H		; ^ -
+   2050/     AB2 :                      ;  20 - 2F
+   2051/     AB2 :  00                  	DB	00H		; SPACE
+   2052/     AB3 :  61                  	DB	61H		; !
+   2053/     AB4 :  62                  	DB	62H		; "
+   2054/     AB5 :  63                  	DB	63H		; #
+   2055/     AB6 :  64                  	DB	64H		; $
+   2056/     AB7 :  65                  	DB	65H		; %
+   2057/     AB8 :  66                  	DB	66H		; &
+   2058/     AB9 :  67                  	DB	67H		; '
+   2059/     ABA :  68                  	DB	68H		; (
+   2060/     ABB :  69                  	DB	69H		; )
+   2061/     ABC :  6B                  	DB	6BH		; *
+   2062/     ABD :  6A                  	DB	6AH		; +
+   2063/     ABE :  2F                  	DB	2FH		; ,
+   2064/     ABF :  2A                  	DB	2AH		; -
+   2065/     AC0 :  2E                  	DB	2EH		; .
+   2066/     AC1 :  2D                  	DB	2DH		; /
+   2067/     AC2 :                      ;  30 - 3F
+   2068/     AC2 :  20                  	DB	20H		; 0
+   2069/     AC3 :  21                  	DB	21H		; 1
+   2070/     AC4 :  22                  	DB	22H		; 2
+   2071/     AC5 :  23                  	DB	23H		; 3
+   2072/     AC6 :  24                  	DB	24H		; 4
+   2073/     AC7 :  25                  	DB	25H		; 5
+   2074/     AC8 :  26                  	DB	26H		; 6
+   2075/     AC9 :  27                  	DB	27H		; 7
+   2076/     ACA :  28                  	DB	28H		; 8
+   2077/     ACB :  29                  	DB	29H		; 9
+   2078/     ACC :  4F                  	DB	4FH		; :
+   2079/     ACD :  2C                  	DB	2CH		; ;
+   2080/     ACE :  51                  	DB	51H		; <
+   2081/     ACF :  2B                  	DB	2BH		; =
+   2082/     AD0 :  57                  	DB	57H		; >
+   2083/     AD1 :  49                  	DB	49H		; ?
+   2084/     AD2 :                      ;  40 - 4F
+   2085/     AD2 :  55                  	DB	55H		; @
+   2086/     AD3 :  01                  	DB	01H		; A
+   2087/     AD4 :  02                  	DB	02H		; B
+   2088/     AD5 :  03                  	DB	03H		; C
+   2089/     AD6 :  04                  	DB	04H		; D
+   2090/     AD7 :  05                  	DB	05H		; E
+   2091/     AD8 :  06                  	DB	06H		; F
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 36 - 9.6.1998 9:06:30
+
+
+   2092/     AD9 :  07                  	DB	07H		; G
+   2093/     ADA :  08                  	DB	08H		; H
+   2094/     ADB :  09                  	DB	09H		; I
+   2095/     ADC :  0A                  	DB	0AH		; J
+   2096/     ADD :  0B                  	DB	0BH		; K
+   2097/     ADE :  0C                  	DB	0CH		; L
+   2098/     ADF :  0D                  	DB	0DH		; M
+   2099/     AE0 :  0E                  	DB	0EH		; N
+   2100/     AE1 :  0F                  	DB	0FH		; O
+   2101/     AE2 :                      ;  50 - 5F
+   2102/     AE2 :  10                  	DB	10H		; P
+   2103/     AE3 :  11                  	DB	11H		; Q
+   2104/     AE4 :  12                  	DB	12H		; R
+   2105/     AE5 :  13                  	DB	13H		; S
+   2106/     AE6 :  14                  	DB	14H		; T
+   2107/     AE7 :  15                  	DB	15H		; U
+   2108/     AE8 :  16                  	DB	16H		; V
+   2109/     AE9 :  17                  	DB	17H		; W
+   2110/     AEA :  18                  	DB	18H		; X
+   2111/     AEB :  19                  	DB	19H		; Y
+   2112/     AEC :  1A                  	DB	1AH		; Z
+   2113/     AED :  52                  	DB	52H		; [
+   2114/     AEE :  59                  	DB	59H		; \
+   2115/     AEF :  54                  	DB	54H		; ]
+   2116/     AF0 :  50                  	DB	50H		; 
+   2117/     AF1 :  45                  	DB	45H		; 
+   2118/     AF2 :                      ;  60 - 6F
+   2119/     AF2 :  C7                  	DB	0C7H		; UFO
+   2120/     AF3 :  C8                  	DB	0C8H
+   2121/     AF4 :  C9                  	DB	0C9H
+   2122/     AF5 :  CA                  	DB	0CAH
+   2123/     AF6 :  CB                  	DB	0CBH
+   2124/     AF7 :  CC                  	DB	0CCH
+   2125/     AF8 :  CD                  	DB	0CDH
+   2126/     AF9 :  CE                  	DB	0CEH
+   2127/     AFA :  CF                  	DB	0CFH
+   2128/     AFB :  DF                  	DB	0DFH
+   2129/     AFC :  E7                  	DB	0E7H
+   2130/     AFD :  E8                  	DB	0E8H
+   2131/     AFE :  E5                  	DB	0E5H
+   2132/     AFF :  E9                  	DB	0E9H
+   2133/     B00 :  EC                  	DB	0ECH
+   2134/     B01 :  ED                  	DB	0EDH
+   2135/     B02 :                      ;  70 - 7F
+   2136/     B02 :  D0                  	DB	0D0H
+   2137/     B03 :  D1                  	DB	0D1H
+   2138/     B04 :  D2                  	DB	0D2H
+   2139/     B05 :  D3                  	DB	0D3H
+   2140/     B06 :  D4                  	DB	0D4H
+   2141/     B07 :  D5                  	DB	0D5H
+   2142/     B08 :  D6                  	DB	0D6H
+   2143/     B09 :  D7                  	DB	0D7H
+   2144/     B0A :  D8                  	DB	0D8H
+   2145/     B0B :  D9                  	DB	0D9H
+   2146/     B0C :  DA                  	DB	0DAH
+   2147/     B0D :  DB                  	DB	0DBH
+   2148/     B0E :  DC                  	DB	0DCH
+   2149/     B0F :  DD                  	DB	0DDH
+   2150/     B10 :  DE                  	DB	0DEH
+   2151/     B11 :  C0                  	DB	0C0H
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 37 - 9.6.1998 9:06:30
+
+
+   2152/     B12 :                      ;  80 - 8F
+   2153/     B12 :  80                  	DB	80H		; }
+   2154/     B13 :  BD                  	DB	0BDH
+   2155/     B14 :  9D                  	DB	9DH
+   2156/     B15 :  B1                  	DB	0B1H
+   2157/     B16 :  B5                  	DB	0B5H
+   2158/     B17 :  B9                  	DB	0B9H
+   2159/     B18 :  B4                  	DB	0B4H
+   2160/     B19 :  9E                  	DB	9EH
+   2161/     B1A :  B2                  	DB	0B2H
+   2162/     B1B :  B6                  	DB	0B6H
+   2163/     B1C :  BA                  	DB	0BAH
+   2164/     B1D :  BE                  	DB	0BEH
+   2165/     B1E :  9F                  	DB	9FH
+   2166/     B1F :  B3                  	DB	0B3H
+   2167/     B20 :  B7                  	DB	0B7H
+   2168/     B21 :  BB                  	DB	0BBH
+   2169/     B22 :                      ;  90 - 9F
+   2170/     B22 :  BF                  	DB	0BFH		; _
+   2171/     B23 :  A3                  	DB	0A3H
+   2172/     B24 :  85                  	DB	85H
+   2173/     B25 :  A4                  	DB	0A4H		; `
+   2174/     B26 :  A5                  	DB	0A5H		; ~
+   2175/     B27 :  A6                  	DB	0A6H
+   2176/     B28 :  94                  	DB	94H
+   2177/     B29 :  87                  	DB	87H
+   2178/     B2A :  88                  	DB	88H
+   2179/     B2B :  9C                  	DB	9CH
+   2180/     B2C :  82                  	DB	82H
+   2181/     B2D :  98                  	DB	98H
+   2182/     B2E :  84                  	DB	84H
+   2183/     B2F :  92                  	DB	92H
+   2184/     B30 :  90                  	DB	90H
+   2185/     B31 :  83                  	DB	83H
+   2186/     B32 :                      ;  A0 - AF
+   2187/     B32 :  91                  	DB	91H
+   2188/     B33 :  81                  	DB	81H
+   2189/     B34 :  9A                  	DB	9AH
+   2190/     B35 :  97                  	DB	97H
+   2191/     B36 :  93                  	DB	93H
+   2192/     B37 :  95                  	DB	95H
+   2193/     B38 :  89                  	DB	89H
+   2194/     B39 :  A1                  	DB	0A1H
+   2195/     B3A :  AF                  	DB	0AFH
+   2196/     B3B :  8B                  	DB	8BH
+   2197/     B3C :  86                  	DB	86H
+   2198/     B3D :  96                  	DB	96H
+   2199/     B3E :  A2                  	DB	0A2H
+   2200/     B3F :  AB                  	DB	0ABH
+   2201/     B40 :  AA                  	DB	0AAH
+   2202/     B41 :  8A                  	DB	8AH
+   2203/     B42 :                      ;  B0 - BF
+   2204/     B42 :  8E                  	DB	8EH
+   2205/     B43 :  B0                  	DB	0B0H
+   2206/     B44 :  AD                  	DB	0ADH
+   2207/     B45 :  8D                  	DB	8DH
+   2208/     B46 :  A7                  	DB	0A7H
+   2209/     B47 :  A8                  	DB	0A8H
+   2210/     B48 :  A9                  	DB	0A9H
+   2211/     B49 :  8F                  	DB	8FH
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 38 - 9.6.1998 9:06:30
+
+
+   2212/     B4A :  8C                  	DB	8CH
+   2213/     B4B :  AE                  	DB	0AEH
+   2214/     B4C :  AC                  	DB	0ACH
+   2215/     B4D :  9B                  	DB	9BH
+   2216/     B4E :  A0                  	DB	0A0H
+   2217/     B4F :  99                  	DB	99H
+   2218/     B50 :  BC                  	DB	0BCH		; {
+   2219/     B51 :  B8                  	DB	0B8H
+   2220/     B52 :                      ;  C0 - CF
+   2221/     B52 :  40                  	DB	40H
+   2222/     B53 :  3B                  	DB	3BH
+   2223/     B54 :  3A                  	DB	3AH
+   2224/     B55 :  70                  	DB	70H
+   2225/     B56 :  3C                  	DB	3CH
+   2226/     B57 :  71                  	DB	71H
+   2227/     B58 :  5A                  	DB	5AH
+   2228/     B59 :  3D                  	DB	3DH
+   2229/     B5A :  43                  	DB	43H
+   2230/     B5B :  56                  	DB	56H
+   2231/     B5C :  3F                  	DB	3FH
+   2232/     B5D :  1E                  	DB	1EH
+   2233/     B5E :  4A                  	DB	4AH
+   2234/     B5F :  1C                  	DB	1CH
+   2235/     B60 :  5D                  	DB	5DH
+   2236/     B61 :  3E                  	DB	3EH
+   2237/     B62 :                      ;  D0 - DF
+   2238/     B62 :  5C                  	DB	5CH
+   2239/     B63 :  1F                  	DB	1FH
+   2240/     B64 :  5F                  	DB	5FH
+   2241/     B65 :  5E                  	DB	5EH
+   2242/     B66 :  37                  	DB	37H
+   2243/     B67 :  7B                  	DB	7BH
+   2244/     B68 :  7F                  	DB	7FH
+   2245/     B69 :  36                  	DB	36H
+   2246/     B6A :  7A                  	DB	7AH
+   2247/     B6B :  7E                  	DB	7EH
+   2248/     B6C :  33                  	DB	33H
+   2249/     B6D :  4B                  	DB	4BH
+   2250/     B6E :  4C                  	DB	4CH
+   2251/     B6F :  1D                  	DB	1DH
+   2252/     B70 :  6C                  	DB	6CH
+   2253/     B71 :  5B                  	DB	5BH
+   2254/     B72 :                      ;  E0 - EF
+   2255/     B72 :  78                  	DB	78H
+   2256/     B73 :  41                  	DB	41H
+   2257/     B74 :  35                  	DB	35H
+   2258/     B75 :  34                  	DB	34H
+   2259/     B76 :  74                  	DB	74H
+   2260/     B77 :  30                  	DB	30H
+   2261/     B78 :  38                  	DB	38H
+   2262/     B79 :  75                  	DB	75H
+   2263/     B7A :  39                  	DB	39H
+   2264/     B7B :  4D                  	DB	4DH
+   2265/     B7C :  6F                  	DB	6FH
+   2266/     B7D :  6E                  	DB	6EH
+   2267/     B7E :  32                  	DB	32H
+   2268/     B7F :  77                  	DB	77H
+   2269/     B80 :  76                  	DB	76H
+   2270/     B81 :  72                  	DB	72H
+   2271/     B82 :                      ;  F0 - FF
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 39 - 9.6.1998 9:06:30
+
+
+   2272/     B82 :  73                  	DB	73H
+   2273/     B83 :  47                  	DB	47H
+   2274/     B84 :  7C                  	DB	7CH
+   2275/     B85 :  53                  	DB	53H
+   2276/     B86 :  31                  	DB	31H
+   2277/     B87 :  4E                  	DB	4EH
+   2278/     B88 :  6D                  	DB	6DH
+   2279/     B89 :  48                  	DB	48H
+   2280/     B8A :  46                  	DB	46H
+   2281/     B8B :  7D                  	DB	7DH
+   2282/     B8C :  44                  	DB	44H
+   2283/     B8D :  1B                  	DB	1BH
+   2284/     B8E :  58                  	DB	58H
+   2285/     B8F :  79                  	DB	79H
+   2286/     B90 :  42                  	DB	42H
+   2287/     B91 :  60                  	DB	60H
+   2288/     B92 :                      
+   2289/     B92 :                      ;	FLASHING DATA SAVE
+   2290/     B92 :                      
+   2291/     B92 :  21 92 11            QSAVE:  LD      HL,FLSDT
+   2292/     B95 :  36 EF                       LD      (HL),0EFH	; NORMAL CURSOR
+   2293/     B97 :  3A 70 11                    LD      A,(KANAF)
+   2294/     B9A :  0F                          RRCA    
+   2295/     B9B :  38 03                       JR      C,L0BA0		; GRAPH MODE
+   2296/     B9D :  0F                          RRCA    
+   2297/     B9E :  30 02                       JR      NC,SV0		; NORMAL MODE
+   2298/     BA0 :  36 FF               L0BA0:  LD      (HL),0FFH	; GRAPH CURSOR
+   2299/     BA2 :  7E                  SV0:    LD      A,(HL)
+   2300/     BA3 :  F5                          PUSH    AF
+   2301/     BA4 :  CD B1 0F                    CALL    QPONT		; FLASHING POSITION
+   2302/     BA7 :  7E                          LD      A,(HL)
+   2303/     BA8 :  32 8E 11                    LD      (FLASH),A
+   2304/     BAB :  F1                          POP     AF
+   2305/     BAC :  77                          LD      (HL),A
+   2306/     BAD :  AF                          XOR     A
+   2307/     BAE :  21 00 E0                    LD      HL,KEYPA
+   2308/     BB1 :  77                  L0BB1:  LD      (HL),A
+   2309/     BB2 :  2F                          CPL     		; OH NO! UNUSED BITS WERE TOUCHED TOO!!!
+   2310/     BB3 :  77                          LD      (HL),A
+   2311/     BB4 :  C9                          RET     
+   2312/     BB5 :                      
+   2313/     BB5 :  36 43               SV1:    LD      (HL),43H	; KANA CURSOR
+   2314/     BB7 :  18 E9                       JR      SV0
+   2315/     BB9 :                      
+   2316/     BB9 :                      ;	ASCII TO DISPLAY CODE CONVERT
+   2317/     BB9 :                      ;	IN ACC:ASCII
+   2318/     BB9 :                      ;	EXIT ACC:DISPLAY CODE
+   2319/     BB9 :                      
+   2320/     BB9 :  C5                  QADCN:  PUSH    BC
+   2321/     BBA :  E5                          PUSH    HL
+   2322/     BBB :  21 92 0A                    LD      HL,ATBL
+   2323/     BBE :  4F                          LD      C,A
+   2324/     BBF :  06 00                       LD      B,0
+   2325/     BC1 :  09                          ADD     HL,BC
+   2326/     BC2 :  7E                          LD      A,(HL)
+   2327/     BC3 :  18 1B                       JR      DACN3
+   2328/     BC5 :                      
+   2329/     BC5 :  56 31 2E 30 41 0D   VRNS:	DB	"V1.0A\r"	; VERSION MANAGEMENT
+   2330/     BCB :  00                          NOP     
+   2331/     BCC :  00                          NOP     
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 40 - 9.6.1998 9:06:30
+
+
+   2332/     BCD :  00                          NOP     
+   2333/     BCE :                      
+   2334/     BCE :                      ;	DISPLAY CODE TO ASCII CONVERSION
+   2335/     BCE :                      ;	IN ACC=DISPLAY CODE
+   2336/     BCE :                      ;	EXIT ACC=ASCII
+   2337/     BCE :                      
+   2338/     BCE :  C5                  QDACN:  PUSH    BC
+   2339/     BCF :  E5                          PUSH    HL
+   2340/     BD0 :  D5                          PUSH    DE
+   2341/     BD1 :  21 92 0A                    LD      HL,ATBL
+   2342/     BD4 :  54                          LD      D,H
+   2343/     BD5 :  5D                          LD      E,L
+   2344/     BD6 :  01 00 01                    LD      BC,0100H
+   2345/     BD9 :  ED B1                       CPIR    
+   2346/     BDB :  28 06                       JR      Z,DACN1
+   2347/     BDD :  3E F0                       LD      A,0F0H
+   2348/     BDF :  D1                  DACN2:  POP     DE
+   2349/     BE0 :  E1                  DACN3:  POP     HL
+   2350/     BE1 :  C1                          POP     BC
+   2351/     BE2 :  C9                          RET     
+   2352/     BE3 :                      
+   2353/     BE3 :  B7                  DACN1:  OR      A
+   2354/     BE4 :  2B                          DEC     HL
+   2355/     BE5 :  ED 52                       SBC     HL,DE
+   2356/     BE7 :  7D                          LD      A,L
+   2357/     BE8 :  18 F5                       JR      DACN2
+   2358/     BEA :                      
+   2359/     BEA :                      ;
+   2360/     BEA :                      ;
+   2361/     BEA :                      ;   KEY MATRIX TO DISPLAY CODE TABL
+   2362/     BEA :                      ;
+   2363/     BEA :                      KTBL:
+   2364/     BEA :                      ;S0   00 - 07
+   2365/     BEA :  BF                  	DB	0BFH		; SPARE
+   2366/     BEB :  CA                  	DB	0CAH		; GRAPH
+   2367/     BEC :  58                  	DB	58H		; 
+   2368/     BED :  C9                  	DB	0C9H		; ALPHA
+   2369/     BEE :  F0                  	DB	0F0H		; NO
+   2370/     BEF :  2C                  	DB	2CH		; ;
+   2371/     BF0 :  4F                  	DB	4FH		; :
+   2372/     BF1 :  CD                  	DB	0CDH		; CR
+   2373/     BF2 :                      ;S1   08 - 0F
+   2374/     BF2 :  19                  	DB	19H		; Y
+   2375/     BF3 :  1A                  	DB	1AH		; Z
+   2376/     BF4 :  55                  	DB	55H		; @
+   2377/     BF5 :  52                  	DB	52H		; [
+   2378/     BF6 :  54                  	DB	54H		; ]
+   2379/     BF7 :  F0                  	DB	0F0H		; NULL
+   2380/     BF8 :  F0                  	DB	0F0H		; NULL
+   2381/     BF9 :  F0                  	DB	0F0H		; NULL
+   2382/     BFA :                      ;S2   10 - 17
+   2383/     BFA :  11                  	DB	11H		; Q
+   2384/     BFB :  12                  	DB	12H		; R
+   2385/     BFC :  13                  	DB	13H		; S
+   2386/     BFD :  14                  	DB	14H		; T
+   2387/     BFE :  15                  	DB	15H		; U
+   2388/     BFF :  16                  	DB	16H		; V
+   2389/     C00 :  17                  	DB	17H		; W
+   2390/     C01 :  18                  	DB	18H		; X
+   2391/     C02 :                      ;S3   18 - 1F
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 41 - 9.6.1998 9:06:30
+
+
+   2392/     C02 :  09                  	DB	09H		; I
+   2393/     C03 :  0A                  	DB	0AH		; J
+   2394/     C04 :  0B                  	DB	0BH		; K
+   2395/     C05 :  0C                  	DB	0CH		; L
+   2396/     C06 :  0D                  	DB	0DH		; M
+   2397/     C07 :  0E                  	DB	0EH		; N
+   2398/     C08 :  0F                  	DB	0FH		; O
+   2399/     C09 :  10                  	DB	10H		; P
+   2400/     C0A :                      ;S4   20 - 27
+   2401/     C0A :  01                  	DB	01H		; A
+   2402/     C0B :  02                  	DB	02H		; B
+   2403/     C0C :  03                  	DB	03H		; C
+   2404/     C0D :  04                  	DB	04H		; D
+   2405/     C0E :  05                  	DB	05H		; E
+   2406/     C0F :  06                  	DB	06H		; F
+   2407/     C10 :  07                  	DB	07H		; G
+   2408/     C11 :  08                  	DB	08H		; H
+   2409/     C12 :                      ;S5   28 - 2F
+   2410/     C12 :  21                  	DB	21H		; 1
+   2411/     C13 :  22                  	DB	22H		; 2
+   2412/     C14 :  23                  	DB	23H		; 3
+   2413/     C15 :  24                  	DB	24H		; 4
+   2414/     C16 :  25                  	DB	25H		; 5
+   2415/     C17 :  26                  	DB	26H		; 6
+   2416/     C18 :  27                  	DB	27H		; 7
+   2417/     C19 :  28                  	DB	28H		; 8
+   2418/     C1A :                      ;S6   30 - 37
+   2419/     C1A :  59                  	DB	59H		; \
+   2420/     C1B :  50                  	DB	50H		; 
+   2421/     C1C :  2A                  	DB	2AH		; -
+   2422/     C1D :  00                  	DB	00H		; SPACE
+   2423/     C1E :  20                  	DB	20H		; 0
+   2424/     C1F :  29                  	DB	29H		; 9
+   2425/     C20 :  2F                  	DB	2FH		; ,
+   2426/     C21 :  2E                  	DB	2EH		; .
+   2427/     C22 :                      ;S7   38 - 3F
+   2428/     C22 :  C8                  	DB	0C8H		; INST.
+   2429/     C23 :  C7                  	DB	0C7H		; DEL.
+   2430/     C24 :  C2                  	DB	0C2H		; CURSOR UP
+   2431/     C25 :  C1                  	DB	0C1H		; CURSOR DOWN
+   2432/     C26 :  C3                  	DB	0C3H		; CURSOR RIGHT
+   2433/     C27 :  C4                  	DB	0C4H		; CURSOR LEFT
+   2434/     C28 :  49                  	DB	49H		; ?
+   2435/     C29 :  2D                  	DB	2DH		; /
+   2436/     C2A :                      ;
+   2437/     C2A :                      ;
+   2438/     C2A :                      ;   KTBL SHIFT ON
+   2439/     C2A :                      ;
+   2440/     C2A :                      KTBLS:
+   2441/     C2A :                      ;S0   00 - 07
+   2442/     C2A :  BF                  	DB	0BFH		; SPARE
+   2443/     C2B :  CA                  	DB	0CAH		; GRAPH
+   2444/     C2C :  1B                  	DB	1BH		; POND
+   2445/     C2D :  C9                  	DB	0C9H		; ALPHA
+   2446/     C2E :  F0                  	DB	0F0H		; NO
+   2447/     C2F :  6A                  	DB	6AH		; +
+   2448/     C30 :  6B                  	DB	6BH		; *
+   2449/     C31 :  CD                  	DB	0CDH		; CR
+   2450/     C32 :                      ;S1   08 - 0F
+   2451/     C32 :  99                  	DB	99H		; y
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 42 - 9.6.1998 9:06:30
+
+
+   2452/     C33 :  9A                  	DB	9AH		; z
+   2453/     C34 :  A4                  	DB	0A4H		; `
+   2454/     C35 :  BC                  	DB	0BCH		; {
+   2455/     C36 :  40                  	DB	40H		; }
+   2456/     C37 :  F0                  	DB	0F0H		; NULL
+   2457/     C38 :  F0                  	DB	0F0H		; NULL
+   2458/     C39 :  F0                  	DB	0F0H		; NULL
+   2459/     C3A :                      ;S2   10 - 17
+   2460/     C3A :  91                  	DB	91H		; q
+   2461/     C3B :  92                  	DB	92H		; r
+   2462/     C3C :  93                  	DB	93H		; s
+   2463/     C3D :  94                  	DB	94H		; t
+   2464/     C3E :  95                  	DB	95H		; u
+   2465/     C3F :  96                  	DB	96H		; v
+   2466/     C40 :  97                  	DB	97H		; w
+   2467/     C41 :  98                  	DB	98H		; x
+   2468/     C42 :                      ;S3   18 - 1F
+   2469/     C42 :  89                  	DB	89H		; i
+   2470/     C43 :  8A                  	DB	8AH		; j
+   2471/     C44 :  8B                  	DB	8BH		; k
+   2472/     C45 :  8C                  	DB	8CH		; l
+   2473/     C46 :  8D                  	DB	8DH		; m
+   2474/     C47 :  8E                  	DB	8EH		; n
+   2475/     C48 :  8F                  	DB	8FH		; o
+   2476/     C49 :  90                  	DB	90H		; p
+   2477/     C4A :                      ;S4   20 - 27
+   2478/     C4A :  81                  	DB	81H		; a
+   2479/     C4B :  82                  	DB	82H		; b
+   2480/     C4C :  83                  	DB	83H		; c
+   2481/     C4D :  84                  	DB	84H		; d
+   2482/     C4E :  85                  	DB	85H		; e
+   2483/     C4F :  86                  	DB	86H		; f
+   2484/     C50 :  87                  	DB	87H		; g
+   2485/     C51 :  88                  	DB	88H		; h
+   2486/     C52 :                      ;S5   28 - 2F
+   2487/     C52 :  61                  	DB	61H		; !
+   2488/     C53 :  62                  	DB	62H		; "
+   2489/     C54 :  63                  	DB	63H		; #
+   2490/     C55 :  64                  	DB	64H		; $
+   2491/     C56 :  65                  	DB	65H		; %
+   2492/     C57 :  66                  	DB	66H		; &
+   2493/     C58 :  67                  	DB	67H		; '
+   2494/     C59 :  68                  	DB	68H		; (
+   2495/     C5A :                      ;S6   30 - 37
+   2496/     C5A :  80                  	DB	80H		; \
+   2497/     C5B :  A5                  	DB	0A5H		; POND MARK
+   2498/     C5C :  2B                  	DB	2BH		; YEN
+   2499/     C5D :  00                  	DB	00H		; SPACE
+   2500/     C5E :  60                  	DB	60H		; �
+   2501/     C5F :  69                  	DB	69H		; )
+   2502/     C60 :  51                  	DB	51H		; <
+   2503/     C61 :  57                  	DB	57H		; >
+   2504/     C62 :                      ;S7   38 - 3F
+   2505/     C62 :  C6                  	DB	0C6H		; CLR
+   2506/     C63 :  C5                  	DB	0C5H		; HOME
+   2507/     C64 :  C2                  	DB	0C2H		; CURSOR UP
+   2508/     C65 :  C1                  	DB	0C1H		; CURSOR DOWN
+   2509/     C66 :  C3                  	DB	0C3H		; CURSOR RIGHT
+   2510/     C67 :  C4                  	DB	0C4H		; CURSOR LEFT
+   2511/     C68 :  5A                  	DB	5AH		;
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 43 - 9.6.1998 9:06:30
+
+
+   2512/     C69 :  45                  	DB	45H		;
+   2513/     C6A :                      ;
+   2514/     C6A :                      ;
+   2515/     C6A :                      ;   GRAPHIC
+   2516/     C6A :                      ;
+   2517/     C6A :                      KTBLGS:
+   2518/     C6A :                      ;S0   00 - 07
+   2519/     C6A :  BF                  	DB	0BFH		; SPARE
+   2520/     C6B :  F0                  	DB	0F0H		; GRAPH BUT NULL
+   2521/     C6C :  E5                  	DB	0E5H		; #
+   2522/     C6D :  C9                  	DB	0C9H		; ALPHA
+   2523/     C6E :  F0                  	DB	0F0H		; NO
+   2524/     C6F :  42                  	DB	42H		; #;
+   2525/     C70 :  B6                  	DB	0B6H		; #:
+   2526/     C71 :  CD                  	DB	0CDH		; CR
+   2527/     C72 :                      ;S1   08 - 0F
+   2528/     C72 :  75                  	DB	75H		; #Y
+   2529/     C73 :  76                  	DB	76H		; #Z
+   2530/     C74 :  B2                  	DB	0B2H		; #@
+   2531/     C75 :  D8                  	DB	0D8H		; #[
+   2532/     C76 :  4E                  	DB	4EH		; #]
+   2533/     C77 :  F0                  	DB	0F0H		; #NULL
+   2534/     C78 :  F0                  	DB	0F0H		; #NULL
+   2535/     C79 :  F0                  	DB	0F0H		; #NULL
+   2536/     C7A :                      ;S2   10 - 17
+   2537/     C7A :  3C                  	DB	3CH		; #Q
+   2538/     C7B :  30                  	DB	30H		; #R
+   2539/     C7C :  44                  	DB	44H		; #S
+   2540/     C7D :  71                  	DB	71H		; #T
+   2541/     C7E :  79                  	DB	79H		; #U
+   2542/     C7F :  DA                  	DB	0DAH		; #V
+   2543/     C80 :  38                  	DB	38H		; #W
+   2544/     C81 :  6D                  	DB	6DH		; #X
+   2545/     C82 :                      ;S3   18 - 1F
+   2546/     C82 :  7D                  	DB	7DH		; #I
+   2547/     C83 :  5C                  	DB	5CH		; #J
+   2548/     C84 :  5B                  	DB	5BH		; #K
+   2549/     C85 :  B4                  	DB	0B4H		; #L
+   2550/     C86 :  1C                  	DB	1CH		; #M
+   2551/     C87 :  32                  	DB	32H		; #N
+   2552/     C88 :  B0                  	DB	0B0H		; #O
+   2553/     C89 :  D6                  	DB	0D6H		; #P
+   2554/     C8A :                      ;S4   20 - 27
+   2555/     C8A :  53                  	DB	53H		; #A
+   2556/     C8B :  6F                  	DB	6FH		; #B
+   2557/     C8C :  DE                  	DB	0DEH		; #C
+   2558/     C8D :  47                  	DB	47H		; #D
+   2559/     C8E :  34                  	DB	34H		; #E
+   2560/     C8F :  4A                  	DB	4AH		; #F
+   2561/     C90 :  4B                  	DB	4BH		; #G
+   2562/     C91 :  72                  	DB	72H		; #H
+   2563/     C92 :                      ;S5   28 - 2F
+   2564/     C92 :  37                  	DB	37H		; #1
+   2565/     C93 :  3E                  	DB	3EH		; #2
+   2566/     C94 :  7F                  	DB	7FH		; #3
+   2567/     C95 :  7B                  	DB	7BH		; #4
+   2568/     C96 :  3A                  	DB	3AH		; #5
+   2569/     C97 :  5E                  	DB	5EH		; #6
+   2570/     C98 :  1F                  	DB	1FH		; #7
+   2571/     C99 :  BD                  	DB	0BDH		; #8
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 44 - 9.6.1998 9:06:30
+
+
+   2572/     C9A :                      ;S6   30 - 37
+   2573/     C9A :  D4                  	DB	0D4H		; #YEN
+   2574/     C9B :  9E                  	DB	9EH		; #+
+   2575/     C9C :  D2                  	DB	0D2H		; #-
+   2576/     C9D :  00                  	DB	00H		; SPACE
+   2577/     C9E :  9C                  	DB	9CH		; #0
+   2578/     C9F :  A1                  	DB	0A1H		; #9
+   2579/     CA0 :  CA                  	DB	0CAH		; #,
+   2580/     CA1 :  B8                  	DB	0B8H		; #.
+   2581/     CA2 :                      ;S7   38 - 3F
+   2582/     CA2 :  C8                  	DB	0C8H		; INST
+   2583/     CA3 :  C7                  	DB	0C7H		; DEL.
+   2584/     CA4 :  C2                  	DB	0C2H		; CURSOR UP
+   2585/     CA5 :  C1                  	DB	0C1H		; CURSOR DOWN
+   2586/     CA6 :  C3                  	DB	0C3H		; CURSOR RIGHT
+   2587/     CA7 :  C4                  	DB	0C4H		; CURSOR LEFT
+   2588/     CA8 :  BA                  	DB	0BAH		; #?
+   2589/     CA9 :  DB                  	DB	0DBH		; #/
+   2590/     CAA :                      ;
+   2591/     CAA :                      ;
+   2592/     CAA :                      ;   CONTROL CODE
+   2593/     CAA :                      ;
+   2594/     CAA :                      KTBLC:
+   2595/     CAA :                      ;S0   00 - 07
+   2596/     CAA :  F0                  	DB	0F0H
+   2597/     CAB :  F0                  	DB	0F0H
+   2598/     CAC :  F0                  	DB	0F0H		; ^
+   2599/     CAD :  F0                  	DB	0F0H
+   2600/     CAE :  F0                  	DB	0F0H
+   2601/     CAF :  F0                  	DB	0F0H
+   2602/     CB0 :  F0                  	DB	0F0H
+   2603/     CB1 :  F0                  	DB	0F0H
+   2604/     CB2 :                      ;S1   08 - 0F
+   2605/     CB2 :  F0                  	DB	0F0H		; ^Y E3
+   2606/     CB3 :  5A                  	DB	5AH		; ^Z E4 (CHECKER)
+   2607/     CB4 :  F0                  	DB	0F0H		; ^@
+   2608/     CB5 :  F0                  	DB	0F0H		; ^[ EB/E5
+   2609/     CB6 :  F0                  	DB	0F0H		; ^] EA/E7 
+   2610/     CB7 :  F0                  	DB	0F0H		; #NULL
+   2611/     CB8 :  F0                  	DB	0F0H		; #NULL
+   2612/     CB9 :  F0                  	DB	0F0H		; #NULL
+   2613/     CBA :                      ;S2   10 - 17
+   2614/     CBA :  C1                  	DB	0C1H		; ^Q
+   2615/     CBB :  C2                  	DB	0C2H		; ^R
+   2616/     CBC :  C3                  	DB	0C3H		; ^S
+   2617/     CBD :  C4                  	DB	0C4H		; ^T
+   2618/     CBE :  C5                  	DB	0C5H		; ^U
+   2619/     CBF :  C6                  	DB	0C6H		; ^V
+   2620/     CC0 :  F0                  	DB	0F0H		; ^W E1
+   2621/     CC1 :  F0                  	DB	0F0H		; ^X E2
+   2622/     CC2 :                      ;S3   18 - 1F
+   2623/     CC2 :  F0                  	DB	0F0H		; ^I F9
+   2624/     CC3 :  F0                  	DB	0F0H		; ^J FA
+   2625/     CC4 :  F0                  	DB	0F0H		; ^K FB
+   2626/     CC5 :  F0                  	DB	0F0H		; ^L FC
+   2627/     CC6 :  F0                  	DB	0F0H		; ^M CD
+   2628/     CC7 :  F0                  	DB	0F0H		; ^N FE
+   2629/     CC8 :  F0                  	DB	0F0H		; ^O FF
+   2630/     CC9 :  F0                  	DB	0F0H		; ^P E0
+   2631/     CCA :                      ;S4   20 - 27
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 45 - 9.6.1998 9:06:30
+
+
+   2632/     CCA :  F0                  	DB	0F0H		; ^A F1
+   2633/     CCB :  F0                  	DB	0F0H		; ^B F2
+   2634/     CCC :  F0                  	DB	0F0H		; ^C F3
+   2635/     CCD :  F0                  	DB	0F0H		; ^D F4
+   2636/     CCE :  F0                  	DB	0F0H		; ^E F5
+   2637/     CCF :  F0                  	DB	0F0H		; ^F F6
+   2638/     CD0 :  F0                  	DB	0F0H		; ^G F7
+   2639/     CD1 :  F0                  	DB	0F0H		; ^H F8
+   2640/     CD2 :                      ;S5   28 - 2F
+   2641/     CD2 :  F0                  	DB	0F0H
+   2642/     CD3 :  F0                  	DB	0F0H
+   2643/     CD4 :  F0                  	DB	0F0H
+   2644/     CD5 :  F0                  	DB	0F0H
+   2645/     CD6 :  F0                  	DB	0F0H
+   2646/     CD7 :  F0                  	DB	0F0H
+   2647/     CD8 :  F0                  	DB	0F0H
+   2648/     CD9 :  F0                  	DB	0F0H
+   2649/     CDA :                      ;S6   30 - 37 (ERROR? 7 VALUES ONLY!!)
+   2650/     CDA :  F0                  	DB	0F0H		; ^YEN E6
+   2651/     CDB :  F0                  	DB	0F0H		; ^    EF
+   2652/     CDC :  F0                  	DB	0F0H
+   2653/     CDD :  F0                  	DB	0F0H
+   2654/     CDE :  F0                  	DB	0F0H
+   2655/     CDF :  F0                  	DB	0F0H		; ^,
+   2656/     CE0 :  F0                  	DB	0F0H
+   2657/     CE1 :                      ;S7   38 - 3F
+   2658/     CE1 :  F0                  	DB	0F0H
+   2659/     CE2 :  F0                  	DB	0F0H
+   2660/     CE3 :  F0                  	DB	0F0H
+   2661/     CE4 :  F0                  	DB	0F0H
+   2662/     CE5 :  F0                  	DB	0F0H
+   2663/     CE6 :  F0                  	DB	0F0H
+   2664/     CE7 :  F0                  	DB	0F0H
+   2665/     CE8 :  F0                  	DB	0F0H		; ^/ EE
+   2666/     CE9 :                      ;
+   2667/     CE9 :                      ;
+   2668/     CE9 :                      ;   KANA
+   2669/     CE9 :                      ;
+   2670/     CE9 :                      KTBLG:
+   2671/     CE9 :                      ;S0   00 - 07
+   2672/     CE9 :  BF                  	DB	0BFH		; SPARE
+   2673/     CEA :  F0                  	DB	0F0H		; GRAPH BUT NULL
+   2674/     CEB :  CF                  	DB	0CFH		; NIKO WH.
+   2675/     CEC :  C9                  	DB	0C9H		; ALPHA
+   2676/     CED :  F0                  	DB	0F0H		; NO
+   2677/     CEE :  B5                  	DB	0B5H		; MO
+   2678/     CEF :  4D                  	DB	4DH		; DAKU TEN
+   2679/     CF0 :  CD                  	DB	0CDH		; CR
+   2680/     CF1 :                      ;S1   08 - 0F
+   2681/     CF1 :  35                  	DB	35H		; HA
+   2682/     CF2 :  77                  	DB	77H		; TA
+   2683/     CF3 :  D7                  	DB	0D7H		; WA
+   2684/     CF4 :  B3                  	DB	0B3H		; YO
+   2685/     CF5 :  B7                  	DB	0B7H		; HANDAKU
+   2686/     CF6 :  F0                  	DB	0F0H
+   2687/     CF7 :  F0                  	DB	0F0H
+   2688/     CF8 :  F0                  	DB	0F0H
+   2689/     CF9 :                      ;S2   10 - 17
+   2690/     CF9 :  7C                  	DB	7CH		; KA
+   2691/     CFA :  70                  	DB	70H		; KE
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 46 - 9.6.1998 9:06:30
+
+
+   2692/     CFB :  41                  	DB	41H		; SHI
+   2693/     CFC :  31                  	DB	31H		; KO
+   2694/     CFD :  39                  	DB	39H		; HI
+   2695/     CFE :  A6                  	DB	0A6H		; TE
+   2696/     CFF :  78                  	DB	78H		; KI
+   2697/     D00 :  DD                  	DB	0DDH		; CHI
+   2698/     D01 :                      ;S3   18 - 1F
+   2699/     D01 :  3D                  	DB	3DH		; FU
+   2700/     D02 :  5D                  	DB	5DH		; MI
+   2701/     D03 :  6C                  	DB	6CH		; MU
+   2702/     D04 :  56                  	DB	56H		; ME
+   2703/     D05 :  1D                  	DB	1DH		; RHI
+   2704/     D06 :  33                  	DB	33H		; RA
+   2705/     D07 :  D5                  	DB	0D5H		; HE
+   2706/     D08 :  B1                  	DB	0B1H		; HO
+   2707/     D09 :                      ;S4   20 - 27
+   2708/     D09 :  46                  	DB	46H		; SA
+   2709/     D0A :  6E                  	DB	6EH		; TO
+   2710/     D0B :  D9                  	DB	0D9H		; THU
+   2711/     D0C :  48                  	DB	48H		; SU
+   2712/     D0D :  74                  	DB	74H		; KU
+   2713/     D0E :  43                  	DB	43H		; SE
+   2714/     D0F :  4C                  	DB	4CH		; SO
+   2715/     D10 :  73                  	DB	73H		; MA
+   2716/     D11 :                      ;S5   28 - 2F
+   2717/     D11 :  3F                  	DB	3FH		; A
+   2718/     D12 :  36                  	DB	36H		; I
+   2719/     D13 :  7E                  	DB	7EH		; U
+   2720/     D14 :  3B                  	DB	3BH		; E
+   2721/     D15 :  7A                  	DB	7AH		; O
+   2722/     D16 :  1E                  	DB	1EH		; NA
+   2723/     D17 :  5F                  	DB	5FH		; NI
+   2724/     D18 :  A2                  	DB	0A2H		; NU
+   2725/     D19 :                      ;S6   30 - 37
+   2726/     D19 :  D3                  	DB	0D3H		; YO
+   2727/     D1A :  9F                  	DB	9FH		; YU
+   2728/     D1B :  D1                  	DB	0D1H		; YA
+   2729/     D1C :  00                  	DB	00H		; SPACE
+   2730/     D1D :  9D                  	DB	9DH		; NO
+   2731/     D1E :  A3                  	DB	0A3H		; NE
+   2732/     D1F :  D0                  	DB	0D0H		; RU
+   2733/     D20 :  B9                  	DB	0B9H		; RE
+   2734/     D21 :                      ;S7   38 - 3F
+   2735/     D21 :  C6                  	DB	0C6H		; ?CLR
+   2736/     D22 :  C5                  	DB	0C5H		; ?HOME
+   2737/     D23 :  C2                  	DB	0C2H		; ?CURSOR UP
+   2738/     D24 :  C1                  	DB	0C1H		; ?CURSOR DOWN
+   2739/     D25 :  C3                  	DB	0C3H		; ?CURSOR RIGHT
+   2740/     D26 :  C4                  	DB	0C4H		; ?CURSOR LEFT 
+   2741/     D27 :  BB                  	DB	0BBH		; DASH
+   2742/     D28 :  BE                  	DB	0BEH		; RO
+   2743/     D29 :                      
+   2744/     D29 :                      ;	MEMORY DUMP COMMAND "D"
+   2745/     D29 :                      
+   2746/     D29 :  CD 3D 01            DUMP:   CALL    HEXIY		; START ADDRESS
+   2747/     D2C :  CD A6 02                    CALL    P4DE
+   2748/     D2F :  E5                          PUSH    HL
+   2749/     D30 :  CD 10 04                    CALL    HLHEX		; END ADDRESS
+   2750/     D33 :  D1                          POP     DE
+   2751/     D34 :  38 52                       JR      C,DUM1		; DATA ERROR THEN
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 47 - 9.6.1998 9:06:30
+
+
+   2752/     D36 :  EB                  L0D36:  EX      DE,HL
+   2753/     D37 :  06 08               DUM3:   LD      B,08H		; DISPLAY 8 BYTES
+   2754/     D39 :  0E 17                       LD      C,23		; CHANGE PRINT BIAS
+   2755/     D3B :  CD FA 05                    CALL    NLPHL		; NEWLINE PRINT
+   2756/     D3E :  CD B1 03            DUM2:   CALL    SPHEX		; SPACE PRINT + ACC PRINT
+   2757/     D41 :  23                          INC     HL
+   2758/     D42 :  F5                          PUSH    AF
+   2759/     D43 :  3A 71 11                    LD      A,(DSPXY)	; DISPLAY POINT
+   2760/     D46 :  81                          ADD     A,C
+   2761/     D47 :  32 71 11                    LD      (DSPXY),A	; X AXIS=X+CREG
+   2762/     D4A :  F1                          POP     AF
+   2763/     D4B :  FE 20                       CP      20H
+   2764/     D4D :  30 02                       JR      NC,L0D51
+   2765/     D4F :  3E 2E                       LD      A,2EH		; "."
+   2766/     D51 :  CD B9 0B            L0D51:  CALL    QADCN		; ASCII TO DISPLAY CODE
+   2767/     D54 :  CD 6C 09                    CALL    PRNT3
+   2768/     D57 :  3A 71 11                    LD      A,(DSPXY)
+   2769/     D5A :  0C                          INC     C
+   2770/     D5B :  91                          SUB     C		; ASCII DISPLAY POSITION
+   2771/     D5C :  32 71 11                    LD      (DSPXY),A
+   2772/     D5F :  0D                          DEC     C
+   2773/     D60 :  0D                          DEC     C
+   2774/     D61 :  0D                          DEC     C
+   2775/     D62 :  E5                          PUSH    HL
+   2776/     D63 :  ED 52                       SBC     HL,DE
+   2777/     D65 :  E1                          POP     HL
+   2778/     D66 :  28 1D                       JR      Z,L0D85
+   2779/     D68 :  3E F8                       LD      A,0F8H
+   2780/     D6A :  32 00 E0                    LD      (KEYPA),A
+   2781/     D6D :  00                          NOP     
+   2782/     D6E :  3A 01 E0                    LD      A,(KEYPB)
+   2783/     D71 :  FE FE                       CP      0FEH		; SHIFT KEY ?
+   2784/     D73 :  20 03                       JR      NZ,L0D78
+   2785/     D75 :  CD A6 0D                    CALL    QBLNK		; 64MSEC DELAY
+   2786/     D78 :  10 C4               L0D78:  DJNZ    DUM2
+   2787/     D7A :  CD CA 08            L0D7A:  CALL    QKEY		; STOP DISPLAY
+   2788/     D7D :  B7                          OR      A
+   2789/     D7E :  28 FA                       JR      Z,L0D7A		; SPACE KEY THEN STOP
+   2790/     D80 :  CD 32 0A                    CALL    QBRK		; BREAK IN ?
+   2791/     D83 :  20 B2                       JR      NZ,DUM3
+   2792/     D85 :  C3 AD 00            L0D85:  JP      ST1		; COMMAND IN !
+   2793/     D88 :                      
+   2794/     D88 :  21 A0 00            DUM1:   LD      HL,160		; 20*8 BYTES
+   2795/     D8B :  19                          ADD     HL,DE
+   2796/     D8C :  18 A8                       JR      L0D36
+   2797/     D8E :                      
+   2798/     D8E :  00                          NOP     
+   2799/     D8F :  00                          NOP     
+   2800/     D90 :  00                          NOP     
+   2801/     D91 :  00                          NOP     
+   2802/     D92 :  00                          NOP     
+   2803/     D93 :  00                          NOP     
+   2804/     D94 :  00                          NOP     
+   2805/     D95 :  00                          NOP     
+   2806/     D96 :  00                          NOP     
+   2807/     D97 :  00                          NOP     
+   2808/     D98 :  00                          NOP     
+   2809/     D99 :  00                          NOP     
+   2810/     D9A :  00                          NOP     
+   2811/     D9B :  00                          NOP     
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 48 - 9.6.1998 9:06:30
+
+
+   2812/     D9C :  00                          NOP     
+   2813/     D9D :  00                          NOP     
+   2814/     D9E :  00                          NOP     
+   2815/     D9F :  00                          NOP     
+   2816/     DA0 :  00                          NOP     
+   2817/     DA1 :  00                          NOP     
+   2818/     DA2 :  00                          NOP     
+   2819/     DA3 :  00                          NOP     
+   2820/     DA4 :  00                          NOP     
+   2821/     DA5 :  00                          NOP     
+   2822/     DA6 :                      
+   2823/     DA6 :                      ;	V-BLANK CHECK
+   2824/     DA6 :                      
+   2825/     DA6 :  F5                  QBLNK:  PUSH    AF
+   2826/     DA7 :  3A 02 E0            L0DA7:  LD      A,(KEYPC)	; V-BLANK
+   2827/     DAA :  07                          RLCA    
+   2828/     DAB :  30 FA                       JR      NC,L0DA7
+   2829/     DAD :  3A 02 E0            L0DAD:  LD      A,(KEYPC)	; 64
+   2830/     DB0 :  07                          RLCA    		;
+   2831/     DB1 :  38 FA                       JR      C,L0DAD		; MSEC
+   2832/     DB3 :  F1                          POP     AF
+   2833/     DB4 :  C9                          RET     
+   2834/     DB5 :                      ;	DISPLAY ON POINTER
+   2835/     DB5 :                      ;	ACC=DISPLAY CODE
+   2836/     DB5 :                      ;	EXCEPT F0H
+   2837/     DB5 :                      
+   2838/     DB5 :  F5                  QDSP:   PUSH    AF
+   2839/     DB6 :  C5                          PUSH    BC
+   2840/     DB7 :  D5                          PUSH    DE
+   2841/     DB8 :  E5                          PUSH    HL
+   2842/     DB9 :  CD B1 0F            DSP01:  CALL    QPONT		; DISPLAY POSITION
+   2843/     DBC :  77                          LD      (HL),A
+   2844/     DBD :  2A 71 11                    LD      HL,(DSPXY)
+   2845/     DC0 :  7D                          LD      A,L
+   2846/     DC1 :  FE 27                       CP      39
+   2847/     DC3 :  20 0B                       JR      NZ,DSP04
+   2848/     DC5 :  CD F3 02                    CALL    PMANG
+   2849/     DC8 :  38 06                       JR      C,DSP04
+   2850/     DCA :  EB                          EX      DE,HL
+   2851/     DCB :  36 01                       LD      (HL),1		; LOGICAL 1ST COLUMN
+   2852/     DCD :  23                          INC     HL
+   2853/     DCE :  36 00                       LD      (HL),0		; LOGICAL 2ND COLUMN
+   2854/     DD0 :  3E C3               DSP04:  LD      A,0C3H		; CURSL
+   2855/     DD2 :  18 0C                       JR      L0DE0
+   2856/     DD4 :                      
+   2857/     DD4 :                      ;	GRAPHIC STATUS CHECK
+   2858/     DD4 :                      
+   2859/     DD4 :  3A 70 11            GRSTAS: LD      A,(KANAF)
+   2860/     DD7 :  FE 01                       CP      01H
+   2861/     DD9 :  3E CA                       LD      A,0CAH
+   2862/     DDB :  C9                          RET     
+   2863/     DDC :                      
+   2864/     DDC :                      ;	DISPLAY CONTROL
+   2865/     DDC :                      ;	ACC=CONTROL CODE
+   2866/     DDC :                      
+   2867/     DDC :  F5                  QDPCT:  PUSH    AF
+   2868/     DDD :  C5                          PUSH    BC
+   2869/     DDE :  D5                          PUSH    DE
+   2870/     DDF :  E5                          PUSH    HL
+   2871/     DE0 :  47                  L0DE0:  LD      B,A
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 49 - 9.6.1998 9:06:30
+
+
+   2872/     DE1 :  E6 F0                       AND     0F0H
+   2873/     DE3 :  FE C0                       CP      0C0H
+   2874/     DE5 :  20 1B                       JR      NZ,CURS5
+   2875/     DE7 :  A8                          XOR     B
+   2876/     DE8 :  07                          RLCA    
+   2877/     DE9 :  4F                          LD      C,A
+   2878/     DEA :  06 00                       LD      B,0
+   2879/     DEC :  21 AA 0E                    LD      HL,CTBL		; PAGE MODE1
+   2880/     DEF :  09                          ADD     HL,BC
+   2881/     DF0 :  5E                          LD      E,(HL)
+   2882/     DF1 :  23                          INC     HL
+   2883/     DF2 :  56                          LD      D,(HL)
+   2884/     DF3 :  2A 71 11                    LD      HL,(DSPXY)
+   2885/     DF6 :  EB                          EX      DE,HL
+   2886/     DF7 :  E9                          JP      (HL)
+   2887/     DF8 :                      
+   2888/     DF8 :  EB                  CURSD:  EX      DE,HL		; LD HL,(DSPXY)
+   2889/     DF9 :  7C                          LD      A,H
+   2890/     DFA :  FE 18                       CP      24
+   2891/     DFC :  28 25                       JR      Z,CURS4
+   2892/     DFE :  24                          INC     H
+   2893/     DFF :                      CURS1:  
+   2894/     DFF :  22 71 11            CURS3:	LD      (DSPXY),HL
+   2895/     E02 :  C3 E5 0E            CURS5:  JP      QRSTR
+   2896/     E05 :                      
+   2897/     E05 :  EB                  CURSU:  EX      DE,HL		; LD HL,(DSPXY)
+   2898/     E06 :  7C                          LD      A,H
+   2899/     E07 :  B7                          OR      A
+   2900/     E08 :  28 F8                       JR      Z,CURS5
+   2901/     E0A :  25                          DEC     H
+   2902/     E0B :  18 F2               CURSU1: JR      CURS3
+   2903/     E0D :                      
+   2904/     E0D :  EB                  CURSR:  EX      DE,HL		; LD HL,(DSPXY)
+   2905/     E0E :  7D                          LD      A,L
+   2906/     E0F :  FE 27                       CP      39
+   2907/     E11 :  30 03                       JR      NC,CURS2
+   2908/     E13 :  2C                          INC     L
+   2909/     E14 :  18 E9                       JR      CURS3
+   2910/     E16 :                      
+   2911/     E16 :  2E 00               CURS2:  LD      L,0
+   2912/     E18 :  24                          INC     H
+   2913/     E19 :  7C                          LD      A,H
+   2914/     E1A :  FE 19                       CP      25
+   2915/     E1C :  38 E1                       JR      C,CURS1
+   2916/     E1E :  26 18                       LD      H,24
+   2917/     E20 :  22 71 11                    LD      (DSPXY),HL
+   2918/     E23 :  18 48               CURS4:  JR      SCROL
+   2919/     E25 :                      
+   2920/     E25 :  EB                  CURSL:  EX      DE,HL		; LD HL,(DSPXY)
+   2921/     E26 :  7D                          LD      A,L
+   2922/     E27 :  B7                          OR      A
+   2923/     E28 :  28 03                       JR      Z,L0E2D
+   2924/     E2A :  2D                          DEC     L
+   2925/     E2B :  18 D2                       JR      CURS3
+   2926/     E2D :                      
+   2927/     E2D :  2E 27               L0E2D:  LD      L,39
+   2928/     E2F :  25                          DEC     H
+   2929/     E30 :  F2 0B 0E                    JP      P,CURSU1
+   2930/     E33 :  26 00                       LD      H,0
+   2931/     E35 :  22 71 11                    LD      (DSPXY),HL
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 50 - 9.6.1998 9:06:30
+
+
+   2932/     E38 :  18 C8                       JR      CURS5
+   2933/     E3A :                      
+   2934/     E3A :  21 73 11            CLRS:   LD      HL,MANG
+   2935/     E3D :  06 1B                       LD      B,27
+   2936/     E3F :  CD D8 0F                    CALL    QCLER
+   2937/     E42 :  21 00 D0                    LD      HL,0D000H	; SCRN TOP
+   2938/     E45 :  CD D4 09                    CALL    NCLR08
+   2939/     E48 :  3E 71                       LD      A,71H		; COLOR DATA
+   2940/     E4A :  CD D5 09                    CALL    NCLR8		; D800H-DFFFH CLEAR
+   2941/     E4D :  21 00 00            HOME:   LD      HL,0		; DSPXY:0 X=0,Y=0
+   2942/     E50 :  18 AD                       JR      CURS3
+   2943/     E52 :                      
+   2944/     E52 :  00                          NOP     
+   2945/     E53 :  00                          NOP     
+   2946/     E54 :  00                          NOP     
+   2947/     E55 :  00                          NOP     
+   2948/     E56 :  00                          NOP     
+   2949/     E57 :  00                          NOP     
+   2950/     E58 :  00                          NOP     
+   2951/     E59 :  00                          NOP     
+   2952/     E5A :                      
+   2953/     E5A :                      ;	CR
+   2954/     E5A :                      
+   2955/     E5A :  CD F3 02            CR:     CALL    PMANG
+   2956/     E5D :  0F                          RRCA    
+   2957/     E5E :  30 B6                       JR      NC,CURS2
+   2958/     E60 :  2E 00                       LD      L,0
+   2959/     E62 :  24                          INC     H
+   2960/     E63 :  FE 18                       CP      24
+   2961/     E65 :  28 03                       JR      Z,CR1
+   2962/     E67 :  24                          INC     H
+   2963/     E68 :  18 95                       JR      CURS1
+   2964/     E6A :                      
+   2965/     E6A :  22 71 11            CR1:    LD      (DSPXY),HL
+   2966/     E6D :                      
+   2967/     E6D :                      ;	SCROLL
+   2968/     E6D :                      
+   2969/     E6D :  01 C0 03            SCROL:  LD      BC,03C0H
+   2970/     E70 :  11 00 D0                    LD      DE,SCRN		; TOP OF $CRT ADDRESS
+   2971/     E73 :  21 28 D0                    LD      HL,SCRN+40	; COLUMN
+   2972/     E76 :  C5                          PUSH    BC		; 1000 STORE
+   2973/     E77 :  ED B0                       LDIR    
+   2974/     E79 :  C1                          POP     BC
+   2975/     E7A :  D5                          PUSH    DE
+   2976/     E7B :  11 00 D8                    LD      DE,SCRN+800H	; COLOR RAM SCROLL
+   2977/     E7E :  21 28 D8                    LD      HL,SCRN+828H	; SCROLL TOP + 40
+   2978/     E81 :  ED B0                       LDIR    
+   2979/     E83 :  06 28                       LD      B,40		; ONE LINE
+   2980/     E85 :  EB                          EX      DE,HL
+   2981/     E86 :  3E 71                       LD      A,71H		; COLOR RAM INITIAL DATA
+   2982/     E88 :  CD DD 0F                    CALL    QDINT
+   2983/     E8B :  E1                          POP     HL
+   2984/     E8C :  06 28                       LD      B,40
+   2985/     E8E :  CD D8 0F                    CALL    QCLER		; LAST LINE CLEAR
+   2986/     E91 :  01 1A 00                    LD      BC,26		; ROW NUMBER+1
+   2987/     E94 :  11 73 11                    LD      DE,MANG		; LOGICAL MANAGEMENT
+   2988/     E97 :  21 74 11                    LD      HL,MANG+1
+   2989/     E9A :  ED B0                       LDIR    
+   2990/     E9C :  36 00                       LD      (HL),0
+   2991/     E9E :  3A 73 11                    LD      A,(MANG)
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 51 - 9.6.1998 9:06:30
+
+
+   2992/     EA1 :  B7                          OR      A
+   2993/     EA2 :  28 41                       JR      Z,QRSTR
+   2994/     EA4 :  21 72 11                    LD      HL,DSPXY+1
+   2995/     EA7 :  35                          DEC     (HL)
+   2996/     EA8 :  18 C3                       JR      SCROL
+   2997/     EAA :                      
+   2998/     EAA :                      ;	CONTROL CODE TABLE
+   2999/     EAA :                      
+   3000/     EAA :  6D 0E               CTBL:	DW	SCROL		; SCROLLING 10H
+   3001/     EAC :  F8 0D               	DW	CURSD		; CURSOR DOWN 11H
+   3002/     EAE :  05 0E               	DW	CURSU		; CURSOR UP 12H
+   3003/     EB0 :  0D 0E               	DW	CURSR		; CURSOR RIGHT 13H
+   3004/     EB2 :  25 0E               	DW	CURSL		; CURSOR LEFT 14H
+   3005/     EB4 :  4D 0E               	DW	HOME		; 15H
+   3006/     EB6 :  3A 0E               	DW	CLRS		; 16H
+   3007/     EB8 :  F8 0E               	DW	DEL		; 17H
+   3008/     EBA :  38 0F               	DW	INST		; 18H
+   3009/     EBC :  E1 0E               	DW	ALPHA		; 19H
+   3010/     EBE :  EE 0E               	DW	KANA		; GRAPHIC 1AH
+   3011/     EC0 :  E5 0E               	DW	QRSTR		; 1BH
+   3012/     EC2 :  E5 0E               	DW	QRSTR		; 1CH
+   3013/     EC4 :  5A 0E               	DW	CR		; 1DH
+   3014/     EC6 :  E5 0E               	DW	QRSTR		; 1EH
+   3015/     EC8 :  E5 0E               	DW	QRSTR		; 1FH
+   3016/     ECA :                      
+   3017/     ECA :                      ;	INST BYPASS
+   3018/     ECA :                      
+   3019/     ECA :  CB DC               INST2:	SET	3,H		; COLOR RAM
+   3020/     ECC :  7E                  	LD	A,(HL)		; FROM
+   3021/     ECD :  23                  	INC	HL
+   3022/     ECE :  77                  	LD      (HL),A		; TO
+   3023/     ECF :  2B                          DEC     HL		; ADDRESS ADJUST
+   3024/     ED0 :  CB 9C                       RES     3,H
+   3025/     ED2 :  ED A8                       LDD     		; CHANGE TRNS.
+   3026/     ED4 :  79                          LD      A,C
+   3027/     ED5 :  B0                          OR      B		; BC=0 ?
+   3028/     ED6 :  20 F2                       JR      NZ,INST2
+   3029/     ED8 :  EB                          EX      DE,HL
+   3030/     ED9 :  36 00                       LD      (HL),0
+   3031/     EDB :  CB DC                       SET     3,H		; COLOR RAM
+   3032/     EDD :  36 71                       LD      (HL),71H
+   3033/     EDF :  18 04                       JR      QRSTR
+   3034/     EE1 :                      
+   3035/     EE1 :  AF                  ALPHA:  XOR     A
+   3036/     EE2 :  32 70 11            ALPH1:  LD      (KANAF),A
+   3037/     EE5 :                      
+   3038/     EE5 :                      ;	RESTORE
+   3039/     EE5 :                      
+   3040/     EE5 :  E1                  QRSTR:  POP     HL
+   3041/     EE6 :  D1                  QRSTR1: POP     DE
+   3042/     EE7 :  C1                          POP     BC
+   3043/     EE8 :  F1                          POP     AF
+   3044/     EE9 :  C9                          RET     
+   3045/     EEA :                      
+   3046/     EEA :  00                          NOP     
+   3047/     EEB :  00                          NOP     
+   3048/     EEC :  00                          NOP     
+   3049/     EED :  00                          NOP     
+   3050/     EEE :                      
+   3051/     EEE :                      ;	MONITOR WORK AREA
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 52 - 9.6.1998 9:06:30
+
+
+   3052/     EEE :                      
+   3053/     EEE :  =D000H              SCRN:	EQU	0D000H
+   3054/     EEE :  =E003H              KANST:	EQU	0E003H		; KANA STATUS REPORT
+   3055/     EEE :                      
+   3056/     EEE :  CD D4 0D            KANA:   CALL    GRSTAS
+   3057/     EF1 :  CA B9 0D                    JP      Z,DSP01		; NOT GRAPH KEY THEN JUMP
+   3058/     EF4 :  3E 01                       LD      A,01H
+   3059/     EF6 :  18 EA                       JR      ALPH1
+   3060/     EF8 :                      
+   3061/     EF8 :  EB                  DEL:    EX      DE,HL		; LD HL,(DSPXY)
+   3062/     EF9 :  7C                          LD      A,H		; HOME ?
+   3063/     EFA :  B5                          OR      L
+   3064/     EFB :  28 E8                       JR      Z,QRSTR
+   3065/     EFD :  7D                          LD      A,L
+   3066/     EFE :  B7                          OR      A
+   3067/     EFF :  20 0D                       JR      NZ,DEL1		; LEFT SIDE ?
+   3068/     F01 :  CD F3 02                    CALL    PMANG
+   3069/     F04 :  38 08                       JR      C,DEL1
+   3070/     F06 :  CD B1 0F                    CALL    QPONT
+   3071/     F09 :  2B                          DEC     HL
+   3072/     F0A :  36 00                       LD      (HL),0
+   3073/     F0C :  18 25                       JR      L0F33		; JUMP CURSL
+   3074/     F0E :                      
+   3075/     F0E :  CD F3 02            DEL1:   CALL    PMANG
+   3076/     F11 :  0F                          RRCA    
+   3077/     F12 :  3E 28                       LD      A,40
+   3078/     F14 :  30 01                       JR      NC,L0F17
+   3079/     F16 :  07                          RLCA    		; ACC=80
+   3080/     F17 :  95                  L0F17:  SUB     L
+   3081/     F18 :  47                          LD      B,A		; TRNS. BYTE
+   3082/     F19 :  CD B1 0F                    CALL    QPONT
+   3083/     F1C :  7E                  DEL2:   LD      A,(HL)		; CHANGE FROM ADDRESS
+   3084/     F1D :  2B                          DEC     HL
+   3085/     F1E :  77                          LD      (HL),A		; TO
+   3086/     F1F :  23                          INC     HL
+   3087/     F20 :  CB DC                       SET     3,H		; COLOR RAM
+   3088/     F22 :  7E                          LD      A,(HL)
+   3089/     F23 :  2B                          DEC     HL
+   3090/     F24 :  77                          LD      (HL),A
+   3091/     F25 :  CB 9C                       RES     3,H		; CHANGE
+   3092/     F27 :  23                          INC     HL
+   3093/     F28 :  23                          INC     HL		; NEXT
+   3094/     F29 :  10 F1                       DJNZ    DEL2
+   3095/     F2B :  2B                          DEC     HL		; ADDRESS ADJUST
+   3096/     F2C :  36 00                       LD      (HL),0
+   3097/     F2E :  CB DC                       SET     3,H
+   3098/     F30 :  21 71 00                    LD      HL,71H		; BLUE + WHITE
+   3099/     F33 :  3E C4               L0F33:  LD      A,0C4H		; JP CURSL
+   3100/     F35 :  C3 E0 0D                    JP      L0DE0
+   3101/     F38 :                      
+   3102/     F38 :  CD F3 02            INST:   CALL    PMANG
+   3103/     F3B :  0F                          RRCA    
+   3104/     F3C :  2E 27                       LD      L,39
+   3105/     F3E :  7D                          LD      A,L
+   3106/     F3F :  30 01                       JR      NC,L0F42
+   3107/     F41 :  24                          INC     H
+   3108/     F42 :  CD B4 0F            L0F42:  CALL    QPNT1
+   3109/     F45 :  E5                          PUSH    HL
+   3110/     F46 :  2A 71 11                    LD      HL,(DSPXY)
+   3111/     F49 :  30 02                       JR      NC,L0F4D
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 53 - 9.6.1998 9:06:30
+
+
+   3112/     F4B :  3E 4F                       LD      A,79
+   3113/     F4D :  95                  L0F4D:  SUB     L
+   3114/     F4E :  06 00                       LD      B,0
+   3115/     F50 :  4F                          LD      C,A
+   3116/     F51 :  D1                          POP     DE
+   3117/     F52 :  28 91                       JR      Z,QRSTR
+   3118/     F54 :  1A                          LD      A,(DE)
+   3119/     F55 :  B7                          OR      A
+   3120/     F56 :  20 8D                       JR      NZ,QRSTR
+   3121/     F58 :  62                          LD      H,D		; HL<-DE
+   3122/     F59 :  6B                          LD      L,E
+   3123/     F5A :  2B                          DEC     HL
+   3124/     F5B :  C3 CA 0E                    JP      INST2		; JUMP NEXT (BYPASS)
+   3125/     F5E :                      
+   3126/     F5E :                      ;	PROGRAM SAVE
+   3127/     F5E :                      ;	COMMAND "S"
+   3128/     F5E :                      
+   3129/     F5E :  CD 3D 01            SAVE:   CALL    HEXIY		; START ADDRESS
+   3130/     F61 :  22 04 11                    LD      (DTADR),HL	; DATA ADDRESS BUFFER
+   3131/     F64 :  44                          LD      B,H
+   3132/     F65 :  4D                          LD      C,L
+   3133/     F66 :  CD A6 02                    CALL    P4DE
+   3134/     F69 :  CD 3D 01                    CALL    HEXIY		; END ADDRESS
+   3135/     F6C :  ED 42                       SBC     HL,BC		; BYTE SIZE
+   3136/     F6E :  23                          INC     HL
+   3137/     F6F :  22 02 11                    LD      (SIZE),HL	; BYTE SIZE BUFFER
+   3138/     F72 :  CD A6 02                    CALL    P4DE
+   3139/     F75 :  CD 3D 01                    CALL    HEXIY		; EXECUTE ADDRESS
+   3140/     F78 :  22 06 11                    LD      (EXADR),HL	; BUFFER
+   3141/     F7B :  CD 09 00                    CALL    NL
+   3142/     F7E :  11 8B 09                    LD      DE,MSGSV	; SAVED FILENAME
+   3143/     F81 :  DF                          RST     18H		; CALL MSGX
+   3144/     F82 :  CD 2F 01                    CALL    BGETL		; FILENAME INPUT
+   3145/     F85 :  CD A6 02                    CALL    P4DE
+   3146/     F88 :  CD A6 02                    CALL    P4DE
+   3147/     F8B :  21 F1 10                    LD      HL,NAME		; NAME BUFFER
+   3148/     F8E :  13                  SAV1:   INC     DE
+   3149/     F8F :  1A                          LD      A,(DE)
+   3150/     F90 :  77                          LD      (HL),A		; FILENAME TRANS.
+   3151/     F91 :  23                          INC     HL
+   3152/     F92 :  FE 0D                       CP      0DH		; END CODE
+   3153/     F94 :  20 F8                       JR      NZ,SAV1
+   3154/     F96 :  3E 01                       LD      A,01H		; ATTRIBUTE: OBJECT CODE
+   3155/     F98 :  32 F0 10                    LD      (ATRB),A
+   3156/     F9B :  CD 36 04                    CALL    QWRI
+   3157/     F9E :  DA 07 01                    JP      C,QER		; WRITE ERROR
+   3158/     FA1 :  CD 75 04                    CALL    QWRD		; DATA
+   3159/     FA4 :  DA 07 01                    JP      C,QER
+   3160/     FA7 :  CD 09 00                    CALL    NL
+   3161/     FAA :  11 42 09                    LD      DE,MSGOK	; OK MESSAGE
+   3162/     FAD :  DF                          RST     18H		; CALL MSGX
+   3163/     FAE :  C3 AD 00                    JP      ST1
+   3164/     FB1 :                      
+   3165/     FB1 :                      ;	COMPUTE POINT ADDRESS
+   3166/     FB1 :                      ;	HL=SCREEN COORDINATE
+   3167/     FB1 :                      ;	EXIT HL=POINT ADDRESS ON SCREEN
+   3168/     FB1 :                      
+   3169/     FB1 :  2A 71 11            QPONT:  LD      HL,(DSPXY)
+   3170/     FB4 :  F5                  QPNT1:  PUSH    AF
+   3171/     FB5 :  C5                          PUSH    BC
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 54 - 9.6.1998 9:06:30
+
+
+   3172/     FB6 :  D5                          PUSH    DE
+   3173/     FB7 :  E5                          PUSH    HL
+   3174/     FB8 :  C1                          POP     BC
+   3175/     FB9 :  11 28 00                    LD      DE,0028H	; 40
+   3176/     FBC :  21 D8 CF                    LD      HL,SCRN-40
+   3177/     FBF :  19                  QPNT2:  ADD     HL,DE
+   3178/     FC0 :  05                          DEC     B
+   3179/     FC1 :  F2 BF 0F                    JP      P,QPNT2
+   3180/     FC4 :  06 00                       LD      B,0
+   3181/     FC6 :  09                          ADD     HL,BC
+   3182/     FC7 :  D1                          POP     DE
+   3183/     FC8 :  C1                          POP     BC
+   3184/     FC9 :  F1                          POP     AF
+   3185/     FCA :  C9                          RET     
+   3186/     FCB :                      
+   3187/     FCB :                      ;	VERIFYING COMMAND "V"
+   3188/     FCB :                      
+   3189/     FCB :  CD 88 05            VRFY:   CALL    QVRFY
+   3190/     FCE :  DA 07 01                    JP      C,QER
+   3191/     FD1 :  11 42 09                    LD      DE,MSGOK
+   3192/     FD4 :  DF                          RST     18H
+   3193/     FD5 :  C3 AD 00                    JP      ST1
+   3194/     FD8 :                      
+   3195/     FD8 :                      ;	CLER
+   3196/     FD8 :                      ;	B=SIZE
+   3197/     FD8 :                      ;	HL=LOW ADDRESS
+   3198/     FD8 :                      
+   3199/     FD8 :  AF                  QCLER:  XOR     A
+   3200/     FD9 :  18 02                       JR      QDINT
+   3201/     FDB :                      
+   3202/     FDB :  3E FF               QCLRFF: LD      A,0FFH
+   3203/     FDD :  77                  QDINT:  LD      (HL),A
+   3204/     FDE :  23                          INC     HL
+   3205/     FDF :  10 FC                       DJNZ    QDINT
+   3206/     FE1 :  C9                          RET     
+   3207/     FE2 :                      
+   3208/     FE2 :                      ;	GAP CHECK
+   3209/     FE2 :                      
+   3210/     FE2 :  C5                  GAPCK:  PUSH    BC
+   3211/     FE3 :  D5                          PUSH    DE
+   3212/     FE4 :  E5                          PUSH    HL
+   3213/     FE5 :  01 01 E0                    LD      BC,KEYPB
+   3214/     FE8 :  11 02 E0                    LD      DE,CSTR
+   3215/     FEB :  26 64               GAPCK1: LD      H,100
+   3216/     FED :  CD 01 06            GAPCK2: CALL    EDGE
+   3217/     FF0 :  38 0B                       JR      C,GAPCK3
+   3218/     FF2 :  CD 4A 0A                    CALL    DLY3		; CALL DLY2*3
+   3219/     FF5 :  1A                          LD      A,(DE)
+   3220/     FF6 :  E6 20                       AND     20H
+   3221/     FF8 :  20 F1                       JR      NZ,GAPCK1
+   3222/     FFA :  25                          DEC     H
+   3223/     FFB :  20 F0                       JR      NZ,GAPCK2
+   3224/     FFD :  C3 9B 06            GAPCK3: JP      RET3
+   3225/    1000 :                      
+   3226/    1000 :                      ;	MONITOR WORK AREA
+   3227/    1000 :                      ;	(MZ700)
+   3228/    1000 :                      
+   3229/    10F0 :                      	ORG	10F0H
+   3230/    10F0 :                      SPV:
+   3231/    10F0 :                      IBUFE:				; TAPE BUFFER (128 BYTES)
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 55 - 9.6.1998 9:06:30
+
+
+   3232/    10F0 :                      ATRB:	DB	?		; ATTRIBUTE
+   3233/    10F1 :                      NAME:	DB	17 DUP ?	; FILE NAME
+   3234/    1102 :                      SIZE:	DB	2 DUP ?		; BYTESIZE
+   3235/    1104 :                      DTADR:	DB	2 DUP ?		; DATA ADDRESS
+   3236/    1106 :                      EXADR:	DB	2 DUP ?		; EXECUTION ADDRESS
+   3237/    1108 :                      COMNT:	DB	104 DUP ?	; COMMENT
+   3238/    1170 :                      KANAF:	DB	?		; KANA FLAG (01=GRAPHIC MODE)
+   3239/    1171 :                      DSPXY:	DB	2 DUP ?		; DISPLAY COORDINATES
+   3240/    1173 :                      MANG:	DB	27 DUP ?	; COLUMN MANAGEMENT
+   3241/    118E :                      FLASH:	DB	?		; FLASHING DATA
+   3242/    118F :                      FLPST:	DB	2 DUP ?		; FLASHING POSITION
+   3243/    1191 :                      FLSST:	DB	?		; FLASHING STATUS
+   3244/    1192 :                      FLSDT:	DB	?		; CURSOR DATA
+   3245/    1193 :                      STRGF:	DB	?		; STRING FLAG
+   3246/    1194 :                      DPRNT:	DB	?		; TAB COUNTER
+   3247/    1195 :                      TMCNT:	DB	2 DUP ?		; TAPE MARK COUNTER
+   3248/    1197 :                      SUMDT:	DB	2 DUP ?		; CHECK SUM DATA
+   3249/    1199 :                      CSMDT:	DB	2 DUP ?		; FOR COMPARE SUM DATA
+   3250/    119B :                      AMPM:	DB	?		; AMPM DATA
+   3251/    119C :                      TIMFG:	DB	?		; TIME FLAG
+   3252/    119D :                      SWRK:	DB	?		; KEY SOUND FLAG
+   3253/    119E :                      TEMPW:	DB	?		; TEMPO WORK
+   3254/    119F :                      ONTYO:	DB	?		; ONTYO WORK
+   3255/    11A0 :                      OCTV:	DB	?		; OCTAVE WORK
+   3256/    11A1 :                      RATIO:	DB	2 DUP ?		; ONPU RATIO
+   3257/    11A3 :                      BUFER:	DB	81 DUP ?	; GET LINE BUFFER
+   3258/    11F4 :                      
+   3259/    11F4 :                      ;	EQU TABLE I/O REPORT
+   3260/    11F4 :                      
+   3261/    11F4 :  =E000H              KEYPA:	EQU	0E000H
+   3262/    11F4 :  =E001H              KEYPB:	EQU	0E001H
+   3263/    11F4 :  =E002H              KEYPC:	EQU	0E002H
+   3264/    11F4 :  =E003H              KEYPF:	EQU	0E003H
+   3265/    11F4 :  =E002H              CSTR:	EQU	0E002H
+   3266/    11F4 :  =E003H              CSTPT:	EQU	0E003H
+   3267/    11F4 :  =E004H              CONT0:	EQU	0E004H
+   3268/    11F4 :  =E005H              CONT1:	EQU	0E005H
+   3269/    11F4 :  =E006H              CONT2:	EQU	0E006H
+   3270/    11F4 :  =E007H              CONTF:	EQU	0E007H
+   3271/    11F4 :  =E008H              SUNDG:	EQU	0E008H
+   3272/    11F4 :  =E008H              TEMP:	EQU	0E008H
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 56 - 9.6.1998 9:06:30
+
+
+  Symboltabelle:
+  --------------
+
+ALPH1 :                         EE2 C | ALPHA :                         EE1 C 
+AMPM :                         119B C | ASC :                           3DA C 
+ATBL :                          A92 C | ATRB :                         10F0 C 
+AUTO3 :                         7ED C | BELL :                           3E C 
+BGETL :                         12F C | BRKEY :                          1E C 
+BUFER :                        11A3 C | CKS1 :                          720 C 
+CKS2 :                          72F C | CKS3 :                          733 C 
+CKSUM :                         71A C | CLEAR :                         9D8 C 
+CLEAR1 :                        9DA C | CLRS :                          E3A C 
+CMY0 :                           5B C | COMNT :                        1108 C 
+CONSTPI :          3.14159265358979 - | CONT0 :                        E004 - 
+CONT1 :                        E005 - | CONT2 :                        E006 - 
+CONTF :                        E007 - | CR :                            E5A C 
+CR1 :                           E6A C | CSMDT :                        1199 C 
+CSTPT :                        E003 - | CSTR :                         E002 - 
+CTBL :                          EAA C | CURS1 :                         DFF C 
+CURS2 :                         E16 C | CURS3 :                         DFF C 
+CURS4 :                         E23 C | CURS5 :                         E02 C 
+CURSD :                         DF8 C | CURSL :                         E25 C 
+CURSR :                         E0D C | CURSU :                         E05 C 
+CURSU1 :                        E0B C | DACN1 :                         BE3 C 
+DACN2 :                         BDF C | DACN3 :                         BE0 C 
+DATE :                     9.6.1998 - | DEL :                           EF8 C 
+DEL1 :                          F0E C | DEL2 :                          F1C C 
+DLY1 :                          759 C | DLY12 :                         996 C 
+DLY2 :                          760 C | DLY3 :                          A4A C 
+DLY4 :                          9A9 C | DMCP :                           6B C 
+DPRNT :                        1194 C | DSP01 :                         DB9 C 
+DSP04 :                         DD0 C | DSPXY :                        1171 C 
+DSWEP :                         830 C | DTADR :                        1104 C 
+DUM1 :                          D88 C | DUM2 :                          D3E C 
+DUM3 :                          D37 C | DUMP :                          D29 C 
+EDG1 :                          607 C | EDG2 :                          613 C 
+EDGE :                          601 C | EXADR :                        1106 C 
+FALSE :                           0 - | FD :                             FF C 
+FD1 :                           106 C | FD2 :                           102 C 
+FLAS1 :                         97B C | FLAS2 :                         9EF C 
+FLASH :                        118E C | FLKEY :                         57E C 
+FLPST :                        118F C | FLSDT :                        1192 C 
+FLSST :                        1191 C | GAP :                           77A C 
+GAP1 :                          78E C | GAP2 :                          796 C 
+GAP3 :                          79C C | GAPCK :                         FE2 C 
+GAPCK1 :                        FEB C | GAPCK2 :                        FED C 
+GAPCK3 :                        FFD C | GETKY :                          1B C 
+GETL :                            3 C | GETL1 :                         7EA C 
+GETL2 :                         818 C | GETL3 :                         85B C 
+GETL5 :                         81D C | GETL6 :                         865 C 
+GETLA :                         82B C | GETLB :                         863 C 
+GETLC :                         822 C | GETLR :                         87E C 
+GETLU :                         876 C | GETLZ :                         86C C 
+GOTO :                           F3 C | GRSTAS :                        DD4 C 
+HASFPU :                          0 - | HASPMMU :                         0 - 
+HEX :                           3F9 C | HEXIY :                         13D C 
+HEXJ :                          3E5 C | HLHEX :                         410 C 
+HOME :                          E4D C | IBUFE :                        10F0 C 
+INMAXMODE :                       0 - | INST :                          F38 C 
+INST2 :                         ECA C | INSUPMODE :                       0 - 
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 57 - 9.6.1998 9:06:30
+
+
+KANA :                          EEE C | KANAF :                        1170 C 
+KANST :                        E003 - | KEYPA :                        E000 - 
+KEYPB :                        E001 - | KEYPC :                        E002 - 
+KEYPF :                        E003 - | KSL1 :                          9B7 C 
+KSL2 :                          9BC C | KTBL :                          BEA C 
+KTBLC :                         CAA C | KTBLG :                         CE9 C 
+KTBLGS :                        C6A C | KTBLS :                         C2A C 
+L010F :                         10F C | L01F5 :                         1F5 C 
+L0207 :                         207 C | L0220 :                         220 C 
+L0239 :                         239 C | L023F :                         23F C 
+L0255 :                         255 C | L025A :                         25A C 
+L02D5 :                         2D5 C | L02DB :                         2DB C 
+L0363 :                         363 C | L0378 :                         378 C 
+L041D :                         41D C | L0434 :                         434 C 
+L047D :                         47D C | L04C2 :                         4C2 C 
+L04C4 :                         4C4 C | L0563 :                         563 C 
+L060E :                         60E C | L061A :                         61A C 
+L066C :                         66C C | L06AD :                         6AD C 
+L06B4 :                         6B4 C | L071C :                         71C C 
+L0725 :                         725 C | L0737 :                         737 C 
+L0739 :                         739 C | L075B :                         75B C 
+L0762 :                         762 C | L08F7 :                         8F7 C 
+L092C :                         92C C | L0968 :                         968 C 
+L0999 :                         999 C | L09AB :                         9AB C 
+L0A89 :                         A89 C | L0BA0 :                         BA0 C 
+L0BB1 :                         BB1 C | L0D36 :                         D36 C 
+L0D51 :                         D51 C | L0D78 :                         D78 C 
+L0D7A :                         D7A C | L0D85 :                         D85 C 
+L0DA7 :                         DA7 C | L0DAD :                         DAD C 
+L0DE0 :                         DE0 C | L0E2D :                         E2D C 
+L0F17 :                         F17 C | L0F33 :                         F33 C 
+L0F42 :                         F42 C | L0F4D :                         F4D C 
+L2HEX :                         41F C | LETNL :                           6 C 
+LISTON :                          1 - | LLPT :                          470 C 
+LOA0 :                          116 C | LOAD :                          111 C 
+LONG :                          A1A C | LPRNT :                         18F C 
+MACEXP :                          1 - | MANG :                         1173 C 
+MCOR :                          7A8 C | MCR1 :                          7AB C 
+MCR2 :                          7D4 C | MCR3 :                          7D7 C 
+MELDY :                          30 C | MLD1 :                          1D1 C 
+MLD2 :                          205 C | MLD3 :                          20D C 
+MLD4 :                          211 C | MLD5 :                          214 C 
+MLDS1 :                         2C4 C | MLDSP :                         2BE C 
+MLDST :                         2AB C | MNTBL :                         284 C 
+MOMCPU :                         80 - | MONIT :                           0 C 
+MOT1 :                          6A4 C | MOT2 :                          6AB C 
+MOT4 :                          6B9 C | MOT5 :                          6D8 C 
+MOT7 :                          6B7 C | MOT8 :                          6D0 C 
+MOT9 :                          6D7 C | MOTOR :                         69F C 
+MSG :                            15 C | MSG1 :                          896 C 
+MSGE1 :                         147 C | MSGN1 :                         3FB C 
+MSGN2 :                         3FD C | MSGN3 :                         402 C 
+MSGN7 :                         467 C | MSGOK :                         942 C 
+MSGQ2 :                         9A0 C | MSGQ3 :                         6E7 C 
+MSGSV :                         98B C | MSGX :                           18 C 
+MSGX1 :                         8A4 C | MSGX2 :                         8A7 C 
+MST1 :                          705 C | MST3 :                          717 C 
+MSTA :                           44 C | MSTOP :                         700 C 
+MSTP :                           47 C | MTBL :                          26C C 
+NAME :                         10F1 C | NBRK :                          8B8 C 
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 58 - 9.6.1998 9:06:30
+
+
+NCLR08 :                        9D4 C | NCLR8 :                         9D5 C 
+NL :                              9 C | NLPHL :                         5FA C 
+NOADD :                         3E2 C | OCTV :                         11A0 C 
+ONP1 :                          21F C | ONP2 :                          22C C 
+ONP3 :                          265 C | ONPU :                          21C C 
+ONTYO :                        119F C | OPTBL :                         29C C 
+P4DE :                          2A6 C | PADDING :                         1 - 
+PEN :                           18B C | PLOT :                          184 C 
+PLPT :                          176 C | PMANG :                         2F3 C 
+PMSG :                          1A5 C | PMSG1 :                         1A8 C 
+PPLPT :                         17B C | PRNT :                           12 C 
+PRNT2 :                         967 C | PRNT3 :                         96C C 
+PRNT4 :                         96F C | PRNT5 :                         959 C 
+PRNTS :                           C C | PRNTT :                           F C 
+PRTHL :                         3BA C | PRTHX :                         3C3 C 
+PTEST :                         155 C | PTRN :                          180 C 
+PTST0 :                         15A C | PTST1 :                         170 C 
+QADCN :                         BB9 C | QBEL :                          577 C 
+QBELD :                         352 C | QBLNK :                         DA6 C 
+QBRK :                          A32 C | QBRK1 :                         A48 C 
+QBRK2 :                         980 C | QBRK3 :                         986 C 
+QCLER :                         FD8 C | QCLRFF :                        FDB C 
+QDACN :                         BCE C | QDINT :                         FDD C 
+QDPCT :                         DDC C | QDSP :                          DB5 C 
+QER :                           107 C | QFLAS :                         9FF C 
+QFLS :                          9E3 C | QGET :                          8BD C 
+QGETL :                         7E6 C | QKEY :                          8CA C 
+QKY1 :                          8D6 C | QKY2 :                          8DA C 
+QKY5 :                          8FA C | QKY55 :                         8FB C 
+QKYGRP :                        8FE C | QKYGRS :                        909 C 
+QKYSM :                         8B3 C | QLOAD :                         5F0 C 
+QLTNL :                         90E C | QMLDY :                         1C7 C 
+QMODE :                         73E C | QMSG :                          893 C 
+QMSGX :                         8A1 C | QNL :                           918 C 
+QPNT1 :                         FB4 C | QPNT2 :                         FBF C 
+QPONT :                         FB1 C | QPRNT :                         935 C 
+QPRT :                          946 C | QPRTS :                         920 C 
+QPRTT :                         924 C | QQKEY :                         9B3 C 
+QRDD :                          4F8 C | QRDI :                          4D8 C 
+QRSTR :                         EE5 C | QRSTR1 :                        EE6 C 
+QSAVE :                         B92 C | QSWEP :                         A50 C 
+QTEMP :                         2E5 C | QTMR1 :                         375 C 
+QTMR2 :                         37F C | QTMRD :                         358 C 
+QTMS1 :                         331 C | QTMS2 :                         344 C 
+QTMST :                         308 C | QVRFY :                         588 C 
+QWRD :                          475 C | QWRI :                          436 C 
+RATIO :                        11A1 C | RBY1 :                          630 C 
+RBY2 :                          649 C | RBY3 :                          654 C 
+RBYTE :                         624 C | RD1 :                           4E6 C 
+RDA :                           1B6 C | RDDAT :                          2A C 
+RDINF :                          27 C | RELAXED :                         0 - 
+RET1 :                          4D2 C | RET2 :                          554 C 
+RET3 :                          69B C | RTAPE :                         50E C 
+RTP1 :                          513 C | RTP2 :                          519 C 
+RTP3 :                          532 C | RTP4 :                          554 C 
+RTP5 :                          565 C | RTP6 :                          572 C 
+RTP7 :                          56E C | RTP8 :                          553 C 
+RTP9 :                          574 C | RYTHM :                         2C8 C 
+SAV1 :                          F8E C | SAVE :                          F5E C 
+SCRN :                         D000 - | SCROL :                         E6D C 
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 59 - 9.6.1998 9:06:30
+
+
+SG :                             F7 C | SHORT :                         A01 C 
+SIZE :                         1102 C | SLPT :                          3D5 C 
+SPHEX :                         3B1 C | SPV :                          10F0 C 
+SS :                             A2 C | ST0 :                            70 C 
+ST1 :                            AD C | ST2 :                            BB C 
+START :                          4A C | STRGF :                        1193 C 
+SUMDT :                        1197 C | SUNDG :                        E008 - 
+SV0 :                           BA2 C | SV1 :                           BB5 C 
+SWEP0 :                         A66 C | SWEP01 :                        A64 C 
+SWEP2 :                         A7F C | SWEP3 :                         A77 C 
+SWEP6 :                         A5F C | SWEP9 :                         A73 C 
+SWRK :                         119D C | TEMP :                         E008 - 
+TEMPW :                        119E C | TIME :                      9:06:28 - 
+TIMFG :                        119C C | TIMIN :                         38D C 
+TIMRD :                          3B C | TIMST :                          33 C 
+TM1 :                           675 C | TM2 :                           678 C 
+TM3 :                           688 C | TM4 :                           69B C 
+TMARK :                         65B C | TMCNT :                        1195 C 
+TRUE :                            1 - | TVF1 :                          5B2 C 
+TVF2 :                          5B8 C | TVF3 :                          5CC C 
+TVRFY :                         5AD C | VERFY :                          2D C 
+VERSION :                      1408 - | VRFY :                          FCB C 
+VRNS :                          BC5 C | WBY1 :                          76D C 
+WBYTE :                         767 C | WRDAT :                          24 C 
+WRI1 :                          444 C | WRI2 :                          45E C 
+WRI3 :                          464 C | WRINF :                          21 C 
+WTAP1 :                         494 C | WTAP2 :                         4A5 C 
+WTAP3 :                         4D2 C | WTAPE :                         48A C 
+XTEMP :                          41 C 
+
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 60 - 9.6.1998 9:06:30
+
+
+
+  Querverweisliste:
+  -----------------
+
+Symbol ALPH1 (=EE2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3036):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3059    
+
+Symbol ALPHA (=EE1,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3035):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3009    
+
+Symbol AMPM (=119B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3250):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    531      610      615      638    
+
+Symbol ASC (=3DA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/706):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    689      692    
+
+Symbol ATBL (=A92,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2015):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2322     2341    
+
+Symbol ATRB (=10F0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3232):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3155    
+
+Symbol BGETL (=12F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/163):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1413     3144    
+
+Symbol BRKEY (=1E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/18):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    270    
+
+Symbol BUFER (=11A3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3257):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     80      165    
+
+Symbol CKS1 (=720,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1303):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1324    
+
+Symbol CKS2 (=72F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1314):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1305    
+
+Symbol CKS3 (=733,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1317):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1320    
+
+Symbol CKSUM (=71A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1299):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    797     1040    
+
+Symbol CLEAR1 (=9DA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1848):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1853    
+
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 61 - 9.6.1998 9:06:30
+
+
+Symbol CLRS (=E3A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2934):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3006    
+
+Symbol CMY0 (=5B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/42):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     95    
+
+Symbol CONT0 (=E004,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3267):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    450    
+
+Symbol CONT2 (=E006,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3269):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    621    
+
+Symbol CONTF (=E007,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3270):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    458      540      595      642    
+
+Symbol CR (=E5A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2955):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3013    
+
+Symbol CR1 (=E6A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2965):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2961    
+
+Symbol CSMDT (=1199,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3249):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1084     1308    
+
+Symbol CSTPT (=E003,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3266):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1248     1287     1289     1888     1892     1900     1903    
+
+Symbol CSTR (=E002,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3265):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    945     1061     1153     1199     1234     1264     1283     3214    
+
+Symbol CTBL (=EAA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3000):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2879    
+
+Symbol CURS1 (=DFF,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2893):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2915     2963    
+
+Symbol CURS2 (=E16,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2911):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2907     2957    
+
+Symbol CURS3 (=DFF,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2894):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2902     2909     2925     2942    
+
+Symbol CURS4 (=E23,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2918):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2891    
+
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 62 - 9.6.1998 9:06:30
+
+
+Symbol CURS5 (=E02,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2895):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2874     2900     2932    
+
+Symbol CURSD (=DF8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2888):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3001    
+
+Symbol CURSL (=E25,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2920):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3004    
+
+Symbol CURSR (=E0D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2904):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3003    
+
+Symbol CURSU (=E05,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2897):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3002    
+
+Symbol CURSU1 (=E0B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2902):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2929    
+
+Symbol DACN1 (=BE3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2353):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2346    
+
+Symbol DACN2 (=BDF,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2348):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2357    
+
+Symbol DACN3 (=BE0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2349):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2327    
+
+Symbol DEL (=EF8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3061):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3007    
+
+Symbol DEL1 (=F0E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3075):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3067     3069    
+
+Symbol DEL2 (=F1C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3083):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3094    
+
+Symbol DLY1 (=759,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1354):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1889     1890     1893     1894    
+
+Symbol DLY12 (=996,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1795):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1238     1496     1830    
+
+Symbol DLY3 (=A4A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1946):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    948     1064     1156     1203     1211     1797     3218    
+
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 63 - 9.6.1998 9:06:30
+
+
+Symbol DLY4 (=9A9,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1808):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1901     1904    
+
+Symbol DMCP (=6B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/49):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     44    
+
+Symbol DPRNT (=1194,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3246):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1692     1699     1714     1762     1766    
+
+Symbol DSP01 (=DB9,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2842):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3057    
+
+Symbol DSP04 (=DD0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2854):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2847     2849    
+
+Symbol DSPXY (=1171,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3239):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    519     2759     2761     2768     2771     2844     2884     2894    
+   2917     2931     2965     2994     3110     3169    
+
+Symbol DSWEP (=830,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1496):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1647    
+
+Symbol DTADR (=1104,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3235):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    835      927     1034     3130    
+
+Symbol DUM1 (=D88,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2794):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2751    
+
+Symbol DUM2 (=D3E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2756):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2786    
+
+Symbol DUM3 (=D37,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2753):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2791    
+
+Symbol DUMP (=D29,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2746):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    105    
+
+Symbol EDG1 (=607,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1119):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1127    
+
+Symbol EDG2 (=613,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1128):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1136    
+
+Symbol EDGE (=601,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1116):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    946     1062     1154     1171     1201     1209     1217     3216    
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 64 - 9.6.1998 9:06:30
+
+
+
+Symbol EXADR (=1106,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3236):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    152     3140    
+
+Symbol FD (=FF,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/127):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     91    
+
+Symbol FD2 (=102,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/128):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     75    
+
+Symbol FLAS1 (=97B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1775):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1864    
+
+Symbol FLAS2 (=9EF,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1866):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1776    
+
+Symbol FLASH (=118E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3241):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1099     1775     2303    
+
+Symbol FLKEY (=57E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1017):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1825     1827    
+
+Symbol FLSDT (=1192,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3244):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1865     2291    
+
+Symbol GAP (=77A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1381):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    810    
+
+Symbol GAP1 (=78E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1390):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1387     1394    
+
+Symbol GAP2 (=796,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1395):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1397    
+
+Symbol GAP3 (=79C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1398):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1400    
+
+Symbol GAPCK (=FE2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3210):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    995     1188    
+
+Symbol GAPCK1 (=FEB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3215):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3221    
+
+Symbol GAPCK2 (=FED,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3216):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3223    
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 65 - 9.6.1998 9:06:30
+
+
+
+Symbol GAPCK3 (=FFD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3224):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3217    
+
+Symbol GETL (=3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/9):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     81      166    
+
+Symbol GETL1 (=7EA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1449):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1474     1477    
+
+Symbol GETL2 (=818,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1473):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1461     1467    
+
+Symbol GETL3 (=85B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1537):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1463    
+
+Symbol GETL5 (=81D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1476):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1469     1472    
+
+Symbol GETL6 (=865,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1542):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1491    
+
+Symbol GETLA (=82B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1490):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1539    
+
+Symbol GETLB (=863,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1541):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1492    
+
+Symbol GETLC (=822,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1481):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1465    
+
+Symbol GETLR (=87E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1564):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1486    
+
+Symbol GETLU (=876,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1553):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1560    
+
+Symbol GETLZ (=86C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1546):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1551    
+
+Symbol GOTO (=F3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/114):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     87    
+
+Symbol GRSTAS (=DD4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2859):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3056    
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 66 - 9.6.1998 9:06:30
+
+
+
+Symbol HEX (=3F9,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/735):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    772      781    
+
+Symbol HEXIY (=13D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/176):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    114     1409     2746     3129     3134     3139    
+
+Symbol HEXJ (=3E5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/718):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    735    
+
+Symbol HLHEX (=410,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/754):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    178     1414     2749    
+
+Symbol HOME (=E4D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2941):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3005    
+
+Symbol IBUFE (=10F0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3231):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    795      909    
+
+Symbol INST (=F38,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3102):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3008    
+
+Symbol INST2 (=ECA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3019):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3028     3124    
+
+Symbol KANA (=EEE,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3056):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3010    
+
+Symbol KANAF (=1170,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3238):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1456     1665     2293     2859     3036    
+
+Symbol KEYPA (=E000,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3261):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    469      852     1117     1928     1981     2307     2780    
+
+Symbol KEYPB (=E001,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3262):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    855      944     1060     1152     1198     1930     1991     2782    
+   3213    
+
+Symbol KEYPC (=E002,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3263):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1861     2826     2829    
+
+Symbol KEYPF (=E003,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3264):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1328    
+
+Symbol KSL1 (=9B7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1825):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 67 - 9.6.1998 9:06:30
+
+
+   1826    
+
+Symbol KSL2 (=9BC,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1827):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1828     1835    
+
+Symbol KTBL (=BEA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2363):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1657    
+
+Symbol KTBLC (=CAA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2594):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1674    
+
+Symbol KTBLG (=CE9,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2670):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1681    
+
+Symbol KTBLGS (=C6A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2517):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1686    
+
+Symbol KTBLS (=C2A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2440):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1614    
+
+Symbol L010F (=10F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/139):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    155      169      179    
+
+Symbol L01F5 (=1F5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/304):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    301    
+
+Symbol L0207 (=207,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/313):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    318    
+
+Symbol L0220 (=220,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/333):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    338    
+
+Symbol L0239 (=239,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/354):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    357    
+
+Symbol L023F (=23F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/359):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    352      355    
+
+Symbol L0255 (=255,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/373):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    369    
+
+Symbol L025A (=25A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/377):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    371    
+
+Symbol L02D5 (=2D5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/478):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 68 - 9.6.1998 9:06:30
+
+
+    474      480      484    
+
+Symbol L02DB (=2DB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/481):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    483    
+
+Symbol L0378 (=378,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/615):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    630    
+
+Symbol L041D (=41D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/761):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    756      759    
+
+Symbol L0434 (=434,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/784):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    773      782    
+
+Symbol L04C2 (=4C2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/878):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    874    
+
+Symbol L04C4 (=4C4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/879):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    881    
+
+Symbol L0563 (=563,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/989):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    987    
+
+Symbol L060E (=60E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1125):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1121    
+
+Symbol L061A (=61A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1134):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1130    
+
+Symbol L066C (=66C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1197):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1195    
+
+Symbol L06AD (=6AD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1238):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1243    
+
+Symbol L06B4 (=6B4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1243):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1239    
+
+Symbol L0737 (=737,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1320):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1318    
+
+Symbol L075B (=75B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1355):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1356    
+
+Symbol L0762 (=762,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1360):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 69 - 9.6.1998 9:06:30
+
+
+   1361     1947    
+
+Symbol L08F7 (=8F7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1674):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1664    
+
+Symbol L092C (=92C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1717):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1719    
+
+Symbol L0968 (=968,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1762):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1769     1771    
+
+Symbol L0999 (=999,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1797):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1798    
+
+Symbol L09AB (=9AB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1809):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1810    
+
+Symbol L0A89 (=A89,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2004):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2006    
+
+Symbol L0BA0 (=BA0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2298):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2295    
+
+Symbol L0D36 (=D36,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2752):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2796    
+
+Symbol L0D51 (=D51,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2766):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2764    
+
+Symbol L0D78 (=D78,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2786):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2784    
+
+Symbol L0D7A (=D7A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2787):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2789    
+
+Symbol L0D85 (=D85,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2792):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2778    
+
+Symbol L0DA7 (=DA7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2826):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2828    
+
+Symbol L0DAD (=DAD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2829):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2831    
+
+Symbol L0DE0 (=DE0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2871):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 70 - 9.6.1998 9:06:30
+
+
+   2855     3100    
+
+Symbol L0E2D (=E2D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2927):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2923    
+
+Symbol L0F17 (=F17,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3080):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3078    
+
+Symbol L0F33 (=F33,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3099):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3073    
+
+Symbol L0F42 (=F42,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3108):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3106    
+
+Symbol L0F4D (=F4D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3113):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3111    
+
+Symbol L2HEX (=41F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/769):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
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+
+Symbol LLPT (=470,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/818):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    212    
+
+Symbol LOAD (=111,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/143):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     89    
+
+Symbol LONG (=A1A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1898):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    872     1368     1370     1395     1401    
+
+Symbol LPRNT (=18F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/231):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    222      252    
+
+Symbol MANG (=1173,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3240):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    508     2934     2987     2988     2991    
+
+Symbol MCOR (=7A8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1409):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     99    
+
+Symbol MCR1 (=7AB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1410):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1419     1421     1427     1430     1434    
+
+Symbol MCR2 (=7D4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1429):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1425    
+
+Symbol MCR3 (=7D7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1432):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 71 - 9.6.1998 9:06:30
+
+
+   1415    
+
+Symbol MLD1 (=1D1,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/286):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    305      310      315    
+
+Symbol MLD2 (=205,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/312):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    292      294    
+
+Symbol MLD3 (=20D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/317):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    296      298    
+
+Symbol MLD4 (=211,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/320):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    288      290    
+
+Symbol MLD5 (=214,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/321):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    307    
+
+Symbol MLDS1 (=2C4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/460):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    455    
+
+Symbol MLDSP (=2BE,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/457):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     33       66      322      447    
+
+Symbol MLDST (=2AB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/444):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     32      308    
+
+Symbol MNTBL (=284,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/407):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    302    
+
+Symbol MOT1 (=6A4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1234):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1252    
+
+Symbol MOT2 (=6AB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1237):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1266    
+
+Symbol MOT4 (=6B9,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1247):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1236    
+
+Symbol MOT5 (=6D8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1264):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1268    
+
+Symbol MOT7 (=6B7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1245):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1270    
+
+Symbol MOT8 (=6D0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1260):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 72 - 9.6.1998 9:06:30
+
+
+   1256    
+
+Symbol MOT9 (=6D7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1263):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1258    
+
+Symbol MOTOR (=69F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1230):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    798      910     1041     1241    
+
+Symbol MSG1 (=896,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1592):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1597    
+
+Symbol MSGE1 (=147,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/182):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    137    
+
+Symbol MSGN1 (=3FB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/739):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1257    
+
+Symbol MSGN2 (=3FD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/740):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1262    
+
+Symbol MSGN3 (=402,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/741):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1260    
+
+Symbol MSGN7 (=467,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/814):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    805    
+
+Symbol MSGOK (=942,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1737):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3161     3191    
+
+Symbol MSGQ2 (=9A0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1804):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    146    
+
+Symbol MSGQ3 (=6E7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1274):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     68    
+
+Symbol MSGSV (=98B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1791):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3142    
+
+Symbol MSGX1 (=8A4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1604):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1610    
+
+Symbol MSGX2 (=8A7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1606):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1594    
+
+Symbol MST1 (=705,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1283):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 73 - 9.6.1998 9:06:30
+
+
+   1290    
+
+Symbol MST3 (=717,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1291):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1285    
+
+Symbol MSTOP (=700,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1279):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    983    
+
+Symbol MTBL (=26C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/391):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    300    
+
+Symbol NAME (=10F1,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3233):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     53      148      807     3147    
+
+Symbol NBRK (=8B8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1619):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1660    
+
+Symbol NCLR08 (=9D4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1844):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2938    
+
+Symbol NCLR8 (=9D5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1845):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     59     2940    
+
+Symbol NL (=9,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/11):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     67       77      145      803     1107     1253     3141     3160    
+
+Symbol NLPHL (=5FA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1107):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1410     2755    
+
+Symbol NOADD (=3E2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/710):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    708    
+
+Symbol OCTV (=11A0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3255):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    284      313      353      360    
+
+Symbol ONP2 (=22C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/344):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    334    
+
+Symbol ONP3 (=265,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/384):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    385    
+
+Symbol ONPU (=21C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/330):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    304    
+
+Symbol OPTBL (=29C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/423):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 74 - 9.6.1998 9:06:30
+
+
+    377    
+
+Symbol P4DE (=2A6,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/436):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1416     2747     3133     3138     3145     3146    
+
+Symbol PEN (=18B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/225):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    204    
+
+Symbol PLOT (=184,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/221):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    206      219      226    
+
+Symbol PLPT (=176,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/212):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    200    
+
+Symbol PMANG (=2F3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/508):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1537     2848     2955     3068     3075     3102    
+
+Symbol PMSG (=1A5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/248):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    209    
+
+Symbol PMSG1 (=1A8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/251):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    256    
+
+Symbol PPLPT (=17B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/215):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    202    
+
+Symbol PRNT (=12,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/14):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     56       79      690      693    
+
+Symbol PRNT2 (=967,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1761):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1758    
+
+Symbol PRNT3 (=96C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1765):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1608     1751     1753     2767    
+
+Symbol PRNT4 (=96F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1766):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1756    
+
+Symbol PRNT5 (=959,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1754):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1694    
+
+Symbol PRNTS (=C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/12):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1713    
+
+Symbol PRTHL (=3BA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/674):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 75 - 9.6.1998 9:06:30
+
+
+   1108    
+
+Symbol PRTHX (=3C3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/684):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    668      675      677    
+
+Symbol PTEST (=155,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/194):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     97    
+
+Symbol PTRN (=180,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/218):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    208    
+
+Symbol PTST0 (=15A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/197):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    223    
+
+Symbol PTST1 (=170,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/209):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    196      213      216    
+
+Symbol QADCN (=BB9,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2320):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1607     1744     2766    
+
+Symbol QBEL (=577,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1007):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     30       70     1454    
+
+Symbol QBELD (=352,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/583):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1008    
+
+Symbol QBLNK (=DA6,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2825):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2785    
+
+Symbol QBRK (=A32,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1927):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     18       38     1267     1969     2790    
+
+Symbol QBRK1 (=A48,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1941):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1936    
+
+Symbol QBRK2 (=980,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1781):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1933    
+
+Symbol QBRK3 (=986,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1786):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1782    
+
+Symbol QCLER (=FD8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3199):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     54     2936     2985    
+
+Symbol QDACN (=BCE,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2338):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 76 - 9.6.1998 9:06:30
+
+
+   1547     1631    
+
+Symbol QDINT (=FDD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3203):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2982     3200     3205    
+
+Symbol QDPCT (=DDC,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2867):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1476     1754    
+
+Symbol QDSP (=DB5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2838):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1473     1765    
+
+Symbol QER (=107,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/135):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    144      151     3157     3159     3190    
+
+Symbol QFLAS (=9FF,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1882):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1017    
+
+Symbol QFLS (=9E3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1859):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1882    
+
+Symbol QGET (=8BD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1627):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     17    
+
+Symbol QGETL (=7E6,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1445):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+      9    
+
+Symbol QKEY (=8CA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1644):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1018     1627     1831     2787    
+
+Symbol QKY1 (=8D6,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1652):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1621     1677    
+
+Symbol QKY2 (=8DA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1657):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1650    
+
+Symbol QKY5 (=8FA,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1675):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1615     1672     1687    
+
+Symbol QKY55 (=8FB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1676):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1684    
+
+Symbol QKYGRP (=8FE,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1679):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1667    
+
+Symbol QKYGRS (=909,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1686):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 77 - 9.6.1998 9:06:30
+
+
+   1680    
+
+Symbol QKYSM (=8B3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1614):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1671    
+
+Symbol QLOAD (=5F0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1098):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1838    
+
+Symbol QLTNL (=90E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1691):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     10     1564     1702     1728    
+
+Symbol QMLDY (=1C7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/280):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     24    
+
+Symbol QMODE (=73E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1328):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     37    
+
+Symbol QMSG (=893,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1589):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     15    
+
+Symbol QMSGX (=8A1,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1601):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     16    
+
+Symbol QNL (=918,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1699):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     11    
+
+Symbol QPNT1 (=FB4,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3170):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1543     3108    
+
+Symbol QPNT2 (=FBF,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3177):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3179    
+
+Symbol QPONT (=FB1,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3169):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1100     1866     2301     2842     3070     3082    
+
+Symbol QPRNT (=935,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1727):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     14     1595     1709    
+
+Symbol QPRT (=946,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1743):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1732    
+
+Symbol QPRTS (=920,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1708):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     12      666     1412    
+
+Symbol QPRTT (=924,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1713):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 78 - 9.6.1998 9:06:30
+
+
+     13     1718    
+
+Symbol QQKEY (=9B3,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1823):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1449    
+
+Symbol QRDD (=4F8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/920):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     22      150    
+
+Symbol QRDI (=4D8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/902):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     21      143    
+
+Symbol QRSTR (=EE5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3040):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2895     2993     3011     3012     3014     3015     3033     3064    
+   3117     3120    
+
+Symbol QRSTR1 (=EE6,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3041):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1291     1606    
+
+Symbol QSAVE (=B92,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2291):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1824    
+
+Symbol QSWEP (=A50,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1964):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1497    
+
+Symbol QTEMP (=2E5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/491):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     31    
+
+Symbol QTMR1 (=375,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/614):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    604    
+
+Symbol QTMR2 (=37F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/620):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    608    
+
+Symbol QTMRD (=358,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/594):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     29    
+
+Symbol QTMS1 (=331,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/553):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    556      559    
+
+Symbol QTMS2 (=344,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/568):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    571      574    
+
+Symbol QTMST (=308,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/527):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     25    
+
+Symbol QVRFY (=588,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1029):
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 79 - 9.6.1998 9:06:30
+
+
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     23     3189    
+
+Symbol QWRD (=475,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/828):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     20     3158    
+
+Symbol QWRI (=436,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/789):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     19     3156    
+
+Symbol RATIO (=11A1,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3256):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    359      444    
+
+Symbol RBY1 (=630,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1154):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1170    
+
+Symbol RBY2 (=649,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1166):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1159    
+
+Symbol RBY3 (=654,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1173):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1155    
+
+Symbol RBYTE (=624,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1148):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    959      968      971     1074     1085     1088    
+
+Symbol RD1 (=4E6,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/910):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    931    
+
+Symbol RDA (=1B6,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/266):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    233      239      271    
+
+Symbol RET1 (=4D2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/889):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    838    
+
+Symbol RET2 (=554,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/980):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    812    
+
+Symbol RET3 (=69B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1219):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    324     1245     3224    
+
+Symbol RTAPE (=50E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/940):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    914    
+
+Symbol RTP1 (=513,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/944):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    996    
+
+Symbol RTP2 (=519,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/946):
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 80 - 9.6.1998 9:06:30
+
+
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    951    
+
+Symbol RTP3 (=532,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/959):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    966    
+
+Symbol RTP4 (=554,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/979):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    915      930     1003     1039     1046    
+
+Symbol RTP5 (=565,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/992):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    974      977    
+
+Symbol RTP6 (=572,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1001):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    911      913      947      960      969      972     1042     1044    
+   1063     1075    
+
+Symbol RTP7 (=56E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/998):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    993     1077     1087     1090    
+
+Symbol RTP8 (=553,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/978):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1092    
+
+Symbol RTP9 (=574,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1002):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    999    
+
+Symbol RYTHM (=2C8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/469):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    306      320    
+
+Symbol SAV1 (=F8E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3148):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   3153    
+
+Symbol SAVE (=F5E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3129):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    101    
+
+Symbol SCRN (=D000,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3053):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2970     2971     2976     2977     3176    
+
+Symbol SCROL (=E6D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2969):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2918     2996     3000    
+
+Symbol SG (=F7,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/119):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     93    
+
+Symbol SHORT (=A01,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1886):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    879     1371     1390     1398    
+
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 81 - 9.6.1998 9:06:30
+
+
+Symbol SIZE (=1102,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3234):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    834      926     1033     3137    
+
+Symbol SLPT (=3D5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/697):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    215    
+
+Symbol SPHEX (=3B1,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/666):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1411     2756    
+
+Symbol SPV (=10F0,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3230):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     35      272    
+
+Symbol SS (=A2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/71):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    123    
+
+Symbol ST0 (=70,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/52):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     39       41    
+
+Symbol ST1 (=AD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/77):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     85      130      136      139      210      273     2792     3163    
+   3193    
+
+Symbol ST2 (=BB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/82):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    110    
+
+Symbol START (=4A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/35):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+      8    
+
+Symbol SUMDT (=1197,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3248):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    867      954      967     1161     1163     1307    
+
+Symbol SUNDG (=E008,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3271):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    460    
+
+Symbol SV0 (=BA2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/2299):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2297     2314    
+
+Symbol SWEP0 (=A66,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1979):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1974     1976     1985     1994    
+
+Symbol SWEP01 (=A64,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1978):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   2010    
+
+Symbol SWEP3 (=A77,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1991):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1983    
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 82 - 9.6.1998 9:06:30
+
+
+
+Symbol SWEP6 (=A5F,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1974):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1970    
+
+Symbol SWEP9 (=A73,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1986):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1972    
+
+Symbol SWRK (=119D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3252):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     72      119     1452    
+
+Symbol TEMP (=E008,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3272):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    478      481    
+
+Symbol TEMPW (=119E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3253):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     65      381      497    
+
+Symbol TIMFG (=119C,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3251):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    533      985    
+
+Symbol TIMIN (=38D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/634):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+     60    
+
+Symbol TM1 (=675,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1200):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1206     1214    
+
+Symbol TM2 (=678,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1201):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1208    
+
+Symbol TM3 (=688,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1209):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1216    
+
+Symbol TM4 (=69B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1218):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1202     1210    
+
+Symbol TMARK (=65B,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1188):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    912     1043    
+
+Symbol TMCNT (=1195,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3247):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1197     1200    
+
+Symbol TVF1 (=5B2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1060):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1094    
+
+Symbol TVF2 (=5B8,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1062):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1067    
+ AS V1.40r8 - Quelle MZ700.ASM - Seite 83 - 9.6.1998 9:06:30
+
+
+
+Symbol TVF3 (=5CC,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1074):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1082    
+
+Symbol TVRFY (=5AD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1056):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1045    
+
+Symbol VRFY (=FCB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3189):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    103    
+
+Symbol WBY1 (=76D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1369):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+   1373    
+
+Symbol WBYTE (=767,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1366):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    854      869      871    
+
+Symbol WRI1 (=444,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/797):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    839    
+
+Symbol WRI2 (=45E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/810):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    802    
+
+Symbol WRI3 (=464,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/812):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    799    
+
+Symbol WTAP1 (=494,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/853):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    866      886    
+
+Symbol WTAP2 (=4A5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/862):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    857    
+
+Symbol WTAP3 (=4D2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/888):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    860      876    
+
+Symbol WTAPE (=48A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/847):
+ Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM :
+    811    
+
+
diff --git a/software/asm/hi-ramcheck.asm b/software/asm/hi-ramcheck.asm
new file mode 100644
index 0000000..4a00c5e
--- /dev/null
+++ b/software/asm/hi-ramcheck.asm
@@ -0,0 +1,241 @@
+
+KEYPC:     EQU     0E002h
+KEYPF:     EQU     0E003h
+CSTR:      EQU     0E002h
+CSTPT:     EQU     0E003h
+CONT0:     EQU     0E004h
+CONT1:     EQU     0E005h
+CONT2:     EQU     0E006h
+CONTF:     EQU     0E007h
+SUNDG:     EQU     0E008h
+TEMP:      EQU     0E008h
+LETNL:     EQU     0006h
+NL:        EQU     0009h
+PRNTS:     EQU     000Ch
+PRNT:      EQU     0012h
+MSG:       EQU     0015h
+MSGX:      EQU     0018h
+MONIT:     EQU     0086h
+ST1:       EQU     0095h
+PRTHL:     EQU     03BAh
+PRTHX:     EQU     03C3h
+DPCT:      EQU     0DDCh
+?BRK:      EQU     0D11h
+?RSTR1:    EQU     0EE6h
+GRAMSTART: EQU     0C000h
+GRAMEND:   EQU     0FFFFh
+TPSTART:   EQU     10F0h
+MEMSTART:  EQU     1200h
+MSTART:    EQU     0BE00h
+
+           ORG     TPSTART
+
+SPV:
+IBUFE:                                                                  ; TAPE BUFFER (128 BYTES)
+;ATRB:      DS      virtual 1                                           ; ATTRIBUTE
+ATRB:      DB      01h                                                  ; Code Type, 01 = Machine Code.
+;NAME:      DS      virtual 17                                          ; FILE NAME
+NAME:      DB      "TAPE CHECK V1.0", 0Dh, 00h                          ; Title/Name (17 bytes).
+;SIZE:      DS      virtual 2                                           ; BYTESIZE
+SIZE:      DW      MEND - MSTART                                        ; Size of program.
+;DTADR:     DS      virtual 2                                           ; DATA ADDRESS
+DTADR:     DW      MSTART                                               ; Load address of program.
+;EXADR:     DS      virtual 2                                           ; EXECUTION ADDRESS
+EXADR:     DW      MSTART                                               ; Exec address of program.
+COMNT:     DS      104                                                  ; COMMENT
+KANAF:     DS      virtual 1                                            ; KANA FLAG (01=GRAPHIC MODE)
+DSPXY:     DS      virtual 2                                            ; DISPLAY COORDINATES
+MANG:      DS      virtual 27                                           ; COLUMN MANAGEMENT
+FLASH:     DS      virtual 1                                            ; FLASHING DATA
+FLPST:     DS      virtual 2                                            ; FLASHING POSITION
+FLSST:     DS      virtual 1                                            ; FLASHING STATUS
+FLSDT:     DS      virtual 1                                            ; CURSOR DATA
+STRGF:     DS      virtual 1                                            ; STRING FLAG
+DPRNT:     DS      virtual 1                                            ; TAB COUNTER
+TMCNT:     DS      virtual 2                                            ; TAPE MARK COUNTER
+SUMDT:     DS      virtual 2                                            ; CHECK SUM DATA
+CSMDT:     DS      virtual 2                                            ; FOR COMPARE SUM DATA
+AMPM:      DS      virtual 1                                            ; AMPM DATA
+TIMFG:     DS      virtual 1                                            ; TIME FLAG
+SWRK:      DS      virtual 1                                            ; KEY SOUND FLAG
+TEMPW:     DS      virtual 1                                            ; TEMPO WORK
+ONTYO:     DS      virtual 1                                            ; ONTYO WORK
+OCTV:      DS      virtual 1                                            ; OCTAVE WORK
+RATIO:     DS      virtual 2                                            ; ONPU RATIO
+BUFER:     DS      virtual 81                                           ; GET LINE BUFFER
+
+           ORG     MSTART
+
+START:     LD      A,0FFh      ; Set Red filter.
+           OUT     (0EBh),A
+           LD      A,000h      ; Set Green filter.
+           OUT     (0ECh),A
+           LD      A,000h      ; Set Blue filter.
+           OUT     (0EDh),A
+           LD      A,000h
+           CALL    GRAMINIT
+           LD      A,005h
+           CALL    GRAMINIT
+           LD      A,00Ah
+           CALL    GRAMINIT
+           LD      A, 0CCh     ; Set graphics mode to Indirect Page write.
+           OUT     (0EAh),A
+           LD      HL,0DE00h
+           LD      (GRPHPOS),HL
+           JR      SIGNON
+
+
+GRAMINIT:  LD      HL,GRAMSTART
+           LD      BC,GRAMEND - GRAMSTART
+GRAM0:     OUT     (0EAh),A
+           OUT     (0E8h),A
+GRAM1:     LD      A,000h
+           LD      (HL),A
+           INC     HL
+           DEC     BC
+           LD      A,B
+           OR      C
+           JR      NZ,GRAM1
+           OUT     (0E9h),A
+           RET
+            
+
+SIGNON:    CALL    LETNL
+           LD      DE,TITLE
+           CALL    MSG
+           CALL    LETNL
+           LD      B,240       ; Number of loops
+LOOP:      LD      HL,MEMSTART ; Start of checked memory,
+           LD      D,0BEh      ; End memory check BE00
+LOOP1:     LD      A,000h
+           CP      L
+           JR      NZ,LOOP1b
+           CALL    PRTHL       ; Print HL as 4digit hex.
+           LD      A,0C4h      ; Move cursor left.
+           LD      E,004h      ; 4 times.
+LOOP1a:    CALL    DPCT
+           DEC     E
+           JR      NZ,LOOP1a
+LOOP1b:    INC     HL
+           LD      A,H
+           CP      D           ; Have we reached end of memory.
+           JR      Z,LOOP3     ; Yes, exit.
+           LD      A,(HL)      ; Read memory location under test, ie. 0.
+           CPL                 ; Subtract, ie. FF - A, ie FF - 0 = FF.
+           LD      (HL),A      ; Write it back, ie. FF.
+           SUB     (HL)        ; Subtract written memory value from A, ie. should be 0.
+           JR      NZ,LOOP2    ; Not zero, we have an error.
+           LD      A,(HL)      ; Reread memory location, ie. FF
+           CPL                 ; Subtract FF - FF
+           LD      (HL),A      ; Write 0
+           SUB     (HL)        ; Subtract 0
+           JR      Z,LOOP1     ; Loop if the same, ie. 0
+LOOP2:     LD      A,16h
+           CALL    PRNT        ; Print A
+           CALL    PRTHX       ; Print HL as 4 digit hex.
+           CALL    PRNTS       ; Print space.
+           XOR     A
+           LD      (HL),A
+           LD      A,(HL)      ; Get into A the failing bits.
+           CALL    PRTHX       ; Print A as 2 digit hex.
+           CALL    PRNTS       ; Print space.
+           LD      A,0FFh      ; Repeat but first load FF into memory
+           LD      (HL),A
+           LD      A,(HL)
+           CALL    PRTHX       ; Print A as 2 digit hex.
+           NOP
+           JR      LOOP4
+
+LOOP3:     CALL    PRTHL
+           LD      DE,OKCHECK
+           CALL    MSG          ; Print check message in DE
+           LD      A,B          ; Print loop count.
+           CALL    PRTHX
+           LD      DE,OKMSG
+           CALL    MSG          ; Print ok message in DE
+           CALL    NL
+           LD      HL,(GRPHPOS) ; Get position of graphics progress line.
+           OUT     (0E8h),A     ; Enable graphics memory.
+           LD      A,0FFh
+           LD      (HL),A
+           OUT     (0E9h),A     ; Disable graphics memory.
+           INC     HL
+           LD      (GRPHPOS),HL
+           DEC     B
+           JR      NZ,LOOP
+           LD      DE,DONEMSG
+           CALL    MSG          ; Print check message in DE
+           JP      MONIT
+
+LOOP4:     LD      B,09h
+           CALL    PRNTS        ; Print space.
+           XOR     A            ; Zero A
+           SCF                  ; Set Carry
+LOOP5:     PUSH    AF           ; Store A and Flags
+           LD      (HL),A       ; Store 0 to bad location.
+           LD      A,(HL)       ; Read back
+           CALL    PRTHX        ; Print A as 2 digit hex.
+           CALL    PRNTS        ; Print space
+           POP     AF           ; Get back A (ie. 0 + C)
+           RLA                  ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB
+           DJNZ    LOOP5        ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit.
+           XOR     A            ; Zero A, clears flags.
+           LD      A,80h
+           LD      B,08h
+LOOP6:     PUSH    AF           ; Repeat above but AND memory location with original A (ie. 80) 
+           LD      C,A          ; Basically walk through all the bits to find which one is stuck.
+           LD      (HL),A
+           LD      A,(HL)
+           AND     C
+           NOP
+           JR      Z,LOOP8      ; If zero then print out the bit number
+           NOP
+           NOP
+           LD      A,C
+           CPL
+           LD      (HL),A
+           LD      A,(HL)
+           AND     C
+           JR      NZ,LOOP8     ; As above, if the compliment doesnt yield zero, print out the bit number.
+LOOP7:     POP     AF
+           RRCA
+           NOP
+           DJNZ    LOOP6
+           JP      MONIT
+
+LOOP8:     CALL    LETNL        ; New line.
+           LD      DE,BITMSG    ; BIT message
+           CALL    MSG          ; Print message in DE
+           LD      A,B
+           DEC     A
+           CALL    PRTHX        ; Print A as 2 digit hex, ie. BIT number.
+           CALL    LETNL        ; New line
+           LD      DE,BANKMSG   ; BANK message
+           CALL    MSG          ; Print message in DE
+           LD      A,H
+           CP      50h          ; 'P'
+           JR      NC,LOOP9     ; Work out bank number, 1, 2 or 3.
+           LD      A,01h
+           JR      LOOP11
+
+LOOP9:     CP      90h
+           JR      NC,LOOP10
+           LD      A,02h
+           JR      LOOP11
+
+LOOP10:    LD      A,03h
+LOOP11:    CALL    PRTHX        ; Print A as 2 digit hex, ie. BANK number.
+           JR      LOOP7
+
+OKCHECK:   DB      ", CHECK: ", 0Dh
+OKMSG:     DB      " OK.", 0Dh
+DONEMSG:   DB      11h
+           DB      "RAM TEST COMPLETE.", 0Dh
+
+BITMSG:    DB      " BIT:  ", 0Dh
+BANKMSG:   DB      " BANK: ", 0Dh
+
+TITLE:     DB      "SHARPMZ RAM TEST (C) P. SMART 2018", 0Dh, 00h
+GRPHPOS:   DB      00h, 00h
+
+MEND:
diff --git a/software/asm/hi-ramcheck.obj b/software/asm/hi-ramcheck.obj
new file mode 100644
index 0000000..c68c09f
Binary files /dev/null and b/software/asm/hi-ramcheck.obj differ
diff --git a/software/asm/hi-ramcheck.sym b/software/asm/hi-ramcheck.sym
new file mode 100644
index 0000000..edef89c
--- /dev/null
+++ b/software/asm/hi-ramcheck.sym
@@ -0,0 +1,55 @@
+AMPM: equ 119BH
+ATRB: equ 10F0H
+BANKMSG: equ 0BF4DH
+BITMSG: equ 0BF45H
+BUFER: equ 11A3H
+COMNT: equ 1108H
+CSMDT: equ 1199H
+DONEMSG: equ 0BF31H
+DPRNT: equ 1194H
+DSPXY: equ 1171H
+DTADR: equ 1104H
+EXADR: equ 1106H
+FLASH: equ 118EH
+FLPST: equ 118FH
+FLSDT: equ 1192H
+FLSST: equ 1191H
+GRAM0: equ 0BE2DH
+GRAM1: equ 0BE31H
+GRAMINIT: equ 0BE27H
+GRPHPOS: equ 0BF79H
+IBUFE: equ 10F0H
+KANAF: equ 1170H
+LOOP: equ 0BE4BH
+LOOP1: equ 0BE50H
+LOOP10: equ 0BF1BH
+LOOP11: equ 0BF1DH
+LOOP1a: equ 0BE5CH
+LOOP1b: equ 0BE62H
+LOOP2: equ 0BE73H
+LOOP3: equ 0BE91H
+LOOP4: equ 0BEC1H
+LOOP5: equ 0BEC8H
+LOOP6: equ 0BEDAH
+LOOP7: equ 0BEEBH
+LOOP8: equ 0BEF3H
+LOOP9: equ 0BF13H
+MANG: equ 1173H
+MEND: equ 0BF7BH
+NAME: equ 10F1H
+OCTV: equ 11A0H
+OKCHECK: equ 0BF22H
+OKMSG: equ 0BF2CH
+ONTYO: equ 119FH
+RATIO: equ 11A1H
+SIGNON: equ 0BE3DH
+SIZE: equ 1102H
+SPV: equ 10F0H
+START: equ 0BE00H
+STRGF: equ 1193H
+SUMDT: equ 1197H
+SWRK: equ 119DH
+TEMPW: equ 119EH
+TIMFG: equ 119CH
+TITLE: equ 0BF55H
+TMCNT: equ 1195H
diff --git a/software/asm/monitor_1Z-013A.asm b/software/asm/monitor_1Z-013A.asm
new file mode 100644
index 0000000..7bb488b
--- /dev/null
+++ b/software/asm/monitor_1Z-013A.asm
@@ -0,0 +1,7 @@
+; Configurable parameters.
+COLW:   EQU     40                      ; Width of the display screen (ie. columns).
+ROW:    EQU     25                      ; Number of rows on display screen.
+SCRNSZ: EQU     COLW * ROW              ; Total size, in bytes, of the screen display area.
+MODE80C:EQU     0
+
+		INCLUDE "1Z-013A.asm"
diff --git a/software/asm/monitor_1Z-013A.obj b/software/asm/monitor_1Z-013A.obj
new file mode 100644
index 0000000..dd66632
Binary files /dev/null and b/software/asm/monitor_1Z-013A.obj differ
diff --git a/software/asm/monitor_1Z-013A.sym b/software/asm/monitor_1Z-013A.sym
new file mode 100644
index 0000000..92ee353
--- /dev/null
+++ b/software/asm/monitor_1Z-013A.sym
@@ -0,0 +1,382 @@
+ALPH1: equ 0EE2H
+ALPHA: equ 0EE1H
+AMPM: equ 119BH
+ASC: equ 3DAH
+ATBL: equ 0A92H
+ATRB: equ 10F0H
+AUTO3: equ 7EDH
+BELL: equ 3EH
+BGETL: equ 12FH
+BRKEY: equ 1EH
+BUFER: equ 11A3H
+CKS1: equ 720H
+CKS2: equ 72FH
+CKS3: equ 733H
+CKSUM: equ 71AH
+CLEAR: equ 9D8H
+CLEAR1: equ 9DAH
+CLRS: equ 0E3AH
+CMY0: equ 5BH
+COMNT: equ 1108H
+CR: equ 0E5AH
+CR1: equ 0E6AH
+CSMDT: equ 1199H
+CTBL: equ 0EAAH
+CURS1: equ 0DFFH
+CURS2: equ 0E16H
+CURS3: equ 0DFFH
+CURS4: equ 0E23H
+CURS5: equ 0E02H
+CURSD: equ 0DF8H
+CURSL: equ 0E25H
+CURSR: equ 0E0DH
+CURSU: equ 0E05H
+CURSU1: equ 0E0BH
+DACN1: equ 0BE3H
+DACN2: equ 0BDFH
+DACN3: equ 0BE0H
+DEL: equ 0EF8H
+DEL1: equ 0F0EH
+DEL2: equ 0F1CH
+DLY1: equ 759H
+DLY12: equ 996H
+DLY2: equ 760H
+DLY3: equ 0A4AH
+DLY4: equ 9A9H
+DMCP: equ 6BH
+DPRNT: equ 1194H
+DSP01: equ 0DB9H
+DSP04: equ 0DD0H
+DSPXY: equ 1171H
+DSWEP: equ 830H
+DTADR: equ 1104H
+DUM1: equ 0D88H
+DUM2: equ 0D3EH
+DUM3: equ 0D37H
+DUMP: equ 0D29H
+EDG1: equ 607H
+EDG2: equ 613H
+EDGE: equ 601H
+EXADR: equ 1106H
+FD: equ 0FFH
+FD1: equ 106H
+FD2: equ 102H
+FLAS1: equ 97BH
+FLAS2: equ 9EFH
+FLASH: equ 118EH
+FLKEY: equ 57EH
+FLPST: equ 118FH
+FLSDT: equ 1192H
+FLSST: equ 1191H
+GAP: equ 77AH
+GAP1: equ 78EH
+GAP2: equ 796H
+GAP3: equ 79CH
+GAPCK: equ 0FE2H
+GAPCK1: equ 0FEBH
+GAPCK2: equ 0FEDH
+GAPCK3: equ 0FFDH
+GETKY: equ 1BH
+GETL: equ 3H
+GETL1: equ 7EAH
+GETL2: equ 818H
+GETL3: equ 85BH
+GETL5: equ 81DH
+GETL6: equ 865H
+GETLA: equ 82BH
+GETLB: equ 863H
+GETLC: equ 822H
+GETLR: equ 87EH
+GETLU: equ 876H
+GETLZ: equ 86CH
+GOTO: equ 0F3H
+GRSTAS: equ 0DD4H
+HEX: equ 3F9H
+HEXIY: equ 13DH
+HEXJ: equ 3E5H
+HLHEX: equ 410H
+HOME: equ 0E4DH
+IBUFE: equ 10F0H
+INST: equ 0F38H
+INST2: equ 0ECAH
+KANA: equ 0EEEH
+KANAF: equ 1170H
+KSL1: equ 9B7H
+KSL2: equ 9BCH
+KTBL: equ 0BEAH
+KTBLC: equ 0CAAH
+KTBLG: equ 0CE9H
+KTBLGS: equ 0C6AH
+KTBLS: equ 0C2AH
+L010F: equ 10FH
+L01F5: equ 1F5H
+L0207: equ 207H
+L0220: equ 220H
+L0239: equ 239H
+L023F: equ 23FH
+L0255: equ 255H
+L025A: equ 25AH
+L02D5: equ 2D5H
+L02DB: equ 2DBH
+L0363: equ 363H
+L0378: equ 378H
+L041D: equ 41DH
+L0434: equ 434H
+L047D: equ 47DH
+L04C2: equ 4C2H
+L04C4: equ 4C4H
+L0563: equ 563H
+L060E: equ 60EH
+L061A: equ 61AH
+L066C: equ 66CH
+L06AD: equ 6ADH
+L06B4: equ 6B4H
+L071C: equ 71CH
+L0725: equ 725H
+L0737: equ 737H
+L0739: equ 739H
+L075B: equ 75BH
+L0762: equ 762H
+L08F7: equ 8F7H
+L092C: equ 92CH
+L0968: equ 968H
+L0999: equ 999H
+L09AB: equ 9ABH
+L0A89: equ 0A89H
+L0BA0: equ 0BA0H
+L0BB1: equ 0BB1H
+L0D36: equ 0D36H
+L0D51: equ 0D51H
+L0D78: equ 0D78H
+L0D7A: equ 0D7AH
+L0D85: equ 0D85H
+L0DA7: equ 0DA7H
+L0DAD: equ 0DADH
+L0DE0: equ 0DE0H
+L0E2D: equ 0E2DH
+L0F17: equ 0F17H
+L0F33: equ 0F33H
+L0F42: equ 0F42H
+L0F4D: equ 0F4DH
+L2HEX: equ 41FH
+LETNL: equ 6H
+LLPT: equ 470H
+LOA0: equ 116H
+LOAD: equ 111H
+LONG: equ 0A1AH
+LPRNT: equ 18FH
+MANG: equ 1173H
+MCOR: equ 7A8H
+MCR1: equ 7ABH
+MCR2: equ 7D4H
+MCR3: equ 7D7H
+MELDY: equ 30H
+MLD1: equ 1D1H
+MLD2: equ 205H
+MLD3: equ 20DH
+MLD4: equ 211H
+MLD5: equ 214H
+MLDS1: equ 2C4H
+MLDSP: equ 2BEH
+MLDST: equ 2ABH
+MNTBL: equ 284H
+MONIT: equ 0H
+MOT1: equ 6A4H
+MOT2: equ 6ABH
+MOT4: equ 6B9H
+MOT5: equ 6D8H
+MOT7: equ 6B7H
+MOT8: equ 6D0H
+MOT9: equ 6D7H
+MOTOR: equ 69FH
+MSG: equ 15H
+MSG1: equ 896H
+MSGE1: equ 147H
+MSGN1: equ 3FBH
+MSGN2: equ 3FDH
+MSGN3: equ 402H
+MSGN7: equ 467H
+MSGOK: equ 942H
+MSGQ2: equ 9A0H
+MSGQ3: equ 6E7H
+MSGSV: equ 98BH
+MSGX: equ 18H
+MSGX1: equ 8A4H
+MSGX2: equ 8A7H
+MST1: equ 705H
+MST3: equ 717H
+MSTA: equ 44H
+MSTOP: equ 700H
+MSTP: equ 47H
+MTBL: equ 26CH
+NAME: equ 10F1H
+NBRK: equ 8B8H
+NCLR08: equ 9D4H
+NCLR8: equ 9D5H
+NL: equ 9H
+NLPHL: equ 5FAH
+NOADD: equ 3E2H
+OCTV: equ 11A0H
+ONP1: equ 21FH
+ONP2: equ 22CH
+ONP3: equ 265H
+ONPU: equ 21CH
+ONTYO: equ 119FH
+OPTBL: equ 29CH
+P4DE: equ 2A6H
+PEN: equ 18BH
+PLOT: equ 184H
+PLPT: equ 176H
+PMANG: equ 2F3H
+PMSG: equ 1A5H
+PMSG1: equ 1A8H
+PPLPT: equ 17BH
+PRNT: equ 12H
+PRNT2: equ 967H
+PRNT3: equ 96CH
+PRNT4: equ 96FH
+PRNT5: equ 959H
+PRNTS: equ 0CH
+PRNTT: equ 0FH
+PRTHL: equ 3BAH
+PRTHX: equ 3C3H
+PTEST: equ 155H
+PTRN: equ 180H
+PTST0: equ 15AH
+PTST1: equ 170H
+QADCN: equ 0BB9H
+QBEL: equ 577H
+QBELD: equ 352H
+QBLNK: equ 0DA6H
+QBRK: equ 0A32H
+QBRK1: equ 0A48H
+QBRK2: equ 980H
+QBRK3: equ 986H
+QCLER: equ 0FD8H
+QCLRFF: equ 0FDBH
+QDACN: equ 0BCEH
+QDINT: equ 0FDDH
+QDPCT: equ 0DDCH
+QDSP: equ 0DB5H
+QER: equ 107H
+QFLAS: equ 9FFH
+QFLS: equ 9E3H
+QGET: equ 8BDH
+QGETL: equ 7E6H
+QKEY: equ 8CAH
+QKY1: equ 8D6H
+QKY2: equ 8DAH
+QKY5: equ 8FAH
+QKY55: equ 8FBH
+QKYGRP: equ 8FEH
+QKYGRS: equ 909H
+QKYSM: equ 8B3H
+QLOAD: equ 5F0H
+QLTNL: equ 90EH
+QMLDY: equ 1C7H
+QMODE: equ 73EH
+QMSG: equ 893H
+QMSGX: equ 8A1H
+QNL: equ 918H
+QPNT1: equ 0FB4H
+QPNT2: equ 0FBFH
+QPONT: equ 0FB1H
+QPRNT: equ 935H
+QPRT: equ 946H
+QPRTS: equ 920H
+QPRTT: equ 924H
+QQKEY: equ 9B3H
+QRDD: equ 4F8H
+QRDI: equ 4D8H
+QRSTR: equ 0EE5H
+QRSTR1: equ 0EE6H
+QSAVE: equ 0B92H
+QSWEP: equ 0A50H
+QTEMP: equ 2E5H
+QTMR1: equ 375H
+QTMR2: equ 37FH
+QTMRD: equ 358H
+QTMS1: equ 331H
+QTMS2: equ 344H
+QTMST: equ 308H
+QVRFY: equ 588H
+QWRD: equ 475H
+QWRI: equ 436H
+RATIO: equ 11A1H
+RBY1: equ 630H
+RBY2: equ 649H
+RBY3: equ 654H
+RBYTE: equ 624H
+RD1: equ 4E6H
+RDA: equ 1B6H
+RDDAT: equ 2AH
+RDINF: equ 27H
+RET1: equ 4D2H
+RET2: equ 554H
+RET3: equ 69BH
+RTAPE: equ 50EH
+RTP1: equ 513H
+RTP2: equ 519H
+RTP3: equ 532H
+RTP4: equ 554H
+RTP5: equ 565H
+RTP6: equ 572H
+RTP7: equ 56EH
+RTP8: equ 553H
+RTP9: equ 574H
+RYTHM: equ 2C8H
+SAV1: equ 0F8EH
+SAVE: equ 0F5EH
+SCROL: equ 0E6DH
+SG: equ 0F7H
+SHORT: equ 0A01H
+SIZE: equ 1102H
+SLPT: equ 3D5H
+SPHEX: equ 3B1H
+SPV: equ 10F0H
+SS: equ 0A2H
+ST0: equ 70H
+ST1: equ 0ADH
+ST2: equ 0BBH
+START: equ 4AH
+STRGF: equ 1193H
+SUMDT: equ 1197H
+SV0: equ 0BA2H
+SV1: equ 0BB5H
+SWEP0: equ 0A66H
+SWEP01: equ 0A64H
+SWEP2: equ 0A7FH
+SWEP3: equ 0A77H
+SWEP6: equ 0A5FH
+SWEP9: equ 0A73H
+SWRK: equ 119DH
+TEMPW: equ 119EH
+TIMFG: equ 119CH
+TIMIN: equ 38DH
+TIMRD: equ 3BH
+TIMST: equ 33H
+TM1: equ 675H
+TM2: equ 678H
+TM3: equ 688H
+TM4: equ 69BH
+TMARK: equ 65BH
+TMCNT: equ 1195H
+TVF1: equ 5B2H
+TVF2: equ 5B8H
+TVF3: equ 5CCH
+TVRFY: equ 5ADH
+VERFY: equ 2DH
+VRFY: equ 0FCBH
+VRNS: equ 0BC5H
+WBY1: equ 76DH
+WBYTE: equ 767H
+WRDAT: equ 24H
+WRI1: equ 444H
+WRI2: equ 45EH
+WRI3: equ 464H
+WRINF: equ 21H
+WTAP1: equ 494H
+WTAP2: equ 4A5H
+WTAP3: equ 4D2H
+WTAPE: equ 48AH
+XTEMP: equ 41H
diff --git a/software/asm/monitor_80c_1Z-013A.asm b/software/asm/monitor_80c_1Z-013A.asm
new file mode 100644
index 0000000..3c1f57e
--- /dev/null
+++ b/software/asm/monitor_80c_1Z-013A.asm
@@ -0,0 +1,7 @@
+; Configurable parameters.
+COLW:   EQU     80                      ; Width of the display screen (ie. columns).
+ROW:    EQU     25                      ; Number of rows on display screen.
+SCRNSZ: EQU     COLW * ROW              ; Total size, in bytes, of the screen display area.
+MODE80C:EQU     1
+
+		INCLUDE "1Z-013A.asm"
diff --git a/software/asm/monitor_80c_1Z-013A.obj b/software/asm/monitor_80c_1Z-013A.obj
new file mode 100644
index 0000000..f86b247
Binary files /dev/null and b/software/asm/monitor_80c_1Z-013A.obj differ
diff --git a/software/asm/monitor_80c_1Z-013A.sym b/software/asm/monitor_80c_1Z-013A.sym
new file mode 100644
index 0000000..92ee353
--- /dev/null
+++ b/software/asm/monitor_80c_1Z-013A.sym
@@ -0,0 +1,382 @@
+ALPH1: equ 0EE2H
+ALPHA: equ 0EE1H
+AMPM: equ 119BH
+ASC: equ 3DAH
+ATBL: equ 0A92H
+ATRB: equ 10F0H
+AUTO3: equ 7EDH
+BELL: equ 3EH
+BGETL: equ 12FH
+BRKEY: equ 1EH
+BUFER: equ 11A3H
+CKS1: equ 720H
+CKS2: equ 72FH
+CKS3: equ 733H
+CKSUM: equ 71AH
+CLEAR: equ 9D8H
+CLEAR1: equ 9DAH
+CLRS: equ 0E3AH
+CMY0: equ 5BH
+COMNT: equ 1108H
+CR: equ 0E5AH
+CR1: equ 0E6AH
+CSMDT: equ 1199H
+CTBL: equ 0EAAH
+CURS1: equ 0DFFH
+CURS2: equ 0E16H
+CURS3: equ 0DFFH
+CURS4: equ 0E23H
+CURS5: equ 0E02H
+CURSD: equ 0DF8H
+CURSL: equ 0E25H
+CURSR: equ 0E0DH
+CURSU: equ 0E05H
+CURSU1: equ 0E0BH
+DACN1: equ 0BE3H
+DACN2: equ 0BDFH
+DACN3: equ 0BE0H
+DEL: equ 0EF8H
+DEL1: equ 0F0EH
+DEL2: equ 0F1CH
+DLY1: equ 759H
+DLY12: equ 996H
+DLY2: equ 760H
+DLY3: equ 0A4AH
+DLY4: equ 9A9H
+DMCP: equ 6BH
+DPRNT: equ 1194H
+DSP01: equ 0DB9H
+DSP04: equ 0DD0H
+DSPXY: equ 1171H
+DSWEP: equ 830H
+DTADR: equ 1104H
+DUM1: equ 0D88H
+DUM2: equ 0D3EH
+DUM3: equ 0D37H
+DUMP: equ 0D29H
+EDG1: equ 607H
+EDG2: equ 613H
+EDGE: equ 601H
+EXADR: equ 1106H
+FD: equ 0FFH
+FD1: equ 106H
+FD2: equ 102H
+FLAS1: equ 97BH
+FLAS2: equ 9EFH
+FLASH: equ 118EH
+FLKEY: equ 57EH
+FLPST: equ 118FH
+FLSDT: equ 1192H
+FLSST: equ 1191H
+GAP: equ 77AH
+GAP1: equ 78EH
+GAP2: equ 796H
+GAP3: equ 79CH
+GAPCK: equ 0FE2H
+GAPCK1: equ 0FEBH
+GAPCK2: equ 0FEDH
+GAPCK3: equ 0FFDH
+GETKY: equ 1BH
+GETL: equ 3H
+GETL1: equ 7EAH
+GETL2: equ 818H
+GETL3: equ 85BH
+GETL5: equ 81DH
+GETL6: equ 865H
+GETLA: equ 82BH
+GETLB: equ 863H
+GETLC: equ 822H
+GETLR: equ 87EH
+GETLU: equ 876H
+GETLZ: equ 86CH
+GOTO: equ 0F3H
+GRSTAS: equ 0DD4H
+HEX: equ 3F9H
+HEXIY: equ 13DH
+HEXJ: equ 3E5H
+HLHEX: equ 410H
+HOME: equ 0E4DH
+IBUFE: equ 10F0H
+INST: equ 0F38H
+INST2: equ 0ECAH
+KANA: equ 0EEEH
+KANAF: equ 1170H
+KSL1: equ 9B7H
+KSL2: equ 9BCH
+KTBL: equ 0BEAH
+KTBLC: equ 0CAAH
+KTBLG: equ 0CE9H
+KTBLGS: equ 0C6AH
+KTBLS: equ 0C2AH
+L010F: equ 10FH
+L01F5: equ 1F5H
+L0207: equ 207H
+L0220: equ 220H
+L0239: equ 239H
+L023F: equ 23FH
+L0255: equ 255H
+L025A: equ 25AH
+L02D5: equ 2D5H
+L02DB: equ 2DBH
+L0363: equ 363H
+L0378: equ 378H
+L041D: equ 41DH
+L0434: equ 434H
+L047D: equ 47DH
+L04C2: equ 4C2H
+L04C4: equ 4C4H
+L0563: equ 563H
+L060E: equ 60EH
+L061A: equ 61AH
+L066C: equ 66CH
+L06AD: equ 6ADH
+L06B4: equ 6B4H
+L071C: equ 71CH
+L0725: equ 725H
+L0737: equ 737H
+L0739: equ 739H
+L075B: equ 75BH
+L0762: equ 762H
+L08F7: equ 8F7H
+L092C: equ 92CH
+L0968: equ 968H
+L0999: equ 999H
+L09AB: equ 9ABH
+L0A89: equ 0A89H
+L0BA0: equ 0BA0H
+L0BB1: equ 0BB1H
+L0D36: equ 0D36H
+L0D51: equ 0D51H
+L0D78: equ 0D78H
+L0D7A: equ 0D7AH
+L0D85: equ 0D85H
+L0DA7: equ 0DA7H
+L0DAD: equ 0DADH
+L0DE0: equ 0DE0H
+L0E2D: equ 0E2DH
+L0F17: equ 0F17H
+L0F33: equ 0F33H
+L0F42: equ 0F42H
+L0F4D: equ 0F4DH
+L2HEX: equ 41FH
+LETNL: equ 6H
+LLPT: equ 470H
+LOA0: equ 116H
+LOAD: equ 111H
+LONG: equ 0A1AH
+LPRNT: equ 18FH
+MANG: equ 1173H
+MCOR: equ 7A8H
+MCR1: equ 7ABH
+MCR2: equ 7D4H
+MCR3: equ 7D7H
+MELDY: equ 30H
+MLD1: equ 1D1H
+MLD2: equ 205H
+MLD3: equ 20DH
+MLD4: equ 211H
+MLD5: equ 214H
+MLDS1: equ 2C4H
+MLDSP: equ 2BEH
+MLDST: equ 2ABH
+MNTBL: equ 284H
+MONIT: equ 0H
+MOT1: equ 6A4H
+MOT2: equ 6ABH
+MOT4: equ 6B9H
+MOT5: equ 6D8H
+MOT7: equ 6B7H
+MOT8: equ 6D0H
+MOT9: equ 6D7H
+MOTOR: equ 69FH
+MSG: equ 15H
+MSG1: equ 896H
+MSGE1: equ 147H
+MSGN1: equ 3FBH
+MSGN2: equ 3FDH
+MSGN3: equ 402H
+MSGN7: equ 467H
+MSGOK: equ 942H
+MSGQ2: equ 9A0H
+MSGQ3: equ 6E7H
+MSGSV: equ 98BH
+MSGX: equ 18H
+MSGX1: equ 8A4H
+MSGX2: equ 8A7H
+MST1: equ 705H
+MST3: equ 717H
+MSTA: equ 44H
+MSTOP: equ 700H
+MSTP: equ 47H
+MTBL: equ 26CH
+NAME: equ 10F1H
+NBRK: equ 8B8H
+NCLR08: equ 9D4H
+NCLR8: equ 9D5H
+NL: equ 9H
+NLPHL: equ 5FAH
+NOADD: equ 3E2H
+OCTV: equ 11A0H
+ONP1: equ 21FH
+ONP2: equ 22CH
+ONP3: equ 265H
+ONPU: equ 21CH
+ONTYO: equ 119FH
+OPTBL: equ 29CH
+P4DE: equ 2A6H
+PEN: equ 18BH
+PLOT: equ 184H
+PLPT: equ 176H
+PMANG: equ 2F3H
+PMSG: equ 1A5H
+PMSG1: equ 1A8H
+PPLPT: equ 17BH
+PRNT: equ 12H
+PRNT2: equ 967H
+PRNT3: equ 96CH
+PRNT4: equ 96FH
+PRNT5: equ 959H
+PRNTS: equ 0CH
+PRNTT: equ 0FH
+PRTHL: equ 3BAH
+PRTHX: equ 3C3H
+PTEST: equ 155H
+PTRN: equ 180H
+PTST0: equ 15AH
+PTST1: equ 170H
+QADCN: equ 0BB9H
+QBEL: equ 577H
+QBELD: equ 352H
+QBLNK: equ 0DA6H
+QBRK: equ 0A32H
+QBRK1: equ 0A48H
+QBRK2: equ 980H
+QBRK3: equ 986H
+QCLER: equ 0FD8H
+QCLRFF: equ 0FDBH
+QDACN: equ 0BCEH
+QDINT: equ 0FDDH
+QDPCT: equ 0DDCH
+QDSP: equ 0DB5H
+QER: equ 107H
+QFLAS: equ 9FFH
+QFLS: equ 9E3H
+QGET: equ 8BDH
+QGETL: equ 7E6H
+QKEY: equ 8CAH
+QKY1: equ 8D6H
+QKY2: equ 8DAH
+QKY5: equ 8FAH
+QKY55: equ 8FBH
+QKYGRP: equ 8FEH
+QKYGRS: equ 909H
+QKYSM: equ 8B3H
+QLOAD: equ 5F0H
+QLTNL: equ 90EH
+QMLDY: equ 1C7H
+QMODE: equ 73EH
+QMSG: equ 893H
+QMSGX: equ 8A1H
+QNL: equ 918H
+QPNT1: equ 0FB4H
+QPNT2: equ 0FBFH
+QPONT: equ 0FB1H
+QPRNT: equ 935H
+QPRT: equ 946H
+QPRTS: equ 920H
+QPRTT: equ 924H
+QQKEY: equ 9B3H
+QRDD: equ 4F8H
+QRDI: equ 4D8H
+QRSTR: equ 0EE5H
+QRSTR1: equ 0EE6H
+QSAVE: equ 0B92H
+QSWEP: equ 0A50H
+QTEMP: equ 2E5H
+QTMR1: equ 375H
+QTMR2: equ 37FH
+QTMRD: equ 358H
+QTMS1: equ 331H
+QTMS2: equ 344H
+QTMST: equ 308H
+QVRFY: equ 588H
+QWRD: equ 475H
+QWRI: equ 436H
+RATIO: equ 11A1H
+RBY1: equ 630H
+RBY2: equ 649H
+RBY3: equ 654H
+RBYTE: equ 624H
+RD1: equ 4E6H
+RDA: equ 1B6H
+RDDAT: equ 2AH
+RDINF: equ 27H
+RET1: equ 4D2H
+RET2: equ 554H
+RET3: equ 69BH
+RTAPE: equ 50EH
+RTP1: equ 513H
+RTP2: equ 519H
+RTP3: equ 532H
+RTP4: equ 554H
+RTP5: equ 565H
+RTP6: equ 572H
+RTP7: equ 56EH
+RTP8: equ 553H
+RTP9: equ 574H
+RYTHM: equ 2C8H
+SAV1: equ 0F8EH
+SAVE: equ 0F5EH
+SCROL: equ 0E6DH
+SG: equ 0F7H
+SHORT: equ 0A01H
+SIZE: equ 1102H
+SLPT: equ 3D5H
+SPHEX: equ 3B1H
+SPV: equ 10F0H
+SS: equ 0A2H
+ST0: equ 70H
+ST1: equ 0ADH
+ST2: equ 0BBH
+START: equ 4AH
+STRGF: equ 1193H
+SUMDT: equ 1197H
+SV0: equ 0BA2H
+SV1: equ 0BB5H
+SWEP0: equ 0A66H
+SWEP01: equ 0A64H
+SWEP2: equ 0A7FH
+SWEP3: equ 0A77H
+SWEP6: equ 0A5FH
+SWEP9: equ 0A73H
+SWRK: equ 119DH
+TEMPW: equ 119EH
+TIMFG: equ 119CH
+TIMIN: equ 38DH
+TIMRD: equ 3BH
+TIMST: equ 33H
+TM1: equ 675H
+TM2: equ 678H
+TM3: equ 688H
+TM4: equ 69BH
+TMARK: equ 65BH
+TMCNT: equ 1195H
+TVF1: equ 5B2H
+TVF2: equ 5B8H
+TVF3: equ 5CCH
+TVRFY: equ 5ADH
+VERFY: equ 2DH
+VRFY: equ 0FCBH
+VRNS: equ 0BC5H
+WBY1: equ 76DH
+WBYTE: equ 767H
+WRDAT: equ 24H
+WRI1: equ 444H
+WRI2: equ 45EH
+WRI3: equ 464H
+WRINF: equ 21H
+WTAP1: equ 494H
+WTAP2: equ 4A5H
+WTAP3: equ 4D2H
+WTAPE: equ 48AH
+XTEMP: equ 41H
diff --git a/software/asm/monitor_80c_SA1510.asm b/software/asm/monitor_80c_SA1510.asm
new file mode 100644
index 0000000..ff7288c
--- /dev/null
+++ b/software/asm/monitor_80c_SA1510.asm
@@ -0,0 +1,7 @@
+; Configurable parameters.
+COLW:   EQU     80                      ; Width of the display screen (ie. columns).
+ROW:    EQU     25                      ; Number of rows on display screen.
+SCRNSZ: EQU     COLW * ROW              ; Total size, in bytes, of the screen display area.
+MODE80C:EQU     1
+
+		INCLUDE "sa1510.asm"
diff --git a/software/asm/monitor_80c_SA1510.obj b/software/asm/monitor_80c_SA1510.obj
new file mode 100644
index 0000000..06ec98a
Binary files /dev/null and b/software/asm/monitor_80c_SA1510.obj differ
diff --git a/software/asm/monitor_80c_SA1510.sym b/software/asm/monitor_80c_SA1510.sym
new file mode 100644
index 0000000..6996cdb
--- /dev/null
+++ b/software/asm/monitor_80c_SA1510.sym
@@ -0,0 +1,394 @@
+.CP1: equ 13AH
+.CR: equ 128H
+.CTBL: equ 168H
+.DSP03: equ 39DH
+.MANG: equ 0A2BH
+.MANG1: equ 0A4CH
+.MANG2: equ 3A6H
+.MANG3: equ 0A38H
+.MANG4: equ 0A45H
+.SCROL: equ 13DH
+?ADCN: equ 0BB9H
+?BEL: equ 2E5H
+?BELD: equ 0DB1H
+?BLNK: equ 0DA6H
+?BRK: equ 0D11H
+?CLER: equ 0FD8H
+?CLRFF: equ 0FDBH
+?DACN: equ 0BCEH
+?DINT: equ 0FDDH
+?DPCT: equ 0DDCH
+?DSP: equ 0DB5H
+?DSPA: equ 0D7CH
+?ER: equ 0CFH
+?FLAS: equ 9FFH
+?GET: equ 8B3H
+?GETL: equ 7A8H
+?KEY: equ 8CAH
+?KY1: equ 8D6H
+?KY10: equ 8EFH
+?KY11: equ 8EAH
+?KY2: equ 8F2H
+?KY3: equ 922H
+?KY4: equ 92FH
+?KY5: equ 91EH
+?KY6: equ 92AH
+?KY7: equ 93AH
+?KY9: equ 93FH
+?LOAD: equ 5F5H
+?LTNL: equ 980H
+?MLDY: equ 188H
+?MODE: equ 74DH
+?MSG: equ 893H
+?MSGX: equ 8A1H
+?NL: equ 97BH
+?PNT1: equ 0FB4H
+?PNT2: equ 0FCAH
+?PONT: equ 0FB1H
+?PRNT: equ 995H
+?PRT: equ 946H
+?PRTS: equ 993H
+?PRTT: equ 984H
+?RDD: equ 4EFH
+?RDI: equ 4CFH
+?RSTR: equ 0EE5H
+?RSTR1: equ 0EE6H
+?SAVE: equ 263H
+?SWEP: equ 0A50H
+?TEMP: equ 2ECH
+?TMR1: equ 361H
+?TMR1A: equ 364H
+?TMR2: equ 36BH
+?TMRD: equ 344H
+?TMST: equ 2FAH
+?VRFY: equ 575H
+?WRD: equ 470H
+?WRI: equ 436H
+ALPHA: equ 0EE1H
+ALPHI: equ 0EE2H
+AMPM: equ 119BH
+ASC: equ 3DAH
+ATBL: equ 0AB5H
+ATRB: equ 10F0H
+AUTCK: equ 9F1H
+AUTO2: equ 807H
+AUTO3: equ 7C4H
+AUTO5: equ 824H
+AUTOL: equ 810H
+AUTOL1: equ 812H
+BELL: equ 3EH
+BRKEY: equ 1EH
+BUFER: equ 11A3H
+CHGP1: equ 84BH
+CHGPA: equ 83EH
+CHGPK: equ 841H
+CHGPK1: equ 843H
+CLR8: equ 9E3H
+CLRS: equ 0EB3H
+CLRS1: equ 0ED1H
+COMNT: equ 1108H
+CR: equ 0F73H
+CR2: equ 0F8BH
+CR3: equ 0F99H
+CSMDT: equ 1199H
+CTBL: equ 0DFFH
+CURS1: equ 0E66H
+CURS2: equ 0E86H
+CURS3: equ 0E69H
+CURS4: equ 0E93H
+CURS5: equ 0EAAH
+CURS5A: equ 0E9FH
+CURS6: equ 0ED7H
+CURSD: equ 0E5DH
+CURSL: equ 0E95H
+CURSR: equ 0E7BH
+CURSU: equ 0E6EH
+CURSU1: equ 0E76H
+DACN1: equ 0BE3H
+DACN2: equ 0BDFH
+DACN3: equ 0BE0H
+DEL: equ 0EF2H
+DEL1: equ 0F0AH
+DEL2: equ 0F1DH
+DLY12: equ 0DA7H
+DLY12A: equ 0DAAH
+DLY3: equ 9A2H
+DMT: equ 857H
+DPCT1: equ 0DF9H
+DPRNT: equ 1194H
+DSP01: equ 0DC2H
+DSP02: equ 0D97H
+DSP04: equ 0D8DH
+DSPXY: equ 1171H
+DTADR: equ 1104H
+EDG1: equ 607H
+EDG1A: equ 60FH
+EDG2: equ 615H
+EDG3: equ 61DH
+EDGE: equ 601H
+EXADR: equ 1106H
+FD: equ 0C7H
+FD2: equ 0CAH
+FLAS1: equ 0A12H
+FLAS2: equ 0A0BH
+FLAS3: equ 0A0FH
+FLASH: equ 118EH
+FLSDT: equ 1192H
+GAPCK: equ 0FE2H
+GAPCK1: equ 0FEBH
+GAPCK2: equ 0FEDH
+GAPCK3: equ 0FFDH
+GETKY: equ 1BH
+GETL: equ 3H
+GETL0: equ 7ACH
+GETL0A: equ 7AFH
+GETL0B: equ 7B6H
+GETL0C: equ 7BEH
+GETL0D: equ 7C5H
+GETL1: equ 81AH
+GETL2: equ 803H
+GETL3: equ 85BH
+GETL5: equ 839H
+GETL6: equ 865H
+GETL6A: equ 86CH
+GETL6B: equ 878H
+GETLA: equ 886H
+GETLB: equ 863H
+GETLC: equ 84EH
+GETLD: equ 5E1H
+GETLR: equ 880H
+GOTO: equ 0BBH
+HEX: equ 3F9H
+HEX1: equ 3F2H
+HEX2: equ 3F5H
+HEXJ: equ 3E5H
+HLHEX: equ 410H
+HOM0: equ 409H
+HOM00: equ 0ED4H
+HOM1: equ 406H
+HOME: equ 3FBH
+HOOK: equ 120H
+IBUFE: equ 10F0H
+INST: equ 0F2DH
+INST1: equ 0F4FH
+INST1A: equ 0F37H
+INST2: equ 0F42H
+KANA: equ 0EEEH
+KANAF: equ 1170H
+KDATW: equ 116EH
+KTBL: equ 0BEAH
+KTBLC: equ 0CDAH
+KTBLG: equ 0C6AH
+KTBLGS: equ 0CA2H
+KTBLS: equ 0C32H
+L0270: equ 270H
+L028F: equ 28FH
+L029A: equ 29AH
+L02C4: equ 2C4H
+L02D5: equ 2D5H
+L02DB: equ 2DBH
+L0323: equ 323H
+L0336: equ 336H
+L03D5: equ 3D5H
+L041D: equ 41DH
+L041F: equ 41FH
+L0434: equ 434H
+L0444: equ 444H
+L045E: equ 45EH
+L0464: equ 464H
+L0485: equ 485H
+L048F: equ 48FH
+L049E: equ 49EH
+L04BB: equ 4BBH
+L04BD: equ 4BDH
+L04CB: equ 4CBH
+L04DD: equ 4DDH
+L0505: equ 505H
+L050A: equ 50AH
+L0510: equ 510H
+L052A: equ 52AH
+L0551: equ 551H
+L0552: equ 552H
+L0561: equ 561H
+L0563: equ 563H
+L056C: equ 56CH
+L0570: equ 570H
+L0572: equ 572H
+L06B1: equ 6B1H
+L06E7: equ 6E7H
+L06F0: equ 6F0H
+L0705: equ 705H
+L0717: equ 717H
+L071A: equ 71AH
+L0720: equ 720H
+L072F: equ 72FH
+L0733: equ 733H
+L0737: equ 737H
+L073E: equ 73EH
+L0743: equ 743H
+L0759: equ 759H
+L075B: equ 75BH
+L0760: equ 760H
+L0762: equ 762H
+L0767: equ 767H
+L076D: equ 76DH
+L077A: equ 77AH
+L078E: equ 78EH
+L0796: equ 796H
+L079C: equ 79CH
+L0917: equ 917H
+L091B: equ 91BH
+L098C: equ 98CH
+L09AB: equ 9ABH
+L09B9: equ 9B9H
+L09C7: equ 9C7H
+L09E2: equ 9E2H
+L09E8: equ 9E8H
+L0D27: equ 0D27H
+L0D2B: equ 0D2BH
+L0D37: equ 0D37H
+L0D3E: equ 0D3EH
+L0D57: equ 0D57H
+L0D80: equ 0D80H
+L0D89: equ 0D89H
+L0D90: equ 0D90H
+L0F13: equ 0F13H
+LETNL: equ 6H
+LOAD: equ 0D9H
+LOCK: equ 88BH
+M?TBL: equ 241H
+MANG: equ 1173H
+MANGE: equ 1179H
+MELDY: equ 30H
+MGP.D: equ 29DH
+MGP.I: equ 283H
+MGPNT: equ 117CH
+MLD1: equ 192H
+MLD1A: equ 1B6H
+MLD2: equ 1C6H
+MLD2A: equ 1C8H
+MLD3: equ 1CEH
+MLD4: equ 1D2H
+MLD5: equ 1D5H
+MLDSP: equ 2BEH
+MLDST: equ 2ABH
+MONIT: equ 0H
+MOT1: equ 6A8H
+MOT2: equ 6AFH
+MOT4: equ 6B9H
+MOT5: equ 6D8H
+MOT7: equ 6B7H
+MOT8: equ 6D0H
+MOT9: equ 6D7H
+MOTOR: equ 6A3H
+MSG: equ 15H
+MSG1: equ 896H
+MSG?2: equ 0F7H
+MSG?3: equ 100H
+MSG?7: equ 467H
+MSGE1: equ 118H
+MSGX: equ 18H
+MSGX1: equ 8A4H
+MSGX2: equ 8A7H
+MSG_1: equ 0D9EH
+MSG_2: equ 0DA0H
+MSG_3: equ 6F4H
+MSTA: equ 44H
+MSTOP: equ 700H
+MSTP: equ 47H
+MTBL: equ 229H
+NAME: equ 10F1H
+NL: equ 9H
+NOADD: equ 3E2H
+OCTV: equ 11A0H
+ONP1A: equ 1E1H
+ONP2: equ 1EDH
+ONP2A: equ 1FAH
+ONP2B: equ 200H
+ONP2C: equ 216H
+ONP2D: equ 21BH
+ONPU: equ 1DDH
+ONTYO: equ 119FH
+OPTBL: equ 259H
+PAGETP: equ 117DH
+PBIAS: equ 117AH
+PRNT: equ 12H
+PRNT2: equ 967H
+PRNT2A: equ 968H
+PRNT3: equ 96CH
+PRNT4: equ 96FH
+PRNT4A: equ 979H
+PRNT5: equ 955H
+PRNTS: equ 0CH
+PRNTT: equ 0FH
+PRTHL: equ 3B8H
+PRTHX: equ 3C3H
+RATIO: equ 11A1H
+RBY1: equ 630H
+RBY2: equ 649H
+RBY3: equ 654H
+RBYTE: equ 624H
+RDDAT: equ 2AH
+RDINF: equ 27H
+RET3: equ 69FH
+REV: equ 0A17H
+REV1: equ 0A25H
+REV2: equ 0A28H
+REVFLG: equ 1190H
+ROL2: equ 0F68H
+ROLD: equ 0F59H
+ROLEND: equ 117FH
+ROLTOP: equ 117BH
+ROLU: equ 0F9FH
+ROLU1: equ 0FA9H
+ROLUP: equ 5E8H
+RYTHM: equ 2C8H
+SCROL: equ 0E1FH
+SCROL1: equ 0E32H
+SCROL2: equ 0E42H
+SCROL3: equ 0E55H
+SFTLK: equ 118FH
+SG: equ 0C1H
+SIZE: equ 1102H
+SPAGE: equ 1191H
+SPV: equ 10F0H
+SS: equ 89H
+SS1: equ 8BH
+ST1: equ 95H
+ST2: equ 0A3H
+START: equ 4AH
+STRGF: equ 1193H
+STRT1: equ 69H
+SUMDT: equ 1197H
+SWEP0: equ 0A76H
+SWEP01: equ 0A74H
+SWEP11: equ 0A8EH
+SWEP2: equ 0AACH
+SWEP3: equ 0A92H
+SWEP6: equ 0A62H
+SWEP7: equ 0AA5H
+SWEP8: equ 0AA0H
+SWEP9: equ 0A8AH
+SWPW: equ 1164H
+SWRK: equ 119DH
+TEMPW: equ 119EH
+TIMFG: equ 119CH
+TIMIN: equ 379H
+TIMRD: equ 3BH
+TIMST: equ 33H
+TM0: equ 66AH
+TM1: equ 673H
+TM2: equ 676H
+TM3: equ 689H
+TM4: equ 69FH
+TMARK: equ 658H
+TMCNT: equ 1195H
+TVF1: equ 5A0H
+TVF2: equ 5A6H
+TVF3: equ 5BAH
+TVRFY: equ 59BH
+VERFY: equ 2DH
+WRDAT: equ 24H
+WRINF: equ 21H
+XTEMP: equ 41H
+_BRK: equ 0BC5H
diff --git a/software/asm/monitor_SA1510.asm b/software/asm/monitor_SA1510.asm
new file mode 100644
index 0000000..e137e14
--- /dev/null
+++ b/software/asm/monitor_SA1510.asm
@@ -0,0 +1,7 @@
+; Configurable parameters.
+COLW:   EQU     40                      ; Width of the display screen (ie. columns).
+ROW:    EQU     25                      ; Number of rows on display screen.
+SCRNSZ: EQU     COLW * ROW              ; Total size, in bytes, of the screen display area.
+MODE80C:EQU     0
+
+		INCLUDE "sa1510.asm"
diff --git a/software/asm/monitor_SA1510.obj b/software/asm/monitor_SA1510.obj
new file mode 100644
index 0000000..2cd2176
Binary files /dev/null and b/software/asm/monitor_SA1510.obj differ
diff --git a/software/asm/monitor_SA1510.sym b/software/asm/monitor_SA1510.sym
new file mode 100644
index 0000000..8c90ec8
--- /dev/null
+++ b/software/asm/monitor_SA1510.sym
@@ -0,0 +1,394 @@
+.CP1: equ 13AH
+.CR: equ 128H
+.CTBL: equ 168H
+.DSP03: equ 39DH
+.MANG: equ 0A2BH
+.MANG1: equ 0A4CH
+.MANG2: equ 3A6H
+.MANG3: equ 0A38H
+.MANG4: equ 0A45H
+.SCROL: equ 13DH
+?ADCN: equ 0BB9H
+?BEL: equ 2E5H
+?BELD: equ 0DB1H
+?BLNK: equ 0DA6H
+?BRK: equ 0D11H
+?CLER: equ 0FD8H
+?CLRFF: equ 0FDBH
+?DACN: equ 0BCEH
+?DINT: equ 0FDDH
+?DPCT: equ 0DDCH
+?DSP: equ 0DB5H
+?DSPA: equ 0D7CH
+?ER: equ 0CFH
+?FLAS: equ 9FFH
+?GET: equ 8B3H
+?GETL: equ 7A8H
+?KEY: equ 8CAH
+?KY1: equ 8D6H
+?KY10: equ 8EFH
+?KY11: equ 8EAH
+?KY2: equ 8F2H
+?KY3: equ 922H
+?KY4: equ 92FH
+?KY5: equ 91EH
+?KY6: equ 92AH
+?KY7: equ 93AH
+?KY9: equ 93FH
+?LOAD: equ 5F5H
+?LTNL: equ 980H
+?MLDY: equ 188H
+?MODE: equ 74DH
+?MSG: equ 893H
+?MSGX: equ 8A1H
+?NL: equ 97BH
+?PNT1: equ 0FB4H
+?PNT2: equ 0FCAH
+?PONT: equ 0FB1H
+?PRNT: equ 995H
+?PRT: equ 946H
+?PRTS: equ 993H
+?PRTT: equ 984H
+?RDD: equ 4EFH
+?RDI: equ 4CFH
+?RSTR: equ 0EE5H
+?RSTR1: equ 0EE6H
+?SAVE: equ 263H
+?SWEP: equ 0A50H
+?TEMP: equ 2ECH
+?TMR1: equ 361H
+?TMR1A: equ 364H
+?TMR2: equ 36BH
+?TMRD: equ 344H
+?TMST: equ 2FAH
+?VRFY: equ 575H
+?WRD: equ 470H
+?WRI: equ 436H
+ALPHA: equ 0EE1H
+ALPHI: equ 0EE2H
+AMPM: equ 119BH
+ASC: equ 3DAH
+ATBL: equ 0AB5H
+ATRB: equ 10F0H
+AUTCK: equ 9F1H
+AUTO2: equ 807H
+AUTO3: equ 7C4H
+AUTO5: equ 824H
+AUTOL: equ 810H
+AUTOL1: equ 812H
+BELL: equ 3EH
+BRKEY: equ 1EH
+BUFER: equ 11A3H
+CHGP1: equ 84BH
+CHGPA: equ 83EH
+CHGPK: equ 841H
+CHGPK1: equ 843H
+CLR8: equ 9E3H
+CLRS: equ 0EB3H
+CLRS1: equ 0ED1H
+COMNT: equ 1108H
+CR: equ 0F73H
+CR2: equ 0F8BH
+CR3: equ 0F99H
+CSMDT: equ 1199H
+CTBL: equ 0DFFH
+CURS1: equ 0E66H
+CURS2: equ 0E86H
+CURS3: equ 0E69H
+CURS4: equ 0E93H
+CURS5: equ 0EAAH
+CURS5A: equ 0E9FH
+CURS6: equ 0ED7H
+CURSD: equ 0E5DH
+CURSL: equ 0E95H
+CURSR: equ 0E7BH
+CURSU: equ 0E6EH
+CURSU1: equ 0E76H
+DACN1: equ 0BE3H
+DACN2: equ 0BDFH
+DACN3: equ 0BE0H
+DEL: equ 0EF2H
+DEL1: equ 0F0AH
+DEL2: equ 0F1DH
+DLY12: equ 0DA7H
+DLY12A: equ 0DAAH
+DLY3: equ 9A2H
+DMT: equ 857H
+DPCT1: equ 0DF9H
+DPRNT: equ 1194H
+DSP01: equ 0DC2H
+DSP02: equ 0D97H
+DSP04: equ 0D8DH
+DSPXY: equ 1171H
+DTADR: equ 1104H
+EDG1: equ 607H
+EDG1A: equ 60FH
+EDG2: equ 615H
+EDG3: equ 61DH
+EDGE: equ 601H
+EXADR: equ 1106H
+FD: equ 0C7H
+FD2: equ 0CAH
+FLAS1: equ 0A12H
+FLAS2: equ 0A0BH
+FLAS3: equ 0A0FH
+FLASH: equ 118EH
+FLSDT: equ 1192H
+GAPCK: equ 0FE2H
+GAPCK1: equ 0FEBH
+GAPCK2: equ 0FEDH
+GAPCK3: equ 0FFDH
+GETKY: equ 1BH
+GETL: equ 3H
+GETL0: equ 7ACH
+GETL0A: equ 7AFH
+GETL0B: equ 7B6H
+GETL0C: equ 7BEH
+GETL0D: equ 7C5H
+GETL1: equ 81AH
+GETL2: equ 803H
+GETL3: equ 85BH
+GETL5: equ 839H
+GETL6: equ 865H
+GETL6A: equ 86CH
+GETL6B: equ 878H
+GETLA: equ 886H
+GETLB: equ 863H
+GETLC: equ 84EH
+GETLD: equ 5E1H
+GETLR: equ 880H
+GOTO: equ 0BBH
+HEX: equ 3F9H
+HEX1: equ 3F2H
+HEX2: equ 3F5H
+HEXJ: equ 3E5H
+HLHEX: equ 410H
+HOM0: equ 409H
+HOM00: equ 0ED4H
+HOM1: equ 406H
+HOME: equ 3FBH
+HOOK: equ 128H
+IBUFE: equ 10F0H
+INST: equ 0F2DH
+INST1: equ 0F4FH
+INST1A: equ 0F37H
+INST2: equ 0F42H
+KANA: equ 0EEEH
+KANAF: equ 1170H
+KDATW: equ 116EH
+KTBL: equ 0BEAH
+KTBLC: equ 0CDAH
+KTBLG: equ 0C6AH
+KTBLGS: equ 0CA2H
+KTBLS: equ 0C32H
+L0270: equ 270H
+L028F: equ 28FH
+L029A: equ 29AH
+L02C4: equ 2C4H
+L02D5: equ 2D5H
+L02DB: equ 2DBH
+L0323: equ 323H
+L0336: equ 336H
+L03D5: equ 3D5H
+L041D: equ 41DH
+L041F: equ 41FH
+L0434: equ 434H
+L0444: equ 444H
+L045E: equ 45EH
+L0464: equ 464H
+L0485: equ 485H
+L048F: equ 48FH
+L049E: equ 49EH
+L04BB: equ 4BBH
+L04BD: equ 4BDH
+L04CB: equ 4CBH
+L04DD: equ 4DDH
+L0505: equ 505H
+L050A: equ 50AH
+L0510: equ 510H
+L052A: equ 52AH
+L0551: equ 551H
+L0552: equ 552H
+L0561: equ 561H
+L0563: equ 563H
+L056C: equ 56CH
+L0570: equ 570H
+L0572: equ 572H
+L06B1: equ 6B1H
+L06E7: equ 6E7H
+L06F0: equ 6F0H
+L0705: equ 705H
+L0717: equ 717H
+L071A: equ 71AH
+L0720: equ 720H
+L072F: equ 72FH
+L0733: equ 733H
+L0737: equ 737H
+L073E: equ 73EH
+L0743: equ 743H
+L0759: equ 759H
+L075B: equ 75BH
+L0760: equ 760H
+L0762: equ 762H
+L0767: equ 767H
+L076D: equ 76DH
+L077A: equ 77AH
+L078E: equ 78EH
+L0796: equ 796H
+L079C: equ 79CH
+L0917: equ 917H
+L091B: equ 91BH
+L098C: equ 98CH
+L09AB: equ 9ABH
+L09B9: equ 9B9H
+L09C7: equ 9C7H
+L09E2: equ 9E2H
+L09E8: equ 9E8H
+L0D27: equ 0D27H
+L0D2B: equ 0D2BH
+L0D37: equ 0D37H
+L0D3E: equ 0D3EH
+L0D57: equ 0D57H
+L0D80: equ 0D80H
+L0D89: equ 0D89H
+L0D90: equ 0D90H
+L0F13: equ 0F13H
+LETNL: equ 6H
+LOAD: equ 0D9H
+LOCK: equ 88BH
+M?TBL: equ 241H
+MANG: equ 1173H
+MANGE: equ 1179H
+MELDY: equ 30H
+MGP.D: equ 29DH
+MGP.I: equ 283H
+MGPNT: equ 117CH
+MLD1: equ 192H
+MLD1A: equ 1B6H
+MLD2: equ 1C6H
+MLD2A: equ 1C8H
+MLD3: equ 1CEH
+MLD4: equ 1D2H
+MLD5: equ 1D5H
+MLDSP: equ 2BEH
+MLDST: equ 2ABH
+MONIT: equ 0H
+MOT1: equ 6A8H
+MOT2: equ 6AFH
+MOT4: equ 6B9H
+MOT5: equ 6D8H
+MOT7: equ 6B7H
+MOT8: equ 6D0H
+MOT9: equ 6D7H
+MOTOR: equ 6A3H
+MSG: equ 15H
+MSG1: equ 896H
+MSG?2: equ 0F7H
+MSG?3: equ 100H
+MSG?7: equ 467H
+MSGE1: equ 118H
+MSGX: equ 18H
+MSGX1: equ 8A4H
+MSGX2: equ 8A7H
+MSG_1: equ 0D9EH
+MSG_2: equ 0DA0H
+MSG_3: equ 6F4H
+MSTA: equ 44H
+MSTOP: equ 700H
+MSTP: equ 47H
+MTBL: equ 229H
+NAME: equ 10F1H
+NL: equ 9H
+NOADD: equ 3E2H
+OCTV: equ 11A0H
+ONP1A: equ 1E1H
+ONP2: equ 1EDH
+ONP2A: equ 1FAH
+ONP2B: equ 200H
+ONP2C: equ 216H
+ONP2D: equ 21BH
+ONPU: equ 1DDH
+ONTYO: equ 119FH
+OPTBL: equ 259H
+PAGETP: equ 117DH
+PBIAS: equ 117AH
+PRNT: equ 12H
+PRNT2: equ 967H
+PRNT2A: equ 968H
+PRNT3: equ 96CH
+PRNT4: equ 96FH
+PRNT4A: equ 979H
+PRNT5: equ 955H
+PRNTS: equ 0CH
+PRNTT: equ 0FH
+PRTHL: equ 3B8H
+PRTHX: equ 3C3H
+RATIO: equ 11A1H
+RBY1: equ 630H
+RBY2: equ 649H
+RBY3: equ 654H
+RBYTE: equ 624H
+RDDAT: equ 2AH
+RDINF: equ 27H
+RET3: equ 69FH
+REV: equ 0A17H
+REV1: equ 0A25H
+REV2: equ 0A28H
+REVFLG: equ 1190H
+ROL2: equ 0F68H
+ROLD: equ 0F59H
+ROLEND: equ 117FH
+ROLTOP: equ 117BH
+ROLU: equ 0F9FH
+ROLU1: equ 0FA9H
+ROLUP: equ 5E8H
+RYTHM: equ 2C8H
+SCROL: equ 0E1FH
+SCROL1: equ 0E32H
+SCROL2: equ 0E42H
+SCROL3: equ 0E55H
+SFTLK: equ 118FH
+SG: equ 0C1H
+SIZE: equ 1102H
+SPAGE: equ 1191H
+SPV: equ 10F0H
+SS: equ 89H
+SS1: equ 8BH
+ST1: equ 95H
+ST2: equ 0A3H
+START: equ 4AH
+STRGF: equ 1193H
+STRT1: equ 69H
+SUMDT: equ 1197H
+SWEP0: equ 0A76H
+SWEP01: equ 0A74H
+SWEP11: equ 0A8EH
+SWEP2: equ 0AACH
+SWEP3: equ 0A92H
+SWEP6: equ 0A62H
+SWEP7: equ 0AA5H
+SWEP8: equ 0AA0H
+SWEP9: equ 0A8AH
+SWPW: equ 1164H
+SWRK: equ 119DH
+TEMPW: equ 119EH
+TIMFG: equ 119CH
+TIMIN: equ 379H
+TIMRD: equ 3BH
+TIMST: equ 33H
+TM0: equ 66AH
+TM1: equ 673H
+TM2: equ 676H
+TM3: equ 689H
+TM4: equ 69FH
+TMARK: equ 658H
+TMCNT: equ 1195H
+TVF1: equ 5A0H
+TVF2: equ 5A6H
+TVF3: equ 5BAH
+TVRFY: equ 59BH
+VERFY: equ 2DH
+WRDAT: equ 24H
+WRINF: equ 21H
+XTEMP: equ 41H
+_BRK: equ 0BC5H
diff --git a/software/asm/monitor_mz-1r12.asm b/software/asm/monitor_mz-1r12.asm
new file mode 100644
index 0000000..0912cc6
--- /dev/null
+++ b/software/asm/monitor_mz-1r12.asm
@@ -0,0 +1,401 @@
+; V1.00
+;
+; To compile use:
+;
+; GLASS Z80 Assembler
+;
+; java -jar ../tools/glass.jar mz-1r12.asm mz-1r12.obj mz-1r12.sym
+
+
+
+LETNL   EQU     00006h
+PRNT    EQU     00012h
+MSG     EQU     00015h
+GETKY   EQU     0001Bh
+RDINF   EQU     00027h
+RDDAT   EQU     0002Ah
+ST1     EQU     000ADh
+QNL     EQU     00918h
+
+NAME    EQU     010F1h
+SIZE    EQU     01102h
+DTADR   EQU     01104h
+COMNT   EQU     01108h
+
+; Macro to align boundaries.
+ALIGN:  MACRO ?boundary, ?fill
+        DS    ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, ?fill
+        ENDM
+
+        ORG 0E800h
+
+MZ1R12:
+        NOP
+        LD      A,016h
+        CALL    PRNT
+        CALL    LETNL
+        CALL    LETNL
+ST1X:
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LE83B                                                 ; 'PRESS R, W OR M'
+        CALL    MSG
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LE85B                                                 ; 'R: READ   S-RAM'
+        CALL    MSG
+        CALL    LETNL
+        LD      DE,LE877                                                 ; 'W: WRITE  S-RAM'
+        CALL    MSG
+        CALL    LETNL
+        LD      DE,LE893                                                 ; 'M: MONITOR'
+        CALL    MSG
+        CALL    LETNL
+        JR      LE8AB
+
+
+LE83B:  DB      "           P",005h,"RESS",005h," R , W ",005h,"OR",005h," M",00Dh
+LE85B:  DB      "            R:",005h,"READ",005h,"  S-RAM",00Dh
+LE877:  DB      "            W:",005h,"WRITE",005h," S-RAM",00Dh
+LE893:  DB      "            M:",005h,"MONITOR",005h,00Dh
+
+
+LE8AB:
+        NOP
+        CALL    GETKY
+        CP      'M'
+        JP      Z,MON
+        CP      'W'
+        JP      Z,LE96A
+        CP      'R'
+        JP      Z,LE8C1
+        JP      NZ,LE8AB
+
+LE8C1:
+        NOP
+        LD      A,016h
+        CALL    PRNT
+        CALL    LETNL
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LEB1B                                                 ; 'LOADING PROGRAM FROM S-RAM'
+        CALL    MSG
+        CALL    LETNL
+        CALL    LETNL
+        CALL    CHECK
+        IN      A,(0F8h)                                                 ; Counter reset
+        IN      A,(0F9h)
+        LD      C,A
+        IN      A,(0F9h)
+        LD      B,A
+        IN      A,(0F9h)
+        LD      L,A
+        IN      A,(0F9h)
+        LD      H,A
+        IN      A,(0F9h)
+        LD      E,A
+        IN      A,(0F9h)
+        LD      D,A
+        PUSH    DE
+        LD      D,B
+        LD      E,C
+        IN      A,(0F9h)
+        LD      C,A
+        IN      A,(0F9h)
+        LD      B,A
+        IN      A,(0F9h)
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      C,0F9h
+        LD      A,E
+        OR      A
+        JR      Z,LE90A
+        LD      B,A
+LE908:
+        INIR
+LE90A:
+        LD      B,000h
+        DEC     D
+        JP      P,LE908
+        POP     DE                                                       ; Data adr
+        POP     BC                                                       ; Size
+        CALL    SUM
+        POP     DE
+        OR      A
+        SBC     HL,DE
+        JR      NZ,LE956
+        POP     HL
+        JP      (HL)
+
+
+;
+;       sum check
+;
+; IN BC=Size
+;    DE=Data adr
+; EXIT HL=Check sum
+;
+SUM:
+        PUSH    BC
+        PUSH    DE
+        EXX
+        LD      HL,00000h                                                ; HL'= Check sum clr
+        LD      C,008h                                                   ; C' = Loop count
+        EXX
+SUMCK1:
+        LD      A,B                                                      ; BC = Size
+        OR      C
+        JR      Z,SUMCK2
+        LD      A,(DE)                                                   ; DE = Data adrs
+        EXX
+        LD      B,C                                                      ; BC'
+SUMCK3:
+        RLCA
+        JR      NC,LE931
+        INC     HL                                                       ; HL' = Check sum data
+LE931:
+        DJNZ    SUMCK3
+        EXX
+        INC     DE                                                       ; DE
+        DEC     BC                                                       ; BC
+        JP      SUMCK1
+SUMCK2:
+        EXX
+        POP     DE
+        POP     BC
+        RET
+
+
+
+;
+;       Information's sum check
+;
+CHECK:
+        IN      A,(0F8h)                                                 ; Counter reset
+        LD      BC,00800h                                                ; B=Byte Counter C=Sum Counter
+CK1:
+        IN      A,(0F9h)                                                 ; Counter=Counter+1
+        PUSH    BC
+        LD      B,008h                                                   ; Bit Counter
+CK2:
+        RLCA
+        JR      NC,LE94B
+        INC     C
+LE94B:
+        DJNZ    CK2
+        LD      A,C
+        POP     BC
+        LD      C,A
+        DJNZ    CK1
+        IN      A,(0F9h)
+        CP      C
+        RET
+
+
+LE956:
+        LD      A,016h
+        CALL    PRNT
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LEA8F                                                 ; 'CHECK SUM ERROR'
+        CALL    LEA3D
+        JP      ST1X
+
+LE96A:
+        LD      A,016h
+        CALL    PRNT
+        CALL    LETNL
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LEAAC                                                 ; 'S-RAM PROGRAMMING'
+        CALL    LEA36
+        LD      DE,LEACB                                                 ; 'SET MASTER TAPE  PLAY'
+        LD      A,011h
+        LD      HL,0D8F0h
+        CALL    LEA4A
+        CALL    LETNL
+        CALL    LEA39
+        CALL    RDINF
+        PUSH    AF
+        PUSH    BC
+        LD      BC,(SIZE)
+        LD      A,07Fh
+        CP      B
+        JR      C,LE9A8
+        JR      NZ,LE9A4
+        LD      A,0F6h
+        CP      C
+        JR      C,LE9A8
+LE9A4:
+        POP     BC
+        POP     AF
+        JR      LE9AD
+LE9A8:
+        POP     BC
+        POP     AF
+        JP      LEA74
+
+LE9AD:
+        LD      A,000h
+        LD      HL,0D0F0h
+        CALL    LEA4A
+        LD      A,071h
+        LD      HL,0D8F0h
+        CALL    LEA4A
+        LD      A,002h
+        JP      C,LEA42
+        CALL    LETNL
+        LD      DE,LEAF1                                                 ; 'FOUND : '
+        CALL    LEA3D
+        LD      DE,NAME
+        PUSH    DE
+        RST     018h
+        CALL    LETNL
+        LD      DE,LEB06                                                 ; 'LOADING : '
+        CALL    LEA3D
+        POP     DE
+        RST     018h
+;
+;       Read data block
+;
+        CALL    RDDAT
+        JR      C,LEA42
+;
+;       Counter reset
+;
+        IN      A,(0F8h)
+;
+;       Sum check for data
+;
+        LD      DE,(DTADR)
+        LD      BC,(SIZE)
+        PUSH    DE
+        PUSH    BC
+        CALL    SUM
+        LD      (COMNT),HL
+;
+;       Write information (8Byte)
+;
+        LD      HL,SIZE
+        LD      BC,008FAh                                                ; B=Byte Counter
+        PUSH    HL
+        PUSH    BC
+        OTIR
+        POP     BC
+        POP     HL
+;
+;       Sum check for information block
+;           AccCheck sum data
+;
+        PUSH    DE                                                       ; DE Size
+        LD      D,000h                                                   ; Sum Counter
+WCK1:
+        PUSH    BC
+        LD      B,008h
+        LD      A,(HL)
+WCK2:
+        RLCA
+        JR      NC,WCK3
+        INC     D
+WCK3:
+        DJNZ    WCK2
+        INC     HL
+        POP     BC
+        DJNZ    WCK1
+        LD      A,D
+        POP     DE
+        OUT     (0FAh),A
+;
+;       Write data block
+;
+        POP     DE                                                       ; DE Size
+        POP     HL                                                       ; HL Data adrs
+        LD      A,E
+        OR      A
+        JR      Z,LEA1C
+        LD      B,E
+LEA1A:
+        OTIR
+LEA1C:
+        LD      B,000h
+        DEC     D
+        JP      P,LEA1A
+        LD      A,016h
+        CALL    PRNT
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LEB8C                                                 ; 'WRITING S-RAM O.K.!'
+        CALL    MSG
+        JP      ST1X
+
+
+LEA36:
+        CALL    QNL
+LEA39:
+        RST     018h
+        JP      QNL
+
+LEA3D:
+        CALL    QNL
+        RST     018h
+        RET
+
+LEA42:
+        CP      002h
+        JP      Z,LEA60
+        JP      LE956
+
+LEA4A:
+        LD      B,006h
+LEA4C:
+        LD      (HL),A
+        INC     HL
+        DEC     B
+        JR      NZ,LEA4C
+        RET
+
+MON:
+        LD      A,016h
+        CALL    PRNT
+        LD      DE,LEB3E                                                 ; '** MONITOR 1Z-009A **'
+        CALL    MSG
+        JP      ST1
+
+LEA60:
+        LD      A,016h
+        CALL    PRNT
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LEB77                                                 ; 'BREAK !'
+        CALL    MSG
+        JP      ST1X
+
+LEA74:
+        LD      DE,00000h
+        LD      (SIZE),DE
+        LD      A,016h
+        CALL    PRNT
+        CALL    LETNL
+        CALL    LETNL
+        LD      DE,LEBAD                                                 ; 'FILE IS TOO LONG'
+        CALL    MSG
+        JP      ST1X
+
+
+LEA8F:  DB      "           C",005h,"HECK SUM ERROR",005h,00Dh
+LEAAC:  DB      "           S-RAM ",005h,"PROGRAMMING",005h,00Dh
+LEACB:  DB      "        S",005h,"ET MASTER TAPE",005h,"   ",07Fh,"P",005h,"LAY",005h,"  ",00Dh
+LEAF1:  DB      "         F",005h,"OUND",005h,"  : ",00Dh
+LEB06:  DB      "         L",005h,"OADING",005h,": ",00Dh
+LEB1B:  DB      "      L",005h,"OADING PROGRAM FROM ",005h,"S-RAM",00Dh
+LEB3E:  DB      "**  MONITOR 1Z-009A  **",00Dh
+LEB56:  DB      "           R",005h,"EADING",005h," S-RAM O.K.!",00Dh
+LEB77:  DB      "           B",005h,"REAK",005h," !",00Dh
+LEB8C:  DB      "           W",005h,"RITING",005h," S-RAM O.K.!",00Dh
+LEBAD:  DB      "           F",005h,"ILE IS TOO LONG",005h,00Dh
+
+; the following is only to get the original length of 4096 bytes
+
+        ALIGN   0F7FFh, 0FFh
+        DB      0FFh
diff --git a/software/asm/monitor_mz-1r12.obj b/software/asm/monitor_mz-1r12.obj
new file mode 100644
index 0000000..e338c7d
Binary files /dev/null and b/software/asm/monitor_mz-1r12.obj differ
diff --git a/software/asm/monitor_mz-1r12.sym b/software/asm/monitor_mz-1r12.sym
new file mode 100644
index 0000000..b1bab48
--- /dev/null
+++ b/software/asm/monitor_mz-1r12.sym
@@ -0,0 +1,49 @@
+CHECK: equ 0E93DH
+CK1: equ 0E942H
+CK2: equ 0E947H
+LE83B: equ 0E83BH
+LE85B: equ 0E85BH
+LE877: equ 0E877H
+LE893: equ 0E893H
+LE8AB: equ 0E8ABH
+LE8C1: equ 0E8C1H
+LE908: equ 0E908H
+LE90A: equ 0E90AH
+LE931: equ 0E931H
+LE94B: equ 0E94BH
+LE956: equ 0E956H
+LE96A: equ 0E96AH
+LE9A4: equ 0E9A4H
+LE9A8: equ 0E9A8H
+LE9AD: equ 0E9ADH
+LEA1A: equ 0EA1AH
+LEA1C: equ 0EA1CH
+LEA36: equ 0EA36H
+LEA39: equ 0EA39H
+LEA3D: equ 0EA3DH
+LEA42: equ 0EA42H
+LEA4A: equ 0EA4AH
+LEA4C: equ 0EA4CH
+LEA60: equ 0EA60H
+LEA74: equ 0EA74H
+LEA8F: equ 0EA8FH
+LEAAC: equ 0EAACH
+LEACB: equ 0EACBH
+LEAF1: equ 0EAF1H
+LEB06: equ 0EB06H
+LEB1B: equ 0EB1BH
+LEB3E: equ 0EB3EH
+LEB56: equ 0EB56H
+LEB77: equ 0EB77H
+LEB8C: equ 0EB8CH
+LEBAD: equ 0EBADH
+MON: equ 0EA52H
+MZ1R12: equ 0E800H
+ST1X: equ 0E80CH
+SUM: equ 0E91DH
+SUMCK1: equ 0E926H
+SUMCK2: equ 0E939H
+SUMCK3: equ 0E92DH
+WCK1: equ 0EA01H
+WCK2: equ 0EA05H
+WCK3: equ 0EA09H
diff --git a/software/asm/mz-1e14.asm b/software/asm/mz-1e14.asm
new file mode 100644
index 0000000..7f7484c
--- /dev/null
+++ b/software/asm/mz-1e14.asm
@@ -0,0 +1,1483 @@
+; V1.01
+;
+; To compile use:
+;
+; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor.
+;
+; Available from:
+;   - http://www.falstaff.demon.co.uk/cross.html
+;   - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip
+;   - and many Simtel mirrors.
+;
+; as80 -i -l -n -x2 -v mz-1e14.asm
+
+
+
+
+SIOAD   EQU     0F4h
+SIOBD   EQU     0F5h
+SIOAC   EQU     0F6h
+SIOBC   EQU     0F7h
+
+
+
+;       RxD_A   <-  RDDT (ReaDDaTa)
+;       RxC_A   <-    (read data clock)
+;       TxD_A   ->  #WRDT (WRiteDaTa)
+;       TxC_A   <-  6.5MHz / 4 / 16 = 101562,5Hz
+;       CTS_A    <-    #WRPR (WRitePRotect)
+;        RTS_A    ->    #WRGA (WRiteGAte)
+;       DCD_A   <-  #HDST (HeaDSeT (disk test)
+;
+;       RTS_B   ->    (?)
+;       DCD_B   <-  #HOME ()
+;       DTR_B   ->  #MTON (MoTorON)
+
+
+
+
+GETL    EQU     00003h
+NL      EQU     00009h
+PRNT    EQU     00012h
+GETKY   EQU     0001Bh
+BRKEY   EQU     0001Eh
+CMY0    EQU     0005Bh
+MSGE1   EQU     00147h
+DOT4DE  EQU     002A6h
+?TMST   EQU     00308h
+SPHEX   EQU     003B1h
+SLPT    EQU     003D5h
+HLHEX   EQU     00410h
+_2HEX   EQU     0041Fh
+?WRI    EQU     00436h
+LLPT    EQU     00470h
+?WRD    EQU     00475h
+?RDI    EQU     004D8h
+?RDD    EQU     004F8h
+?VRFY   EQU     00588h
+NLPHL   EQU     005FAh
+?KEY    EQU     008CAh
+?PRTS   EQU     00920h
+MSGOK   EQU     00942h
+PRNT3   EQU     0096Ch
+MSGSV   EQU     0098Bh
+MSG?2   EQU     009A0h
+?BRK    EQU     00A32h
+?ADCN   EQU     00BB9h
+?BLNK   EQU     00DA6h
+?DPCT   EQU     00DDCh
+
+BRKCD   EQU     00
+NTFECD  EQU     40
+HDERCD  EQU     41
+WPRTCD  EQU     46
+QNTRCD  EQU     50
+NFSECD  EQU     53
+UNFMCD  EQU     54
+
+ATRB    EQU     010F0h
+NAME    EQU     010F1h
+SIZE    EQU     01102h
+DTADR   EQU     01104h
+EXADR   EQU     01106h
+COMNT   EQU     01108h
+
+NAMSIZ  EQU     011h
+OBJCD   EQU     001h
+                                                                         ; QD command table
+QDPA    EQU     01130h                                                   ; QD code 1
+QDPB    EQU     01131h                                                   ; QD code 2
+QDPC    EQU     01132h                                                   ; QD header startaddress
+QDPE    EQU     01134h                                                   ; QD header length
+QDCPA   EQU     0113Bh                                                   ; QD error flag
+HDPT    EQU     0113Ch                                                   ; QD new headpoint possition
+HDPT0   EQU     0113Dh                                                   ; QD actual headpoint possition
+FNUPS   EQU     0113Eh
+FNUPF   EQU     01140h
+FNA     EQU     01141h                                                   ; File Number A (actual file number)
+FNB     EQU     01142h                                                   ; File Number B (next file number)
+MTF     EQU     01143h                                                   ; QD motor flag
+RTYF    EQU     01144h
+SYNCF   EQU     01146h                                                   ; SyncFlags
+RETSP   EQU     01147h
+DSPXY   EQU     01171h
+DPRNT   EQU     01194h
+SWRK    EQU     0119Dh
+BUFER   EQU     011A3h
+QDIRBF  EQU     0CD90h
+
+; Macro to align boundaries.
+ALIGN:  MACRO ?boundary
+        DS    ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, 0FFh
+        ENDM
+
+        ORG     0E800h
+
+MZ1E14:
+LE800:
+        NOP
+        JP LE80A
+        JP ST1X
+QDIOS:
+        JP QDIOS1
+
+LE80A:
+        LD A,0C6h                                                        ; clear screen
+        CALL ?DPCT
+        XOR A
+        LD (DPRNT),A
+        DI
+        XOR A
+        LD DE,00000h
+        CALL ?TMST
+        LD A,001h
+        OUT (SIOBC),A                                                    ; select Write Register 1
+        XOR A
+        OUT (SIOBC),A                                                    ; Rx INT DISABLE
+        CALL GETKY
+        CP 'M'
+        JR Z,MON
+        CP 'Q'
+        JR Z,QBT
+        CALL LEB22                                                       ; check ROM at 0xF000 (FDD)
+        CALL Z,0F006h
+        JR QBT
+;
+;===============================
+;
+;       Quick disk boot-up
+;
+;===============================
+;
+QBT:
+        CALL IOFRS                                                       ; IO Flag ReSet
+        CALL NL
+        CALL QDRCK                                                       ; QuickDisk Ready ChecK
+        JR C,LE868
+        LD A,00Dh                                                        ; set filename to ""
+        LD (BUFER),A
+        CALL HDPCL                                                       ; HeaD Point CLear
+;
+;       Error return set
+;
+        LD A,001h
+        LD (QDCPA),A
+        LD HL,LE86B
+        LD SP,010EEh
+        EX (SP),HL
+;
+;
+        CALL FILSCH                                                      ; filesearch
+        JP C,LEBAC
+        LD A,(ATRB)
+        CP OBJCD                                                         ; is it an "OBJ" file
+        JR NZ,LE871
+;
+;       Quick disk boot
+;
+        LD DE,LEB27
+        RST 018h
+        JP DSFLNA
+
+LE868:
+        LD DE,LEB37
+LE86B:
+        CALL NL
+        RST 018h
+        JR LE87D
+LE871:
+        LD A,006h                                                        ; Motor off
+        LD (QDPA),A
+        CALL QDIOS
+        LD DE,LED4C
+        RST 018h
+LE87D:
+        CALL NL
+
+MON:
+        LD DE,DISCLR                                                     ; '**  MONITOR 9Z-503M  **'
+        RST 018h
+
+
+ST1X:
+        CALL NL
+        LD A,'*'
+        CALL PRNT
+        LD DE,BUFER
+        CALL GETL
+ST2X:
+        LD A,(DE)
+        INC DE
+        CP 00Dh
+        JR Z,ST1X
+        CP 'J'                                                           ; JUMP
+        JR Z,GOTOX
+        CP 'L'                                                           ; Load CMT
+        JR Z,LOADX
+        CP 'F'                                                           ; Floppy boot
+        JR Z,FDCK
+        CP 'B'                                                           ; Bell
+        JP Z,SGX
+        CP '#'
+        JP Z,LEA6A
+        CP 'P'                                                           ; Printer test
+        JP Z,PTESTX
+        CP 'M'                                                           ; Memory correction
+        JP Z,MCORX
+        CP 'S'                                                           ; Save CMT
+        JP Z,SAVEX
+        CP 'V'                                                           ; Verify
+        JP Z,VRFYX
+        CP 'D'                                                           ; Dump memory
+        JP Z,DUMPX
+        CP 'Q'                                                           ; Quick disk cmd.
+        JR NZ,ST2X
+;
+;       Quick disk cmd.
+;
+QUICK:
+        LD HL,00000h
+        LD (0113Ah),HL
+        LD A,(DE)
+        CP 'L'                                                           ; Load QD
+        JP Z,QL
+        CP 'D'                                                           ; Directory
+        JP Z,QD
+ST1X1:
+        JR ST1X
+
+
+FDCK:
+        LD A,(DE)
+        CP 00Dh
+        JR NZ,ST1X1
+        CALL LEB22
+        CALL Z,0F006h
+        JR ST1X1
+?ERX:
+        CP 002h
+        JR Z,ST1X1
+        CALL NL
+        LD DE,MSGE1                                                      ; 'CHECK SUM ER.'
+        RST 018h
+        JR ST1X1
+BGETLX:
+        EX (SP),HL
+        POP BC
+        LD DE,BUFER
+        CALL GETL
+        LD A,(DE)
+        CP 01Bh
+        JR Z,ST1X1
+        JP (HL)
+
+HEXIYX:
+        EX (SP),IY
+        POP AF
+        CALL HLHEX
+        JR C,ST1X1
+        JP (IY)
+
+GOTOX:
+        CALL HEXIYX
+        JP (HL)
+
+               
+LOADX:
+        CALL ?RDI
+        JR C,?ERX
+        CALL NL
+        LD DE,MSG?2                                                      ; 'LOADING '
+        RST 018h
+        LD DE,NAME
+        RST 018h
+        XOR A
+        LD (BUFER),A
+        LD HL,(DTADR)
+        LD A,H
+        OR L
+        JR NZ,LE941
+        LD HL,(EXADR)
+        LD A,H
+        OR L
+        JR NZ,LE941
+        LD A,0FFh
+        LD (BUFER),A
+        LD HL,01200h
+        LD (DTADR),HL
+LE941:
+        CALL ?RDD
+        JR C,?ERX
+        LD A,(BUFER)
+        CP 0FFh
+        JR Z,LE954
+        LD BC,00100h
+        LD HL,(EXADR)
+        JP (HL)
+LE954:
+        OUT (0E0h),A
+        LD HL,01200h
+        LD DE,00000h
+        LD BC,(SIZE)
+        LDIR
+        LD BC,00100h
+        JP 00000h
+
+PTESTX:
+        LD A,(DE)
+        CP '&'                                                           ; plotter test
+        JR NZ,PTST1X
+PTST0X:
+        INC DE
+        LD A,(DE)
+        CP 'L'                                                           ; 40 in 1 line
+        JR Z,.LPTX
+        CP 'S'                                                           ; 80 in 1 line
+        JR Z,..LPTX
+        CP 'C'                                                           ; Pen change
+        JR Z,PENX
+        CP 'G'                                                           ; Graph mode
+        JR Z,PLOTX
+        CP 'T'                                                           ; Test
+        JR Z,PTRNX
+;
+PTST1X:
+        CALL PMSGX
+ST1X2:
+        JP ST1X1
+.LPTX:
+        LD DE,LLPT                                                       ; 01-09-09-0B-0D
+        JR PTST1X
+..LPTX:
+        LD DE,SLPT                                                       ; 01-09-09-09-0D
+        JR PTST1X
+PTRNX:
+        LD A,004h                                                        ; Test pattern
+        JR LE999
+PLOTX:
+        LD A,002h                                                        ; Graph mode
+LE999:
+        CALL LPRNTX
+        JR PTST0X
+PENX:
+        LD A,01Dh                                                        ; 1 change code (text mode)
+        JR LE999
+;
+;
+;       1 char print to $LPT
+;
+;        in: ACC print data
+;
+;
+LPRNTX:
+        LD C,000h                                                        ; RDAX test
+        LD B,A                                                           ; print data store
+        CALL RDAX
+        LD A,B
+        OUT (0FFh),A                                                     ; data out
+        LD A,080h                                                        ; RDP high
+        OUT (0FEh),A
+        LD C,001h                                                        ; RDA test
+        CALL RDAX
+        XOR A                                                            ; RDP low
+        OUT (0FEh),A
+        RET
+;
+;       $LPT msg.
+;       in: DE data low address
+;       0D msg. end
+;
+PMSGX:
+        PUSH DE
+        PUSH BC
+        PUSH AF
+PMSGX1:
+        LD A,(DE)                                                        ; ACC = data
+        CALL LPRNTX
+        LD A,(DE)
+        INC DE
+        CP 00Dh                                                          ; end ?
+        JR NZ,PMSGX1
+        POP AF
+        POP BC
+        POP DE
+        RET
+;
+;       RDA check
+;
+;       BRKEY in to monitor return
+;       in: C RDA code
+;
+RDAX:
+        IN A,(0FEh)
+        AND 00Dh
+        CP C
+        RET Z
+        CALL BRKEY
+        JR NZ,RDAX
+        LD SP,ATRB
+        JR ST1X2
+;
+;       Memory correction
+;       command 'M'
+;
+MCORX:
+        CALL HEXIYX                                                      ; correction address
+MCORX1:
+        CALL NLPHL                                                       ; corr. adr. print
+        CALL SPHEX                                                       ; ACC ASCII display
+        CALL ?PRTS                                                       ; space print
+        CALL BGETLX                                                      ; get data & check data
+        CALL HLHEX                                                       ; HLASCII(DE)
+        JR C,MCRX3
+        CALL DOT4DE                                                      ; INC DE * 4
+        INC DE
+        CALL _2HEX                                                       ; data check
+        JR C,MCORX1
+        CP (HL)
+        JR NZ,MCORX1
+        INC DE
+        LD A,(DE)
+        CP 00Dh                                                          ; not correction
+        JR Z,MCRX2
+        CALL _2HEX                                                       ; ACCHL(ASCII)
+        JR C,MCORX1
+        LD (HL),A                                                        ; data correct
+MCRX2:
+        INC HL
+        JR MCORX1
+MCRX3:
+        LD H,B                                                           ; memory address
+        LD L,C
+        JR MCORX1
+;
+;       Programm save
+;
+;       cmd. 'S'
+;
+SAVEX:
+        CALL HEXIYX                                                      ; Start address
+        LD (DTADR),HL                                                    ; data adress buffer
+        LD B,H
+        LD C,L
+        CALL DOT4DE
+        CALL HEXIYX                                                      ; End address
+        SBC HL,BC                                                        ; byte size
+        INC HL
+        LD (SIZE),HL                                                     ; byte size buffer
+        CALL DOT4DE
+        CALL HEXIYX                                                      ; execute address
+        LD (EXADR),HL                                                    ; buffer
+        CALL NL
+        LD DE,MSGSV                                                      ; 'FILENAME? '
+        RST 018h
+        CALL BGETLX                                                      ; filename input
+        CALL DOT4DE
+        CALL DOT4DE
+        LD HL,NAME                                                       ; name buffer
+SAVX1:
+        INC DE
+        LD A,(DE)
+        LD (HL),A                                                        ; filename trans.
+        INC HL
+        CP 00Dh                                                          ; end code
+        JR NZ,SAVX1
+        LD A,OBJCD                                                       ; attribute: OBJ
+        LD (ATRB),A
+        CALL ?WRI
+?ERX1:
+        JP C,?ERX
+        CALL ?WRD                                                        ; data
+        JR C,?ERX1
+        CALL NL
+        LD DE,MSGOK                                                      ; 'OK!'
+        RST 018h
+LEA5B:
+        JP ST1X
+
+VRFYX:
+        CALL ?VRFY
+        JP C,?ERX
+        LD DE,MSGOK                                                      ; 'OK!'
+        RST 018h
+        JR LEA5B
+LEA6A:
+        JP CMY0
+
+SGX:
+        LD A,(SWRK)
+        RRA
+        CCF
+        RLA
+        LD (SWRK),A
+LEA76:
+        JR LEA5B
+
+DUMPX:
+        CALL HEXIYX
+        CALL DOT4DE
+        PUSH HL
+        CALL HLHEX
+        POP DE
+        JR C,LEAD6
+LEA85:
+        EX DE,HL
+LEA86:
+        LD B,008h
+        LD C,017h
+        CALL NLPHL
+LEA8D:
+        CALL SPHEX
+        INC HL
+        PUSH AF
+        LD A,(DSPXY)
+        ADD A,C
+        LD (DSPXY),A
+        POP AF
+        CP 020h
+        JR NC,LEAA0
+        LD A,02Eh
+LEAA0:
+        CALL ?ADCN
+        CALL PRNT3
+        LD A,(DSPXY)
+        INC C
+        SUB C
+        LD (DSPXY),A
+        DEC C
+        DEC C
+        DEC C
+        PUSH HL
+        SBC HL,DE
+        POP HL
+        JR Z,LEAD3
+        LD A,0F8h
+        LD (0E000h),A
+        NOP
+        LD A,(0E001h)
+        CP 0FEh
+        JR NZ,LEAC7
+        CALL ?BLNK
+LEAC7:
+        DJNZ LEA8D
+LEAC9:
+        CALL ?KEY
+        OR A
+        JR Z,LEAC9
+        CALL ?BRK
+        DB  020h
+LEAD3:
+        DB  0B2h
+      
+        JR LEA76
+LEAD6:
+        LD HL,000A0h
+        ADD HL,DE
+        JR LEA85
+
+FNINP:
+        CALL NL
+        LD DE,MSGSV                                                      ; 'FILENAME? '
+        RST 018h
+        LD DE,BUFER
+        CALL GETL
+        LD A,(DE)
+        CP #1B
+        JR NZ,LEAF3
+        LD HL,ST1X
+        EX (SP),HL
+        RET
+
+LEAF3:
+        LD B,000h
+        LD DE,011ADh
+        LD HL,BUFER
+        LD A,(DE)
+        CP 00Dh
+        JR Z,LEB20
+LEB00:
+        CP 020h
+        JR NZ,LEB08
+        INC DE
+        LD A,(DE)
+        JR LEB00
+LEB08:
+        CP 022h
+        JR Z,LEB14
+LEB0C:
+        LD (HL),A
+        INC HL
+        INC B
+        LD A,011h
+        CP B
+        JR Z,FNINP
+LEB14:
+        INC DE
+        LD A,(DE)
+        CP 022h
+        JR Z,LEB1E
+        CP 00Dh
+        JR NZ,LEB0C
+LEB1E:
+        LD A,00dh
+LEB20:
+        LD (HL),A
+        RET
+
+LEB22:
+        LD A,(0F000h)
+        OR A
+        RET
+               
+
+LEB27:  DB      "IPL IS LOADING ",00Dh
+LEB37:  DB      "MAKE READY QD",00Dh
+DISCLR: DB      "**  MONITOR 9Z-503M  **",00Dh
+
+;
+;====================================
+;
+;       QUICK DISK LOAD COMMAND
+;
+;====================================
+;
+QL:
+        CALL IOFRS
+        CALL QDRCK                                                       ; Ready check
+        JR C,LEBAC
+        CALL FNINP                                                       ; Input filename
+        CALL HDPCL                                                       ; Head point clear
+;
+;       Disp 'Loading...'
+;
+        LD DE,MSG?2                                                      ; 'LOADING '
+        RST 018h
+;
+;       File search
+;
+FILESH:
+        CALL FILSCH
+        JR C,LEBAC
+;
+;       Atribute check
+;
+        LD A,(ATRB)
+        CP OBJCD
+        JR NZ,FILESH
+;
+;
+;
+DSFLNA:
+        LD DE,NAME
+        RST 018h
+
+        LD HL,(EXADR)
+        LD A,H
+        OR L
+        JR NZ,LEB8B
+        LD HL,(COMNT)
+        LD A,H
+        OR L
+LEB8B:
+        JR NZ,LPARA0
+        LD A,0FFh
+        LD (0113Ah),A
+
+
+
+;
+;       Iocs parameter set
+;
+        LD HL,01200h
+        JR LPARA1
+LPARA0:
+        LD HL,(EXADR)
+LPARA1:
+        LD (QDPC),HL                                                     ; Data adrs set
+        LD HL,(DTADR)
+        LD (QDPE),HL
+        LD HL,00103h                                                     ; Read data block cmd.
+        LD (QDPA),HL                                                     ; QDPA = 3 (read from headpoint)
+                                                                         ; QDPB = 1 (data should be read)
+;
+;       Read data block
+;
+        CALL QDIOS                                                       ; QD iocs
+LEBAC:
+        JP C,QER04
+        LD A,(0113Ah)
+        CP 0FFh
+        JR Z,LEBBD
+;
+;       Exec load file
+;
+        LD BC,00300h
+        LD HL,(COMNT)
+        JP (HL)
+
+LEBBD:
+        OUT (0E0h),A
+        LD HL,01200h
+        LD DE,00000h
+        LD BC,(DTADR)
+        LDIR
+        LD BC,00300h
+        JP 00000h
+
+;
+;       Iocs flag reset
+;
+IOFRS:
+        XOR A
+        LD (MTF),A                                                       ; Motor Flag = 0 (OFF)
+        LD (FNUPS),A                                                     ; File number flag = 0
+        LD (FNUPF),A                                                     ; File number up flag = 0
+        RET
+
+;
+;
+;       File search sub.
+;
+;
+FILSCH:
+;
+;       Iocs parameter set
+;
+        LD HL,00003h                                                     ; read from headpoint
+        LD (QDPA),HL                                                     ; QDPA = 3 (read from head point)
+                                                                         ; QDPB = 0 (header should be read)
+        LD HL,ATRB                                                       ; Head adrs
+        LD (QDPC),HL
+        LD HL,00040h                                                     ; Read size
+        LD (QDPE),HL
+
+;
+;       Read information block
+;
+QLINF:
+        CALL QDIOS
+        RET C
+;
+;       File name check
+;
+        LD A,(BUFER)
+        CP 00Dh
+        RET Z
+        LD HL,BUFER
+        LD DE,NAME
+        LD B,NAMSIZ
+LDFNCK:
+        LD A,(DE)
+        CP (HL)
+        JR NZ,QLINF
+        CP 00Dh
+        RET Z
+        INC DE
+        INC HL
+        DJNZ LDFNCK
+        RET
+;
+;       Quick disk ready check
+;
+QDRCK:
+        XOR A
+        LD (QDPB),A                                                      ; QDPB = 0 -> only Ready check
+        INC A
+        LD (QDPA),A                                                      ; QDPA = 1
+        CALL QDIOS
+        RET
+;
+;======================================
+;
+;       Quick disk directory command
+;
+;======================================
+;
+QD:
+        CALL IOFRS
+        CALL QDRCK
+        JR C,QER04
+        CALL HDPCL
+        LD B,000h
+;
+;       Disp 'Directory of QD:'
+;
+        LD DE,DIRMSG
+        RST 018h
+;
+;       Iocs parameter set
+;
+        LD HL,QDIRBF
+DIRIOP:
+        LD (QDPC),HL
+        LD HL,00003h
+        LD (QDPA),HL                                                     ; QDPA = 3 (read from headpoint)
+                                                                         ; QDPB = 0 (header should be read)
+        LD HL,00040h
+        LD (QDPE),HL                                                     ; QDPE = 64 (header length)
+;
+;       Read information block
+;
+        PUSH BC
+        CALL QDIOS
+        POP BC
+        JR C,DIREFC
+        INC B
+;
+;       Buffer adrs increment
+;
+        LD HL,(QDPC)
+        LD DE,PRNT
+        ADD HL,DE
+        JR DIRIOP
+;
+;       End file check
+;
+DIREFC:
+        CP NTFECD
+        JR Z,DIRMTF
+        SCF
+QER04:
+        JR C,QERTRT
+;
+;       Motor off
+;
+DIRMTF:
+        LD A,006h                                                        ; Motor off command
+        LD (QDPA),A
+        PUSH BC
+        CALL QDIOS
+        POP BC
+;
+;       No file check
+;
+        XOR A
+        CP B
+        JR NC,QDOKM
+;
+;       Directory disp
+;
+        CALL NL
+        LD HL,QDIRBF
+;
+;       Disp atribute
+;
+DSPATR:
+        LD A,(HL)
+        LD DE,MSGQ01
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ02
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ03
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ04
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ05
+        DEC A
+        JR Z,LECA4
+        DEC A
+        JR Z,LECA1
+        LD DE,MSGQ07
+        DEC A
+        JR Z,LECA4
+        DEC A
+        JR Z,LECA1
+        DEC A
+        JR Z,LECA1
+        LD DE,MSGQ10
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ11
+        DEC A
+        JR Z,LECA4
+LECA1:
+        LD DE,MSGQ??
+LECA4:
+        RST 018h
+;
+;       Disp file name
+;
+LECA5:
+        LD A,'"'
+        CALL PRNT
+        INC HL
+        PUSH HL
+        POP DE
+        RST 018h
+        LD A,'"'
+        CALL PRNT
+        CALL NL
+;
+;       Counter decrement
+;
+LECB6:
+        LD DE,00011h
+        ADD HL,DE
+LECBA:
+        CALL ?KEY
+        OR A
+        JR Z,LECBA
+        CALL ?BRK
+        JP Z,ST1X
+        DJNZ DSPATR
+
+QDOKM:
+        CALL NL
+        LD DE,MSGQOK
+        RST 018h
+        JP ST1X
+
+;
+;======================================
+;
+;       Error treatment
+;
+;=====================================
+;
+QERTRT:
+        LD DE,MGNFE                                                      ; 'Not Found err'
+        CP NTFECD                                                        ; Not found err
+        JR Z,QERMF
+        LD DE,MGNRE                                                      ; 'Not ready'
+        CP QNTRCD                                                        ; Not ready
+        JR Z,QERMF
+        LD DE,MGUFE                                                      ; 'Unformat'
+        CP UNFMCD                                                        ; Unformat err
+        JR Z,QERMF
+        LD DE,MSGTRM
+        CP BRKCD                                                         ; Break
+        JR Z,QERMF
+        LD DE,MGHDE                                                      ; 'Hard error'
+;
+;       Motor off
+;
+QERMF:
+        LD A,006h                                                        ; Motor off cmd.
+        LD (QDPA),A
+        CALL QDIOS
+        CALL HDPCL
+;
+LECFC:
+        LD A,(QDCPA)
+        RRA
+        RET C                                                            ; Boot err
+        CALL NL
+        RST 018h
+        JP ST1X
+;
+;       Header point clear
+;
+HDPCL:
+        LD A,005h                                                        ; Head point clear cmd.
+        LD (QDPA),A
+        CALL QDIOS
+        RET
+
+;
+;======================================
+;
+;       Message table
+;
+;======================================
+;
+MSGQOK: DB      "OK!"
+MSGTRM: DB      00Dh
+MGNFE:  DB      "QD:FILE NOT FOUND",00Dh
+MGHDE:  DB      "QD:HARD ERR",00Dh
+MGNRE:  DB      "QD:NOT READY",00Dh
+MGUFE:  DB      "QD:UNFORMAT",00Dh
+LED4C:  DB      "QD:FILE MODE ERR",00Dh
+DIRMSG: DB      "DIRECTORY OF QD:",00Dh
+MSGQ01: DB      "    OBJ   ",00Dh
+MSGQ02: DB      "    BTX   ",00Dh
+MSGQ03: DB      "    BSD   ",00Dh
+MSGQ04: DB      "    BRD   ",00Dh
+MSGQ05: DB      "    RB    ",00Dh
+MSGQ07: DB      "    LIB   ",00Dh
+MSGQ10: DB      "    SYS   ",00Dh
+MSGQ11: DB      "    GR    ",00Dh
+MSGQ??: DB      "    ???   ",00Dh
+
+
+QDIOS1:
+        LD A,005h                                                        ; Retry 4
+        LD (RTYF),A
+;
+RTY:
+        DI
+        CALL QMEIN
+        EI
+        RET NC
+        PUSH AF
+        CP 028h
+        JR Z,RTY4
+        CALL MTOF
+        POP AF
+        PUSH AF
+        CP 029h
+        JR NZ,RTY4
+        LD HL,RTYF
+        DEC (HL)
+        JR Z,LEDF3
+        POP AF
+        JR RTY
+LEDF3:
+        CALL QDHPC
+RTY4:
+        POP AF
+        RET
+
+QMEIN:
+        LD (RETSP),SP
+        LD A,(QDPA)
+        DEC A                                                            ; ready check           (1)
+        JR Z,QDRC
+        DEC A                                                            ; format                (2)
+                                                                         ; not implemented
+        DEC A                                                            ; read from headpoint   (3)
+        JR Z,QDRD
+        DEC A                                                            ; save from headpoint   (4)
+                                                                         ; not implemented
+        DEC A                                                            ; headpoint clear       (5)
+        JR Z,QDHPC
+        JP MTOF                                                          ; else motor off
+;
+;======================================
+;
+;       Head Point Clear
+;
+;======================================
+;
+QDHPC:
+        PUSH AF
+        XOR A
+        LD (HDPT),A
+        POP AF
+        RET
+;
+;=================================
+;
+;       Ready Check
+;
+;=================================
+;
+QDRC:
+        LD A,(QDPB)                                                      ; QDPB = 0 -> only Ready check
+        JP QREDY
+;
+;=================================
+;
+;       Read
+;
+;=================================
+;
+QDRD:
+        LD A,(MTF)                                                       ; A = Motor Flag
+        OR A                                                             ; test Motor Flag
+        CALL Z,MTON                                                      ; if Motor Flag = 0 then Motor On and go to home position
+        CALL HPS                                                         ; head point search
+        RET C
+        CALL BRKC                                                        ; check break key
+;
+        CALL RDATANRCK                                                   ; read low-byte blocksize
+        LD C,A
+        CALL RDATANRCK                                                   ; read high-byte blocksize
+        LD B,A
+        LD HL,(QDPE)
+        SBC HL,BC                                                        ;
+        JP C,IOE41
+        LD HL,(QDPC)
+;
+; Block Data Read
+;
+BDR:
+        CALL RDATANRCK                                                   ; read data
+        LD (HL),A                                                        ; save it
+        INC HL                                                           ; inc address
+        DEC BC                                                           ; dec counter
+        LD A,B
+        OR C
+        JR NZ,BDR                                                        ; counter not zero than read again
+        CALL RDCRC                                                       ; read checksum (3 bytes)
+        LD A,(QDPB)
+        BIT 0,A
+        JP NZ,MTOF
+        RET
+;
+; Head Point Search
+;
+HPS:
+        LD HL,FNB                                                        ; HL = next file number
+        DEC (HL)
+        JR Z,HPNFE                                                       ; Not found
+        CALL SYNCL2                                                      ; read 2 bytes last is in A
+        LD C,A                                                           ; BLocKFLaG => C reg
+        LD A,(HDPT)                                                      ; A = destination head point position
+        LD HL,HDPT0                                                      ; HL = address of the actual head point position
+        CP (HL)                                                          ; Search ok ?
+        JR NZ,HPS1                                                       ; no, than make dummy block read
+        INC A                                                            ; HDPT count up
+        LD (HDPT),A
+        LD (HL),A                                                        ; HDPT0 count up
+        LD A,(QDPB)                                                      ; A = filetype to load
+        XOR C                                                            ; xor with BLocKFLaG which
+        RRA
+        RET NC                                                           ; same, than ret else ...
+;
+; Dummy read
+;
+DMR:
+        CALL RDATANRCK                                                   ; read size low byte
+        LD C,A
+        CALL RDATANRCK                                                   ; read size high byte
+        LD B,A
+;
+DMR1:                                                                    ; read size bytes
+        CALL RDATANRCK
+        DEC BC
+        LD A,B
+        OR C
+        JR NZ,DMR1
+        CALL RDCRC                                                       ; read checksum (3 bytes)
+        JR HPS                                                           ; next
+;
+HPS1:
+        INC (HL)                                                         ; increment actual head point position
+        JR DMR
+;
+HPNFE:
+        LD A,NTFECD                                                      ; Not Found
+        SCF
+        RET
+
+
+
+;
+; Ready & Write protect
+;       ACC = 0 : Ready check
+;       ACC = 1 : & Write Protect
+;
+QREDY:
+        LD B,A                                                           ; save command
+        LD A,002h
+        OUT (SIOBC),A                                                    ; select register 2 (IV)
+        LD A,081h
+        OUT (SIOBC),A                                                    ; write 81h in register 2
+        LD A,002h
+        OUT (SIOBC),A                                                    ; select register 2 (IV)
+        IN A,(SIOBC)                                                     ; read back register 2
+        AND 081h
+        CP 081h
+        JP NZ,IOE50                                                      ; Not ready
+        LD A,010h
+        OUT (SIOAC),A                                                    ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0
+        IN A,(SIOAC)
+        LD C,A                                                           ; save Read Register 0
+        AND 008h                                                         ; test DCD (HeadSet)
+        JP Z,IOE50                                                       ; Not ready
+        LD A,B                                                           ; restore command
+        OR A                                                             ; if command = 0 then
+        RET Z                                                            ; return
+        LD A,C                                                           ; else restore Read Register 0
+        AND 020h                                                         ; test CTS (WriteProtect)
+        RET NZ                                                           ; if CTS then not protected, return
+        JP IOE46                                                         ; else Write protect
+
+;
+;
+; MTON -- QD MOTOR ON
+;         READ FILE NUMBER
+;         READ & CHECK CRC,FLAG
+;
+MTON:
+        LD HL,SIOLD                                                      ; SIO Load Data
+        LD B,00Bh
+        CALL LSINT                                                       ; load SIO init and motor on and go to home position
+
+        CALL SYNCL1                                                      ; search for sync and read first 2 bytes, last is in A
+        LD (FNA),A                                                       ; save actual file no in File Number A
+        INC A
+        LD (FNB),A                                                       ; save next file no in File Number B
+        CALL RDCRC                                                       ; read checksum (3 bytes)
+FNEND:
+        LD HL,SYNCF
+        SET 3,(HL)                                                       ; set bit3 of SyncFlags
+        XOR A                                                            ; A = 0
+        LD (HDPT0),A                                                     ; actual head point position = 0
+        RET
+;
+;       sio initial
+;
+LSINT:
+        LD C,SIOAC
+        OTIR
+        LD A,005h                                                        ; 00000101
+        LD (MTF),A                                                       ; MoTor Flag = 5
+        OUT (SIOBC),A                                                    ; ch B select register 5
+        LD A,080h                                                        ; 10000000
+        OUT (SIOBC),A                                                    ; set DTR_B (Motor On), clear RTS_B
+
+LREDY:                                                                   ; check for ready and if so, than goto home position
+        LD A,010h                                                        ; 00010000
+        OUT (SIOAC),A                                                    ; reset ext/status interrupts, set register 0
+        IN A,(SIOAC)                                                     ; read register 0
+        AND 008h                                                         ; test DCD_A (disk inside ?)
+        JP Z,IOE50                                                       ; Not ready
+        CALL BRKC                                                        ; BReak Key Check
+        LD A,010h                                                        ; 00010000
+        OUT (SIOBC),A                                                    ; reset ext/status interrupts, set register 0
+        IN A,(SIOBC)                                                     ; read register 0
+        AND 008h                                                         ; test DCD_B (Home)
+        JR Z,LREDY
+        LD BC,000E9h                                                     ; wait 160ms
+        JP TIMW
+
+;
+; Motor off
+;
+QDOFF:                                                                   ; basic call
+MTOF:
+        PUSH AF
+        LD A,005h
+        OUT (SIOAC),A                                                    ; select Write Register 5
+        LD A,060h                                                        ; 01100000
+        OUT (SIOAC),A                                                    ; DTR OFF (Motor Off), Tx DISABLE, RTS OFF (WRGA)
+        LD A,005h
+        OUT (SIOBC),A                                                    ; select Write Register 5
+        XOR A                                                            ; 00000000
+        LD (MTF),A                                                       ; Motor Flag = 0
+        OUT (SIOBC),A                                                    ; DTR OFF (Motor Off), clear  RTS_B
+        POP AF
+        RET
+
+;
+; SYNCL1 -- LOAD F.N SYNC ONLY
+;                (SEND BREAK 110ms)
+; SYNCL2 -- LOAD FIRST FILE SYNC
+;                (SEND BREAK 110ms)
+;
+SYNCL2:
+        LD A,058h                                                        ; 01011000
+                                                                         ; RESET Rx CRC CHECKER, CHANNEL RESET, REGISTER 0
+        LD B,00Bh                                                        ; 11 values to load
+        LD HL,SIOLD
+        CALL SYNCA
+        LD HL,SYNCF
+        BIT 3,(HL)                                                       ; test bit3 of SyncFlags
+        LD BC,00003h                                                     ; WAIT 2ms
+        JR Z,TMLPL
+        RES 3,(HL)                                                       ; reset bit3 of SyncFlags
+SYNCL1:
+        ld bc,000a0h                                                     ; WAIT 110ms
+;
+TMLPL:                                                                   ; the motor is switched on
+                                                                         ; and a hunt phase is initiated,
+                                                                         ; that means the incoming datastream
+                                                                         ; is inspected for the programmed 
+                                                                         ; sync characters
+        CALL TIMW
+        LD A,005h
+        OUT (SIOBC),A                                                    ; select Write Register 5
+        LD A,082h                                                        ; 10000010
+        OUT (SIOBC),A                                                    ; DTR ON (Motor On), RTS ON ()
+        LD A,003h
+        OUT (SIOAC),A                                                    ; select Write Register 3
+        LD A,0D3h                                                        ; 11010011
+        OUT (SIOAC),A                                                    ; RX 8 BIT, ENTER HUNT PHASE, SYNC, Rx ENABLE
+        LD BC,02CC0h                                                     ; 220ms timeout
+;
+SYNCW0:                                                                  ; now the datastream is inspected
+                                                                         ; also a timeout is checked
+        LD A,010h
+        OUT (SIOAC),A                                                    ; RESET EXT/STATUS INT, select Register 0
+        IN A,(SIOAC)
+        AND 010h                                                         ; test SYNC/HUNT
+        JR Z,SYNCW1                                                      ; first 2 syncbytes found
+        DEC BC
+        LD A,B
+        OR C
+        JR NZ,SYNCW0
+        JP IOE54                                                         ; unformatted
+;
+SYNCW1:                                                                  ; now we should ignore further sync characters
+        LD A,003h
+        OUT (SIOAC),A                                                    ; select Write Register 3
+        LD A,0C3h                                                        ; 11000011
+        OUT (SIOAC),A                                                    ; Rx 8 BIT, SYNC CHAR LOAD INHIBIT, Rx ENABLE
+        LD B,09Fh                                                        ; timeout
+;
+SYNCW2:
+                                                                         ; loop for find the end of syncbytes:
+                                                                         ; rx available is only set if the first
+                                                                         ; byte is found which is not a syncbyte
+        LD A,010h
+        OUT (SIOAC),A                                                    ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0
+        IN A,(SIOAC)
+        AND 001h                                                         ; test Rx CHARACTER AVAILABLE
+        JR NZ,SYNCW3
+        DEC B
+        JR NZ,SYNCW2
+SYNCW01:
+        JP IOE54                                                         ; unformated
+;
+SYNCW3:                                                                  ; now the datastream is in sync and the
+                                                                         ; first real data is ready to read
+        LD A,003h
+        OUT (SIOAC),A                                                    ; select Write Register 3
+        LD A,0C9h                                                        ; 11001001
+        OUT (SIOAC),A                                                    ; Rx 8 BIT, Rx CRC ENABLE, Rx ENABLE
+        CALL RDATANRCK
+        JP RDATANRCK
+
+;
+;
+;
+SYNCA:
+        LD C,SIOAC
+        OUT (C),A
+        LD A,005h
+        OUT (SIOBC),A                                                    ; select Write Register 5
+        LD A,080h
+        OUT (SIOBC),A                                                    ; set DTR_B (Motor On), clear RTS_B
+        OTIR
+        RET
+
+;
+;       RDCRC -- READ CRC & CHECK
+;
+RDCRC:
+        LD B,003h                                                        ; 3 retries
+RDCR1:
+        CALL RDATANRCK                                                   ; read 3 bytes
+        DJNZ RDCR1
+RDCR2:                                                                   ; read REGISTER 0
+        IN A,(SIOAC)
+        RRCA                                                             ; test Rx CHARACTER AVAILABLE
+        JR NC,RDCR2                                                      ; Rx Available
+        LD A,001h                
+        OUT (SIOAC),A                                                    ; select REGISTER 1
+        IN A,(SIOAC)                                                     ; read REGISTER 1
+        AND 040h                                                         ; test CRC ERROR
+        JR NZ,IOE41                                                      ; Hard err
+        OR A
+        RET
+
+RDATANRCK:
+NRCK:
+        LD A,010h
+        OUT (SIOAC),A                                                    ; reset ext/status interrupts, set register 0
+        IN A,(SIOAC)                                                     ; read register 0
+        AND 008h                                                         ; test DCD (HeadSet)
+        JP Z,IOE50                                                       ; Not Ready
+;
+;       Read data (1 chr)
+;
+RDATA:
+        IN A,(SIOAC)                                                     ; read REGISTER 0
+        RLCA
+        JR C,IOE41                                                       ; test BREAK/ABORT (Hard Err)
+        RRCA
+        RRCA
+        JR NC,NRCK                                                       ; test Rx AVAILABLE
+        IN A,(SIOAD)                                                     ; read data
+        OR A
+        RET
+               
+;
+;       i/o err
+;
+IOE41:
+        LD A,HDERCD                                                      ; Hard err
+        DB 021h
+IOE46:
+        LD A,WPRTCD                                                      ; Write protect
+        DB 021h
+IOE50:
+        LD A,QNTRCD                                                      ; Not ready
+        DB 021h
+IOE53:
+        LD A,NFSECD                                                      ; No file space
+        DB 021h
+IOE54:
+        LD A,UNFMCD                                                      ; Unformat
+        LD SP,(RETSP)
+        SCF
+        RET
+               
+
+;
+;       wait timer
+;
+;
+;       BC = 0001H =   0.7ms (  0.704ms)
+;            0003H =   2.0ms (  2.107ms)
+;            001DH =  20.0ms ( 19.938ms)
+;            00A0H = 110.0ms (110.050ms)
+;            00E9H = 160.0ms (160.140ms)
+;            0140H = 220.0ms (219.940ms)
+;
+;
+TIMW:
+        PUSH AF
+TIMW1:
+        LD A,086h
+TIMW2:
+        DEC A
+        JR NZ,TIMW2
+        DEC BC
+        LD A,B
+        OR C
+        JR NZ,TIMW1
+        POP AF
+        RET
+
+;
+;
+;
+; SIO CH A COMMAND CHAIN
+;
+; SIOLD -- LOAD INIT. DATA
+;
+;
+;
+; BiSync mode, uses 16h and 16h as sync characters
+; the SIO works also in polling mode, no interrupt is generated
+;
+SIOLD:
+        DB      058h                                                     ; RESET Rx CRC CHECKER, CHANNEL RESET
+        DB      004h                                                     ; select Write Register 4
+        DB      010h                                                     ; X1 CLOCK mode, 16 bit sync char, sync mode, no parity
+        DB      005h                                                     ; select Write Register 5
+        DB      004h                                                     ; CRC-16
+        DB      003h                                                     ; select Write Register 3
+        DB      0D0h                                                     ; RX 8 BITS, AUTO ENABLES, ENTER HUNT PHASE
+        DB      006h                                                     ; select Write Register 6
+        DB      016h                                                     ; set SYNC CHR(1)
+        DB      007h                                                     ; select Write Register 7
+        DB      016h                                                     ; set SYNC CHR(2)
+
+
+;
+;
+; BREAK CHECK
+;
+BRKC:
+        LD A,0E8h
+        LD (0E000h),A
+        NOP
+        LD A,(0E001h)
+        AND 081h
+        RET NZ
+        LD SP,(RETSP)
+        SCF
+        RET
+               
+        ld l,#41
+
+; the following is only to get the original length of 4096 bytes
+        ALIGN 0F7FFh
+        DB      0FFh
diff --git a/software/asm/mz80kfdif.asm b/software/asm/mz80kfdif.asm
new file mode 100644
index 0000000..8dd073b
--- /dev/null
+++ b/software/asm/mz80kfdif.asm
@@ -0,0 +1,661 @@
+;
+; MZ-80K FDC ROM
+;
+		ORG	F000H
+F000  00        NOP     
+F001  F3        DI      
+F002  AF        XOR     A
+F003  329C11    LD      (#119C),A	;clock off
+F006  3EC3      LD      A,#C3		;JP code for error trap
+F008  320B10    LD      (#100B),A
+F00B  215AF0    LD      HL,#F05A	;error can't boot
+F00E  220C10    LD      (#100C),HL	;error trap
+F011  11F09F    LD      DE,#9FF0	;transfer 9 bytes from
+F014  2187F0    LD      HL,#F087	;ROM to RAM for use
+;
+;IBT1
+;
+F017  010900    IBT1:	LD      BC,#0009 ;by (IX+D) in reader
+F01A  EDB0      LDIR    
+F01C  CD0900    CALL    CRLF		;NL
+F01F  117AF0    LD      DE,MESS1
+F022  CD1500    CALL    MESSAGE		;msg "BOOT DRIVE ?"
+F025  11009F    LD      DE,BUFF2
+F028  CD0300    CALL    USER		;get line
+F02B  210C00    LD      HL,#000C
+F02E  19        ADD     HL,DE		;skip around msg
+F02F  7E        LD      A,(HL)		;pickup answer to prompt
+F030  FE0D      CP      #0D		;CR ?
+F032  2002      JR      NZ,#F036        ;Z=CR assume drive 1
+F034  3E31      LD      A,#31		;ASCII for 1
+;
+;IBT2
+;
+F036  47        IBT2:	LD      B,A	;save driveno
+F037  E6F0      AND     #F0		;take ASCII and convert
+F039  FE30      CP      #30		;to numeric having
+F03B  20DF      JR      NZ,IBT1		;checked >1 & <=4
+F03D  78        LD      A,B		;get driveno
+F03E  E60F      AND     #0F		;mask
+F040  3D        DEC     A		;-1 00-03
+F041  FE04      CP      #04
+F043  30D7      JR      NC,IBT1		;dud key, >=4, try again
+F045  32F09F    LD      (#9FF0),A	;save drive no
+F048  321110    LD      (#1011),A	;save drive no
+F04B  DD21F09F  LD      IX,#9FF0	;IX pointer to fdc parameters at 9FF0
+					;ready for disk read
+F04F  CD3BF1    CALL    READER		;get boot records
+F052  3A0098    LD      A,(#9800)	;1st byte of input buffer of boot records
+F055  FEC3      CP      #C3		;jump cmd?
+F057  CA0098    JP      Z,#9800		;yes, execute to 9800
+;
+;IBT3
+;
+F05A  31F010 	IBT3:   LD      SP,#10F0 ;no, reset stack
+F05D  CD0900    CALL    CRLF		;NL
+F060  116CF0    LD      DE,MESS2	;msg can't boot
+F063  CD1500    CALL    MESSAGE
+F066  CDA7F0    CALL    MOTOFF		;motor off
+F069  C38200    JP      MAINLP		;warm start, ret to monitor
+;
+;MESS2
+;
+F06C  45523A43	MESS2:	DB	"ER:CAN'T BOOT"
+F070  414E2754
+F074  20424F4F
+F078  54
+F079  0D	DB	0DH
+;
+;MESS1
+;
+F07A  424F4F54	DB	"BOOT DRIVE ?"
+F07E  20445249
+F082  5645203F
+F086  0D	DB	0DH
+;
+;DDATA
+;fdc parameters
+;
+F087  00	DB	00H		;drive no-1
+F088  00	DB	00H		;trk*2 remainder = head
+F089  01	DB	01H		;sector no (range: 01 - 10)
+F08A  00	DB	00H		;$80 = add 1 record to read to (F08B)
+F08B  0700	DB	07H		;07H = 07*2 = 14 sectors to read, add 1 if (F08A = $80)
+F08D  0098	DB	00H,98H		;9800H = load addr.
+F08F  00	DB	00H		;no meaning
+;
+;MOTON
+;
+F090  C5        MOTON:	PUSH    BC	;starts motors
+F091  01F808    LD      BC,#08F8
+F094  ED78      IN      A,(C)		;start motor
+F096  010000    LD      BC,#0000
+;
+;WAIT1
+;
+F099  0B        WAIT1:	DEC     BC	;wait for motor to
+F09A  00        NOP     		;get up to speed
+F09B  00        NOP     
+F09C  78        LD      A,B
+F09D  B1        OR      C
+F09E  20F9      JR      NZ,WAIT1
+F0A0  3E01      LD      A,#01
+F0A2  320210    LD      (MOTFLG),A	;01=on 00=off
+F0A5  C1        POP     BC
+F0A6  C9        RET     
+;
+;MOTOFF
+;
+F0A7  C5        MOTOFF:	PUSH    BC	;stop motors
+F0A8  CDAEF1    CALL    LNGDEL		;timed wait
+F0AB  01F800    LD      BC,#00F8
+F0AE  ED78      IN      A,(C)
+F0B0  C1        POP     BC
+F0B1  C9        RET     
+;
+;SKZERO
+;
+F0B2  CDBDF0    SKZERO:	CALL    DREADY	;seek track 0
+F0B5  AF        XOR     A
+F0B6  D3F9      OUT     (#F9),A		;clear track reg
+F0B8  320010    LD      (#1000),A
+F0BB  D3FA      OUT     (#FA),A		;send seek zero code
+;
+;DREADY
+;
+F0BD  C5        DREADY:	PUSH    BC
+F0BE  010000    LD      BC,#0000
+;
+;DRY1
+;
+F0C1  DBF9      DRY1:	IN      A,(#F9)	;get DRDY, CRDY, RQM
+F0C3  E603      AND     #03		;leave DRDY, CRDY
+;
+;DRY2
+;
+F0C5  FE02      DRY2:	CP      #02	;wait for DRDY & CRDY
+F0C7  2002      JR      NZ,WAIT2        ;no, =03
+F0C9  C1        POP     BC		;yes, =02
+F0CA  C9        RET     
+;
+;WAIT2
+;
+F0CB  0B        WAIT2:	DEC     BC
+F0CC  78        LD      A,B
+F0CD  B1        OR      C
+F0CE  20F1      JR      NZ,DRY1
+F0D0  C1        POP     BC
+F0D1  3E32      LD      A,#32
+F0D3  320810    LD      (#1008),A	;error 40 (not found)
+F0D6  C30B10    JP      #100B		;error can't boot
+;
+;STATUS
+;
+F0D9  DBFA      STATUS:	IN      A,(#FA)	;read status
+F0DB  E6F0      AND     #F0
+F0DD  07        RLCA    
+F0DE  30F9      JR      NC,STATUS	;wait for CRDY
+F0E0  E6F0      AND     #F0		;mask leave CRDY, S1, S2, S3
+F0E2  0F        RRCA    		;move right until S�
+F0E3  0F        RRCA    		;is in B0
+F0E4  0F        RRCA    
+F0E5  0F        RRCA    
+F0E6  B7        OR      A		;clear flags
+F0E7  C8        RET     Z		;Z=ok
+F0E8  FE0C      CP      #0C		;0C=drive not ready etc.
+F0EA  2004      JR      NZ,STS1
+F0EC  3E32      LD      A,#32		;error code 40 (not found)
+F0EE  180A      JR      STS3
+;
+STS1
+;
+F0F0  FE04      STS1:	CP      #04	;04=ID not found
+F0F2  2004      JR      NZ,STS2
+F0F4  3E36      LD      A,#36		;error code 54 (unformat error)
+F0F6  1802      JR      STS3
+;
+;STS2
+;
+F0F8  3E29      STS2:	LD      A,#29	
+F0FA  320810    LD      (#1008),A	;error code 41 disk hw error
+F0FD  37        SCF     
+F0FE  C9        RET     
+;
+;PRMDRV
+;
+F0FF  C5        PRMDRV:	PUSH    BC	;prime drive
+F100  E5        PUSH    HL
+F101  CD90F0    CALL    MOTON
+F104  DD7E00    LD      A,(IX+#00)	;get drive no-1
+F107  E603      AND     #03		;form drive code
+F109  F61C      OR      #1C		;set TND, MOTOR, SELECT BIT
+F10B  320110    LD      (#1001),A	;keep drive code
+F10E  E60F      AND     #0F		;mask out TND
+F110  47        LD      B,A
+F111  0EF8      LD      C,#F8
+F113  ED60      IN      H,(C)		;select drive
+F115  3E32      LD      A,#32
+;
+;PRM1
+;
+F117  CDAEF1    PRM1:	CALL    LNGDEL	;wait for head
+F11A  3D        DEC     A		:to load
+F11B  20FA      JR      NZ,PRM1
+F11D  010000    LD      BC,#0000
+;
+;PRM2
+;
+F120  DBF9      PRM2:	IN      A,(#F9)	;get DRDY, CRDY, RQM
+F122  E607      AND     #07		;mask out RUBBISH
+F124  FE06      CP      #06		;DRDY & CRDY ?
+F126  2006      JR      NZ,PRM3		;NZ=no, keep trying
+F128  CDB2F0    CALL    SKZERO
+F12B  E1        POP     HL
+F12C  C1        POP     BC
+F12D  C9        RET     		;correct exit
+;
+;PRM3
+;
+F12E  0B        PRM3:	DEC     BC
+F12F  78        LD      A,B
+F130  B1        OR      C
+F131  20ED      JR      NZ,PRM2
+F133  3E32      LD      A,#32
+F135  320810    LD      (#1008),A	;error 40 (not found)
+F138  C30B10    JP      #100B		;abort; error can't boot
+;
+;READER
+;
+F13B  3E0A      READER:	LD      A,#0A	;no. of tries
+F13D  320710    LD      (#1007),A
+;
+;RDR1
+;
+F140  CDFFF0    RDR1:	CALL    PRMDRV
+F143  3A0110    LD      A,(#1001)	;keep drive in use
+F146  47        LD      B,A
+F147  0EF8      LD      C,#F8
+F149  D9        EXX     		;save all regs
+F14A  0EFB      LD      C,#FB		;port fb??
+F14C  DD5E03    LD      E,(IX+#03)	;no meaning
+F14F  DD5604    LD      D,(IX+#04)	;get half of numbers to read (7)
+F152  CB13      RL      E		;B7 to carry
+F154  CB12      RL      D		;double number of sectors (14), add carry
+F156  1E03      LD      E,#03		;no meaning
+F158  DD6E05    LD      L,(IX+#05)	;get loading address lo
+F15B  DD6606    LD      H,(IX+#06)	;hi into HL
+F15E  CDBDF0    CALL    DREADY
+F161  AF        XOR     A		;no meaning
+F162  DD7E01    LD      A,(IX+#01)	;get track to read
+F165  1F        RRA     		;divide by 2, remainder to carry = head no.
+F166  D3F9      OUT     (#F9),A		;send track to FDC
+F168  DD7E02    LD      A,(IX+#02)	;sector number
+F16B  3002      JR      NC,RDR2
+F16D  F680      OR      #80		;odds/evens for side code
+;
+;RDR2
+;
+F16F  D3F8      RDR2:	OUT     (#F8),A	;send sect+side
+F171  CDA6F1    CALL    SHTDEL		;short delay
+F174  3E70      LD      A,#70		;seek & read code
+F176  320010    LD      (#1000),A	;keep it
+F179  F3        DI      
+F17A  D3FA      OUT     (#FA),A		;send seek & read code to FDC
+;
+;RDR3
+;
+F17C  0680      RDR3:	LD      B,#80	;128 bytes/sector
+;
+;RDR4
+;
+F17E  DBF9      RDR4:	IN      A,(#F9)	;get DRDY, CRDY, RQM
+F180  A3        AND     E		;mask with 03
+F181  28FB      JR      Z,RDR4		;wait for either CRDY/RQM
+F183  0F        RRCA    		;RQM into carry
+F184  300C      JR      NC,RDR5		;NC=no RQM
+F186  EDA2      INI 			;get data. port FB to (HL), B=B-1   
+F188  C27EF1    JP      NZ,RDR4		;do whole sector
+F18B  15        DEC     D		;dec sector counter
+F18C  C27CF1    JP      NZ,RDR3		;NZ=more to do
+F18F  D9        EXX     		;restore all regs
+F190  ED78      IN      A,(C)		;send TND high
+;
+;RDR5
+;
+F192  CDD9F0    RDR5:	CALL    STATUS
+F195  D0        RET     NC		;NC=good read
+F196  3A0710    LD      A,(#1007)
+F199  3D        DEC     A		;A try gone
+F19A  320710    LD      (#1007),A	;counter 10times
+F19D  CA0B10    JP      Z,#100B		;can't read at all abort
+F1A0  CDB2F0    CALL    SKZERO
+F1A3  C340F1    JP      RDR1
+;
+;SHTDEL
+;
+F1A6  F5        SHTDEL:	PUSH    AF
+F1A7  3E0A      LD      A,#0A
+;
+;SDY1
+;
+F1A9  3D        SDY1:	DEC     A
+F1AA  20FD      JR      NZ,SDY1
+F1AC  F1        POP     AF
+F1AD  C9        RET     
+;
+;LNGDEL
+;
+F1AE  F5        LNGDEL:	PUSH    AF	;long delay
+F1AF  3E0A      LD      A,#0A
+;
+;LDY1
+;
+F1B1  CDA6F1    LDY1:	CALL    SHTDEL
+F1B4  3D        DEC     A
+F1B5  20FA      JR      NZ,LDY1
+F1B7  F1        POP     AF
+F1B8  C9        RET 
+
+CRLF:		EQU	00009H
+MESSAGE:	EQU	00015H
+BUFF2:		EQU	9F00H
+USER:		EQU	00003H
+MAINLP:		EQU	00082H
+MOTFLG:		EQU	1002H
+		END
+    
+;
+;no meaning !!
+;
+F1B9  13        INC     DE
+F1BA  1B        DEC     DE
+F1BB  72        LD      (HL),D
+F1BC  DE42      SBC     A,#42
+F1BE  FB        EI      
+F1BF  2F        CPL     
+F1C0  58        LD      E,B
+F1C1  43        LD      B,E
+F1C2  7C        LD      A,H
+F1C3  52        LD      D,D
+F1C4  3023      JR      NC,#F1E9        ; (35)
+F1C6  71        LD      (HL),C
+F1C7  42        LD      B,D
+F1C8  1020      DJNZ    #F1EA           ; (32)
+F1CA  74        LD      (HL),H
+F1CB  40        LD      B,B
+F1CC  43        LD      B,E
+F1CD  03        INC     BC
+F1CE  51        LD      D,C
+F1CF  00        NOP     
+F1D0  3C        INC     A
+F1D1  42        LD      B,D
+F1D2  D8        RET     C
+F1D3  60        LD      H,B
+F1D4  FB        EI      
+F1D5  09        ADD     HL,BC
+F1D6  FC402C    CALL    M,#2C40
+F1D9  80        ADD     A,B
+F1DA  79        LD      A,C
+F1DB  2A4940    LD      HL,(#4049)
+F1DE  4D        LD      C,L
+F1DF  EE3E      XOR     #3E
+F1E1  B2        OR      D
+F1E2  1EA2      LD      E,#A2
+F1E4  58        LD      E,B
+F1E5  02        LD      (BC),A
+F1E6  58        LD      E,B
+F1E7  12        LD      (DE),A
+F1E8  02        LD      (BC),A
+F1E9  43        LD      B,E
+F1EA  02        LD      (BC),A
+F1EB  220002    LD      (#0200),HL
+F1EE  2D        DEC     L
+F1EF  4B        LD      C,E
+F1F0  5A        LD      E,D
+F1F1  0A        LD      A,(BC)
+F1F2  40        LD      B,B
+F1F3  4A        LD      C,D
+F1F4  13        INC     DE
+F1F5  42        LD      B,D
+F1F6  45        LD      B,L
+F1F7  0A        LD      A,(BC)
+F1F8  5B        LD      E,E
+F1F9  6E        LD      L,(HL)
+F1FA  6A        LD      L,D
+F1FB  4E        LD      C,(HL)
+F1FC  4E        LD      C,(HL)
+F1FD  4E        LD      C,(HL)
+F1FE  5D        LD      E,L
+F1FF  7E        LD      A,(HL)
+F200  3011      JR      NC,#F213        ; (17)
+F202  DD300E    JR      NC,#F213        ; (14)
+F205  067E      LD      B,#7E
+F207  FE3A      CP      #3A
+F209  CAC221    JP      Z,#21C2
+F20C  12        LD      (DE),A
+F20D  23        INC     HL
+F20E  13        INC     DE
+F20F  0D        DEC     C
+F210  C20622    JP      NZ,#2206
+F213  C3C221    JP      #21C2
+
+F216  3AB830    LD      A,(#30B8)
+F219  FEB1      CP      #B1
+F21B  CA4522    JP      Z,#2245
+F21E  2A5030    LD      HL,(#3050)
+F221  CD1E20    CALL    #201E
+F224  7E        LD      A,(HL)
+F225  FE27      CP      #27
+F227  CA5722    JP      Z,#2257
+F22A  3E84      LD      A,#84
+F22C  327630    LD      (#3076),A
+F22F  3E02      LD      A,#02
+F231  327730    LD      (#3077),A
+F234  CDCA13    CALL    #13CA
+F237  D24A22    JP      NC,#224A
+F23A  2E00      LD      L,#00
+F23C  3EB2      LD      A,#B2
+F23E  32C830    LD      (#30C8),A
+F241  7D        LD      A,L
+F242  326F30    LD      (#306F),A
+F245  3E01      LD      A,#01
+F247  C3C321    JP      #21C3
+
+F24A  3ABE30    LD      A,(#30BE)
+F24D  FEC5      CP      #C5
+F24F  C23C22    JP      NZ,#223C
+F252  3EB0      LD      A,#B0
+F254  C33E22    JP      #223E
+
+F257  23        INC     HL
+F258  7E        LD      A,(HL)
+F259  E67F      AND     #7F
+F25B  6F        LD      L,A
+F25C  C33C22    JP      #223C
+
+F25F  3AB830    LD      A,(#30B8)
+F262  FEB1      CP      #B1
+F264  CA9022    JP      Z,#2290
+F267  2A5030    LD      HL,(#3050)
+F26A  CD1E20    CALL    #201E
+F26D  3E80      LD      A,#80
+F26F  327630    LD      (#3076),A
+F272  3E01      LD      A,#01
+F274  327730    LD      (#3077),A
+F277  CDCA13    CALL    #13CA
+F27A  D29522    JP      NC,#2295
+F27D  210000    LD      HL,#0000
+F280  3E82      LD      A,#82
+F282  32C830    LD      (#30C8),A
+F285  226330    LD      (#3063),HL
+F288  116F30    LD      DE,#306F
+F28B  7C        LD      A,H
+F28C  12        LD      (DE),A
+F28D  13        INC     DE
+F28E  7D        LD      A,L
+F28F  12        LD      (DE),A
+F290  3E02      LD      A,#02
+F292  C3C321    JP      #21C3
+
+F295  3ABE30    LD      A,(#30BE)
+F298  FEC5      CP      #C5
+F29A  C2A222    JP      NZ,#22A2
+F29D  3EB1      LD      A,#B1
+F29F  C38222    JP      #2282
+
+F2A2  CDEA1A    CALL    #1AEA
+F2A5  C38222    JP      #2282
+
+F2A8  2A5030    LD      HL,(#3050)
+F2AB  CD1E20    CALL    #201E
+F2AE  116F30    LD      DE,#306F
+F2B1  0600      LD      B,#00
+F2B3  0E04      LD      C,#04
+F2B5  7E        LD      A,(HL)
+F2B6  23        INC     HL
+F2B7  FE27      CP      #27
+F2B9  C2F822    JP      NZ,#22F8
+F2BC  7E        LD      A,(HL)
+F2BD  FE27      CP      #27
+F2BF  C2DE22    JP      NZ,#22DE
+F2C2  3AB830    LD      A,(#30B8)
+F2C5  FEB1      CP      #B1
+F2C7  CAD522    JP      Z,#22D5
+F2CA  AF        XOR     A
+F2CB  21C830    LD      HL,#30C8
+F2CE  B8        CP      B
+F2CF  CAD922    JP      Z,#22D9
+F2D2  3EB3      LD      A,#B3
+F2D4  77        LD      (HL),A
+F2D5  78        LD      A,B
+F2D6  C3C321    JP      #21C3
+
+F2D9  3EB4      LD      A,#B4
+F2DB  C3D422    JP      #22D4
+
+F2DE  FE8D      CP      #8D
+F2E0  CAF822    JP      Z,#22F8
+F2E3  FE0A      CP      #0A
+F2E5  CAF822    JP      Z,#22F8
+F2E8  E67F      AND     #7F
+F2EA  12        LD      (DE),A
+F2EB  23        INC     HL
+F2EC  13        INC     DE
+F2ED  04        INC     B
+F2EE  0D        DEC     C
+F2EF  C2BC22    JP      NZ,#22BC
+F2F2  117A30    LD      DE,#307A
+F2F5  C3BC22    JP      #22BC
+
+F2F8  3E53      LD      A,#53
+F2FA  CD111C    CALL    #1C11
+F2FD  C3C222    JP      #22C2
+
+F300  CDE511    CALL    #11E5
+F303  CD0C20    CALL    #200C
+F306  FE3A      CP      #3A
+F308  C26423    JP      NZ,#2364
+F30B  2A5030    LD      HL,(#3050)
+F30E  CD1E20    CALL    #201E
+F311  3E80      LD      A,#80
+F313  327630    LD      (#3076),A
+F316  3E02      LD      A,#02
+F318  327730    LD      (#3077),A
+F31B  CDCA13    CALL    #13CA
+F31E  DA2E23    JP      C,#232E
+F321  3ACC30    LD      A,(#30CC)
+F324  FE01      CP      #01
+F326  C23123    JP      NZ,#2331
+F329  3ECC      LD      A,#CC
+F32B  CD111C    CALL    #1C11
+F32E  210000    LD      HL,#0000
+F331  3AB830    LD      A,(#30B8)
+F334  FEB1      CP      #B1
+F336  CA6E23    JP      Z,#236E
+F339  FEB2      CP      #B2
+F33B  CAC221    JP      Z,#21C2
+F33E  226330    LD      (#3063),HL
+F341  3EA2      LD      A,#A2
+F343  32C830    LD      (#30C8),A
+F346  CDB51D    CALL    #1DB5
+F349  06DD      LD      B,#DD
+F34B  30CD      JR      NC,#F31A        ; (-51)
+F34D  E5        PUSH    HL
+F34E  1111DD    LD      DE,#DD11
+F351  300E      JR      NC,#F361        ; (14)
+F353  067E      LD      B,#7E
+F355  FE3A      CP      #3A
+F357  CAC221    JP      Z,#21C2
+F35A  12        LD      (DE),A
+F35B  23        INC     HL
+F35C  13        INC     DE
+F35D  0D        DEC     C
+F35E  C25423    JP      NZ,#2354
+F361  C3C221    JP      #21C2
+
+F364  3E4E      LD      A,#4E
+F366  CD111C    CALL    #1C11
+F369  3EB4      LD      A,#B4
+F36B  C3BF21    JP      #21BF
+
+F36E  EB        EX      DE,HL
+F36F  2A4D31    LD      HL,(#314D)
+F372  2B        DEC     HL
+F373  2B        DEC     HL
+F374  2B        DEC     HL
+F375  72        LD      (HL),D
+F376  23        INC     HL
+F377  73        LD      (HL),E
+F378  23        INC     HL
+F379  3680      LD      (HL),#80
+F37B  C3C221    JP      #21C2
+
+F37E  CC44A0    CALL    Z,#A044
+F381  41        LD      B,C
+F382  AC        XOR     H
+F383  2842      JR      Z,#F3C7         ; (66)
+F385  C3A9F1    JP      #F1A9
+
+F388  0A        LD      A,(BC)
+F389  CC44A0    CALL    Z,#A044
+F38C  41        LD      B,C
+F38D  AC        XOR     H
+F38E  2844      JR      Z,#F3D4         ; (68)
+F390  C5        PUSH    BC
+F391  A9        XOR     C
+F392  F1        POP     AF
+F393  1A        LD      A,(DE)
+F394  CC44A0    CALL    Z,#A044
+F397  2842      JR      Z,#F3DB         ; (66)
+F399  C3A9AC    JP      #ACA9
+
+F39C  41        LD      B,C
+F39D  F1        POP     AF
+F39E  02        LD      (BC),A
+F39F  CC44A0    CALL    Z,#A044
+F3A2  2844      JR      Z,#F3E8         ; (68)
+F3A4  C5        PUSH    BC
+F3A5  A9        XOR     C
+F3A6  AC        XOR     H
+F3A7  41        LD      B,C
+F3A8  F1        POP     AF
+F3A9  12        LD      (DE),A
+F3AA  CC44A0    CALL    Z,#A044
+F3AD  41        LD      B,C
+F3AE  AC        XOR     H
+F3AF  C9        RET     
+
+F3B0  F2ED57    JP      P,#57ED
+F3B3  CC44A0    CALL    Z,#A044
+F3B6  41        LD      B,C
+F3B7  AC        XOR     H
+F3B8  D2F2ED    JP      NC,#EDF2
+F3BB  5F        LD      E,A
+F3BC  CC44A0    CALL    Z,#A044
+F3BF  C9        RET     
+
+F3C0  AC        XOR     H
+F3C1  41        LD      B,C
+F3C2  F2ED47    JP      P,#47ED
+F3C5  CC44A0    CALL    Z,#A044
+F3C8  D2AC41    JP      NC,#41AC
+F3CB  F2ED4F    JP      P,#4FED
+F3CE  CC44A0    CALL    Z,#A044
+F3D1  53        LD      D,E
+F3D2  50        LD      D,B
+F3D3  AC        XOR     H
+F3D4  48        LD      C,B
+F3D5  CCF1F9    CALL    Z,#F9F1
+F3D8  CC44A0    CALL    Z,#A044
+F3DB  53        LD      D,E
+F3DC  50        LD      D,B
+F3DD  AC        XOR     H
+F3DE  C9        RET     
+
+F3DF  D8        RET     C
+F3E0  F2DDF9    JP      P,#F9DD
+F3E3  CC44A0    CALL    Z,#A044
+F3E6  53        LD      D,E
+F3E7  50        LD      D,B
+F3E8  AC        XOR     H
+F3E9  C9        RET     
+
+F3EA  59        LD      E,C
+F3EB  F2FDF9    JP      P,#F9FD
+F3EE  50        LD      D,B
+F3EF  55        LD      D,L
+F3F0  53        LD      D,E
+F3F1  48        LD      C,B
+F3F2  A0        AND     B
+F3F3  42        LD      B,D
+F3F4  C3F1C5    JP      #C5F1
+
+F3F7  50        LD      D,B
+F3F8  55        LD      D,L
+F3F9  53        LD      D,E
+F3FA  48        LD      C,B
+F3FB  A0        AND     B
+F3FC  44        LD      B,H
+F3FD  C5        PUSH    BC
+F3FE  F1        POP     AF
+F3FF  D5        PUSH    DE
\ No newline at end of file
diff --git a/software/asm/quickdisk_mz-1e05.asm b/software/asm/quickdisk_mz-1e05.asm
new file mode 100644
index 0000000..a8374b6
--- /dev/null
+++ b/software/asm/quickdisk_mz-1e05.asm
@@ -0,0 +1,620 @@
+; V1.10
+;
+; To compile use:
+;
+; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor.
+;
+; Available from:
+;   - http://www.falstaff.demon.co.uk/cross.html
+;   - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip
+;   - and many Simtel mirrors.
+;
+; as80 -i -l -n -x2 -v -z mz-1e05.asm
+
+
+
+
+;
+;----< MFM Minifloppy control >----
+;
+;
+; Call condition
+;
+; Case of disk initialize
+;       Drive N         = IX+0      (0 - 3)
+;
+;
+; Case of sequential read & write
+;       Drive N         = IX+0      (0 - 3)
+;
+;       Sector addrs    = IX+1,2    (0 - $045F)                      H   C    S
+;                                   (0 - 1119) -> 70 x 16 sectors -> 2 x 35 x 16
+;       Byte size       = IX+3,4
+;       Address         = IX+5,6
+;       Next track      = IX+7
+;       Next sector     = IX+8
+;       Start track     = IX+9
+;       Start sector    = IX+10
+;
+;
+;       I/O Port address
+;
+CR      EQU     0D8h                        ; CommandRegister
+TR      EQU     0D9h                        ; TrackRegister
+SCR     EQU     0DAh                        ; SeCtorRegister
+DR      EQU     0DBh                        ; DataRegister
+DM      EQU     0DCh                        ; DriveMotor
+HS      EQU     0DDh                        ; HeadSelect
+
+
+
+TIMST   EQU     00033h
+
+;
+;       Subroutine work
+;
+BPRO    EQU     0CF00h
+BUF     EQU     011A3h
+BPARA   EQU     BPRO - 23                   ; BootPARAmeter
+
+
+CMD     EQU     BPARA + 11                  ; CoMmanD
+MTFG    EQU     CMD + 1                     ; MoTorFlaG
+CLBF0   EQU     MTFG + 1
+CLBF1   EQU     CLBF0 + 1
+CLBF2   EQU     CLBF1 + 1
+CLBF3   EQU     CLBF2 + 1
+VRFCNT  EQU     CLBF3 + 1                   ; VeRiFyCouNT
+STAFG   EQU     VRFCNT + 1                  ; STAtusFlaG
+
+; Macro to align boundaries.
+ALIGN:  MACRO ?boundary, ?fill
+        DS    ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, ?fill
+        ENDM
+
+;
+;
+;--------< Ercode map >--------
+;
+; 50 : Not ready
+; 41 : Data error
+;       Track 80 err
+;       Write protect err
+;       Seek err
+;       CRC err
+;       Lost data
+; 54 : Unformat
+;       Recode not found
+; 56 : Invalid data
+;
+;
+
+
+        ORG     0F000h
+
+
+MZ_1E05:
+        NOP
+        LD      HL,000ADh
+        JR      L_F007
+FDX:
+        EX      (SP),HL
+L_F007:
+        LD      (BPARA + 21),HL
+        XOR     A
+        LD      DE,0
+        CALL    TIMST
+        CALL    FDCC                    ; FD i/o check
+        JP      NZ,NOTIO
+        LD      DE,BPARA                ; destination address
+        LD      HL,BOOT                 ; source address
+        LD      BC,11                   ; 11 bytes
+        LDIR                            ; copy
+SJP:
+        LD      IX,BPARA
+        CALL    BREAD                   ; read from drive 0, sector 0, 
+                                        ; 
+        LD      HL,BPRO                 ; compare this address
+        LD      DE,IPLMC                ; with the IPL MasterCode
+        LD      B,7                     ; this are 7 bytes : 3,'IPLPRO'
+MCHECK:
+        LD      C,(HL)
+        LD      A,(DE)
+        CP      C
+        JP      NZ,MASTE                ; not equal than MasterError
+        INC     HL
+        INC     DE
+        DJNZ    MCHECK
+                                        ; else Master was found
+        LD      DE,IPLM0                ; 'IPL IS LOADING'
+        RST     018h
+        LD      DE,BPRO + 7             ; NAME
+        RST     018h
+        LD      HL,(BPRO + 016h)        ; TARGETADDRESS from BootBlock
+        LD      A,H
+        OR      L
+        JR      NZ,L_F051               ; if it is != 0 than normal file
+        LD      HL,(BPRO + 018h)        ; TARGETADDRESS from BootBlock
+        LD      A,H
+        OR      L
+        JR      Z,L_F057                ; if it is also 0 than ROM replace file
+L_F051:
+        XOR     A                       ; else normal file,
+        LD      HL,(BPRO + 018h)        ; TARGETADDRESS from BootBlock
+        JR      L_F05C
+L_F057:
+        LD      A,0FFh                  ; target is at $0000, bankswitching is needed
+        LD      HL,01200h               ; for now use temporary buffer at $1200
+L_F05C:
+        LD      (0CEFDh),A
+        
+        LD      (IX + 5),L              ; set the TargetAddress
+        LD      (IX + 6),H
+        
+        LD      HL,(BPRO + 014h)        ; BYTE SIZE from BootBlock
+        LD      (IX + 3),L
+        LD      (IX + 4),H
+        
+        LD      HL,(BPRO + 01Eh)        ; START SECTOR from BootBlock
+        LD      (IX + 1),L
+        LD      (IX + 2),H
+;
+        CALL    BREAD
+        CALL    MOFF
+
+        LD      A,(0CEFDh)
+        CP      0FFh
+        JR      NZ,L_F093
+        OUT     (0E0h),A
+        LD      HL,01200h               ; SourceAddress
+        LD      DE,(BPRO + 016h)        ; TargetAddress
+        LD      BC,(BPRO + 014h)        ; ByteCounter
+        LDIR                            ; copy
+L_F093:
+        LD      BC,00200h               ; Default code
+        LD      HL,(BPRO + 018h)        ; TARGET/EXECUTION ADDRESS from BootBlock
+        JP      (HL)
+
+MASTE:
+        CALL    MOFF
+        LD      DE,ERRM1                ; 'NOT MASTER'
+        JR      ERRTR1
+ERRTRT:
+        CP      50
+NOTIO:
+        LD      DE,IPLM3                ; 'MAKE READY FD'
+        JR      Z,ERRTR1
+        LD      DE,ERRM0                ; 'FD:LOADING ERROR'
+ERRTR1:
+        CALL    00009h
+        RST     018h
+        LD      SP,010EEh
+        LD      HL,(BPARA + 21)
+        EX      (SP),HL
+        RET
+;
+;
+; PARAMETER SETTING
+;
+IPLMC:
+        DB      003h                    ; IPL MASTER FLAG
+        DB      "IPLPRO"
+
+BOOT:
+        DB      000h                    ; DRIVE NO.
+        DW      00000h                  ; SECTOR ADDR.
+        DW      00100h                  ; IFM BYTE SIZE
+        DW      BPRO                    ; IFM LOADING ADDR.
+        DW      00000h                  ; IX+7,8 (track 0, sector 0)
+
+
+
+ERRM1:
+        DB      "FD:NOT MASTER",00Dh
+IPLM0:
+        DB      "IPL IS LOADING ",00Dh
+IPLM3:
+        DB      "MAKE READY FD",00Dh
+ERRM0:
+        DB      "FD:LOADING ERROR",00Dh
+
+FDCC:
+        LD      A,0A5h
+        LD      B,A
+        OUT     (TR),A
+        CALL    DLY80U
+        IN      A,(TR)
+        CP      B
+        RET
+
+L_F111:
+        DB      000h, 000h
+;
+;
+; READY CHECK
+;
+READY:
+        LD      A,(MTFG)
+        RRCA
+        CALL    NC,MTON
+        LD      A,(IX + 0)              ; DRIVE NO SET
+        OR      084h
+        OUT     (DM),A                  ; DRIVE SELECT MOTON
+        XOR     A
+        LD      (CMD),A
+        CALL    DLY60M
+        LD      HL,0
+REDY0:
+        DEC     HL
+        LD      A,H
+        OR      L
+        JR      Z,REDY1
+        IN      A,(CR)                  ; STATUS GET
+        CPL
+        RLCA
+        JR      C,REDY0
+        LD      C,(IX + 0)
+        LD      HL,CLBF0
+        LD      B,000h
+        ADD     HL,BC
+        BIT     0,(HL)
+        JR      NZ,REDY2
+        CALL    RCLB
+        SET     0,(HL)
+REDY2:
+        RET
+
+REDY1:
+        LD      A,032h
+        JP      ERJMP
+;
+;
+; MOTOR ON
+;
+MTON:
+        LD      A,080h
+        OUT     (DM),A
+        LD      B,16
+MTD1:
+        CALL    DLY60M
+        DJNZ    MTD1
+        LD      A,1
+        LD      (MTFG),A
+        RET
+;
+;
+; SEEK TREATMENT
+;
+SEEK:
+        LD      A,01Bh                  ; 1x = SEEK, 
+        CALL    CMDOT1                  ; load head, no verify, max stepping rate
+        AND     099h
+        RET
+;
+;
+; MOTOR OFF
+;
+MOFF:
+        PUSH    AF
+        CALL    DLY1M                   ; 1000 US DELAY
+        XOR     A
+        OUT     (DM),A
+        LD      (CLBF0),A
+        LD      (CLBF1),A
+        LD      (CLBF2),A
+        LD      (CLBF3),A
+        LD      (MTFG),A
+        POP     AF
+        RET
+;
+;
+; RECALIBRATION
+;
+RCLB:
+        LD      A,00Bh                  ; 0x = RESTORE (seek track 0)
+        CALL    CMDOT1                  ; load head, no verify, max stepping rate
+        AND     085h
+        XOR     004h
+        RET     Z
+
+L_F189:
+        JP      STERROR
+;
+;
+; COMMAND OUT ROUTINE
+;
+CMDOT1:
+        LD      (CMD),A
+        CPL
+        OUT     (CR),A
+        CALL    BSYON
+        CALL    DLY60M
+        IN      A,(CR)
+        CPL
+        LD      (STAFG),A
+        RET
+;
+;
+; BUSY AND WAIT
+;
+BSYON:
+        PUSH    DE
+        PUSH    HL
+        CALL    BSY0
+BSYON2:
+        LD      HL,00000h
+BSYON0:
+        DEC     HL
+        LD      A,H
+        OR      L
+        JR      Z,BSYON1
+        IN      A,(CR)
+        RRCA
+        JR      NC,BSYON0
+        POP     HL
+        POP     DE
+        RET
+;
+BSYON1:
+        DEC     E
+        JR      NZ,BSYON2
+BSYONE:
+        LD      A,029h
+        POP     HL
+        POP     DE
+        JP      ERJMP
+;
+BSYOFF:
+        PUSH    DE
+        PUSH    HL
+        CALL    BSY0
+BSYOF2:
+        LD      HL,00000h
+BSYOF0:
+        DEC     HL
+        LD      A,H
+        OR      L
+        JR      Z,BSYOF1
+        IN      A,(CR)                  ; Status Register
+        RRCA
+        JR      C,BSYOF0
+        POP     HL
+        POP     DE
+        RET
+;
+BSYOF1:
+        DEC     E
+        JR      NZ,BSYOF2
+        JR      BSYONE
+;
+BSY0:
+        CALL    DLY80U
+        LD      E,007h
+        RET
+;
+;
+; SEQUENTIAL READ
+;
+BREAD:
+        CALL    CNVRT
+        CALL    PARST1                  ; HL = IX + 5,6 (TargetAddress)
+RE8:
+        CALL    SIDST
+        CALL    SEEK
+        JP      NZ,ERJMP
+        CALL    PARST2                  ; C = DataRegister
+        DI                              ; disable interrupts
+        LD      A,094h                  ; 9x = READ SECTOR, multiple records
+        CALL    CMDOT2                  ; compare for side 0, 15ms delay, 
+RE6:                                    ; disable side select compare
+        LD      B,0                     ; ByteCounter = 0, to load 256 bytes of the sector
+RE4:
+        IN      A,(CR)
+        RRCA
+        JR      C,RE3
+        RRCA
+        JR      C,RE4
+        INI                             ; (HL) = in(C), B = B - 1 , HL = HL + 1
+        JR      NZ,RE4
+        
+        INC     (IX + 8)                ; NextSector = NextSector + 1
+        LD      A,(IX + 8)
+        CP      011h                    ; if NextSector = 17
+        JR      Z,L_F213                ; than end
+        DEC     D                       ; else SectorCounter = SectorCounter - 1
+        JR      NZ,RE6                  ; if SectorCounter = 0
+        JR      L_F214                  ; than end
+L_F213:
+        DEC     D
+L_F214:
+        CALL    INTER
+RE3:
+        EI                              ; enable interrupts
+        IN      A,(CR)
+        CPL
+        LD      (STAFG),A
+        AND     0FFh
+        JR      NZ,STERROR
+        CALL    ADJ                     ; adjust sector and track
+        JP      Z,REND
+        LD      A,(IX + 7)              ; track
+        JR      RE8
+REND:
+        LD      A,080h      
+        OUT     (DM),A                  ; motor on
+        RET
+;
+;
+; PARAMETER SET
+;
+;
+PARST1:
+        CALL    READY
+        LD      D,(IX + 4)              ; D = bytes to read (highbyte) (256 bytes)
+        LD      A,(IX + 3)              ; A = bytes to read (lowbyte)
+        OR      A                       ; if A = 0
+        JR      Z,L_F23F                ; than it's ok
+        INC     D                       ; else read 256 bytes more (1 sector)
+L_F23F:
+        LD      A,(IX + 10)             ; NextSector = StartSector
+        LD      (IX + 8),A
+        
+        LD      A,(IX + 9)              ; NextTrack = StartTrack
+        LD      (IX + 7),A
+        
+        LD      L,(IX + 5)              ; HL = TargetAddress
+        LD      H,(IX + 6)
+        RET
+
+;
+;
+; SIZE SEEK SET
+;
+SIDST:
+        SRL     A
+        CPL
+        OUT     (DR),A
+        JR      NC,L_F25D               ; NC than Head 0
+        LD      A,1                     ; else Head 1
+        JR      L_F25E
+L_F25D:
+        XOR     A
+L_F25E:
+        CPL
+        OUT     (HS),A                  ; set HeadSelect
+        RET
+;
+;
+; TRACK & SECTOR SET
+;
+PARST2:
+        LD      C,DR
+        LD      A,(IX + 7)              ; A = NextTrack
+        SRL     A
+        CPL
+        OUT     (TR),A
+        LD      A,(IX + 8)              ; A = NextSector
+        CPL
+        OUT     (SCR),A
+        RET
+;
+;
+; ADJUST SECT & TRACK
+;
+ADJ:
+        LD      A,(IX + 8)              ; A = NextSector
+        CP      17                      ; if NextSector = 17  
+        JR      NZ,L_F282               ; than the border is not reached
+        LD      A,001h                  ; else
+        LD      (IX + 8),A              ; NextSector = 1
+        INC     (IX + 7)                ; NextTrack = NextTrack + 1
+L_F282:
+        LD      A,D
+        OR      A
+        RET
+;
+;
+; COMMAND OUT & WAIT
+;
+CMDOT2:
+        LD      (CMD),A
+        CPL
+        OUT     (CR),A
+        CALL    BSYOFF
+        RET
+;
+;
+; FORCE INTERRUPT
+;
+INTER:
+        LD      A,0D8h
+        CPL
+        OUT     (CR),A
+        CALL    BSYON
+        RET
+
+;
+;
+; STATUS CHECK
+;
+STERROR:
+        LD      A,(CMD)
+        CP      00Bh                    ; Restore (seek track 0)
+        JR      Z,ERCK1
+        CP      01Bh                    ; Seek
+        JR      Z,ERCK1
+        CP      0F4h                    ; Write track
+        JR      Z,ERCK1
+        LD      A,(STAFG)
+        BIT     7,A
+        JR      NZ,ERRET
+        BIT     6,A
+        JR      NZ,ERRET1
+        BIT     4,A
+        LD      A,54
+        JR      NZ,ERJMP
+        JR      ERRET1
+ERCK1:
+        LD      A,(STAFG)
+        BIT     7,A
+        JR      NZ,ERRET
+ERRET1:
+        LD      A,41
+        JR      ERJMP
+ERRET:
+        LD      A,50
+ERJMP:
+        CALL    MOFF
+        JP      ERRTRT
+;
+;
+; SECTOR TO TRACK & SECTOR CONVERT
+;
+CNVRT:
+        LD      B,0                     ; TrackCounter = 0
+        LD      DE,16                   ; 16 sectors per track
+        LD      L,(IX + 1)              ; HL = SectorAddress
+        LD      H,(IX + 2)
+        XOR     A
+TRANS0:
+        SBC     HL,DE                   ; SectorAddress - SectorPerTrack
+        JR      C,TRANS1                ; if < 0 than ready
+        INC     B                       ; else TrackCounter = TrackCounter + 1
+        JR      TRANS0                  ; next try
+
+TRANS1:
+        ADD     HL,DE                   ; undo the last substraction
+        LD      H,B
+        INC     L                       ; adjust sector (sector is 1..16 and not 0..15)
+        LD      (IX + 9),H              ; set StartTrack
+        LD      (IX + 10),L             ; set StartSector
+        RET
+
+;
+;
+;       TIME DELAY ( 1m & 60m & 80u )
+;
+DLY80U:
+        PUSH    DE
+        LD      DE,15
+        JP      DLYT
+
+DLY1M:
+        PUSH    DE
+        LD      DE,160
+        JP      DLYT
+
+DLY60M:
+        PUSH    DE
+        LD      DE,8230
+DLYT:
+        DEC     DE
+        LD      A,E
+        OR      D
+        JR      NZ,DLYT
+        POP     DE
+        RET
+
+
+        ALIGN   0FFF0h, 000h
+        DB      "  84.03.14 V1.0A"
diff --git a/software/asm/quickdisk_mz-1e05.obj b/software/asm/quickdisk_mz-1e05.obj
new file mode 100644
index 0000000..8dec829
Binary files /dev/null and b/software/asm/quickdisk_mz-1e05.obj differ
diff --git a/software/asm/quickdisk_mz-1e05.sym b/software/asm/quickdisk_mz-1e05.sym
new file mode 100644
index 0000000..4eacde1
--- /dev/null
+++ b/software/asm/quickdisk_mz-1e05.sym
@@ -0,0 +1,72 @@
+ADJ: equ 0F273H
+BOOT: equ 0F0BFH
+BREAD: equ 0F1DEH
+BSY0: equ 0F1D8H
+BSYOF0: equ 0F1C6H
+BSYOF1: equ 0F1D3H
+BSYOF2: equ 0F1C3H
+BSYOFF: equ 0F1BEH
+BSYON: equ 0F19FH
+BSYON0: equ 0F1A7H
+BSYON1: equ 0F1B4H
+BSYON2: equ 0F1A4H
+BSYONE: equ 0F1B7H
+CMDOT1: equ 0F18CH
+CMDOT2: equ 0F285H
+CNVRT: equ 0F2CDH
+DLY1M: equ 0F2F1H
+DLY60M: equ 0F2F8H
+DLY80U: equ 0F2EAH
+DLYT: equ 0F2FCH
+ERCK1: equ 0F2BAH
+ERJMP: equ 0F2C7H
+ERRET: equ 0F2C5H
+ERRET1: equ 0F2C1H
+ERRM0: equ 0F0F4H
+ERRM1: equ 0F0C8H
+ERRTR1: equ 0F0ACH
+ERRTRT: equ 0F0A2H
+FDCC: equ 0F105H
+FDX: equ 0F006H
+INTER: equ 0F28FH
+IPLM0: equ 0F0D6H
+IPLM3: equ 0F0E6H
+IPLMC: equ 0F0B8H
+L_F007: equ 0F007H
+L_F051: equ 0F051H
+L_F057: equ 0F057H
+L_F05C: equ 0F05CH
+L_F093: equ 0F093H
+L_F111: equ 0F111H
+L_F189: equ 0F189H
+L_F213: equ 0F213H
+L_F214: equ 0F214H
+L_F23F: equ 0F23FH
+L_F25D: equ 0F25DH
+L_F25E: equ 0F25EH
+L_F282: equ 0F282H
+MASTE: equ 0F09AH
+MCHECK: equ 0F031H
+MOFF: equ 0F167H
+MTD1: equ 0F154H
+MTON: equ 0F14EH
+MZ_1E05: equ 0F000H
+NOTIO: equ 0F0A4H
+PARST1: equ 0F232H
+PARST2: equ 0F262H
+RCLB: equ 0F17FH
+RE3: equ 0F217H
+RE4: equ 0F1F8H
+RE6: equ 0F1F6H
+RE8: equ 0F1E4H
+READY: equ 0F113H
+REDY0: equ 0F12BH
+REDY1: equ 0F149H
+REDY2: equ 0F148H
+REND: equ 0F22DH
+SEEK: equ 0F15FH
+SIDST: equ 0F252H
+SJP: equ 0F022H
+STERROR: equ 0F298H
+TRANS0: equ 0F2D9H
+TRANS1: equ 0F2E0H
diff --git a/software/asm/quickdisk_mz-1e14.asm b/software/asm/quickdisk_mz-1e14.asm
new file mode 100644
index 0000000..cb7910f
--- /dev/null
+++ b/software/asm/quickdisk_mz-1e14.asm
@@ -0,0 +1,1484 @@
+; V1.01
+;
+; To compile use:
+;
+; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor.
+;
+; Available from:
+;   - http://www.falstaff.demon.co.uk/cross.html
+;   - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip
+;   - and many Simtel mirrors.
+;
+; as80 -i -l -n -x2 -v mz-1e14.asm
+
+
+
+
+SIOAD   EQU     0F4h
+SIOBD   EQU     0F5h
+SIOAC   EQU     0F6h
+SIOBC   EQU     0F7h
+
+
+
+;       RxD_A   <-  RDDT (ReaDDaTa)
+;       RxC_A   <-    (read data clock)
+;       TxD_A   ->  #WRDT (WRiteDaTa)
+;       TxC_A   <-  6.5MHz / 4 / 16 = 101562,5Hz
+;       CTS_A    <-    #WRPR (WRitePRotect)
+;        RTS_A    ->    #WRGA (WRiteGAte)
+;       DCD_A   <-  #HDST (HeaDSeT (disk test)
+;
+;       RTS_B   ->    (?)
+;       DCD_B   <-  #HOME ()
+;       DTR_B   ->  #MTON (MoTorON)
+
+
+
+
+GETL    EQU     00003h
+NL      EQU     00009h
+PRNT    EQU     00012h
+GETKY   EQU     0001Bh
+BRKEY   EQU     0001Eh
+CMY0    EQU     0005Bh
+MSGE1   EQU     00147h
+DOT4DE  EQU     002A6h
+?TMST   EQU     00308h
+SPHEX   EQU     003B1h
+SLPT    EQU     003D5h
+HLHEX   EQU     00410h
+_2HEX   EQU     0041Fh
+?WRI    EQU     00436h
+LLPT    EQU     00470h
+?WRD    EQU     00475h
+?RDI    EQU     004D8h
+?RDD    EQU     004F8h
+?VRFY   EQU     00588h
+NLPHL   EQU     005FAh
+?KEY    EQU     008CAh
+?PRTS   EQU     00920h
+MSGOK   EQU     00942h
+PRNT3   EQU     0096Ch
+MSGSV   EQU     0098Bh
+MSG?2   EQU     009A0h
+?BRK    EQU     00A32h
+?ADCN   EQU     00BB9h
+?BLNK   EQU     00DA6h
+?DPCT   EQU     00DDCh
+
+BRKCD   EQU     00
+NTFECD  EQU     40
+HDERCD  EQU     41
+WPRTCD  EQU     46
+QNTRCD  EQU     50
+NFSECD  EQU     53
+UNFMCD  EQU     54
+
+ATRB    EQU     010F0h
+NAME    EQU     010F1h
+SIZE    EQU     01102h
+DTADR   EQU     01104h
+EXADR   EQU     01106h
+COMNT   EQU     01108h
+
+NAMSIZ  EQU     011h
+OBJCD   EQU     001h
+                                                                         ; QD command table
+QDPA    EQU     01130h                                                   ; QD code 1
+QDPB    EQU     01131h                                                   ; QD code 2
+QDPC    EQU     01132h                                                   ; QD header startaddress
+QDPE    EQU     01134h                                                   ; QD header length
+QDCPA   EQU     0113Bh                                                   ; QD error flag
+HDPT    EQU     0113Ch                                                   ; QD new headpoint possition
+HDPT0   EQU     0113Dh                                                   ; QD actual headpoint possition
+FNUPS   EQU     0113Eh
+FNUPF   EQU     01140h
+FNA     EQU     01141h                                                   ; File Number A (actual file number)
+FNB     EQU     01142h                                                   ; File Number B (next file number)
+MTF     EQU     01143h                                                   ; QD motor flag
+RTYF    EQU     01144h
+SYNCF   EQU     01146h                                                   ; SyncFlags
+RETSP   EQU     01147h
+DSPXY   EQU     01171h
+DPRNT   EQU     01194h
+SWRK    EQU     0119Dh
+BUFER   EQU     011A3h
+QDIRBF  EQU     0CD90h
+
+
+
+        ORG     0E800h
+
+MZ1E14:
+LE800:
+        NOP
+        JP LE80A
+        JP ST1X
+QDIOS:
+        JP QDIOS1
+
+LE80A:
+        LD A,0C6h                                                        ; clear screen
+        CALL ?DPCT
+        XOR A
+        LD (DPRNT),A
+        DI
+        XOR A
+        LD DE,00000h
+        CALL ?TMST
+        LD A,001h
+        OUT (SIOBC),A                                                    ; select Write Register 1
+        XOR A
+        OUT (SIOBC),A                                                    ; Rx INT DISABLE
+        CALL GETKY
+        CP 'M'
+        JR Z,MON
+        CP 'Q'
+        JR Z,QBT
+        CALL LEB22                                                       ; check ROM at 0xF000 (FDD)
+        CALL Z,0F006h
+        JR QBT
+;
+;===============================
+;
+;       Quick disk boot-up
+;
+;===============================
+;
+QBT:
+        CALL IOFRS                                                       ; IO Flag ReSet
+        CALL NL
+        CALL QDRCK                                                       ; QuickDisk Ready ChecK
+        JR C,LE868
+        LD A,00Dh                                                        ; set filename to ""
+        LD (BUFER),A
+        CALL HDPCL                                                       ; HeaD Point CLear
+;
+;       Error return set
+;
+        LD A,001h
+        LD (QDCPA),A
+        LD HL,LE86B
+        LD SP,010EEh
+        EX (SP),HL
+;
+;
+        CALL FILSCH                                                      ; filesearch
+        JP C,LEBAC
+        LD A,(ATRB)
+        CP OBJCD                                                         ; is it an "OBJ" file
+        JR NZ,LE871
+;
+;       Quick disk boot
+;
+        LD DE,LEB27
+        RST 018h
+        JP DSFLNA
+
+LE868:
+        LD DE,LEB37
+LE86B:
+        CALL NL
+        RST 018h
+        JR LE87D
+LE871:
+        LD A,006h                                                        ; Motor off
+        LD (QDPA),A
+        CALL QDIOS
+        LD DE,LED4C
+        RST 018h
+LE87D:
+        CALL NL
+
+MON:
+        LD DE,DISCLR                                                     ; '**  MONITOR 9Z-503M  **'
+        RST 018h
+
+
+ST1X:
+        CALL NL
+        LD A,'*'
+        CALL PRNT
+        LD DE,BUFER
+        CALL GETL
+ST2X:
+        LD A,(DE)
+        INC DE
+        CP 00Dh
+        JR Z,ST1X
+        CP 'J'                                                           ; JUMP
+        JR Z,GOTOX
+        CP 'L'                                                           ; Load CMT
+        JR Z,LOADX
+        CP 'F'                                                           ; Floppy boot
+        JR Z,FDCK
+        CP 'B'                                                           ; Bell
+        JP Z,SGX
+        CP '#'
+        JP Z,LEA6A
+        CP 'P'                                                           ; Printer test
+        JP Z,PTESTX
+        CP 'M'                                                           ; Memory correction
+        JP Z,MCORX
+        CP 'S'                                                           ; Save CMT
+        JP Z,SAVEX
+        CP 'V'                                                           ; Verify
+        JP Z,VRFYX
+        CP 'D'                                                           ; Dump memory
+        JP Z,DUMPX
+        CP 'Q'                                                           ; Quick disk cmd.
+        JR NZ,ST2X
+;
+;       Quick disk cmd.
+;
+QUICK:
+        LD HL,00000h
+        LD (0113Ah),HL
+        LD A,(DE)
+        CP 'L'                                                           ; Load QD
+        JP Z,QL
+        CP 'D'                                                           ; Directory
+        JP Z,QD
+ST1X1:
+        JR ST1X
+
+
+FDCK:
+        LD A,(DE)
+        CP 00Dh
+        JR NZ,ST1X1
+        CALL LEB22
+        CALL Z,0F006h
+        JR ST1X1
+?ERX:
+        CP 002h
+        JR Z,ST1X1
+        CALL NL
+        LD DE,MSGE1                                                      ; 'CHECK SUM ER.'
+        RST 018h
+        JR ST1X1
+BGETLX:
+        EX (SP),HL
+        POP BC
+        LD DE,BUFER
+        CALL GETL
+        LD A,(DE)
+        CP 01Bh
+        JR Z,ST1X1
+        JP (HL)
+
+HEXIYX:
+        EX (SP),IY
+        POP AF
+        CALL HLHEX
+        JR C,ST1X1
+        JP (IY)
+
+GOTOX:
+        CALL HEXIYX
+        JP (HL)
+
+               
+LOADX:
+        CALL ?RDI
+        JR C,?ERX
+        CALL NL
+        LD DE,MSG?2                                                      ; 'LOADING '
+        RST 018h
+        LD DE,NAME
+        RST 018h
+        XOR A
+        LD (BUFER),A
+        LD HL,(DTADR)
+        LD A,H
+        OR L
+        JR NZ,LE941
+        LD HL,(EXADR)
+        LD A,H
+        OR L
+        JR NZ,LE941
+        LD A,0FFh
+        LD (BUFER),A
+        LD HL,01200h
+        LD (DTADR),HL
+LE941:
+        CALL ?RDD
+        JR C,?ERX
+        LD A,(BUFER)
+        CP 0FFh
+        JR Z,LE954
+        LD BC,00100h
+        LD HL,(EXADR)
+        JP (HL)
+LE954:
+        OUT (0E0h),A
+        LD HL,01200h
+        LD DE,00000h
+        LD BC,(SIZE)
+        LDIR
+        LD BC,00100h
+        JP 00000h
+
+PTESTX:
+        LD A,(DE)
+        CP '&'                                                           ; plotter test
+        JR NZ,PTST1X
+PTST0X:
+        INC DE
+        LD A,(DE)
+        CP 'L'                                                           ; 40 in 1 line
+        JR Z,.LPTX
+        CP 'S'                                                           ; 80 in 1 line
+        JR Z,..LPTX
+        CP 'C'                                                           ; Pen change
+        JR Z,PENX
+        CP 'G'                                                           ; Graph mode
+        JR Z,PLOTX
+        CP 'T'                                                           ; Test
+        JR Z,PTRNX
+;
+PTST1X:
+        CALL PMSGX
+ST1X2:
+        JP ST1X1
+.LPTX:
+        LD DE,LLPT                                                       ; 01-09-09-0B-0D
+        JR PTST1X
+..LPTX:
+        LD DE,SLPT                                                       ; 01-09-09-09-0D
+        JR PTST1X
+PTRNX:
+        LD A,004h                                                        ; Test pattern
+        JR LE999
+PLOTX:
+        LD A,002h                                                        ; Graph mode
+LE999:
+        CALL LPRNTX
+        JR PTST0X
+PENX:
+        LD A,01Dh                                                        ; 1 change code (text mode)
+        JR LE999
+;
+;
+;       1 char print to $LPT
+;
+;        in: ACC print data
+;
+;
+LPRNTX:
+        LD C,000h                                                        ; RDAX test
+        LD B,A                                                           ; print data store
+        CALL RDAX
+        LD A,B
+        OUT (0FFh),A                                                     ; data out
+        LD A,080h                                                        ; RDP high
+        OUT (0FEh),A
+        LD C,001h                                                        ; RDA test
+        CALL RDAX
+        XOR A                                                            ; RDP low
+        OUT (0FEh),A
+        RET
+;
+;       $LPT msg.
+;       in: DE data low address
+;       0D msg. end
+;
+PMSGX:
+        PUSH DE
+        PUSH BC
+        PUSH AF
+PMSGX1:
+        LD A,(DE)                                                        ; ACC = data
+        CALL LPRNTX
+        LD A,(DE)
+        INC DE
+        CP 00Dh                                                          ; end ?
+        JR NZ,PMSGX1
+        POP AF
+        POP BC
+        POP DE
+        RET
+;
+;       RDA check
+;
+;       BRKEY in to monitor return
+;       in: C RDA code
+;
+RDAX:
+        IN A,(0FEh)
+        AND 00Dh
+        CP C
+        RET Z
+        CALL BRKEY
+        JR NZ,RDAX
+        LD SP,ATRB
+        JR ST1X2
+;
+;       Memory correction
+;       command 'M'
+;
+MCORX:
+        CALL HEXIYX                                                      ; correction address
+MCORX1:
+        CALL NLPHL                                                       ; corr. adr. print
+        CALL SPHEX                                                       ; ACC ASCII display
+        CALL ?PRTS                                                       ; space print
+        CALL BGETLX                                                      ; get data & check data
+        CALL HLHEX                                                       ; HLASCII(DE)
+        JR C,MCRX3
+        CALL DOT4DE                                                      ; INC DE * 4
+        INC DE
+        CALL _2HEX                                                       ; data check
+        JR C,MCORX1
+        CP (HL)
+        JR NZ,MCORX1
+        INC DE
+        LD A,(DE)
+        CP 00Dh                                                          ; not correction
+        JR Z,MCRX2
+        CALL _2HEX                                                       ; ACCHL(ASCII)
+        JR C,MCORX1
+        LD (HL),A                                                        ; data correct
+MCRX2:
+        INC HL
+        JR MCORX1
+MCRX3:
+        LD H,B                                                           ; memory address
+        LD L,C
+        JR MCORX1
+;
+;       Programm save
+;
+;       cmd. 'S'
+;
+SAVEX:
+        CALL HEXIYX                                                      ; Start address
+        LD (DTADR),HL                                                    ; data adress buffer
+        LD B,H
+        LD C,L
+        CALL DOT4DE
+        CALL HEXIYX                                                      ; End address
+        SBC HL,BC                                                        ; byte size
+        INC HL
+        LD (SIZE),HL                                                     ; byte size buffer
+        CALL DOT4DE
+        CALL HEXIYX                                                      ; execute address
+        LD (EXADR),HL                                                    ; buffer
+        CALL NL
+        LD DE,MSGSV                                                      ; 'FILENAME? '
+        RST 018h
+        CALL BGETLX                                                      ; filename input
+        CALL DOT4DE
+        CALL DOT4DE
+        LD HL,NAME                                                       ; name buffer
+SAVX1:
+        INC DE
+        LD A,(DE)
+        LD (HL),A                                                        ; filename trans.
+        INC HL
+        CP 00Dh                                                          ; end code
+        JR NZ,SAVX1
+        LD A,OBJCD                                                       ; attribute: OBJ
+        LD (ATRB),A
+        CALL ?WRI
+?ERX1:
+        JP C,?ERX
+        CALL ?WRD                                                        ; data
+        JR C,?ERX1
+        CALL NL
+        LD DE,MSGOK                                                      ; 'OK!'
+        RST 018h
+LEA5B:
+        JP ST1X
+
+VRFYX:
+        CALL ?VRFY
+        JP C,?ERX
+        LD DE,MSGOK                                                      ; 'OK!'
+        RST 018h
+        JR LEA5B
+LEA6A:
+        JP CMY0
+
+SGX:
+        LD A,(SWRK)
+        RRA
+        CCF
+        RLA
+        LD (SWRK),A
+LEA76:
+        JR LEA5B
+
+DUMPX:
+        CALL HEXIYX
+        CALL DOT4DE
+        PUSH HL
+        CALL HLHEX
+        POP DE
+        JR C,LEAD6
+LEA85:
+        EX DE,HL
+LEA86:
+        LD B,008h
+        LD C,017h
+        CALL NLPHL
+LEA8D:
+        CALL SPHEX
+        INC HL
+        PUSH AF
+        LD A,(DSPXY)
+        ADD A,C
+        LD (DSPXY),A
+        POP AF
+        CP 020h
+        JR NC,LEAA0
+        LD A,02Eh
+LEAA0:
+        CALL ?ADCN
+        CALL PRNT3
+        LD A,(DSPXY)
+        INC C
+        SUB C
+        LD (DSPXY),A
+        DEC C
+        DEC C
+        DEC C
+        PUSH HL
+        SBC HL,DE
+        POP HL
+        JR Z,LEAD3
+        LD A,0F8h
+        LD (0E000h),A
+        NOP
+        LD A,(0E001h)
+        CP 0FEh
+        JR NZ,LEAC7
+        CALL ?BLNK
+LEAC7:
+        DJNZ LEA8D
+LEAC9:
+        CALL ?KEY
+        OR A
+        JR Z,LEAC9
+        CALL ?BRK
+        DB  020h
+LEAD3:
+        DB  0B2h
+      
+        JR LEA76
+LEAD6:
+        LD HL,000A0h
+        ADD HL,DE
+        JR LEA85
+
+FNINP:
+        CALL NL
+        LD DE,MSGSV                                                      ; 'FILENAME? '
+        RST 018h
+        LD DE,BUFER
+        CALL GETL
+        LD A,(DE)
+        CP #1B
+        JR NZ,LEAF3
+        LD HL,ST1X
+        EX (SP),HL
+        RET
+
+LEAF3:
+        LD B,000h
+        LD DE,011ADh
+        LD HL,BUFER
+        LD A,(DE)
+        CP 00Dh
+        JR Z,LEB20
+LEB00:
+        CP 020h
+        JR NZ,LEB08
+        INC DE
+        LD A,(DE)
+        JR LEB00
+LEB08:
+        CP 022h
+        JR Z,LEB14
+LEB0C:
+        LD (HL),A
+        INC HL
+        INC B
+        LD A,011h
+        CP B
+        JR Z,FNINP
+LEB14:
+        INC DE
+        LD A,(DE)
+        CP 022h
+        JR Z,LEB1E
+        CP 00Dh
+        JR NZ,LEB0C
+LEB1E:
+        LD A,00dh
+LEB20:
+        LD (HL),A
+        RET
+
+LEB22:
+        LD A,(0F000h)
+        OR A
+        RET
+               
+
+LEB27:  DB      "IPL IS LOADING ",00Dh
+LEB37:  DB      "MAKE READY QD",00Dh
+DISCLR: DB      "**  MONITOR 9Z-503M  **",00Dh
+
+;
+;====================================
+;
+;       QUICK DISK LOAD COMMAND
+;
+;====================================
+;
+QL:
+        CALL IOFRS
+        CALL QDRCK                                                       ; Ready check
+        JR C,LEBAC
+        CALL FNINP                                                       ; Input filename
+        CALL HDPCL                                                       ; Head point clear
+;
+;       Disp 'Loading...'
+;
+        LD DE,MSG?2                                                      ; 'LOADING '
+        RST 018h
+;
+;       File search
+;
+FILESH:
+        CALL FILSCH
+        JR C,LEBAC
+;
+;       Atribute check
+;
+        LD A,(ATRB)
+        CP OBJCD
+        JR NZ,FILESH
+;
+;
+;
+DSFLNA:
+        LD DE,NAME
+        RST 018h
+
+        LD HL,(EXADR)
+        LD A,H
+        OR L
+        JR NZ,LEB8B
+        LD HL,(COMNT)
+        LD A,H
+        OR L
+LEB8B:
+        JR NZ,LPARA0
+        LD A,0FFh
+        LD (0113Ah),A
+
+
+
+;
+;       Iocs parameter set
+;
+        LD HL,01200h
+        JR LPARA1
+LPARA0:
+        LD HL,(EXADR)
+LPARA1:
+        LD (QDPC),HL                                                     ; Data adrs set
+        LD HL,(DTADR)
+        LD (QDPE),HL
+        LD HL,00103h                                                     ; Read data block cmd.
+        LD (QDPA),HL                                                     ; QDPA = 3 (read from headpoint)
+                                                                         ; QDPB = 1 (data should be read)
+;
+;       Read data block
+;
+        CALL QDIOS                                                       ; QD iocs
+LEBAC:
+        JP C,QER04
+        LD A,(0113Ah)
+        CP 0FFh
+        JR Z,LEBBD
+;
+;       Exec load file
+;
+        LD BC,00300h
+        LD HL,(COMNT)
+        JP (HL)
+
+LEBBD:
+        OUT (0E0h),A
+        LD HL,01200h
+        LD DE,00000h
+        LD BC,(DTADR)
+        LDIR
+        LD BC,00300h
+        JP 00000h
+
+;
+;       Iocs flag reset
+;
+IOFRS:
+        XOR A
+        LD (MTF),A                                                       ; Motor Flag = 0 (OFF)
+        LD (FNUPS),A                                                     ; File number flag = 0
+        LD (FNUPF),A                                                     ; File number up flag = 0
+        RET
+
+;
+;
+;       File search sub.
+;
+;
+FILSCH:
+;
+;       Iocs parameter set
+;
+        LD HL,00003h                                                     ; read from headpoint
+        LD (QDPA),HL                                                     ; QDPA = 3 (read from head point)
+                                                                         ; QDPB = 0 (header should be read)
+        LD HL,ATRB                                                       ; Head adrs
+        LD (QDPC),HL
+        LD HL,00040h                                                     ; Read size
+        LD (QDPE),HL
+
+;
+;       Read information block
+;
+QLINF:
+        CALL QDIOS
+        RET C
+;
+;       File name check
+;
+        LD A,(BUFER)
+        CP 00Dh
+        RET Z
+        LD HL,BUFER
+        LD DE,NAME
+        LD B,NAMSIZ
+LDFNCK:
+        LD A,(DE)
+        CP (HL)
+        JR NZ,QLINF
+        CP 00Dh
+        RET Z
+        INC DE
+        INC HL
+        DJNZ LDFNCK
+        RET
+;
+;       Quick disk ready check
+;
+QDRCK:
+        XOR A
+        LD (QDPB),A                                                      ; QDPB = 0 -> only Ready check
+        INC A
+        LD (QDPA),A                                                      ; QDPA = 1
+        CALL QDIOS
+        RET
+;
+;======================================
+;
+;       Quick disk directory command
+;
+;======================================
+;
+QD:
+        CALL IOFRS
+        CALL QDRCK
+        JR C,QER04
+        CALL HDPCL
+        LD B,000h
+;
+;       Disp 'Directory of QD:'
+;
+        LD DE,DIRMSG
+        RST 018h
+;
+;       Iocs parameter set
+;
+        LD HL,QDIRBF
+DIRIOP:
+        LD (QDPC),HL
+        LD HL,00003h
+        LD (QDPA),HL                                                     ; QDPA = 3 (read from headpoint)
+                                                                         ; QDPB = 0 (header should be read)
+        LD HL,00040h
+        LD (QDPE),HL                                                     ; QDPE = 64 (header length)
+;
+;       Read information block
+;
+        PUSH BC
+        CALL QDIOS
+        POP BC
+        JR C,DIREFC
+        INC B
+;
+;       Buffer adrs increment
+;
+        LD HL,(QDPC)
+        LD DE,PRNT
+        ADD HL,DE
+        JR DIRIOP
+;
+;       End file check
+;
+DIREFC:
+        CP NTFECD
+        JR Z,DIRMTF
+        SCF
+QER04:
+        JR C,QERTRT
+;
+;       Motor off
+;
+DIRMTF:
+        LD A,006h                                                        ; Motor off command
+        LD (QDPA),A
+        PUSH BC
+        CALL QDIOS
+        POP BC
+;
+;       No file check
+;
+        XOR A
+        CP B
+        JR NC,QDOKM
+;
+;       Directory disp
+;
+        CALL NL
+        LD HL,QDIRBF
+;
+;       Disp atribute
+;
+DSPATR:
+        LD A,(HL)
+        LD DE,MSGQ01
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ02
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ03
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ04
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ05
+        DEC A
+        JR Z,LECA4
+        DEC A
+        JR Z,LECA1
+        LD DE,MSGQ07
+        DEC A
+        JR Z,LECA4
+        DEC A
+        JR Z,LECA1
+        DEC A
+        JR Z,LECA1
+        LD DE,MSGQ10
+        DEC A
+        JR Z,LECA4
+        LD DE,MSGQ11
+        DEC A
+        JR Z,LECA4
+LECA1:
+        LD DE,MSGQ??
+LECA4:
+        RST 018h
+;
+;       Disp file name
+;
+LECA5:
+        LD A,'"'
+        CALL PRNT
+        INC HL
+        PUSH HL
+        POP DE
+        RST 018h
+        LD A,'"'
+        CALL PRNT
+        CALL NL
+;
+;       Counter decrement
+;
+LECB6:
+        LD DE,00011h
+        ADD HL,DE
+LECBA:
+        CALL ?KEY
+        OR A
+        JR Z,LECBA
+        CALL ?BRK
+        JP Z,ST1X
+        DJNZ DSPATR
+
+QDOKM:
+        CALL NL
+        LD DE,MSGQOK
+        RST 018h
+        JP ST1X
+
+;
+;======================================
+;
+;       Error treatment
+;
+;=====================================
+;
+QERTRT:
+        LD DE,MGNFE                                                      ; 'Not Found err'
+        CP NTFECD                                                        ; Not found err
+        JR Z,QERMF
+        LD DE,MGNRE                                                      ; 'Not ready'
+        CP QNTRCD                                                        ; Not ready
+        JR Z,QERMF
+        LD DE,MGUFE                                                      ; 'Unformat'
+        CP UNFMCD                                                        ; Unformat err
+        JR Z,QERMF
+        LD DE,MSGTRM
+        CP BRKCD                                                         ; Break
+        JR Z,QERMF
+        LD DE,MGHDE                                                      ; 'Hard error'
+;
+;       Motor off
+;
+QERMF:
+        LD A,006h                                                        ; Motor off cmd.
+        LD (QDPA),A
+        CALL QDIOS
+        CALL HDPCL
+;
+LECFC:
+        LD A,(QDCPA)
+        RRA
+        RET C                                                            ; Boot err
+        CALL NL
+        RST 018h
+        JP ST1X
+;
+;       Header point clear
+;
+HDPCL:
+        LD A,005h                                                        ; Head point clear cmd.
+        LD (QDPA),A
+        CALL QDIOS
+        RET
+
+;
+;======================================
+;
+;       Message table
+;
+;======================================
+;
+MSGQOK: DB      "OK!"
+MSGTRM: DB      00Dh
+MGNFE:  DB      "QD:FILE NOT FOUND",00Dh
+MGHDE:  DB      "QD:HARD ERR",00Dh
+MGNRE:  DB      "QD:NOT READY",00Dh
+MGUFE:  DB      "QD:UNFORMAT",00Dh
+LED4C:  DB      "QD:FILE MODE ERR",00Dh
+DIRMSG: DB      "DIRECTORY OF QD:",00Dh
+MSGQ01: DB      "    OBJ   ",00Dh
+MSGQ02: DB      "    BTX   ",00Dh
+MSGQ03: DB      "    BSD   ",00Dh
+MSGQ04: DB      "    BRD   ",00Dh
+MSGQ05: DB      "    RB    ",00Dh
+MSGQ07: DB      "    LIB   ",00Dh
+MSGQ10: DB      "    SYS   ",00Dh
+MSGQ11: DB      "    GR    ",00Dh
+MSGQ??: DB      "    ???   ",00Dh
+
+
+QDIOS1:
+        LD A,005h                                                        ; Retry 4
+        LD (RTYF),A
+;
+RTY:
+        DI
+        CALL QMEIN
+        EI
+        RET NC
+        PUSH AF
+        CP 028h
+        JR Z,RTY4
+        CALL MTOF
+        POP AF
+        PUSH AF
+        CP 029h
+        JR NZ,RTY4
+        LD HL,RTYF
+        DEC (HL)
+        JR Z,LEDF3
+        POP AF
+        JR RTY
+LEDF3:
+        CALL QDHPC
+RTY4:
+        POP AF
+        RET
+
+QMEIN:
+        LD (RETSP),SP
+        LD A,(QDPA)
+        DEC A                                                            ; ready check           (1)
+        JR Z,QDRC
+        DEC A                                                            ; format                (2)
+                                                                         ; not implemented
+        DEC A                                                            ; read from headpoint   (3)
+        JR Z,QDRD
+        DEC A                                                            ; save from headpoint   (4)
+                                                                         ; not implemented
+        DEC A                                                            ; headpoint clear       (5)
+        JR Z,QDHPC
+        JP MTOF                                                          ; else motor off
+;
+;======================================
+;
+;       Head Point Clear
+;
+;======================================
+;
+QDHPC:
+        PUSH AF
+        XOR A
+        LD (HDPT),A
+        POP AF
+        RET
+;
+;=================================
+;
+;       Ready Check
+;
+;=================================
+;
+QDRC:
+        LD A,(QDPB)                                                      ; QDPB = 0 -> only Ready check
+        JP QREDY
+;
+;=================================
+;
+;       Read
+;
+;=================================
+;
+QDRD:
+        LD A,(MTF)                                                       ; A = Motor Flag
+        OR A                                                             ; test Motor Flag
+        CALL Z,MTON                                                      ; if Motor Flag = 0 then Motor On and go to home position
+        CALL HPS                                                         ; head point search
+        RET C
+        CALL BRKC                                                        ; check break key
+;
+        CALL RDATANRCK                                                   ; read low-byte blocksize
+        LD C,A
+        CALL RDATANRCK                                                   ; read high-byte blocksize
+        LD B,A
+        LD HL,(QDPE)
+        SBC HL,BC                                                        ;
+        JP C,IOE41
+        LD HL,(QDPC)
+;
+; Block Data Read
+;
+BDR:
+        CALL RDATANRCK                                                   ; read data
+        LD (HL),A                                                        ; save it
+        INC HL                                                           ; inc address
+        DEC BC                                                           ; dec counter
+        LD A,B
+        OR C
+        JR NZ,BDR                                                        ; counter not zero than read again
+        CALL RDCRC                                                       ; read checksum (3 bytes)
+        LD A,(QDPB)
+        BIT 0,A
+        JP NZ,MTOF
+        RET
+;
+; Head Point Search
+;
+HPS:
+        LD HL,FNB                                                        ; HL = next file number
+        DEC (HL)
+        JR Z,HPNFE                                                       ; Not found
+        CALL SYNCL2                                                      ; read 2 bytes last is in A
+        LD C,A                                                           ; BLocKFLaG => C reg
+        LD A,(HDPT)                                                      ; A = destination head point position
+        LD HL,HDPT0                                                      ; HL = address of the actual head point position
+        CP (HL)                                                          ; Search ok ?
+        JR NZ,HPS1                                                       ; no, than make dummy block read
+        INC A                                                            ; HDPT count up
+        LD (HDPT),A
+        LD (HL),A                                                        ; HDPT0 count up
+        LD A,(QDPB)                                                      ; A = filetype to load
+        XOR C                                                            ; xor with BLocKFLaG which
+        RRA
+        RET NC                                                           ; same, than ret else ...
+;
+; Dummy read
+;
+DMR:
+        CALL RDATANRCK                                                   ; read size low byte
+        LD C,A
+        CALL RDATANRCK                                                   ; read size high byte
+        LD B,A
+;
+DMR1:                                                                    ; read size bytes
+        CALL RDATANRCK
+        DEC BC
+        LD A,B
+        OR C
+        JR NZ,DMR1
+        CALL RDCRC                                                       ; read checksum (3 bytes)
+        JR HPS                                                           ; next
+;
+HPS1:
+        INC (HL)                                                         ; increment actual head point position
+        JR DMR
+;
+HPNFE:
+        LD A,NTFECD                                                      ; Not Found
+        SCF
+        RET
+
+
+
+;
+; Ready & Write protect
+;       ACC = 0 : Ready check
+;       ACC = 1 : & Write Protect
+;
+QREDY:
+        LD B,A                                                           ; save command
+        LD A,002h
+        OUT (SIOBC),A                                                    ; select register 2 (IV)
+        LD A,081h
+        OUT (SIOBC),A                                                    ; write 81h in register 2
+        LD A,002h
+        OUT (SIOBC),A                                                    ; select register 2 (IV)
+        IN A,(SIOBC)                                                     ; read back register 2
+        AND 081h
+        CP 081h
+        JP NZ,IOE50                                                      ; Not ready
+        LD A,010h
+        OUT (SIOAC),A                                                    ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0
+        IN A,(SIOAC)
+        LD C,A                                                           ; save Read Register 0
+        AND 008h                                                         ; test DCD (HeadSet)
+        JP Z,IOE50                                                       ; Not ready
+        LD A,B                                                           ; restore command
+        OR A                                                             ; if command = 0 then
+        RET Z                                                            ; return
+        LD A,C                                                           ; else restore Read Register 0
+        AND 020h                                                         ; test CTS (WriteProtect)
+        RET NZ                                                           ; if CTS then not protected, return
+        JP IOE46                                                         ; else Write protect
+
+;
+;
+; MTON -- QD MOTOR ON
+;         READ FILE NUMBER
+;         READ & CHECK CRC,FLAG
+;
+MTON:
+        LD HL,SIOLD                                                      ; SIO Load Data
+        LD B,00Bh
+        CALL LSINT                                                       ; load SIO init and motor on and go to home position
+
+        CALL SYNCL1                                                      ; search for sync and read first 2 bytes, last is in A
+        LD (FNA),A                                                       ; save actual file no in File Number A
+        INC A
+        LD (FNB),A                                                       ; save next file no in File Number B
+        CALL RDCRC                                                       ; read checksum (3 bytes)
+FNEND:
+        LD HL,SYNCF
+        SET 3,(HL)                                                       ; set bit3 of SyncFlags
+        XOR A                                                            ; A = 0
+        LD (HDPT0),A                                                     ; actual head point position = 0
+        RET
+;
+;       sio initial
+;
+LSINT:
+        LD C,SIOAC
+        OTIR
+        LD A,005h                                                        ; 00000101
+        LD (MTF),A                                                       ; MoTor Flag = 5
+        OUT (SIOBC),A                                                    ; ch B select register 5
+        LD A,080h                                                        ; 10000000
+        OUT (SIOBC),A                                                    ; set DTR_B (Motor On), clear RTS_B
+
+LREDY:                                                                   ; check for ready and if so, than goto home position
+        LD A,010h                                                        ; 00010000
+        OUT (SIOAC),A                                                    ; reset ext/status interrupts, set register 0
+        IN A,(SIOAC)                                                     ; read register 0
+        AND 008h                                                         ; test DCD_A (disk inside ?)
+        JP Z,IOE50                                                       ; Not ready
+        CALL BRKC                                                        ; BReak Key Check
+        LD A,010h                                                        ; 00010000
+        OUT (SIOBC),A                                                    ; reset ext/status interrupts, set register 0
+        IN A,(SIOBC)                                                     ; read register 0
+        AND 008h                                                         ; test DCD_B (Home)
+        JR Z,LREDY
+        LD BC,000E9h                                                     ; wait 160ms
+        JP TIMW
+
+;
+; Motor off
+;
+QDOFF:                                                                   ; basic call
+MTOF:
+        PUSH AF
+        LD A,005h
+        OUT (SIOAC),A                                                    ; select Write Register 5
+        LD A,060h                                                        ; 01100000
+        OUT (SIOAC),A                                                    ; DTR OFF (Motor Off), Tx DISABLE, RTS OFF (WRGA)
+        LD A,005h
+        OUT (SIOBC),A                                                    ; select Write Register 5
+        XOR A                                                            ; 00000000
+        LD (MTF),A                                                       ; Motor Flag = 0
+        OUT (SIOBC),A                                                    ; DTR OFF (Motor Off), clear  RTS_B
+        POP AF
+        RET
+
+;
+; SYNCL1 -- LOAD F.N SYNC ONLY
+;                (SEND BREAK 110ms)
+; SYNCL2 -- LOAD FIRST FILE SYNC
+;                (SEND BREAK 110ms)
+;
+SYNCL2:
+        LD A,058h                                                        ; 01011000
+                                                                         ; RESET Rx CRC CHECKER, CHANNEL RESET, REGISTER 0
+        LD B,00Bh                                                        ; 11 values to load
+        LD HL,SIOLD
+        CALL SYNCA
+        LD HL,SYNCF
+        BIT 3,(HL)                                                       ; test bit3 of SyncFlags
+        LD BC,00003h                                                     ; WAIT 2ms
+        JR Z,TMLPL
+        RES 3,(HL)                                                       ; reset bit3 of SyncFlags
+SYNCL1:
+        ld bc,000a0h                                                     ; WAIT 110ms
+;
+TMLPL:                                                                   ; the motor is switched on
+                                                                         ; and a hunt phase is initiated,
+                                                                         ; that means the incoming datastream
+                                                                         ; is inspected for the programmed 
+                                                                         ; sync characters
+        CALL TIMW
+        LD A,005h
+        OUT (SIOBC),A                                                    ; select Write Register 5
+        LD A,082h                                                        ; 10000010
+        OUT (SIOBC),A                                                    ; DTR ON (Motor On), RTS ON ()
+        LD A,003h
+        OUT (SIOAC),A                                                    ; select Write Register 3
+        LD A,0D3h                                                        ; 11010011
+        OUT (SIOAC),A                                                    ; RX 8 BIT, ENTER HUNT PHASE, SYNC, Rx ENABLE
+        LD BC,02CC0h                                                     ; 220ms timeout
+;
+SYNCW0:                                                                  ; now the datastream is inspected
+                                                                         ; also a timeout is checked
+        LD A,010h
+        OUT (SIOAC),A                                                    ; RESET EXT/STATUS INT, select Register 0
+        IN A,(SIOAC)
+        AND 010h                                                         ; test SYNC/HUNT
+        JR Z,SYNCW1                                                      ; first 2 syncbytes found
+        DEC BC
+        LD A,B
+        OR C
+        JR NZ,SYNCW0
+        JP IOE54                                                         ; unformatted
+;
+SYNCW1:                                                                  ; now we should ignore further sync characters
+        LD A,003h
+        OUT (SIOAC),A                                                    ; select Write Register 3
+        LD A,0C3h                                                        ; 11000011
+        OUT (SIOAC),A                                                    ; Rx 8 BIT, SYNC CHAR LOAD INHIBIT, Rx ENABLE
+        LD B,09Fh                                                        ; timeout
+;
+SYNCW2:
+                                                                         ; loop for find the end of syncbytes:
+                                                                         ; rx available is only set if the first
+                                                                         ; byte is found which is not a syncbyte
+        LD A,010h
+        OUT (SIOAC),A                                                    ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0
+        IN A,(SIOAC)
+        AND 001h                                                         ; test Rx CHARACTER AVAILABLE
+        JR NZ,SYNCW3
+        DEC B
+        JR NZ,SYNCW2
+SYNCW01:
+        JP IOE54                                                         ; unformated
+;
+SYNCW3:                                                                  ; now the datastream is in sync and the
+                                                                         ; first real data is ready to read
+        LD A,003h
+        OUT (SIOAC),A                                                    ; select Write Register 3
+        LD A,0C9h                                                        ; 11001001
+        OUT (SIOAC),A                                                    ; Rx 8 BIT, Rx CRC ENABLE, Rx ENABLE
+        CALL RDATANRCK
+        JP RDATANRCK
+
+;
+;
+;
+SYNCA:
+        LD C,SIOAC
+        OUT (C),A
+        LD A,005h
+        OUT (SIOBC),A                                                    ; select Write Register 5
+        LD A,080h
+        OUT (SIOBC),A                                                    ; set DTR_B (Motor On), clear RTS_B
+        OTIR
+        RET
+
+;
+;       RDCRC -- READ CRC & CHECK
+;
+RDCRC:
+        LD B,003h                                                        ; 3 retries
+RDCR1:
+        CALL RDATANRCK                                                   ; read 3 bytes
+        DJNZ RDCR1
+RDCR2:                                                                   ; read REGISTER 0
+        IN A,(SIOAC)
+        RRCA                                                             ; test Rx CHARACTER AVAILABLE
+        JR NC,RDCR2                                                      ; Rx Available
+        LD A,001h                
+        OUT (SIOAC),A                                                    ; select REGISTER 1
+        IN A,(SIOAC)                                                     ; read REGISTER 1
+        AND 040h                                                         ; test CRC ERROR
+        JR NZ,IOE41                                                      ; Hard err
+        OR A
+        RET
+
+RDATANRCK:
+NRCK:
+        LD A,010h
+        OUT (SIOAC),A                                                    ; reset ext/status interrupts, set register 0
+        IN A,(SIOAC)                                                     ; read register 0
+        AND 008h                                                         ; test DCD (HeadSet)
+        JP Z,IOE50                                                       ; Not Ready
+;
+;       Read data (1 chr)
+;
+RDATA:
+        IN A,(SIOAC)                                                     ; read REGISTER 0
+        RLCA
+        JR C,IOE41                                                       ; test BREAK/ABORT (Hard Err)
+        RRCA
+        RRCA
+        JR NC,NRCK                                                       ; test Rx AVAILABLE
+        IN A,(SIOAD)                                                     ; read data
+        OR A
+        RET
+               
+;
+;       i/o err
+;
+IOE41:
+        LD A,HDERCD                                                      ; Hard err
+        DB 021h
+IOE46:
+        LD A,WPRTCD                                                      ; Write protect
+        DB 021h
+IOE50:
+        LD A,QNTRCD                                                      ; Not ready
+        DB 021h
+IOE53:
+        LD A,NFSECD                                                      ; No file space
+        DB 021h
+IOE54:
+        LD A,UNFMCD                                                      ; Unformat
+        LD SP,(RETSP)
+        SCF
+        RET
+               
+
+;
+;       wait timer
+;
+;
+;       BC = 0001H =   0.7ms (  0.704ms)
+;            0003H =   2.0ms (  2.107ms)
+;            001DH =  20.0ms ( 19.938ms)
+;            00A0H = 110.0ms (110.050ms)
+;            00E9H = 160.0ms (160.140ms)
+;            0140H = 220.0ms (219.940ms)
+;
+;
+TIMW:
+        PUSH AF
+TIMW1:
+        LD A,086h
+TIMW2:
+        DEC A
+        JR NZ,TIMW2
+        DEC BC
+        LD A,B
+        OR C
+        JR NZ,TIMW1
+        POP AF
+        RET
+
+;
+;
+;
+; SIO CH A COMMAND CHAIN
+;
+; SIOLD -- LOAD INIT. DATA
+;
+;
+;
+; BiSync mode, uses 16h and 16h as sync characters
+; the SIO works also in polling mode, no interrupt is generated
+;
+SIOLD:
+        DB      058h                                                     ; RESET Rx CRC CHECKER, CHANNEL RESET
+        DB      004h                                                     ; select Write Register 4
+        DB      010h                                                     ; X1 CLOCK mode, 16 bit sync char, sync mode, no parity
+        DB      005h                                                     ; select Write Register 5
+        DB      004h                                                     ; CRC-16
+        DB      003h                                                     ; select Write Register 3
+        DB      0D0h                                                     ; RX 8 BITS, AUTO ENABLES, ENTER HUNT PHASE
+        DB      006h                                                     ; select Write Register 6
+        DB      016h                                                     ; set SYNC CHR(1)
+        DB      007h                                                     ; select Write Register 7
+        DB      016h                                                     ; set SYNC CHR(2)
+
+
+;
+;
+; BREAK CHECK
+;
+BRKC:
+        LD A,0E8h
+        LD (0E000h),A
+        NOP
+        LD A,(0E001h)
+        AND 081h
+        RET NZ
+        LD SP,(RETSP)
+        SCF
+        RET
+               
+        ld l,#41
+
+; the following is only to get the original length of 4096 bytes
+ALIGN:  MACRO ?boundary
+        DS    ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, 0FFh
+        ENDM
+
+        ALIGN 0F7FFh
+        DB      0FFh
diff --git a/software/asm/quickdisk_mz-1e14.obj b/software/asm/quickdisk_mz-1e14.obj
new file mode 100644
index 0000000..aac54ba
Binary files /dev/null and b/software/asm/quickdisk_mz-1e14.obj differ
diff --git a/software/asm/quickdisk_mz-1e14.sym b/software/asm/quickdisk_mz-1e14.sym
new file mode 100644
index 0000000..1952597
--- /dev/null
+++ b/software/asm/quickdisk_mz-1e14.sym
@@ -0,0 +1,161 @@
+..LPTX: equ 0E98EH
+.LPTX: equ 0E989H
+?ERX: equ 0E8EBH
+?ERX1: equ 0EA4CH
+BDR: equ 0EE3BH
+BGETLX: equ 0E8F8H
+BRKC: equ 0EFECH
+DIREFC: equ 0EC4CH
+DIRIOP: equ 0EC2CH
+DIRMSG: equ 0ED5DH
+DIRMTF: equ 0EC53H
+DISCLR: equ 0EB45H
+DMR: equ 0EE6FH
+DMR1: equ 0EE77H
+DSFLNA: equ 0EB7BH
+DSPATR: equ 0EC67H
+DUMPX: equ 0EA78H
+FDCK: equ 0E8DEH
+FILESH: equ 0EB6FH
+FILSCH: equ 0EBDCH
+FNEND: equ 0EECCH
+FNINP: equ 0EADCH
+GOTOX: equ 0E910H
+HDPCL: equ 0ED08H
+HEXIYX: equ 0E906H
+HPNFE: equ 0EE87H
+HPS: equ 0EE51H
+HPS1: equ 0EE84H
+IOE41: equ 0EFC0H
+IOE46: equ 0EFC3H
+IOE50: equ 0EFC6H
+IOE53: equ 0EFC9H
+IOE54: equ 0EFCCH
+IOFRS: equ 0EBD1H
+LDFNCK: equ 0EC00H
+LE800: equ 0E800H
+LE80A: equ 0E80AH
+LE868: equ 0E868H
+LE86B: equ 0E86BH
+LE871: equ 0E871H
+LE87D: equ 0E87DH
+LE941: equ 0E941H
+LE954: equ 0E954H
+LE999: equ 0E999H
+LEA5B: equ 0EA5BH
+LEA6A: equ 0EA6AH
+LEA76: equ 0EA76H
+LEA85: equ 0EA85H
+LEA86: equ 0EA86H
+LEA8D: equ 0EA8DH
+LEAA0: equ 0EAA0H
+LEAC7: equ 0EAC7H
+LEAC9: equ 0EAC9H
+LEAD3: equ 0EAD3H
+LEAD6: equ 0EAD6H
+LEAF3: equ 0EAF3H
+LEB00: equ 0EB00H
+LEB08: equ 0EB08H
+LEB0C: equ 0EB0CH
+LEB14: equ 0EB14H
+LEB1E: equ 0EB1EH
+LEB20: equ 0EB20H
+LEB22: equ 0EB22H
+LEB27: equ 0EB27H
+LEB37: equ 0EB37H
+LEB8B: equ 0EB8BH
+LEBAC: equ 0EBACH
+LEBBD: equ 0EBBDH
+LECA1: equ 0ECA1H
+LECA4: equ 0ECA4H
+LECA5: equ 0ECA5H
+LECB6: equ 0ECB6H
+LECBA: equ 0ECBAH
+LECFC: equ 0ECFCH
+LED4C: equ 0ED4CH
+LEDF3: equ 0EDF3H
+LOADX: equ 0E914H
+LPARA0: equ 0EB97H
+LPARA1: equ 0EB9AH
+LPRNTX: equ 0E9A2H
+LREDY: equ 0EEE5H
+LSINT: equ 0EED6H
+MCORX: equ 0E9D9H
+MCORX1: equ 0E9DCH
+MCRX2: equ 0EA05H
+MCRX3: equ 0EA08H
+MGHDE: equ 0ED27H
+MGNFE: equ 0ED15H
+MGNRE: equ 0ED33H
+MGUFE: equ 0ED40H
+MON: equ 0E880H
+MSGQ01: equ 0ED6EH
+MSGQ02: equ 0ED79H
+MSGQ03: equ 0ED84H
+MSGQ04: equ 0ED8FH
+MSGQ05: equ 0ED9AH
+MSGQ07: equ 0EDA5H
+MSGQ10: equ 0EDB0H
+MSGQ11: equ 0EDBBH
+MSGQ??: equ 0EDC6H
+MSGQOK: equ 0ED11H
+MSGTRM: equ 0ED14H
+MTOF: equ 0EF03H
+MTON: equ 0EEB7H
+MZ1E14: equ 0E800H
+NRCK: equ 0EFA8H
+PENX: equ 0E99EH
+PLOTX: equ 0E997H
+PMSGX: equ 0E9B8H
+PMSGX1: equ 0E9BBH
+PTESTX: equ 0E968H
+PTRNX: equ 0E993H
+PTST0X: equ 0E96DH
+PTST1X: equ 0E983H
+QBT: equ 0E835H
+QD: equ 0EC18H
+QDHPC: equ 0EE0DH
+QDIOS: equ 0E807H
+QDIOS1: equ 0EDD1H
+QDOFF: equ 0EF03H
+QDOKM: equ 0ECC8H
+QDRC: equ 0EE14H
+QDRCK: equ 0EC0CH
+QDRD: equ 0EE1AH
+QER04: equ 0EC51H
+QERMF: equ 0ECF1H
+QERTRT: equ 0ECD2H
+QL: equ 0EB5DH
+QLINF: equ 0EBEEH
+QMEIN: equ 0EDF8H
+QREDY: equ 0EE8BH
+QUICK: equ 0E8CBH
+RDATA: equ 0EFB3H
+RDATANRCK: equ 0EFA8H
+RDAX: equ 0E9C9H
+RDCR1: equ 0EF92H
+RDCR2: equ 0EF97H
+RDCRC: equ 0EF90H
+RTY: equ 0EDD6H
+RTY4: equ 0EDF6H
+SAVEX: equ 0EA0CH
+SAVX1: equ 0EA3CH
+SGX: equ 0EA6DH
+SIOLD: equ 0EFE1H
+ST1X: equ 0E884H
+ST1X1: equ 0E8DCH
+ST1X2: equ 0E986H
+ST2X: equ 0E892H
+SYNCA: equ 0EF81H
+SYNCL1: equ 0EF2EH
+SYNCL2: equ 0EF18H
+SYNCW0: equ 0EF47H
+SYNCW01: equ 0EF70H
+SYNCW1: equ 0EF59H
+SYNCW2: equ 0EF63H
+SYNCW3: equ 0EF73H
+TIMW: equ 0EFD4H
+TIMW1: equ 0EFD5H
+TIMW2: equ 0EFD7H
+TMLPL: equ 0EF31H
+VRFYX: equ 0EA5EH
diff --git a/software/asm/ramcheck.asm b/software/asm/ramcheck.asm
new file mode 100644
index 0000000..dce76f5
--- /dev/null
+++ b/software/asm/ramcheck.asm
@@ -0,0 +1,155 @@
+
+LETNL:     EQU     0006h
+PRNTS:     EQU     000Ch
+PRNT:      EQU     0012h
+MSG:       EQU     0015h
+MONIT:     EQU     0086h
+PRTHL:     EQU     03BAh
+PRTHX:     EQU     03C3h
+DPCT:      EQU     0DDCh
+MSTART:    EQU     1200h
+
+           ORG     10F0h
+
+           DB      01h                                                                                     ; Code Type, 01 = Machine Code.
+           DB      "RAM TEST V1.0", 0Dh, 00h, 00h                                                         ; Title/Name (17 bytes).
+           DW      MSTART - START                                                                          ; Size of program.
+           DW      START                                                                                   ; Load address of program.
+           DW      START                                                                                   ; Exec address of program.
+           DB      00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h          ; Comment (104 bytes).
+           DB      00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+           DB      00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+           DB      00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+           DB      00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+           DB      00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+           DB      00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+
+           ORG     01200h
+
+START:     LD      DE,TITLE
+           CALL    MSG
+           CALL    LETNL
+           LD      B, 20       ; Number of loops
+LOOP:      LD      HL,MSTART   ; Start of checked memory,
+           LD      D,0CEh      ; End memory check CE00
+LOOP1:     LD      A,000h
+           CP      L
+           JR      NZ,LOOP1b
+           CALL    PRTHL       ; Print HL as 4digit hex.
+           LD      A,0C4h      ; Move cursor left.
+           LD      E,004h      ; 4 times.
+LOOP1a:    CALL    DPCT
+           DEC     E
+           JR      NZ,LOOP1a
+LOOP1b:    INC     HL
+           LD      A,H
+           CP      D           ; Have we reached end of memory.
+           JR      Z,LOOP3     ; Yes, exit.
+           LD      A,(HL)      ; Read memory location under test, ie. 0.
+           CPL                 ; Subtract, ie. FF - A, ie FF - 0 = FF.
+           LD      (HL),A      ; Write it back, ie. FF.
+           SUB     (HL)        ; Subtract written memory value from A, ie. should be 0.
+           JR      NZ,LOOP2    ; Not zero, we have an error.
+           LD      A,(HL)      ; Reread memory location, ie. FF
+           CPL                 ; Subtract FF - FF
+           LD      (HL),A      ; Write 0
+           SUB     (HL)        ; Subtract 0
+           JR      Z,LOOP1     ; Loop if the same, ie. 0
+LOOP2:     LD      A,16h
+           CALL    PRNT        ; Print A
+           CALL    PRTHX       ; Print HL as 4 digit hex.
+           CALL    PRNTS       ; Print space.
+           XOR     A
+           LD      (HL),A
+           LD      A,(HL)      ; Get into A the failing bits.
+           CALL    PRTHX       ; Print A as 2 digit hex.
+           CALL    PRNTS       ; Print space.
+           LD      A,0FFh      ; Repeat but first load FF into memory
+           LD      (HL),A
+           LD      A,(HL)
+           CALL    PRTHX       ; Print A as 2 digit hex.
+           NOP
+           JR      LOOP4
+
+LOOP3:     LD      DE,OKCHECK
+           CALL    MSG         ; Print check message in DE
+           LD      A,B         ; Print loop count.
+           CALL    PRTHX
+           LD      DE,OKMSG
+           CALL    MSG         ; Print ok message in DE
+           DEC     B
+           JR      NZ,LOOP
+           LD      DE,DONEMSG
+           CALL    MSG         ; Print check message in DE
+           JP      MONIT
+
+OKCHECK:   DB      11h
+           DB      "CHECK: ", 0Dh
+OKMSG:     DB      "OK.", 0Dh
+DONEMSG:   DB      11h
+           DB      "RAM TEST COMPLETE.", 0Dh
+
+LOOP4:     LD      B,09h
+           CALL    PRNTS        ; Print space.
+           XOR     A            ; Zero A
+           SCF                  ; Set Carry
+LOOP5:     PUSH    AF           ; Store A and Flags
+           LD      (HL),A       ; Store 0 to bad location.
+           LD      A,(HL)       ; Read back
+           CALL    PRTHX        ; Print A as 2 digit hex.
+           CALL    PRNTS        ; Print space
+           POP     AF           ; Get back A (ie. 0 + C)
+           RLA                  ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB
+           DJNZ    LOOP5        ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit.
+           XOR     A            ; Zero A, clears flags.
+           LD      A,80h
+           LD      B,08h
+LOOP6:     PUSH    AF           ; Repeat above but AND memory location with original A (ie. 80) 
+           LD      C,A          ; Basically walk through all the bits to find which one is stuck.
+           LD      (HL),A
+           LD      A,(HL)
+           AND     C
+           NOP
+           JR      Z,LOOP8      ; If zero then print out the bit number
+           NOP
+           NOP
+           LD      A,C
+           CPL
+           LD      (HL),A
+           LD      A,(HL)
+           AND     C
+           JR      NZ,LOOP8     ; As above, if the compliment doesnt yield zero, print out the bit number.
+LOOP7:     POP     AF
+           RRCA
+           NOP
+           DJNZ    LOOP6
+           JP      MONIT
+
+LOOP8:     CALL    LETNL        ; New line.
+           LD      DE,BITMSG    ; BIT message
+           CALL    MSG          ; Print message in DE
+           LD      A,B
+           DEC     A
+           CALL    PRTHX        ; Print A as 2 digit hex, ie. BIT number.
+           CALL    LETNL        ; New line
+           LD      DE,BANKMSG   ; BANK message
+           CALL    MSG          ; Print message in DE
+           LD      A,H
+           CP      50h          ; 'P'
+           JR      NC,LOOP9     ; Work out bank number, 1, 2 or 3.
+           LD      A,01h
+           JR      LOOP11
+
+LOOP9:     CP      90h
+           JR      NC,LOOP10
+           LD      A,02h
+           JR      LOOP11
+
+LOOP10:    LD      A,03h
+LOOP11:    CALL    PRTHX        ; Print A as 2 digit hex, ie. BANK number.
+           JR      LOOP7
+
+BITMSG:    DB      " BIT:  ", 0Dh
+BANKMSG:   DB      " BANK: ", 0Dh
+
+TITLE:     DB      "SHARPMZ RAM TEST (C) P. SMART 2018", 0Dh, 00h
diff --git a/software/asm/sa1510.asm b/software/asm/sa1510.asm
new file mode 100644
index 0000000..51444ab
--- /dev/null
+++ b/software/asm/sa1510.asm
@@ -0,0 +1,2788 @@
+; Disassembly of the file "sa1510.rom"
+; 
+
+; Configurable parameters. These are set in the wrapper file, ie monitor_SA1510.asm
+;
+;COLW:   EQU     40                      ; Width of the display screen (ie. columns).
+;ROW:    EQU     25                      ; Number of rows on display screen.
+;SCRNSZ: EQU     COLW * ROW              ; Total size, in bytes, of the screen display area.
+
+        ORG     00000H
+MONIT:  JP      START
+GETL:   JP      ?GETL
+LETNL:  JP      ?LTNL
+NL:     JP      ?NL
+PRNTS:  JP      ?PRTS
+PRNTT:  JP      ?PRTT
+PRNT:   JP      ?PRNT
+MSG:    JP      ?MSG
+MSGX:   JP      ?MSGX                   ; RST 3
+GETKY:  JP      ?GET
+BRKEY:  JP      ?BRK
+WRINF:  JP      ?WRI
+WRDAT:  JP      ?WRD
+RDINF:  JP      ?RDI
+RDDAT:  JP      ?RDD
+VERFY:  JP      ?VRFY
+MELDY:  JP      ?MLDY
+TIMST:  JP      ?TMST
+        NOP     
+        NOP     
+        JP      1038H                   ; Interrupt routine
+TIMRD:  JP      ?TMRD
+BELL:   JP      ?BEL
+XTEMP:  JP      ?TEMP
+MSTA:   JP      MLDST
+MSTP:   JP      MLDSP
+START:  LD      SP,STACK
+        IM      1
+        CALL    ?MODE
+        LD      B,0FFH
+        LD      HL,NAME
+        CALL    ?CLER
+        LD      A,016H
+        CALL    PRNT
+        ;LD      A,0CFH                  ; Original attribute is white background in colour mode.
+        LD      A,071H                  ; MZ700 Blue background in colour mode.
+        LD      HL,ARAM
+        JR      STRT1                   
+        JP      1035H                   ; NMI routine.
+STRT1:  CALL    CLR8
+        LD      HL,TIMIN
+        LD      A,0C3H
+        LD      (1038H),A
+        LD      (01039H),HL
+        LD      A,004H
+        LD      (TEMPW),A
+        CALL    MLDSP
+        CALL    NL
+        LD      DE,00100H
+        RST     018H
+        IF      MODE80C = 0             ; For 80 char mode we need a hook to setup SPAGE mode.
+        CALL    ?BEL
+        ELSE
+        CALL    HOOK                    ; Call new routine to setup SPAGE.
+        ENDIF
+SS:     LD      A,0FFH
+SS1:    LD      (SWRK),A
+        LD      HL,0E800H
+        LD      (HL),055H
+        JR      FD2                   
+
+ST1:    CALL    NL
+        LD      A,03EH
+        CALL    PRNT
+        LD      DE,BUFER
+        CALL    GETL
+ST2:    LD      A,(DE)
+        INC     DE
+        CP      00DH
+        JR      Z,ST1                 
+        CP      'J'                    ; JUMP?
+        JR      Z,GOTO                 
+        CP      'L'                    ; LOAD?
+        JR      Z,LOAD                 
+        CP      'F'                    ; FLOPPY?
+        JR      Z,FD                 
+        CP      'B'                     ; BELL?
+        JR      Z,SG                 
+        JR      ST2                   
+
+        ; JUMP COMMAND
+GOTO:   CALL    HLHEX
+        JR      C,ST1                 
+        JP      (HL)
+
+        ; KEY SOUND ON OFF
+SG:     LD      A,(SWRK)
+        CPL     
+        JR      SS1                   
+
+        ; FLOPPY ROM CHECK AND RUN
+FD:     LD      HL,0F000H
+FD2:    LD      A,(HL)
+        OR      A
+        JR      NZ,ST1                
+        JP      (HL)
+
+?ER:    CP      002H
+        JR      Z,ST1                 
+        LD      DE,MSGE1
+        RST     018H
+        JR      ST1                   
+
+        ; LOAD COMMAND
+LOAD:   CALL    ?RDI
+        JR      C,?ER                 
+        CALL    NL
+        LD      DE,MSG?2
+        RST     018H
+        LD      DE,NAME
+        RST     018H
+        CALL    ?RDD
+        JR      C,?ER                 
+        LD      HL,(EXADR)
+        LD      A,H
+        CP      012H
+        JR      C,ST1                 
+        JP      (HL)
+
+        ; LOADING
+MSG?2:  DB      04CH, 0B7H, 0A1H, 09CH
+        DB      0A6H, 0B0H, 097H, 020H
+        DB      00DH
+
+        ; SIGN ON BANNER
+MSG?3:  DB      "**  MONITOR SA-1510  **", 0DH
+
+        ; For 80 Character mode we need some space, so shorten the Check Sum Error message.
+        ;
+        ; CHECK SUM ERROR
+MSGE1:  IF      MODE80C = 0
+        DB      043H, 098H, 092H, 09FH, 0A9H, 020H, 0A4H, 0A5H
+        DB      0B3H, 020H, 092H, 09DH, 09DH, 0B7H, 09DH, 00DH
+        ELSE
+        DB      "CK SUM?", 0DH
+        ENDIF
+
+        ; Hook = 7 bytes.
+HOOK:   IF      MODE80C = 1
+        LD      A,0FFH
+        LD      (SPAGE),A
+        JP      ?BEL                     ; Original called routine
+        ENDIF
+
+        ; CR PAGE MODE1
+.CR:    CALL    .MANG
+        RRCA    
+        JP      NC,CURS2
+        LD      L,000H
+        INC     H
+        CP      ROW - 1                 ; End of line?
+        JR      Z,.CP1                 
+        INC     H
+        JP      CURS1
+
+.CP1:   LD      (DSPXY),HL
+
+        ; SCROLLER
+.SCROL: LD      BC,SCRNSZ - COLW        ; Scroll COLW -1 lines
+        LD      DE,SCRN                 ; Start of the screen.
+        LD      HL,SCRN + COLW          ; Start of screen + 1 line.
+        LDIR    
+        EX      DE,HL
+        LD      B,COLW                  ; Clear last line at bottom of screen.
+        CALL    ?CLER
+        LD      BC,0001AH
+        LD      DE,MANG
+        LD      HL,MANG + 1
+        LDIR    
+        LD      (HL),000H
+        LD      A,(MANG)
+        OR      A
+        JP      Z,?RSTR
+        LD      HL,DSPXY + 1
+        DEC     (HL)
+        JR      .SCROL                   
+
+
+        ; CTBL PAGE MODE1
+.CTBL:  DW      .SCROL
+        DW      CURSD
+        DW      CURSU
+        DW      CURSR
+        DW      CURSL
+        DW      HOM0
+        DW      CLRS
+        DW      DEL
+        DW      INST
+        DW      ALPHA
+        DW      KANA
+        DW      ?RSTR
+        DW      REV
+        DW      .CR
+        DW      ?RSTR
+        DW      ?RSTR
+
+?MLDY:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      A,002H
+        LD      (OCTV),A
+        LD      B,001H
+MLD1:   LD      A,(DE)
+        CP      00DH
+        JR      Z,MLD4                 
+        CP      0C8H
+        JR      Z,MLD4                 
+        CP      0CFH
+        JR      Z,MLD2                 
+        CP      02DH
+        JR      Z,MLD2                 
+        CP      02BH
+        JR      Z,MLD3                 
+        CP      0D7H
+        JR      Z,MLD3                 
+        CP      023H
+        LD      HL,MTBL
+        JR      NZ,MLD1A                
+        LD      HL,M?TBL
+        INC     DE
+MLD1A:  CALL    ONPU
+        JR      C,MLD1                 
+        CALL    RYTHM
+        JR      C,MLD5                 
+        CALL    MLDST
+        LD      B,C
+        JR      MLD1                   
+MLD2:   LD      A,003H
+MLD2A:  LD      (OCTV),A
+        INC     DE
+        JR      MLD1                   
+MLD3:   LD      A,001H
+        JR      MLD2A                   
+MLD4:   CALL    RYTHM
+MLD5:   PUSH    AF
+        CALL    MLDSP
+        POP     AF
+        JP      RET3
+
+ONPU:   PUSH    BC
+        LD      B,008H
+        LD      A,(DE)
+ONP1A:  CP      (HL)
+        JR      Z,ONP2                 
+        INC     HL
+        INC     HL
+        INC     HL
+        DJNZ    ONP1A                   
+        SCF     
+        INC     DE
+        POP     BC
+        RET     
+
+ONP2:   INC     HL
+        PUSH    DE
+        LD      E,(HL)
+        INC     HL
+        LD      D,(HL)
+        EX      DE,HL
+        LD      A,H
+        OR      A
+        JR      Z,ONP2B                 
+        LD      A,(OCTV)
+ONP2A:  DEC     A
+        JR      Z,ONP2B                 
+        ADD     HL,HL
+        JR      ONP2A                   
+ONP2B:  LD      (RATIO),HL
+        LD      HL,OCTV
+        LD      (HL),002H
+        DEC     HL
+        POP     DE
+        INC     DE
+        LD      A,(DE)
+        LD      B,A
+        AND     0F0H
+        CP      030H
+        JR      Z,ONP2C                 
+        LD      A,(HL)
+        JR      ONP2D                   
+ONP2C:  INC     DE
+        LD      A,B
+        AND     00FH
+        LD      (HL),A
+ONP2D:  LD      HL,OPTBL
+        ADD     A,L
+        LD      L,A
+        LD      C,(HL)
+        LD      A,(TEMPW)
+        LD      B,A
+        XOR     A
+        JP      L09AB
+
+MTBL:   DB      043H
+        DB      077H
+        DB      007H
+        DB      044H
+        DB      0A7H
+        DB      006H
+        DB      045H
+        DB      0EDH
+        DB      005H
+        DB      046H
+        DB      098H
+        DB      005H
+        DB      047H
+        DB      0FCH
+        DB      004H
+        DB      041H
+        DB      071H
+        DB      004H
+        DB      042H
+        DB      0F5H
+        DB      003H
+        DB      052H
+        DB      000H
+        DB      000H
+M?TBL:  DB      043H
+        DB      00CH
+        DB      007H
+        DB      044H
+        DB      047H
+        DB      006H
+        DB      045H
+        DB      098H
+        DB      005H
+        DB      046H
+        DB      048H
+        DB      005H
+        DB      047H
+        DB      0B4H
+        DB      004H
+        DB      041H
+        DB      031H
+        DB      004H
+        DB      042H
+        DB      0BBH
+        DB      003H
+        DB      052H
+        DB      000H
+        DB      000H
+
+OPTBL:  DB      001H
+        DB      002H
+        DB      003H
+        DB      004H
+        DB      006H
+        DB      008H
+        DB      00CH
+        DB      010H
+        DB      018H
+        DB      020H
+
+?SAVE:  LD      HL,FLSDT
+        LD      (HL),0EFH
+        LD      A,(KANAF)
+        OR      A
+        JR      Z,L0270                 
+        LD      (HL),0FFH
+L0270:  LD      A,(HL)
+        PUSH    AF
+        CALL    ?PONT
+        LD      A,(HL)
+        LD      (FLASH),A
+        POP     AF
+        LD      (HL),A
+        XOR     A
+        LD      HL,KEYPA
+        LD      (HL),A
+        CPL     
+        LD      (HL),A
+        RET     
+
+MGP.I:  PUSH    AF
+        PUSH    HL
+        LD      HL,MGPNT
+        LD      A,(HL)
+        INC     A
+        CP      033H
+        JR      NZ,L028F                
+        XOR     A
+L028F:  PUSH    HL
+        LD      L,A
+        LD      A,(SPAGE)
+        OR      A
+        LD      A,L
+        POP     HL
+        JR      NZ,L029A                
+        LD      (HL),A
+L029A:  POP     HL
+        POP     AF
+        RET     
+
+MGP.D:  PUSH    AF
+        PUSH    HL
+        LD      HL,MGPNT
+        LD      A,(HL)
+        DEC     A
+        JP      P,L028F
+        LD      A,032H
+        JR      L028F                   
+MLDST:  LD      HL,(RATIO)
+        LD      A,H
+        OR      A
+        JR      Z,MLDSP                 
+        PUSH    DE
+        EX      DE,HL
+        LD      HL,CONT0
+        LD      (HL),E
+        LD      (HL),D
+        LD      A,001H
+        POP     DE
+        JR      L02C4                   
+MLDSP:  LD      A,034H
+        LD      (CONTF),A
+        XOR     A
+L02C4:  LD      (SUNDG),A
+        RET     
+
+RYTHM:  LD      HL,KEYPA
+        LD      (HL),0F0H
+        INC     HL
+        LD      A,(HL)
+        AND     081H
+        JR      NZ,L02D5                
+        SCF     
+        RET     
+
+L02D5:  LD      A,(SUNDG)
+        RRCA    
+        JR      C,L02D5                 
+L02DB:  LD      A,(SUNDG)
+        RRCA    
+        JR      NC,L02DB                
+        DJNZ    L02D5                   
+        XOR     A
+        RET     
+
+?BEL:   PUSH    DE
+        LD      DE,00DB1H
+        RST     030H
+        POP     DE
+        RET     
+
+?TEMP:  PUSH    AF
+        PUSH    BC
+        AND     00FH
+        LD      B,A
+        LD      A,008H
+        SUB     B
+        LD      (TEMPW),A
+        POP     BC
+        POP     AF
+        RET     
+
+?TMST:  DI      
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      (AMPM),A
+        LD      A,0F0H
+        LD      (TIMFG),A
+        LD      HL,0A8C0H
+        XOR     A
+        SBC     HL,DE
+        PUSH    HL
+        INC     HL
+        EX      DE,HL
+        LD      HL,CONTF
+        LD      (HL),074H
+        LD      (HL),0B0H
+        DEC     HL
+        LD      (HL),E
+        LD      (HL),D
+        DEC     HL
+        LD      (HL),00AH
+        LD      (HL),000H
+        INC     HL
+        INC     HL
+        LD      (HL),080H
+        DEC     HL
+L0323:  LD      C,(HL)
+        LD      A,(HL)
+        CP      D
+        JR      NZ,L0323                
+        LD      A,C
+        CP      E
+        JR      NZ,L0323                
+        DEC     HL
+        NOP     
+        NOP     
+        NOP     
+        LD      (HL),00CH
+        LD      (HL),07BH
+        INC     HL
+        POP     DE
+L0336:  LD      C,(HL)
+        LD      A,(HL)
+        CP      D
+        JR      NZ,L0336                
+        LD      A,C
+        CP      E
+        JR      NZ,L0336                
+        POP     HL
+        POP     DE
+        POP     BC
+        EI      
+        RET     
+
+?TMRD:  PUSH    HL
+        LD      HL,CONTF
+        LD      (HL),080H
+        DEC     HL
+        DI      
+        LD      E,(HL)
+        LD      D,(HL)
+        EI      
+        LD      A,E
+        OR      D
+        JR      Z,?TMR1                 
+        XOR     A
+        LD      HL,0A8C0H
+        SBC     HL,DE
+        JR      C,?TMR2                 
+        EX      DE,HL
+        LD      A,(AMPM)
+        POP     HL
+        RET     
+
+?TMR1:  LD      DE,0A8C0H
+?TMR1A: LD      A,(AMPM)
+        XOR     001H
+        POP     HL
+        RET     
+
+?TMR2:  DI      
+        LD      HL,CONT2
+        LD      A,(HL)
+        CPL     
+        LD      E,A
+        LD      A,(HL)
+        CPL     
+        LD      D,A
+        EI      
+        INC     DE
+        JR      ?TMR1A                   
+
+TIMIN:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,AMPM
+        LD      A,(HL)
+        XOR     001H
+        LD      (HL),A
+        LD      HL,CONTF
+        LD      (HL),080H
+        DEC     HL
+        PUSH    HL
+        LD      E,(HL)
+        LD      D,(HL)
+        LD      HL,0A8C0H
+        ADD     HL,DE
+        DEC     HL
+        DEC     HL
+        EX      DE,HL
+        POP     HL
+        LD      (HL),E
+        LD      (HL),D
+        POP     HL
+        POP     DE
+        POP     BC
+        POP     AF
+        EI      
+        RET     
+
+.DSP03:  EX      DE,HL
+        LD      (HL),001H
+        INC     HL
+        LD      (HL),000H
+        JP      CURSR
+.MANG2: LD      A,(DSPXY + 1)
+        ADD     A,L
+        LD      L,A
+        LD      A,(HL)
+        INC     HL
+        RL      (HL)
+        OR      (HL)
+        RR      (HL)
+        RRCA    
+        EX      DE,HL
+        LD      HL,(DSPXY)
+        RET     
+
+PRTHL:  LD      C,H
+        POP     AF
+        LD      A,H
+        CALL    PRTHX
+        LD      A,L
+        JR      PRTHX                   
+        LD      B,E
+        LD      B,E
+PRTHX:  PUSH    AF
+        RRCA    
+        RRCA    
+        RRCA    
+        RRCA    
+        CALL    ASC
+        CALL    PRNT
+        POP     AF
+        CALL    ASC
+        JP      PRNT
+L03D5:  POP     DE
+        POP     HL
+        POP     BC
+        POP     AF
+        RET     
+
+ASC:    AND     00FH
+        CP      00AH
+        JR      C,NOADD                 
+        ADD     A,007H
+NOADD:  ADD     A,030H
+        RET     
+
+HEXJ:   CP      030H
+        RET     C
+        CP      03AH
+        JR      C,HEX1                 
+        SUB     007H
+        CP      040H
+        JR      NC,HEX2                
+HEX1:   AND     00FH
+        RET     
+HEX2:   SCF     
+        RET     
+
+        ; Unused memory.
+        LD      C,B
+        LD      C,H
+
+HEX:    JR      HEXJ                   
+
+HOME:   LD      HL,(DSPXY)
+        LD      A,(MGPNT)
+        SUB     H
+        JR      NC,HOM1                
+        ADD     A,032H
+HOM1:   LD      (MGPNT),A
+HOM0:   LD      HL,00000H
+        JP      CURS3
+
+        ; Unused memory.
+        INC     L
+
+HLHEX:  PUSH    DE
+        CALL    L041F
+        JR      C,L041D                 
+        LD      H,A
+        CALL    L041F
+        JR      C,L041D                 
+        LD      L,A
+L041D:  POP     DE
+        RET     
+
+L041F:  PUSH    BC
+        LD      A,(DE)
+        INC     DE
+        CALL    HEX
+        JR      C,L0434                 
+        RRCA    
+        RRCA    
+        RRCA    
+        RRCA    
+        LD      C,A
+        LD      A,(DE)
+        INC     DE
+        CALL    HEX
+        JR      C,L0434                 
+        OR      C
+L0434:  POP     BC
+        RET     
+
+?WRI:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D7H
+        LD      E,0CCH
+        LD      HL,STACK
+        LD      BC,00080H
+L0444:  CALL    L071A
+        CALL    MOTOR
+        JR      C,L0464                 
+        LD      A,E
+        CP      0CCH
+        JR      NZ,L045E                
+        CALL    NL
+        PUSH    DE
+        LD      DE,MSG?7                ; Writing Message
+        RST     018H
+        LD      DE,NAME
+        RST     018H
+        POP     DE
+L045E:  CALL    L077A
+        CALL    L0485
+L0464:  JP      L0552
+
+        ; Writing
+MSG?7:  DB      057H, 09DH, 0A6H, 096H, 0A6H
+        DB      0B0H, 097H, 020H, 00DH
+
+?WRD:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D7H
+        LD      E,053H
+        LD      BC,(SIZE)
+        LD      HL,(DTADR)
+        LD      A,B
+        OR      C
+        JR      Z,L04CB                 
+        JR      L0444                   
+L0485:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,002H
+        LD      A,0F0H
+        LD      (KEYPA),A
+L048F:  LD      A,(HL)
+        CALL    L0767
+        LD      A,(KEYPB)
+        AND     081H
+        JP      NZ,L049E
+        SCF     
+        JR      L04CB                   
+L049E:  INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JP      NZ,L048F
+        LD      HL,(SUMDT)
+        LD      A,H
+        CALL    L0767
+        LD      A,L
+        CALL    L0767
+        CALL    L0D57
+        DEC     D
+        JP      NZ,L04BB
+        OR      A
+        JP      L04CB
+L04BB:  LD      B,000H
+L04BD:  CALL    L0D3E
+        DEC     B
+        JP      NZ,L04BD
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+        JP      L048F
+L04CB:  POP     HL
+        POP     BC
+        POP     DE
+        RET     
+
+?RDI:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D2H
+        LD      E,0CCH
+        LD      BC,00080H
+        LD      HL,STACK
+L04DD:  CALL    MOTOR
+        JP      C,L0570
+        CALL    TMARK
+        JP      C,L0570
+        CALL    L0505
+        JP      L0552
+
+?RDD:   DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      D,0D2H
+        LD      E,053H
+        LD      BC,(SIZE)
+        LD      HL,(DTADR)
+        LD      A,B
+        OR      C
+        JP      Z,L0552
+        JR      L04DD                   
+L0505:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      H,002H
+L050A:  LD      BC,KEYPB
+        LD      DE,KEYPC
+L0510:  CALL    EDGE
+        JP      C,L0570
+        CALL    DLY3
+        LD      A,(DE)
+        AND     020H
+        JP      Z,L0510
+        LD      D,H
+        LD      HL,00000H
+        LD      (SUMDT),HL
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+L052A:  CALL    RBYTE
+        JP      C,L0570
+        LD      (HL),A
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JP      NZ,L052A
+        LD      HL,(SUMDT)
+        CALL    RBYTE
+        JP      C,L0570
+        LD      E,A
+        CALL    RBYTE
+        JP      C,L0570
+        CP      L
+        JP      NZ,L0563
+        LD      A,E
+        CP      H
+        JP      NZ,L0563
+L0551:  XOR     A
+L0552:  POP     HL
+        POP     BC
+        POP     DE
+        CALL    MSTOP
+        PUSH    AF
+        LD      A,(TIMFG)
+        CP      0F0H
+        JR      NZ,L0561                
+        EI      
+L0561:  POP     AF
+        RET     
+
+L0563:  DEC     D
+        JR      Z,L056C                 
+        LD      H,D
+        CALL    GAPCK
+        JR      L050A                   
+L056C:  LD      A,001H
+        JR      L0572                   
+L0570:  LD      A,002H
+L0572:  SCF     
+        JR      L0552                   
+
+
+?VRFY:  DI      
+        PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      BC,(SIZE)
+        LD      HL,(DTADR)
+        LD      D,0D2H
+        LD      E,053H
+        LD      A,B
+        OR      C
+        JR      Z,L0552                 
+        CALL    L071A
+        CALL    MOTOR
+        JR      C,L0570                 
+        CALL    TMARK
+        JP      C,L0570
+        CALL    TVRFY
+        JR      L0552                   
+
+TVRFY:  PUSH    DE
+        PUSH    BC
+        PUSH    HL
+        LD      H,002H
+TVF1:   LD      BC,KEYPB
+        LD      DE,KEYPC
+TVF2:   CALL    EDGE
+        JP      C,L0570
+        CALL    DLY3
+        LD      A,(DE)
+        AND     020H
+        JP      Z,TVF2
+        LD      D,H
+        POP     HL
+        POP     BC
+        PUSH    BC
+        PUSH    HL
+TVF3:   CALL    RBYTE
+        JP      C,L0570
+        CP      (HL)
+        JP      NZ,L056C
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JP      NZ,TVF3
+        LD      HL,(CSMDT)
+        CALL    RBYTE
+        CP      H
+        JR      NZ,L056C                
+        CALL    RBYTE
+        CP      L
+        JR      NZ,L056C                
+        DEC     D
+        JP      Z,L0551
+        LD      H,D
+        JR      TVF1                   
+
+        ; PRINT '00'
+GETLD:  LD      DE,009FCH
+        RST     018H
+        JP      AUTO2
+
+        ; ROLL UP
+ROLUP:  LD      HL,PBIAS
+        LD      A,(ROLEND)
+        CP      (HL)
+        JP      Z,?RSTR
+        JP      ROLU1
+
+?LOAD:  PUSH    AF
+        LD      A,(FLASH)
+        CALL    ?PONT
+        LD      (HL),A
+        POP     AF
+        RET     
+
+        ; Unused memory
+        XOR     E
+        LD      C,A
+
+EDGE:   LD      A,0F0H
+        LD      (KEYPA),A
+        NOP     
+EDG1:   LD      A,(BC)
+        AND     081H
+        JP      NZ,EDG1A
+        SCF     
+        RET     
+EDG1A:  LD      A,(DE)
+        AND     020H
+        JP      NZ,EDG1
+EDG2:   LD      A,(BC)
+        AND     081H
+        JP      NZ,EDG3
+        SCF     
+        RET     
+EDG3:   LD      A,(DE)
+        AND     020H
+        JP      Z,EDG2
+        RET     
+
+RBYTE:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,00800H
+        LD      BC,KEYPB
+        LD      DE,KEYPC
+RBY1:   CALL    EDGE
+        JP      C,RBY3
+        CALL    DLY3
+        LD      A,(DE)
+        AND     020H
+        JP      Z,RBY2
+        PUSH    HL
+        LD      HL,(SUMDT)
+        INC     HL
+        LD      (SUMDT),HL
+        POP     HL
+        SCF     
+RBY2:   LD      A,L
+        RLA     
+        LD      L,A
+        DEC     H
+        JP      NZ,RBY1
+        CALL    EDGE
+        LD      A,L
+RBY3:   POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+TMARK:  CALL    GAPCK
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      HL,02828H              ; 40 short and 40 long gap pulses
+        LD      A,E
+        CP      0CCH
+        JP      Z,TM0
+        LD      HL,01414H              ; 20 short and 20 long tape mark pulses
+TM0:    LD      (TMCNT),HL
+        LD      BC,KEYPB
+        LD      DE,KEYPC
+TM1:    LD      HL,(TMCNT)
+TM2:    CALL    EDGE
+        JP      C,RET3
+        CALL    DLY3
+        LD      A,(DE)
+        AND     020H
+        JP      Z,TM1
+        DEC     H
+        JP      NZ,TM2
+TM3:    CALL    EDGE
+        JP      C,RET3
+        CALL    DLY3
+        LD      A,(DE)
+        AND     020H
+        JP      NZ,TM1
+        DEC     L
+        JP      NZ,TM3
+        CALL    EDGE
+RET3:
+TM4:    POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+MOTOR:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      B,00AH
+MOT1:   LD      A,(KEYPC)
+        AND     010H
+        JR      Z,MOT4                 
+MOT2:   LD      B,0A6H
+L06B1:  CALL    DLY12
+        DJNZ    L06B1                   
+        XOR     A
+MOT7:   JR      RET3                   
+MOT4:   LD      A,006H
+        LD      HL,KEYPF
+        LD      (HL),A
+        INC     A
+        LD      (HL),A
+        DJNZ    MOT1                   
+        CALL    NL
+        LD      A,D
+        CP      0D7H
+        JR      Z,MOT8                 
+        LD      DE,00D9EH
+        JR      MOT9                   
+MOT8:   LD      DE,MSG_3                ; RECORD message.
+        RST     018H
+        LD      DE,00DA0H
+MOT9:   RST     018H
+MOT5:   LD      A,(KEYPC)
+        AND     010H
+        JR      NZ,MOT2                
+        CALL    ?BRK
+        JR      NZ,MOT5                
+        SCF     
+        JR      MOT7                   
+
+L06E7:  LD      B,0C9H
+        LD      A,(KANAF)
+        OR      A
+        JR      NZ,L06F0                
+        INC     B
+L06F0:  LD      A,B
+        JP      ?KY1
+
+        ; PRESS RECORD message.
+MSG_3:  DB      07FH, 020H
+        DB      052H, 045H, 043H, 04FH, 052H
+        DB      044H, 02EH, 00DH
+
+        ; Padding not used
+        DB      034H
+        DB      044H
+
+MSTOP:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        LD      B,00AH
+L0705:  LD      A,(KEYPC)
+        AND     010H
+        JR      Z,L0717                 
+        LD      A,006H
+        LD      (KEYPF),A
+        INC     A
+        LD      (KEYPF),A
+        DJNZ    L0705                   
+L0717:  JP      ?RSTR1
+L071A:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      DE,00000H
+L0720:  LD      A,B
+        OR      C
+        JR      NZ,L072F                
+        EX      DE,HL
+        LD      (SUMDT),HL
+        LD      (CSMDT),HL
+        POP     HL
+        POP     DE
+        POP     BC
+        RET     
+
+L072F:  LD      A,(HL)
+        PUSH    BC
+        LD      B,008H
+L0733:  RLCA    
+        JR      NC,L0737                
+        INC     DE
+L0737:  DJNZ    L0733                   
+        POP     BC
+        INC     HL
+        DEC     BC
+        JR      L0720                   
+L073E:  RLCA    
+        RLCA    
+        RLCA    
+        LD      C,A
+        LD      A,E
+L0743:  DEC     H
+        RRCA    
+        JR      NC,L0743                
+        LD      A,H
+        ADD     A,C
+        LD      C,A
+        JP      SWEP01
+?MODE:  LD      HL,KEYPF
+        LD      (HL),08AH
+        LD      (HL),007H
+        LD      (HL),005H
+        LD      (HL),001H
+        RET     
+
+L0759:  LD      A,00EH
+L075B:  DEC     A
+        JP      NZ,L075B
+        RET     
+
+L0760:  LD      A,00DH
+L0762:  DEC     A
+        JP      NZ,L0762
+        RET     
+
+L0767:  PUSH    BC
+        LD      B,008H
+        CALL    L0D57
+L076D:  RLCA    
+        CALL    C,L0D57
+        CALL    NC,L0D3E
+        DEC     B
+        JP      NZ,L076D
+        POP     BC
+        RET     
+
+L077A:  PUSH    BC
+        PUSH    DE
+        LD      A,E
+        LD      BC,055F0H
+        LD      DE,02828H
+        CP      0CCH
+        JP      Z,L078E
+        LD      BC,02AF8H
+        LD      DE,01414H
+L078E:  CALL    L0D3E
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,L078E                
+L0796:  CALL    L0D57
+        DEC     D
+        JR      NZ,L0796                
+L079C:  CALL    L0D3E
+        DEC     E
+        JR      NZ,L079C                
+        CALL    L0D57
+        POP     DE
+        POP     BC
+        RET     
+
+?GETL:  PUSH    AF
+        PUSH    BC
+        PUSH    HL
+        PUSH    DE
+GETL0:  CALL    ?SAVE
+GETL0A: CALL    ?KEY
+        CP      0CBH
+        JR      Z,GETL0A                 
+GETL0B: CALL    ?KEY
+        CALL    ?FLAS
+        JR      Z,GETL0B                 
+GETL0C: PUSH    AF
+        XOR     A
+        LD      (STRGF),A
+        POP     AF
+AUTO3:  LD      B,A
+GETL0D: CALL    ?LOAD
+        LD      A,(SWRK)
+        OR      A
+        CALL    Z,?BEL
+        LD      A,B
+        CP      0E7H
+        JP      Z,GETLD
+        CP      0E6H
+        JR      Z,CHGPK                 
+        CP      0EEH
+        JR      Z,CHGPA                 
+        CP      0E5H
+        JR      Z,DMT                 
+        CP      0E0H
+        JP      Z,LOCK
+        JR      NC,GETL0B                
+        AND     0F0H
+        CP      0C0H
+        JR      NZ,GETL2                
+        LD      A,B
+        CP      0CDH
+        JR      Z,GETL3                 
+        CP      0CBH
+        JP      Z,GETLC
+        CP      0C7H
+        JR      NC,GETL5                
+        LD      A,(KANAF)
+        OR      A
+        LD      A,B
+        JR      Z,GETL5                 
+GETL2:  LD      A,B
+        CALL    ?DSP
+AUTO2:  CALL    ?SAVE
+        LD      A,(STRGF)
+        OR      A
+        JR      NZ,AUTO5                
+AUTOL:  LD      E,014H
+AUTOL1: CALL    ?KEY
+        JR      NZ,AUTO3                
+        CALL    AUTCK
+GETL1:  JR      C,GETL0B                 
+        DEC     E
+        JR      NZ,AUTOL1                
+        LD      A,001H
+        LD      (STRGF),A
+AUTO5:  CALL    DLY12
+        CALL    DLY12
+        CALL    ?KEY
+        CALL    ?FLAS
+        JR      NZ,GETL0C                
+        CALL    AUTCK
+        JR      C,GETL1                 
+        JR      GETL0D                   
+GETL5:  CALL    ?DPCT
+        JR      AUTO2                   
+
+CHGPA:  XOR     A
+        IF      MODE80C = 1
+        JR      CHGPK
+        ELSE
+        JR      CHGPK1                   
+        ENDIF
+CHGPK:  LD      A,0FFH
+CHGPK1: LD      (SPAGE),A
+        LD      A,0C6H
+        CALL    ?DPCT
+CHGP1:  JP      GETL0
+
+GETLC:  POP     HL
+        PUSH    HL
+        LD      (HL),01BH
+        INC     HL
+        LD      (HL),00DH
+        JR      GETLR                   
+
+DMT:    LD      B,05AH
+        JR      GETL2                   
+
+GETL3:  CALL    .MANG
+        LD      B,COLW     ; PDS was 028H
+        JR      NC,GETLA                
+        DEC     H
+GETLB:  LD      B,COLW*2   ; 050H
+GETL6:  LD      L,000H
+        CALL    ?PNT1
+        POP     DE
+        PUSH    DE
+GETL6A: LD      A,(HL)
+        CALL    ?DACN
+        LD      (DE),A
+        INC     HL
+        RES     3,H
+        INC     DE
+        DJNZ    GETL6A                   
+        EX      DE,HL
+GETL6B: LD      (HL),00DH
+        DEC     HL
+        LD      A,(HL)
+        CP      020H
+        JR      Z,GETL6B                 
+GETLR:  CALL    ?LTNL
+        JP      L03D5
+
+GETLA:  RRCA    
+        JR      NC,GETL6                
+        JR      GETLB                   
+
+LOCK:   LD      HL,SFTLK
+        LD      A,(HL)
+        CPL     
+        LD      (HL),A
+        JR      CHGP1                   
+
+?MSG:   PUSH    AF
+        PUSH    BC
+        PUSH    DE
+MSG1:   LD      A,(DE)
+        CP      00DH
+        JR      Z,MSGX2                 
+        CALL    ?PRNT
+        INC     DE
+        JR      MSG1                   
+
+?MSGX:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+MSGX1:  LD      A,(DE)
+        CP      00DH
+MSGX2:  JP      Z,?RSTR1
+        CALL    ?ADCN
+        CALL    PRNT3
+        INC     DE
+        JR      MSGX1                   
+
+?GET:   PUSH    BC
+        PUSH    HL
+        LD      B,009H
+        LD      HL,01165H
+        CALL    ?CLRFF
+        POP     HL
+        POP     BC
+        CALL    ?KEY
+        SUB     0F0H
+        RET     Z
+        ADD     A,0F0H
+        JP      ?DACN
+
+?KEY:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        CALL    ?SWEP
+        LD      A,B
+        RLCA    
+        JR      C,?KY2                 
+        LD      A,0F0H
+?KY1:  LD      E,A
+        CALL    AUTCK
+        LD      A,(KDATW)
+        OR      A
+        JR      Z,?KY11                 
+        CALL    DLY12
+        CALL    ?SWEP
+        LD      A,B
+        RLCA    
+        JR      C,?KY2                 
+?KY11:  LD      A,E
+        CP      0F0H
+        JR      NZ,?KY9                
+?KY10:  JP      RET3
+?KY2:   RLCA    
+        RLCA    
+        RLCA    
+        JP      C,L06E7
+        RLCA    
+        JP      C,_BRK
+        LD      H,000H
+        LD      L,C
+        LD      A,C
+        CP      038H
+        JR      NC,?KY6                
+        LD      A,(KANAF)
+        OR      A
+        LD      A,B
+        RLCA    
+        JR      NZ,?KY4                
+        LD      B,A
+        LD      A,(SFTLK)
+        OR      A
+        LD      A,B
+        JR      Z,L0917                 
+        RLA     
+        CCF     
+        RRA     
+L0917:  RLA     
+        RLA     
+        JR      NC,?KY3                
+L091B:  LD      DE,KTBLC
+?KY5:   ADD     HL,DE
+        LD      A,(HL)
+        JR      ?KY1                   
+?KY3:   RRA     
+        JR      NC,?KY6                
+        LD      DE,KTBLS
+        JR      ?KY5                   
+?KY6:   LD      DE,KTBL ; 00BEAH
+        JR      ?KY5                   
+?KY4:   RLCA    
+        JR      C,?KY7                 
+        RLCA    
+        JR      C,L091B                 
+        LD      DE,KTBLG
+        JR      ?KY5                   
+?KY7:   LD      DE,KTBLGS
+        JR      ?KY5                   
+?KY9:   CALL    AUTCK
+        INC     A
+        LD      A,E
+        JR      ?KY10                   
+
+?PRT:   LD      A,C
+        CALL    ?ADCN
+        LD      C,A
+        AND     0F0H
+        CP      0F0H
+        RET     Z
+
+        CP      0C0H
+        LD      A,C
+        JR      NZ,PRNT3                
+PRNT5:  CALL    ?DPCT
+        CP      0C3H
+        JR      Z,PRNT4                 
+        CP      0C5H
+        JR      Z,PRNT2                 
+        CP      0CDH                   ; CR
+        JR      Z,PRNT2                 
+        CP      0C6H
+        RET     NZ
+
+PRNT2:  XOR     A
+PRNT2A: LD      (DPRNT),A
+        RET     
+
+PRNT3:  CALL    ?DSP
+PRNT4:  LD      A,(DPRNT)
+        INC     A
+        CP      COLW*2                 ; 050H
+        JR      C,PRNT4A                 
+        SUB     COLW*2                 ; 050H
+PRNT4A: JR      PRNT2A                   
+
+?NL:    LD      A,(DPRNT)
+        OR      A
+        RET     Z
+
+?LTNL:  LD      A,0CDH
+        JR      PRNT5                   
+?PRTT:  CALL    PRNTS
+        LD      A,(DPRNT)
+        OR      A
+        RET     Z
+
+L098C:  SUB     00AH
+        JR      C,?PRTT                 
+        JR      NZ,L098C                
+        RET     
+
+?PRTS:  LD      A,020H
+?PRNT:  CP      00DH
+        JR      Z,?LTNL                 
+        PUSH    BC
+        LD      C,A
+        LD      B,A
+        CALL    ?PRT
+        LD      A,B
+        POP     BC
+        RET     
+
+DLY3:  NEG     
+        NEG     
+        LD      A,02AH
+        JP      L0762
+L09AB:  ADD     A,C
+        DJNZ    L09AB                   
+        POP     BC
+        LD      C,A
+        XOR     A
+        RET     
+
+        DJNZ    PRNT4A                   
+        PUSH    DE
+        PUSH    HL
+        CALL    ?SAVE
+L09B9:  CALL    ?KEY
+        CALL    ?FLAS
+        JR      Z,L09B9                 
+        CALL    ?LOAD
+        JP      RET3
+L09C7:  PUSH    DE
+        PUSH    HL
+        LD      HL,PBIAS
+        XOR     A
+        RLD     
+        LD      D,A
+        LD      E,(HL)
+        RRD     
+        XOR     A
+        RR      D
+        RR      E
+        LD      HL,SCRN
+        ADD     HL,DE
+        LD      (PAGETP),HL
+        POP     HL
+        POP     DE
+        RET     
+
+L09E2:  XOR     A
+CLR8:   LD      BC,00800H
+        PUSH    DE
+        LD      D,A
+L09E8:  LD      (HL),D
+        INC     HL
+        DEC     BC
+        LD      A,B
+        OR      C
+        JR      NZ,L09E8                
+        POP     DE
+        RET     
+
+AUTCK:  LD      HL,KDATW
+        LD      A,(HL)
+        INC     HL
+        LD      D,(HL)
+        LD      (HL),A
+        SUB     D
+        RET     NC
+        INC     (HL)
+        RET     
+
+        DB      030H
+        DB      030H
+        DB      00DH
+
+?FLAS:  PUSH    AF
+        PUSH    HL
+        LD      A,(KEYPC)
+        RLCA    
+        RLCA    
+        JR      C,FLAS1                 
+        LD      A,(FLSDT)
+FLAS2:  CALL    ?PONT
+        LD      (HL),A
+FLAS3:  POP     HL
+        POP     AF
+        RET     
+
+FLAS1:  LD      A,(FLASH)
+        JR      FLAS2                   
+
+REV:    LD      HL,REVFLG
+        LD      A,(HL)
+        OR      A
+        CPL     
+        LD      (HL),A
+        JR      Z,REV1                 
+        LD      A,(INVDSP)
+        JR      REV2                   
+REV1:   LD      A,(NRMDSP)
+REV2:   JP      ?RSTR
+
+.MANG:  LD      HL,MANG
+        LD      A,(SPAGE)
+        OR      A
+        JP      NZ,.MANG2
+        LD      A,(MGPNT)
+.MANG3: SUB     008H
+        INC     HL
+        JR      NC,.MANG3                
+        ADD     A,008H
+        LD      C,(HL)
+        DEC     HL
+        LD      B,A
+        INC     B
+        PUSH    BC
+        LD      A,(HL)
+.MANG4: RR      C
+        RRA     
+        DJNZ    .MANG4                   
+        POP     BC
+        EX      DE,HL
+.MANG1: LD      HL,(DSPXY)
+        RET     
+
+?SWEP:  PUSH    DE
+        PUSH    HL
+        XOR     A
+        LD      (KDATW),A
+        LD      B,0FAH
+        LD      D,A
+        CALL    ?BRK
+        JR      NZ,SWEP6                
+        LD      D,088H
+        JR      SWEP9                   
+SWEP6:  LD      HL,SWPW
+        PUSH    HL
+        JR      NC,SWEP11                
+        LD      D,A
+        AND     060H
+        JR      NZ,SWEP11                
+        LD      A,D
+        XOR     (HL)
+        BIT     4,A
+        LD      (HL),D
+        JR      Z,SWEP0                 
+SWEP01: SET     7,D
+SWEP0:  DEC     B
+        POP     HL
+        INC     HL
+        LD      A,B
+        LD      (KEYPA),A
+        CP      0F0H
+        JR      NZ,SWEP3                
+        LD      A,(HL)
+        CP      003H
+        JR      C,SWEP9                 
+        LD      (HL),000H
+        RES     7,D
+SWEP9:  LD      B,D
+        POP     HL
+        POP     DE
+        RET     
+
+SWEP11: LD      (HL),000H
+        JR      SWEP0                   
+SWEP3:  LD      A,(KEYPB)
+        LD      E,A
+        CPL     
+        AND     (HL)
+        LD      (HL),E
+        PUSH    HL
+        LD      HL,KDATW
+        PUSH    BC
+        LD      B,008H
+SWEP8:  RLC     E
+        JR      C,SWEP7                 
+        INC     (HL)
+SWEP7:  DJNZ    SWEP8                   
+        POP     BC
+        OR      A
+        JR      Z,SWEP0                 
+        LD      E,A
+SWEP2:  LD      H,008H
+        LD      A,B
+        DEC     A
+        AND     00FH
+        JP      L073E
+
+; ASCII TO DISPLAY CODE TABLE
+ATBL:   DB      0CCH
+        DB      0E0H
+        DB      0F2H
+        DB      0F3H
+        DB      0CEH
+        DB      0CFH
+        DB      0F6H
+        DB      0F7H
+        DB      0F8H
+        DB      0F9H
+        DB      0FAH
+        DB      0FBH
+        DB      0FCH
+        DB      0FDH
+        DB      0FEH
+        DB      0FFH
+        DB      0E1H
+        DB      0C1H
+        DB      0C2H
+        DB      0C3H
+        DB      0C4H
+        DB      0C5H
+        DB      0C6H
+        DB      0E2H
+        DB      0E3H
+        DB      0E4H
+        DB      0E5H
+        DB      0E6H
+        DB      0EBH
+        DB      0EEH
+        DB      0EFH
+        DB      0F4H
+        DB      000H
+        DB      061H
+        DB      062H
+        DB      063H
+        DB      064H
+        DB      065H
+        DB      066H
+        DB      067H
+        DB      068H
+        DB      069H
+        DB      06BH
+        DB      06AH
+        DB      02FH
+        DB      02AH
+        DB      02EH
+        DB      02DH
+        DB      020H
+        DB      021H
+        DB      022H
+        DB      023H
+        DB      024H
+        DB      025H
+        DB      026H
+        DB      027H
+        DB      028H
+        DB      029H
+        DB      04FH
+        DB      02CH
+        DB      051H
+        DB      02BH
+        DB      057H
+        DB      049H
+        DB      055H
+        DB      001H
+        DB      002H
+        DB      003H
+        DB      004H
+        DB      005H
+        DB      006H
+        DB      007H
+        DB      008H
+        DB      009H
+        DB      00AH
+        DB      00BH
+        DB      00CH
+        DB      00DH
+        DB      00EH
+        DB      00FH
+        DB      010H
+        DB      011H
+        DB      012H
+        DB      013H
+        DB      014H
+        DB      015H
+        DB      016H
+        DB      017H
+        DB      018H
+        DB      019H
+        DB      01AH
+        DB      052H
+        DB      059H
+        DB      054H
+        DB      050H
+        DB      045H
+        DB      0C7H
+        DB      0C8H
+        DB      0C9H
+        DB      0CAH
+        DB      0CBH
+        DB      0CCH
+        DB      0CDH
+        DB      0CEH
+        DB      0CFH
+        DB      0DFH
+        DB      0E7H
+        DB      0E8H
+        DB      0E9H
+        DB      0EAH
+        DB      0ECH
+        DB      0EDH
+        DB      0D0H
+        DB      0D1H
+        DB      0D2H
+        DB      0D3H
+        DB      0D4H
+        DB      0D5H
+        DB      0D6H
+        DB      0D7H
+        DB      0D8H
+        DB      0D9H
+        DB      0DAH
+        DB      0DBH
+        DB      0DCH
+        DB      0DDH
+        DB      0DEH
+        DB      0C0H
+        DB      040H
+        DB      0BDH
+        DB      09DH
+        DB      0B1H
+        DB      0B5H
+        DB      0B9H
+        DB      0B4H
+        DB      09EH
+        DB      0B2H
+        DB      0B6H
+        DB      0BAH
+        DB      0BEH
+        DB      09FH
+        DB      0B3H
+        DB      0B7H
+        DB      0BBH
+        DB      0BFH
+        DB      0A3H
+        DB      085H
+        DB      0A4H
+        DB      0A5H
+        DB      0A6H
+        DB      094H
+        DB      087H
+        DB      088H
+        DB      09CH
+        DB      082H
+        DB      098H
+        DB      084H
+        DB      092H
+        DB      090H
+        DB      083H
+        DB      091H
+        DB      081H
+        DB      09AH
+        DB      097H
+        DB      093H
+        DB      095H
+        DB      089H
+        DB      0A1H
+        DB      0AFH
+        DB      08BH
+        DB      086H
+        DB      096H
+        DB      0A2H
+        DB      0ABH
+        DB      0AAH
+        DB      08AH
+        DB      08EH
+        DB      0B0H
+        DB      0ADH
+        DB      08DH
+        DB      0A7H
+        DB      0A8H
+        DB      0A9H
+        DB      08FH
+        DB      08CH
+        DB      0AEH
+        DB      0ACH
+        DB      09BH
+        DB      0A0H
+        DB      099H
+        DB      0BCH
+        DB      0B8H
+        DB      080H
+        DB      03BH
+        DB      03AH
+        DB      070H
+        DB      03CH
+        DB      071H
+        DB      05AH
+        DB      03DH
+        DB      043H
+        DB      056H
+        DB      03FH
+        DB      01EH
+        DB      04AH
+        DB      01CH
+        DB      05DH
+        DB      03EH
+        DB      05CH
+        DB      01FH
+        DB      05FH
+        DB      05EH
+        DB      037H
+        DB      07BH
+        DB      07FH
+        DB      036H
+        DB      07AH
+        DB      07EH
+        DB      033H
+        DB      04BH
+        DB      04CH
+        DB      01DH
+        DB      06CH
+        DB      05BH
+        DB      078H
+        DB      041H
+        DB      035H
+        DB      034H
+        DB      074H
+        DB      030H
+        DB      038H
+        DB      075H
+        DB      039H
+        DB      04DH
+        DB      06FH
+        DB      06EH
+        DB      032H
+        DB      077H
+        DB      076H
+        DB      072H
+        DB      073H
+        DB      047H
+        DB      07CH
+        DB      053H
+        DB      031H
+        DB      04EH
+        DB      06DH
+        DB      048H
+        DB      046H
+        DB      07DH
+        DB      044H
+        DB      01BH
+        DB      058H
+        DB      079H
+        DB      042H
+        DB      060H
+        DB      0FDH
+        DB      0CBH
+        DB      000H
+        DB      01EH
+
+?ADCN:  PUSH    BC
+        PUSH    HL
+        LD      HL,ATBL      ;00AB5H
+        LD      C,A
+        LD      B,000H
+        ADD     HL,BC
+        LD      A,(HL)
+        JR      DACN3                   
+
+_BRK:   LD      A,0CBH
+        OR      A
+        JP      ?KY10
+
+        ; Unused memory.
+        DB      029H
+        DB      0F4H
+        DB      0DDH
+
+?DACN:  PUSH    BC
+        PUSH    HL
+        PUSH    DE
+        LD      HL,00AB5H
+        LD      D,H
+        LD      E,L
+        LD      BC,00100H
+        CPIR    
+        JR      Z,DACN1                 
+        LD      A,0F0H
+DACN2:  POP     DE
+DACN3:  POP     HL
+        POP     BC
+        RET     
+
+DACN1:  OR      A
+        DEC     HL
+        SBC     HL,DE
+        LD      A,L
+        JR      DACN2                   
+
+KTBL:   DB      022H
+        DB      021H
+        DB      017H
+        DB      011H
+        DB      001H
+        DB      0C7H
+        DB      000H
+        DB      01AH
+        DB      024H
+        DB      023H
+        DB      012H
+        DB      005H
+        DB      004H
+        DB      013H
+        DB      018H
+        DB      003H
+        DB      026H
+        DB      025H
+        DB      019H
+        DB      014H
+        DB      007H
+        DB      006H
+        DB      016H
+        DB      002H
+        DB      028H
+        DB      027H
+        DB      009H
+        DB      015H
+        DB      00AH
+        DB      008H
+        DB      00EH
+        DB      000H
+        DB      020H
+        DB      029H
+        DB      010H
+        DB      00FH
+        DB      00CH
+        DB      00BH
+        DB      02FH
+        DB      00DH
+        DB      0BEH
+        DB      02AH
+        DB      052H
+        DB      055H
+        DB      04FH
+        DB      02CH
+        DB      02DH
+        DB      02EH
+        DB      0C5H
+        DB      059H
+        DB      0C3H
+        DB      0C2H
+        DB      0CDH
+        DB      054H
+        DB      000H
+        DB      049H
+        DB      028H
+        DB      027H
+        DB      025H
+        DB      024H
+        DB      022H
+        DB      021H
+        DB      0E7H
+        DB      020H
+        DB      06AH
+        DB      029H
+        DB      02AH
+        DB      026H
+        DB      000H
+        DB      023H
+        DB      000H
+        DB      02EH
+
+KTBLS:  DB      062H
+        DB      061H
+        DB      097H
+        DB      091H
+        DB      081H
+        DB      0C8H
+        DB      000H
+        DB      09AH
+        DB      064H
+        DB      063H
+        DB      092H
+        DB      085H
+        DB      084H
+        DB      093H
+        DB      098H
+        DB      083H
+        DB      066H
+        DB      065H
+        DB      099H
+        DB      094H
+        DB      087H
+        DB      086H
+        DB      096H
+        DB      082H
+        DB      068H
+        DB      067H
+        DB      089H
+        DB      095H
+        DB      08AH
+        DB      088H
+        DB      08EH
+        DB      000H
+        DB      0BFH
+        DB      069H
+        DB      090H
+        DB      08FH
+        DB      08CH
+        DB      08BH
+        DB      051H
+        DB      08DH
+        DB      0A5H
+        DB      02BH
+        DB      0BCH
+        DB      0A4H
+        DB      06BH
+        DB      06AH
+        DB      045H
+        DB      057H
+        DB      0C6H
+        DB      080H
+        DB      0C4H
+        DB      0C1H
+        DB      0CDH
+        DB      040H
+        DB      000H
+        DB      050H
+
+KTBLG:  DB      03EH
+        DB      037H
+        DB      038H
+        DB      03CH
+        DB      053H
+        DB      0C7H
+        DB      000H
+        DB      076H
+        DB      07BH
+        DB      07FH
+        DB      030H
+        DB      034H
+        DB      047H
+        DB      044H
+        DB      06DH
+        DB      0DEH
+        DB      05EH
+        DB      03AH
+        DB      075H
+        DB      071H
+        DB      04BH
+        DB      04AH
+        DB      0DAH
+        DB      06FH
+        DB      0BDH
+        DB      01FH
+        DB      07DH
+        DB      079H
+        DB      05CH
+        DB      072H
+        DB      032H
+        DB      000H
+        DB      09CH
+        DB      0A1H
+        DB      0D6H
+        DB      0B0H
+        DB      0B4H
+        DB      05BH
+        DB      060H
+        DB      01CH
+        DB      09EH
+        DB      0D2H
+        DB      0D8H
+        DB      0B2H
+        DB      0B6H
+        DB      042H
+        DB      0DBH
+        DB      0B8H
+        DB      0C5H
+        DB      0D4H
+        DB      0C3H
+        DB      0C2H
+        DB      0CDH
+        DB      04EH
+        DB      000H
+        DB      0BAH
+
+KTBLGS: DB      036H
+        DB      03FH
+        DB      078H
+        DB      07CH
+        DB      046H
+        DB      0C8H
+        DB      000H
+        DB      077H
+        DB      03BH
+        DB      07EH
+        DB      070H
+        DB      074H
+        DB      048H
+        DB      041H
+        DB      0DDH
+        DB      0D9H
+        DB      01EH
+        DB      07AH
+        DB      035H
+        DB      031H
+        DB      04CH
+        DB      043H
+        DB      0A6H
+        DB      06EH
+        DB      0A2H
+        DB      05FH
+        DB      03DH
+        DB      039H
+        DB      05DH
+        DB      073H
+        DB      033H
+        DB      000H
+        DB      09DH
+        DB      0A3H
+        DB      0B1H
+        DB      0D5H
+        DB      056H
+        DB      06CH
+        DB      0D0H
+        DB      01DH
+        DB      09FH
+        DB      0D1H
+        DB      0B3H
+        DB      0D7H
+        DB      04DH
+        DB      0B5H
+        DB      01BH
+        DB      0B9H
+        DB      0C6H
+        DB      0D3H
+        DB      0C4H
+        DB      0C1H
+        DB      0CDH
+        DB      0B7H
+        DB      000H
+        DB      0BBH
+
+KTBLC:  DB      0F0H
+        DB      0F0H
+        DB      0E2H
+        DB      0C1H
+        DB      0E0H
+        DB      0F0H
+        DB      000H
+        DB      0E5H
+        DB      0F0H
+        DB      0F0H
+        DB      0C2H
+        DB      0CFH
+        DB      0CEH
+        DB      0C3H
+        DB      0E3H
+        DB      0F3H
+        DB      0F0H
+        DB      0F0H
+        DB      0E4H
+        DB      0C4H
+        DB      0F7H
+        DB      0F6H
+        DB      0C6H
+        DB      0F2H
+        DB      0F0H
+        DB      0F0H
+        DB      0F9H
+        DB      0C5H
+        DB      0FAH
+        DB      0F8H
+        DB      0FEH
+        DB      0F0H
+        DB      0F0H
+        DB      0F0H
+        DB      0E1H
+        DB      0FFH
+        DB      0FCH
+        DB      0FBH
+        DB      0F0H
+        DB      0FDH
+        DB      0EFH
+        DB      0F4H
+        DB      0E6H
+        DB      0CCH
+        DB      0F0H
+        DB      0F0H
+        DB      0F0H
+        DB      0F0H
+        DB      0F0H
+        DB      0EBH
+        DB      0F0H
+        DB      0F0H
+        DB      0F0H
+        DB      0EEH
+        DB      0F0H
+
+?BRK:  LD      A,0F0H
+        LD      (KEYPA),A
+        NOP     
+        LD      A,(KEYPB)
+        OR      A
+        RLA     
+        JR      NC,L0D37                
+        RRA     
+        RRA     
+        JR      NC,L0D27                
+        RRA     
+        JR      NC,L0D2B                
+        CCF     
+        RET     
+
+L0D27:  LD      A,040H
+        SCF     
+        RET     
+
+L0D2B:  LD      A,(KDATW)
+        LD      A,001H
+        LD      (KDATW),A
+        LD      A,010H
+        SCF     
+        RET     
+
+L0D37:  AND     002H
+        RET     Z
+
+        LD      A,020H
+        SCF     
+        RET     
+
+L0D3E:  PUSH    AF
+        LD      A,003H
+        LD      (KEYPF),A
+        CALL    L0759
+        CALL    L0759
+        LD      A,002H
+        LD      (KEYPF),A
+        CALL    L0759
+        CALL    L0759
+        POP     AF
+        RET     
+
+L0D57:  PUSH    AF
+        LD      A,003H
+        LD      (KEYPF),A
+        CALL    L0759
+        CALL    L0759
+        CALL    L0759
+        CALL    L0759
+        LD      A,002H
+        LD      (KEYPF),A
+        CALL    L0759
+        CALL    L0759
+        CALL    L0759
+        CALL    L0760
+        POP     AF
+        RET     
+
+?DSPA:  CP      008H
+        JR      Z,L0D90                 
+L0D80:  RRC     (HL)
+        DJNZ    L0D80                   
+        SET     0,(HL)
+        RES     1,(HL)
+        LD      B,A
+L0D89:  RLC     (HL)
+        DJNZ    L0D89                   
+DSP04:  JP      CURSR
+L0D90:  INC     HL
+        SET     0,(HL)
+        RES     1,(HL)
+        JR      DSP04                   
+DSP02:  SET     7,(HL)
+        INC     HL
+        RES     0,(HL)
+        JR      DSP04                   
+
+
+MSG_1:  DB      07FH, 020H
+MSG_2:  DB      050H, 04CH, 041H, 059H, 00DH, 0F3H
+
+?BLNK:  RET     
+
+DLY12:  PUSH    BC
+        LD      B,023H
+DLY12A: CALL    DLY3
+        DJNZ    DLY12A                   
+        POP     BC
+        RET     
+
+        ; BELL DATA
+?BELD:  DB      0D7H, 041H, 030H, 00DH
+
+?DSP:   PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      B,A
+        CALL    ?PONT
+        LD      (HL),B
+        LD      HL,(DSPXY)
+        LD      A,L
+DSP01:  CP      COLW - 1                ; End of line.
+        JR      NZ,DSP04                
+        CALL    .MANG
+        JR      C,DSP04                 
+        LD      A,(SPAGE)
+        OR      A
+        JP      NZ,.DSP03
+        EX      DE,HL
+        LD      A,B
+        CP      007H
+        JR      Z,DSP02                 
+        JR      ?DSPA                   
+
+        ; Unused memory.
+        INC     H
+        DI      
+
+?DPCT:  PUSH    AF                      ; Display control, character is mapped to a function call.
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      B,A
+        AND     0F0H
+        CP      0C0H
+        JP      NZ,?RSTR
+        XOR     B
+        RLCA    
+        LD      C,A
+        LD      B,000H
+        LD      HL,CTBL
+        LD      A,(SPAGE)
+        OR      A
+        JR      Z,DPCT1                 
+        LD      HL,.CTBL
+DPCT1:  ADD     HL,BC
+        LD      E,(HL)
+        INC     HL
+        LD      D,(HL)
+        EX      DE,HL
+        JP      (HL)
+
+
+CTBL:   DW      SCROL
+        DW      CURSD
+        DW      CURSU
+        DW      CURSR
+        DW      CURSL
+        DW      HOME
+        DW      CLRS
+        DW      DEL
+        DW      INST
+        DW      ALPHA
+        DW      KANA
+        DW      ?RSTR
+        DW      REV
+        DW      CR
+        DW      ROLUP
+        DW      ROLD
+
+;.CTBL: DW      .SCROL
+;       DW      CURSD
+;       DW      CURSU
+;       DW      CURSR
+;       DW      CURSL
+;       DW      HOM0
+;       DW      CLRS
+;       DW      DEL
+;       DW      INST
+;       DW      ALPHA
+;       DW      KANA
+;       DW      ?RSTR
+;       DW      REV
+;       DW      .CR
+;       DW      ?RSTR
+;       DW      ?RSTR
+
+SCROL:  LD      HL,PBIAS
+        LD      C,005H
+        LD      A,(ROLEND)
+        ADD     A,C
+        LD      (ROLEND),A
+        LD      A,(ROLTOP)
+        ADD     A,C
+        LD      (ROLTOP),A
+SCROL1: LD      A,C
+        ADD     A,(HL)
+        LD      (HL),A
+        CALL    L09C7
+        LD      HL,(PAGETP)
+        LD      DE,SCRNSZ
+        ADD     HL,DE                    ; HL=PAGETOP + 1000/2000
+        LD      B,COLW
+        XOR     A
+SCROL2: RES     3,H
+        LD      (HL),A
+        INC     HL
+        DJNZ    SCROL2                   
+        LD      A,(PBIAS)                ; PBIAS is the offest for hardware scroll.
+        LD      L,A
+        LD      H,0E2H                   ; Hardware scroll region, E2<xx>
+        LD      A,(HL)
+        LD      HL,MANGE
+        OR      A
+        LD      B,007H
+SCROL3: RR      (HL)
+        DEC     HL
+        DJNZ    SCROL3                   
+        JP      ?RSTR
+
+CURSD:  LD      HL,(DSPXY)
+        LD      A,H
+        CP      ROW - 1
+        JR      Z,CURS4                 
+        INC     H
+CURS1:  CALL    MGP.I
+CURS3:  LD      (DSPXY),HL
+        JR      ?RSTR                   
+
+CURSU:  LD      HL,(DSPXY)
+        LD      A,H
+        OR      A
+        JR      Z,CURS5                 
+        DEC     H
+CURSU1: CALL    MGP.D
+        JR      CURS3                   
+
+CURSR:  LD      HL,(DSPXY)
+        LD      A,L
+        CP      COLW - 1                ; End of line
+        JR      NC,CURS2                
+        INC     L
+        JR      CURS3                   
+CURS2:  LD      L,000H
+        INC     H
+        LD      A,H
+        CP      ROW 
+        JR      C,CURS1                 
+        LD      H,ROW - 1
+        LD      (DSPXY),HL
+CURS4:  JR      CURS6                   
+
+CURSL:  LD      HL,(DSPXY)
+        LD      A,L
+        OR      A
+        JR      Z,CURS5A                 
+        DEC     L
+        JR      CURS3                   
+CURS5A: LD      L,COLW - 1              ; End of line
+        DEC     H
+        JP      P,CURSU1
+        LD      H,000H
+        LD      (DSPXY),HL
+CURS5:  LD      A,(SPAGE)
+        OR      A
+        JR      NZ,?RSTR                
+        JP      ROLD
+
+CLRS:   LD      HL,MANG
+        LD      B,01BH
+        CALL    ?CLER
+        LD      HL,SCRN
+        PUSH    HL
+        CALL    L09E2
+        POP     HL
+        LD      A,(SPAGE)
+        OR      A
+        JR      NZ,CLRS1                
+        LD      (PAGETP),HL
+        LD      A,07DH
+        LD      (ROLEND),A
+CLRS1:  LD      A,(SCLDSP)
+HOM00:  JP      HOM0
+
+CURS6:  LD      A,(SPAGE)
+        OR      A
+        JP      NZ,.SCROL
+        JP      ROLU
+
+ALPHA:  XOR     A
+ALPHI:  LD      (KANAF),A
+?RSTR:  POP     HL
+?RSTR1: POP     DE
+        POP     BC
+        POP     AF
+        RET     
+
+        ; Unused memory
+        DEC     C
+        DEC     C
+        DEC     C
+        DEC     C
+
+KANA:   LD      A,001H
+        JR      ALPHI                   
+
+DEL:    LD      HL,(DSPXY)
+        LD      A,H
+        OR      L
+        JR      Z,?RSTR                 
+        LD      A,L
+        OR      A
+        JR      NZ,DEL1                
+        CALL    .MANG
+        JR      C,DEL1                 
+        CALL    ?PONT
+        DEC     HL
+        LD      (HL),000H
+        JR      CURSL                   
+DEL1:   CALL    .MANG
+        RRCA    
+        LD      A,COLW
+        JR      NC,L0F13                
+        RLCA    
+L0F13:  SUB     L
+        LD      B,A
+        CALL    ?PONT
+        PUSH    HL
+        POP     DE
+        DEC     DE
+        SET     4,D
+DEL2:   RES     3,H
+        RES     3,D
+        LD      A,(HL)
+        LD      (DE),A
+        INC     HL
+        INC     DE
+        DJNZ    DEL2                   
+        DEC     HL
+        LD      (HL),000H
+        JP      CURSL
+
+INST:   CALL    .MANG
+        RRCA    
+        LD      L,COLW - 1              ; End of line
+        LD      A,L
+        JR      NC,INST1A                
+        INC     H
+INST1A: CALL    ?PNT1
+        PUSH    HL
+        LD      HL,(DSPXY)
+        JR      NC,INST2                
+        LD      A,(COLW*2)-1            ; 04FH
+INST2:  SUB     L
+        LD      B,A
+        POP     DE
+        LD      A,(DE)
+        OR      A
+        JR      NZ,?RSTR                
+        CALL    ?PONT
+        LD      A,(HL)
+        LD      (HL),000H
+INST1:  INC     HL
+        RES     3,H
+        LD      E,(HL)
+        LD      (HL),A
+        LD      A,E
+        DJNZ    INST1                   
+        JR      ?RSTR                   
+
+ROLD:   LD      HL,PBIAS
+        LD      A,(ROLTOP)
+        CP      (HL)
+        JR      Z,?RSTR                 
+        CALL    MGP.D
+        LD      A,(HL)
+        SUB     005H
+ROL2:   LD      (HL),A
+        LD      L,A
+        LD      H,0E2H
+        LD      A,(HL)
+        CALL    L09C7
+        JP      ?RSTR
+
+CR:     CALL    .MANG
+        RRCA    
+        JP      NC,CURS2
+        LD      L,000H
+        INC     H
+        LD      A,H
+        CP      ROW - 1                   ; End of line?
+        JR      Z,CR3                 
+        JR      NC,CR2                
+        CALL    MGP.I
+        INC     H
+        JP      CURS1
+CR2:    DEC     H
+        LD      (DSPXY),HL
+        LD      HL,ROLU
+        PUSH    HL
+        PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        CALL    ROLU
+CR3:    LD      (DSPXY),HL
+        CALL    MGP.I
+
+ROLU:   LD      HL,PBIAS
+        LD      A,(ROLEND)
+        CP      (HL)
+        JP      Z,SCROL
+ROLU1:  CALL    MGP.I
+        LD      A,(HL)
+        ADD     A,005H
+        JR      ROL2                   
+
+?PONT:  LD      HL,(DSPXY)
+?PNT1:  PUSH    AF
+        PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        POP     BC
+        LD      DE,COLW
+        LD      HL,SCRN - COLW
+        LD      A,(SPAGE)
+        OR      A
+        JR      NZ,?PNT2                
+        LD      HL,(PAGETP)
+        SBC     HL,DE
+?PNT2:  ADD     HL,DE
+        DEC     B
+        JP      P,?PNT2
+        LD      B,000H
+        ADD     HL,BC
+        RES     3,H
+        POP     DE
+        POP     BC
+        POP     AF
+        RET     
+
+?CLER:  XOR     A
+        JR      ?DINT                   
+?CLRFF: LD      A,0FFH
+?DINT:  LD      (HL),A
+        INC     HL
+        DJNZ    ?DINT                   
+        RET     
+
+GAPCK:  PUSH    BC
+        PUSH    DE
+        PUSH    HL
+        LD      BC,KEYPB
+        LD      DE,KEYPC
+GAPCK1: LD      H,064H
+GAPCK2: CALL    EDGE
+        JR      C,GAPCK3                 
+        CALL    DLY3
+        LD      A,(DE)
+        AND     020H
+        JR      NZ,GAPCK1                
+        DEC     H
+        JR      NZ,GAPCK2                
+GAPCK3: JP      RET3
+
+        ;    MONITOR WORK AREA
+        ;    (MZ700)
+
+STACK:  EQU     010F0H
+
+        ORG     STACK
+SPV:
+IBUFE:                                                                   ; TAPE BUFFER (128 BYTES)
+ATRB:   DS      virtual 1                                                ; ATTRIBUTE
+NAME:   DS      virtual 17                                               ; FILE NAME
+SIZE:   DS      virtual 2                                                ; BYTESIZE
+DTADR:  DS      virtual 2                                                ; DATA ADDRESS
+EXADR:  DS      virtual 2                                                ; EXECUTION ADDRESS
+COMNT:  DS      virtual 92                                               ; COMMENT
+SWPW:   DS      virtual 10                                               ; SWEEP WORK
+KDATW:  DS      virtual 2                                                ; KEY WORK
+KANAF:  DS      virtual 1                                                ; KANA FLAG (01=GRAPHIC MODE)
+DSPXY:  DS      virtual 2                                                ; DISPLAY COORDINATES
+MANG:   DS      virtual 6                                                ; COLUMN MANAGEMENT
+MANGE:  DS      virtual 1                                                ; COLUMN MANAGEMENT END
+PBIAS:  DS      virtual 1                                                ; PAGE BIAS
+ROLTOP: DS      virtual 1                                                ; ROLL TOP BIAS
+MGPNT:  DS      virtual 1                                                ; COLUMN MANAG. POINTER
+PAGETP: DS      virtual 2                                                ; PAGE TOP
+ROLEND: DS      virtual 1                                                ; ROLL END
+        DS      virtual 14                                               ; BIAS
+FLASH:  DS      virtual 1                                                ; FLASHING DATA
+SFTLK:  DS      virtual 1                                                ; SHIFT LOCK
+REVFLG: DS      virtual 1                                                ; REVERSE FLAG
+SPAGE:  DS      virtual 1                                                ; PAGE CHANGE
+FLSDT:  DS      virtual 1                                                ; CURSOR DATA
+STRGF:  DS      virtual 1                                                ; STRING FLAG
+DPRNT:  DS      virtual 1                                                ; TAB COUNTER
+TMCNT:  DS      virtual 2                                                ; TAPE MARK COUNTER
+SUMDT:  DS      virtual 2                                                ; CHECK SUM DATA
+CSMDT:  DS      virtual 2                                                ; FOR COMPARE SUM DATA
+AMPM:   DS      virtual 1                                                ; AMPM DATA
+TIMFG:  DS      virtual 1                                                ; TIME FLAG
+SWRK:   DS      virtual 1                                                ; KEY SOUND FLAG
+TEMPW:  DS      virtual 1                                                ; TEMPO WORK
+ONTYO:  DS      virtual 1                                                ; ONTYO WORK
+OCTV:   DS      virtual 1                                                ; OCTAVE WORK
+RATIO:  DS      virtual 2                                                ; ONPU RATIO
+BUFER:  DS      virtual 81                                               ; GET LINE BUFFER
+
+        ;    EQU TABLE I/O REPORT
+
+SCRN:   EQU     0D000H
+ARAM:   EQU     0D800H
+KEYPA:  EQU     0E000H
+KEYPB:  EQU     0E001H
+KEYPC:  EQU     0E002H
+KEYPF:  EQU     0E003H
+CSTR:   EQU     0E002H
+CSTPT:  EQU     0E003H
+CONT0:  EQU     0E004H
+CONT1:  EQU     0E005H
+CONT2:  EQU     0E006H
+CONTF:  EQU     0E007H
+SUNDG:  EQU     0E008H
+TEMP:   EQU     0E008H
+MEMSW:  EQU     0E00CH
+MEMSWR: EQU     0E010H
+INVDSP: EQU     0E014H
+NRMDSP: EQU     0E015H
+SCLDSP: EQU     0E200H
diff --git a/software/asm/sharpmz-test.asm b/software/asm/sharpmz-test.asm
new file mode 100644
index 0000000..35c9c2a
--- /dev/null
+++ b/software/asm/sharpmz-test.asm
@@ -0,0 +1,1780 @@
+;--------------------------------------------------------------------------------------------------------
+;-
+;- Name:            sharpmz-test.asm
+;- Created:         October 2018
+;- Author(s):       Philip Smart
+;- Description:     Sharp MZ series tester utility.
+;-                  This assembly language program is written to aid in testing components
+;-                  of the SharpMZ Series FPGA emulation.
+;-
+;-                  Currently it aids in testing:
+;-                      1. Tape Read
+;-                      2. Tape Write
+;-                      3. Memory Test
+;-                      4. Graphics RAM Test
+;-
+;- Credits:         
+;- Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+;-
+;- History:         October 2018 - Merged 2 utilities to create this compilation.
+;-
+;--------------------------------------------------------------------------------------------------------
+;- This source file is free software: you can redistribute it and-or modify
+;- it under the terms of the GNU General Public License as published
+;- by the Free Software Foundation, either version 3 of the License, or
+;- (at your option) any later version.
+;-
+;- This source file is distributed in the hope that it will be useful,
+;- but WITHOUT ANY WARRANTY; without even the implied warranty of
+;- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;- GNU General Public License for more details.
+;-
+;- You should have received a copy of the GNU General Public License
+;- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+;--------------------------------------------------------------------------------------------------------
+
+KEYPA:     EQU      0E000h
+KEYPB:     EQU      0E001h
+KEYPC:     EQU      0E002h
+KEYPF:     EQU      0E003h
+CSTR:      EQU      0E002h
+CSTPT:     EQU      0E003h
+CONT0:     EQU      0E004h
+CONT1:     EQU      0E005h
+CONT2:     EQU      0E006h
+CONTF:     EQU      0E007h
+SUNDG:     EQU      0E008h
+TEMP:      EQU      0E008h
+GETL:      EQU      00003h
+LETNL:     EQU      00006h
+NL:        EQU      00009h
+PRNTS:     EQU      0000Ch
+PRNT:      EQU      00012h
+MSG:       EQU      00015h
+MSGX:      EQU      00018h
+MONIT:     EQU      00086h
+ST1:       EQU      00095h
+PRTHL:     EQU      003BAh
+PRTHX:     EQU      003C3h
+DPCT:      EQU      00DDCh
+?BRK:      EQU      00D11h
+?RSTR1:    EQU      00EE6h
+TPSTART:   EQU      010F0h
+MEMSTART:  EQU      01200h
+GRAMSTART: EQU      0C000h
+GRAMEND:   EQU      0FFFFh
+MSTART:    EQU      0BF00h
+GRCTL:     EQU      0C8h
+GRREDFLT:  EQU      0C9h
+GRGRNFLT:  EQU      0CAh
+GRBLUFLT:  EQU      0CBh
+GRENABLE:  EQU      0CCh
+GRDISABLE: EQU      0CDh
+
+
+           ORG      TPSTART
+
+SPV:
+IBUFE:                                                                   ; TAPE BUFFER (128 BYTES)
+;ATRB:      DS       virtual 1                                           ; ATTRIBUTE
+ATRB:      DB       01h                                                  ; Code Type, 01 = Machine Code.
+;NAME:      DS       virtual 17                                          ; FILE NAME
+NAME:      DB       "SHARPMZ TEST V1", 0Dh, 00h                          ; Title/Name (17 bytes).
+;SIZE:      DS       virtual 2                                           ; BYTESIZE
+SIZE:      DW       MEND - MSTART                                        ; Size of program.
+;DTADR:     DS       virtual 2                                           ; DATA ADDRESS
+DTADR:     DW       MSTART                                               ; Load address of program.
+;EXADR:     DS       virtual 2                                           ; EXECUTION ADDRESS
+EXADR:     DW       MSTART                                               ; Exec address of program.
+COMNT:     DS       104                                                  ; COMMENT
+KANAF:     DS       virtual 1                                            ; KANA FLAG (01=GRAPHIC MODE)
+DSPXY:     DS       virtual 2                                            ; DISPLAY COORDINATES
+MANG:      DS       virtual 27                                           ; COLUMN MANAGEMENT
+FLASH:     DS       virtual 1                                            ; FLASHING DATA
+FLPST:     DS       virtual 2                                            ; FLASHING POSITION
+FLSST:     DS       virtual 1                                            ; FLASHING STATUS
+FLSDT:     DS       virtual 1                                            ; CURSOR DATA
+STRGF:     DS       virtual 1                                            ; STRING FLAG
+DPRNT:     DS       virtual 1                                            ; TAB COUNTER
+TMCNT:     DS       virtual 2                                            ; TAPE MARK COUNTER
+SUMDT:     DS       virtual 2                                            ; CHECK SUM DATA
+CSMDT:     DS       virtual 2                                            ; FOR COMPARE SUM DATA
+AMPM:      DS       virtual 1                                            ; AMPM DATA
+TIMFG:     DS       virtual 1                                            ; TIME FLAG
+SWRK:      DS       virtual 1                                            ; KEY SOUND FLAG
+TEMPW:     DS       virtual 1                                            ; TEMPO WORK
+ONTYO:     DS       virtual 1                                            ; ONTYO WORK
+OCTV:      DS       virtual 1                                            ; OCTAVE WORK
+RATIO:     DS       virtual 2                                            ; ONPU RATIO
+BUFER:     DS       virtual 81                                           ; GET LINE BUFFER
+
+
+
+           ORG      MSTART
+           JP       START
+
+           ; Graphics Initialisation. Needs to be in memory before C000-FFFF
+           ;
+GRAMINIT:  OUT      (GRCTL),A
+           OUT      (GRENABLE),A
+GRAM0:     LD       HL,GRAMSTART
+           LD       BC,GRAMEND - GRAMSTART
+GRAM1:     LD       A,000h
+           LD       (HL),A
+           INC      HL
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GRAM1
+           OUT      (GRDISABLE),A
+           RET
+
+           ; Graphics Test. Needs to be in memory before C000-FFFF
+           ;
+GRAMTEST:  OUT      (GRCTL),A
+           OUT      (GRENABLE),A
+           LD       E,080h
+GRAMTEST0: LD       HL,GRAMSTART
+           LD       BC,GRAMEND - GRAMSTART
+GRAMTEST1: LD       A,E
+           LD       (HL),A
+           INC      HL
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GRAMTEST1
+           SRL      E
+           JR       NZ,GRAMTEST0
+           JR       C,GRAMTEST0
+           OUT      (GRDISABLE),A
+           RET
+
+           ; Graphics Test routine.
+           ;
+           ;   Graphics mode:- 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR),
+           ;                     5 = GRAM Output Enable  0 = active.
+           ;                     4 = VRAM Output Enable, 0 = active.
+           ;                   3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect),
+           ;                   1/0 = Read mode  (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
+           ;
+GRAPHICS:  LD       A,000h
+           CALL     GRAMTEST
+           LD       A,005h
+           CALL     GRAMTEST
+           LD       A,00Ah
+           CALL     GRAMTEST
+           LD       A,0AAh      ; Set Red filter.
+           OUT      (GRREDFLT),A
+           LD       A,055h      ; Set Green filter.
+           OUT      (GRGRNFLT),A
+           LD       A,0FFh      ; Set Blue filter.
+           OUT      (GRBLUFLT),A
+           LD       A, 00Ch     ; Set graphics mode to Indirect Page write.
+           CALL     GRAMTEST
+           LD       A, 0CCh     ; Set graphics mode to Indirect Page write.
+           OUT      (GRCTL),A
+           JR       GETL1
+
+           ; Graphics progress bar indicator. Needs to be in memory before C000-FFFF
+           ;
+GRPHIND:   LD       HL,(GRPHPOS) ; Get position of graphics progress line.
+           OUT      (GRENABLE),A ; Enable graphics memory.
+           LD       A,0FFh
+           LD       (HL),A
+           OUT      (GRDISABLE),A; Disable graphics memory.
+           INC      HL
+           LD       (GRPHPOS),HL
+           RET
+           
+
+           ;
+           ; Start of main program.
+           ;
+START:     CALL     LETNL
+           LD       DE,TITLE
+           CALL     MSG
+           CALL     LETNL
+           CALL     LETNL
+           ;
+INITGRPH:  LD       DE,MSG_INITGR
+           CALL     MSG
+           CALL     LETNL
+           LD       A,0FFh      ; Set Red filter.
+           OUT      (GRREDFLT),A
+           LD       A,000h      ; Set Green filter.
+           OUT      (GRGRNFLT),A
+           LD       A,000h      ; Set Blue filter.
+           OUT      (GRBLUFLT),A
+           LD       A,000h
+           CALL     GRAMINIT
+           LD       A,005h
+           CALL     GRAMINIT
+           LD       A,00Ah
+           CALL     GRAMINIT
+           LD       A, 0CCh     ; Set graphics mode to Indirect Page write.
+           OUT      (GRCTL),A
+           LD       HL,0DE00h
+           LD       (GRPHPOS),HL
+           ;
+INITMEM:   LD       DE,MSG_INITM
+           CALL     MSG
+           CALL     LETNL
+           LD       HL,1200h
+           LD       BC,MSTART - 1200h
+CLEAR1:    LD       A,00h
+           LD       (HL),A
+           INC      HL
+           DEC      BC
+           LD       A,B
+           OR       C
+           JP       NZ,CLEAR1
+GETL1:     CALL     NL
+           LD       A,03EH
+           CALL     PRNT
+           LD       DE,BUFER
+           CALL     GETL
+GETL2:     LD       A,(DE)
+           INC      DE
+           CP       00DH
+           JR       Z,GETL1                 
+           CP       'G'                    ; Graphics Test
+           JP       Z,GRAPHICS                 
+           CP       'H'                    ; Command Synopsis
+           JP       Z,HELP                 
+           CP       'M'                    ; Memory Test
+           JR       Z,MEMTEST                 
+           CP       'R'                    ; Read Test
+           JP       Z,LOAD                 
+           CP       'T'                    ; Timer Test
+           JP       Z,TIMERTST
+           CP       'W'                    ; Write Test
+           JP       Z,SAVE                 
+           CP       'Q'                    ; Quit?
+           JP       Z,ST1                 
+           JR       GETL2     
+
+
+MEMTEST:   LD       B,240       ; Number of loops
+LOOP:      LD       HL,MEMSTART ; Start of checked memory,
+           LD       D,0BFh      ; End memory check BF00
+LOOP1:     LD       A,000h
+           CP       L
+           JR       NZ,LOOP1b
+           CALL     PRTHL       ; Print HL as 4digit hex.
+           LD       A,0C4h      ; Move cursor left.
+           LD       E,004h      ; 4 times.
+LOOP1a:    CALL     DPCT
+           DEC      E
+           JR       NZ,LOOP1a
+LOOP1b:    INC      HL
+           LD       A,H
+           CP       D           ; Have we reached end of memory.
+           JR       Z,LOOP3     ; Yes, exit.
+           LD       A,(HL)      ; Read memory location under test, ie. 0.
+           CPL                  ; Subtract, ie. FF - A, ie FF - 0 = FF.
+           LD       (HL),A      ; Write it back, ie. FF.
+           SUB      (HL)        ; Subtract written memory value from A, ie. should be 0.
+           JR       NZ,LOOP2    ; Not zero, we have an error.
+           LD       A,(HL)      ; Reread memory location, ie. FF
+           CPL                  ; Subtract FF - FF
+           LD       (HL),A      ; Write 0
+           SUB      (HL)        ; Subtract 0
+           JR       Z,LOOP1     ; Loop if the same, ie. 0
+LOOP2:     LD       A,16h
+           CALL     PRNT        ; Print A
+           CALL     PRTHX       ; Print HL as 4 digit hex.
+           CALL     PRNTS       ; Print space.
+           XOR      A
+           LD       (HL),A
+           LD       A,(HL)      ; Get into A the failing bits.
+           CALL     PRTHX       ; Print A as 2 digit hex.
+           CALL     PRNTS       ; Print space.
+           LD       A,0FFh      ; Repeat but first load FF into memory
+           LD       (HL),A
+           LD       A,(HL)
+           CALL     PRTHX       ; Print A as 2 digit hex.
+           NOP
+           JR       LOOP4
+
+LOOP3:     CALL     PRTHL
+           LD       DE,OKCHECK
+           CALL     MSG          ; Print check message in DE
+           LD       A,B          ; Print loop count.
+           CALL     PRTHX
+           LD       DE,OKMSG
+           CALL     MSG          ; Print ok message in DE
+           CALL     NL
+           CALL     GRPHIND
+           DEC      B
+           JR       NZ,LOOP
+           LD       DE,DONEMSG
+           CALL     MSG          ; Print check message in DE
+           JP       GETL1
+
+LOOP4:     LD       B,09h
+           CALL     PRNTS        ; Print space.
+           XOR      A            ; Zero A
+           SCF                   ; Set Carry
+LOOP5:     PUSH     AF           ; Store A and Flags
+           LD       (HL),A       ; Store 0 to bad location.
+           LD       A,(HL)       ; Read back
+           CALL     PRTHX        ; Print A as 2 digit hex.
+           CALL     PRNTS        ; Print space
+           POP      AF           ; Get back A (ie. 0 + C)
+           RLA                   ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB
+           DJNZ     LOOP5        ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit.
+           XOR      A            ; Zero A, clears flags.
+           LD       A,80h
+           LD       B,08h
+LOOP6:     PUSH     AF           ; Repeat above but AND memory location with original A (ie. 80) 
+           LD       C,A          ; Basically walk through all the bits to find which one is stuck.
+           LD       (HL),A
+           LD       A,(HL)
+           AND      C
+           NOP
+           JR       Z,LOOP8      ; If zero then print out the bit number
+           NOP
+           NOP
+           LD       A,C
+           CPL
+           LD       (HL),A
+           LD       A,(HL)
+           AND      C
+           JR       NZ,LOOP8     ; As above, if the compliment doesnt yield zero, print out the bit number.
+LOOP7:     POP      AF
+           RRCA
+           NOP
+           DJNZ     LOOP6
+           JP       GETL1
+
+LOOP8:     CALL     LETNL        ; New line.
+           LD       DE,BITMSG    ; BIT message
+           CALL     MSG          ; Print message in DE
+           LD       A,B
+           DEC      A
+           CALL     PRTHX        ; Print A as 2 digit hex, ie. BIT number.
+           CALL     LETNL        ; New line
+           LD       DE,BANKMSG   ; BANK message
+           CALL     MSG          ; Print message in DE
+           LD       A,H
+           CP       50h          ; 'P'
+           JR       NC,LOOP9     ; Work out bank number, 1, 2 or 3.
+           LD       A,01h
+           JR       LOOP11
+
+LOOP9:     CP       90h
+           JR       NC,LOOP10
+           LD       A,02h
+           JR       LOOP11
+
+LOOP10:    LD       A,03h
+LOOP11:    CALL     PRTHX        ; Print A as 2 digit hex, ie. BANK number.
+           JR       LOOP7
+
+
+           ;
+           ; LOAD COMMAND
+           ;
+LOAD:      CALL     ?RDI
+           JP       C,?ER
+LOA0:      CALL     NL
+           LD       DE,MSG_LOADFROM
+           CALL     MSG
+           LD       HL,(DTADR)
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_LOADEXEC
+           CALL     MSG
+           LD       HL,(EXADR)
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_LOADSIZE
+           CALL     MSG
+           LD       HL,(SIZE)
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_LOADFILE
+           CALL     MSGX
+           LD       DE,NAME
+           CALL     MSGX
+           CALL     NL
+           CALL     ?RDD
+           JP       C,?ER
+           LD       HL,(EXADR)
+           LD       A,H
+           CP       12h
+           JP       C,GETL1
+           JP       (HL)
+
+
+           ; SAVE COMMAND
+
+SAVE:      LD       HL,TESTBUF
+           LD       DE,IBUFE
+           LD       BC,128
+           LDIR
+           LD       DE,TITLE_SAVE
+           CALL     MSG
+           CALL     LETNL
+           CALL     LETNL
+           LD       DE,MSG_SAVEFROM
+           CALL     MSG
+           LD       HL,(DTADR)
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_SAVEEXEC
+           CALL     MSG
+           LD       HL,(EXADR)
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_SAVESIZE
+           CALL     MSG
+           LD       HL,(SIZE)
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_SAVEFILE
+           CALL     MSGX
+           LD       DE,NAME
+           CALL     MSGX
+           CALL     NL
+           LD       A,01H                                                    ; ATTRIBUTE: OBJECT CODE
+           LD       (ATRB),A
+           ;
+           LD       DE,MSG_WHDR
+           CALL     MSGX
+           CALL     NL
+           CALL     QWRI
+           JP       C,QER                                                    ; WRITE ERROR
+           ;
+           LD       DE,MSG_WDATA
+           CALL     MSGX
+           CALL     NL
+           ;
+           CALL     QWRD                                                     ; DATA
+           JP       C,QER
+           CALL     NL
+           LD       DE,MSGOK                                                 ; OK MESSAGE
+           CALL     MSGX                                                     ; CALL MSGX
+           JP       GETL1           
+
+           ;
+           ; ERROR (LOADING)
+           ;
+QER:       CP       02h
+           JP       Z,GETL1
+           LD       DE,MSG_ERRWRITE
+           CALL     MSG
+           JP       GETL1
+           ;
+           ; ERROR (LOADING)
+           ;
+?ER:       CP       02h
+           JP       Z,GETL1
+           LD       DE,MSG_ERRCHKSUM
+           CALL     MSG
+           JP       GETL1
+           ;
+           ; READ INFORMATION
+           ;
+           ; EXIT ACC = 0 : OK CF=0
+           ;          = 1 : ER CF=1
+           ;          = 2 : BREAK CF=1
+           ;
+?RDI:      DI
+           PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       D,0D2h
+           LD       E,0CCh
+           LD       BC,80h
+           LD       HL,IBUFE
+RD1:       CALL     MOTOR
+           JP       C,RTP6
+           CALL     TMARK
+           JP       C,RTP6
+;   CALL     PRTHL
+           CALL     RTAPE
+           POP      HL
+           POP      BC
+           POP      DE
+           ;CALL     MSTOP
+           PUSH     AF
+           LD       A,(TIMFG)
+           CP       0F0h
+           JR       NZ,RD2
+           EI
+RD2:       POP      AF
+           RET
+
+           ;
+           ; READ DATA
+           ;
+?RDD:      DI
+           PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       D,0D2h
+           LD       E,53h
+           LD       BC,(SIZE)
+           LD       HL,(DTADR)
+           LD       A,B
+           OR       C
+           JP       Z,RDD1
+           JR       RD1
+RDD1:      POP      HL
+           POP      BC
+           POP      DE
+           ;CALL     MSTOP
+           PUSH     AF
+           LD       A,(TIMFG)
+           CP       0F0h
+           JR       NZ,RDD2
+           EI
+RDD2:      POP      AF
+           RET
+
+           ;
+           ; READ TAPE
+           ;
+RTAPE:     ;PUSH     BC
+           ;PUSH     DE
+           ;LD       DE,MSG_READTAPE
+           ;CALL     MSG
+           ;CALL     NL
+           ;POP      DE
+           ;POP      BC
+           PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       H,2
+RTP1:      LD       BC,KEYPB
+           LD       DE,CSTR
+RTP2:      CALL     EDGE
+           JP       C,RTP6
+           CALL     DLY3
+           LD       A,(DE)
+           AND      20h
+           JP       Z,RTP2
+           LD       D,H
+           LD       HL,0
+           LD       (SUMDT),HL
+           POP      HL
+           POP      BC
+           PUSH     BC
+           PUSH     HL
+RTP3:      CALL     RBYTE
+           JP       C,RTP6
+           LD       (HL),A
+           INC      HL
+           DEC      BC
+           LD       A,B
+           OR       C
+           JP       NZ,RTP3
+           LD       HL,(SUMDT)
+           CALL     RBYTE                 ; Checksum MSB
+           JP       C,RTP6
+           LD       D,A
+           CALL     RBYTE                 ; Checksum LSB
+           JP       C,RTP6
+           LD       E,A
+           CP       L
+           JP       NZ,RTP5
+           LD       A,D
+           CP       H
+           JP       NZ,RTP5
+RTP0:      XOR      A
+           ;
+           PUSH     HL
+           PUSH     DE
+           PUSH     DE
+           LD       DE,MSG_CHKSUM_MZ1
+           CALL     MSGX
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_CHKSUM_TP1
+           CALL     MSGX
+           POP      DE
+           EX       DE,HL
+           CALL     PRTHL
+           CALL     NL
+           POP      DE
+           POP      HL
+           ;
+RTP4:      
+RET2:      POP      HL
+           POP      BC
+           POP      DE
+           CALL     MSTOP
+           PUSH     AF
+           LD       A,(TIMFG)
+           CP       0F0h
+           JR       NZ,RTP8
+           EI
+RTP8:      POP      AF
+           RET
+
+RTP5:      PUSH     HL
+           PUSH     DE
+           PUSH     DE
+           LD       DE,MSG_CHKSUM_MZ2
+           CALL     MSGX
+           CALL     PRTHL
+           CALL     NL
+           LD       DE,MSG_CHKSUM_TP2
+           CALL     MSGX
+           POP      DE
+           EX       DE,HL
+           CALL     PRTHL
+           CALL     NL
+           POP      DE
+           POP      HL
+           ;
+           LD       D,1
+           DEC      D
+           JR       Z,RTP7
+           LD       H,D
+           CALL     GAPCK
+           JP       RTP1
+RTP7:      LD       A,1
+           JR       RTP9
+RTP6:      LD       A,2
+RTP9:      SCF
+           JR       RTP4
+
+
+           ;
+           ; EDGE
+           ;  BC = KEYPB
+           ;  DE = CSTR
+           ; EXIT CF = 0 : EDGE
+           ;         = 1 : BREAK
+           ;
+EDGE:      LD       A,0F0h
+           LD       (KEYPA),A
+           NOP
+EDG1:      LD       A,(BC)
+           AND      81h             ; SHIFT & BREAK
+           JP       NZ,EDG0
+           SCF
+           RET
+EDG0:      LD       A,(DE)
+           AND      20h
+           JP       NZ,EDG1
+EDG2:      LD       A,(BC)
+           AND      81h
+           JP       NZ,EDG3
+           SCF
+           RET
+EDG3:      LD       A,(DE)
+           AND      20h
+           JP       Z,EDG2
+           RET
+
+
+           ;
+           ; 1 BYTE READ
+           ;
+           ; EXIT  SUMDT=STORE
+           ; CF = 1 : BREAK
+           ;    = 0 : DATA=ACC
+           ;
+RBYTE:     PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           LD       HL,0800h
+           LD       BC,KEYPB
+           LD       DE,CSTR
+RBY1:      CALL     EDGE
+           JP       C,RBY3
+           CALL     DLY3
+           LD       A,(DE)
+           AND      20h
+           JP       Z,RBY2
+           PUSH     HL
+           LD       HL,(SUMDT)
+           INC      HL
+           LD       (SUMDT),HL
+           POP      HL
+           SCF
+RBY2:      LD       A,L
+           RLA
+           LD       L,A
+           DEC      H
+           JP       NZ,RBY1
+           CALL     EDGE
+           LD       A,L
+RBY3:      POP      HL
+           POP      DE
+           POP      BC
+           RET
+
+           ;
+           ; TAPE MARK DETECT
+           ;
+           ;    E=@L@     : INFORMATION
+           ;     =@S@     : DATA
+           ; EXIT CF = 0  : OK
+           ;         = 1  : BREAK
+           ;
+TMARK:     CALL     GAPCK
+           PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           PUSH     BC
+           PUSH     DE
+           LD       DE,MSG_TAPEMARK
+           CALL     MSG
+           CALL     NL
+           POP      DE
+           POP      BC
+           LD       HL,2828h
+           LD       A,E
+           CP       0CCh
+           JP       Z,TM0
+           LD       HL,1414h
+TM0:       LD       (TMCNT),HL
+           LD       BC,KEYPB
+           LD       DE,CSTR
+TM1:       LD       HL,(TMCNT)
+TM2:       CALL     EDGE
+           JP       C,TM4
+           CALL     DLY3
+           LD       A,(DE)
+           AND      20h
+           JP       Z,TM1
+           DEC      H
+           JP       NZ,TM2
+;  CALL     PRTHL
+TM3:       CALL     EDGE
+           JP       C,TM4
+           CALL     DLY3
+           LD       A,(DE)
+           AND      20h
+           JP       NZ,TM1
+           DEC      L
+           JP       NZ,TM3
+           CALL     EDGE
+RET3:
+TM4:       POP      HL
+           POP      DE
+           POP      BC
+           RET
+
+TM4A:      CALL     NL
+           CALL     PRTHL       ; Print HL as 4digit hex.
+           LD       A,0C4h      ; Move cursor left.
+TM4B:      CALL     DPCT
+           CALL     DPCT
+           CALL     DPCT
+           CALL     DPCT
+           CALL     NL
+           JP       GETL1
+
+           ;
+           ; MOTOR ON
+           ;
+           ;    D=@W@   : WRITE
+           ;     =@R@   : READ
+           ; EXIT CF=0  : OK
+           ;        =1  : BREAK
+MOTOR:     PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           PUSH     BC
+           PUSH     DE
+           LD       DE,MSG_MOTORTG
+           CALL     MSG
+           CALL     NL
+           POP      DE
+           POP      BC
+           LD       B,10
+MOT1:      LD       A,(CSTR)
+           AND      10h
+           JR       Z,MOT4
+MOT2:      LD       B,0A6h
+MOT3:      CALL     DLY12
+           DJNZ     MOT3
+           XOR      A
+MOT7:      JR       RET3
+MOT4:      LD       A,06h
+           LD       HL,CSTPT
+           LD       (HL),A
+           INC      A
+           LD       (HL),A
+           DJNZ     MOT1
+           CALL     NL
+           LD       A,D
+           CP       0D7h
+           JR       Z,MOT8
+           LD       DE,MSG1
+           JR       MOT9
+MOT8:      LD       DE,MSG3
+           CALL     MSGX
+           LD       DE,MSG2
+MOT9:      CALL     MSGX
+MOT5:      LD       A,(CSTR)
+           AND      10h
+           JR       NZ,MOT2
+           CALL     ?BRK
+           JR       NZ,MOT5
+           SCF
+           JR       MOT7
+
+           ;
+           ; MOTOR STOP
+           ;
+MSTOP:     PUSH     AF
+           PUSH     BC
+           PUSH     DE
+           PUSH     BC
+           PUSH     DE
+           LD       DE,MSG_MOTORSTP
+           CALL     MSG
+           CALL     NL
+           POP      DE
+           POP      BC
+           LD       B,10
+MST1:      LD       A,(CSTR)
+           AND      10H
+           JR       Z,MST3
+MST2:      LD       A,06h
+           LD       (CSTPT),A
+           INC      A
+           LD       (CSTPT),A
+           DJNZ     MST1
+MST3:      JP       ?RSTR1
+
+           ;
+           ; CHECK SUM
+           ;
+           ;   BC = SIZE
+           ;   HL = DATA ADR
+           ; EXIT SUMDT=STORE
+           ;      CSMDT=STORE
+           ;
+CKSUM:     PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           LD       DE,0
+CKS1:      LD       A,B
+           OR       C
+           JR       NZ,CKS2
+           EX       DE,HL
+           LD       (SUMDT),HL
+           LD       (CSMDT),HL
+           POP      HL
+           POP      DE
+           POP      BC
+           RET
+CKS2:      LD       A,(HL)
+           PUSH     BC
+           LD       B,+8
+CKS3:      RLCA
+           JR       NC,CKS4
+           INC      DE
+CKS4:       DJNZ     CKS3
+           POP      BC
+           INC      HL
+           DEC      BC
+           JR       CKS1
+
+
+           ;
+           ; 107 uS DELAY
+           ;
+DLY1:      LD       A,14
+DLY1A:     DEC      A
+           JP       NZ,DLY1A
+           RET
+
+           ;
+           ; 240 uS DELAY
+           ;
+DLY2:      LD       A,13
+DLY2A:     DEC      A
+           JP       NZ,DLY2A
+           RET
+
+           ;
+           ; 240 uS x 3 DELAY
+           ;
+DLY3:      NEG
+           NEG
+           LD       A,42
+           JP       DLY2A
+
+           ;
+           ; 12mS DELAY
+DLY12:     PUSH     BC
+           LD       B,35
+DLY12A:    CALL     DLY3
+           DJNZ     DLY12A
+           POP      BC
+           RET
+
+
+           ;
+           ; GAP * TAPEMARK
+           ;
+           ;  E = @L@   : LONG GAP
+           ;    = @S@   : SHORT GAP
+           ;
+GAP:       PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           LD       A,E
+           LD       BC,55F0h           ;Number of pulses for the Long Gap.
+           LD       DE,2828h           ;40 + 40 LTM
+           CP       0CCh
+           JP       Z,GAP0
+           LD       BC,2AF8h           ;Number of pulses for a Short Gap.
+           LD       DE,1414h           ;20 + 20 LTM
+GAP0:      PUSH     DE
+           LD       DE,MSG_WGAPS
+           CALL     MSG
+           ;
+GAP1:      CALL     SHORT              ;22000 short GAP pulses.
+           LD       H,B
+           LD       L,C
+           LD       A,000h
+           CP       L
+           JR       NZ,GAP1D
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           LD       A,0C4h             ; Move cursor left.
+           LD       E,004h             ; 4 times.
+GAP1B:     CALL     DPCT
+           DEC      E
+           JR       NZ,GAP1B
+GAP1D:     DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GAP1
+           LD       H,B
+           LD       L,C
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           LD       DE,MSG_SPC
+           CALL     MSG
+           CALL     LETNL
+           POP      DE
+           ;
+           LD       BC,20000            ; 2 Second delay
+GAP1C:     CALL     DLY1
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GAP1C
+           ;
+           PUSH     DE
+GAP1A:     LD       DE,MSG_WGAPL
+           CALL     MSGX
+           POP      DE
+GAP2:      PUSH     DE
+           CALL     LONG               ;40 or 20 Long Pulses (LTM or STM)
+           LD       H,00h
+           LD       L,D
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           LD       A,0C4h             ; Move cursor left.
+           LD       E,004h             ; 4 times.
+GAP2B:     CALL     DPCT
+           DEC      E
+           JR       NZ,GAP2B
+           LD       BC,1000           ; .1 Second delay
+GAP2D:     CALL     DLY1
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GAP2D
+           POP      DE
+           DEC      D
+           JR       NZ,GAP2
+           LD       H,000h
+           LD       L,D
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           PUSH     DE
+           LD       DE,MSG_SPC
+           CALL     MSG
+           CALL     LETNL
+           POP      DE
+           ;
+           LD       BC,20000           ; 2 Second delay
+GAP2C:     CALL     DLY1
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GAP2C
+           ;
+GAP2A:     PUSH     DE
+           LD       DE,MSG_WGAPS2
+           CALL     MSGX
+           POP      DE
+GAP3:      PUSH     DE
+           CALL     SHORT              ;40 or 20 Short Pulses (LTM or STM)
+           LD       H,00h
+           LD       L,E
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           LD       A,0C4h             ; Move cursor left.
+           LD       E,004h             ; 4 times.
+GAP3B:     CALL     DPCT
+           DEC      E
+           JR       NZ,GAP3B
+           LD       BC,1000            ; .1 Second delay
+GAP3D:     CALL     DLY1
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GAP3D
+           POP      DE
+           DEC      E
+           JR       NZ,GAP3
+           LD       H,000h
+           LD       L,E
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           PUSH     DE
+           LD       DE,MSG_SPC
+           CALL     MSGX
+           CALL     LETNL
+           POP      DE
+           ;
+           LD       BC,20000           ; 2 Second delay
+GAP3C:     CALL     DLY1
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,GAP3C
+           ;
+GAP3A:     PUSH     DE
+           LD       DE,MSG_WGAPL2
+           CALL     MSGX
+           CALL     LETNL
+           POP      DE
+           CALL     LONG               ;1 Long Pulse
+           POP      HL
+           POP      DE
+           POP      BC
+           RET
+
+           ;GAP Test - fixed 80 x short, 80 x long to see if hardware is receiving and counting correctly.
+           ;
+;GAP:       PUSH     BC
+;           PUSH     DE
+;GAP0:      LD       BC,050h          ;Number of pulses for the Long Gap.
+;GAP1:      CALL     SHORT              
+;GAP1A:     DEC      BC
+;           LD       A,B
+;           OR       C
+;           JR       NZ,GAP1
+;           LD       BC,0050h          ;Number of pulses for the Long Gap.
+;GAP2:      CALL     LONG              
+;GAP2A:     DEC      BC
+;           LD       A,B
+;           OR       C
+;           JR       NZ,GAP2
+;GAP3A:     JR       GAP3A
+;GAP3:      POP      DE
+;           POP      BC
+;           RET
+
+
+           ;
+           ; GAP CHECK
+           ;
+GAPCK:     PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           LD       DE,MSG_GAPCK
+           CALL     MSG
+           CALL     NL
+           LD       BC,KEYPB
+           LD       DE,CSTR
+GAPCK1:    LD       H,100
+GAPCK2:    CALL     EDGE
+           JR       C,GAPCK3
+           CALL     DLY3
+           LD       A,(DE)
+           AND      20h
+           JR       NZ,GAPCK1
+           DEC      H
+           JR       NZ,GAPCK2
+GAPCK3:    JP       RET3
+
+           ;
+           ; 1 bit write
+           ; Short Pulse
+           ;
+SHORT:     PUSH     AF
+           LD       A,03h
+           LD       (CSTPT),A
+           CALL     DLY1
+           CALL     DLY1
+           LD       A,02h
+           LD       (CSTPT),A
+           CALL     DLY1
+           CALL     DLY1
+           POP      AF
+           RET
+
+           ;
+           ; 1 bit write
+           ; Long Pulse
+           ;
+LONG:      PUSH     AF
+           LD       A,03h
+           LD       (CSTPT),A
+           CALL     DLY1
+           CALL     DLY1
+           CALL     DLY1
+           CALL     DLY1
+           LD       A,02h
+           LD       (CSTPT),A
+           CALL     DLY1
+           CALL     DLY1
+           CALL     DLY1
+           CALL     DLY2
+           POP      AF
+           RET
+
+
+           ;    WRITE INFORMATION
+
+QWRI:      DI      
+           PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       D,0D7H                                                   ; "W"
+           LD       E,0CCH                                                   ; "L"
+           LD       HL,IBUFE                                                 ; 10F0H
+           LD       BC,80H                                                   ; WRITE BYTE SIZE
+WRI1:      CALL     CKSUM                                                    ; CHECK SUM
+           CALL     MOTOR                                                    ; MOTOR ON
+           JR       C,WRI3
+           LD       A,E
+           CP       0CCH                                                     ; "L" - Long Gap/Tape Mark?
+           JR       NZ,WRI2
+           CALL     NL
+           PUSH     DE
+           LD       DE,MSGN7                                                 ; WRITING
+           RST      18H                                                      ; CALL MSGX
+           LD       DE,NAME                                                  ; FILE NAME
+           RST      18H                                                      ; CALL MSGX
+           CALL     NL
+           POP      DE
+WRI2:      CALL     GAP
+           CALL     WTAPE
+WRI3:      JP       RET2
+
+
+           ;    WRITE DATA
+           ;    EXIT CF=0 : OK
+           ;           =1 : BREAK
+
+QWRD:      DI      
+           PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       D,0D7H                                                   ; "W"
+           LD       E,53H                                                    ; "S"
+L047D:     LD       BC,(SIZE)                                                ; WRITE DATA BYTE SIZE
+           LD       HL,(DTADR)                                               ; WRITE DATA ADDRESS
+           LD       A,B
+           OR       C
+           JP       Z,RET1
+           JR       WRI1
+
+           ;    TAPE WRITE
+           ;    BC=BYTE SIZE
+           ;    HL=DATA LOW ADDRESS
+           ;    EXIT CF=0 : OK
+           ;           =1 : BREAK
+
+WTAPE:     PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       D,02H
+           LD       A,0F0H                                                   ; 88H WOULD BE BETTER!!
+           LD       (KEYPA),A                                                ; E000H
+WTAP1:     LD       A,(HL)
+           CALL     WBYTE                                                    ; 1 BYTE WRITE
+           LD       A,(KEYPB)                                                ; E001H
+           AND      81H                                                      ; SHIFT & BREAK
+           JP       NZ,WTAP2
+           LD       A,02H                                                    ; BREAK IN CODE
+           SCF     
+           JR       WTAP3
+
+WTAP2:     INC      HL
+           DEC      BC
+           LD       A,B
+           OR       C
+           JP       NZ,WTAP1
+           LD       HL,(SUMDT)                                               ; SUM DATA SET
+           LD       A,H
+           CALL     WBYTE                                                    ; Send Checksum
+           LD       A,L
+           CALL     WBYTE
+WTAP3A:    PUSH     DE
+           LD       DE,MSG_WGAPL2
+           CALL     MSGX
+           CALL     LETNL
+           POP      DE
+           CALL     LONG
+           DEC      D
+           JP       NZ,L04C2                                                 ; Another copy to be sent?
+           OR       A
+           JP       WTAP3
+
+L04C2:     PUSH     DE
+           LD       DE,MSG_SPCS
+           CALL     MSGX
+           POP      DE
+           LD       B,0                                                      ; Send 256 short pulses.
+
+L04C4:     CALL     SHORT
+           LD       H,00h
+           LD       L,B
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           LD       A,0C4h             ; Move cursor left.
+           LD       E,004h             ; 4 times.
+SPCS2:     CALL     DPCT
+           DEC      E
+           JR       NZ,SPCS2
+           DEC      B
+           JP       NZ,L04C4
+           LD       H,00h
+           LD       L,B
+           CALL     PRTHL              ; Print HL as 4digit hex.
+           LD       BC,2500            ; .25 Second delay
+SPCS3:     CALL     DLY1
+           DEC      BC
+           LD       A,B
+           OR       C
+           JR       NZ,SPCS3
+           CALL     LETNL
+           POP      HL                                                       ; Retrieve saved location and size
+           POP      BC
+           PUSH     BC
+           PUSH     HL
+           JP       WTAP1                                                    ; Repeat send.
+
+WTAP3:
+RET1:      POP      HL
+           POP      BC
+           POP      DE
+           RET     
+
+           DB       2FH
+           DB       4EH
+
+           ;    VERIFY (FROM $CMT)
+           ;    EXIT ACC=0 : OK CF=0
+           ;            =1 : ER CF=1
+           ;            =2 : BREAK CF=1
+
+QVRFY:     DI      
+           PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       BC,(SIZE)
+           LD       HL,(DTADR)
+           LD       D,0D2H                                                   ; "R"
+           LD       E,53H                                                    ; "S"
+           LD       A,B
+           OR       C
+           JP       Z,RTP4                                                   ; END
+           CALL     CKSUM
+           CALL     MOTOR
+           JP       C,RTP6                                                   ; BRK
+           CALL     TMARK                                                    ; TAPE MARK DETECT
+           JP       C,RTP6                                                   ; BRK
+           CALL     TVRFY
+           JP       RTP4
+
+           ;    DATA VERIFY
+           ;    BC=SIZE
+           ;    HL=DATA LOW ADDRESS
+           ;    CSMDT=CHECK SUM
+           ;    EXIT ACC=0 : OK  CF=0
+           ;            =1 : ER    =1
+           ;            =2 : BREAK =1
+
+TVRFY:     PUSH     DE
+           PUSH     BC
+           PUSH     HL
+           LD       H,02H                                                    ; COMPARE TWICE
+TVF1:      LD       BC,KEYPB
+           LD       DE,CSTR
+TVF2:      CALL     EDGE
+           JP       C,RTP6                                                   ; BRK
+           CALL     DLY3                                                     ; CALL DLY2*3
+           LD       A,(DE)
+           AND      20H
+           JP       Z,TVF2
+           LD       D,H
+           POP      HL
+           POP      BC
+           PUSH     BC
+           PUSH     HL
+           ;    COMPARE TAPE DATA AND STORAGE
+TVF3:      CALL     RBYTE
+           JP       C,RTP6                                                   ; BRK
+           CP       (HL)
+           JP       NZ,RTP7                                                  ; ERROR, NOT EQUAL
+           INC      HL                                                       ; STORAGE ADDRESS + 1
+           DEC      BC                                                       ; SIZE - 1
+           LD       A,B
+           OR       C
+           JR       NZ,TVF3
+           ;    COMPARE CHECK SUM (1199H/CSMDT) AND TAPE
+           LD       HL,(CSMDT)
+           CALL     RBYTE
+           CP       H
+           JP       NZ,RTP7                                                  ; ERROR, NOT EQUAL
+           CALL     RBYTE
+           CP       L
+           JP       NZ,RTP7                                                  ; ERROR, NOT EQUAL
+           DEC      D                                                        ; NUMBER OF COMPARES (2) - 1
+           JP       Z,RTP8                                                   ; OK, 2 COMPARES
+           LD       H,D                                                      ; (-->05C7H), SAVE NUMBER OF COMPARES
+           JR       TVF1                                                     ; NEXT COMPARE
+
+           ;    1 BYTE WRITE
+
+WBYTE:     PUSH     BC
+           LD       B,8
+           CALL     LONG
+WBY1:      RLCA    
+           CALL     C,LONG
+           CALL     NC,SHORT
+           DEC      B
+           JP       NZ,WBY1
+           POP      BC
+           RET     
+
+ARARA:     POP      HL
+           JP       ABCD
+
+DLY1S:     PUSH     AF
+           PUSH     BC
+           LD       C,10
+L0324:     CALL     DLY12
+           DEC      C
+           JR       NZ,L0324
+           POP      BC
+           POP      AF
+           RET
+
+           ; Test the 8253 Timer, configure it as per the monitor and display the read back values.
+TIMERTST:  CALL     NL
+           LD       DE,MSG_TIMERTST
+           CALL     MSG
+           CALL     NL
+           LD       DE,MSG_TIMERVAL
+           CALL     MSG
+           LD       A,01h
+           LD       DE,8000h
+           CALL     ?TMST
+NDE:       JP       NDE
+           JP       GETL1
+?TMST:     DI      
+           PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           LD       (AMPM),A
+           LD       A,0F0H
+           LD       (TIMFG),A
+ABCD:      LD       HL,0A8C0H
+           XOR      A
+           SBC      HL,DE
+           PUSH     HL
+           INC      HL
+           EX       DE,HL
+
+           LD       HL,CONTF    ; Control Register
+           LD       (HL),0B0H   ; 10110000 Control Counter 2 10, Write 2 bytes 11, 000 Interrupt on Terminal Count, 0 16 bit binary
+           LD       (HL),074H   ; 01110100 Control Counter 1 01, Write 2 bytes 11, 010 Rate Generator, 0 16 bit binary
+           LD       (HL),030H   ; 00110100 Control Counter 1 01, Write 2 bytes 11, 010 interrupt on Terminal Count, 0 16 bit binary
+
+           LD       HL,CONT2    ; Counter 2
+           LD       (HL),E
+           LD       (HL),D
+
+           LD       HL,CONT1    ; Counter 1
+           LD       (HL),00AH
+           LD       (HL),000H
+
+           LD       HL,CONT0    ; Counter 0
+           LD       (HL),00CH
+           LD       (HL),0C0H
+
+;           LD       HL,CONT2    ; Counter 2
+;           LD       C,(HL)
+;           LD       A,(HL)
+;           CP       D
+;           JP       NZ,L0323                
+;           LD       A,C
+;           CP       E
+;           JP       Z,CDEF                
+           ;
+
+L0323:     PUSH     AF
+           PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           ;
+           LD       HL,CONTF    ; Control Register
+           LD       (HL),080H
+           LD       HL,CONT2    ; Counter 2
+           LD       C,(HL)
+           LD       A,(HL)
+           CALL     PRTHX
+           LD       A,C
+           CALL     PRTHX
+           ;
+           CALL     PRNTS
+           ;CALL     DLY1S
+           ;
+           LD       HL,CONTF    ; Control Register
+           LD       (HL),040H
+           LD       HL,CONT1    ; Counter 1
+           LD       C,(HL)
+           LD       A,(HL)
+           CALL     PRTHX
+           LD       A,C
+           CALL     PRTHX
+           ;
+           CALL     PRNTS
+           ;CALL     DLY1S
+           ;
+           LD       HL,CONTF    ; Control Register
+           LD       (HL),000H
+           LD       HL,CONT0    ; Counter 0
+           LD       C,(HL)
+           LD       A,(HL)
+           CALL     PRTHX
+           LD       A,C
+           CALL     PRTHX
+           ;
+           ;CALL     DLY1S
+           ;
+           LD       A,0C4h      ; Move cursor left.
+           LD       E,0Eh      ; 4 times.
+L0330:     CALL     DPCT
+           DEC      E
+           JR       NZ,L0330
+           ;
+;           LD       C,20
+;L0324:     CALL     DLY12
+;           DEC      C
+;           JR       NZ,L0324
+           ;
+           POP      HL
+           POP      DE
+           POP      BC
+           POP      AF
+           ;
+           LD       HL,CONT2    ; Counter 2
+           LD       C,(HL)
+           LD       A,(HL)
+           CP       D
+           JP       NZ,L0323                
+           LD       A,C
+           CP       E
+           JP       NZ,L0323                
+           ;
+           ;
+           PUSH     AF
+           PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           CALL     NL
+           CALL     NL
+           CALL     NL
+           LD       DE,MSG_TIMERVAL2
+           CALL     MSG
+           POP      HL
+           POP      DE
+           POP      BC
+           POP      AF
+
+           ;
+CDEF:      POP      DE
+           LD       HL,CONT1
+           LD       (HL),00CH
+           LD       (HL),07BH
+           INC      HL
+
+L0336:     PUSH     AF
+           PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           ;
+           LD       HL,CONTF    ; Control Register
+           LD       (HL),080H
+           LD       HL,CONT2    ; Counter 2
+           LD       C,(HL)
+           LD       A,(HL)
+           CALL     PRTHX
+           LD       A,C
+           CALL     PRTHX
+           ;
+           CALL     PRNTS
+           CALL     DLY1S
+           ;
+           LD       HL,CONTF    ; Control Register
+           LD       (HL),040H
+           LD       HL,CONT1    ; Counter 1
+           LD       C,(HL)
+           LD       A,(HL)
+           CALL     PRTHX
+           LD       A,C
+           CALL     PRTHX
+           ;
+           CALL     PRNTS
+           CALL     DLY1S
+           ;
+           LD       HL,CONTF    ; Control Register
+           LD       (HL),000H
+           LD       HL,CONT0    ; Counter 0
+           LD       C,(HL)
+           LD       A,(HL)
+           CALL     PRTHX
+           LD       A,C
+           CALL     PRTHX
+           ;
+           CALL     DLY1S
+           ;
+           LD       A,0C4h      ; Move cursor left.
+           LD       E,0Eh      ; 4 times.
+L0340:     CALL     DPCT
+           DEC      E
+           JR       NZ,L0340
+           ;
+           POP      HL
+           POP      DE
+           POP      BC
+           POP      AF
+
+           LD       HL,CONT2    ; Counter 2
+           LD       C,(HL)
+           LD       A,(HL)
+           CP       D
+           JR       NZ,L0336                
+           LD       A,C
+           CP       E
+           JR       NZ,L0336                
+           CALL     NL
+           LD       DE,MSG_TIMERVAL3
+           CALL     MSG
+           POP      HL
+           POP      DE
+           POP      BC
+           EI      
+           RET     
+
+?TMRD:     PUSH     HL
+           LD       HL,CONTF
+           LD       (HL),080H
+           DEC      HL
+           DI      
+           LD       E,(HL)
+           LD       D,(HL)
+           EI      
+           LD       A,E
+           OR       D
+           JR       Z,?TMR1                 
+           XOR      A
+           LD       HL,0A8C0H
+           SBC      HL,DE
+           JR       C,?TMR2                 
+           EX       DE,HL
+           LD       A,(AMPM)
+           POP      HL
+           RET     
+
+?TMR1:     LD       DE,0A8C0H
+?TMR1A:    LD       A,(AMPM)
+           XOR      001H
+           POP      HL
+           RET     
+
+?TMR2:     DI      
+           LD       HL,CONT2
+           LD       A,(HL)
+           CPL      
+           LD       E,A
+           LD       A,(HL)
+           CPL      
+           LD       D,A
+           EI      
+           INC      DE
+           JR       ?TMR1A     
+
+TIMIN:     PUSH     AF
+           PUSH     BC
+           PUSH     DE
+           PUSH     HL
+           LD       HL,AMPM
+           LD       A,(HL)
+           XOR      001H
+           LD       (HL),A
+           LD       HL,CONTF
+           LD       (HL),080H
+           DEC      HL
+           PUSH     HL
+           LD       E,(HL)
+           LD       D,(HL)
+           LD       HL,0A8C0H
+           ADD      HL,DE
+           DEC      HL
+           DEC      HL
+           EX       DE,HL
+           POP      HL
+           LD       (HL),E
+           LD       (HL),D
+           POP      HL
+           POP      DE
+           POP      BC
+           POP      AF
+           EI      
+           RET
+
+           ; Help/Synoposis of commands available.
+           ;
+HELP:      CALL     LETNL
+           LD       DE,MSG_HELP1
+           CALL     MSG
+           CALL     LETNL
+           LD       DE,MSG_HELP2
+           CALL     MSG
+           CALL     LETNL
+           LD       DE,MSG_HELP3
+           CALL     MSG
+           CALL     LETNL
+           LD       DE,MSG_HELP4
+           CALL     MSG
+           CALL     LETNL
+           LD       DE,MSG_HELP5
+           CALL     MSG
+           CALL     LETNL
+           LD       DE,MSG_HELP6
+           CALL     MSG
+           CALL     LETNL
+           CALL     LETNL
+           JP       GETL1
+
+MSG_HELP1: DB       "COMMANDS: G TEST GRAPHICS",   0Dh, 00h
+MSG_HELP2: DB       "          M TEST MEMORY",     0Dh, 00h
+MSG_HELP3: DB       "          R LOAD TAPE",       0Dh, 00h
+MSG_HELP4: DB       "          T TIMER TEST",      0Dh, 00h
+MSG_HELP5: DB       "          W WRITE TEST TAPE", 0Dh, 00h
+MSG_HELP6: DB       "          Q QUIT TO MONITOR", 0Dh, 00h
+
+TITLE:     DB       "SHARPMZ TESTER (C) P.SMART 2018", 0Dh, 00h
+MSG_INITGR:DB       "INIT GRAPHICS", 0Dh
+MSG_INITM: DB       "INIT MEMORY", 0Dh
+TITLE_SAVE:DB       "WRITE TEST TAPE", 0Dh
+            
+MSG1:      DW       207Fh
+MSG2:      DB       "PLAY", 0Dh, 00h
+MSG3:      DW       207Fh                     ; PRESS RECORD
+           DB       "RECORD.", 0Dh, 00h
+MSGN7:     DB       "WRITING ", 0Dh, 00h
+MSGOK:     DB       "OK", 0Dh, 00h
+MSG_ERRCHKSUM:
+           DB       "CHECKSUM ERROR", 0Dh
+MSG_ERRWRITE:
+           DB       "WRITE ERROR", 0Dh
+
+MSG_READTAPE:
+           DB       "READ TAPE", 0Dh, 00h
+MSG_TAPEMARK:
+           DB       "TAPEMARK", 0Dh, 00h
+MSG_MOTORTG:
+           DB       "MOTOR TOGGLE", 0Dh, 00h
+MSG_MOTORSTP:
+           DB       "MOTOR STOP", 0Dh, 00h
+MSG_TPMARK:
+           DB       "TAPE MARK START", 0Dh, 00h
+MSG_GAPCK:
+           DB       "GAP CHECK", 0Dh, 00h
+MSG_LOADFILE:
+           DB       "LOAD FILE          = ",0Dh, 00h
+MSG_LOADFROM:
+           DB       "LOAD ADDRESS       = ", 0Dh, 00h
+MSG_LOADEXEC:
+           DB       "EXEC ADDRESS       = ", 0Dh, 00h
+MSG_LOADSIZE:
+           DB       "LOAD SIZE          = ", 0Dh, 00h
+MSG_SAVEFILE:
+           DB       "SAVE FILE          = ",0Dh, 00h
+MSG_SAVEFROM:
+           DB       "SAVE ADDRESS       = ", 0Dh, 00h
+MSG_SAVEEXEC:
+           DB       "SAVE EXEC ADDRESS  = ", 0Dh, 00h
+MSG_SAVESIZE:
+           DB       "SAVE SIZE          = ", 0Dh, 00h
+MSG_CHKSUM_MZ1:
+           DB       "  MZ CHECKSUM (OK) = ", 0Dh, 00h
+MSG_CHKSUM_TP1:
+           DB       "TAPE CHECKSUM (OK) = ", 0Dh, 00h
+MSG_CHKSUM_MZ2:
+           DB       "  MZ CHECKSUM (ER) = ", 0Dh, 00h
+MSG_CHKSUM_TP2:
+           DB       "TAPE CHECKSUM (ER) = ", 0Dh, 00h
+MSG_WHDR:  DB       "WRITE HEADER...", 0Dh
+MSG_WDATA: DB       "WRITE DATA...", 0Dh
+MSGGAP:    DB       "GAP WRITTEN", 0Dh, 00h
+MSG_WGAPS: DB       "WRITE GAP: ", 0Dh, 00h
+MSG_WGAPS2:DB       "WRITE TM SHORT: ", 0Dh, 00h
+MSG_WGAPL: DB       "WRITE TM LONG: ", 0Dh, 00h
+MSG_WGAPL2:DB       "WRITE 1 LONG BIT", 0Dh, 00h
+MSG_SPCS:  DB       "WRITE 256 SHORT: ", 0Dh, 00h
+MSG_SPC:   DB       ", WAIT.", 0Dh, 00h
+MSGTAPE    DB       "HEADER WRITTEN", 0Dh, 00h
+MSG_TIMERTST:
+           DB      "8253 TIMER TEST", 0Dh, 00h
+MSG_TIMERVAL:
+           DB      "READ VALUE 1: ", 0Dh, 00h
+MSG_TIMERVAL2:
+           DB      "READ VALUE 2: ", 0Dh, 00h
+MSG_TIMERVAL3:
+           DB      "READ DONE.", 0Dh, 00h
+
+OKCHECK:   DB      ", CHECK: ", 0Dh
+OKMSG:     DB      " OK.", 0Dh
+DONEMSG:   DB      11h
+           DB      "RAM TEST COMPLETE.", 0Dh
+
+BITMSG:    DB      " BIT:  ", 0Dh
+BANKMSG:   DB      " BANK: ", 0Dh
+
+GRPHPOS:   DB      00h, 00h
+
+           ; Test tape image to save.
+TESTBUF:                                                                 ; TAPE BUFFER (128 BYTES)
+TATRB:     DB       02h                                                  ; Code Type, 01 = Machine Code.
+TNAME:     DB       "TEST TAPE SAVE", 0Dh, 00h, 00h                      ; Title/Name (17 bytes).
+TSIZE:     DW       TESTEND - TESTSTART                                  ; Size of program.
+TDTADR:    DW       TESTSTART                                            ; Load address of program.
+TEXADR:    DW       TESTSTART                                            ; Exec address of program.
+TCOMNT:    DB       "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz"
+
+TESTSTART: DB       01h
+           DB       0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+           DB       16,17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+           DB       32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47
+           DB       48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63
+           DB       64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79
+           DB       80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95
+           DB       96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111
+           DB       112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127
+           DB       128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143
+           DB       144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159
+           DB       160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175
+           DB       176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
+           DB       192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207
+           DB       208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223
+           DB       224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239
+           DB       240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255 
+TESTEND:
+
+MEND:
diff --git a/software/asm/sharpmz-test.obj b/software/asm/sharpmz-test.obj
new file mode 100644
index 0000000..826d0ba
Binary files /dev/null and b/software/asm/sharpmz-test.obj differ
diff --git a/software/asm/sharpmz-test.sym b/software/asm/sharpmz-test.sym
new file mode 100644
index 0000000..5991419
--- /dev/null
+++ b/software/asm/sharpmz-test.sym
@@ -0,0 +1,252 @@
+?ER: equ 0C1ACH
+?RDD: equ 0C1E5H
+?RDI: equ 0C1BAH
+?TMR1: equ 0C854H
+?TMR1A: equ 0C857H
+?TMR2: equ 0C85EH
+?TMRD: equ 0C837H
+?TMST: equ 0C71FH
+ABCD: equ 0C72BH
+AMPM: equ 119BH
+ARARA: equ 0C6EEH
+ATRB: equ 10F0H
+BANKMSG: equ 0CC53H
+BITMSG: equ 0CC4BH
+BUFER: equ 11A3H
+CDEF: equ 0C7C0H
+CKS1: equ 0C406H
+CKS2: equ 0C415H
+CKS3: equ 0C419H
+CKS4: equ 0C41DH
+CKSUM: equ 0C400H
+CLEAR1: equ 0BFB7H
+COMNT: equ 1108H
+CSMDT: equ 1199H
+DLY1: equ 0C424H
+DLY12: equ 0C43BH
+DLY12A: equ 0C43EH
+DLY1A: equ 0C426H
+DLY1S: equ 0C6F2H
+DLY2: equ 0C42BH
+DLY2A: equ 0C42DH
+DLY3: equ 0C432H
+DONEMSG: equ 0CC37H
+DPRNT: equ 1194H
+DSPXY: equ 1171H
+DTADR: equ 1104H
+EDG0: equ 0C2C9H
+EDG1: equ 0C2C1H
+EDG2: equ 0C2CFH
+EDG3: equ 0C2D7H
+EDGE: equ 0C2BBH
+EXADR: equ 1106H
+FLASH: equ 118EH
+FLPST: equ 118FH
+FLSDT: equ 1192H
+FLSST: equ 1191H
+GAP: equ 0C445H
+GAP0: equ 0C45AH
+GAP1: equ 0C461H
+GAP1A: equ 0C498H
+GAP1B: equ 0C472H
+GAP1C: equ 0C48FH
+GAP1D: equ 0C478H
+GAP2: equ 0C49FH
+GAP2A: equ 0C4DEH
+GAP2B: equ 0C4ADH
+GAP2C: equ 0C4D6H
+GAP2D: equ 0C4B6H
+GAP3: equ 0C4E6H
+GAP3A: equ 0C525H
+GAP3B: equ 0C4F4H
+GAP3C: equ 0C51DH
+GAP3D: equ 0C4FDH
+GAPCK: equ 0C537H
+GAPCK1: equ 0C549H
+GAPCK2: equ 0C54BH
+GAPCK3: equ 0C55BH
+GETL1: equ 0BFC1H
+GETL2: equ 0BFCFH
+GRAM0: equ 0BF07H
+GRAM1: equ 0BF0DH
+GRAMINIT: equ 0BF03H
+GRAMTEST: equ 0BF19H
+GRAMTEST0: equ 0BF1FH
+GRAMTEST1: equ 0BF25H
+GRAPHICS: equ 0BF36H
+GRPHIND: equ 0BF5CH
+GRPHPOS: equ 0CC5BH
+HELP: equ 0C890H
+IBUFE: equ 10F0H
+INITGRPH: equ 0BF7AH
+INITMEM: equ 0BFA8H
+KANAF: equ 1170H
+L0323: equ 0C750H
+L0324: equ 0C6F6H
+L0330: equ 0C791H
+L0336: equ 0C7C9H
+L0340: equ 0C813H
+L047D: equ 0C5D8H
+L04C2: equ 0C629H
+L04C4: equ 0C633H
+LOA0: equ 0C0CDH
+LOAD: equ 0C0C7H
+LONG: equ 0C577H
+LOOP: equ 0BFFBH
+LOOP1: equ 0C000H
+LOOP10: equ 0C0C0H
+LOOP11: equ 0C0C2H
+LOOP1a: equ 0C00CH
+LOOP1b: equ 0C012H
+LOOP2: equ 0C023H
+LOOP3: equ 0C041H
+LOOP4: equ 0C066H
+LOOP5: equ 0C06DH
+LOOP6: equ 0C07FH
+LOOP7: equ 0C090H
+LOOP8: equ 0C098H
+LOOP9: equ 0C0B8H
+MANG: equ 1173H
+MEMTEST: equ 0BFF9H
+MEND: equ 0CDDEH
+MOT1: equ 0C396H
+MOT2: equ 0C39DH
+MOT3: equ 0C39FH
+MOT4: equ 0C3A7H
+MOT5: equ 0C3CAH
+MOT7: equ 0C3A5H
+MOT8: equ 0C3BEH
+MOT9: equ 0C3C7H
+MOTOR: equ 0C384H
+MSG1: equ 0C9B7H
+MSG2: equ 0C9B9H
+MSG3: equ 0C9BFH
+MSGGAP: equ 0CB70H
+MSGN7: equ 0C9CAH
+MSGOK: equ 0C9D4H
+MSGTAPE: equ 0CBDBH
+MSG_CHKSUM_MZ1: equ 0CAF6H
+MSG_CHKSUM_MZ2: equ 0CB24H
+MSG_CHKSUM_TP1: equ 0CB0DH
+MSG_CHKSUM_TP2: equ 0CB3BH
+MSG_ERRCHKSUM: equ 0C9D8H
+MSG_ERRWRITE: equ 0C9E7H
+MSG_GAPCK: equ 0CA33H
+MSG_HELP1: equ 0C8CFH
+MSG_HELP2: equ 0C8EAH
+MSG_HELP3: equ 0C903H
+MSG_HELP4: equ 0C91AH
+MSG_HELP5: equ 0C932H
+MSG_HELP6: equ 0C94FH
+MSG_INITGR: equ 0C98DH
+MSG_INITM: equ 0C99BH
+MSG_LOADEXEC: equ 0CA6CH
+MSG_LOADFILE: equ 0CA3EH
+MSG_LOADFROM: equ 0CA55H
+MSG_LOADSIZE: equ 0CA83H
+MSG_MOTORSTP: equ 0CA16H
+MSG_MOTORTG: equ 0CA08H
+MSG_READTAPE: equ 0C9F3H
+MSG_SAVEEXEC: equ 0CAC8H
+MSG_SAVEFILE: equ 0CA9AH
+MSG_SAVEFROM: equ 0CAB1H
+MSG_SAVESIZE: equ 0CADFH
+MSG_SPC: equ 0CBD2H
+MSG_SPCS: equ 0CBBFH
+MSG_TAPEMARK: equ 0C9FEH
+MSG_TIMERTST: equ 0CBEBH
+MSG_TIMERVAL: equ 0CBFCH
+MSG_TIMERVAL2: equ 0CC0CH
+MSG_TIMERVAL3: equ 0CC1CH
+MSG_TPMARK: equ 0CA22H
+MSG_WDATA: equ 0CB62H
+MSG_WGAPL: equ 0CB9CH
+MSG_WGAPL2: equ 0CBADH
+MSG_WGAPS: equ 0CB7DH
+MSG_WGAPS2: equ 0CB8AH
+MSG_WHDR: equ 0CB52H
+MST1: equ 0C3EBH
+MST2: equ 0C3F2H
+MST3: equ 0C3FDH
+MSTOP: equ 0C3D9H
+NAME: equ 10F1H
+NDE: equ 0C719H
+OCTV: equ 11A0H
+OKCHECK: equ 0CC28H
+OKMSG: equ 0CC32H
+ONTYO: equ 119FH
+QER: equ 0C19EH
+QVRFY: equ 0C66BH
+QWRD: equ 0C5D0H
+QWRI: equ 0C59CH
+RATIO: equ 11A1H
+RBY1: equ 0C2EAH
+RBY2: equ 0C303H
+RBY3: equ 0C30EH
+RBYTE: equ 0C2DEH
+RD1: equ 0C1C8H
+RD2: equ 0C1E3H
+RDD1: equ 0C1FBH
+RDD2: equ 0C207H
+RET1: equ 0C665H
+RET2: equ 0C276H
+RET3: equ 0C366H
+RTAPE: equ 0C209H
+RTP0: equ 0C256H
+RTP1: equ 0C20EH
+RTP2: equ 0C214H
+RTP3: equ 0C22EH
+RTP4: equ 0C276H
+RTP5: equ 0C287H
+RTP6: equ 0C2B6H
+RTP7: equ 0C2B2H
+RTP8: equ 0C285H
+RTP9: equ 0C2B8H
+SAVE: equ 0C11CH
+SHORT: equ 0C55EH
+SIZE: equ 1102H
+SPCS2: equ 0C640H
+SPCS3: equ 0C653H
+SPV: equ 10F0H
+START: equ 0BF6BH
+STRGF: equ 1193H
+SUMDT: equ 1197H
+SWRK: equ 119DH
+TATRB: equ 0CC5DH
+TCOMNT: equ 0CC75H
+TDTADR: equ 0CC71H
+TEMPW: equ 119EH
+TESTBUF: equ 0CC5DH
+TESTEND: equ 0CDDEH
+TESTSTART: equ 0CCDDH
+TEXADR: equ 0CC73H
+TIMERTST: equ 0C6FFH
+TIMFG: equ 119CH
+TIMIN: equ 0C86CH
+TITLE: equ 0C96CH
+TITLE_SAVE: equ 0C9A7H
+TM0: equ 0C331H
+TM1: equ 0C33AH
+TM2: equ 0C33DH
+TM3: equ 0C350H
+TM4: equ 0C366H
+TM4A: equ 0C36AH
+TM4B: equ 0C372H
+TMARK: equ 0C312H
+TMCNT: equ 1195H
+TNAME: equ 0CC5EH
+TSIZE: equ 0CC6FH
+TVF1: equ 0C699H
+TVF2: equ 0C69FH
+TVF3: equ 0C6B3H
+TVRFY: equ 0C694H
+WBY1: equ 0C6E1H
+WBYTE: equ 0C6DBH
+WRI1: equ 0C5AAH
+WRI2: equ 0C5C7H
+WRI3: equ 0C5CDH
+WTAP1: equ 0C5F0H
+WTAP2: equ 0C601H
+WTAP3: equ 0C665H
+WTAP3A: equ 0C613H
+WTAPE: equ 0C5E6H
diff --git a/software/asm/tapecheck.obj b/software/asm/tapecheck.obj
new file mode 100644
index 0000000..52b8e7f
Binary files /dev/null and b/software/asm/tapecheck.obj differ
diff --git a/software/asm/tapecheck.sym b/software/asm/tapecheck.sym
new file mode 100644
index 0000000..82ac031
--- /dev/null
+++ b/software/asm/tapecheck.sym
@@ -0,0 +1,192 @@
+?ER: equ 0C23BH
+?RDD: equ 0C274H
+?RDI: equ 0C249H
+AMPM: equ 119BH
+ATRB: equ 10F0H
+BANKMSG: equ 0C888H
+BITMSG: equ 0C880H
+BUFER: equ 11A3H
+CKS1: equ 0C495H
+CKS2: equ 0C4A4H
+CKS3: equ 0C4A8H
+CKS4: equ 0C4ACH
+CKSUM: equ 0C48FH
+CLEAR1: equ 0C043H
+COMNT: equ 1108H
+CSMDT: equ 1199H
+DLY1: equ 0C4B3H
+DLY12: equ 0C4CAH
+DLY12A: equ 0C4CDH
+DLY1A: equ 0C4B5H
+DLY2: equ 0C4BAH
+DLY2A: equ 0C4BCH
+DLY3: equ 0C4C1H
+DONEMSG: equ 0C86CH
+DPRNT: equ 1194H
+DSPXY: equ 1171H
+DTADR: equ 1104H
+EDG0: equ 0C358H
+EDG1: equ 0C350H
+EDG2: equ 0C35EH
+EDG3: equ 0C366H
+EDGE: equ 0C34AH
+EXADR: equ 1106H
+FLASH: equ 118EH
+FLPST: equ 118FH
+FLSDT: equ 1192H
+FLSST: equ 1191H
+GAP: equ 0C4D4H
+GAP1: equ 0C4E8H
+GAP1A: equ 0C4EBH
+GAP2: equ 0C4F0H
+GAP3: equ 0C4F6H
+GAPCK: equ 0C502H
+GAPCK1: equ 0C514H
+GAPCK2: equ 0C516H
+GAPCK3: equ 0C526H
+GETL1: equ 0C04DH
+GETL2: equ 0C05BH
+GRAM0: equ 0C07CH
+GRAM1: equ 0C080H
+GRAMINIT: equ 0C076H
+GRPHPOS: equ 0C890H
+IBUFE: equ 10F0H
+INITGRPH: equ 0C018H
+INITMEM: equ 0C03DH
+KANAF: equ 1170H
+L047D: equ 0C5A3H
+L04C2: equ 0C5E8H
+L04C4: equ 0C5EAH
+LOA0: equ 0C16BH
+LOAD: equ 0C165H
+LONG: equ 0C542H
+LOOP: equ 0C08EH
+LOOP1: equ 0C093H
+LOOP10: equ 0C15EH
+LOOP11: equ 0C160H
+LOOP1a: equ 0C09FH
+LOOP1b: equ 0C0A5H
+LOOP2: equ 0C0B6H
+LOOP3: equ 0C0D4H
+LOOP4: equ 0C104H
+LOOP5: equ 0C10BH
+LOOP6: equ 0C11DH
+LOOP7: equ 0C12EH
+LOOP8: equ 0C136H
+LOOP9: equ 0C156H
+MANG: equ 1173H
+MEMTEST: equ 0C08CH
+MEND: equ 0CA13H
+MOT1: equ 0C425H
+MOT2: equ 0C42CH
+MOT3: equ 0C42EH
+MOT4: equ 0C436H
+MOT5: equ 0C459H
+MOT7: equ 0C434H
+MOT8: equ 0C44DH
+MOT9: equ 0C456H
+MOTOR: equ 0C413H
+MSG1: equ 0C681H
+MSG2: equ 0C683H
+MSG3: equ 0C689H
+MSGN7: equ 0C694H
+MSGOK: equ 0C69EH
+MSG_CHKSUM_MZ1: equ 0C7C0H
+MSG_CHKSUM_MZ2: equ 0C7EEH
+MSG_CHKSUM_TP1: equ 0C7D7H
+MSG_CHKSUM_TP2: equ 0C805H
+MSG_ERRCHKSUM: equ 0C6A2H
+MSG_ERRWRITE: equ 0C6B1H
+MSG_GAPCK: equ 0C6FDH
+MSG_HELP: equ 0C83EH
+MSG_LOADEXEC: equ 0C736H
+MSG_LOADFILE: equ 0C708H
+MSG_LOADFROM: equ 0C71FH
+MSG_LOADSIZE: equ 0C74DH
+MSG_MOTORSTP: equ 0C6E0H
+MSG_MOTORTG: equ 0C6D2H
+MSG_READTAPE: equ 0C6BDH
+MSG_SAVEEXEC: equ 0C792H
+MSG_SAVEFILE: equ 0C764H
+MSG_SAVEFROM: equ 0C77BH
+MSG_SAVESIZE: equ 0C7A9H
+MSG_TAPEMARK: equ 0C6C8H
+MSG_TPMARK: equ 0C6ECH
+MST1: equ 0C47AH
+MST2: equ 0C481H
+MST3: equ 0C48CH
+MSTOP: equ 0C468H
+NAME: equ 10F1H
+OCTV: equ 11A0H
+OKCHECK: equ 0C85DH
+OKMSG: equ 0C867H
+ONTYO: equ 119FH
+QER: equ 0C22DH
+QVRFY: equ 0C5FEH
+QWRD: equ 0C59BH
+QWRI: equ 0C567H
+RATIO: equ 11A1H
+RBY1: equ 0C379H
+RBY2: equ 0C392H
+RBY3: equ 0C39DH
+RBYTE: equ 0C36DH
+RD1: equ 0C257H
+RD2: equ 0C272H
+RDD1: equ 0C28AH
+RDD2: equ 0C296H
+RET1: equ 0C5F8H
+RET2: equ 0C305H
+RET3: equ 0C3F5H
+RTAPE: equ 0C298H
+RTP0: equ 0C2E5H
+RTP1: equ 0C29DH
+RTP2: equ 0C2A3H
+RTP3: equ 0C2BDH
+RTP4: equ 0C305H
+RTP5: equ 0C316H
+RTP6: equ 0C345H
+RTP7: equ 0C341H
+RTP8: equ 0C314H
+RTP9: equ 0C347H
+SAVE: equ 0C1BAH
+SHORT: equ 0C529H
+SIZE: equ 1102H
+SPV: equ 10F0H
+START: equ 0C000H
+STRGF: equ 1193H
+SUMDT: equ 1197H
+SWRK: equ 119DH
+TATRB: equ 0C892H
+TCOMNT: equ 0C8AAH
+TDTADR: equ 0C8A6H
+TEMPW: equ 119EH
+TESTBUF: equ 0C892H
+TESTEND: equ 0CA13H
+TESTSTART: equ 0C912H
+TEXADR: equ 0C8A8H
+TIMFG: equ 119CH
+TITLE: equ 0C81CH
+TM0: equ 0C3C0H
+TM1: equ 0C3C9H
+TM2: equ 0C3CCH
+TM3: equ 0C3DFH
+TM4: equ 0C3F5H
+TM4A: equ 0C3F9H
+TM4B: equ 0C401H
+TMARK: equ 0C3A1H
+TMCNT: equ 1195H
+TNAME: equ 0C893H
+TSIZE: equ 0C8A4H
+TVF1: equ 0C62CH
+TVF2: equ 0C632H
+TVF3: equ 0C646H
+TVRFY: equ 0C627H
+WBY1: equ 0C674H
+WBYTE: equ 0C66EH
+WRI1: equ 0C575H
+WRI2: equ 0C592H
+WRI3: equ 0C598H
+WTAP1: equ 0C5BAH
+WTAP2: equ 0C5CBH
+WTAP3: equ 0C5F8H
+WTAPE: equ 0C5B0H
diff --git a/software/mif/ascii_conv.mif b/software/mif/ascii_conv.mif
new file mode 100644
index 0000000..3181e07
--- /dev/null
+++ b/software/mif/ascii_conv.mif
@@ -0,0 +1,38 @@
+DEPTH = 512;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT BEGIN
+0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 0D 00 00;
+0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+0020: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F;
+0030: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F;
+0040: 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F;
+0050: 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F;
+0060: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+0070: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+0080: 7D 20 20 20 20 20 20 20 20 20 20 5E 20 20 20 20;
+0090: 20 20 65 88 7E 20 74 20 68 20 62 78 64 72 70 63;
+00a0: 71 61 7A 77 73 75 69 20 D6 6B 66 76 20 FC DF 6A;
+00b0: 6E 20 DC 6D 20 20 20 6F 6C C4 F6 E4 20 79 7B 20;
+00c0: 7C 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+00d0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+00e0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+00f0: 20 20 20 20 20 20 20 20 20 20 20 A3 20 20 20 20;
+0100: 00 00 00 00 00 00 00 00 00 00 00 00 00 0D 00 00;
+0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+0120: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F;
+0130: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F;
+0140: 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F;
+0150: 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 8B 20;
+0160: 93 A1 9A 9F 9C 92 AA 97 98 A6 AF A9 B8 B3 B0 B7;
+0170: 9E A0 9D A4 96 A5 AB A3 98 BD A2 BE C0 80 94 20;
+0180: 20 20 20 20 20 20 20 20 8B 20 20 20 20 20 20 20;
+0190: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+01a0: 20 20 20 FB 20 20 20 20 20 20 20 20 20 20 20 20;
+01b0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+01c0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+01d0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+01e0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+01f0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
+END;
diff --git a/software/mif/combined_cgrom.mif b/software/mif/combined_cgrom.mif
new file mode 100644
index 0000000..b9e611a
--- /dev/null
+++ b/software/mif/combined_cgrom.mif
@@ -0,0 +1,1286 @@
+DEPTH = 20480;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT BEGIN
+0000: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
+0010: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
+0020: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
+0030: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
+0040: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
+0050: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
+0060: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
+0070: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
+0080: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
+0090: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
+00a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
+00b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
+00c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
+00d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
+00e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
+00f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
+0100: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
+0110: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
+0120: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
+0130: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
+0140: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
+0150: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
+0160: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
+0170: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
+0180: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
+0190: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
+01a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
+01b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
+01c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
+01d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
+01e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
+01f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
+0200: 00 00 00 00 00 00 00 00 08 1c 3e 7f 7f 1c 3e 00;
+0210: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
+0220: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
+0230: 08 1c 2a 7f 2a 08 08 00 00 3c 7e 7e 7e 7e 3c 00;
+0240: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
+0250: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
+0260: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
+0270: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
+0280: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
+0290: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
+02a0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
+02b0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
+02c0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
+02d0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
+02e0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
+02f0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
+0300: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
+0310: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
+0320: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
+0330: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
+0340: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
+0350: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
+0360: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
+0370: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
+0380: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
+0390: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
+03a0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
+03b0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
+03c0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
+03d0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
+03e0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
+03f0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
+0400: 00 00 00 00 00 00 00 00 00 00 38 04 3c 44 3a 00;
+0410: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
+0420: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
+0430: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
+0440: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
+0450: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
+0460: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
+0470: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
+0480: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
+0490: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
+04a0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 42 3c 00;
+04b0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
+04c0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
+04d0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
+04e0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
+04f0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
+0500: 00 00 00 00 c0 30 0c 03 00 ff 00 00 00 ff 00 00;
+0510: 44 44 44 44 44 44 44 44 44 ff 44 44 44 ff 44 44;
+0520: 22 44 88 11 22 44 88 11 88 44 22 11 88 44 22 11;
+0530: aa 44 aa 11 aa 44 aa 11 00 00 00 00 03 0c 30 c0;
+0540: 03 0c 30 c0 00 00 00 00 c0 30 0c 03 00 00 00 00;
+0550: 38 44 44 4a 42 52 4c 00 00 22 00 22 22 22 1c 00;
+0560: 00 22 00 1c 22 22 1c 00 42 00 42 42 42 42 3c 00;
+0570: 42 18 24 42 7e 42 42 00 42 18 24 42 42 24 18 00;
+0580: 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80;
+0590: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
+05a0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01;
+05b0: 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08;
+05c0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1c 03;
+05d0: 00 00 00 00 01 06 38 c0 08 10 20 40 80 00 00 00;
+05e0: 22 14 3e 08 3e 08 08 00 08 08 08 08 ff 08 08 08;
+05f0: 24 24 24 24 c3 81 42 3c 00 3c 7a a9 a9 7a 3c 00;
+0600: 1c 1c 3e 1c 08 00 3e 00 ff f7 f7 f7 d5 e3 f7 ff;
+0610: ff f7 e3 d5 f7 f7 f7 ff ff ff f7 fb 81 fb f7 ff;
+0620: ff ff ef df 81 df ef ff bd bd bd 81 bd bd bd ff;
+0630: e3 dd bf bf bf dd e3 ff 18 24 7e ff 5a 24 00 00;
+0640: e0 47 42 7e 42 47 e0 00 22 3e 2a 08 08 49 7f 41;
+0650: 1c 1c 08 3e 08 08 14 22 00 11 d2 fc d2 11 00 00;
+0660: 00 88 4b 3f 4b 88 00 00 22 14 08 08 3e 08 1c 1c;
+0670: 3c 7e ff db ff 67 7e 3c 3c 42 81 a5 81 99 42 3c;
+0680: aa 55 aa 55 aa 55 aa 55 0a 05 0a 05 0a 05 0a 05;
+0690: a0 50 a0 50 a0 50 a0 50 aa 55 aa 55 00 00 00 00;
+06a0: 00 00 00 00 aa 55 aa 55 aa 54 a8 50 a0 40 80 00;
+06b0: aa 55 2a 15 0a 05 02 01 80 40 a0 50 a8 54 aa 55;
+06c0: 00 01 02 05 0a 15 2a 55 80 80 40 40 20 20 10 10;
+06d0: 08 08 04 04 02 02 01 01 38 28 38 00 00 00 00 00;
+06e0: 00 54 2a 54 2a 54 2a 00 01 01 02 02 04 04 08 08;
+06f0: 10 10 20 20 40 40 80 80 00 c0 c8 54 54 55 22 00;
+0700: 00 00 00 00 00 02 ff 02 02 02 02 02 02 02 07 02;
+0710: 02 02 02 02 02 02 ff 02 00 00 20 50 88 05 02 00;
+0720: 00 0e 11 22 c4 04 02 01 00 ff 00 81 42 42 81 00;
+0730: 00 70 88 44 23 20 40 80 00 c4 a4 94 8f 94 a4 c4;
+0740: 00 23 25 49 f1 49 25 23 88 90 a0 c0 c0 a8 98 b8;
+0750: a8 b0 b8 c0 c0 a0 90 88 80 40 20 10 1f 20 40 80;
+0760: 00 00 24 24 e7 24 24 00 08 08 3e 00 00 3e 08 08;
+0770: 08 10 20 10 08 04 02 04 55 aa 55 aa 55 aa 55 aa;
+0780: 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
+0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00;
+07a0: 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
+07b0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
+07c0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07;
+07d0: 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
+07e0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
+07f0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
+0800: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
+0810: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
+0820: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
+0830: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
+0840: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
+0850: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
+0860: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
+0870: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
+0880: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
+0890: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
+08a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
+08b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
+08c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
+08d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
+08e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
+08f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
+0900: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
+0910: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
+0920: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
+0930: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
+0940: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
+0950: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
+0960: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
+0970: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
+0980: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
+0990: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
+09a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
+09b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
+09c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
+09d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
+09e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
+09f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
+0a00: 00 00 00 00 00 00 00 00 08 1c 3e 7f 7f 1c 3e 00;
+0a10: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
+0a20: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
+0a30: 08 1c 2a 7f 2a 08 08 00 00 3c 7e 7e 7e 7e 3c 00;
+0a40: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
+0a50: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
+0a60: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
+0a70: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
+0a80: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
+0a90: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
+0aa0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
+0ab0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
+0ac0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
+0ad0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
+0ae0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
+0af0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
+0b00: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
+0b10: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
+0b20: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
+0b30: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
+0b40: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
+0b50: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
+0b60: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
+0b70: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
+0b80: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
+0b90: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
+0ba0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
+0bb0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
+0bc0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
+0bd0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
+0be0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
+0bf0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
+0c00: 00 00 00 00 00 00 00 00 00 00 38 04 3c 44 3a 00;
+0c10: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
+0c20: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
+0c30: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
+0c40: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
+0c50: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
+0c60: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
+0c70: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
+0c80: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
+0c90: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
+0ca0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 42 3c 00;
+0cb0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
+0cc0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
+0cd0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
+0ce0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
+0cf0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
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+4560: ff ff ff ff ff f7 f7 ef ff ff ff 81 ff ff ff ff;
+4570: ff ff ff ff ff e7 e7 ff ff fd fb f7 ef df bf ff;
+4580: c3 bd b9 a5 9d bd c3 ff f7 e7 d7 f7 f7 f7 c1 ff;
+4590: c3 bd fd f3 cf bf 81 ff c3 bd fd c3 fd bd c3 ff;
+45a0: fb f3 eb db 81 fb fb ff 81 bf 87 fb fd bb c7 ff;
+45b0: e3 df bf 83 bd bd c3 ff 81 bd fb f7 ef ef ef ff;
+45c0: c3 bd bd c3 bd bd c3 ff c3 bd bd c1 fd fb c7 ff;
+45d0: ff ff f7 ff ff f7 ff ff ff ff f7 ff ff f7 f7 ef;
+45e0: f1 e7 cf 9f cf e7 f1 ff ff ff 81 ff 81 ff ff ff;
+45f0: 8f e7 f3 f9 f3 e7 8f ff c3 bd fd f3 ef ff ef ff;
+4600: e3 dd b5 a9 b3 df e1 ff e7 db bd 81 bd bd bd ff;
+4610: 83 dd dd c3 dd dd 83 ff e3 dd bf bf bf dd e3 ff;
+4620: 87 db dd dd dd db 87 ff 81 bf bf 87 bf bf 81 ff;
+4630: 81 bf bf 87 bf bf bf ff e3 dd bf b1 bd dd e3 ff;
+4640: bd bd bd 81 bd bd bd ff e3 f7 f7 f7 f7 f7 e3 ff;
+4650: f1 fb fb fb fb bb c7 ff bd bb b7 8f b7 bb bd ff;
+4660: bf bf bf bf bf bf 81 ff bd 99 a5 a5 bd bd bd ff;
+4670: bd 9d ad b5 b9 bd bd ff e7 db bd bd bd db e7 ff;
+4680: 83 bd bd 83 bf bf bf ff e7 db bd bd b5 db e5 ff;
+4690: 83 bd bd 83 b7 bb bd ff c3 bd bf c3 fd bd c3 ff;
+46a0: c1 f7 f7 f7 f7 f7 f7 ff bd bd bd bd bd bd c3 ff;
+46b0: bd bd bd db db e7 e7 ff bd bd bd a5 a5 99 bd ff;
+46c0: bd bd db e7 db bd bd ff dd dd dd e3 f7 f7 f7 ff;
+46d0: 81 fd fb e7 df bf 81 ff c3 df df df df df c3 ff;
+46e0: ff bf df ef f7 fb fd ff c3 fb fb fb fb fb c3 ff;
+46f0: f7 eb dd ff ff ff ff ff 00 ff ff ff ff ff ff ff;
+4700: df ef f7 ff ff ff ff ff ff ff c3 fb c3 bb c5 ff;
+4710: bf bf a3 9d bd 9d a3 ff ff ff c3 bd bf bd c3 ff;
+4720: fd fd c5 b9 bd b9 c5 ff ff ff c3 bd 81 bf c3 ff;
+4730: f3 ed ef 83 ef ef ef ff ff ff c5 b9 b9 c5 fd c3;
+4740: bf bf a3 9d bd bd bd ff f7 ff e7 f7 f7 f7 e3 ff;
+4750: fb ff f3 fb fb fb bb c7 bf bf bb b7 af 97 bb ff;
+4760: e7 f7 f7 f7 f7 f7 e3 ff ff ff 89 b6 b6 b6 b6 ff;
+4770: ff ff a3 9d bd bd bd ff ff ff c3 bd bd bd c3 ff;
+4780: ff ff a3 9d 9d a3 bf bf ff ff c5 b9 b9 c5 fd fd;
+4790: ff ff a3 9d bf bf bf ff ff ff c1 bf c3 fd 83 ff;
+47a0: ef ef 83 ef ef ed f3 ff ff ff bd bd bd b9 c5 ff;
+47b0: ff ff bd bd bd db e7 ff ff ff be b6 b6 b6 c9 ff;
+47c0: ff ff bd db e7 db bd ff ff ff bd bd b9 c5 fd c3;
+47d0: ff ff 81 fb e7 df 81 ff f7 ef ef df ef ef f7 ff;
+47e0: e7 e7 e7 e7 e7 e7 e7 ff ef f7 f7 fb f7 f7 ef ff;
+47f0: ff ff ff cd b3 ff ff ff 00 00 01 3e 54 14 14 00;
+4800: 00 00 00 00 00 00 00 00 1c 14 14 77 22 14 08 00;
+4810: 08 14 22 77 14 14 1c 00 08 0c 7a 41 7a 0c 08 00;
+4820: 08 18 2f 41 2f 18 08 00 77 55 5d 41 5d 55 77 00;
+4830: 1e 21 4f 50 4f 21 1e 00 00 00 00 00 00 00 00 00;
+4840: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+4850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+4860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+4870: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+4880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+4890: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+48a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+48b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+48c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+48d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+48e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+48f0: 00 00 00 00 00 00 00 00 aa 55 aa 55 aa 55 aa 55;
+4900: 00 00 00 00 00 00 00 00 08 08 08 08 00 00 08 00;
+4910: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
+4920: 08 1e 28 1c 0a 3c 08 00 00 62 64 08 10 26 46 00;
+4930: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
+4940: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
+4950: 08 2a 1c 3e 1c 2a 08 00 00 08 08 3e 08 08 00 00;
+4960: 00 00 00 00 00 08 08 10 00 00 00 7e 00 00 00 00;
+4970: 00 00 00 00 00 18 18 00 00 02 04 08 10 20 40 00;
+4980: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
+4990: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
+49a0: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
+49b0: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
+49c0: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
+49d0: 00 00 08 00 00 08 00 00 00 00 08 00 00 08 08 10;
+49e0: 0e 18 30 60 30 18 0e 00 00 00 7e 00 7e 00 00 00;
+49f0: 70 18 0c 06 0c 18 70 00 3c 42 02 0c 10 00 10 00;
+4a00: 1c 22 4a 56 4c 20 1e 00 18 24 42 7e 42 42 42 00;
+4a10: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
+4a20: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
+4a30: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
+4a40: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
+4a50: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
+4a60: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
+4a70: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
+4a80: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
+4a90: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
+4aa0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
+4ab0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
+4ac0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
+4ad0: 7e 02 04 18 20 40 7e 00 3c 20 20 20 20 20 3c 00;
+4ae0: 00 40 20 10 08 04 02 00 3c 04 04 04 04 04 3c 00;
+4af0: 08 14 22 00 00 00 00 00 ff 00 00 00 00 00 00 00;
+4b00: 20 10 08 00 00 00 00 00 00 00 3c 04 3c 44 3a 00;
+4b10: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
+4b20: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
+4b30: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
+4b40: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
+4b50: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
+4b60: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
+4b70: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
+4b80: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
+4b90: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
+4ba0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 46 3a 00;
+4bb0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
+4bc0: 00 00 42 24 18 24 42 00 00 00 42 42 46 3a 02 3c;
+4bd0: 00 00 7e 04 18 20 7e 00 08 10 10 20 10 10 08 00;
+4be0: 18 18 18 18 18 18 18 00 10 08 08 04 08 08 10 00;
+4bf0: 00 00 00 32 4c 00 00 00 00 7c 04 04 15 0e 04 00;
+4c00: 28 28 28 28 28 28 28 28 00 08 08 08 2a 1c 08 00;
+4c10: 00 08 1c 2a 08 08 08 00 00 08 04 7e 04 08 00 00;
+4c20: 00 10 20 7e 20 10 00 00 08 1c 3e 7f 7f 1c 3e 00;
+4c30: 36 7f 7f 7f 3e 1c 08 00 08 1c 3e 7f 3e 1c 08 00;
+4c40: 1c 1c 6b 7f 6b 08 1c 00 10 10 10 1f 1f 10 10 10;
+4c50: 10 10 10 f0 f0 10 10 10 00 00 00 ff 28 28 28 28;
+4c60: 28 28 28 ff 00 00 00 00 28 28 28 ff ff 28 28 28;
+4c70: 10 10 10 ff ff 10 10 10 28 28 28 ff 28 28 28 28;
+4c80: 00 00 00 ff ff 00 00 00 22 14 3e 08 3e 08 08 00;
+4c90: 0c 12 10 38 10 10 3e 00 00 3c 7e 7e 7e 7e 3c 00;
+4ca0: 00 3c 42 42 42 42 3c 00 00 00 00 f0 10 10 10 10;
+4cb0: 10 10 10 f0 00 00 00 00 00 00 00 1f 10 10 10 10;
+4cc0: 10 10 10 1f 00 00 00 00 10 10 10 ff 10 10 10 10;
+4cd0: 10 10 10 10 10 10 10 10 00 00 00 ff 00 00 00 00;
+4ce0: 10 10 10 ff 00 00 00 00 00 00 00 ff 10 10 10 10;
+4cf0: 10 10 10 f0 10 10 10 10 10 10 10 1f 10 10 10 10;
+4d00: ff ff ff ff ff ff ff ff f7 f7 f7 f7 ff ff f7 ff;
+4d10: db db db ff ff ff ff ff db db 81 db 81 db db ff;
+4d20: f7 e1 d7 e3 f5 c3 f7 ff ff 9d 9b f7 ef d9 b9 ff;
+4d30: cf b7 b7 cf b5 bb c5 ff fb f7 ef ff ff ff ff ff;
+4d40: fb f7 ef ef ef f7 fb ff df ef f7 f7 f7 ef df ff;
+4d50: f7 d5 e3 c1 e3 d5 f7 ff ff f7 f7 c1 f7 f7 ff ff;
+4d60: ff ff ff ff ff f7 f7 ef ff ff ff 81 ff ff ff ff;
+4d70: ff ff ff ff ff e7 e7 ff ff fd fb f7 ef df bf ff;
+4d80: c3 bd b9 a5 9d bd c3 ff f7 e7 d7 f7 f7 f7 c1 ff;
+4d90: c3 bd fd f3 cf bf 81 ff c3 bd fd c3 fd bd c3 ff;
+4da0: fb f3 eb db 81 fb fb ff 81 bf 87 fb fd bb c7 ff;
+4db0: e3 df bf 83 bd bd c3 ff 81 bd fb f7 ef ef ef ff;
+4dc0: c3 bd bd c3 bd bd c3 ff c3 bd bd c1 fd fb c7 ff;
+4dd0: ff ff f7 ff ff f7 ff ff ff ff f7 ff ff f7 f7 ef;
+4de0: f1 e7 cf 9f cf e7 f1 ff ff ff 81 ff 81 ff ff ff;
+4df0: 8f e7 f3 f9 f3 e7 8f ff c3 bd fd f3 ef ff ef ff;
+4e00: e3 dd b5 a9 b3 df e1 ff e7 db bd 81 bd bd bd ff;
+4e10: 83 dd dd c3 dd dd 83 ff e3 dd bf bf bf dd e3 ff;
+4e20: 87 db dd dd dd db 87 ff 81 bf bf 87 bf bf 81 ff;
+4e30: 81 bf bf 87 bf bf bf ff e3 dd bf b1 bd dd e3 ff;
+4e40: bd bd bd 81 bd bd bd ff e3 f7 f7 f7 f7 f7 e3 ff;
+4e50: f1 fb fb fb fb bb c7 ff bd bb b7 8f b7 bb bd ff;
+4e60: bf bf bf bf bf bf 81 ff bd 99 a5 a5 bd bd bd ff;
+4e70: bd 9d ad b5 b9 bd bd ff e7 db bd bd bd db e7 ff;
+4e80: 83 bd bd 83 bf bf bf ff e7 db bd bd b5 db e5 ff;
+4e90: 83 bd bd 83 b7 bb bd ff c3 bd bf c3 fd bd c3 ff;
+4ea0: c1 f7 f7 f7 f7 f7 f7 ff bd bd bd bd bd bd c3 ff;
+4eb0: bd bd bd db db e7 e7 ff bd bd bd a5 a5 99 bd ff;
+4ec0: bd bd db e7 db bd bd ff dd dd dd e3 f7 f7 f7 ff;
+4ed0: 81 fd fb e7 df bf 81 ff c3 df df df df df c3 ff;
+4ee0: ff bf df ef f7 fb fd ff c3 fb fb fb fb fb c3 ff;
+4ef0: f7 eb dd ff ff ff ff ff 00 ff ff ff ff ff ff ff;
+4f00: df ef f7 ff ff ff ff ff ff ff c3 fb c3 bb c5 ff;
+4f10: bf bf a3 9d bd 9d a3 ff ff ff c3 bd bf bd c3 ff;
+4f20: fd fd c5 b9 bd b9 c5 ff ff ff c3 bd 81 bf c3 ff;
+4f30: f3 ed ef 83 ef ef ef ff ff ff c5 b9 b9 c5 fd c3;
+4f40: bf bf a3 9d bd bd bd ff f7 ff e7 f7 f7 f7 e3 ff;
+4f50: fb ff f3 fb fb fb bb c7 bf bf bb b7 af 97 bb ff;
+4f60: e7 f7 f7 f7 f7 f7 e3 ff ff ff 89 b6 b6 b6 b6 ff;
+4f70: ff ff a3 9d bd bd bd ff ff ff c3 bd bd bd c3 ff;
+4f80: ff ff a3 9d 9d a3 bf bf ff ff c5 b9 b9 c5 fd fd;
+4f90: ff ff a3 9d bf bf bf ff ff ff c1 bf c3 fd 83 ff;
+4fa0: ef ef 83 ef ef ed f3 ff ff ff bd bd bd b9 c5 ff;
+4fb0: ff ff bd bd bd db e7 ff ff ff be b6 b6 b6 c9 ff;
+4fc0: ff ff bd db e7 db bd ff ff ff bd bd b9 c5 fd c3;
+4fd0: ff ff 81 fb e7 df 81 ff f7 ef ef df ef ef f7 ff;
+4fe0: e7 e7 e7 e7 e7 e7 e7 ff ef f7 f7 fb f7 f7 ef ff;
+4ff0: ff ff ff cd b3 ff ff ff 00 00 01 3e 54 14 14 00;
+END;
diff --git a/software/mif/combined_keymap.mif b/software/mif/combined_keymap.mif
new file mode 100644
index 0000000..6381432
--- /dev/null
+++ b/software/mif/combined_keymap.mif
@@ -0,0 +1,134 @@
+DEPTH = 2048;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT BEGIN
+0000: ff ff ff ff ff ff ff 86 ff 37 ff ff ff 90 93 ff;
+0010: ff ff 80 ff ff 20 00 ff ff ff 60 50 40 30 10 ff;
+0020: ff 61 70 41 21 11 01 ff ff 91 71 51 22 31 02 ff;
+0030: ff 72 62 52 42 32 12 ff ff ff 63 43 23 03 13 ff;
+0040: ff 73 53 33 24 14 04 ff ff 64 74 44 54 34 05 ff;
+0050: ff 95 45 ff 25 15 ff ff 81 85 84 55 ff 75 ff ff;
+0060: ff ff ff ff ff ff 65 ff ff 66 35 46 26 ff ff ff;
+0070: 96 87 76 56 47 36 ff 06 77 57 67 17 07 27 ff ff;
+0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+00c0: ff ff ff ff ff ff ff ff ff ff 16 ff ff ff ff ff;
+00d0: ff ff ff ff ff ff ff ff ff ff 97 ff ff ff ff ff;
+00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ef;
+00f0: ff 81 92 ff 83 ff ff ff ff ff ff ff ff ff ff ff;
+0100: ff ff ff ff ff ff ff 86 ff 37 ff ff ff 90 93 ff;
+0110: ff ff 80 ff ff 20 00 ff ff ff 60 50 40 30 10 ff;
+0120: ff 61 70 41 21 11 01 ff ff 91 71 51 22 31 02 ff;
+0130: ff 72 62 52 42 32 12 ff ff ff 63 43 23 03 13 ff;
+0140: ff 73 53 33 24 14 04 ff ff 64 74 44 54 34 05 ff;
+0150: ff 95 45 ff 25 15 ff ff 81 85 84 55 ff 75 ff ff;
+0160: ff ff ff ff ff ff 65 ff ff 66 35 46 26 ff ff ff;
+0170: 96 87 76 56 47 36 ff 06 77 57 67 17 07 27 ff ff;
+0180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+01a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+01b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+01c0: ff ff ff ff ff ff ff ff ff ff 16 ff ff ff ff ff;
+01d0: ff ff ff ff ff ff ff ff ff ff 97 ff ff ff ff ff;
+01e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ef;
+01f0: ff 81 92 ff 83 ff ff ff ff ff ff ff ff ff ff ff;
+0200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0210: ff ff 00 ff 27 14 16 ff ff ff 10 22 13 15 17 ff;
+0220: ff 20 21 23 24 27 26 ff ff 40 31 32 34 25 36 ff;
+0230: ff 41 30 42 33 35 37 ff ff ff 50 43 44 46 47 ff;
+0240: ff 51 52 45 54 57 56 ff ff 60 70 53 63 55 67 ff;
+0250: ff ff 62 ff 65 66 ff ff 11 07 73 72 64 76 ff ff;
+0260: ff ff ff ff ff ff 61 ff ff 8a ff 84 77 ff ff ff;
+0270: 12 ff 74 85 75 a7 ff ff ff 97 92 95 90 96 ff ff;
+0280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+02a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+02b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+02c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+02d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+02e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+02f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0310: ff ff 00 ff 27 14 16 ff ff ff 10 22 13 15 17 ff;
+0320: ff 20 21 23 24 27 26 ff ff 40 31 32 34 25 36 ff;
+0330: ff 41 30 42 33 35 37 ff ff ff 50 43 44 46 47 ff;
+0340: ff 51 52 45 54 57 56 ff ff 60 70 53 63 55 67 ff;
+0350: ff ff 62 ff 65 66 ff ff 11 07 73 72 64 76 ff ff;
+0360: ff ff ff ff ff ff 61 ff ff 8a ff 84 77 ff ff ff;
+0370: 12 ff 74 85 75 a7 ff ff ff 97 92 95 90 96 ff ff;
+0380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+03a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+03b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+03c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+03d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+03e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+03f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0400: ff ff ff 93 95 97 96 ff ff ff ff ff 94 ff ff ff;
+0410: ff 06 80 ff a6 27 57 ff ff ff 16 25 47 21 56 ff;
+0420: ff 45 20 44 43 45 55 ff ff 64 22 42 24 26 53 ff;
+0430: ff 32 46 40 41 17 52 ff ff ff 33 36 23 51 50 ff;
+0440: ff 61 35 37 31 63 62 ff ff 60 70 34 0a 30 75 ff;
+0450: ff ff ff ff 14 65 ff ff 04 ff 00 13 ff 67 ff ff;
+0460: ff ff ff ff ff ff ff ff ff ff ff 72 ff ff ff ff;
+0470: 77 76 74 ff 73 75 87 ff ff ff ff ff ff ff ff ff;
+0480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+04a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+04b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+04c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+04d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+04e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+04f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0500: ff ff ff 93 95 97 96 ff ff ff ff ff 94 ff ff ff;
+0510: ff 06 80 ff a6 27 57 ff ff ff 16 25 47 21 56 ff;
+0520: ff 45 20 44 43 45 55 ff ff 64 22 42 24 26 53 ff;
+0530: ff 32 46 40 41 17 52 ff ff ff 33 36 23 51 50 ff;
+0540: ff 61 35 37 31 63 62 ff ff 60 70 34 0a 30 75 ff;
+0550: ff ff ff ff 14 65 ff ff 04 ff 00 13 ff 67 ff ff;
+0560: ff ff ff ff ff ff ff ff ff ff ff 72 ff ff ff ff;
+0570: 77 76 74 ff 73 75 87 ff ff ff ff ff ff ff ff ff;
+0580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+05a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+05b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+05c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+05d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+05e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+05f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+0600: ff 10 ff 04 02 00 01 ff ff 11 07 05 03 b0 b3 ff;
+0610: ff 30 b2 ff ff 61 81 ff ff ff 72 63 41 67 82 ff;
+0620: ff 43 70 44 45 84 83 ff ff 31 66 46 64 62 85 ff;
+0630: ff 56 42 50 47 71 86 ff ff ff 55 52 65 87 90 ff;
+0640: ff 77 53 51 57 80 91 ff ff 76 40 54 93 60 94 ff;
+0650: ff 75 92 ff 95 73 ff ff b1 b2 32 96 ff a0 ff ff;
+0660: ff ff ff ff ff ff 37 ff ff 21 74 24 27 ff ff ff;
+0670: 20 15 22 25 26 12 ff ff ff 17 23 16 ff 13 ff ff;
+0680: ff ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff;
+0690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+06a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+06b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+06c0: ff ff ff ff ff ff ff ff ff ff 14 ff ff ff ff ff;
+06d0: ff ff ff ff ff ff ff ff ff ff 32 ff ff ff ff ff;
+06e0: ff ff ff ff ff ff ff ff ff ff ff 35 ff ff ff ef;
+06f0: a2 a3 34 ff 36 33 ff ff ff ff ff ff ff ff ff ff;
+0700: ff 10 ff 04 02 00 01 ff ff 11 07 05 03 b0 b3 ff;
+0710: ff 30 b2 ff ff 61 81 ff ff ff 72 63 41 67 82 ff;
+0720: ff 43 70 44 45 84 83 ff ff 31 66 46 64 62 85 ff;
+0730: ff 56 42 50 47 71 86 ff ff ff 55 52 65 87 90 ff;
+0740: ff 77 53 51 57 80 91 ff ff 76 40 54 93 60 94 ff;
+0750: ff 75 92 ff 95 73 ff ff b1 b2 32 96 ff a0 ff ff;
+0760: ff ff ff ff ff ff 37 ff ff 21 74 24 27 ff ff ff;
+0770: 20 15 22 25 26 12 ff ff ff 17 23 16 ff 13 ff ff;
+0780: ff ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff;
+0790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+07a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+07b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+07c0: ff ff ff ff ff ff ff ff ff ff 14 ff ff ff ff ff;
+07d0: ff ff ff ff ff ff ff ff ff ff 32 ff ff ff ff ff;
+07e0: ff ff ff ff ff ff ff ff ff ff ff 35 ff ff ff ef;
+07f0: a2 a3 34 ff 36 33 ff ff ff ff ff ff ff ff ff ff;
+END;
diff --git a/software/mif/combined_mainmemory.mif b/software/mif/combined_mainmemory.mif
new file mode 100644
index 0000000..e71d8e1
--- /dev/null
+++ b/software/mif/combined_mainmemory.mif
@@ -0,0 +1,3718 @@
+DEPTH = 59392;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT BEGIN
+0000: c3 4a 00 c3 a8 07 c3 80 09 c3 7b 09 c3 93 09 c3;
+0010: 84 09 c3 95 09 c3 93 08 c3 a1 08 c3 b3 08 c3 11;
+0020: 0d c3 36 04 c3 70 04 c3 cf 04 c3 ef 04 c3 75 05;
+0030: c3 88 01 c3 fa 02 00 00 c3 38 10 c3 44 03 c3 e5;
+0040: 02 c3 ec 02 c3 ab 02 c3 be 02 31 f0 10 ed 56 cd;
+0050: 4d 07 06 ff 21 f1 10 cd d8 0f 3e 16 cd 12 00 3e;
+0060: 71 21 00 d8 18 03 c3 35 10 cd e3 09 21 79 03 3e;
+0070: c3 32 38 10 22 39 10 3e 04 32 9e 11 cd be 02 cd;
+0080: 09 00 11 00 01 df cd e5 02 3e ff 32 9d 11 21 00;
+0090: e8 36 55 18 35 cd 09 00 3e 3e cd 12 00 11 a3 11;
+00a0: cd 03 00 1a 13 fe 0d 28 ec fe 4a 28 0e fe 4c 28;
+00b0: 28 fe 46 28 12 fe 42 28 08 18 e8 cd 10 04 38 d5;
+00c0: e9 3a 9d 11 2f 18 c4 21 00 f0 7e b7 20 c7 e9 fe;
+00d0: 02 28 c2 11 18 01 df 18 bc cd cf 04 38 f1 cd 09;
+00e0: 00 11 f7 00 df 11 f1 10 df cd ef 04 38 e1 2a 06;
+00f0: 11 7c fe 12 38 9f e9 4c b7 a1 9c a6 b0 97 20 0d;
+0100: 2a 2a 20 20 4d 4f 4e 49 54 4f 52 20 53 41 2d 31;
+0110: 35 31 30 20 20 2a 2a 0d 43 98 92 9f a9 20 a4 a5;
+0120: b3 20 92 9d 9d b7 9d 0d cd 2b 0a 0f d2 86 0e 2e;
+0130: 00 24 fe 18 28 04 24 c3 66 0e 22 71 11 01 c0 03;
+0140: 11 00 d0 21 28 d0 ed b0 eb 06 28 cd d8 0f 01 1a;
+0150: 00 11 73 11 21 74 11 ed b0 36 00 3a 73 11 b7 ca;
+0160: e5 0e 21 72 11 35 18 d5 3d 01 5d 0e 6e 0e 7b 0e;
+0170: 95 0e 09 04 b3 0e f2 0e 2d 0f e1 0e ee 0e e5 0e;
+0180: 17 0a 28 01 e5 0e e5 0e c5 d5 e5 3e 02 32 a0 11;
+0190: 06 01 1a fe 0d 28 3b fe c8 28 37 fe cf 28 27 fe;
+01a0: 2d 28 23 fe 2b 28 27 fe d7 28 23 fe 23 21 29 02;
+01b0: 20 04 21 41 02 13 cd dd 01 38 d7 cd c8 02 38 15;
+01c0: cd ab 02 41 18 cc 3e 03 32 a0 11 13 18 c4 3e 01;
+01d0: 18 f6 cd c8 02 f5 cd be 02 f1 c3 9f 06 c5 06 08;
+01e0: 1a be 28 09 23 23 23 10 f8 37 13 c1 c9 23 d5 5e;
+01f0: 23 56 eb 7c b7 28 09 3a a0 11 3d 28 03 29 18 fa;
+0200: 22 a1 11 21 a0 11 36 02 2b d1 13 1a 47 e6 f0 fe;
+0210: 30 28 03 7e 18 05 13 78 e6 0f 77 21 59 02 85 6f;
+0220: 4e 3a 9e 11 47 af c3 ab 09 43 77 07 44 a7 06 45;
+0230: ed 05 46 98 05 47 fc 04 41 71 04 42 f5 03 52 00;
+0240: 00 43 0c 07 44 47 06 45 98 05 46 48 05 47 b4 04;
+0250: 41 31 04 42 bb 03 52 00 00 01 02 03 04 06 08 0c;
+0260: 10 18 20 21 92 11 36 ef 3a 70 11 b7 28 02 36 ff;
+0270: 7e f5 cd b1 0f 7e 32 8e 11 f1 77 af 21 00 e0 77;
+0280: 2f 77 c9 f5 e5 21 7c 11 7e 3c fe 33 20 01 af e5;
+0290: 6f 3a 91 11 b7 7d e1 20 01 77 e1 f1 c9 f5 e5 21;
+02a0: 7c 11 7e 3d f2 8f 02 3e 32 18 e4 2a a1 11 7c b7;
+02b0: 28 0c d5 eb 21 04 e0 73 72 3e 01 d1 18 06 3e 34;
+02c0: 32 07 e0 af 32 08 e0 c9 21 00 e0 36 f0 23 7e e6;
+02d0: 81 20 02 37 c9 3a 08 e0 0f 38 fa 3a 08 e0 0f 30;
+02e0: fa 10 f2 af c9 d5 11 b1 0d f7 d1 c9 f5 c5 e6 0f;
+02f0: 47 3e 08 90 32 9e 11 c1 f1 c9 f3 c5 d5 e5 32 9b;
+0300: 11 3e f0 32 9c 11 21 c0 a8 af ed 52 e5 23 eb 21;
+0310: 07 e0 36 74 36 b0 2b 73 72 2b 36 0a 36 00 23 23;
+0320: 36 80 2b 4e 7e ba 20 fb 79 bb 20 f7 2b 00 00 00;
+0330: 36 0c 36 7b 23 d1 4e 7e ba 20 fb 79 bb 20 f7 e1;
+0340: d1 c1 fb c9 e5 21 07 e0 36 80 2b f3 5e 56 fb 7b;
+0350: b2 28 0e af 21 c0 a8 ed 52 38 10 eb 3a 9b 11 e1;
+0360: c9 11 c0 a8 3a 9b 11 ee 01 e1 c9 f3 21 06 e0 7e;
+0370: 2f 5f 7e 2f 57 fb 13 18 eb f5 c5 d5 e5 21 9b 11;
+0380: 7e ee 01 77 21 07 e0 36 80 2b e5 5e 56 21 c0 a8;
+0390: 19 2b 2b eb e1 73 72 e1 d1 c1 f1 fb c9 eb 36 01;
+03a0: 23 36 00 c3 7b 0e 3a 72 11 85 6f 7e 23 cb 16 b6;
+03b0: cb 1e 0f eb 2a 71 11 c9 4c f1 7c cd c3 03 7d 18;
+03c0: 02 43 43 f5 0f 0f 0f 0f cd da 03 cd 12 00 f1 cd;
+03d0: da 03 c3 12 00 d1 e1 c1 f1 c9 e6 0f fe 0a 38 02;
+03e0: c6 07 c6 30 c9 fe 30 d8 fe 3a 38 06 d6 07 fe 40;
+03f0: 30 03 e6 0f c9 37 c9 48 4c 18 ea 2a 71 11 3a 7c;
+0400: 11 94 30 02 c6 32 32 7c 11 21 00 00 c3 69 0e 2c;
+0410: d5 cd 1f 04 38 07 67 cd 1f 04 38 01 6f d1 c9 c5;
+0420: 1a 13 cd f9 03 38 0d 0f 0f 0f 0f 4f 1a 13 cd f9;
+0430: 03 38 01 b1 c1 c9 f3 d5 c5 e5 16 d7 1e cc 21 f0;
+0440: 10 01 80 00 cd 1a 07 cd a3 06 38 18 7b fe cc 20;
+0450: 0d cd 09 00 d5 11 67 04 df 11 f1 10 df d1 cd 7a;
+0460: 07 cd 85 04 c3 52 05 57 9d a6 96 a6 b0 97 20 0d;
+0470: f3 d5 c5 e5 16 d7 1e 53 ed 4b 02 11 2a 04 11 78;
+0480: b1 28 48 18 bf d5 c5 e5 16 02 3e f0 32 00 e0 7e;
+0490: cd 67 07 3a 01 e0 e6 81 c2 9e 04 37 18 2d 23 0b;
+04a0: 78 b1 c2 8f 04 2a 97 11 7c cd 67 07 7d cd 67 07;
+04b0: cd 57 0d 15 c2 bb 04 b7 c3 cb 04 06 00 cd 3e 0d;
+04c0: 05 c2 bd 04 e1 c1 c5 e5 c3 8f 04 e1 c1 d1 c9 f3;
+04d0: d5 c5 e5 16 d2 1e cc 01 80 00 21 f0 10 cd a3 06;
+04e0: da 70 05 cd 58 06 da 70 05 cd 05 05 c3 52 05 f3;
+04f0: d5 c5 e5 16 d2 1e 53 ed 4b 02 11 2a 04 11 78 b1;
+0500: ca 52 05 18 d8 d5 c5 e5 26 02 01 01 e0 11 02 e0;
+0510: cd 01 06 da 70 05 cd a2 09 1a e6 20 ca 10 05 54;
+0520: 21 00 00 22 97 11 e1 c1 c5 e5 cd 24 06 da 70 05;
+0530: 77 23 0b 78 b1 c2 2a 05 2a 97 11 cd 24 06 da 70;
+0540: 05 5f cd 24 06 da 70 05 bd c2 63 05 7b bc c2 63;
+0550: 05 af e1 c1 d1 cd 00 07 f5 3a 9c 11 fe f0 20 01;
+0560: fb f1 c9 15 28 06 62 cd e2 0f 18 9e 3e 01 18 02;
+0570: 3e 02 37 18 dd f3 d5 c5 e5 ed 4b 02 11 2a 04 11;
+0580: 16 d2 1e 53 78 b1 28 ca cd 1a 07 cd a3 06 38 e0;
+0590: cd 58 06 da 70 05 cd 9b 05 18 b7 d5 c5 e5 26 02;
+05a0: 01 01 e0 11 02 e0 cd 01 06 da 70 05 cd a2 09 1a;
+05b0: e6 20 ca a6 05 54 e1 c1 c5 e5 cd 24 06 da 70 05;
+05c0: be c2 6c 05 23 0b 78 b1 c2 ba 05 2a 99 11 cd 24;
+05d0: 06 bc 20 98 cd 24 06 bd 20 92 15 ca 51 05 62 18;
+05e0: bf 11 fc 09 df c3 07 08 21 7a 11 3a 7f 11 be ca;
+05f0: e5 0e c3 a9 0f f5 3a 8e 11 cd b1 0f 77 f1 c9 ab;
+0600: 4f 3e f0 32 00 e0 00 0a e6 81 c2 0f 06 37 c9 1a;
+0610: e6 20 c2 07 06 0a e6 81 c2 1d 06 37 c9 1a e6 20;
+0620: ca 15 06 c9 c5 d5 e5 21 00 08 01 01 e0 11 02 e0;
+0630: cd 01 06 da 54 06 cd a2 09 1a e6 20 ca 49 06 e5;
+0640: 2a 97 11 23 22 97 11 e1 37 7d 17 6f 25 c2 30 06;
+0650: cd 01 06 7d e1 d1 c1 c9 cd e2 0f c5 d5 e5 21 28;
+0660: 28 7b fe cc ca 6a 06 21 14 14 22 95 11 01 01 e0;
+0670: 11 02 e0 2a 95 11 cd 01 06 da 9f 06 cd a2 09 1a;
+0680: e6 20 ca 73 06 25 c2 76 06 cd 01 06 da 9f 06 cd;
+0690: a2 09 1a e6 20 c2 73 06 2d c2 89 06 cd 01 06 e1;
+06a0: d1 c1 c9 c5 d5 e5 06 0a 3a 02 e0 e6 10 28 0a 06;
+06b0: a6 cd a7 0d 10 fb af 18 e6 3e 06 21 03 e0 77 3c;
+06c0: 77 10 e5 cd 09 00 7a fe d7 28 05 11 9e 0d 18 07;
+06d0: 11 f4 06 df 11 a0 0d df 3a 02 e0 e6 10 20 d0 cd;
+06e0: 11 0d 20 f4 37 18 d0 06 c9 3a 70 11 b7 20 01 04;
+06f0: 78 c3 d6 08 7f 20 52 45 43 4f 52 44 2e 0d 34 44;
+0700: f5 c5 d5 06 0a 3a 02 e0 e6 10 28 0b 3e 06 32 03;
+0710: e0 3c 32 03 e0 10 ee c3 e6 0e c5 d5 e5 11 00 00;
+0720: 78 b1 20 0b eb 22 97 11 22 99 11 e1 d1 c1 c9 7e;
+0730: c5 06 08 07 30 01 13 10 fa c1 23 0b 18 e2 07 07;
+0740: 07 4f 7b 25 0f 30 fc 7c 81 4f c3 74 0a 21 03 e0;
+0750: 36 8a 36 07 36 05 36 01 c9 3e 0e 3d c2 5b 07 c9;
+0760: 3e 0d 3d c2 62 07 c9 c5 06 08 cd 57 0d 07 dc 57;
+0770: 0d d4 3e 0d 05 c2 6d 07 c1 c9 c5 d5 7b 01 f0 55;
+0780: 11 28 28 fe cc ca 8e 07 01 f8 2a 11 14 14 cd 3e;
+0790: 0d 0b 78 b1 20 f8 cd 57 0d 15 20 fa cd 3e 0d 1d;
+07a0: 20 fa cd 57 0d d1 c1 c9 f5 c5 e5 d5 cd 63 02 cd;
+07b0: ca 08 fe cb 28 f9 cd ca 08 cd ff 09 28 f8 f5 af;
+07c0: 32 93 11 f1 47 cd f5 05 3a 9d 11 b7 cc e5 02 78;
+07d0: fe e7 ca e1 05 fe e6 28 68 fe ee 28 61 fe e5 28;
+07e0: 76 fe e0 ca 8b 08 30 ce e6 f0 fe c0 20 15 78 fe;
+07f0: cd 28 68 fe cb ca 4e 08 fe c7 30 3d 3a 70 11 b7;
+0800: 78 28 36 78 cd b5 0d cd 63 02 3a 93 11 b7 20 14;
+0810: 1e 14 cd ca 08 20 ad cd f1 09 38 9a 1d 20 f3 3e;
+0820: 01 32 93 11 cd a7 0d cd a7 0d cd ca 08 cd ff 09;
+0830: 20 8c cd f1 09 38 e3 18 8c cd dc 0d 18 c9 af 18;
+0840: 02 3e ff 32 91 11 3e c6 cd dc 0d c3 ac 07 e1 e5;
+0850: 36 1b 23 36 0d 18 29 06 5a 18 a8 cd 2b 0a 06 28;
+0860: 30 24 25 06 50 2e 00 cd b4 0f d1 d5 7e cd ce 0b;
+0870: 12 23 cb 9c 13 10 f5 eb 36 0d 2b 7e fe 20 28 f8;
+0880: cd 80 09 c3 d5 03 0f 30 dc 18 d8 21 8f 11 7e 2f;
+0890: 77 18 b8 f5 c5 d5 1a fe 0d 28 0c cd 95 09 13 18;
+08a0: f5 f5 c5 d5 1a fe 0d ca e6 0e cd b9 0b cd 6c 09;
+08b0: 13 18 f1 c5 e5 06 09 21 65 11 cd db 0f e1 c1 cd;
+08c0: ca 08 d6 f0 c8 c6 f0 c3 ce 0b c5 d5 e5 cd 50 0a;
+08d0: 78 07 38 1e 3e f0 5f cd f1 09 3a 6e 11 b7 28 0a;
+08e0: cd a7 0d cd 50 0a 78 07 38 08 7b fe f0 20 50 c3;
+08f0: 9f 06 07 07 07 da e7 06 07 da c5 0b 26 00 69 79;
+0900: fe 38 30 26 3a 70 11 b7 78 07 20 23 47 3a 8f 11;
+0910: b7 78 28 03 17 3f 1f 17 17 30 07 11 da 0c 19 7e;
+0920: 18 b4 1f 30 05 11 32 0c 18 f4 11 ea 0b 18 ef 07;
+0930: 38 08 07 38 e6 11 6a 0c 18 e4 11 a2 0c 18 df cd;
+0940: f1 09 3c 7b 18 a9 79 cd b9 0b 4f e6 f0 fe f0 c8;
+0950: fe c0 79 20 17 cd dc 0d fe c3 28 13 fe c5 28 07;
+0960: fe cd 28 03 fe c6 c0 af 32 94 11 c9 cd b5 0d 3a;
+0970: 94 11 3c fe 50 38 02 d6 50 18 ed 3a 94 11 b7 c8;
+0980: 3e cd 18 d1 cd 0c 00 3a 94 11 b7 c8 d6 0a 38 f4;
+0990: 20 fa c9 3e 20 fe 0d 28 e7 c5 4f 47 cd 46 09 78;
+09a0: c1 c9 ed 44 ed 44 3e 2a c3 62 07 81 10 fd c1 4f;
+09b0: af c9 10 c5 d5 e5 cd 63 02 cd ca 08 cd ff 09 28;
+09c0: f8 cd f5 05 c3 9f 06 d5 e5 21 7a 11 af ed 6f 57;
+09d0: 5e ed 67 af cb 1a cb 1b 21 00 d0 19 22 7d 11 e1;
+09e0: d1 c9 af 01 00 08 d5 57 72 23 0b 78 b1 20 f9 d1;
+09f0: c9 21 6e 11 7e 23 56 77 92 d0 34 c9 30 30 0d f5;
+0a00: e5 3a 02 e0 07 07 38 0a 3a 92 11 cd b1 0f 77 e1;
+0a10: f1 c9 3a 8e 11 18 f4 21 90 11 7e b7 2f 77 28 05;
+0a20: 3a 14 e0 18 03 3a 15 e0 c3 e5 0e 21 73 11 3a 91;
+0a30: 11 b7 c2 a6 03 3a 7c 11 d6 08 23 30 fb c6 08 4e;
+0a40: 2b 47 04 c5 7e cb 19 1f 10 fb c1 eb 2a 71 11 c9;
+0a50: d5 e5 af 32 6e 11 06 fa 57 cd 11 0d 20 04 16 88;
+0a60: 18 28 21 64 11 e5 30 26 57 e6 60 20 21 7a ae cb;
+0a70: 67 72 28 02 cb fa 05 e1 23 78 32 00 e0 fe f0 20;
+0a80: 11 7e fe 03 38 04 36 00 cb ba 42 e1 d1 c9 36 00;
+0a90: 18 e4 3a 01 e0 5f 2f a6 73 e5 21 6e 11 c5 06 08;
+0aa0: cb 03 38 01 34 10 f9 c1 b7 28 cb 5f 26 08 78 3d;
+0ab0: e6 0f c3 3e 07 cc e0 f2 f3 ce cf f6 f7 f8 f9 fa;
+0ac0: fb fc fd fe ff e1 c1 c2 c3 c4 c5 c6 e2 e3 e4 e5;
+0ad0: e6 eb ee ef f4 00 61 62 63 64 65 66 67 68 69 6b;
+0ae0: 6a 2f 2a 2e 2d 20 21 22 23 24 25 26 27 28 29 4f;
+0af0: 2c 51 2b 57 49 55 01 02 03 04 05 06 07 08 09 0a;
+0b00: 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a;
+0b10: 52 59 54 50 45 c7 c8 c9 ca cb cc cd ce cf df e7;
+0b20: e8 e9 ea ec ed d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da;
+0b30: db dc dd de c0 40 bd 9d b1 b5 b9 b4 9e b2 b6 ba;
+0b40: be 9f b3 b7 bb bf a3 85 a4 a5 a6 94 87 88 9c 82;
+0b50: 98 84 92 90 83 91 81 9a 97 93 95 89 a1 af 8b 86;
+0b60: 96 a2 ab aa 8a 8e b0 ad 8d a7 a8 a9 8f 8c ae ac;
+0b70: 9b a0 99 bc b8 80 3b 3a 70 3c 71 5a 3d 43 56 3f;
+0b80: 1e 4a 1c 5d 3e 5c 1f 5f 5e 37 7b 7f 36 7a 7e 33;
+0b90: 4b 4c 1d 6c 5b 78 41 35 34 74 30 38 75 39 4d 6f;
+0ba0: 6e 32 77 76 72 73 47 7c 53 31 4e 6d 48 46 7d 44;
+0bb0: 1b 58 79 42 60 fd cb 00 1e c5 e5 21 b5 0a 4f 06;
+0bc0: 00 09 7e 18 1b 3e cb b7 c3 ef 08 29 f4 dd c5 e5;
+0bd0: d5 21 b5 0a 54 5d 01 00 01 ed b1 28 06 3e f0 d1;
+0be0: e1 c1 c9 b7 2b ed 52 7d 18 f5 22 21 17 11 01 c7;
+0bf0: 00 1a 24 23 12 05 04 13 18 03 26 25 19 14 07 06;
+0c00: 16 02 28 27 09 15 0a 08 0e 00 20 29 10 0f 0c 0b;
+0c10: 2f 0d be 2a 52 55 4f 2c 2d 2e c5 59 c3 c2 cd 54;
+0c20: 00 49 28 27 25 24 22 21 e7 20 6a 29 2a 26 00 23;
+0c30: 00 2e 62 61 97 91 81 c8 00 9a 64 63 92 85 84 93;
+0c40: 98 83 66 65 99 94 87 86 96 82 68 67 89 95 8a 88;
+0c50: 8e 00 bf 69 90 8f 8c 8b 51 8d a5 2b bc a4 6b 6a;
+0c60: 45 57 c6 80 c4 c1 cd 40 00 50 3e 37 38 3c 53 c7;
+0c70: 00 76 7b 7f 30 34 47 44 6d de 5e 3a 75 71 4b 4a;
+0c80: da 6f bd 1f 7d 79 5c 72 32 00 9c a1 d6 b0 b4 5b;
+0c90: 60 1c 9e d2 d8 b2 b6 42 db b8 c5 d4 c3 c2 cd 4e;
+0ca0: 00 ba 36 3f 78 7c 46 c8 00 77 3b 7e 70 74 48 41;
+0cb0: dd d9 1e 7a 35 31 4c 43 a6 6e a2 5f 3d 39 5d 73;
+0cc0: 33 00 9d a3 b1 d5 56 6c d0 1d 9f d1 b3 d7 4d b5;
+0cd0: 1b b9 c6 d3 c4 c1 cd b7 00 bb f0 f0 e2 c1 e0 f0;
+0ce0: 00 e5 f0 f0 c2 cf ce c3 e3 f3 f0 f0 e4 c4 f7 f6;
+0cf0: c6 f2 f0 f0 f9 c5 fa f8 fe f0 f0 f0 e1 ff fc fb;
+0d00: f0 fd ef f4 e6 cc f0 f0 f0 f0 f0 eb f0 f0 f0 ee;
+0d10: f0 3e f0 32 00 e0 00 3a 01 e0 b7 17 30 19 1f 1f;
+0d20: 30 05 1f 30 06 3f c9 3e 40 37 c9 3a 6e 11 3e 01;
+0d30: 32 6e 11 3e 10 37 c9 e6 02 c8 3e 20 37 c9 f5 3e;
+0d40: 03 32 03 e0 cd 59 07 cd 59 07 3e 02 32 03 e0 cd;
+0d50: 59 07 cd 59 07 f1 c9 f5 3e 03 32 03 e0 cd 59 07;
+0d60: cd 59 07 cd 59 07 cd 59 07 3e 02 32 03 e0 cd 59;
+0d70: 07 cd 59 07 cd 59 07 cd 60 07 f1 c9 fe 08 28 10;
+0d80: cb 0e 10 fc cb c6 cb 8e 47 cb 06 10 fc c3 7b 0e;
+0d90: 23 cb c6 cb 8e 18 f6 cb fe 23 cb 86 18 ef 7f 20;
+0da0: 50 4c 41 59 0d f3 c9 c5 06 23 cd a2 09 10 fb c1;
+0db0: c9 d7 41 30 0d f5 c5 d5 e5 47 cd b1 0f 70 2a 71;
+0dc0: 11 7d fe 27 20 c7 cd 2b 0a 38 c2 3a 91 11 b7 c2;
+0dd0: 9d 03 eb 78 fe 07 28 bf 18 a2 24 f3 f5 c5 d5 e5;
+0de0: 47 e6 f0 fe c0 c2 e5 0e a8 07 4f 06 00 21 ff 0d;
+0df0: 3a 91 11 b7 28 03 21 68 01 09 5e 23 56 eb e9 1f;
+0e00: 0e 5d 0e 6e 0e 7b 0e 95 0e fb 03 b3 0e f2 0e 2d;
+0e10: 0f e1 0e ee 0e e5 0e 17 0a 73 0f e8 05 59 0f 21;
+0e20: 7a 11 0e 05 3a 7f 11 81 32 7f 11 3a 7b 11 81 32;
+0e30: 7b 11 79 86 77 cd c7 09 2a 7d 11 11 e8 03 19 06;
+0e40: 28 af cb 9c 77 23 10 fa 3a 7a 11 6f 26 e2 7e 21;
+0e50: 79 11 b7 06 07 cb 1e 2b 10 fb c3 e5 0e 2a 71 11;
+0e60: 7c fe 18 28 2e 24 cd 83 02 22 71 11 18 77 2a 71;
+0e70: 11 7c b7 28 35 25 cd 9d 02 18 ee 2a 71 11 7d fe;
+0e80: 27 30 03 2c 18 e3 2e 00 24 7c fe 19 38 d8 26 18;
+0e90: 22 71 11 18 42 2a 71 11 7d b7 28 03 2d 18 ca 2e;
+0ea0: 27 25 f2 76 0e 26 00 22 71 11 3a 91 11 b7 20 35;
+0eb0: c3 59 0f 21 73 11 06 1b cd d8 0f 21 00 d0 e5 cd;
+0ec0: e2 09 e1 3a 91 11 b7 20 08 22 7d 11 3e 7d 32 7f;
+0ed0: 11 3a 00 e2 c3 09 04 3a 91 11 b7 c2 3d 01 c3 9f;
+0ee0: 0f af 32 70 11 e1 d1 c1 f1 c9 0d 0d 0d 0d 3e 01;
+0ef0: 18 f0 2a 71 11 7c b5 28 ec 7d b7 20 0d cd 2b 0a;
+0f00: 38 08 cd b1 0f 2b 36 00 18 8b cd 2b 0a 0f 3e 28;
+0f10: 30 01 07 95 47 cd b1 0f e5 d1 1b cb e2 cb 9c cb;
+0f20: 9a 7e 12 23 13 10 f6 2b 36 00 c3 95 0e cd 2b 0a;
+0f30: 0f 2e 27 7d 30 01 24 cd b4 0f e5 2a 71 11 30 02;
+0f40: 3e 4f 95 47 d1 1a b7 20 9c cd b1 0f 7e 36 00 23;
+0f50: cb 9c 5e 77 7b 10 f8 18 8c 21 7a 11 3a 7b 11 be;
+0f60: 28 83 cd 9d 02 7e d6 05 77 6f 26 e2 7e cd c7 09;
+0f70: c3 e5 0e cd 2b 0a 0f d2 86 0e 2e 00 24 7c fe 18;
+0f80: 28 17 30 07 cd 83 02 24 c3 66 0e 25 22 71 11 21;
+0f90: 9f 0f e5 f5 c5 d5 cd 9f 0f 22 71 11 cd 83 02 21;
+0fa0: 7a 11 3a 7f 11 be ca 1f 0e cd 83 02 7e c6 05 18;
+0fb0: b7 2a 71 11 f5 c5 d5 e5 c1 11 28 00 21 d8 cf 3a;
+0fc0: 91 11 b7 20 05 2a 7d 11 ed 52 19 05 f2 ca 0f 06;
+0fd0: 00 09 cb 9c d1 c1 f1 c9 af 18 02 3e ff 77 23 10;
+0fe0: fc c9 c5 d5 e5 01 01 e0 11 02 e0 26 64 cd 01 06;
+0ff0: 38 0b cd a2 09 1a e6 20 20 f1 25 20 f0 c3 9f 06;
+1000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+1090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
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+e520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e530: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e570: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e580: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e590: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e5a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e5b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e5c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e5d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e5e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e5f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e600: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e610: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e620: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e630: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e640: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e650: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e660: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e670: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e680: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e690: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e6a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e6b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e6c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e6d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e6e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e6f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e700: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e710: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e720: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e730: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e740: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e750: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e760: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e770: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e780: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e790: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e7a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e7b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e7c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e7d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e7e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+e7f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+END;
diff --git a/software/mif/combined_mrom.mif b/software/mif/combined_mrom.mif
new file mode 100644
index 0000000..5ac534b
--- /dev/null
+++ b/software/mif/combined_mrom.mif
@@ -0,0 +1,8198 @@
+DEPTH = 131072;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT BEGIN
+0000: c3 4a 00 c3 e6 07 c3 0e 09 c3 18 09 c3 20 09 c3;
+0010: 26 09 c3 35 09 c3 81 09 c3 99 09 c3 bd 08 c3 32;
+0020: 0a c3 36 04 c3 75 04 c3 d8 04 c3 f8 04 c3 88 05;
+0030: c3 c7 01 c3 08 03 00 00 c3 38 10 c3 58 03 c3 e5;
+0040: 02 c3 fa 02 c3 ab 02 c3 be 02 31 f0 10 ed 56 cd;
+0050: c9 0f 3e 16 cd 12 00 06 3c 21 70 11 cd d8 0f 21;
+0060: 92 03 3e c3 32 38 10 22 39 10 3e 04 32 9e 11 3c;
+0070: 32 9f 11 cd be 02 cd 09 00 11 41 01 cd 15 00 c3;
+0080: 6b 01 cd 09 00 3e 2a cd 12 00 11 a3 11 cd 03 00;
+0090: 1a fe 1b ca 82 00 fe 2a 20 01 13 21 96 01 06 04;
+00a0: cd 80 01 ca cf 00 21 9a 01 cd 80 01 ca 59 01 21;
+00b0: 9e 01 06 02 cd 80 01 ca 6b 01 21 a0 01 cd 80 01;
+00c0: ca 73 01 21 a2 01 cd 80 01 ca 77 01 c3 82 00 13;
+00d0: 13 13 13 1a fe 0d c2 04 01 cd d8 04 da a4 01 cd;
+00e0: 09 00 11 38 01 cd 15 00 11 f1 10 21 10 00 19 36;
+00f0: 0d cd 15 00 cd f8 04 da a4 01 2a 06 11 7c fe 12;
+0100: da 82 00 e9 d5 cd d8 04 da a4 01 cd 09 00 11 31;
+0110: 01 cd 15 00 11 f1 10 21 10 00 19 36 0d cd 15 00;
+0120: d1 d5 21 f1 10 06 10 cd 80 01 c2 05 01 d1 c3 df;
+0130: 00 46 4f 55 4e 44 20 0d 4c 4f 41 44 49 4e 47 20;
+0140: 0d 2a 2a 20 20 4d 4f 4e 49 54 4f 52 20 53 50 2d;
+0150: 31 30 30 32 20 20 2a 2a 0d 13 13 13 13 1a fe 24;
+0160: c2 82 00 13 cd 10 04 da 82 00 e9 3e ff 32 9d 11;
+0170: c3 82 00 af c3 6d 01 21 00 f0 7e b7 c2 82 00 e9;
+0180: c5 d5 e5 1a be 20 0b 05 28 08 fe 0d 28 04 13 23;
+0190: 18 f1 e1 d1 c1 c9 4c 4f 41 44 47 4f 54 4f 53 53;
+01a0: 53 47 46 44 fe 02 ca 82 00 cd 09 00 11 b5 01 cd;
+01b0: 15 00 c3 82 00 22 43 48 45 43 4b 20 53 55 4d 20;
+01c0: 45 52 52 4f 52 22 0d c5 d5 e5 3e 02 32 a0 11 06;
+01d0: 01 1a fe 0d 28 02 fe c8 ca 10 02 fe cf ca 03 02;
+01e0: fe d7 ca 0c 02 fe 23 21 71 02 20 04 21 89 02 13;
+01f0: cd 1c 02 da d1 01 cd c8 02 da 13 02 cd ab 02 41;
+0200: c3 d1 01 3e 03 32 a0 11 13 c3 d1 01 3e 01 18 f5;
+0210: cd c8 02 f5 cd be 02 f1 e1 d1 c1 c9 c5 06 08 1a;
+0220: be 28 09 23 23 23 10 f8 37 13 c1 c9 23 d5 5e 23;
+0230: 56 eb 7c b7 28 09 3a a0 11 3d 28 03 29 18 fa 22;
+0240: a1 11 3e 02 32 a0 11 d1 13 1a 47 e6 f0 fe 30 28;
+0250: 05 3a 9f 11 18 07 13 78 e6 0f 32 9f 11 4f 06 00;
+0260: 21 a1 02 09 4e 3a 9e 11 47 af 81 10 fd c1 4f af;
+0270: c9 43 77 07 44 a7 06 45 ed 05 46 98 05 47 fc 04;
+0280: 41 71 04 42 f5 03 52 00 00 43 0c 07 44 47 06 45;
+0290: 98 05 46 48 05 47 b4 04 41 31 04 42 bb 03 52 00;
+02a0: 00 01 02 03 04 06 08 0c 10 18 20 2a a1 11 7c b7;
+02b0: 28 0c d5 eb 21 04 e0 73 72 3e 01 d1 18 06 3e 34;
+02c0: 32 07 e0 af 32 08 e0 c9 21 00 e0 36 f9 23 7e e6;
+02d0: 08 20 02 37 c9 3a 08 e0 0f 38 fa 3a 08 e0 0f 30;
+02e0: fa 10 f2 af c9 c5 e5 21 71 04 cd ae 02 06 32 af;
+02f0: cd 5b 07 10 fa e1 c1 c3 be 02 f5 c5 e6 0f 47 3e;
+0300: 08 90 32 9e 11 c1 f1 c9 f3 c5 d5 e5 32 9b 11 3e;
+0310: f0 32 9c 11 21 c0 a8 af ed 52 e5 23 eb 3e 74 32;
+0320: 07 e0 3e b0 32 07 e0 21 06 e0 73 72 2b 36 0a 36;
+0330: 00 3e 80 32 07 e0 23 4e 7e ba 20 fb 79 bb 20 f7;
+0340: 2b 00 00 00 36 12 36 7a 23 d1 4e 7e ba 20 fb 79;
+0350: bb 20 f7 e1 d1 c1 fb c9 e5 3e 80 32 07 e0 21 06;
+0360: e0 f3 5e 56 fb 7b b2 ca 79 03 af 21 c0 a8 ed 52;
+0370: da 83 03 eb 3a 9b 11 e1 c9 11 c0 a8 3a 9b 11 ee;
+0380: 01 e1 c9 f3 21 06 e0 7e 2f 5f 7e 2f 57 fb 13 c3;
+0390: 7c 03 f5 c5 d5 e5 3a 9b 11 ee 01 32 9b 11 3e 80;
+03a0: 32 07 e0 21 06 e0 5e 56 21 c0 a8 19 2b 2b eb 21;
+03b0: 06 e0 73 72 e1 d1 c1 f1 fb c9 7c cd c3 03 7d cd;
+03c0: c3 03 c9 f5 e6 f0 0f 0f 0f 0f cd da 03 cd 12 00;
+03d0: f1 e6 0f cd da 03 cd 12 00 c9 d5 e5 21 e9 03 e6;
+03e0: 0f 5f 16 00 19 7e e1 d1 c9 30 31 32 33 34 35 36;
+03f0: 37 38 39 41 42 43 44 45 46 c5 e5 01 00 10 21 e9;
+0400: 03 be 20 03 79 18 06 23 0c 05 20 f5 37 e1 c1 c9;
+0410: d5 cd 1f 04 38 07 67 cd 1f 04 38 01 6f d1 c9 c5;
+0420: 1a 13 cd f9 03 38 0d 07 07 07 07 4f 1a 13 cd f9;
+0430: 03 38 01 b1 c1 c9 f3 d5 c5 e5 16 d7 1e cc 21 f0;
+0440: 10 01 80 00 cd 33 07 cd b2 06 da 63 05 7b fe cc;
+0450: 20 11 cd 09 00 d5 11 6c 04 cd 15 00 11 f1 10 cd;
+0460: 15 00 d1 cd b8 07 cd 8d 04 c3 63 05 57 52 49 54;
+0470: 49 4e 47 20 0d f3 d5 c5 e5 16 d7 1e 53 2a 02 11;
+0480: e5 c1 2a 04 11 78 b1 ca d4 04 c3 44 04 d5 c5 e5;
+0490: 16 02 3e f9 32 00 e0 7e cd a5 07 3a 01 e0 e6 08;
+04a0: c2 a7 04 37 c3 d4 04 23 0b 78 b1 c2 97 04 2a 97;
+04b0: 11 7c cd a5 07 7d cd a5 07 cd 80 07 15 c2 c4 04;
+04c0: b7 c3 d4 04 06 00 cd 67 07 05 c2 c6 04 e1 c1 c5;
+04d0: e5 c3 97 04 e1 c1 d1 c9 f3 d5 c5 e5 16 d2 1e cc;
+04e0: 01 80 00 21 f0 10 cd b2 06 da 82 05 cd 5e 06 da;
+04f0: 82 05 cd 10 05 c3 63 05 f3 d5 c5 e5 16 d2 1e 53;
+0500: 2a 02 11 e5 c1 2a 04 11 78 b1 ca 63 05 c3 e6 04;
+0510: d5 c5 e5 26 02 01 01 e0 11 02 e0 cd 01 06 da 82;
+0520: 05 cd 60 07 cd 60 07 cd 60 07 1a e6 20 ca 1b 05;
+0530: 54 21 00 00 22 97 11 e1 c1 c5 e5 cd 24 06 da 82;
+0540: 05 77 23 0b 78 b1 c2 3b 05 2a 97 11 cd 24 06 da;
+0550: 82 05 5f cd 24 06 da 82 05 bd c2 74 05 7b bc c2;
+0560: 74 05 af e1 c1 d1 cd 00 07 f5 3a 9c 11 fe f0 20;
+0570: 01 fb f1 c9 15 ca 7c 05 62 c3 15 05 3e 01 37 c3;
+0580: 63 05 3e 02 37 c3 63 05 f3 d5 c5 e5 2a 02 11 e5;
+0590: c1 2a 04 11 16 d2 1e 53 78 b1 ca 63 05 cd 33 07;
+05a0: cd b2 06 da 82 05 cd 5e 06 da 82 05 cd b2 05 c3;
+05b0: 63 05 d5 c5 e5 26 02 01 01 e0 11 02 e0 cd 01 06;
+05c0: da 82 05 cd 60 07 cd 60 07 cd 60 07 1a e6 20 ca;
+05d0: bd 05 54 e1 c1 c5 e5 cd 24 06 da 82 05 be c2 7c;
+05e0: 05 23 0b 78 b1 c2 d7 05 2a 99 11 cd 24 06 bc c2;
+05f0: 7c 05 cd 24 06 bd c2 7c 05 15 ca 62 05 62 c3 b7;
+0600: 05 3e f9 32 00 e0 00 0a e6 08 c2 0f 06 37 c9 1a;
+0610: e6 20 c2 07 06 0a e6 08 c2 1d 06 37 c9 1a e6 20;
+0620: ca 15 06 c9 c5 d5 e5 21 00 08 01 01 e0 11 02 e0;
+0630: cd 01 06 da 5a 06 cd 60 07 cd 60 07 cd 60 07 1a;
+0640: e6 20 ca 4f 06 e5 2a 97 11 23 22 97 11 e1 37 7d;
+0650: 17 6f 25 c2 30 06 cd 01 06 7d e1 d1 c1 c9 c5 d5;
+0660: e5 21 28 28 7b fe cc ca 6d 06 21 14 14 22 95 11;
+0670: 01 01 e0 11 02 e0 2a 95 11 cd 01 06 da ae 06 cd;
+0680: 60 07 cd 60 07 cd 60 07 1a e6 20 ca 76 06 25 c2;
+0690: 79 06 cd 01 06 da ae 06 cd 60 07 cd 60 07 cd 60;
+06a0: 07 1a e6 20 c2 76 06 2d c2 92 06 cd 01 06 e1 d1;
+06b0: c1 c9 c5 d5 e5 0e 0a 3a 02 e0 e6 10 ca c4 06 af;
+06c0: e1 d1 c1 c9 3e 06 32 03 e0 3e 07 32 03 e0 0d c2;
+06d0: b7 06 cd 09 00 7a fe d7 28 08 11 22 07 cd 18 00;
+06e0: 18 0c 11 29 07 cd 18 00 11 24 07 cd 18 00 3a 02;
+06f0: e0 e6 10 c2 bf 06 cd 44 0a c2 ee 06 37 c3 c0 06;
+0700: f5 c5 d5 06 0a 3a 02 e0 e6 10 20 04 d1 c1 f1 c9;
+0710: 3e 06 32 03 e0 3e 07 32 03 e0 05 c2 05 07 d1 c1;
+0720: f1 c9 7f 20 50 4c 41 59 0d 7f 20 52 45 43 4f 52;
+0730: 44 2e 0d c5 d5 e5 11 00 00 78 b1 20 0b eb 22 97;
+0740: 11 22 99 11 e1 d1 c1 c9 7e e5 26 08 07 30 01 13;
+0750: 25 20 f9 e1 23 0b c3 39 07 3e 0e 3d c2 5b 07 c9;
+0760: 3e 0d 3d c2 62 07 c9 f5 3e 03 32 03 e0 cd 59 07;
+0770: cd 59 07 3e 02 32 03 e0 cd 59 07 cd 59 07 f1 c9;
+0780: f5 3e 03 32 03 e0 cd 59 07 cd 59 07 cd 59 07 cd;
+0790: 59 07 3e 02 32 03 e0 cd 59 07 cd 59 07 cd 59 07;
+07a0: cd 60 07 f1 c9 c5 06 08 cd 80 07 07 dc 80 07 d4;
+07b0: 67 07 05 c2 ab 07 c1 c9 c5 d5 7b 01 f0 55 11 28;
+07c0: 28 fe cc ca cc 07 01 f8 2a 11 14 14 cd 67 07 0b;
+07d0: 78 b1 20 f8 cd 80 07 15 20 fa cd 67 07 1d 20 fa;
+07e0: cd 80 07 d1 c1 c9 f5 c5 e5 d5 af 32 93 11 cd b3;
+07f0: 09 47 3a 9d 11 b7 cc e5 02 78 e6 f0 fe c0 c2 a6;
+0800: 08 78 fe cd ca 5b 08 fe c9 ca 2b 08 fe ca ca 2b;
+0810: 08 fe cb ca b3 08 fe c8 ca 38 08 fe c7 ca 2b 08;
+0820: 3a 93 11 b7 fa 42 08 c2 31 08 78 cd dc 0d c3 ee;
+0830: 07 3d 32 93 11 c3 42 08 3a 93 11 3c 32 93 11 c3;
+0840: 2a 08 78 cd a6 0d cd b5 0d fe 62 c2 ee 07 3a 93;
+0850: 11 e6 80 ee 80 32 93 11 c3 ee 07 2a 71 11 5c 16;
+0860: 00 21 73 11 19 eb 1a b7 01 28 00 2a 71 11 c2 7a;
+0870: 08 13 1a b7 ca 7d 08 c3 7b 08 25 0e 50 2e 00 cd;
+0880: b4 0f d1 d5 c5 cd a6 0d ed b0 c1 e1 e5 41 7e cd;
+0890: ce 0b 77 23 10 f8 36 0d 2b 7e fe 20 28 f8 cd 06;
+08a0: 00 d1 e1 c1 f1 c9 3a 93 11 b7 fa 42 08 ca 42 08;
+08b0: c3 31 08 e1 e5 36 1b 23 36 0d c3 9e 08 cd ca 08;
+08c0: fe f0 20 02 af c9 cd ce 0b c9 c5 d5 e5 cd 50 0a;
+08d0: 78 07 38 06 3e f0 e1 d1 c1 c9 07 d2 ec 08 06 00;
+08e0: 21 08 00 09 11 c9 0a 19 7e c3 d6 08 3a 70 11 b7;
+08f0: c2 fd 08 06 00 21 c9 0a 09 7e c3 d6 08 79 e6 f0;
+0900: 0f 47 79 e6 0f 80 c6 a0 6f 26 00 c3 e4 08 af 32;
+0910: 94 11 3e cd cd dc 0d c9 3a 94 11 b7 c8 c3 06 00;
+0920: 3e 20 cd 35 09 c9 cd 0c 00 3a 94 11 b7 c8 d6 0a;
+0930: 38 f4 20 fa c9 fe 0d ca 0e 09 c5 4f 47 cd a6 0d;
+0940: cd 46 09 78 c1 c9 79 cd b9 0b 4f e6 f0 fe f0 c8;
+0950: fe c0 79 c2 70 09 fe c7 d2 70 09 cd dc 0d fe c3;
+0960: ca 73 09 fe c5 ca 6b 09 fe c6 c0 af 32 94 11 c9;
+0970: cd b5 0d 3a 94 11 3c fe 50 38 02 d6 50 32 94 11;
+0980: c9 f5 c5 d5 06 05 cd a6 0d 1a fe 0d ca df 0f 4f;
+0990: cd 46 09 13 10 f3 c3 84 09 f5 c5 d5 06 05 cd a6;
+09a0: 0d 1a fe 0d ca df 0f cd b9 0b cd 70 09 13 10 f1;
+09b0: c3 9c 09 c5 d5 e5 cd b1 0f cd a6 0d 7e 32 8e 11;
+09c0: 22 8f 11 21 92 11 36 ef af 32 00 e0 32 91 11 2f;
+09d0: 32 00 e0 16 14 cd ff 09 cd 50 0a 78 07 da d3 09;
+09e0: 15 c2 d5 09 cd ff 09 cd ca 08 fe f0 ca e4 09 f5;
+09f0: cd a6 0d 3a 8e 11 2a 8f 11 77 f1 e1 d1 c1 c9 f5;
+0a00: e5 3a 02 e0 07 07 da 25 0a 3a 91 11 0f da 22 0a;
+0a10: 3a 92 11 2a 8f 11 cd a6 0d 77 3a 91 11 ee 01 32;
+0a20: 91 11 e1 f1 c9 3a 91 11 0f d2 22 0a 3a 8e 11 c3;
+0a30: 13 0a 3e f8 32 00 e0 00 3a 01 e0 2f e6 21 c2 44;
+0a40: 0a c6 01 c9 3e f9 32 00 e0 00 3a 01 e0 e6 08 c9;
+0a50: d5 e5 06 fa 16 00 05 78 32 00 e0 fe ef c2 64 0a;
+0a60: 42 d1 e1 c9 fe f8 ca b2 0a 3a 01 e0 2f b7 ca 56;
+0a70: 0a 5f 7a f6 80 57 21 ad 0a 78 e6 0f 07 07 07 07;
+0a80: 4f 7b 07 30 03 3e 07 e9 07 30 03 3e 06 e9 07 30;
+0a90: 03 3e 05 e9 07 30 03 3e 04 e9 07 30 03 3e 03 e9;
+0aa0: 07 30 03 3e 02 e9 07 30 03 3e 01 e9 af 81 4f c3;
+0ab0: 56 0a 3a 01 e0 2f 5f e6 21 ca c0 0a 7a f6 40 57;
+0ac0: 7b e6 de ca 56 0a c3 71 0a 21 23 25 27 29 2a 1d;
+0ad0: 1f 61 63 65 67 69 6a 5d 5f 22 24 26 28 20 1c 1e;
+0ae0: d1 62 64 66 68 60 5c 5e d0 11 05 14 15 0f 2b 31;
+0af0: 33 51 45 54 55 4f 6b 71 73 17 12 19 09 10 30 32;
+0b00: d3 57 52 59 49 50 70 72 d2 01 04 07 0a 0c 1b 35;
+0b10: 37 41 44 47 4a 4c 5b 75 77 13 06 08 0b 2c 34 36;
+0b20: d5 53 46 48 4b 6c 74 76 d4 1a 03 02 0d 2e c9 39;
+0b30: 3b 5a 43 42 4d 6e ca 79 7b 18 16 0e 2f 2d 38 3a;
+0b40: d7 58 56 4e 6f 6d 78 7a d6 f0 c7 f0 c3 cd f0 3d;
+0b50: 3f f0 c8 f0 c4 cd f0 7d 7f c5 00 c1 f0 f0 3c 3e;
+0b60: dc c6 00 c2 cb f0 7c 7e d8 a1 a3 a5 a7 a9 aa 9d;
+0b70: 9f a2 a4 a6 a8 a0 9c 9e dd 91 85 94 95 8f ab b1;
+0b80: b3 97 92 99 89 90 b0 b2 de 81 84 87 8a 8c 9b b5;
+0b90: b7 93 86 88 8b ac b4 b6 d9 9a 83 82 8d ae c9 b9;
+0ba0: bb 98 96 8e af ad b8 ba da f0 c7 f0 c3 cd f0 bd;
+0bb0: bf c5 00 c1 f0 f0 bc be db d6 10 d2 c1 0b 3e f0;
+0bc0: c9 c5 e5 21 d6 0b 4f 06 00 09 7e e1 c1 c9 c5 e5;
+0bd0: 21 c6 0c c3 c6 0b f0 c1 c2 c3 c4 c5 c6 f0 f0 f0;
+0be0: f0 f0 f0 f0 f0 f0 00 61 62 63 64 65 66 67 68 69;
+0bf0: 6b 6a 2f 2a 2e 2d 20 21 22 23 24 25 26 27 28 29;
+0c00: 4f 2c 51 2b 57 49 55 01 02 03 04 05 06 07 08 09;
+0c10: 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19;
+0c20: 1a 52 59 54 50 45 c7 c8 c9 ca cb cc cd ce cf df;
+0c30: e7 e8 e9 ea ec ed d0 d1 d2 d3 d4 d5 d6 d7 d8 d9;
+0c40: da db dc dd de c0 00 bd 9d b1 b5 b9 b4 9e b2 b6;
+0c50: ba be 9f b3 b7 bb bf a3 85 a4 a5 a6 94 87 88 9c;
+0c60: 82 98 84 92 90 83 91 81 9a 97 93 95 89 a1 af 8b;
+0c70: 86 96 a2 ab aa 8a 8e b0 ad 8d a7 a8 a9 8f 8c ae;
+0c80: ac 9b a0 99 bc b8 00 3b 3a 70 3c 71 5a 3d 43 56;
+0c90: 3f 1e 4a 1c 5d 3e 5c 1f 5f 5e 37 7b 7f 36 7a 7e;
+0ca0: 33 4b 4c 1d 6c 5b 78 41 35 34 74 30 38 75 39 4d;
+0cb0: 6f 6e 32 77 76 72 73 47 7c 53 31 4e 6d 48 46 7d;
+0cc0: 44 1b 58 79 42 60 20 41 42 43 44 45 46 47 48 49;
+0cd0: 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59;
+0ce0: 5a fb cd dd cb d1 30 31 32 33 34 35 36 37 38 39;
+0cf0: 2d 3d 3b 2f 2e 2c e5 f4 ec da e3 e2 d7 d4 e6 e8;
+0d00: c2 c1 c4 c7 cf ca 20 e1 fe c8 fa 5f f8 f1 f7 3f;
+0d10: cc db dc e9 f5 3a 5e 3c 5b f3 5d 40 c9 3e fc 5c;
+0d20: c6 df d0 ce d3 d2 ff 21 22 23 24 25 26 27 28 29;
+0d30: 2b 2a de f6 eb ea c3 c5 ef f0 e4 e7 ee ed e0 fd;
+0d40: d8 d5 f2 f9 d9 d6 20 a1 9a 9f 9c 92 aa 97 98 a6;
+0d50: af a9 b8 b3 b0 b7 9e a0 9d a4 96 a5 ab a3 9b bd;
+0d60: a2 bb 99 82 87 8c bc a7 ac 91 93 94 95 b4 b5 b6;
+0d70: ae ad ba b2 b9 a8 b1 83 88 8d 86 84 89 8e bf 85;
+0d80: 8a 8f be 81 8b 90 7f 11 12 13 14 15 16 60 61 62;
+0d90: 63 64 65 66 67 68 70 71 72 73 74 75 76 77 78 79;
+0da0: 7a 7b 7c 7d 7e 69 f5 3a 02 e0 07 30 fa 3a 02 e0;
+0db0: 07 38 fa f1 c9 f5 c5 d5 e5 47 cd b1 0f 70 2a 71;
+0dc0: 11 7d fe 27 c2 90 0e 5c 16 00 21 73 11 19 7e b7;
+0dd0: c2 90 0e 23 36 01 23 36 00 c3 90 0e f5 c5 d5 e5;
+0de0: 47 e6 f0 fe c0 c2 de 0f a8 07 07 4f 06 00 21 f3;
+0df0: 0d 09 e9 c3 32 0e 00 c3 74 0e 00 c3 84 0e 00 c3;
+0e00: 90 0e 00 c3 ae 0e 00 c3 bf 0e 00 c3 c5 0e 00 c3;
+0e10: f8 0e 00 c3 49 0f 00 c3 e1 0e 00 c3 ee 0e 00 c3;
+0e20: de 0f 00 c3 de 0f 00 c3 8b 0f 00 c3 de 0f 00 c3;
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+1ee0: 0e 3e 05 32 03 e0 3e 00 32 70 11 c3 de 0f 3e 04;
+1ef0: 32 03 e0 3e 01 c3 e8 0e 2a 71 11 7c b5 ca de 0f;
+1f00: 7d b7 c2 1d 0f 5c 16 00 21 73 11 19 7e b7 c2 1d;
+1f10: 0f cd b1 0f cd a6 0d 2b 36 00 c3 ae 0e 2a 71 11;
+1f20: 5c 1c 16 00 21 73 11 19 7e 47 b7 3e 28 28 02 3e;
+1f30: 50 2a 71 11 95 4f 06 00 cd b1 0f e5 d1 1b cd a6;
+1f40: 0d ed b0 2b 36 00 c3 ae 0e 2a 71 11 5c 1c 16 00;
+1f50: 21 73 11 19 7e b7 0e 00 2a 71 11 2e 27 28 02 24;
+1f60: 0c cd b4 0f 7e b7 c2 de 0f e5 2a 71 11 3e 27 95;
+1f70: 47 79 b7 28 04 3e 28 80 47 d1 d5 e1 2b cd a6 0d;
+1f80: 7e 12 36 00 2b 1b 10 f8 c3 de 0f 2a 71 11 5c 1c;
+1f90: 16 00 21 73 11 19 7e b7 2a 71 11 ca 9d 0e 2e 00;
+1fa0: 7c fe 17 28 05 24 24 c3 7e 0e 24 22 71 11 c3 32;
+1fb0: 0e 2a 71 11 c5 d5 e5 c1 11 28 00 21 d8 cf 19 05;
+1fc0: f2 be 0f 06 00 09 d1 c1 c9 21 03 e0 36 8a 36 07;
+1fd0: 36 05 3e 01 32 03 e0 c9 af 77 23 10 fc c9 e1 d1;
+1fe0: c1 f1 c9 ae cd ee ff ae fe ac de 4e ff ae df ae;
+1ff0: df 2f ff 26 7d fe fd ee fd ac df 7e df ae df ff;
+2000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+20a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+20b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+20c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+20d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+20e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+20f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+21a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+21b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+21c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+21d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+21e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+21f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+22a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+22b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+22c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+22d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+22e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+22f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+23a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+23b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+23c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+23d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+23e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+23f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+24a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+24b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+24c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+24d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+24e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+24f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+25a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+25b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+25c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+25d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+25e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+25f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+26a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+26b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+26c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+26d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+26e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+26f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+27a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+27b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+27c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+27d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+27e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+27f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+28a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+28b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+28c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+28d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+28e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+28f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+29a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+29b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+29c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+29d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+29e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+29f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+2ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+30a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+30b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+30c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+30d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+30e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+30f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+31a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+31b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+31c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+31d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+31e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+31f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+32a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+32b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+32c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+32d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+32e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+32f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+33a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+33b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+33c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+33d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+33e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+33f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+3420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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+5680: 11 c3 de 0f 2a 71 11 7c b7 ca de 0f 25 c3 7e 0e;
+5690: 2a 71 11 7d fe 27 d2 9d 0e 2c c3 7e 0e 2e 00 24;
+56a0: 7c fe 19 da 7e 0e 26 18 22 71 11 c3 32 0e 2a 71;
+56b0: 11 7d b7 28 04 2d c3 7e 0e 2e 27 25 f2 7e 0e 21;
+56c0: 00 00 c3 7e 0e cd a6 0d 0e 19 21 00 d0 06 28 cd;
+56d0: d8 0f 0d c2 cd 0e 21 73 11 06 1b cd d8 0f c3 bf;
+56e0: 0e 21 70 11 af be 18 01 3c 77 d6 06 2f 32 03 e0;
+56f0: 18 8f 21 70 11 af 18 f0 2a 71 11 7c b5 ca de 0f;
+5700: 7d b7 20 16 5c 16 00 21 73 11 19 7e b7 20 0b cd;
+5710: b1 0f cd a6 0d 2b 36 00 18 94 2a 71 11 5c 1c 16;
+5720: 00 21 73 11 19 7e 47 b7 3e 28 28 02 3e 50 2a 71;
+5730: 11 95 4f 06 00 cd b1 0f e5 d1 1b cd a6 0d ed b0;
+5740: 18 d3 cd f4 00 c3 ee 07 00 2a 71 11 5c 1c 16 00;
+5750: 21 73 11 19 7e b7 0e 00 2a 71 11 2e 27 28 02 24;
+5760: 0c cd b4 0f 7e b7 c2 de 0f e5 2a 71 11 3e 27 95;
+5770: 47 79 b7 28 04 3e 28 80 47 d1 d5 e1 2b cd a6 0d;
+5780: 7e 12 36 00 2b 1b 10 f8 c3 de 0f 2a 71 11 5c 1c;
+5790: 16 00 21 73 11 19 7e b7 2a 71 11 ca 9d 0e 2e 00;
+57a0: 7c fe 17 28 05 24 24 c3 7e 0e 24 22 71 11 c3 32;
+57b0: 0e 2a 71 11 c5 d5 e5 c1 11 28 00 21 d8 cf 19 05;
+57c0: f2 be 0f 06 00 09 d1 c1 c9 21 03 e0 36 8a 36 07;
+57d0: 36 05 3e 01 32 03 e0 c9 af 77 23 10 fc c9 e1 d1;
+57e0: c1 f1 c9 3e 3a d7 2a 04 11 cd ba 03 eb 2a 02 11;
+57f0: 19 2b cd f8 0f 2a 06 11 3e 2d d7 cd ba 03 af ff;
+5800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+58a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+58b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+58c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+58d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+58e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+58f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+59a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+59b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+59c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+59d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+59e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+59f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+5ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+60a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+60b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+60c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+60d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+60e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+60f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+61a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+61b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+61c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+61d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+61e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+61f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+62a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+62b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+62c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+62d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+62e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+62f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+63a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+63b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+63c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+63d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+63e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+63f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+64a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+64b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+64c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+64d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+64e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+64f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+65a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+65b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+65c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+65d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+65e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+65f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+66a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+66b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+66c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+66d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+66e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+66f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+67a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+67b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+67c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+67d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+67e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+67f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+68a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+68b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+68c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+68d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+68e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+68f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+69a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+69b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+69c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+69d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+69e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+69f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+6ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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+8e10: f8 0e 00 c3 49 0f 00 c3 e1 0e 00 c3 ee 0e 00 c3;
+8e20: de 0f 00 c3 de 0f 00 c3 8b 0f 00 c3 de 0f 00 c3;
+8e30: de 0f cd a6 0d af 32 03 e0 01 c0 03 11 00 d0 21;
+8e40: 28 d0 ed b0 eb 06 28 cd d8 0f 01 1a 00 11 73 11;
+8e50: 21 73 11 23 ed b0 36 00 3a 73 11 b7 c2 6a 0e cd;
+8e60: a6 0d 3e 01 32 03 e0 c3 de 0f 2a 71 11 25 22 71;
+8e70: 11 c3 39 0e 2a 71 11 7c fe 18 ca 32 0e 24 22 71;
+8e80: 11 c3 de 0f 2a 71 11 7c b7 ca de 0f 25 c3 7e 0e;
+8e90: 2a 71 11 7d fe 27 d2 9d 0e 2c c3 7e 0e 2e 00 24;
+8ea0: 7c fe 19 da 7e 0e 26 18 22 71 11 c3 32 0e 2a 71;
+8eb0: 11 7d b7 28 04 2d c3 7e 0e 2e 27 25 f2 7e 0e 21;
+8ec0: 00 00 c3 7e 0e cd a6 0d 0e 19 21 00 d0 06 28 cd;
+8ed0: d8 0f 0d c2 cd 0e 21 73 11 06 1b cd d8 0f c3 bf;
+8ee0: 0e 3e 05 32 03 e0 3e 00 32 70 11 c3 de 0f 3e 04;
+8ef0: 32 03 e0 3e 01 c3 e8 0e 2a 71 11 7c b5 ca de 0f;
+8f00: 7d b7 c2 1d 0f 5c 16 00 21 73 11 19 7e b7 c2 1d;
+8f10: 0f cd b1 0f cd a6 0d 2b 36 00 c3 ae 0e 2a 71 11;
+8f20: 5c 1c 16 00 21 73 11 19 7e 47 b7 3e 28 28 02 3e;
+8f30: 50 2a 71 11 95 4f 06 00 cd b1 0f e5 d1 1b cd a6;
+8f40: 0d ed b0 2b 36 00 c3 ae 0e 2a 71 11 5c 1c 16 00;
+8f50: 21 73 11 19 7e b7 0e 00 2a 71 11 2e 27 28 02 24;
+8f60: 0c cd b4 0f 7e b7 c2 de 0f e5 2a 71 11 3e 27 95;
+8f70: 47 79 b7 28 04 3e 28 80 47 d1 d5 e1 2b cd a6 0d;
+8f80: 7e 12 36 00 2b 1b 10 f8 c3 de 0f 2a 71 11 5c 1c;
+8f90: 16 00 21 73 11 19 7e b7 2a 71 11 ca 9d 0e 2e 00;
+8fa0: 7c fe 17 28 05 24 24 c3 7e 0e 24 22 71 11 c3 32;
+8fb0: 0e 2a 71 11 c5 d5 e5 c1 11 28 00 21 d8 cf 19 05;
+8fc0: f2 be 0f 06 00 09 d1 c1 c9 21 03 e0 36 8a 36 07;
+8fd0: 36 05 3e 01 32 03 e0 c9 af 77 23 10 fc c9 e1 d1;
+8fe0: c1 f1 c9 ae cd ee ff ae fe ac de 4e ff ae df ae;
+8ff0: df 2f ff 26 7d fe fd ee fd ac df 7e df ae df ff;
+9000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+90a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+90b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+90c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+90d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+90e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+90f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+91a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+91b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+91c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+91d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+91e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+91f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+92a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+92b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+92c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+92d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+92e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+92f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+93a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+93b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+93c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+93d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+93e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+93f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+94a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+94b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+94c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+94d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+94e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+94f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+95a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+95b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+95c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+95d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+95e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+95f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+96a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+96b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+96c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+96d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+96e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+96f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+97a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+97b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+97c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+97d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+97e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+97f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+98a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+98b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+98c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+98d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+98e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+98f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+99a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+99b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+99c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+99d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+99e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+99f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+9ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a0a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a0b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a0c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a0d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a0e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a0f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a1a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a1b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a1c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a1d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a1e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a1f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a2a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a2b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a2c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a2d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+a2e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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+c570: 07 cd 59 07 cd 59 07 cd 60 07 f1 c9 fe 08 28 10;
+c580: cb 0e 10 fc cb c6 cb 8e 47 cb 06 10 fc c3 7b 0e;
+c590: 23 cb c6 cb 8e 18 f6 cb fe 23 cb 86 18 ef 7f 20;
+c5a0: 50 4c 41 59 0d f3 c9 c5 06 23 cd a2 09 10 fb c1;
+c5b0: c9 d7 41 30 0d f5 c5 d5 e5 47 cd b1 0f 70 2a 71;
+c5c0: 11 7d fe 4f 20 c7 cd 2b 0a 38 c2 3a 91 11 b7 c2;
+c5d0: 9d 03 eb 78 fe 07 28 bf 18 a2 24 f3 f5 c5 d5 e5;
+c5e0: 47 e6 f0 fe c0 c2 e5 0e a8 07 4f 06 00 21 ff 0d;
+c5f0: 3a 91 11 b7 28 03 21 68 01 09 5e 23 56 eb e9 1f;
+c600: 0e 5d 0e 6e 0e 7b 0e 95 0e fb 03 b3 0e f2 0e 2d;
+c610: 0f e1 0e ee 0e e5 0e 17 0a 73 0f e8 05 59 0f 21;
+c620: 7a 11 0e 05 3a 7f 11 81 32 7f 11 3a 7b 11 81 32;
+c630: 7b 11 79 86 77 cd c7 09 2a 7d 11 11 d0 07 19 06;
+c640: 50 af cb 9c 77 23 10 fa 3a 7a 11 6f 26 e2 7e 21;
+c650: 79 11 b7 06 07 cb 1e 2b 10 fb c3 e5 0e 2a 71 11;
+c660: 7c fe 18 28 2e 24 cd 83 02 22 71 11 18 77 2a 71;
+c670: 11 7c b7 28 35 25 cd 9d 02 18 ee 2a 71 11 7d fe;
+c680: 4f 30 03 2c 18 e3 2e 00 24 7c fe 19 38 d8 26 18;
+c690: 22 71 11 18 42 2a 71 11 7d b7 28 03 2d 18 ca 2e;
+c6a0: 4f 25 f2 76 0e 26 00 22 71 11 3a 91 11 b7 20 35;
+c6b0: c3 59 0f 21 73 11 06 1b cd d8 0f 21 00 d0 e5 cd;
+c6c0: e2 09 e1 3a 91 11 b7 20 08 22 7d 11 3e 7d 32 7f;
+c6d0: 11 3a 00 e2 c3 09 04 3a 91 11 b7 c2 3d 01 c3 9f;
+c6e0: 0f af 32 70 11 e1 d1 c1 f1 c9 0d 0d 0d 0d 3e 01;
+c6f0: 18 f0 2a 71 11 7c b5 28 ec 7d b7 20 0d cd 2b 0a;
+c700: 38 08 cd b1 0f 2b 36 00 18 8b cd 2b 0a 0f 3e 50;
+c710: 30 01 07 95 47 cd b1 0f e5 d1 1b cb e2 cb 9c cb;
+c720: 9a 7e 12 23 13 10 f6 2b 36 00 c3 95 0e cd 2b 0a;
+c730: 0f 2e 4f 7d 30 01 24 cd b4 0f e5 2a 71 11 30 02;
+c740: 3e 9f 95 47 d1 1a b7 20 9c cd b1 0f 7e 36 00 23;
+c750: cb 9c 5e 77 7b 10 f8 18 8c 21 7a 11 3a 7b 11 be;
+c760: 28 83 cd 9d 02 7e d6 05 77 6f 26 e2 7e cd c7 09;
+c770: c3 e5 0e cd 2b 0a 0f d2 86 0e 2e 00 24 7c fe 18;
+c780: 28 17 30 07 cd 83 02 24 c3 66 0e 25 22 71 11 21;
+c790: 9f 0f e5 f5 c5 d5 cd 9f 0f 22 71 11 cd 83 02 21;
+c7a0: 7a 11 3a 7f 11 be ca 1f 0e cd 83 02 7e c6 05 18;
+c7b0: b7 2a 71 11 f5 c5 d5 e5 c1 11 50 00 21 b0 cf 3a;
+c7c0: 91 11 b7 20 05 2a 7d 11 ed 52 19 05 f2 ca 0f 06;
+c7d0: 00 09 cb 9c d1 c1 f1 c9 af 18 02 3e ff 77 23 10;
+c7e0: fc c9 c5 d5 e5 01 01 e0 11 02 e0 26 64 cd 01 06;
+c7f0: 38 0b cd a2 09 1a e6 20 20 f1 25 20 f0 c3 9f 06;
+c800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c8a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c8b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c8c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c8d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c8e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c8f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c9a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c9b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c9c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c9d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c9e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+c9f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ca90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+caa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+caf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cb90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cbb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cbc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cbd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cbe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cbf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cc90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ccb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ccc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ccd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ccf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cd90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cda0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cdb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cdc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cdd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cde0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cdf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ce90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ceb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+ced0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cf90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cfa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cfb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cfc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cfd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cfe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+cff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d0a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d0b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d0c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d0d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d0e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d0f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d1a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d1b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d1c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d1d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d1e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d1f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d2a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d2b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d2c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d2d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d2e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d2f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d3a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d3b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d3c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d3d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d3e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d3f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d4a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d4b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d4c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d4d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d4e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d4f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d5a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d5b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d5c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d5d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d5e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d5f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d6a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d6b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d6c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d6d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d6e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d6f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d7a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d7b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d7c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d7d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d7e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d7f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d8a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d8b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d8c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d8d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d8e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d8f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d9a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d9b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d9c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d9d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d9e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+d9f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+da00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+da10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+da20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+da30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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+e9e0: f9 d1 c9 f5 e5 3a 02 e0 07 07 38 8f 3a 92 11 cd;
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+ebd0: d5 21 92 0a 54 5d 01 00 01 ed b1 28 06 3e f0 d1;
+ebe0: e1 c1 c9 b7 2b ed 52 7d 18 f5 bf ca 58 c9 f0 2c;
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+ec20: 2f 2e c8 c7 c2 c1 c3 c4 49 2d bf ca 1b c9 f0 6a;
+ec30: 6b cd 99 9a a4 bc 40 f0 f0 f0 91 92 93 94 95 96;
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+fd20: b9 c6 c5 c2 c1 c3 c4 bb be cd 3d 01 cd a6 02 e5;
+fd30: cd 10 04 d1 38 52 eb 06 08 0e 17 cd fa 05 cd b1;
+fd40: 03 23 f5 3a 71 11 81 32 71 11 f1 fe 20 30 02 3e;
+fd50: 2e cd b9 0b cd 6c 09 3a 71 11 0c 91 32 71 11 0d;
+fd60: 0d 0d e5 ed 52 e1 28 1d 3e f8 32 00 e0 00 3a 01;
+fd70: e0 fe fe 20 03 cd a6 0d 10 c4 cd ca 08 b7 28 fa;
+fd80: cd 32 0a 20 b2 c3 ad 00 21 a0 00 19 18 a8 00 00;
+fd90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+fda0: 00 00 00 00 00 00 f5 3a 02 e0 07 30 fa 3a 02 e0;
+fdb0: 07 38 fa f1 c9 f5 c5 d5 e5 cd b1 0f 77 2a 71 11;
+fdc0: 7d fe 4f 20 0b cd f3 02 38 06 eb 36 01 23 36 00;
+fdd0: 3e c3 18 0c 3a 70 11 fe 01 3e ca c9 f5 c5 d5 e5;
+fde0: 47 e6 f0 fe c0 20 1b a8 07 4f 06 00 21 aa 0e 09;
+fdf0: 5e 23 56 2a 71 11 eb e9 eb 7c fe 18 28 25 24 22;
+fe00: 71 11 c3 e5 0e eb 7c b7 28 f8 25 18 f2 eb 7d fe;
+fe10: 4f 30 03 2c 18 e9 2e 00 24 7c fe 19 38 e1 26 18;
+fe20: 22 71 11 18 48 eb 7d b7 28 03 2d 18 d2 2e 4f 25;
+fe30: f2 0b 0e 26 00 22 71 11 18 c8 21 73 11 06 1b cd;
+fe40: d8 0f 21 00 d0 cd d4 09 3e 71 cd d5 09 21 00 00;
+fe50: 18 ad 00 00 00 00 00 00 00 00 cd f3 02 0f 30 b6;
+fe60: 2e 00 24 fe 18 28 03 24 18 95 22 71 11 01 80 07;
+fe70: 11 00 d0 21 50 d0 c5 ed b0 c1 d5 11 00 d8 21 50;
+fe80: d8 ed b0 06 50 eb 3e 71 cd dd 0f e1 06 50 cd d8;
+fe90: 0f 01 1a 00 11 73 11 21 74 11 ed b0 36 00 3a 73;
+fea0: 11 b7 28 41 21 72 11 35 18 c3 6d 0e f8 0d 05 0e;
+feb0: 0d 0e 25 0e 4d 0e 3a 0e f8 0e 38 0f e1 0e ee 0e;
+fec0: e5 0e e5 0e 5a 0e e5 0e e5 0e cb dc 7e 23 77 2b;
+fed0: cb 9c ed a8 79 b0 20 f2 eb 36 00 cb dc 36 71 18;
+fee0: 04 af 32 70 11 e1 d1 c1 f1 c9 00 00 00 00 cd d4;
+fef0: 0d ca b9 0d 3e 01 18 ea eb 7c b5 28 e8 7d b7 20;
+ff00: 0d cd f3 02 38 08 cd b1 0f 2b 36 00 18 25 cd f3;
+ff10: 02 0f 3e 50 30 01 07 95 47 cd b1 0f 7e 2b 77 23;
+ff20: cb dc 7e 2b 77 cb 9c 23 23 10 f1 2b 36 00 cb dc;
+ff30: 21 71 00 3e c4 c3 e0 0d cd f3 02 0f 2e 4f 7d 30;
+ff40: 01 24 cd b4 0f e5 2a 71 11 30 02 3e 9f 95 06 00;
+ff50: 4f d1 28 91 1a b7 20 8d 62 6b 2b c3 ca 0e cd 3d;
+ff60: 01 22 04 11 44 4d cd a6 02 cd 3d 01 ed 42 23 22;
+ff70: 02 11 cd a6 02 cd 3d 01 22 06 11 cd 09 00 11 8b;
+ff80: 09 df cd 2f 01 cd a6 02 cd a6 02 21 f1 10 13 1a;
+ff90: 77 23 fe 0d 20 f8 3e 01 32 f0 10 cd 36 04 da 07;
+ffa0: 01 cd 75 04 da 07 01 cd 09 00 11 42 09 df c3 ad;
+ffb0: 00 2a 71 11 f5 c5 d5 e5 c1 11 50 00 21 b0 cf 19;
+ffc0: 05 f2 bf 0f 06 00 09 d1 c1 f1 c9 cd 88 05 da 07;
+ffd0: 01 11 42 09 df c3 ad 00 af 18 02 3e ff 77 23 10;
+ffe0: fc c9 c5 d5 e5 01 01 e0 11 02 e0 26 64 cd 01 06;
+fff0: 38 0b cd 4a 0a 1a e6 20 20 f1 25 20 f0 c3 9b 06;
+10000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+100a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+100b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+100c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+100d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+100e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+100f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+101a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+101b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+101c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+101d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+101e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+101f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+102a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+102b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+102c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+102d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+102e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+102f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+103a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+103b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+103c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+103d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+103e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+103f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+104a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+104b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+104c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+104d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+104e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+104f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+105a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+105b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+105c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+105d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+105e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+105f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+106a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+106b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+106c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+106d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+106e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+106f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+107a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+107b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+107c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+107d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+107e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+107f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+108a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+108b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+108c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+108d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+108e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+108f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+109a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+109b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+109c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+109d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+109e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+109f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+10ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+110a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+110b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+110c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+110d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+110e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+110f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+11190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+111a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+111b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+111c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+111d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+111e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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+134f0: cd 35 77 d7 b3 b7 f0 f0 f0 7c 70 41 31 39 a6 78;
+13500: dd 3d 5d 6c 56 1d 33 d5 b1 46 6e d9 48 74 43 4c;
+13510: 73 3f 36 7e 3b 7a 1e 5f a2 d3 9f d1 00 9d a3 d0;
+13520: b9 c6 c5 c2 c1 c3 c4 bb be cd 3d 01 cd a6 02 e5;
+13530: cd 10 04 d1 38 52 eb 06 08 0e 17 cd fa 05 cd b1;
+13540: 03 23 f5 3a 71 11 81 32 71 11 f1 fe 20 30 02 3e;
+13550: 2e cd b9 0b cd 6c 09 3a 71 11 0c 91 32 71 11 0d;
+13560: 0d 0d e5 ed 52 e1 28 1d 3e f8 32 00 e0 00 3a 01;
+13570: e0 fe fe 20 03 cd a6 0d 10 c4 cd ca 08 b7 28 fa;
+13580: cd 32 0a 20 b2 c3 ad 00 21 a0 00 19 18 a8 00 00;
+13590: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+135a0: 00 00 00 00 00 00 f5 3a 02 e0 07 30 fa 3a 02 e0;
+135b0: 07 38 fa f1 c9 f5 c5 d5 e5 cd b1 0f 77 2a 71 11;
+135c0: 7d fe 4f 20 0b cd f3 02 38 06 eb 36 01 23 36 00;
+135d0: 3e c3 18 0c 3a 70 11 fe 01 3e ca c9 f5 c5 d5 e5;
+135e0: 47 e6 f0 fe c0 20 1b a8 07 4f 06 00 21 aa 0e 09;
+135f0: 5e 23 56 2a 71 11 eb e9 eb 7c fe 18 28 25 24 22;
+13600: 71 11 c3 e5 0e eb 7c b7 28 f8 25 18 f2 eb 7d fe;
+13610: 4f 30 03 2c 18 e9 2e 00 24 7c fe 19 38 e1 26 18;
+13620: 22 71 11 18 48 eb 7d b7 28 03 2d 18 d2 2e 4f 25;
+13630: f2 0b 0e 26 00 22 71 11 18 c8 21 73 11 06 1b cd;
+13640: d8 0f 21 00 d0 cd d4 09 3e 71 cd d5 09 21 00 00;
+13650: 18 ad 00 00 00 00 00 00 00 00 cd f3 02 0f 30 b6;
+13660: 2e 00 24 fe 18 28 03 24 18 95 22 71 11 01 80 07;
+13670: 11 00 d0 21 50 d0 c5 ed b0 c1 d5 11 00 d8 21 50;
+13680: d8 ed b0 06 50 eb 3e 71 cd dd 0f e1 06 50 cd d8;
+13690: 0f 01 1a 00 11 73 11 21 74 11 ed b0 36 00 3a 73;
+136a0: 11 b7 28 41 21 72 11 35 18 c3 6d 0e f8 0d 05 0e;
+136b0: 0d 0e 25 0e 4d 0e 3a 0e f8 0e 38 0f e1 0e ee 0e;
+136c0: e5 0e e5 0e 5a 0e e5 0e e5 0e cb dc 7e 23 77 2b;
+136d0: cb 9c ed a8 79 b0 20 f2 eb 36 00 cb dc 36 71 18;
+136e0: 04 af 32 70 11 e1 d1 c1 f1 c9 00 00 00 00 cd d4;
+136f0: 0d ca b9 0d 3e 01 18 ea eb 7c b5 28 e8 7d b7 20;
+13700: 0d cd f3 02 38 08 cd b1 0f 2b 36 00 18 25 cd f3;
+13710: 02 0f 3e 50 30 01 07 95 47 cd b1 0f 7e 2b 77 23;
+13720: cb dc 7e 2b 77 cb 9c 23 23 10 f1 2b 36 00 cb dc;
+13730: 21 71 00 3e c4 c3 e0 0d cd f3 02 0f 2e 4f 7d 30;
+13740: 01 24 cd b4 0f e5 2a 71 11 30 02 3e 9f 95 06 00;
+13750: 4f d1 28 91 1a b7 20 8d 62 6b 2b c3 ca 0e cd 3d;
+13760: 01 22 04 11 44 4d cd a6 02 cd 3d 01 ed 42 23 22;
+13770: 02 11 cd a6 02 cd 3d 01 22 06 11 cd 09 00 11 8b;
+13780: 09 df cd 2f 01 cd a6 02 cd a6 02 21 f1 10 13 1a;
+13790: 77 23 fe 0d 20 f8 3e 01 32 f0 10 cd 36 04 da 07;
+137a0: 01 cd 75 04 da 07 01 cd 09 00 11 42 09 df c3 ad;
+137b0: 00 2a 71 11 f5 c5 d5 e5 c1 11 50 00 21 b0 cf 19;
+137c0: 05 f2 bf 0f 06 00 09 d1 c1 f1 c9 cd 88 05 da 07;
+137d0: 01 11 42 09 df c3 ad 00 af 18 02 3e ff 77 23 10;
+137e0: fc c9 c5 d5 e5 01 01 e0 11 02 e0 26 64 cd 01 06;
+137f0: 38 0b cd 4a 0a 1a e6 20 20 f1 25 20 f0 c3 9b 06;
+13800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+138a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+138b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+138c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+138d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+138e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+138f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+139a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+139b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+139c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+139d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+139e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+139f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+13ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+140a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+140b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+140c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+140d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+140e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+140f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+141a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+141b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+141c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+141d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+141e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+141f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+142a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+142b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+142c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+142d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+142e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+142f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+143a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+143b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+143c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+143d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+143e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+143f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+144a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+144b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+144c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+144d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+144e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+144f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+145a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+145b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+145c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+145d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+145e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+145f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+146a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+146b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+146c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+146d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+146e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+146f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+147a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+147b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+147c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+147d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+147e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+147f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+148a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+148b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+148c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+148d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+148e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+148f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+14980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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+15050: f0 b0 d3 e8 db ea c9 cd 5f 00 ca 3c 03 18 0c 3e;
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+15070: 02 cd ce 01 cd ae 00 38 17 cd 30 02 21 01 cf 1e;
+15080: 10 0e 10 cd 39 02 3a 00 cf fe 01 20 11 cd cf 00;
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+150a0: 03 1e 0a 0e 0f cd 46 02 cd b5 01 37 18 e2 f3 16;
+150b0: 04 01 80 00 21 00 cf cd 86 01 38 0e cd 52 01 38;
+150c0: 09 cd db 00 38 04 cb 5a 28 03 cd b5 01 fb c9 f3;
+150d0: 16 08 ed 4b 12 cf 21 00 80 18 dc d5 c5 e5 26 02;
+150e0: cd 7a 01 38 38 28 f9 54 21 00 00 22 e0 ff e1 c1;
+150f0: c5 e5 cd 32 01 38 26 77 23 0b 78 b1 20 f4 2a e0;
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+15c50: 60 2c fd 74 04 fd 75 05 3a ec ff fe 04 30 18 fd;
+15c60: 7e 04 fe 46 30 11 fd 7e 05 b7 28 0b fe 11 30 07;
+15c70: fd 7e 02 fd b6 03 c0 c3 56 05 f3 cd 3f 04 3e 0a;
+15c80: 32 eb ff cd 99 03 fd 56 03 fd 7e 02 b7 28 01 14;
+15c90: fd 7e 05 fd 77 01 fd 7e 04 fd 77 00 dd e5 e1 cb;
+15ca0: 3f 2f d3 db 30 04 3e 01 18 02 3e 00 2f d3 dd cd;
+15cb0: e2 03 20 6a 0e db fd 7e 00 cb 3f 2f d3 d9 fd 7e;
+15cc0: 01 2f d3 da d9 21 f7 04 e5 d9 3e 94 2f d3 d8 cd;
+15cd0: 2d 05 06 00 db d8 0f d8 0f 38 f9 ed a2 20 f5 fd;
+15ce0: 34 01 fd 7e 01 fe 11 28 05 15 20 e6 18 01 15 3e;
+15cf0: d8 2f d3 d8 cd 21 04 db d8 2f e6 ff 20 20 d9 e1;
+15d00: d9 fd 7e 01 fe 11 20 08 3e 01 fd 77 01 fd 34 00;
+15d10: 7a b7 20 05 3e 80 d3 dc c9 fd 7e 00 18 81 3a eb;
+15d20: ff 3d 32 eb ff 28 2f cd 09 04 c3 83 04 d5 e5 cd;
+15d30: d6 05 1e 08 21 00 00 2b 7c b5 28 09 db d8 2f 0f;
+15d40: 30 f5 e1 d1 c9 1d 20 ec 18 0c 21 ee 02 1e 07 0e;
+15d50: 1b cd 46 02 18 03 cd 3f 02 cd f3 03 31 e0 ff cd;
+15d60: 5f 00 20 47 21 b3 02 1e 5a 0e 0c cd 39 02 1e ab;
+15d70: 0e 11 cd 39 02 1e d3 0e 0f cd 39 02 cd 4b 00 cb;
+15d80: 5f ca 6b 00 cb 77 28 02 18 f2 21 df 02 1e 0a 0e;
+15d90: 0f cd 46 02 16 12 cd c1 05 30 09 16 18 cd c1 05;
+15da0: 30 02 18 f0 78 32 ec ff c3 3c 03 21 09 03 1e 54;
+15db0: 0e 1d cd 39 02 06 06 cd 4d 00 cb 5f ca 6b 00 18;
+15dc0: f6 db e8 e6 f0 b2 d3 e8 db ea 06 00 0e 04 0f 0f;
+15dd0: d0 04 0d 20 fa c9 d5 11 0d 00 c3 e8 05 d5 11 82;
+15de0: 00 c3 e8 05 d5 11 2c 1a 1b 7b b2 20 fb d1 c9 21;
+15df0: 00 80 dd 21 f8 05 18 1a db f9 fe 00 c2 57 00 dd;
+15e00: 21 05 06 18 0d db f9 77 23 7d b4 20 f6 d3 f8 c3;
+15e10: 02 00 7c d3 f8 7d d3 f9 16 04 15 20 fd dd e9 00;
+15e20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15e30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15e40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+15ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+16000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+160a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+160b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+160c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+160d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+160e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+160f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+161a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+161b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+161c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+161d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+161e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+161f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+162a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+162b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+162c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+162d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+162e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+162f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+163a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+163b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+163c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+163d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+163e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+163f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+164a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+164b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+164c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+164d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+164e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+164f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+165a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+165b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+165c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+165d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+165e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+165f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+166a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+166b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+166c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+166d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+166e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+166f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+167a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+167b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+167c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+167d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+167e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+167f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+168a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+168b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+168c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+168d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+168e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+168f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+169a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+169b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+169c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+169d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+169e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+169f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+16ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+170a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+170b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+170c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+170d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+170e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+170f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+17160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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+18430: db d8 2f 0f 38 f5 e1 d1 c9 1d 20 ec c3 56 05 06;
+18440: 00 11 10 00 2a 1e cf af ed 52 38 03 04 18 f9 19;
+18450: 60 2c fd 74 04 fd 75 05 3a ec ff fe 04 30 18 fd;
+18460: 7e 04 fe 46 30 11 fd 7e 05 b7 28 0b fe 11 30 07;
+18470: fd 7e 02 fd b6 03 c0 c3 56 05 f3 cd 3f 04 3e 0a;
+18480: 32 eb ff cd 99 03 fd 56 03 fd 7e 02 b7 28 01 14;
+18490: fd 7e 05 fd 77 01 fd 7e 04 fd 77 00 dd e5 e1 cb;
+184a0: 3f 2f d3 db 30 04 3e 01 18 02 3e 00 2f d3 dd cd;
+184b0: e2 03 20 6a 0e db fd 7e 00 cb 3f 2f d3 d9 fd 7e;
+184c0: 01 2f d3 da d9 21 f7 04 e5 d9 3e 94 2f d3 d8 cd;
+184d0: 2d 05 06 00 db d8 0f d8 0f 38 f9 ed a2 20 f5 fd;
+184e0: 34 01 fd 7e 01 fe 11 28 05 15 20 e6 18 01 15 3e;
+184f0: d8 2f d3 d8 cd 21 04 db d8 2f e6 ff 20 20 d9 e1;
+18500: d9 fd 7e 01 fe 11 20 08 3e 01 fd 77 01 fd 34 00;
+18510: 7a b7 20 05 3e 80 d3 dc c9 fd 7e 00 18 81 3a eb;
+18520: ff 3d 32 eb ff 28 2f cd 09 04 c3 83 04 d5 e5 cd;
+18530: d6 05 1e 08 21 00 00 2b 7c b5 28 09 db d8 2f 0f;
+18540: 30 f5 e1 d1 c9 1d 20 ec 18 0c 21 ee 02 1e 07 0e;
+18550: 1b cd 46 02 18 03 cd 3f 02 cd f3 03 31 e0 ff cd;
+18560: 5f 00 20 47 21 b3 02 1e 5a 0e 0c cd 39 02 1e ab;
+18570: 0e 11 cd 39 02 1e d3 0e 0f cd 39 02 cd 4b 00 cb;
+18580: 5f ca 6b 00 cb 77 28 02 18 f2 21 df 02 1e 0a 0e;
+18590: 0f cd 46 02 16 12 cd c1 05 30 09 16 18 cd c1 05;
+185a0: 30 02 18 f0 78 32 ec ff c3 3c 03 21 09 03 1e 54;
+185b0: 0e 1d cd 39 02 06 06 cd 4d 00 cb 5f ca 6b 00 18;
+185c0: f6 db e8 e6 f0 b2 d3 e8 db ea 06 00 0e 04 0f 0f;
+185d0: d0 04 0d 20 fa c9 d5 11 0d 00 c3 e8 05 d5 11 82;
+185e0: 00 c3 e8 05 d5 11 2c 1a 1b 7b b2 20 fb d1 c9 21;
+185f0: 00 80 dd 21 f8 05 18 1a db f9 fe 00 c2 57 00 dd;
+18600: 21 05 06 18 0d db f9 77 23 7d b4 20 f6 d3 f8 c3;
+18610: 02 00 7c d3 f8 7d d3 f9 16 04 15 20 fd dd e9 00;
+18620: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18630: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18640: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18650: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18660: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18670: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18680: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18690: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+186a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+186b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+186c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+186d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+186e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+186f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18700: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18710: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18720: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18730: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18740: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18750: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18760: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18770: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18780: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18790: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+187a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+187b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+187c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+187d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+187e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+187f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
+18800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+188a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+188b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+188c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+188d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+188e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+188f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+189a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+189b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+189c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+189d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+189e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+189f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+18ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+190a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+190b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+190c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+190d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+190e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+190f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+191a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+191b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+191c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+191d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+191e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+191f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+192a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+192b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+192c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+192d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+192e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+192f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+193a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+193b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+193c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+193d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+193e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+193f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+194a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+194b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+194c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+194d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+194e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+194f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+195a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+195b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+195c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+195d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+195e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+195f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+196a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+196b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+196c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+196d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+196e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+196f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+197a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+197b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+197c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+197d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+197e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+197f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+198a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+198b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+198c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+198d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+198e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+198f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
+19930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
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diff --git a/software/mzf/3-D MAZE.MZF b/software/mzf/3-D MAZE.MZF
new file mode 100644
index 0000000..e359492
Binary files /dev/null and b/software/mzf/3-D MAZE.MZF differ
diff --git a/software/mzf/MYMAZE.mzf b/software/mzf/MYMAZE.mzf
new file mode 100644
index 0000000..847ea93
Binary files /dev/null and b/software/mzf/MYMAZE.mzf differ
diff --git a/software/mzf/hi-ramcheck.mzf b/software/mzf/hi-ramcheck.mzf
new file mode 100644
index 0000000..c68c09f
Binary files /dev/null and b/software/mzf/hi-ramcheck.mzf differ
diff --git a/software/mzf/ramtest.mzf b/software/mzf/ramtest.mzf
new file mode 100644
index 0000000..6813dbc
Binary files /dev/null and b/software/mzf/ramtest.mzf differ
diff --git a/software/mzf/sharpmz-test.mzf b/software/mzf/sharpmz-test.mzf
new file mode 100644
index 0000000..826d0ba
Binary files /dev/null and b/software/mzf/sharpmz-test.mzf differ
diff --git a/software/mzf/tapecheck.mzf b/software/mzf/tapecheck.mzf
new file mode 100644
index 0000000..52b8e7f
Binary files /dev/null and b/software/mzf/tapecheck.mzf differ
diff --git a/software/roms/IPL.rom b/software/roms/IPL.rom
new file mode 100644
index 0000000..f46fa39
Binary files /dev/null and b/software/roms/IPL.rom differ
diff --git a/software/roms/MZ700_cgrom.rom b/software/roms/MZ700_cgrom.rom
new file mode 100644
index 0000000..27ea643
Binary files /dev/null and b/software/roms/MZ700_cgrom.rom differ
diff --git a/software/roms/MZ80B.rom b/software/roms/MZ80B.rom
new file mode 100644
index 0000000..12e9248
Binary files /dev/null and b/software/roms/MZ80B.rom differ
diff --git a/software/roms/MZ80K_cgrom.rom b/software/roms/MZ80K_cgrom.rom
new file mode 100644
index 0000000..6598e21
Binary files /dev/null and b/software/roms/MZ80K_cgrom.rom differ
diff --git a/software/roms/MZFONT.rom b/software/roms/MZFONT.rom
new file mode 100644
index 0000000..c8f22c2
Binary files /dev/null and b/software/roms/MZFONT.rom differ
diff --git a/software/roms/NEWMON.rom b/software/roms/NEWMON.rom
new file mode 100644
index 0000000..237f8b0
Binary files /dev/null and b/software/roms/NEWMON.rom differ
diff --git a/software/roms/SP1002.rom b/software/roms/SP1002.rom
new file mode 100644
index 0000000..a493a99
Binary files /dev/null and b/software/roms/SP1002.rom differ
diff --git a/software/roms/combined_cgrom.rom b/software/roms/combined_cgrom.rom
new file mode 100644
index 0000000..ab53838
Binary files /dev/null and b/software/roms/combined_cgrom.rom differ
diff --git a/software/roms/combined_keymap.rom b/software/roms/combined_keymap.rom
new file mode 100644
index 0000000..5808455
Binary files /dev/null and b/software/roms/combined_keymap.rom differ
diff --git a/software/roms/combined_mainmemory.rom b/software/roms/combined_mainmemory.rom
new file mode 100644
index 0000000..b6f82d0
Binary files /dev/null and b/software/roms/combined_mainmemory.rom differ
diff --git a/software/roms/combined_mrom.rom b/software/roms/combined_mrom.rom
new file mode 100644
index 0000000..0261d02
Binary files /dev/null and b/software/roms/combined_mrom.rom differ
diff --git a/software/roms/fdcrom.rom b/software/roms/fdcrom.rom
new file mode 100644
index 0000000..7de9e36
--- /dev/null
+++ b/software/roms/fdcrom.rom
@@ -0,0 +1 @@
+����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
\ No newline at end of file
diff --git a/software/roms/key_1200.rom b/software/roms/key_1200.rom
new file mode 100644
index 0000000..3093ac8
Binary files /dev/null and b/software/roms/key_1200.rom differ
diff --git a/software/roms/key_700.rom b/software/roms/key_700.rom
new file mode 100644
index 0000000..a0ee0a1
Binary files /dev/null and b/software/roms/key_700.rom differ
diff --git a/software/roms/key_80a.rom b/software/roms/key_80a.rom
new file mode 100644
index 0000000..3093ac8
Binary files /dev/null and b/software/roms/key_80a.rom differ
diff --git a/software/roms/key_80b.rom b/software/roms/key_80b.rom
new file mode 100644
index 0000000..5f9ab43
Binary files /dev/null and b/software/roms/key_80b.rom differ
diff --git a/software/roms/key_80c.rom b/software/roms/key_80c.rom
new file mode 100644
index 0000000..7f80112
Binary files /dev/null and b/software/roms/key_80c.rom differ
diff --git a/software/roms/key_80k.rom b/software/roms/key_80k.rom
new file mode 100644
index 0000000..7f80112
Binary files /dev/null and b/software/roms/key_80k.rom differ
diff --git a/software/roms/monitor_1Z-013A.rom b/software/roms/monitor_1Z-013A.rom
new file mode 100644
index 0000000..dd66632
Binary files /dev/null and b/software/roms/monitor_1Z-013A.rom differ
diff --git a/software/roms/monitor_80c_1Z-013A.rom b/software/roms/monitor_80c_1Z-013A.rom
new file mode 100644
index 0000000..f86b247
Binary files /dev/null and b/software/roms/monitor_80c_1Z-013A.rom differ
diff --git a/software/roms/monitor_80c_SA1510.rom b/software/roms/monitor_80c_SA1510.rom
new file mode 100644
index 0000000..06ec98a
Binary files /dev/null and b/software/roms/monitor_80c_SA1510.rom differ
diff --git a/software/roms/monitor_SA1510.rom b/software/roms/monitor_SA1510.rom
new file mode 100644
index 0000000..2cd2176
Binary files /dev/null and b/software/roms/monitor_SA1510.rom differ
diff --git a/software/roms/monitor_mz-1r12.rom b/software/roms/monitor_mz-1r12.rom
new file mode 100644
index 0000000..e338c7d
Binary files /dev/null and b/software/roms/monitor_mz-1r12.rom differ
diff --git a/software/roms/mz-80acg.rom b/software/roms/mz-80acg.rom
new file mode 100644
index 0000000..0d87664
Binary files /dev/null and b/software/roms/mz-80acg.rom differ
diff --git a/software/roms/quickdisk_mz-1e05.rom b/software/roms/quickdisk_mz-1e05.rom
new file mode 100644
index 0000000..8dec829
Binary files /dev/null and b/software/roms/quickdisk_mz-1e05.rom differ
diff --git a/software/roms/quickdisk_mz-1e14.rom b/software/roms/quickdisk_mz-1e14.rom
new file mode 100644
index 0000000..aac54ba
Binary files /dev/null and b/software/roms/quickdisk_mz-1e14.rom differ
diff --git a/software/roms/userrom.rom b/software/roms/userrom.rom
new file mode 100644
index 0000000..279435a
--- /dev/null
+++ b/software/roms/userrom.rom
@@ -0,0 +1 @@
+��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
\ No newline at end of file
diff --git a/sys/build_id.tcl b/sys/build_id.tcl
new file mode 100644
index 0000000..8777a14
--- /dev/null
+++ b/sys/build_id.tcl
@@ -0,0 +1,69 @@
+
+# Build TimeStamp Verilog Module
+# Jeff Wiencrot - 8/1/2011
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Build CDF file
+# Sorgelig - 17/2/2018
+proc generateCDF {revision device outpath} {
+
+	set outputFileName "jtag.cdf"
+	set outputFile [open $outputFileName "w"]
+
+	puts $outputFile "JedecChain;"
+	puts $outputFile "	FileRevision(JESD32A);"
+	puts $outputFile "	DefaultMfr(6E);"
+	puts $outputFile ""
+	puts $outputFile "	P ActionCode(Ign)"
+	puts $outputFile "		Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
+	puts $outputFile "	P ActionCode(Cfg)"
+	puts $outputFile "		Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
+	puts $outputFile "ChainEnd;"
+	puts $outputFile ""
+	puts $outputFile "AlteraBegin;"
+	puts $outputFile "	ChainType(JTAG);"
+	puts $outputFile "AlteraEnd;"
+}
+
+set project_name [lindex $quartus(args) 1]
+set revision [lindex $quartus(args) 2]
+
+if {[project_exists $project_name]} {
+    if {[string equal "" $revision]} {
+        project_open $project_name -revision [get_current_revision $project_name]
+    } else {
+        project_open $project_name -revision $revision
+    }
+} else {
+    post_message -type error "Project $project_name does not exist"
+    exit
+}
+
+set device  [get_global_assignment -name DEVICE]
+set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
+
+if [is_project_open] {
+    project_close
+}
+
+generateBuildID_Verilog
+generateCDF $revision $device $outpath
diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv
new file mode 100644
index 0000000..0265c5c
--- /dev/null
+++ b/sys/hdmi_config.sv
@@ -0,0 +1,202 @@
+
+module hdmi_config
+(
+	//	Host Side
+	input			iCLK,
+	input			iRST_N,
+	
+	input       dvi_mode,
+	input       audio_96k,
+
+	//	I2C Side
+	output		I2C_SCL,
+	inout 		I2C_SDA
+);
+
+//	Internal Registers/Wires
+reg        mI2C_GO = 0;
+wire       mI2C_END;
+wire       mI2C_ACK;
+reg [15:0] LUT_DATA;
+reg  [7:0] LUT_INDEX = 0;
+
+i2c #(50_000_000, 20_000) i2c_av
+(
+	.CLK(iCLK),
+
+	.I2C_SCL(I2C_SCL),		//	I2C CLOCK
+	.I2C_SDA(I2C_SDA),		//	I2C DATA
+
+	.I2C_DATA({8'h72,init_data[LUT_INDEX]}),	//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip!
+	.START(mI2C_GO),    		//	START transfer
+	.END(mI2C_END),			//	END transfer 
+	.ACK(mI2C_ACK) 			//	ACK
+);
+
+//////////////////////	Config Control	////////////////////////////
+always@(posedge iCLK or negedge iRST_N) begin
+	reg  [1:0] mSetup_ST = 0;
+
+	if(!iRST_N) begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+	end else begin
+		if(init_data[LUT_INDEX] != 16'hFFFF) begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1: if(~mI2C_END) mSetup_ST	<=	2;
+			2:	begin
+					mI2C_GO <= 0;
+					if(mI2C_END) begin
+						mSetup_ST <= 0;
+						if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
+					end
+				end
+			endcase
+		end
+	end
+end
+
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT   //////////////////////////
+
+wire [15:0] init_data[58] = 
+'{
+	16'h9803,					// ADI required Write.
+
+	{8'hD6, 8'b1100_0000},	// [7:6] HPD Control...
+									// 00 = HPD is from both HPD pin or CDC HPD
+									// 01 = HPD is from CDC HPD
+									// 10 = HPD is from HPD pin
+									// 11 = HPD is always high
+
+	16'h4110,					// Power Down control
+	16'h9A70,					// ADI required Write.
+	16'h9C30,					// ADI required Write.
+	{8'h9D, 8'b0110_0001},	// [7:4] must be b0110!.
+									// [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid!
+									//	[1:0] must be b01!
+	16'hA2A4,					// ADI required Write.
+	16'hA3A4,					// ADI required Write.
+	16'hE0D0,					// ADI required Write.
+
+
+	16'h35_40,
+	16'h36_D9,
+	16'h37_0A,
+	16'h38_00,
+	16'h39_2D,
+	16'h3A_00,
+
+	{8'h16, 8'b0011_1000},	// Output Format 444 [7]=0.
+									// [6] must be 0!
+									// Colour Depth for Input Video data [5:4] b11 = 8-bit.
+									// Input Style [3:2] b10 = Style 1 (ignored when using 444 input).
+									// DDR Input Edge falling [1]=0 (not using DDR atm).
+									// Output Colour Space RGB [0]=0.
+
+	{8'h17, 8'b01100010},   // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
+
+	{8'h18, 8'b0100_0110},	// CSC disabled [7]=0.
+									// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
+									// CSC Equation 3 [4:0] b00110.
+
+
+	{8'h3B, 8'b0000_0000},	// Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
+
+	16'h4000,					// General Control Packet Enable
+
+	{8'h48, 8'b0000_1000},	// [6]=0 Normal bus order!
+									// [5] DDR Alignment.
+									// [4:3] b01 Data right justified (for YCbCr 422 input modes).
+
+	16'h49A8,					// ADI required Write.
+	16'h4C00,					// ADI required Write.
+
+	{8'h55, 8'b0001_0000},	// [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
+									// AVI InfoFrame Valid [4].
+									// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
+									// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
+
+	16'h7301,
+
+	{8'h94, 8'b1000_0000},	// [7]=1 HPD Interrupt ENabled.
+
+	16'h9902,					// ADI required Write.
+	16'h9B18,					// ADI required Write.
+
+	16'h9F00,					// ADI required Write.
+
+	{8'hA1, 8'b0000_0000},	// [6]=1 Monitor Sense Power Down DISabled.
+	
+	16'hA408,					// ADI required Write.
+	16'hA504,					// ADI required Write.
+	16'hA600,					// ADI required Write.
+	16'hA700,					// ADI required Write.
+	16'hA800,					// ADI required Write.
+	16'hA900,					// ADI required Write.
+	16'hAA00,					// ADI required Write.
+	16'hAB40,					// ADI required Write.
+	
+	{8'hAF, 6'b0001_01,~dvi_mode,1'b0},	// [7]=0 HDCP Disabled.
+									// [6:5] must be b00!
+									// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
+									// [3:2] must be b01!
+									//	[1]=1 HDMI Mode.
+									// [0] must be b0!
+
+	16'hB900,					// ADI required Write.
+
+	{8'hBA, 8'b0110_0000},	// [7:5] Input Clock delay...
+									// b000 = -1.2ns.
+									// b001 = -0.8ns.
+									// b010 = -0.4ns.
+									// b011 = No delay.
+									// b100 = 0.4ns.
+									// b101 = 0.8ns.
+									// b110 = 1.2ns.
+									// b111 = 1.6ns.
+					
+	16'hBB00,					// ADI required Write.
+	
+	16'hDE9C,					// ADI required Write.
+	16'hE460,					// ADI required Write.
+	16'hFA7D,					// Nbr of times to search for good phase
+
+	
+									// (Audio stuff on Programming Guide, Page 66)...
+	
+	{8'h0A, 8'b0000_0000},	// [6:4] Audio Select. b000 = I2S.
+									// [3:2] Audio Mode. (HBR stuff, leave at 00!).
+
+	{8'h0B, 8'b0000_1110},	//
+									
+	{8'h0C, 8'b0000_0100},	// [7] 0 = Use sampling rate from I2S stream.   1 = Use samp rate from I2C Register.
+									// [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register.
+									// [2] 1 = I2S0 Enable.
+									// [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES.
+									
+	{8'h0D, 8'b0001_0000},	// [4:0] I2S Bit (Word) Width for Right-Justified.
+	{8'h14, 8'b0000_0010},	// [3:0] Audio Word Length. b0010 = 16 bits.
+	{8'h15, audio_96k, 7'b010_0000},	// I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
+									// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
+
+	// Audio Clock Config
+	16'h0100,					//  
+	audio_96k ? 16'h0230 : 16'h0218,	// Set N Value 12288/6144
+	16'h0300,					//
+
+	16'h0701,					//
+	16'h0822,					// Set CTS Value 74250
+	16'h090A,					//
+
+	16'hFFFF 				   // END
+};
+
+////////////////////////////////////////////////////////////////////
+
+endmodule
\ No newline at end of file
diff --git a/sys/hdmi_lite.sv b/sys/hdmi_lite.sv
new file mode 100644
index 0000000..ef80764
--- /dev/null
+++ b/sys/hdmi_lite.sv
@@ -0,0 +1,395 @@
+//============================================================================
+//
+//  HDMI Lite output module
+//  Copyright (C) 2017 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//============================================================================
+
+
+module hdmi_lite
+(
+	input          reset,
+
+	input          clk_video,
+	input          ce_pixel,
+	input          video_vs,
+	input          video_de,
+	input   [23:0] video_d,
+
+	input          clk_hdmi,
+	input          hdmi_hde,
+	input          hdmi_vde,
+	output reg     hdmi_de,
+	output  [23:0] hdmi_d,
+
+	input   [11:0] screen_w,
+	input   [11:0] screen_h,
+	input          quadbuf,
+
+	// 0-3 => scale 1-4
+	input    [1:0] scale_x,
+	input    [1:0] scale_y,
+	input          scale_auto,
+
+	input          clk_vbuf,
+	output  [27:0] vbuf_address,
+	input  [127:0] vbuf_readdata,
+	output [127:0] vbuf_writedata,
+	output   [7:0] vbuf_burstcount,
+	output  [15:0] vbuf_byteenable,
+	input          vbuf_waitrequest,
+	input          vbuf_readdatavalid,
+	output reg     vbuf_read,
+	output reg     vbuf_write
+);
+
+localparam  [7:0] burstsz  = 64;
+
+reg   [1:0] nbuf = 0;
+wire [27:0] read_buf  = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
+wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
+
+assign vbuf_address    = vbuf_write ? vbuf_waddress    : vbuf_raddress;
+assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
+
+wire [95:0] hf_out;
+wire  [7:0] hf_usedw;
+reg         hf_reset = 0;
+
+vbuf_fifo out_fifo
+(
+	.aclr(hf_reset),
+
+	.wrclk(clk_vbuf),
+	.wrreq(vbuf_readdatavalid),
+	.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
+	.wrusedw(hf_usedw),
+
+	.rdclk(~clk_hdmi),
+	.rdreq(hf_rdreq),
+	.q(hf_out)
+);
+
+reg [11:0] rd_stride;
+wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
+
+reg [27:0] vbuf_raddress;
+reg  [7:0] vbuf_rburstcount;
+always @(posedge clk_vbuf) begin
+	reg [18:0] rdcnt;
+	reg  [7:0] bcnt;
+	reg        vde1, vde2;
+	reg  [1:0] mcnt;
+	reg  [1:0] my;
+	reg [18:0] fsz; 
+	reg [11:0] strd;
+
+	vde1 <= hdmi_vde;
+	vde2 <= vde1;
+
+	if(vbuf_readdatavalid) begin
+		rdcnt <= rdcnt + 1'd1;
+		if(bcnt) bcnt <= bcnt - 1'd1;
+		vbuf_raddress <= vbuf_raddress + 1'd1;
+	end
+
+	if(!bcnt && reading) reading <= 0;
+
+	vbuf_read <= 0;
+	if(~vbuf_waitrequest) begin
+		if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
+			vbuf_read <= 1;
+			reading   <= 1;
+			bcnt <= rd_burst;
+			vbuf_rburstcount <= rd_burst;
+			rd_stride <= rd_stride - rd_burst;
+			if(!(rd_stride - rd_burst)) rd_stride <= strd;
+
+			if(!rdcnt) begin
+				vbuf_raddress <= read_buf;
+				mcnt <= my;
+			end
+			else if (rd_stride == strd) begin
+				mcnt <= mcnt - 1'd1;
+				if(!mcnt) mcnt <= my;
+					else vbuf_raddress <= vbuf_raddress - strd;
+			end
+		end
+	end
+
+	hf_reset <= 0;
+	if(vde2 & ~vde1) begin
+		hf_reset <= 1;
+		rdcnt <= 0;
+		bcnt <= 0;
+		rd_stride <= stride;
+		strd <= stride;
+		fsz <= framesz;
+		my <= mult_y;
+	end
+end
+
+
+reg [11:0] off_x, off_y;
+reg [11:0] x, y;
+reg [11:0] vh_height;
+reg [11:0] vh_width;
+reg  [1:0] pcnt;
+reg  [1:0] hload;
+wire       hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
+wire       de_in = hdmi_hde & hdmi_vde;
+
+always @(posedge clk_hdmi) begin
+	reg [71:0] px_out;
+	reg  [1:0] mx;
+	reg        vde;
+
+	vde <= hdmi_vde;
+
+	if(vde & ~hdmi_vde) begin
+		off_x <= (screen_w>v_width)  ? (screen_w - v_width)>>1  : 12'd0;
+		off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
+		vh_height <= v_height;
+		vh_width  <= v_width;
+		mx <= mult_x;
+	end
+
+	pcnt <= pcnt + 1'd1;
+	if(pcnt == mx) begin
+		pcnt <= 0;
+		hload <= hload + 1'd1;
+	end 
+
+	if(~de_in || x<off_x || y<off_y) begin
+		hload <= 0;
+		pcnt <= 0;
+	end
+
+	hdmi_de <= de_in;
+
+	x <= x + 1'd1;
+	if(~hdmi_de & de_in) x <= 0;
+	if(hdmi_de & ~de_in) y <= y + 1'd1;
+	if(~hdmi_vde) y <= 0;
+
+	if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
+	if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
+end
+
+//////////////////////////////////////////////////////////////////////////////
+
+reg reading = 0;
+reg writing = 0;
+
+reg op_split = 0;
+always @(posedge clk_vbuf) op_split <= ~op_split;
+
+wire allow_rd = ~reading & ~writing &  op_split & ~reset;
+wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
+
+//////////////////////////////////////////////////////////////////////////////
+
+reg         vf_rdreq = 0;
+wire [95:0] vf_out;
+assign      vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
+
+vbuf_fifo in_fifo
+(
+	.aclr(video_vs),
+
+	.rdclk(clk_vbuf),
+	.rdreq(vf_rdreq & ~vbuf_waitrequest),
+	.q(vf_out),
+
+	.wrclk(clk_video),
+	.wrreq(infifo_wr),
+	.data({video_de ? video_d : 24'd0, pix_acc})
+);
+
+assign vbuf_byteenable = '1;
+
+reg [35:0] addrque[3:0] = '{0,0,0,0};
+
+reg  [7:0] flush_size;
+reg [27:0] flush_addr;
+reg        flush_req = 0;
+reg        flush_ack = 0;
+
+reg [27:0] vbuf_waddress;
+reg  [7:0] vbuf_wburstcount;
+
+always @(posedge clk_vbuf) begin
+	reg [7:0] ibcnt = 0;
+	reg       reqd = 0;
+	
+	reqd <= flush_req;
+
+	if(~vbuf_waitrequest) begin
+		vbuf_write <= vf_rdreq;
+		if(~vf_rdreq && writing) writing <= 0;
+		if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
+			{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
+			ibcnt <= addrque[0][7:0];
+			addrque[0] <= addrque[1];
+			addrque[1] <= addrque[2];
+			addrque[2] <= addrque[3];
+			addrque[3] <= 0;
+			vf_rdreq <= 1;
+			writing <= 1;
+		end
+		else if(flush_ack != reqd) begin
+				  if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
+			else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
+			else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
+			else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
+			flush_ack <= reqd;
+		end
+
+		if(vf_rdreq) begin
+			if(ibcnt == 1) vf_rdreq <= 0;
+			ibcnt <= ibcnt - 1'd1;
+		end
+	end
+end
+
+reg  [11:0] stride;
+reg  [18:0] framesz;
+reg  [11:0] v_height;
+reg  [11:0] v_width;
+reg   [1:0] mult_x;
+reg   [1:0] mult_y;
+
+reg  [71:0] pix_acc;
+wire        pix_wr = ce_pixel && video_de;
+
+reg  [27:0] cur_addr;
+reg  [11:0] video_x;
+reg  [11:0] video_y;
+
+wire        infifo_tail = ~video_de && video_x[1:0];
+wire        infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
+
+wire  [1:0] tm_y     = (video_y  > (screen_h/2)) ? 2'b00 : (video_y  > (screen_h/3)) ? 2'b01 : (video_y  > (screen_h/4)) ? 2'b10 : 2'b11;
+wire  [1:0] tm_x     = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
+wire  [1:0] tm_xy    = (tm_x < tm_y) ? tm_x : tm_y;
+wire  [1:0] tmf_y    = scale_auto ? tm_xy : scale_y;
+wire  [1:0] tmf_x    = scale_auto ? tm_xy : scale_x;
+wire [11:0] t_height = video_y  + (tmf_y[0] ? video_y  : 12'd0) + (tmf_y[1] ? video_y<<1  : 12'd0);
+wire [11:0] t_width  = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
+wire [23:0] t_fsz    = l1_stride * t_height;
+
+reg  [11:0] l1_width;
+reg  [11:0] l1_stride;
+always @(posedge clk_video) begin
+	reg  [7:0] loaded = 0;
+	reg [11:0] strd   = 0;
+	reg        old_de = 0;
+	reg        old_vs = 0;
+
+	old_vs <= video_vs;
+	if(~old_vs & video_vs) begin
+		cur_addr<= write_buf;
+		video_x <= 0;
+		video_y <= 0;
+		loaded  <= 0;
+		strd <= 0;
+		nbuf <= nbuf + 1'd1;
+
+		stride  <= l1_stride;
+		framesz <= t_fsz[18:0];
+		v_height<= t_height;
+		v_width <= t_width;
+		mult_x  <= tmf_x;
+		mult_y  <= tmf_y;
+	end
+
+	if(pix_wr) begin
+		case(video_x[1:0])
+			0: pix_acc        <= video_d; // zeroes upper bits too
+			1: pix_acc[47:24] <= video_d;
+			2: pix_acc[71:48] <= video_d;
+			3: loaded <= loaded + 1'd1;
+		endcase
+		if(video_x<screen_w) video_x <= video_x + 1'd1;
+	end
+
+	old_de <= video_de;
+	if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
+		if(loaded + infifo_tail) begin
+			flush_size <= loaded + infifo_tail;
+			flush_addr <= cur_addr;
+			flush_req  <= ~flush_req;
+			loaded <= 0;
+			strd   <= strd + loaded;
+		end
+
+		cur_addr <= cur_addr + loaded + infifo_tail;
+		if(~video_de) begin
+			if(video_y<screen_h) video_y <= video_y + 1'd1;
+			video_x <= 0;
+			strd    <= 0;
+
+			// measure width by first line (same as VIP)
+			if(!video_y) begin
+				l1_width <= video_x;
+				l1_stride  <= strd + loaded + infifo_tail;
+			end
+		end
+	end
+end
+
+endmodule
+
+module vbuf_fifo
+(
+	input	        aclr,
+
+	input	        rdclk,
+	input	        rdreq,
+	output [95:0] q,
+
+	input	        wrclk,
+	input	        wrreq,
+	input	 [95:0] data,
+	output  [7:0] wrusedw
+);
+
+dcfifo dcfifo_component
+(
+	.aclr (aclr),
+	.data (data),
+	.rdclk (rdclk),
+	.rdreq (rdreq),
+	.wrclk (wrclk),
+	.wrreq (wrreq),
+	.q (q),
+	.wrusedw (wrusedw),
+	.eccstatus (),
+	.rdempty (),
+	.rdfull (),
+	.rdusedw (),
+	.wrempty (),
+	.wrfull ()
+);
+
+defparam
+	dcfifo_component.intended_device_family = "Cyclone V",
+	dcfifo_component.lpm_numwords = 256,
+	dcfifo_component.lpm_showahead = "OFF",
+	dcfifo_component.lpm_type = "dcfifo",
+	dcfifo_component.lpm_width = 96,
+	dcfifo_component.lpm_widthu = 8,
+	dcfifo_component.overflow_checking = "ON",
+	dcfifo_component.rdsync_delaypipe = 5,
+	dcfifo_component.read_aclr_synch = "OFF",
+	dcfifo_component.underflow_checking = "ON",
+	dcfifo_component.use_eab = "ON",
+	dcfifo_component.write_aclr_synch = "OFF",
+	dcfifo_component.wrsync_delaypipe = 5;
+
+endmodule
diff --git a/sys/hps_io.v b/sys/hps_io.v
new file mode 100644
index 0000000..e175af5
--- /dev/null
+++ b/sys/hps_io.v
@@ -0,0 +1,1096 @@
+//
+// hps_io.v
+//
+// mist_io-like module for MiSTer
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2017,2018 Sorgelig
+// SharpMZ series specific updates made by Philip Smart, 2018.
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = CLK_SYS/(PS2DIV*2)
+//
+
+// WIDE=1 for 16 bit file I/O
+// VDNUM 1-4
+module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
+(
+    input             clk_sys,
+    inout      [44:0] HPS_BUS,
+
+    // parameter STRLEN and the actual length of conf_str have to match
+    input [(8*STRLEN)-1:0] conf_str,
+
+    output reg [15:0] joystick_0,
+    output reg [15:0] joystick_1,
+    output reg [15:0] joystick_analog_0,
+    output reg [15:0] joystick_analog_1,
+
+    output      [1:0] buttons,
+    output            forced_scandoubler,
+
+    output reg [31:0] status,
+    
+    //toggle to force notify of video mode change
+    input             new_vmode,
+
+    // SD config
+    output reg [VD:0] img_mounted,  // signaling that new image has been mounted
+    output reg        img_readonly, // mounted as read only. valid only for active bit in img_mounted
+    output reg [63:0] img_size,     // size of image in bytes. valid only for active bit in img_mounted
+
+    // SD block level access
+    input      [31:0] sd_lba,
+    input      [VD:0] sd_rd,       // only single sd_rd can be active at any given time
+    input      [VD:0] sd_wr,       // only single sd_wr can be active at any given time
+    output reg        sd_ack,
+    
+    // do not use in new projects.
+    // CID and CSD are fake except CSD image size field.
+    input             sd_conf,
+    output reg        sd_ack_conf,
+
+    // SD byte level access. Signals for 2-PORT altsyncram.
+    output reg [AW:0] sd_buff_addr,
+    output reg [DW:0] sd_buff_dout,
+    input      [DW:0] sd_buff_din,
+    output reg        sd_buff_wr,
+
+    // ARM -> FPGA download
+    output reg        ioctl_download = 0, // signal indicating an active download
+    output reg        ioctl_upload = 0,   // signal indicating an active upload
+    output reg  [7:0] ioctl_index,        // menu index used to upload the file
+    output reg        ioctl_wr,
+    output reg        ioctl_rd,
+    output reg [24:0] ioctl_addr,         // in WIDE mode address will be incremented by 2
+    output reg [15:0] ioctl_dout,
+    input      [15:0] ioctl_din,
+    input             ioctl_wait,
+
+    // RTC MSM6242B layout
+    output reg [64:0] RTC,
+
+    // Seconds since 1970-01-01 00:00:00
+    output reg [32:0] TIMESTAMP,
+
+    // ps2 keyboard emulation
+    output            ps2_kbd_clk_out,
+    output            ps2_kbd_data_out,
+    input             ps2_kbd_clk_in,
+    input             ps2_kbd_data_in,
+
+    input       [2:0] ps2_kbd_led_status,
+    input       [2:0] ps2_kbd_led_use,
+
+    output            ps2_mouse_clk_out,
+    output            ps2_mouse_data_out,
+    input             ps2_mouse_clk_in,
+    input             ps2_mouse_data_in,
+
+    // ps2 alternative interface.
+
+    // [8] - extended, [9] - pressed, [10] - toggles with every press/release
+    output reg [10:0] ps2_key = 0,
+    
+    // [24] - toggles with every event
+    output reg [24:0] ps2_mouse = 0
+);
+
+localparam DW = (WIDE) ? 15 : 7;
+localparam AW = (WIDE) ?  7 : 8;
+localparam VD = VDNUM-1;
+
+wire        io_wait  = ioctl_wait;
+wire        io_enable= |HPS_BUS[35:34];
+wire        io_strobe= HPS_BUS[33];
+wire        io_wide  = (WIDE) ? 1'b1 : 1'b0;
+wire [15:0] io_din   = HPS_BUS[31:16];
+reg  [15:0] io_dout;
+
+assign HPS_BUS[37]   = io_wait;
+assign HPS_BUS[36]   = clk_sys;
+assign HPS_BUS[32]   = io_wide;
+assign HPS_BUS[15:0] = io_dout;
+
+reg [7:0] cfg;
+assign buttons = cfg[1:0];
+//cfg[2] - vga_scaler handled in sys_top
+//cfg[3] - csync handled in sys_top
+assign forced_scandoubler = cfg[4];
+//cfg[5] - ypbpr handled in sys_top
+
+// command byte read by the io controller
+wire [15:0] sd_cmd = 
+{
+    2'b00,
+    (VDNUM>=4) ? sd_wr[3] : 1'b0,
+    (VDNUM>=3) ? sd_wr[2] : 1'b0,
+    (VDNUM>=2) ? sd_wr[1] : 1'b0,
+
+    (VDNUM>=4) ? sd_rd[3] : 1'b0,
+    (VDNUM>=3) ? sd_rd[2] : 1'b0,
+    (VDNUM>=2) ? sd_rd[1] : 1'b0,
+    
+    4'h5, sd_conf, 1'b1,
+    sd_wr[0],
+    sd_rd[0]
+};
+
+///////////////// calc video parameters //////////////////
+
+wire clk_100 = HPS_BUS[43];
+wire clk_vid = HPS_BUS[42];
+wire ce_pix  = HPS_BUS[41];
+wire de      = HPS_BUS[40];
+wire hs      = HPS_BUS[39];
+wire vs      = HPS_BUS[38];
+wire vs_hdmi = HPS_BUS[44];
+
+reg [31:0] vid_hcnt = 0;
+reg [31:0] vid_vcnt = 0;
+reg  [7:0] vid_nres = 0;
+integer hcnt;
+
+always @(posedge clk_vid) begin
+    integer vcnt;
+    reg old_vs= 0, old_de = 0, old_vmode = 0;
+    reg calch = 0;
+
+    if(ce_pix) begin
+        old_vs <= vs;
+        old_de <= de;
+
+        if(~vs & ~old_de & de) vcnt <= vcnt + 1;
+        if(calch & de) hcnt <= hcnt + 1;
+        if(old_de & ~de) calch <= 0;
+
+        if(old_vs & ~vs) begin
+            if(hcnt && vcnt) begin
+                old_vmode <= new_vmode;
+                if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1;
+                vid_hcnt <= hcnt;
+                vid_vcnt <= vcnt;
+            end
+            vcnt <= 0;
+            hcnt <= 0;
+            calch <= 1;
+        end
+    end
+end
+
+reg [31:0] vid_htime = 0;
+reg [31:0] vid_vtime = 0;
+reg [31:0] vid_pix = 0;
+
+always @(posedge clk_100) begin
+    integer vtime, htime, hcnt;
+    reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
+    reg calch = 0;
+
+    old_vs <= vs;
+    old_hs <= hs;
+
+    old_vs2 <= old_vs;
+    old_hs2 <= old_hs;
+
+    vtime <= vtime + 1'd1;
+    htime <= htime + 1'd1;
+
+    if(~old_vs2 & old_vs) begin
+        vid_pix <= hcnt;
+        vid_vtime <= vtime;
+        vtime <= 0;
+        hcnt <= 0;
+    end
+
+    if(old_vs2 & ~old_vs) calch <= 1;
+
+    if(~old_hs2 & old_hs) begin
+        vid_htime <= htime;
+        htime <= 0;
+    end
+
+    old_de   <= de;
+    old_de2  <= old_de;
+
+    if(calch & old_de) hcnt <= hcnt + 1;
+    if(old_de2 & ~old_de) calch <= 0;
+end
+
+reg [31:0] vid_vtime_hdmi;
+always @(posedge clk_100) begin
+    integer vtime;
+    reg old_vs, old_vs2;
+
+    old_vs <= vs_hdmi;
+    old_vs2 <= old_vs;
+
+    vtime <= vtime + 1'd1;
+
+    if(~old_vs2 & old_vs) begin
+        vid_vtime_hdmi <= vtime;
+        vtime <= 0;
+    end
+end
+
+
+///////////////////////////////// HPS I/O ////////////////////////////////////
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+localparam UIO_FILE_INFO    = 8'h56;
+localparam UIO_FILE_ADDR    = 8'h57;
+localparam UIO_FILE_ADDR_TX = 8'h58;
+localparam UIO_FILE_ADDR_RX = 8'h59;
+localparam UIO_CONFIG_RX    = 8'h5A;
+localparam UIO_CONFIG_TX    = 8'h5B;
+
+
+reg [31:0] ps2_key_raw = 0;
+wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
+
+// Primary loop for HPS <-> FPGA I/O. Look at sys_top.v in the HPS I/O section
+// for the ack pulse going back to the HPS when data is written.
+//
+// Basic mode of operation is the HPS writes a byte on io_din and reads back
+// io_dout within the same clock cycle (clk_sys). io_enable is set active when
+// an EnableFPGA is executed within the HPS Main MiSTer program. io_strobe is
+// set active by the HPS when it writes a byte (sys_top.v acknowledges the 
+// strobe) and reset within the same clk_sys cycle.
+//
+always@(posedge clk_sys) begin
+    reg [15:0] cmd;
+    reg [15:0] byte_cnt;   // counts bytes
+    reg  [2:0] b_wr;
+    reg  [2:0] stick_idx;
+    reg        ps2skip = 0;
+    reg [24:0] addr;       // Address signal to hps logic in emulator.
+    reg        wr;         // Write signal to hps logic in emulator.
+    reg        rd;         // Read signal to hps logic in emulator.
+
+    // After the UIO_FILE_ADDR_TX command, wr will be set to 1, this is then transferred
+    // to the wire ioctl_wr at next clock cycle (1 cycle after address setup) and will be held
+    // high for 1 clock cycle of clk_sys. This provides the setup and hold time for the data
+    // before the write signal is generated.
+    //
+    ioctl_wr <= wr;
+    wr <= 0;
+
+    // For read, the UIO_FILE_ADDR_RX command places the wire ioctl_rd to 1 on the clock
+    // immediately follwing the command along with the address. It is held
+    // high for 2 cycles, on the 2nd cycle the data is sampled. The read data
+    // belongs to the previous address as the HPS mechanism writes data
+    // synchronised with the sys_clk and reads back within that same cycle
+    // (ie. 1x sys_clk). Thus the HPS needs to write a 0 @ addr1 then write another
+    // 0 @ addr2 and the data read back belongs to addr1.
+    //
+    ioctl_rd <= rd;
+    if(ioctl_rd == 1) begin
+        io_dout <= ioctl_din[15:0];   // This read is for previous address setup.
+    end
+    rd <= 0;
+
+    sd_buff_wr <= b_wr[0];
+    if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
+    b_wr <= (b_wr<<1);
+
+    {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
+    
+    if(~io_enable)
+    begin
+        if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
+        if(cmd == 5 && !ps2skip) begin
+            ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+            if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+            if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+            if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
+        end
+        if(cmd == 'h22) RTC[64] <= ~RTC[64];
+        if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
+        cmd <= 0;
+        byte_cnt <= 0;
+        sd_ack <= 0;
+        sd_ack_conf <= 0;
+        io_dout <= 0;
+        ps2skip <= 0;
+        addr <= 0;
+		ioctl_upload   <= 0;
+		ioctl_download <= 0;
+		ioctl_rd       <= 0;
+		ioctl_wr       <= 0;
+    end
+    else
+    begin
+        if(io_strobe)
+        begin
+            // Reset the input bus as needed.
+            if(cmd != UIO_CONFIG_RX)
+            begin
+                io_dout <= 0;
+            end
+
+            // Increment but dont let the byte counter roll-over.
+            if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
+
+            // First byte after strobe is the command, store and setup for
+            // command processing.
+            if(byte_cnt == 0)
+            begin
+                cmd <= io_din;
+
+                case(io_din)
+                    'h19: sd_ack_conf <= 1;
+                    'h17,
+                    'h18: sd_ack <= 1;
+                endcase
+
+                sd_buff_addr <= 0;
+                img_mounted <= 0;
+                if(io_din == 5) ps2_key_raw <= 0;
+            end
+            else
+            begin
+                case(cmd)
+                    // buttons and switches
+                    'h01: cfg        <= io_din[7:0]; 
+                    'h02: joystick_0 <= io_din;
+                    'h03: joystick_1 <= io_din;
+
+                    // store incoming ps2 mouse bytes 
+                    'h04: begin
+                            mouse_data <= io_din[7:0];
+                            mouse_we   <= 1;
+                            if(&io_din[15:8]) ps2skip <= 1;
+                            if(~&io_din[15:8] & ~ps2skip) begin
+                                case(byte_cnt)
+                                    1: ps2_mouse[7:0]   <= io_din[7:0];
+                                    2: ps2_mouse[15:8]  <= io_din[7:0];
+                                    3: ps2_mouse[23:16] <= io_din[7:0];
+                                endcase
+                            end
+                          end
+
+                    // store incoming ps2 keyboard bytes 
+                    'h05: begin
+                            if(&io_din[15:8]) ps2skip <= 1;
+                            if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
+                            kbd_data <= io_din[7:0];
+                            kbd_we <= 1;
+                          end
+
+                    // reading config string
+                    'h14: begin
+                            // returning a byte from string
+                            if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
+                          end
+
+                    // reading sd card status
+                    'h16: begin
+                            case(byte_cnt)
+                                1: io_dout <= sd_cmd;
+                                2: io_dout <= sd_lba[15:0];
+                                3: io_dout <= sd_lba[31:16];
+                            endcase
+                          end
+
+                    // send SD config IO -> FPGA
+                    // flag that download begins
+                    // sd card knows data is config if sd_dout_strobe is asserted
+                    // with sd_ack still being inactive (low)
+                    'h19,
+                    // send sector IO -> FPGA
+                    // flag that download begins
+                    'h17: begin
+                            sd_buff_dout <= io_din[DW:0];
+                            b_wr <= 1;
+                          end
+
+                    // reading sd card write data
+                    'h18: begin
+                            if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+                            io_dout <= sd_buff_din;
+                          end
+
+                    // joystick analog
+                    'h1a: begin
+                            // first byte is joystick index
+                            if(byte_cnt == 1) stick_idx <= io_din[2:0];
+                            if(byte_cnt == 2) begin
+                                if(stick_idx == 0) joystick_analog_0 <= io_din;
+                                if(stick_idx == 1) joystick_analog_1 <= io_din;
+                            end
+                          end
+
+                    // notify image selection
+                    'h1c: begin
+                            img_mounted  <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
+                            img_readonly <= io_din[7];
+                          end
+
+                    // send image info
+                    'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
+
+                    // status, 32bit version
+                    'h1e: if(byte_cnt==1) status[15:0] <= io_din;
+                          else if(byte_cnt==2) status[31:16] <= io_din;
+
+                    // reading keyboard LED status
+                    'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
+
+                    // reading ps2 keyboard/mouse control
+                    'h21: begin
+                            if(byte_cnt == 1) begin
+                                io_dout <= kbd_data_host;
+                                kbd_rd <= 1;
+                            end
+
+                            if(byte_cnt == 2) begin
+                                io_dout <= mouse_data_host;
+                                mouse_rd <= 1;
+                            end
+                          end
+                    //RTC
+                    'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+
+                    //Video res.
+                    'h23: begin
+                                case(byte_cnt)
+                                    1: io_dout <= vid_nres;
+                                    2: io_dout <= vid_hcnt[15:0];
+                                    3: io_dout <= vid_hcnt[31:16];
+                                    4: io_dout <= vid_vcnt[15:0];
+                                    5: io_dout <= vid_vcnt[31:16];
+                                    6: io_dout <= vid_htime[15:0];
+                                    7: io_dout <= vid_htime[31:16];
+                                    8: io_dout <= vid_vtime[15:0];
+                                    9: io_dout <= vid_vtime[31:16];
+                                   10: io_dout <= vid_pix[15:0];
+                                   11: io_dout <= vid_pix[31:16];
+                                   12: io_dout <= vid_vtime_hdmi[15:0];
+                                   13: io_dout <= vid_vtime_hdmi[31:16];
+                                endcase
+                          end
+
+                    //RTC
+                    'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+
+                    UIO_FILE_ADDR:    // Direct setup/change of address, each byte becomes the lower 7-0 bits of address.
+                        begin
+                            addr <= (addr << 8) | io_din[7:0];
+                        end
+
+                    UIO_FILE_INDEX:   // Setup of index (0-255), for index addressing.
+                        begin
+                            ioctl_index <= io_din[7:0];
+                        end
+
+                    UIO_FILE_TX:      // Standard file download, address starts at 0.
+                        begin
+                            if(io_din[7:0]) begin
+                                addr           <= 0;
+                                ioctl_download <= 1; 
+                            end else begin
+                                ioctl_addr     <= addr;
+                                ioctl_download <= 0;
+                            end
+                        end
+
+                    UIO_FILE_TX_DAT:  // File data download, byte sent to output bus and wr is pulsed (for 1 clock after address/data setup).
+                        begin
+                            ioctl_addr <= addr;
+                            ioctl_dout <= io_din[15:0];
+                            wr         <= 1;
+                            addr       <= addr + (WIDE ? 2'd2 : 2'd1);
+                        end
+
+                    UIO_FILE_ADDR_TX: // Modified file download, starting address is sent.
+                        begin
+                            // Address - 1=:24, 1 = 23:16, 2 = 15:8, 3 = 7:0
+                            if(byte_cnt < 5)
+                            begin
+                                addr <= (addr << 8) | io_din[7:0];
+
+                                // LSB byte signifies start of data receipt.
+                                if(byte_cnt == 4)
+                                begin
+                                    ioctl_download <= 1; 
+                                end
+                            end
+                            else
+                            begin
+                                ioctl_addr <= addr;
+                                ioctl_dout <= io_din[15:0];
+                                wr         <= 1;
+                                addr       <= addr + (WIDE ? 2'd2 : 2'd1);
+                            end
+                        end
+
+                    UIO_FILE_ADDR_RX: // Modified file upload, starting address is sent.
+                        begin
+
+                            // Address - 1=:24, 1 = 23:16, 2 = 15:8, 3 = 7:0
+                            if(byte_cnt < 5)
+                            begin
+                                addr <= (addr << 8) | io_din[7:0];
+ 
+                                // 4th byte signifies address received, upload
+                                // commences. Due to timings of an IO read, we
+                                // set up the address and read signals
+                                // 1 period before it is read, so at byte 4,
+                                // we setup first read which occurs at byte 5.
+                                //
+                                if(byte_cnt == 4)
+                                begin
+                                    ioctl_addr   <= (addr << 8) | io_din[7:0];
+                                    ioctl_upload <= 1; 
+                                    ioctl_rd     <= 1;
+                                    rd           <= 1;
+                                end
+                            end
+                            else
+                            begin
+                                // Normally the HPS sets io_din to 0 during
+                                // receive operation. If it is set to non-zero
+                                // the this is the end of upload marker.
+                                //
+                                //if(io_din[7:0]) begin
+                                //    ioctl_upload <= 0;
+                                //    ioctl_rd     <= 0;
+                                //end
+                                //else
+                                //begin
+                                    ioctl_addr   <= addr;
+                                    ioctl_rd     <= 1;
+                                    rd           <= 1;
+                                    addr         <= addr + (WIDE ? 2'd2 : 2'd1);
+                                //end
+                            end
+                        end
+                    UIO_CONFIG_RX:
+                        begin
+                            if(byte_cnt == 1)
+                            begin
+                                ioctl_addr   <= ({21'b100000000000000000000, io_din[3:0]});
+                                ioctl_rd     <= 1;
+                                rd           <= 1;
+                                //ioctl_upload <= 1; 
+                            end
+                            //else
+                            //begin
+                            //    if(io_din[7:0]) begin
+                            //        ioctl_upload <= 0;
+                            //        ioctl_rd     <= 0;
+                            //    end
+                            //end
+                            io_dout <= ioctl_din[DW:0];   // This read is for previous address setup.
+                        end
+                    UIO_CONFIG_TX:
+                        begin
+                            case(byte_cnt)
+                                1: begin
+                                       ioctl_addr <= ({21'b100000000000000000000, io_din[3:0]});
+                                   end
+                                2: begin
+                                       ioctl_dout <= io_din[DW:0];
+                                       wr <= 1;
+                                   end
+                            endcase
+                        end
+                endcase
+            end
+        end
+    end
+end
+
+///////////////////////////////   PS2   ///////////////////////////////
+reg clk_ps2;
+always @(negedge clk_sys) begin
+    integer cnt;
+    cnt <= cnt + 1'd1;
+    if(cnt == PS2DIV) begin
+        clk_ps2 <= ~clk_ps2;
+        cnt <= 0;
+    end
+end
+
+reg  [7:0] kbd_data;
+reg        kbd_we;
+wire [8:0] kbd_data_host;
+reg        kbd_rd;
+
+ps2_device keyboard
+(
+    .clk_sys(clk_sys),
+
+    .wdata(kbd_data),
+    .we(kbd_we),
+
+    .ps2_clk(clk_ps2),
+    .ps2_clk_out(ps2_kbd_clk_out),
+    .ps2_dat_out(ps2_kbd_data_out),
+    
+    .ps2_clk_in(ps2_kbd_clk_in  || !PS2WE),
+    .ps2_dat_in(ps2_kbd_data_in || !PS2WE),
+
+    .rdata(kbd_data_host),
+    .rd(kbd_rd)
+);
+
+reg  [7:0] mouse_data;
+reg        mouse_we;
+wire [8:0] mouse_data_host;
+reg        mouse_rd;
+
+ps2_device mouse
+(
+    .clk_sys(clk_sys),
+
+    .wdata(mouse_data),
+    .we(mouse_we),
+
+    .ps2_clk(clk_ps2),
+    .ps2_clk_out(ps2_mouse_clk_out),
+    .ps2_dat_out(ps2_mouse_data_out),
+
+    .ps2_clk_in(ps2_mouse_clk_in  || !PS2WE),
+    .ps2_dat_in(ps2_mouse_data_in || !PS2WE),
+
+    .rdata(mouse_data_host),
+    .rd(mouse_rd)
+);
+
+endmodule
+
+
+//reg [31:0] ps2_key_raw = 0;
+//wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+//wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
+//
+//always@(posedge clk_sys) begin
+//    reg [15:0] cmd;
+//    reg  [9:0] byte_cnt;   // counts bytes
+//    reg  [2:0] b_wr;
+//    reg  [2:0] stick_idx;
+//    reg [24:0] addr;
+//    reg        ps2skip = 0;
+//
+//    sd_buff_wr <= b_wr[0];
+//    if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
+//    b_wr <= (b_wr<<1);
+//
+//    {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
+//    
+//    if(~io_enable) begin
+//        if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
+//        if(cmd == 5 && !ps2skip) begin
+//            ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+//            if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+//            if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+//            if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
+//        end
+//        if(cmd == 'h22) RTC[64] <= ~RTC[64];
+//        if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
+//        cmd <= 0;
+//        byte_cnt <= 0;
+//        sd_ack <= 0;
+//        sd_ack_conf <= 0;
+//        io_dout <= 0;
+//        ps2skip <= 0;
+//        addr <= 0;
+//    end else begin
+//        if(io_strobe) begin
+//
+//            io_dout <= 0;
+//            if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
+//
+//            if(byte_cnt == 0) begin
+//                cmd <= io_din;
+//
+//                case(io_din)
+//                    'h19: sd_ack_conf <= 1;
+//                    'h17,
+//                    'h18: sd_ack <= 1;
+//                endcase
+//
+//                sd_buff_addr <= 0;
+//                img_mounted <= 0;
+//                if(io_din == 5) ps2_key_raw <= 0;
+//            end else begin
+//
+//                case(cmd)
+//                    // buttons and switches
+//                    'h01: cfg        <= io_din[7:0]; 
+//                    'h02: joystick_0 <= io_din;
+//                    'h03: joystick_1 <= io_din;
+//
+//                    // store incoming ps2 mouse bytes 
+//                    'h04: begin
+//                            mouse_data <= io_din[7:0];
+//                            mouse_we   <= 1;
+//                            if(&io_din[15:8]) ps2skip <= 1;
+//                            if(~&io_din[15:8] & ~ps2skip) begin
+//                                case(byte_cnt)
+//                                    1: ps2_mouse[7:0]   <= io_din[7:0];
+//                                    2: ps2_mouse[15:8]  <= io_din[7:0];
+//                                    3: ps2_mouse[23:16] <= io_din[7:0];
+//                                endcase
+//                            end
+//                        end
+//
+//                    // store incoming ps2 keyboard bytes 
+//                    'h05: begin
+//                            if(&io_din[15:8]) ps2skip <= 1;
+//                            if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
+//                            kbd_data <= io_din[7:0];
+//                            kbd_we <= 1;
+//                        end
+//
+//                    // reading config string
+//                    'h14: begin
+//                            // returning a byte from string
+//                            if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
+//                        end
+//
+//                    // reading sd card status
+//                    'h16: begin
+//                            case(byte_cnt)
+//                                1: io_dout <= sd_cmd;
+//                                2: io_dout <= sd_lba[15:0];
+//                                3: io_dout <= sd_lba[31:16];
+//                            endcase
+//                        end
+//
+//                    // send SD config IO -> FPGA
+//                    // flag that download begins
+//                    // sd card knows data is config if sd_dout_strobe is asserted
+//                    // with sd_ack still being inactive (low)
+//                    'h19,
+//                    // send sector IO -> FPGA
+//                    // flag that download begins
+//                    'h17: begin
+//                            sd_buff_dout <= io_din[DW:0];
+//                            b_wr <= 1;
+//                        end
+//
+//                    // reading sd card write data
+//                    'h18: begin
+//                            if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+//                            io_dout <= sd_buff_din;
+//                        end
+//
+//                    // joystick analog
+//                    'h1a: begin
+//                            // first byte is joystick index
+//                            if(byte_cnt == 1) stick_idx <= io_din[2:0];
+//                            if(byte_cnt == 2) begin
+//                                if(stick_idx == 0) joystick_analog_0 <= io_din;
+//                                if(stick_idx == 1) joystick_analog_1 <= io_din;
+//                            end
+//                        end
+//
+//                    // notify image selection
+//                    'h1c: begin
+//                            img_mounted  <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
+//                            img_readonly <= io_din[7];
+//                        end
+//
+//                    // send image info
+//                    'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
+//
+//                    // status, 32bit version
+//                    'h1e: if(byte_cnt==1) status[15:0] <= io_din;
+//                                else if(byte_cnt==2) status[31:16] <= io_din;
+//
+//                    // reading keyboard LED status
+//                    'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
+//
+//                    // reading ps2 keyboard/mouse control
+//                    'h21: begin
+//                            if(byte_cnt == 1) begin
+//                                io_dout <= kbd_data_host;
+//                                kbd_rd <= 1;
+//                            end
+//
+//                            if(byte_cnt == 2) begin
+//                                io_dout <= mouse_data_host;
+//                                mouse_rd <= 1;
+//                            end
+//                        end
+//                    //RTC
+//                    'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+//
+//                    //Video res.
+//                    'h23: begin
+//                                case(byte_cnt)
+//                                    1: io_dout <= vid_nres;
+//                                    2: io_dout <= vid_hcnt[15:0];
+//                                    3: io_dout <= vid_hcnt[31:16];
+//                                    4: io_dout <= vid_vcnt[15:0];
+//                                    5: io_dout <= vid_vcnt[31:16];
+//                                    6: io_dout <= vid_htime[15:0];
+//                                    7: io_dout <= vid_htime[31:16];
+//                                    8: io_dout <= vid_vtime[15:0];
+//                                    9: io_dout <= vid_vtime[31:16];
+//                                  10: io_dout <= vid_pix[15:0];
+//                                  11: io_dout <= vid_pix[31:16];
+//                                  12: io_dout <= vid_vtime_hdmi[15:0];
+//                                  13: io_dout <= vid_vtime_hdmi[31:16];
+//                                endcase
+//                        end
+//
+//                    //RTC
+//                    'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+//
+//                    // Read emulator memory, main task performed in download
+//                    // block, this component just puts the data onto the
+//                    // io_dout bus.
+//                    'h59: io_dout    <= 'h55; //ioctl_din[DW:0];
+//                endcase
+//            end
+//        end
+//    end
+//end
+
+//localparam UIO_FILE_TX      = 8'h53;
+//localparam UIO_FILE_TX_DAT  = 8'h54;
+//localparam UIO_FILE_INDEX   = 8'h55;
+//localparam UIO_FILE_INFO    = 8'h56;
+//localparam UIO_FILE_ADDR    = 8'h57;
+//localparam UIO_FILE_RX      = 8'h58;
+//localparam UIO_FILE_RX_DAT  = 8'h59;
+//
+//always@(posedge clk_sys) begin
+//    reg [15:0] cmd;
+//    reg        has_cmd;
+//    reg [24:0] addr;
+//    reg        wr;
+//    reg        rd;
+//
+//    ioctl_wr <= wr;
+//    ioctl_rd <= rd;
+//    wr <= 0;
+//    rd <= 0;
+//
+//    if(~io_enable) has_cmd <= 0;
+//    else begin
+//        if(io_strobe) begin
+//
+//            if(!has_cmd) begin
+//                cmd <= io_din;
+//                has_cmd <= 1;
+//            end else begin
+//
+//                case(cmd)
+//                    UIO_FILE_ADDR: // Direct setup of address, each byte becomes the lower 7-0 bits of address.
+//                        begin
+//                            addr <= (addr << 8) | io_din[7:0];
+//                        end
+//
+//                    UIO_FILE_INDEX:
+//                        begin
+//                            ioctl_index <= io_din[7:0];
+//                        end
+//
+//                    UIO_FILE_TX:
+//                        begin
+//                            if(io_din[7:0]) begin
+//                                addr <= 0;
+//                                ioctl_download <= 1; 
+//                            end else begin
+//                                ioctl_addr <= addr;
+//                                ioctl_download <= 0;
+//                            end
+//                        end
+//
+//                    UIO_FILE_TX_DAT:
+//                        begin
+//                            ioctl_addr <= addr;
+//                            ioctl_dout <= io_din[DW:0];
+//                            wr   <= 1;
+//                            addr <= addr + (WIDE ? 2'd2 : 2'd1);
+//                        end
+//
+//                    UIO_FILE_RX:
+//                        begin
+//                            if(io_din[7:0]) begin
+//                                addr <= 0;
+//                                ioctl_upload <= 1; 
+//                            end else begin
+//                                ioctl_addr <= addr;
+//                                ioctl_upload <= 0;
+//                            end
+//                        end
+//
+//                    UIO_FILE_RX_DAT:
+//                        begin
+//                            ioctl_addr <= addr;
+//                            rd         <= 1;
+//                            addr       <= addr + (WIDE ? 2'd2 : 2'd1);
+//                        end
+//                endcase
+//            end
+//        end
+//    end
+//end
+
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ps2_device #(parameter PS2_FIFO_BITS=5)
+(
+    input        clk_sys,
+
+    input  [7:0] wdata,
+    input        we,
+
+    input        ps2_clk,
+    output reg   ps2_clk_out,
+    output reg   ps2_dat_out,
+    output reg   tx_empty,
+
+    input        ps2_clk_in,
+    input        ps2_dat_in,
+    
+    output [8:0] rdata,
+    input        rd
+);
+
+
+(* ramstyle = "logic" *) reg [7:0] fifo[1<<PS2_FIFO_BITS];
+
+reg [PS2_FIFO_BITS-1:0] wptr;
+reg [PS2_FIFO_BITS-1:0] rptr;
+
+reg [2:0] rx_state = 0;
+reg [3:0] tx_state = 0;
+
+reg       has_data;
+reg [7:0] data;
+assign    rdata = {has_data, data};
+
+always@(posedge clk_sys) begin
+    reg [7:0] tx_byte;
+    reg parity;
+    reg r_inc;
+    reg old_clk;
+    reg [1:0] timeout;
+
+    reg [3:0] rx_cnt;
+
+    reg c1,c2,d1;
+
+    tx_empty <= ((wptr == rptr) && (tx_state == 0));
+
+    if(we) begin
+        fifo[wptr] <= wdata;
+        wptr <= wptr + 1'd1;
+    end
+
+    if(rd) has_data <= 0;
+
+    c1 <= ps2_clk_in;
+    c2 <= c1;
+    d1 <= ps2_dat_in;
+    if(!rx_state && !tx_state && ~c2 && c1 && ~d1) begin
+        rx_state <= rx_state + 1'b1;
+        ps2_dat_out <= 1;
+    end
+
+    old_clk <= ps2_clk;
+    if(~old_clk & ps2_clk) begin
+
+        if(rx_state) begin
+            case(rx_state)
+                1: begin
+                        rx_state <= rx_state + 1'b1;
+                        rx_cnt <= 0;
+                    end
+                    
+                2: begin
+                        if(rx_cnt <= 7) data <= {d1, data[7:1]};
+                        else rx_state <= rx_state + 1'b1;
+                        rx_cnt <= rx_cnt + 1'b1;
+                    end
+
+                3: if(d1) begin
+                        rx_state <= rx_state + 1'b1;
+                        ps2_dat_out <= 0;
+                    end
+                
+                4: begin
+                        ps2_dat_out <= 1;
+                        has_data <= 1;
+                        rx_state <= 0;
+                    end
+            endcase
+        end else begin
+
+            // transmitter is idle?
+            if(tx_state == 0) begin
+                // data in fifo present?
+                if(c2 && c1 && d1 && wptr != rptr) begin
+
+                    timeout <= timeout - 1'd1;
+                    if(!timeout) begin
+                        tx_byte <= fifo[rptr];
+                        rptr <= rptr + 1'd1;
+
+                        // reset parity
+                        parity <= 1;
+
+                        // start transmitter
+                        tx_state <= 1;
+
+                        // put start bit on data line
+                        ps2_dat_out <= 0;            // start bit is 0
+                    end
+                end
+            end else begin
+
+                // transmission of 8 data bits
+                if((tx_state >= 1)&&(tx_state < 9)) begin
+                    ps2_dat_out <= tx_byte[0];              // data bits
+                    tx_byte[6:0] <= tx_byte[7:1]; // shift down
+                    if(tx_byte[0]) 
+                        parity <= !parity;
+                end
+
+                // transmission of parity
+                if(tx_state == 9) ps2_dat_out <= parity;
+
+                // transmission of stop bit
+                if(tx_state == 10) ps2_dat_out <= 1;    // stop bit is 1
+
+                // advance state machine
+                if(tx_state < 11) tx_state <= tx_state + 1'd1;
+                    else tx_state <= 0;
+            end
+        end
+    end
+
+    if(~old_clk & ps2_clk) ps2_clk_out <= 1;
+    if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2));
+
+end
+
+endmodule
diff --git a/sys/hq2x.sv b/sys/hq2x.sv
new file mode 100644
index 0000000..ece54f9
--- /dev/null
+++ b/sys/hq2x.sv
@@ -0,0 +1,385 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017,2018 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input             clk,
+	input             ce_x4,
+	input  [DWIDTH:0] inputpixel,
+	input             mono,
+	input             disable_hq2x,
+	input             reset_frame,
+	input             reset_line,
+	input       [1:0] read_y,
+	input             hblank,
+	output [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = $clog2(LENGTH)-1;
+localparam DWIDTH = HALF_DEPTH ? 11 : 23;
+localparam DWIDTH1 = DWIDTH+1;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
+reg [23:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] cyc;
+
+reg  curbuf;
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
+wire [23:0] blend_result_pre;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre);
+
+wire [DWIDTH:0] Curr20tmp;
+wire     [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
+wire [DWIDTH:0] Curr21tmp;
+wire     [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [23:0] h2rgb;
+	input [11:0] v;
+begin
+	h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
+end
+endfunction
+
+function [11:0] rgb2h;
+	input [23:0] v;
+begin
+	rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(offs),
+	.rdbuf0(prevbuf),
+	.rdbuf1(curbuf),
+	.q0(Curr20tmp),
+	.q1(Curr21tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg     [AWIDTH+1:0] read_x;
+reg     [AWIDTH+1:0] wrout_addr; 
+reg                  wrout_en;
+reg  [DWIDTH1*4-1:0] wrdata, wrdata_pre;
+wire [DWIDTH1*4-1:0] outpixel_x4;
+reg  [DWIDTH1*2-1:0] outpixel_x2;
+
+assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
+
+hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
+(
+	.clock(clk),
+
+	.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
+	.q(outpixel_x4),
+
+	.data(wrdata),
+	.wraddress(wrout_addr),
+	.wren(wrout_en)
+);
+
+wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
+
+reg [AWIDTH:0] offs;
+always @(posedge clk) begin
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+		if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
+
+		if(~&offs) begin
+			if (cyc == 1) begin
+				Prev2 <= Curr20;
+				Curr2 <= Curr21;
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+
+			case({cyc[1],^cyc})
+				0: wrdata[DWIDTH:0]                   <= blend_result;
+				1: wrdata[DWIDTH1+DWIDTH:DWIDTH1]     <= blend_result;
+				2: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
+				3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
+			endcase
+
+			if(cyc==3) begin
+				offs <= offs + 1'd1;
+				wrout_addr <= {offs, curbuf};
+				wrout_en <= 1;
+			end
+		end
+
+		if(cyc==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		cyc <= cyc + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			cyc <= 0;
+			curbuf <= ~curbuf;
+			prevbuf <= curbuf;
+			{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
+			if(old_reset_frame & ~reset_frame) begin
+				curbuf <= 0;
+				prevbuf <= 0;
+			end
+		end
+		
+		if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
+		if(hblank) read_x <= 0;
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf0, rdbuf1,
+	output[DWIDTH:0] q0,q1,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = $clog2(LENGTH)-1;
+	wire  [DWIDTH:0] out[2];
+	assign q0 = out[rdbuf0];
+	assign q1 = out[rdbuf1];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input                   clock,
+	input        [DWIDTH:0] data,
+	input        [AWIDTH:0] rdaddress,
+	input        [AWIDTH:0] wraddress,
+	input                   wren,
+	output logic [DWIDTH:0] q
+);
+
+logic [DWIDTH:0] ram[0:NUMWORDS-1];
+
+always_ff@(posedge clock) begin
+	if(wren) ram[wraddress] <= data;
+	q <= ram[rdaddress];
+end
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [23:0] rgb1,
+	input [23:0] rgb2,
+	output result
+);
+
+	wire [7:0] r = rgb1[7:1]   - rgb2[7:1];
+	wire [7:0] g = rgb1[15:9]  - rgb2[15:9];
+	wire [7:0] b = rgb1[23:17] - rgb2[23:17];
+	wire [8:0] t = $signed(r) + $signed(b);
+	wire [8:0] gx = {g[7], g};
+	wire [9:0] y = $signed(t) + $signed(gx);
+	wire [8:0] u = $signed(r) - $signed(b);
+	wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-96..96)
+	wire y_inside = (y < 10'h60 || y >= 10'h3a0);
+
+	// if u is inside (-16, 16)
+	wire u_inside = (u < 9'h10 || u >= 9'h1f0);
+
+	// if v is inside (-24, 24)
+	wire v_inside = (v < 10'h18 || v >= 10'h3e8);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [7:0] A,
+	input  [7:0] B,
+	input  [7:0] C,
+	output [7:0] O
+);
+
+	function  [10:0] mul8x3;
+		input   [7:0] op1;
+		input   [2:0] op2;
+	begin
+		mul8x3 = 11'd0;
+		if(op2[0]) mul8x3 = mul8x3 + op1;
+		if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
+		if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [10:0] Amul = mul8x3(A, Op[7:5]);
+	wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
+	wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
+	wire [10:0] At =  Amul;
+	wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [11:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[11:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [23:0] E,
+	input  [23:0] A,
+	input  [23:0] B,
+	input  [23:0] D,
+	input  [23:0] F,
+	input  [23:0] H,
+	output [23:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			 8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			 9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = {11{1'bx}};
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [23:0] Input1 = E;
+	wire [23:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [23:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[7:0],   Input2[7:0],   Input3[7:0],   Result[7:0]);
+	InnerBlend inner_blend2(op, Input1[15:8],  Input2[15:8],  Input3[15:8],  Result[15:8]);
+	InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
+endmodule
diff --git a/sys/i2c.v b/sys/i2c.v
new file mode 100644
index 0000000..1b89b4f
--- /dev/null
+++ b/sys/i2c.v
@@ -0,0 +1,69 @@
+
+module i2c
+(
+	input        CLK,
+
+	input        START,
+	input [23:0] I2C_DATA,
+	output reg   END = 1,
+	output reg   ACK = 0,
+
+	//I2C bus
+	output       I2C_SCL,
+ 	inout        I2C_SDA
+);
+
+
+//	Clock Setting
+parameter CLK_Freq = 50_000_000;	//	50 MHz
+parameter I2C_Freq = 400_000;		//	400 KHz
+
+reg I2C_CLOCK;
+always@(negedge CLK) begin
+	integer mI2C_CLK_DIV = 0;
+	if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin
+		mI2C_CLK_DIV <= mI2C_CLK_DIV + 1;
+	end else	begin
+		mI2C_CLK_DIV <= 0;
+		I2C_CLOCK    <= ~I2C_CLOCK;
+	end
+end
+
+assign I2C_SCL = SCLK | I2C_CLOCK;
+assign I2C_SDA = SDO  ? 1'bz : 1'b0;
+
+reg SCLK = 1, SDO = 1;
+
+always @(posedge CLK) begin
+	reg old_clk;
+	reg old_st;
+
+	reg  [5:0] SD_COUNTER = 'b111111;
+	reg [0:31] SD;
+
+	old_clk <= I2C_CLOCK;
+	old_st  <= START;
+
+	if(~old_st && START) begin
+		SCLK <= 1;
+		SDO  <= 1;
+		ACK  <= 0;
+		END  <= 0;
+		SD   <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011};
+		SD_COUNTER <= 0;
+	end else begin
+		if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
+			SD_COUNTER <= SD_COUNTER + 6'd1;	
+			case(SD_COUNTER)
+				      01: SCLK <= 0;
+				10,19,28: ACK  <= ACK | I2C_SDA;
+				      29: SCLK <= 1;
+				      32: END  <= 1;
+			endcase
+		end
+
+		if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]];
+	end
+end
+
+endmodule
diff --git a/sys/i2s.v b/sys/i2s.v
new file mode 100644
index 0000000..d0480ce
--- /dev/null
+++ b/sys/i2s.v
@@ -0,0 +1,136 @@
+
+module i2s
+#(
+	parameter CLK_RATE   = 50000000,
+	parameter AUDIO_DW   = 16,
+	parameter AUDIO_RATE = 96000
+)
+(
+	input      reset,
+	input      clk_sys,
+	input      half_rate,
+
+	output reg sclk,
+	output reg lrclk,
+	output reg sdata,
+
+	input [AUDIO_DW-1:0]	left_chan,
+	input [AUDIO_DW-1:0]	right_chan
+);
+
+localparam WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
+localparam ERROR_BASE            = 10000;
+localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
+
+reg lpf_ce;
+wire [AUDIO_DW-1:0] al, ar;
+
+lpf_i2s lpf_l
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+   .IDATA(left_chan),
+   .ODATA(al)
+);
+
+lpf_i2s lpf_r
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+
+   .IDATA(right_chan),
+   .ODATA(ar)
+);
+
+always @(posedge clk_sys) begin
+	reg [31:0] count_q;
+	reg [31:0] error_q;
+	reg  [7:0] bit_cnt;
+	reg        skip = 0;
+
+	reg [AUDIO_DW-1:0] left;
+	reg [AUDIO_DW-1:0] right;
+
+	reg msclk;
+	reg ce;
+	
+	lpf_ce <= 0;
+
+	if (reset) begin
+		count_q   <= 0;
+		error_q   <= 0;
+		ce        <= 0;
+		bit_cnt   <= 1;
+		lrclk     <= 1;
+		sclk      <= 1;
+		msclk     <= 1;
+	end
+	else
+	begin
+		if(count_q == WHOLE_CYCLES-1) begin
+			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0];
+				count_q <= 0;
+			end else begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
+				count_q <= count_q + 1;
+			end
+		end else if(count_q == WHOLE_CYCLES) begin
+			count_q <= 0;
+		end else begin
+			count_q <= count_q + 1;
+		end
+
+		sclk <= msclk;
+		if(!count_q) begin
+			ce <= ~ce;
+			if(~half_rate || ce) begin
+				msclk <= ~msclk;
+				if(msclk) begin
+					skip <= ~skip;
+					if(skip) lpf_ce <= 1;
+					if(bit_cnt >= AUDIO_DW) begin
+						bit_cnt <= 1;
+						lrclk <= ~lrclk;
+						if(lrclk) begin
+							left  <= al;
+							right <= ar;
+						end
+					end
+					else begin
+						bit_cnt <= bit_cnt + 1'd1;
+					end
+					sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
+				end
+			end
+		end
+	end
+end
+
+endmodule
+
+module lpf_i2s
+(
+   input         CLK,
+   input         CE,
+   input  [15:0] IDATA,
+   output reg [15:0] ODATA
+);
+
+reg [511:0] acc;
+reg [20:0] sum;
+
+always @(*) begin
+	integer i;
+	sum = 0;
+	for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
+end
+
+always @(posedge CLK) begin
+	if(CE) begin
+		acc <= {acc[495:0], IDATA};
+		ODATA <= sum[20:5];
+	end
+end
+
+endmodule
diff --git a/sys/ip/avalon_combiner.v b/sys/ip/avalon_combiner.v
new file mode 100644
index 0000000..3a26c6a
--- /dev/null
+++ b/sys/ip/avalon_combiner.v
@@ -0,0 +1,60 @@
+// avalon_combiner.v
+
+`timescale 1 ps / 1 ps
+module avalon_combiner
+(
+	input  wire        clk,                //      clock.clk
+	input  wire        rst,                //      reset.reset
+
+	output wire [6:0]  mixer_address,      //  ctl_mixer.address
+	output wire [3:0]  mixer_byteenable,   //           .byteenable
+	output wire        mixer_write,        //           .write
+	output wire [31:0] mixer_writedata,    //           .writedata
+	input  wire        mixer_waitrequest,  //           .waitrequest
+
+	output wire [6:0]  scaler_address,     // ctl_scaler.address
+	output wire [3:0]  scaler_byteenable,  //           .byteenable
+	input  wire        scaler_waitrequest, //           .waitrequest
+	output wire        scaler_write,       //           .write
+	output wire [31:0] scaler_writedata,   //           .writedata
+
+	output wire [7:0]  video_address,      //  ctl_video.address
+	output wire [3:0]  video_byteenable,   //           .byteenable
+	input  wire        video_waitrequest,  //           .waitrequest
+	output wire        video_write,        //           .write
+	output wire [31:0] video_writedata,    //           .writedata
+
+	output wire        clock,              //    control.clock
+	output wire        reset,              //           .reset
+	input  wire [8:0]  address,            //           .address
+	input  wire        write,              //           .write
+	input  wire [31:0] writedata,          //           .writedata
+	output wire        waitrequest         //           .waitrequest
+);
+
+assign clock = clk;
+assign reset = rst;
+
+assign mixer_address  = address[6:0];
+assign scaler_address = address[6:0];
+assign video_address  = address[7:0];
+
+assign mixer_byteenable  = 4'b1111;
+assign scaler_byteenable = 4'b1111;
+assign video_byteenable  = 4'b1111;
+
+wire   en_scaler = (address[8:7] == 0);
+wire   en_mixer  = (address[8:7] == 1);
+wire   en_video  =  address[8];
+
+assign mixer_write  = en_mixer  & write;
+assign scaler_write = en_scaler & write;
+assign video_write  = en_video  & write;
+
+assign mixer_writedata  = writedata;
+assign scaler_writedata = writedata;
+assign video_writedata  = writedata;
+
+assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
+
+endmodule
diff --git a/sys/ip/avalon_combiner_hw.tcl b/sys/ip/avalon_combiner_hw.tcl
new file mode 100644
index 0000000..5eede9c
--- /dev/null
+++ b/sys/ip/avalon_combiner_hw.tcl
@@ -0,0 +1,204 @@
+# TCL File Generated by Component Editor 17.0
+# Wed Dec 13 01:40:49 CST 2017
+# DO NOT MODIFY
+
+
+# 
+# avalon_combiner "avalon_combiner" v17.0
+# sorgelig 2017.12.13.01:40:49
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module avalon_combiner
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME avalon_combiner
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR sorgelig
+set_module_property DISPLAY_NAME avalon_combiner
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset rst reset Input 1
+
+
+# 
+# connection point ctl_mixer
+# 
+add_interface ctl_mixer avalon start
+set_interface_property ctl_mixer addressUnits WORDS
+set_interface_property ctl_mixer associatedClock clock
+set_interface_property ctl_mixer associatedReset reset
+set_interface_property ctl_mixer bitsPerSymbol 8
+set_interface_property ctl_mixer burstOnBurstBoundariesOnly false
+set_interface_property ctl_mixer burstcountUnits WORDS
+set_interface_property ctl_mixer doStreamReads false
+set_interface_property ctl_mixer doStreamWrites false
+set_interface_property ctl_mixer holdTime 0
+set_interface_property ctl_mixer linewrapBursts false
+set_interface_property ctl_mixer maximumPendingReadTransactions 0
+set_interface_property ctl_mixer maximumPendingWriteTransactions 0
+set_interface_property ctl_mixer readLatency 0
+set_interface_property ctl_mixer readWaitTime 1
+set_interface_property ctl_mixer setupTime 0
+set_interface_property ctl_mixer timingUnits Cycles
+set_interface_property ctl_mixer writeWaitTime 0
+set_interface_property ctl_mixer ENABLED true
+set_interface_property ctl_mixer EXPORT_OF ""
+set_interface_property ctl_mixer PORT_NAME_MAP ""
+set_interface_property ctl_mixer CMSIS_SVD_VARIABLES ""
+set_interface_property ctl_mixer SVD_ADDRESS_GROUP ""
+
+add_interface_port ctl_mixer mixer_address address Output 7
+add_interface_port ctl_mixer mixer_byteenable byteenable Output 4
+add_interface_port ctl_mixer mixer_write write Output 1
+add_interface_port ctl_mixer mixer_writedata writedata Output 32
+add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1
+
+
+# 
+# connection point ctl_scaler
+# 
+add_interface ctl_scaler avalon start
+set_interface_property ctl_scaler addressUnits WORDS
+set_interface_property ctl_scaler associatedClock clock
+set_interface_property ctl_scaler associatedReset reset
+set_interface_property ctl_scaler bitsPerSymbol 8
+set_interface_property ctl_scaler burstOnBurstBoundariesOnly false
+set_interface_property ctl_scaler burstcountUnits WORDS
+set_interface_property ctl_scaler doStreamReads false
+set_interface_property ctl_scaler doStreamWrites false
+set_interface_property ctl_scaler holdTime 0
+set_interface_property ctl_scaler linewrapBursts false
+set_interface_property ctl_scaler maximumPendingReadTransactions 0
+set_interface_property ctl_scaler maximumPendingWriteTransactions 0
+set_interface_property ctl_scaler readLatency 0
+set_interface_property ctl_scaler readWaitTime 1
+set_interface_property ctl_scaler setupTime 0
+set_interface_property ctl_scaler timingUnits Cycles
+set_interface_property ctl_scaler writeWaitTime 0
+set_interface_property ctl_scaler ENABLED true
+set_interface_property ctl_scaler EXPORT_OF ""
+set_interface_property ctl_scaler PORT_NAME_MAP ""
+set_interface_property ctl_scaler CMSIS_SVD_VARIABLES ""
+set_interface_property ctl_scaler SVD_ADDRESS_GROUP ""
+
+add_interface_port ctl_scaler scaler_address address Output 7
+add_interface_port ctl_scaler scaler_byteenable byteenable Output 4
+add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1
+add_interface_port ctl_scaler scaler_write write Output 1
+add_interface_port ctl_scaler scaler_writedata writedata Output 32
+
+
+# 
+# connection point ctl_video
+# 
+add_interface ctl_video avalon start
+set_interface_property ctl_video addressUnits WORDS
+set_interface_property ctl_video associatedClock clock
+set_interface_property ctl_video associatedReset reset
+set_interface_property ctl_video bitsPerSymbol 8
+set_interface_property ctl_video burstOnBurstBoundariesOnly false
+set_interface_property ctl_video burstcountUnits WORDS
+set_interface_property ctl_video doStreamReads false
+set_interface_property ctl_video doStreamWrites false
+set_interface_property ctl_video holdTime 0
+set_interface_property ctl_video linewrapBursts false
+set_interface_property ctl_video maximumPendingReadTransactions 0
+set_interface_property ctl_video maximumPendingWriteTransactions 0
+set_interface_property ctl_video readLatency 0
+set_interface_property ctl_video readWaitTime 1
+set_interface_property ctl_video setupTime 0
+set_interface_property ctl_video timingUnits Cycles
+set_interface_property ctl_video writeWaitTime 0
+set_interface_property ctl_video ENABLED true
+set_interface_property ctl_video EXPORT_OF ""
+set_interface_property ctl_video PORT_NAME_MAP ""
+set_interface_property ctl_video CMSIS_SVD_VARIABLES ""
+set_interface_property ctl_video SVD_ADDRESS_GROUP ""
+
+add_interface_port ctl_video video_address address Output 8
+add_interface_port ctl_video video_byteenable byteenable Output 4
+add_interface_port ctl_video video_waitrequest waitrequest Input 1
+add_interface_port ctl_video video_write write Output 1
+add_interface_port ctl_video video_writedata writedata Output 32
+
+
+# 
+# connection point control
+# 
+add_interface control conduit end
+set_interface_property control associatedClock clock
+set_interface_property control associatedReset reset
+set_interface_property control ENABLED true
+set_interface_property control EXPORT_OF ""
+set_interface_property control PORT_NAME_MAP ""
+set_interface_property control CMSIS_SVD_VARIABLES ""
+set_interface_property control SVD_ADDRESS_GROUP ""
+
+add_interface_port control address address Input 9
+add_interface_port control write write Input 1
+add_interface_port control writedata writedata Input 32
+add_interface_port control waitrequest waitrequest Output 1
+add_interface_port control clock clock Output 1
+add_interface_port control reset reset Output 1
+
diff --git a/sys/ip/de10_hps_hw.tcl b/sys/ip/de10_hps_hw.tcl
new file mode 100644
index 0000000..a166ca0
--- /dev/null
+++ b/sys/ip/de10_hps_hw.tcl
@@ -0,0 +1,3706 @@
+# (C) 2001-2017 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel MegaCore Function License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+# This IP is modified standard Altera HPS IP.
+# Direct DDR3 SDRAM access has been removed since it won't work together with HPS DDR3 SDRAM access.
+# FPGA access the memory through MPFE (FPGA2SDRAM bridge).
+# By removing direct DDR3 SDRAM access synthesis time has been reduced by 3 times!
+
+
+package require -exact qsys 12.0
+package require -exact altera_terp 1.0
+package require quartus::advanced_wysiwyg
+
+set_module_property NAME altera_hps_lite
+set_module_property VERSION 17.0
+set_module_property AUTHOR "Altera Corporation/Sorgelig"                
+set_module_property SUPPORTED_DEVICE_FAMILIES {CYCLONEV ARRIAV}
+
+set_module_property DISPLAY_NAME "DE10-nano Hard Processor System"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE false
+set_module_property HIDE_FROM_SOPC true
+set_module_property HIDE_FROM_QUARTUS true
+
+add_documentation_link "HPS User Guide for Cyclone V" "http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf"
+add_documentation_link "HPS User Guide for Arria V"   "http://www.altera.com/literature/hb/arria-v/av_5v4.pdf"
+
+set alt_mem_if_tcl_libs_dir "$env(QUARTUS_ROOTDIR)/../ip/altera/alt_mem_if/alt_mem_if_tcl_packages"
+if {[lsearch -exact $auto_path $alt_mem_if_tcl_libs_dir] == -1} {                                                                                           
+	lappend auto_path $alt_mem_if_tcl_libs_dir
+} 
+
+package require alt_mem_if::gui::system_info
+
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/constants.tcl
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/procedures.tcl
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux.tcl
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux_db.tcl
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/locations.tcl
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/ui.tcl
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clocks.tcl
+source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clock_manager.tcl
+
+proc add_storage_parameter {name { default_value {} } } {
+    add_parameter $name string $default_value ""
+    set_parameter_property $name derived true
+    set_parameter_property $name visible false   
+}
+
+proc add_reset_parameters {} {
+    set group_name "Resets"
+    add_display_item "FPGA Interfaces" $group_name "group" ""
+
+    add_parameter           S2FCLK_COLDRST_Enable boolean false ""
+    set_parameter_property  S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output"
+    set_parameter_property  S2FCLK_COLDRST_Enable group $group_name
+    
+    add_parameter           S2FCLK_PENDINGRST_Enable boolean false ""
+    set_parameter_property  S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals"
+    set_parameter_property  S2FCLK_PENDINGRST_Enable group $group_name
+
+    add_parameter           F2SCLK_DBGRST_Enable boolean false ""
+    set_parameter_property  F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request"
+    set_parameter_property  F2SCLK_DBGRST_Enable group $group_name
+    
+    add_parameter           F2SCLK_WARMRST_Enable boolean false ""
+    set_parameter_property  F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request"
+    set_parameter_property  F2SCLK_WARMRST_Enable group $group_name
+    
+    add_parameter           F2SCLK_COLDRST_Enable boolean false ""
+    set_parameter_property  F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request"
+    set_parameter_property  F2SCLK_COLDRST_Enable group $group_name
+
+}
+
+proc list_h2f_interrupt_groups {} {
+    return {
+	"CAN"      "CLOCKPERIPHERAL" "CTI"
+	"DMA"      "EMAC"            "FPGAMANAGER" 
+	"GPIO"     "I2CEMAC"         "I2CPERIPHERAL"
+	"L4TIMER"  "NAND"            "OSCTIMER"
+	"QSPI"     "SDMMC"           "SPIMASTER"
+	"SPISLAVE" "UART" 	     "USB"
+	"WATCHDOG"       
+    }
+}
+
+proc get_h2f_interrupt_descriptions {data_ref} {
+    upvar 1 $data_ref data
+    array set data {
+	"DMA"             "Enable DMA interrupts"
+	"EMAC"            "Enable EMAC interrupts (for EMAC0 and EMAC1)"
+	"USB"             "Enable USB interrupts"
+	"CAN"             "Enable CAN interrupts"
+	"SDMMC"           "Enable SD/MMC interrupt"
+	"NAND"		  "Enable NAND interrupt"
+	"QSPI"		  "Enable Quad SPI interrupt"
+	"SPIMASTER"	  "Enable SPI master interrupts"
+	"SPISLAVE"	  "Enable SPI slave interrupts"
+	"I2CPERIPHERAL"   "Enable I2C peripheral interrupts (for I2C0 and I2C1)"
+	"I2CEMAC"	  "Enable I2C-EMAC interrupts (for I2C2 and I2C3)"
+	"UART" 		  "Enable UART interrupts"
+	"GPIO"		  "Enable GPIO interrupts"
+	"L4TIMER"	  "Enable L4 timer interrupts"
+	"OSCTIMER"	  "Enable OSC timer interrupts"
+	"WATCHDOG"	  "Enable watchdog interrupts"
+	"CLOCKPERIPHERAL" "Enable clock peripheral interrupts"
+	"FPGAMANAGER" 	  "Enable FPGA manager interrupt"
+	"CTI"             "Enable CTI interrupts"
+    }
+}
+
+proc load_h2f_interrupt_table {functions_by_group_ref
+			       width_by_function_ref
+			       inverted_by_function_ref} {
+    upvar 1 $functions_by_group_ref   functions_by_group
+    upvar 1 $width_by_function_ref    width_by_function
+    upvar 1 $inverted_by_function_ref inverted_by_function
+    array set functions_by_group {
+ 	"DMA"             {"dma"       "dma_abort"        }
+	"EMAC"            {"emac0"     "emac1"            }
+	"USB"             {"usb0"      "usb1"             }
+	"CAN"             {"can0"      "can1"             }
+	"SDMMC"           {"sdmmc"                        }
+	"NAND"		  {"nand"                         }
+	"QSPI"		  {"qspi"                         }
+	"SPIMASTER"	  {"spi0"      "spi1"             }
+	"SPISLAVE"	  {"spi2"      "spi3"             }
+	"I2CPERIPHERAL"   {"i2c0"      "i2c1"             }
+	"I2CEMAC"	  {"i2c_emac0" "i2c_emac1"        }
+	"UART" 		  {"uart0"     "uart1"            }
+	"GPIO"		  {"gpio0"     "gpio1"     "gpio2"}
+	"L4TIMER"	  {"l4sp0"     "l4sp1"            }
+	"OSCTIMER"	  {"osc0"      "osc1"             }
+	"WATCHDOG"	  {"wdog0"     "wdog1"            }
+	"CLOCKPERIPHERAL" {"clkmgr"    "mpuwakeup"        }
+	"FPGAMANAGER" 	  {"fpga_man"                     }
+	"CTI"             {"cti"                          }
+    }
+    array set width_by_function {
+	"dma"        8
+	"cti"        2
+    }
+    array set inverted_by_function {
+	"cti" 1
+    }
+}
+
+proc add_interrupt_parameters {} {
+    set top_group_name "Interrupts"
+    add_display_item "FPGA Interfaces" $top_group_name "group" ""
+    
+    #    add_display_item $group_name "f2h_interrupts_label" "text" "FPGA-to-HPS"
+    add_parameter            F2SINTERRUPT_Enable   boolean        false
+    set_parameter_property   F2SINTERRUPT_Enable   enabled        true
+    set_parameter_property   F2SINTERRUPT_Enable   display_name   "Enable FPGA-to-HPS Interrupts"
+    set_parameter_property   F2SINTERRUPT_Enable   group          $top_group_name 
+    
+    set inner_group_name "HPS-to-FPGA"
+    add_display_item $top_group_name $inner_group_name "group" ""
+    get_h2f_interrupt_descriptions descriptions_by_group
+    set interrupt_groups [list_h2f_interrupt_groups]
+    foreach interrupt_group $interrupt_groups {
+	set parameter "S2FINTERRUPT_${interrupt_group}_Enable"
+	add_parameter          $parameter boolean      false
+	set_parameter_property $parameter enabled      true
+	set_parameter_property $parameter display_name $descriptions_by_group($interrupt_group)
+	set_parameter_property $parameter group        $inner_group_name
+    }
+}
+
+proc add_dma_parameters {} {
+    set group_name "DMA Peripheral Request"
+    add_display_item "FPGA Interfaces" $group_name "group" ""
+    add_display_item $group_name "DMA Table" "group" "table"
+
+    add_parameter           DMA_PeriphId_DERIVED string_list {0 1 2 3 4 5 6 7}
+    set_parameter_property  DMA_PeriphId_DERIVED display_name "Peripheral Request ID"
+    set_parameter_property  DMA_PeriphId_DERIVED derived true
+    set_parameter_property  DMA_PeriphId_DERIVED display_hint "FIXED_SIZE"
+    set_parameter_property  DMA_PeriphId_DERIVED group "DMA Table"
+ 
+    add_parameter           DMA_Enable string_list {"No" "No" "No" "No" "No" "No" "No" "No"}
+    set_parameter_property  DMA_Enable allowed_ranges {"Yes" "No"}
+    set_parameter_property  DMA_Enable display_name "Enabled"
+    set_parameter_property  DMA_Enable display_hint "FIXED_SIZE"
+    set_parameter_property  DMA_Enable group "DMA Table"
+}
+                                                     
+proc range_from_zero {end} {
+    set result [list]
+    for {set i 0} {$i <= $end} {incr i} {
+	lappend result $i
+    }
+    return $result
+}
+
+proc create_generic_parameters {} {
+	
+	::alt_mem_if::util::hwtcl_utils::_add_parameter SYS_INFO_DEVICE_FAMILY STRING "" 
+	set_parameter_property SYS_INFO_DEVICE_FAMILY SYSTEM_INFO DEVICE_FAMILY
+	set_parameter_property SYS_INFO_DEVICE_FAMILY VISIBLE FALSE
+	
+	::alt_mem_if::util::hwtcl_utils::_add_parameter DEVICE_FAMILY STRING "" 
+	set_parameter_property DEVICE_FAMILY DERIVED true
+	set_parameter_property DEVICE_FAMILY VISIBLE FALSE
+
+	return 1
+}
+
+create_generic_parameters
+
+add_display_item "" "FPGA Interfaces"  "group" "tab"   
+add_display_item "" "Peripheral Pins"    "group" "tab"                        
+add_display_item "" "HPS Clocks" "group" "tab" 
+add_clock_tab "HPS Clocks"
+
+add_display_item "FPGA Interfaces" "General"          "group" ""
+                                                                  
+add_parameter            MPU_EVENTS_Enable  boolean        true
+set_parameter_property   MPU_EVENTS_Enable  display_name   "Enable MPU standby and event signals"
+set_parameter_property   MPU_EVENTS_Enable  description    "Enables elaboration of the mpu_events interface."
+set_parameter_property   MPU_EVENTS_Enable  group          "General"
+
+add_parameter            GP_Enable   boolean        false
+set_parameter_property   GP_Enable   display_name   "Enable general purpose signals"
+set_parameter_property   GP_Enable   description    "Enables elaboration of interface h2f_gp."
+set_parameter_property   GP_Enable   group          "General"
+
+add_parameter            DEBUGAPB_Enable  boolean       false
+set_parameter_property   DEBUGAPB_Enable  display_name  "Enable Debug APB interface"
+set_parameter_property   DEBUGAPB_Enable  description   "Enables elaboration of Debug APB interfaces."
+set_parameter_property   DEBUGAPB_Enable  group         "General"
+
+add_parameter            STM_Enable   boolean        false
+set_parameter_property   STM_Enable   display_name   "Enable System Trace Macrocell hardware events"
+set_parameter_property   STM_Enable   description    "Enables elaboration of interface stm_hwevents."
+set_parameter_property   STM_Enable   group          "General"
+
+add_parameter            CTI_Enable   boolean        false
+set_parameter_property   CTI_Enable   display_name   "Enable FPGA Cross Trigger Interface"
+set_parameter_property   CTI_Enable   description    "Enables elaboration of interface cti_trigger, cti_clk_in."
+set_parameter_property   CTI_Enable   group          "General"
+
+add_parameter            TPIUFPGA_Enable   boolean        false
+set_parameter_property   TPIUFPGA_Enable   display_name   "Enable FPGA Trace Port Interface Unit"
+set_parameter_property   TPIUFPGA_Enable   description    "Enables elaboration of TPIU FPGA interfaces."
+set_parameter_property   TPIUFPGA_Enable   group          "General"
+
+add_parameter            TPIUFPGA_alt   boolean        false
+set_parameter_property   TPIUFPGA_alt   display_name   "Enable FPGA Trace Port Alternate FPGA Interface"
+set_parameter_property   TPIUFPGA_alt   description    "When the trace port is enabled, it creates an interface compatible with the Arria 10 Trace Interface. (This just moves the clock_in port into the same conduit)"
+set_parameter_property   TPIUFPGA_alt   group          "General"
+set_parameter_property   TPIUFPGA_alt   enabled        false
+
+
+add_parameter            BOOTFROMFPGA_Enable   boolean        false
+set_parameter_property   BOOTFROMFPGA_Enable   enabled        true
+set_parameter_property   BOOTFROMFPGA_Enable   display_name   "Enable boot from fpga signals"
+set_parameter_property   BOOTFROMFPGA_Enable   description    "Enables elaboration of interface boot_from_fpga."
+set_parameter_property   BOOTFROMFPGA_Enable   group          "General"
+
+add_parameter            TEST_Enable  boolean        false
+set_parameter_property   TEST_Enable  enabled        true
+set_parameter_property   TEST_Enable  display_name   "Enable Test Interface"
+set_parameter_property   TEST_Enable  group          "General"
+
+add_parameter            HLGPI_Enable  boolean        false
+set_parameter_property   HLGPI_Enable  enabled        true
+set_parameter_property   HLGPI_Enable  display_name   "Enable HLGPI Interface"
+set_parameter_property   HLGPI_Enable  group          "General"
+
+add_display_item "FPGA Interfaces" "Boot and Clock Selection" "group" ""
+add_parameter            BSEL_EN      boolean        false
+set_parameter_property   BSEL_EN      enabled        true
+set_parameter_property   BSEL_EN      display_name   "Enable boot selection from FPGA"
+set_parameter_property   BSEL_EN      group          "Boot and Clock Selection"
+set_parameter_property   BSEL_EN      visible        false
+set_parameter_property   BSEL_EN      enabled        false
+
+add_parameter            BSEL         integer 1
+set_parameter_property   BSEL         allowed_ranges {"1:FPGA" "2:NAND Flash (1.8v)" "3:NAND Flash (3.0v)" "4:SD/MMC External Transceiver (1.8v)" "5:SD/MMC Internal Transceiver (3.0v)" "6:Quad SPI Flash (1.8v)" "7:Quad SPI Flash (3.0v)"}
+set_parameter_property   BSEL         display_name   "Boot selection from FPGA"
+set_parameter_property   BSEL         group          "Boot and Clock Selection"
+set_parameter_property   BSEL         visible        false
+set_parameter_property   BSEL         enabled        false
+
+add_parameter            CSEL_EN      boolean        false
+set_parameter_property   CSEL_EN      enabled        true
+set_parameter_property   CSEL_EN      display_name   "Enable clock selection from FPGA"
+set_parameter_property   CSEL_EN      group          "Boot and Clock Selection"
+set_parameter_property   CSEL_EN      visible        false
+set_parameter_property   CSEL_EN      enabled        false
+
+add_parameter            CSEL         integer 0
+set_parameter_property   CSEL         allowed_ranges {"0:CSEL_0" "1:CSEL_1" "2:CSEL_2" "3:CSEL_3"}
+set_parameter_property   CSEL         display_name   "Clock selection from FPGA"
+set_parameter_property   CSEL         group          "Boot and Clock Selection"
+set_parameter_property   CSEL         visible        false
+set_parameter_property   CSEL         enabled        false
+
+add_display_item "FPGA Interfaces"   "AXI Bridges" "group" ""
+add_parameter            F2S_Width  integer 2
+set_parameter_property   F2S_Width  allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"}
+set_parameter_property   F2S_Width  display_name   "FPGA-to-HPS interface width"
+set_parameter_property   F2S_Width  hdl_parameter  true
+set_parameter_property   F2S_Width  group          "AXI Bridges"
+
+add_parameter            S2F_Width  integer 2
+set_parameter_property   S2F_Width  allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"}
+set_parameter_property   S2F_Width  display_name   "HPS-to-FPGA interface width"
+set_parameter_property   S2F_Width  hdl_parameter  true
+set_parameter_property   S2F_Width  group          "AXI Bridges"
+
+add_parameter            LWH2F_Enable string true
+set_parameter_property   LWH2F_Enable display_name "Lightweight HPS-to-FPGA interface width"
+set_parameter_property   LWH2F_Enable description  "The lightweight HPS-to-FPGA bridge provides a secondary, fixed-width, smaller address space, lower-performance master interface to the FPGA fabric. Use the lightweight HPS-to-FPGA bridge for high-latency, low-bandwidth traffic, such as memory-mapped register accesses of FPGA peripherals. This approach diverts traffic from the high-performance HPS-to-FPGA bridge, which can improve overall performance."
+set_parameter_property   LWH2F_Enable allowed_ranges {"true:32-bit" "false:Unused"}
+set_parameter_property   LWH2F_Enable group "AXI Bridges"
+
+
+set group_name "FPGA-to-HPS SDRAM Interface"
+add_display_item "FPGA Interfaces" $group_name "group" ""
+add_display_item $group_name "f2sdram_label" "text" "Click the '+' and '-' buttons to add and remove FPGA-to-HPS SDRAM ports."
+set table_name "F2SDRAM Settings"
+add_display_item $group_name $table_name "group" "table"
+
+add_parameter            F2SDRAM_Name_DERIVED   string_list   {"f2h_sdram0"}
+set_parameter_property   F2SDRAM_Name_DERIVED   derived       true
+set_parameter_property   F2SDRAM_Name_DERIVED   display_name  "Name"
+set_parameter_property   F2SDRAM_Name_DERIVED   group         $table_name
+
+add_parameter            F2SDRAM_Type   string_list  [list [F2HSDRAM_AXI3]]
+set_parameter_property   F2SDRAM_Type   allowed_ranges [list [F2HSDRAM_AXI3] [F2HSDRAM_AVM] [F2HSDRAM_AVM_WRITEONLY] [F2HSDRAM_AVM_READONLY]]
+set_parameter_property   F2SDRAM_Type   display_name   "Type"
+set_parameter_property   F2SDRAM_Type   group          $table_name
+
+add_parameter                 F2SDRAM_Width   integer_list   {"64"}
+set_parameter_property        F2SDRAM_Width   allowed_ranges "32,64,128,256"
+set_parameter_property        F2SDRAM_Width   display_name   "Width"
+set_parameter_property        F2SDRAM_Width   group          $table_name
+set_parameter_update_callback F2SDRAM_Width on_altered_f2sdram_width
+# TODO: f2sdram derived parameters for resource counts in the table
+# TODO: f2sdram derived parameters for remaining resources, not a part of the table
+
+add_storage_parameter  F2SDRAM_Width_Last_Size 1
+add_storage_parameter  F2SDRAM_CMD_PORT_USED 0
+add_storage_parameter  F2SDRAM_WR_PORT_USED 0
+add_storage_parameter  F2SDRAM_RD_PORT_USED 0
+add_storage_parameter  F2SDRAM_RST_PORT_USED 0
+set_parameter_property F2SDRAM_Width_Last_Size group $group_name
+set_parameter_property F2SDRAM_CMD_PORT_USED   group $group_name
+set_parameter_property F2SDRAM_WR_PORT_USED    group $group_name
+set_parameter_property F2SDRAM_RD_PORT_USED    group $group_name
+set_parameter_property F2SDRAM_RST_PORT_USED    group $group_name
+
+#Parameter to export Bonding_out signal from fpga2sdram Atom 
+add_parameter		BONDING_OUT_ENABLED	boolean		false
+set_parameter_property	BONDING_OUT_ENABLED	display_name	"Enable BONDING-OUT signals"
+set_parameter_property	BONDING_OUT_ENABLED	group		$group_name
+set_parameter_property	BONDING_OUT_ENABLED	enabled		false
+set_parameter_property	BONDING_OUT_ENABLED	visible		false
+
+
+proc on_altered_f2sdram_width { param } {
+    set old_size [get_parameter_value F2SDRAM_Width_Last_Size]
+    set current_value [get_parameter_value F2SDRAM_Width]
+    set current_size  [llength $current_value]
+    
+    if {$current_size == $old_size + 1} { ;# look for case of newly added row
+	set last_element_index [expr {$current_size - 1}]
+	set new_value [lreplace $current_value $last_element_index $last_element_index "64"]
+	set_parameter_value F2SDRAM_Width $new_value
+    }
+}
+
+add_reset_parameters
+
+add_dma_parameters
+
+add_interrupt_parameters
+
+    set group_name "EMAC ptp interface"
+    add_display_item "FPGA Interfaces" $group_name     "group" ""
+
+    add_parameter            EMAC0_PTP  boolean        false
+    set_parameter_property   EMAC0_PTP  display_name   "Enable EMAC0 Precision Time Protocol (PTP) FPGA Interface"
+    set_parameter_property   EMAC0_PTP  hdl_parameter  false
+    set_parameter_property   EMAC0_PTP  enabled        false
+    set_parameter_property   EMAC0_PTP  group          $group_name
+    set_parameter_property   EMAC0_PTP  description    "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available."
+
+    add_parameter            EMAC1_PTP  boolean        false
+    set_parameter_property   EMAC1_PTP  display_name   "Enable EMAC1 Precision Time Protocol (PTP) FPGA Interface"
+    set_parameter_property   EMAC1_PTP  hdl_parameter  false
+    set_parameter_property   EMAC1_PTP  enabled        false
+    set_parameter_property   EMAC1_PTP  group          $group_name
+    set_parameter_property   EMAC1_PTP  description    "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available."
+
+
+proc make_mode_display_name {peripheral} {
+    set default_suffix "mode"
+    array set custom_suffix_by_peripheral {
+	USB0 "PHY interface mode"
+	USB1 "PHY interface mode"
+    }
+    if {[info exists custom_suffix_by_peripheral($peripheral)]} {
+	set suffix $custom_suffix_by_peripheral($peripheral)
+    } else {
+	set suffix $default_suffix
+    }
+    
+    set display_name "${peripheral} ${suffix}"
+    return $display_name
+}
+
+proc add_peripheral_pin_muxing_parameters {} {
+    set TOP_LEVEL_GROUP_NAME "Peripheral Pins"    
+                                                                     
+    
+    foreach group_name [list_group_names] {
+	add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" ""
+	
+	foreach peripheral_name [peripherals_in_group $group_name] {
+	    set pin_muxing_param_name "${peripheral_name}_PinMuxing"
+	    set mode_param_name       "${peripheral_name}_Mode"             
+	    add_parameter                 $pin_muxing_param_name  string [UNUSED_MUX_VALUE]
+	    set_parameter_property        $pin_muxing_param_name  enabled          false
+	    set_parameter_property        $pin_muxing_param_name  display_name     "${peripheral_name} pin"
+	    set_parameter_property        $pin_muxing_param_name  allowed_ranges   [UNUSED_MUX_VALUE]
+	    set_parameter_property        $pin_muxing_param_name  group            $group_name
+	    set_parameter_update_callback $pin_muxing_param_name  on_altered_peripheral_pin_muxing $peripheral_name
+	    
+	    set mode_display_name [make_mode_display_name $peripheral_name]
+	    add_parameter            $mode_param_name        string [NA_MODE_VALUE]
+	    set_parameter_property   $mode_param_name        enabled          false
+	    set_parameter_property   $mode_param_name        display_name     $mode_display_name
+	    set_parameter_property   $mode_param_name        allowed_ranges   [NA_MODE_VALUE]
+	    set_parameter_property   $mode_param_name        group            $group_name
+
+	    if {[string match "*EMAC*" $peripheral_name]} {
+		set_parameter_update_callback $mode_param_name on_emac_mode_switch_internal $peripheral_name
+	    }
+	}
+    }
+}
+add_peripheral_pin_muxing_parameters
+
+proc add_gpio_parameters {} {
+    set TOP_LEVEL_GROUP_NAME "Peripheral Pins"
+    set group_name "Peripherals Mux Table"
+    set table_name "Conflict Table"
+    
+    add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" ""
+    #add_display_item $group_name $table_name "group" "table"
+
+    add_parameter           Customer_Pin_Name_DERIVED  string_list {}
+    set_parameter_property  Customer_Pin_Name_DERIVED  display_name "Pin Name"
+    set_parameter_property  Customer_Pin_Name_DERIVED  derived true
+    set_parameter_property  Customer_Pin_Name_DERIVED  display_hint "FIXED_SIZE"
+    set_parameter_property Customer_Pin_Name_DERIVED visible false
+   # set_parameter_property  Customer_Pin_Name_DERIVED  group $table_name 
+       
+    add_parameter           GPIO_Conflict_DERIVED string_list {}
+    set_parameter_property  GPIO_Conflict_DERIVED display_name "Used by"
+    set_parameter_property  GPIO_Conflict_DERIVED derived true
+    set_parameter_property  GPIO_Conflict_DERIVED display_hint "FIXED_SIZE"
+    set_parameter_property GPIO_Conflict_DERIVED visible false
+    #set_parameter_property  GPIO_Conflict_DERIVED group $table_name
+
+    add_parameter           GPIO_Name_DERIVED string_list {}
+    set_parameter_property  GPIO_Name_DERIVED display_name "GPIO"
+    set_parameter_property  GPIO_Name_DERIVED derived true
+    set_parameter_property  GPIO_Name_DERIVED display_hint "FIXED_SIZE"
+     set_parameter_property GPIO_Name_DERIVED visible false
+    #set_parameter_property  GPIO_Name_DERIVED group $table_name
+    
+    # TODO: change?
+    set max_possible_gpio_options 100
+    set enable_list [list]
+    for {set i 0} {$i < $max_possible_gpio_options} {incr i} {
+	lappend enable_list "No"
+    }
+ 
+    add_parameter           GPIO_Enable string_list $enable_list
+    set_parameter_property  GPIO_Enable allowed_ranges {"Yes" "No"}
+    set_parameter_property  GPIO_Enable display_name "GPIO Enabled"
+       set_parameter_property GPIO_Enable visible false
+  #  set_parameter_property  GPIO_Enable group $table_name
+
+    add_parameter           LOANIO_Name_DERIVED string_list {}
+    set_parameter_property  LOANIO_Name_DERIVED display_name "Loan I/O"
+    set_parameter_property  LOANIO_Name_DERIVED derived true
+    set_parameter_property  LOANIO_Name_DERIVED display_hint "FIXED_SIZE"
+    set_parameter_property LOANIO_Name_DERIVED visible false  
+
+    add_parameter           GPIO_Pin_Used_DERIVED boolean false
+    set_parameter_property  GPIO_Pin_Used_DERIVED display_name "GPIO Pin Used"
+    set_parameter_property  GPIO_Pin_Used_DERIVED derived true
+    set_parameter_property  GPIO_Pin_Used_DERIVED display_hint "GPIO Pin Used"
+    set_parameter_property  GPIO_Pin_Used_DERIVED visible false
+
+    add_parameter           LOANIO_Enable string_list $enable_list
+    set_parameter_property  LOANIO_Enable allowed_ranges {"Yes" "No"}
+    set_parameter_property  LOANIO_Enable display_name "Loan I/O Enabled"
+    set_parameter_property LOANIO_Enable visible false
+    #set_parameter_property  LOANIO_Enable group $table_name
+
+    
+
+}
+add_gpio_parameters
+
+proc add_reset_parameters {} {
+    set group_name "Resets"
+    add_display_item "FPGA Interfaces" $group_name "group" ""
+
+    add_parameter           S2FCLK_COLDRST_Enable boolean false ""
+    set_parameter_property  S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output"
+    set_parameter_property  S2FCLK_COLDRST_Enable group $group_name
+    
+    add_parameter           S2FCLK_PENDINGRST_Enable boolean false ""
+    set_parameter_property  S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals"
+    set_parameter_property  S2FCLK_PENDINGRST_Enable group $group_name
+
+    add_parameter           F2SCLK_DBGRST_Enable boolean false ""
+    set_parameter_property  F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request"
+    set_parameter_property  F2SCLK_DBGRST_Enable group $group_name
+    
+    add_parameter           F2SCLK_WARMRST_Enable boolean false ""
+    set_parameter_property  F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request"
+    set_parameter_property  F2SCLK_WARMRST_Enable group $group_name
+    
+    add_parameter           F2SCLK_COLDRST_Enable boolean false ""
+    set_parameter_property  F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request"                                                  
+    set_parameter_property  F2SCLK_COLDRST_Enable group $group_name
+
+}                                                              
+                                                                                                        
+proc add_java_gui_parameters {} {                                                                                
+    set TOP_LEVEL_GROUP_NAME "Peripheral Pins"
+    set group_name "Peripherals Mux Table"   
+    
+    add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" ""
+   # add_display_item $group_name the_widget "group" ""
+      
+    add_parameter           JAVA_CONFLICT_PIN string_list {}
+    set_parameter_property  JAVA_CONFLICT_PIN derived true
+    set_parameter_property  JAVA_CONFLICT_PIN visible false
+    
+    
+    add_parameter           JAVA_GUI_PIN_LIST string_list {}
+    set_parameter_property  JAVA_GUI_PIN_LIST derived true
+    set_parameter_property  JAVA_GUI_PIN_LIST visible false
+       
+     set peripherals [list_peripheral_names]  
+     set widget_parameter [list \
+     Customer_Pin_Name_DERIVED Customer_Pin_Name_DERIVED \
+     GPIO_Name_DERIVED GPIO_Name_DERIVED \
+     LOANIO_Name_DERIVED LOANIO_Name_DERIVED \
+     LOANIO_Enable LOANIO_Enable \
+     GPIO_Enable GPIO_Enable \
+     JAVA_CONFLICT_PIN GUI_Conflict_Pins_List \
+     JAVA_GUI_PIN_LIST GUI_GPIO_Pins_List]        
+     
+    foreach peripheral_name $peripherals {        
+    	 add_parameter "JAVA_${peripheral_name}_DATA"  string ""
+    	 set_parameter_property "JAVA_${peripheral_name}_DATA"  derived true
+    	 set_parameter_property "JAVA_${peripheral_name}_DATA"  visible false 
+                                                                           
+    	lappend widget_parameter "JAVA_${peripheral_name}_DATA" 
+    	lappend widget_parameter "${peripheral_name}_pin_muxing" 
+    	lappend widget_parameter "${peripheral_name}_PinMuxing"
+    	lappend widget_parameter "${peripheral_name}_PinMuxing"
+    	lappend widget_parameter "${peripheral_name}_Mode"  
+    	lappend widget_parameter "${peripheral_name}_Mode"  
+    }                                       
+      
+    add_display_item $group_name the_widget "group"                                                    
+    set_display_item_property the_widget widget [list ../widget/pin_mux_widget.jar Altera_hps_widget]      
+    set_display_item_property the_widget widget_parameter_map $widget_parameter                                                           
+}                                                                                                           
+                                                             
+add_java_gui_parameters                    
+
+##############################################
+# Clocks!
+#
+# All clock enable parameters go here.
+# Clock frequency parameters also go here. All
+# the parameters need to be declared regardless
+# of whether the clock will be exercised.
+# 
+# Validation logic will enable/show frequency
+# parameters based on whether the actual clock
+# is being elaborated.
+#
+# There are four categories of clocks in this
+# component: inputs on SoC I/O
+#            outputs on SoC I/O
+#            inputs on FPGA pins
+#            outputs on FPGA pins              
+#
+# Inputs on SoC I/O have user-input parameters
+# so the data can be consumed by downstream
+# embedded software tools.
+# Outputs on SoC I/O need not have frequency
+# information recorded.
+# Inputs on FPGA pins have system info parameters
+# so the data can be consumed by downstream
+# embedded software tools.
+# Outputs on FPGA pins have user input parameters
+# to be consumed by Quartus via SDC.
+#
+##############################################
+proc add_clock_parameters {} {
+    set TOP_LEVEL_GROUP_NAME "Input Clocks"                     
+                                                             
+    set group_name "User Clocks"
+    add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" 
+
+    # fake group
+    set group_name "FPGA Interface Clocks"
+    add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" ""
+    
+    foreach interface {
+	f2h_axi_clock           h2f_axi_clock           h2f_lw_axi_clock
+	f2h_sdram0_clock        f2h_sdram1_clock        f2h_sdram2_clock    
+	f2h_sdram3_clock        f2h_sdram4_clock        f2h_sdram5_clock
+	h2f_cti_clock           h2f_tpiu_clock_in       h2f_debug_apb_clock
+    } {
+	set parameter "[string toupper ${interface}]_FREQ"
+	add_parameter          $parameter integer 100 ""
+	set_parameter_property $parameter display_name  "${interface} clock frequency"
+	set_parameter_property $parameter system_info_type "CLOCK_RATE"
+	set_parameter_property $parameter system_info_arg $interface
+	set_parameter_property $parameter visible false               
+	set_parameter_property $parameter group $group_name
+    }
+
+    set peripherals [list_peripheral_names]
+
+    # TODO: Remove the following for 12.0
+    set group_name "Peripheral FPGA Clocks"
+    add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" ""
+    
+    # Add parameter explicitly for cross-emac ptp since it doesn't belong to a single peripheral
+    set parameter [form_peripheral_fpga_input_clock_frequency_parameter emac_ptp_ref_clock]
+    add_parameter          $parameter integer 100 ""
+    set_parameter_property $parameter display_name  "EMAC emac_ptp_ref_clock clock frequency"
+    set_parameter_property $parameter group $group_name
+    set_parameter_property $parameter system_info_type "CLOCK_RATE"
+    set_parameter_property $parameter system_info_arg emac_ptp_ref_clock
+    set_parameter_property $parameter visible false
+    
+    foreach peripheral $peripherals {
+	set clocks [get_peripheral_fpga_input_clocks $peripheral]
+	foreach clock $clocks {
+	    set parameter [form_peripheral_fpga_input_clock_frequency_parameter $clock]
+	    add_parameter          $parameter integer 100 ""
+	    set_parameter_property $parameter display_name  "${peripheral} ${clock} clock frequency"
+	    set_parameter_property $parameter group $group_name
+	    set_parameter_property $parameter system_info_type "CLOCK_RATE"
+	    set_parameter_property $parameter system_info_arg $clock
+	    set_parameter_property $parameter visible false
+	}
+	
+	set clocks [get_peripheral_fpga_output_clocks $peripheral]
+	foreach clock $clocks {
+	    set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock]
+		if { [string match "*emac?_md*" $clock]} {
+	    	add_parameter          $parameter float 2.5 ""
+		} elseif { [string match "*emac?_gtx_clk*" $clock] } {
+            add_parameter          $parameter integer 125 ""
+		} else {
+	    	add_parameter          $parameter integer 100 ""
+            if { [string compare $peripheral "SDIO" ] == 0 } {
+	        	set_parameter_property $parameter visible false
+            }
+        }
+    	set_parameter_property $parameter display_name  "${peripheral} ${clock} clock frequency"
+    	set_parameter_property $parameter group $group_name
+    	set_parameter_property $parameter units Megahertz
+    	set_parameter_property $parameter allowedRanges {1:1000}
+		}
+
+    }
+}
+add_clock_parameters
+
+add_parameter          hps_device_family string "" ""
+set_parameter_property hps_device_family derived true
+set_parameter_property hps_device_family visible false
+
+add_parameter	        device_name string "" ""
+set_parameter_property 	device_name system_info {DEVICE}
+set_parameter_property	device_name visible false
+
+add_parameter          quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces boolean "" ""
+set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_type quartus_ini 
+set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_arg  hps_ip_enable_all_peripheral_fpga_interfaces
+set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces visible false
+
+add_parameter          quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface boolean "" ""
+set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_type quartus_ini
+set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_arg  hps_ip_enable_emac0_peripheral_fpga_interface
+set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface visible false
+
+add_parameter          quartus_ini_hps_ip_enable_test_interface boolean "" ""
+set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_type quartus_ini
+set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_arg  hps_ip_enable_test_interface
+set_parameter_property quartus_ini_hps_ip_enable_test_interface visible false
+
+add_parameter          quartus_ini_hps_ip_fast_f2sdram_sim_model boolean "" ""
+set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_type quartus_ini
+set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_arg  hps_ip_fast_f2sdram_sim_model
+set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model visible false
+
+add_parameter          quartus_ini_hps_ip_suppress_sdram_synth boolean "" ""
+set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_type quartus_ini
+set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_arg  hps_ip_suppress_sdram_synth
+set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth visible false
+
+add_parameter          quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces boolean "" ""
+set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_type quartus_ini
+set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_arg  hps_ip_enable_low_speed_serial_fpga_interfaces
+set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces visible false
+
+add_parameter          quartus_ini_hps_ip_enable_bsel_csel boolean "" ""
+set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_type quartus_ini
+set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_arg  hps_ip_enable_bsel_csel
+set_parameter_property quartus_ini_hps_ip_enable_bsel_csel visible false
+
+add_parameter          quartus_ini_hps_ip_f2sdram_bonding_out boolean "" ""
+set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_type 	quartus_ini 
+set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_arg  hps_ip_enable_f2sdram_bonding_out
+set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out visible false
+
+
+add_parameter          quartus_ini_hps_emif_pll boolean "" ""
+set_parameter_property quartus_ini_hps_emif_pll system_info_type quartus_ini 
+set_parameter_property quartus_ini_hps_emif_pll system_info_arg  hps_emif_pll
+set_parameter_property quartus_ini_hps_emif_pll visible false
+
+
+proc load_test_iface_definition {} {
+    set csv_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/test_iface.csv
+
+    set data [list]
+    set count 0
+    csv_foreach_row $csv_file cols {
+	incr count
+	if {$count == 1} {
+	    continue
+	}
+	
+	lassign_trimmed $cols port width dir
+	lappend data $port $width $dir
+    }
+    return $data
+}
+add_storage_parameter test_iface_definition [load_test_iface_definition]
+
+# order of interfaces per peripheral should be kept
+# order of ports per interface should be kept
+proc load_periph_ifaces_db {} {
+    set interfaces_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_interfaces.csv
+    set peripherals_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_atoms.csv
+    set ports_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_interface_ports.csv
+    set pins_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_port_pins.csv
+    set bfm_types_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_bfm_types.csv
+
+    # peripherals and interfaces
+    set peripherals([ORDERED_NAMES]) [list]
+    funset interface_ports
+    set count 0
+    set PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START 4
+    csv_foreach_row $interfaces_file cols {
+	incr count
+	# skip header
+	if {$count == 1} {
+	    set ordered_names [list]
+	    set length [llength $cols]
+	    for {set col $PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START} {$col < $length} {incr col} {
+		set col_value [lindex $cols $col]
+		if {$col_value != ""} {
+		    set property_to_col($col_value) $col
+		    lappend ordered_names $col_value
+		}
+	    }
+	    set property_to_col([ORDERED_NAMES]) $ordered_names
+	    continue
+	}
+	
+	set peripheral_name [string trim [lindex $cols 0]]
+	set interface_name  [string trim [lindex $cols 1]]
+	set type            [string trim [lindex $cols 2]]
+	set dir             [string trim [lindex $cols 3]]
+	
+	funset peripheral
+	if {[info exists peripherals($peripheral_name)]} {
+	    array set peripheral $peripherals($peripheral_name)
+	} else {
+	    funset interfaces
+	    set interfaces([ORDERED_NAMES]) [list]
+	    set peripheral(interfaces) [array get interfaces]
+	    set ordered_names $peripherals([ORDERED_NAMES])
+	    lappend ordered_names $peripheral_name
+	    set peripherals([ORDERED_NAMES]) $ordered_names
+	}
+	funset interfaces
+	array set interfaces $peripheral(interfaces)
+	set ordered_names $interfaces([ORDERED_NAMES])
+	lappend ordered_names $interface_name
+	set interfaces([ORDERED_NAMES]) $ordered_names
+	funset interface
+	set interface(type) $type
+	set interface(direction) $dir
+	funset properties
+	foreach property $property_to_col([ORDERED_NAMES]) {
+	    set col $property_to_col($property)
+	    set property_value [lindex $cols $col]
+
+	    if {$property_value != ""} {
+		# Add Meta Property
+		if { [string compare [string index ${property} 0] "@" ] == 0 } {
+		    set interface(${property}) ${property_value}
+		} else {                                 
+		    set properties($property) $property_value
+		}
+	    }
+	}                                                                      
+
+	set interface(properties)         [array get properties]
+                                                                      
+	set interfaces($interface_name)   [array get interface]	
+	set peripheral(interfaces)        [array get interfaces]
+	set peripherals($peripheral_name) [array get peripheral]
+	
+	funset ports
+	set ports([ORDERED_NAMES]) [list]
+	set interface_ports($interface_name) [array get ports]
+    }
+    set count 0
+    csv_foreach_row $peripherals_file cols {  ;# peripheral atom and location table
+	incr count
+	
+	# skip header
+	if {$count == 1} {
+	    continue
+	}
+	
+	set peripheral_name      [string trim [lindex $cols 0]]
+	set atom_name            [string trim [lindex $cols 1]]
+	
+	funset peripheral
+	if {[info exists peripherals($peripheral_name)]} {
+	    array set peripheral $peripherals($peripheral_name)
+	} else {
+	    # Assume that if a peripheral hasn't be recognized until now, we won't be using it
+	    continue
+	}
+	set peripheral(atom_name)           $atom_name
+	set peripherals($peripheral_name)   [array get peripheral]
+    }    
+    add_parameter          DB_periph_ifaces string [array get peripherals] ""
+    set_parameter_property DB_periph_ifaces derived true
+    set_parameter_property DB_periph_ifaces visible false
+    
+    set p [array get peripherals]
+    send_message debug "DB_periph_ifaces: ${p}"
+    
+    # ports
+    array set ports_to_pins {}
+    #    # prepopulate interface_ports with names of interfaces that are known
+    #    foreach {peripheral_name peripheral_string} [array get peripherals] {
+    #	array set peripheral_array $peripheral_string
+    #	foreach interface_name [array names peripheral_array] {
+    #	    set interface_ports($interface_name) {}
+    #	}
+    #    }
+    set count 0
+    csv_foreach_row $ports_file cols {
+	incr count
+	
+	# skip header
+	if {$count == 1} continue
+	
+	set interface_name   [string trim [lindex $cols 0]]
+	set port_name        [string trim [lindex $cols 1]]
+	set role             [string trim [lindex $cols 2]]
+	set dir              [string trim [lindex $cols 3]]
+	set atom_signal_name [string trim [lindex $cols 4]]
+
+	funset interface
+	array set interface $interface_ports($interface_name)
+	set ordered_names $interface([ORDERED_NAMES])
+	lappend ordered_names $port_name
+	set interface([ORDERED_NAMES]) $ordered_names
+	
+	funset port
+	set port(role) $role
+	set port(direction) $dir
+	set port(atom_signal_name) $atom_signal_name
+	set interface($port_name) [array get port]
+	set interface_ports($interface_name) [array get interface]
+	
+	set ports_to_pins($port_name) {}
+    }
+    add_parameter          DB_iface_ports string [array get interface_ports] ""
+    set_parameter_property DB_iface_ports derived true
+    set_parameter_property DB_iface_ports visible false
+    
+    set p [array get interface_ports]
+    send_message debug "DB_iface_ports: ${p}"
+    
+    # peripheral signals to ports
+    set count 0
+    csv_foreach_row $pins_file cols {
+	incr count
+	
+	# skip header
+	if {$count == 1} continue
+	
+	set peripheral_name [string trim [lindex $cols 0]]
+	set pin_name        [string trim [lindex $cols 1]]
+	set port_name       [string trim [lindex $cols 2]]
+	
+	set is_multibit_signal [regexp {^([a-zA-Z0-9_]+)\[([0-9]+)\]} $port_name match real_name bit]
+	if {$is_multibit_signal == 0} {
+	    set bit 0
+	} else {
+	    set port_name $real_name
+	}
+	
+	if {[info exists ports_to_pins($port_name)] == 0} {
+	    send_message error "Peripheral ${peripheral_name} signal ${pin_name} is defined but corresponding FPGA signal ${port_name}\[${bit}\] is not"
+	} else {
+	    funset port
+	    array set port $ports_to_pins($port_name)
+	    
+	    if {[info exists port($bit)]} {
+		# collision!
+		send_message error "Signal ${port_name}\[${bit}\] is having original assignment ${peripheral_name}.${port($bit)} replaced with ${peripheral_name}.${pin_name}"
+	    }
+	    set port($bit) $pin_name
+	    set ports_to_pins($port_name) [array get port]
+	}
+    }
+    add_parameter          DB_port_pins string [array get ports_to_pins] ""
+    set_parameter_property DB_port_pins derived true
+    set_parameter_property DB_port_pins visible false
+
+    set p [array get ports_to_pins]
+    send_message debug "DB_port_pins: ${p}"
+
+    # bfm types
+    set count 0
+    funset bfm_types
+    csv_foreach_row $bfm_types_file cols {
+	incr count
+	
+	# skip header
+	if {$count == 1} continue
+	
+	set bfm_type_name [string trim [lindex $cols 0]]
+	set property_name [string trim [lindex $cols 1]]
+	set value         [string trim [lindex $cols 2]]
+
+	if {[info exists bfm_types($bfm_type_name)] == 0} {
+	    set bfm_types($bfm_type_name) {}
+	}
+	funset bfm_type
+	array set bfm_type $bfm_types($bfm_type_name)
+	set bfm_type($property_name) $value
+	set bfm_types($bfm_type_name) [array get bfm_type]
+    }
+    add_parameter          DB_bfm_types string [array get bfm_types] ""
+    set_parameter_property DB_bfm_types derived true
+    set_parameter_property DB_bfm_types visible false
+    # TODO: what to do so that mode information on a peripheral.pin basis can be used for elaboration???
+}
+
+# only run during class creation
+load_periph_ifaces_db
+
+#######################
+##### Composition #####
+#######################
+
+namespace eval ::fpga_interfaces {
+    source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl
+}
+
+namespace eval ::hps_io {
+    namespace eval internal {
+	source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl
+    }
+    variable pins
+    
+    proc add_peripheral {peripheral_name atom_name location} {
+	internal::add_module_instance $peripheral_name $atom_name $location
+    }
+    
+    # oe used in tristate output and inout
+    # out used in output and inout
+    # in used in input and inout
+    proc add_pin {peripheral_name pin_name dir location in_port out_port oe_port} {
+	variable pins
+	lappend  pins [list $peripheral_name $pin_name $dir $location $in_port $out_port $oe_port]
+    }
+    
+    proc process_pins {} {
+	variable pins
+
+	set interface_name "hps_io"
+	set hps_io_interface_created 0
+	funset ports_used ;# set of inst/ports used
+	funset port_wire  ;# map of ports to aliased wires
+	foreach pin $pins { ;# Check for multiple uses of the same port and create wires for those cases
+	    lassign $pin peripheral_name pin_name dir location in_port out_port oe_port
+	    
+	    # check to see if port is used multiple times
+	    foreach port_part [list $in_port $out_port $oe_port] {
+		if {$port_part != "" && [info exists ports_used($port_part)]} {
+		    # Assume only outputs will be used multiple times. Inputs would be an error
+		    if {[info exists port_wire($port_part)] == 0} {
+			set port_wire($port_part) [internal::allocate_wire]
+			# Drive new wire with port
+			internal::set_wire_port_fragments $port_wire($port_part) driven_by $port_part
+		    }
+		}
+		set ports_used($port_part) 1
+	    }
+	}
+	
+	set qip [list]
+	foreach pin $pins {
+	    lassign $pin peripheral_name pin_name dir location in_port out_port oe_port
+	    foreach port_part_ref {in_port out_port oe_port} { ;# Replace ports with wires if needed
+		set port_part [set $port_part_ref]
+		if {[info exists port_wire($port_part)]} {
+		    set $port_part_ref [internal::wire_tofragment $port_wire($port_part)]
+		}
+	    }
+
+	    # Hook things up
+	    set instance_name [string tolower $peripheral_name] ;# is this necessary???
+	    if {$hps_io_interface_created == 0} {
+		set hps_io_interface_created 1
+		internal::add_interface $interface_name conduit input
+	    }
+	    set export_signal_name "hps_io_${instance_name}_${pin_name}"
+	    internal::add_interface_port $interface_name $export_signal_name $export_signal_name $dir 1
+	    if {[string compare $dir "input"] == 0} {
+			internal::set_port_fragments $interface_name $export_signal_name $in_port
+			internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *"
+	    } elseif {[string compare $dir "output"] == 0} {
+		if {[string compare $oe_port "" ] == 0} {
+			internal::set_port_fragments $interface_name $export_signal_name $out_port
+			internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]"
+		} else {
+			internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port
+			internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]"
+		}
+	    } else {
+			internal::set_port_fragments $interface_name $export_signal_name $in_port
+			internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port
+			internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *"
+			internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]"
+	    }
+	    set path_to_pin "hps_io|border|${export_signal_name}\[0\]"
+	    set location_assignment "set_instance_assignment -name HPS_LOCATION ${location} -entity %entityName% -to ${path_to_pin}"
+	    lappend qip $location_assignment
+	}
+	set_qip_strings $qip
+    }
+    
+    proc init {} {
+	internal::init
+	variable pins [list]
+    }
+    
+    proc serialize {var_name} {
+	upvar 1 $var_name data
+	process_pins
+	internal::serialize data
+    }
+}
+
+set_module_property composition_callback compose
+
+proc compose {} {
+    # synchronize device families between the EMIF and HPS parameter sets
+    set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY]
+    fpga_interfaces::init
+    fpga_interfaces::set_bfm_types [array get DB_bfm_types]
+    
+    hps_io::init
+    validate
+    elab 0
+
+    update_hps_to_fpga_clock_frequency_parameters
+
+
+    fpga_interfaces::serialize fpga_interfaces_data
+
+    add_instance fpga_interfaces altera_interface_generator
+    set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data]
+    
+    expose_border fpga_interfaces $fpga_interfaces_data(interfaces)
+
+    declare_cmsis_svd $fpga_interfaces_data(interfaces)
+
+    clear_array temp_array
+}
+
+proc logicalview_dtg {} {
+
+    set hard_peripheral_logical_view_dir $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/hard_peripheral_logical_view
+
+    source "$hard_peripheral_logical_view_dir/common/hps_utils.tcl"
+
+    source "$hard_peripheral_logical_view_dir/hps_periphs/hps_periphs.tcl"
+
+    set f2h_present [ expr [ get_parameter_value F2S_Width ] != 0]
+    set h2f_present [ expr [ get_parameter_value S2F_Width ] != 0]
+    set F2S_Width [ get_parameter_value F2S_Width ]
+    set S2F_Width [ get_parameter_value S2F_Width ]
+    set h2f_lw_present [ expr [ string compare [ get_parameter_value LWH2F_Enable ] "true" ] == 0 ]
+    set LWH2F_Enable [ get_parameter_value LWH2F_Enable ]
+    set device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY]
+
+    # Need to add whole bunch of device tree generation parameters here (dtg)
+    # Getting whether is it single or dual core by checking the device family. List of single core:
+    # Cyclone V SE                                                                          
+    regsub "^.* V" $device_family "" se_family
+    regsub " " $se_family "" se_family
+   
+    set number_of_a9 0
+    if { [string toupper $se_family] == "SE"} {
+        set number_of_a9 1
+    } else {
+        set number_of_a9 2                                                                  
+    }
+
+    set F2SDRAM_Width [get_parameter_value F2SDRAM_Width]
+    set F2SDRAM_Type [get_parameter_value F2SDRAM_Type]
+    set quartus_ini_hps_ip_f2sdram_bonding_out  [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out]
+    set BONDING_OUT_ENABLED [get_parameter_value BONDING_OUT_ENABLED]
+    add_instance clk_0 hps_clk_src
+    hps_utils_add_instance_clk_reset clk_0 bridges hps_bridge_avalon
+    set_instance_parameter_value bridges F2S_Width $F2S_Width
+    set_instance_parameter_value bridges S2F_Width $S2F_Width
+    set_instance_parameter_value bridges BONDING_OUT_ENABLED $BONDING_OUT_ENABLED
+    set_instance_parameter_value bridges LWH2F_Enable $LWH2F_Enable
+    set_instance_parameter_value bridges quartus_ini_hps_ip_f2sdram_bonding_out $quartus_ini_hps_ip_f2sdram_bonding_out 
+    add_interface h2f_reset reset output
+    set_interface_property h2f_reset EXPORT_OF bridges.h2f_reset
+    set_interface_property h2f_reset PORT_NAME_MAP "h2f_rst_n h2f_rst_n"
+
+    set rows [llength $F2SDRAM_Width]
+    set type_list $F2SDRAM_Type  
+    set append_type_list ""
+    set append_type_width ""
+    set total_command_port 0
+    set total_write_port 0
+    set total_read_port 0
+    if {$rows > 0} {
+        for {set i 0} {${i} < $rows} {incr i} {           
+            set type_choice  [lindex $type_list  $i]
+            set type_width  [lindex $F2SDRAM_Width  $i]
+            if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } {
+                set type_id 1
+                set total_command_port [expr $total_command_port + 1]
+                if {$type_width == 128} {
+                    set total_write_port [expr $total_write_port + 2]
+                    set total_read_port [expr $total_read_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_write_port [expr $total_write_port + 4]
+                    set total_read_port [expr $total_read_port + 4]
+                } else {
+                    set total_write_port [expr $total_write_port + 1]
+                    set total_read_port [expr $total_read_port + 1]
+                }
+            } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } {
+                set type_id 2
+                set total_command_port [expr $total_command_port + 1]
+                if {$type_width == 128} {
+                    set total_write_port [expr $total_write_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_write_port [expr $total_write_port + 4]
+                } else {
+                    set total_write_port [expr $total_write_port + 1]
+                }
+            } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } {    
+                set type_id 3
+                set total_command_port [expr $total_command_port + 1]
+                if {$type_width == 128} {
+                    set total_read_port [expr $total_read_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_read_port [expr $total_read_port + 4]
+                } else {
+                    set total_read_port [expr $total_read_port + 1]
+                }         
+            } else {
+                set type_id 0
+                if { [ expr $total_command_port % 2 ] } {
+                    incr total_command_port 1
+                }
+                set total_command_port [expr $total_command_port + 2]
+                if {$type_width == 128} {
+                    set total_write_port [expr $total_write_port + 2]
+                    set total_read_port [expr $total_read_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_write_port [expr $total_write_port + 4]
+                    set total_read_port [expr $total_read_port + 4]
+                } else {
+                    set total_write_port [expr $total_write_port + 1]
+                    set total_read_port [expr $total_read_port + 1]
+                }
+            }
+            
+            if {$total_command_port > 6} {
+                if {$type_id == 0} {
+                    send_message error "No command ports available to allocate AXI Interface f2h_sdram${i}"
+                } else {
+                    send_message error "No command ports available to allocate Avalon-MM Interface f2h_sdram${i}"    
+                }
+            }
+            if {$total_read_port > 4} {
+                if {$type_id == 0} {
+                    send_message error "No read ports available to allocate AXI Interface f2h_sdram${i}"
+                } else {
+                    send_message error "No read ports available to allocate Avalon-MM Interface f2h_sdram${i}"    
+                }
+            }
+            if {$total_write_port > 4} {
+                if {$type_id == 0} {
+                    send_message error "No write ports available to allocate AXI Interface f2h_sdram${i}"
+                } else {
+                    send_message error "No write ports available to allocate Avalon-MM Interface f2h_sdram${i}"    
+                }
+            }
+            if {$total_command_port < 7 && $total_write_port < 5 && $total_read_port < 5} {
+                lappend append_type_list $type_id
+                lappend append_type_width $type_width
+            }
+        }
+    }
+    set_instance_parameter_value bridges F2SDRAM_Type $append_type_list
+    set_instance_parameter_value bridges F2SDRAM_Width $append_type_width
+    set total_command_port 0
+    set total_write_port 0
+    set total_read_port 0
+    set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}]
+
+    if {$rows > 0} {
+        for {set i 0} {${i} < $rows} {incr i} {           
+           
+            set type_choice  [lindex $type_list  $i]
+            set type_width  [lindex $F2SDRAM_Width  $i]
+
+            if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } {
+                set type "avalon"
+                set total_command_port [expr $total_command_port + 1]
+                if {$type_width == 128} {
+                    set total_write_port [expr $total_write_port + 2]
+                    set total_read_port [expr $total_read_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_write_port [expr $total_write_port + 4]
+                    set total_read_port [expr $total_read_port + 4]
+                } else {
+                    set total_write_port [expr $total_write_port + 1]
+                    set total_read_port [expr $total_read_port + 1]
+                }
+                set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE"
+            } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } {
+                set type "avalon"
+                set total_command_port [expr $total_command_port + 1]
+                if {$type_width == 128} {
+                    set total_write_port [expr $total_write_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_write_port [expr $total_write_port + 4]
+                } else {
+                    set total_write_port [expr $total_write_port + 1]
+                }
+                set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE"
+            } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } {    
+                set type "avalon"                  
+                set total_command_port [expr $total_command_port + 1]
+                if {$type_width == 128} {
+                    set total_read_port [expr $total_read_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_read_port [expr $total_read_port + 4]
+                } else {
+                    set total_read_port [expr $total_read_port + 1]
+                }
+                set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ"
+            } else {
+                set type "axi"
+                if { [ expr $total_command_port % 2 ] } {
+                    incr total_command_port 1
+                }
+                set total_command_port [expr $total_command_port + 2]
+                if {$type_width == 128} {
+                    set total_write_port [expr $total_write_port + 2]
+                    set total_read_port [expr $total_read_port + 2]
+                } elseif {$type_width == 256 } {
+                    set total_write_port [expr $total_write_port + 4]
+                    set total_read_port [expr $total_read_port + 4]
+                } else {
+                    set total_write_port [expr $total_write_port + 1]
+                    set total_read_port [expr $total_read_port + 1]
+                }
+                set sdram_data "f2h_sdram${i}_ARADDR f2h_sdram${i}_ARADDR   f2h_sdram${i}_ARLEN f2h_sdram${i}_ARLEN f2h_sdram${i}_ARID f2h_sdram${i}_ARID f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARBURST f2h_sdram${i}_ARBURST f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARPROT f2h_sdram${i}_ARPROT f2h_sdram${i}_ARVALID f2h_sdram${i}_ARVALID f2h_sdram${i}_ARCACHE f2h_sdram${i}_ARCACHE f2h_sdram${i}_AWADDR f2h_sdram${i}_AWADDR f2h_sdram${i}_AWLEN f2h_sdram${i}_AWLEN f2h_sdram${i}_AWID f2h_sdram${i}_AWID f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWBURST f2h_sdram${i}_AWBURST f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWPROT f2h_sdram${i}_AWPROT f2h_sdram${i}_AWVALID f2h_sdram${i}_AWVALID f2h_sdram${i}_AWCACHE f2h_sdram${i}_AWCACHE f2h_sdram${i}_BRESP f2h_sdram${i}_BRESP f2h_sdram${i}_BID f2h_sdram${i}_BID f2h_sdram${i}_BVALID f2h_sdram${i}_BVALID f2h_sdram${i}_BREADY f2h_sdram${i}_BREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RDATA f2h_sdram${i}_RDATA f2h_sdram${i}_RRESP f2h_sdram${i}_RRESP f2h_sdram${i}_RLAST f2h_sdram${i}_RLAST f2h_sdram${i}_RID f2h_sdram${i}_RID f2h_sdram${i}_RVALID f2h_sdram${i}_RVALID f2h_sdram${i}_WLAST f2h_sdram${i}_WLAST f2h_sdram${i}_WVALID f2h_sdram${i}_WVALID f2h_sdram${i}_WDATA f2h_sdram${i}_WDATA f2h_sdram${i}_WSTRB f2h_sdram${i}_WSTRB f2h_sdram${i}_WREADY f2h_sdram${i}_WREADY f2h_sdram${i}_WID f2h_sdram${i}_WID"
+            }
+
+            if {$total_command_port > 6 || $total_write_port > 4 || $total_read_port > 4} {
+                break
+            }
+            add_interface f2h_sdram${i}_clock clock Input
+            set_interface_property f2h_sdram${i}_clock EXPORT_OF bridges.f2h_sdram${i}_clock
+            set_interface_property f2h_sdram${i}_clock PORT_NAME_MAP "f2h_sdram${i}_clk f2h_sdram${i}_clk"
+            add_interface f2h_sdram${i}_data $type slave
+            set_interface_property f2h_sdram${i}_data EXPORT_OF bridges.f2h_sdram${i}_data
+            set_interface_property f2h_sdram${i}_data PORT_NAME_MAP "$sdram_data"	    
+        }
+
+	if $bonding_out_signal {
+	    set bon_out_signal "f2h_sdram_BONOUT_1 f2h_sdram_BONOUT_1 	  f2h_sdram_BONOUT_2 f2h_sdram_BONOUT_2" 	
+	    add_interface f2h_sdram_bon_out conduit Output
+	    set_interface_property f2h_sdram_bon_out EXPORT_OF bridges.f2h_sdram_bon_out
+            set_interface_property f2h_sdram_bon_out PORT_NAME_MAP "$bon_out_signal"
+   	}
+
+    }
+
+    set declared_svd_file 0
+    set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd]
+    if { $h2f_present } {
+        hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f {0xc0000000}
+        if { $number_of_a9 > 1 } {
+            hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f {0xc0000000}
+        }
+        
+        add_interface h2f_axi_clock clock Input
+        set_interface_property h2f_axi_clock EXPORT_OF bridges.h2f_axi_clock
+        set_interface_property h2f_axi_clock PORT_NAME_MAP "h2f_axi_clk h2f_axi_clk"
+        
+        add_interface h2f_axi_master axi master
+        set_interface_property h2f_axi_master EXPORT_OF bridges.h2f
+        set_interface_property h2f_axi_master PORT_NAME_MAP "h2f_AWID h2f_AWID h2f_AWADDR h2f_AWADDR h2f_AWLEN h2f_AWLEN h2f_AWSIZE h2f_AWSIZE h2f_AWBURST h2f_AWBURST h2f_AWLOCK h2f_AWLOCK h2f_AWCACHE h2f_AWCACHE h2f_AWPROT h2f_AWPROT h2f_AWVALID h2f_AWVALID h2f_AWREADY h2f_AWREADY h2f_WID h2f_WID h2f_WDATA h2f_WDATA h2f_WSTRB h2f_WSTRB h2f_WLAST h2f_WLAST h2f_WVALID h2f_WVALID h2f_WREADY h2f_WREADY h2f_BID h2f_BID h2f_BRESP h2f_BRESP h2f_BVALID h2f_BVALID h2f_BREADY h2f_BREADY h2f_ARID h2f_ARID h2f_ARADDR h2f_ARADDR h2f_ARLEN h2f_ARLEN h2f_ARSIZE h2f_ARSIZE h2f_ARBURST h2f_ARBURST h2f_ARLOCK h2f_ARLOCK h2f_ARCACHE h2f_ARCACHE h2f_ARPROT h2f_ARPROT h2f_ARVALID h2f_ARVALID h2f_ARREADY h2f_ARREADY h2f_RID h2f_RID h2f_RDATA h2f_RDATA h2f_RRESP h2f_RRESP h2f_RLAST h2f_RLAST h2f_RVALID h2f_RVALID h2f_RREADY h2f_RREADY"
+        set_interface_property h2f_axi_master SVD_ADDRESS_GROUP  "hps"
+        set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000
+        if {!$declared_svd_file} {
+            set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path
+            set declared_svd_file 1
+        }
+    }
+    
+    if { $f2h_present } {
+        add_interface f2h_axi_clock clock Input
+        set_interface_property f2h_axi_clock EXPORT_OF bridges.f2h_axi_clock
+        set_interface_property f2h_axi_clock PORT_NAME_MAP "f2h_axi_clk f2h_axi_clk"
+        
+        add_interface f2h_axi_slave axi slave
+        set_interface_property f2h_axi_slave EXPORT_OF bridges.f2h
+        set_interface_property f2h_axi_slave PORT_NAME_MAP "f2h_AWID f2h_AWID f2h_AWADDR f2h_AWADDR f2h_AWLEN f2h_AWLEN f2h_AWSIZE f2h_AWSIZE f2h_AWBURST f2h_AWBURST f2h_AWLOCK f2h_AWLOCK f2h_AWCACHE f2h_AWCACHE f2h_AWPROT f2h_AWPROT f2h_AWVALID f2h_AWVALID f2h_AWREADY f2h_AWREADY f2h_AWUSER f2h_AWUSER f2h_WID f2h_WID f2h_WDATA f2h_WDATA f2h_WSTRB f2h_WSTRB f2h_WLAST f2h_WLAST f2h_WVALID f2h_WVALID f2h_WREADY f2h_WREADY f2h_BID f2h_BID f2h_BRESP f2h_BRESP f2h_BVALID f2h_BVALID f2h_BREADY f2h_BREADY f2h_ARID f2h_ARID f2h_ARADDR f2h_ARADDR f2h_ARLEN f2h_ARLEN f2h_ARSIZE f2h_ARSIZE f2h_ARBURST f2h_ARBURST f2h_ARLOCK f2h_ARLOCK f2h_ARCACHE f2h_ARCACHE f2h_ARPROT f2h_ARPROT f2h_ARVALID f2h_ARVALID f2h_ARREADY f2h_ARREADY f2h_ARUSER f2h_ARUSER f2h_RID f2h_RID f2h_RDATA f2h_RDATA f2h_RRESP f2h_RRESP f2h_RLAST f2h_RLAST f2h_RVALID f2h_RVALID f2h_RREADY f2h_RREADY"
+    }
+    
+    if { $h2f_lw_present } {
+        hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f_lw {0xff200000}
+        if { $number_of_a9 > 1 } {
+            hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f_lw {0xff200000}
+        }
+        
+        add_interface h2f_lw_axi_clock clock Input
+        set_interface_property h2f_lw_axi_clock EXPORT_OF bridges.h2f_lw_axi_clock
+        set_interface_property h2f_lw_axi_clock PORT_NAME_MAP "h2f_lw_axi_clk h2f_lw_axi_clk"
+        
+        add_interface h2f_lw_axi_master axi start
+        set_interface_property h2f_lw_axi_master EXPORT_OF bridges.h2f_lw
+        set_interface_property h2f_lw_axi_master PORT_NAME_MAP "h2f_lw_AWID h2f_lw_AWID h2f_lw_AWADDR h2f_lw_AWADDR h2f_lw_AWLEN h2f_lw_AWLEN h2f_lw_AWSIZE h2f_lw_AWSIZE h2f_lw_AWBURST h2f_lw_AWBURST h2f_lw_AWLOCK h2f_lw_AWLOCK h2f_lw_AWCACHE h2f_lw_AWCACHE h2f_lw_AWPROT h2f_lw_AWPROT h2f_lw_AWVALID h2f_lw_AWVALID h2f_lw_AWREADY h2f_lw_AWREADY h2f_lw_WID h2f_lw_WID h2f_lw_WDATA h2f_lw_WDATA h2f_lw_WSTRB h2f_lw_WSTRB h2f_lw_WLAST h2f_lw_WLAST h2f_lw_WVALID h2f_lw_WVALID h2f_lw_WREADY h2f_lw_WREADY h2f_lw_BID h2f_lw_BID h2f_lw_BRESP h2f_lw_BRESP h2f_lw_BVALID h2f_lw_BVALID h2f_lw_BREADY h2f_lw_BREADY h2f_lw_ARID h2f_lw_ARID h2f_lw_ARADDR h2f_lw_ARADDR h2f_lw_ARLEN h2f_lw_ARLEN h2f_lw_ARSIZE h2f_lw_ARSIZE h2f_lw_ARBURST h2f_lw_ARBURST h2f_lw_ARLOCK h2f_lw_ARLOCK h2f_lw_ARCACHE h2f_lw_ARCACHE h2f_lw_ARPROT h2f_lw_ARPROT h2f_lw_ARVALID h2f_lw_ARVALID h2f_lw_ARREADY h2f_lw_ARREADY h2f_lw_RID h2f_lw_RID h2f_lw_RDATA h2f_lw_RDATA h2f_lw_RRESP h2f_lw_RRESP h2f_lw_RLAST h2f_lw_RLAST h2f_lw_RVALID h2f_lw_RVALID h2f_lw_RREADY h2f_lw_RREADY"
+        set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP  "hps"
+        set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000
+        if {!$declared_svd_file} {
+            set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path
+            set declared_svd_file 1
+        }
+    }
+
+    if {!$declared_svd_file} {
+        set_module_assignment "cmsis.svd.file"   $svd_path
+        set_module_assignment "cmsis.svd.suffix" "hps"
+    }
+
+    clocks_logicalview_dtg
+    
+    if { $number_of_a9 > 0 } {
+        hps_utils_add_instance_clk_reset clk_0 arm_a9_0 arm_a9
+    }
+    
+    if { $number_of_a9 > 1 } {
+        hps_utils_add_instance_clk_reset clk_0 arm_a9_1 arm_a9
+    }
+    
+
+    hps_instantiate_arm_gic_0 $number_of_a9
+    
+    hps_instantiate_L2 $number_of_a9
+    
+    hps_instantiate_dma $number_of_a9
+    
+    hps_instantiate_sysmgr $number_of_a9
+    
+    hps_instantiate_clkmgr $number_of_a9
+
+    hps_instantiate_rstmgr $number_of_a9
+    
+    hps_instantiate_fpgamgr $number_of_a9
+    
+    hps_instantiate_uart0 $number_of_a9 "UART0_PinMuxing" [get_parameter_value l4_sp_clk_mhz]
+    
+    hps_instantiate_uart1 $number_of_a9 "UART1_PinMuxing" [get_parameter_value l4_sp_clk_mhz]
+    
+    hps_instantiate_timer0 $number_of_a9
+    
+    hps_instantiate_timer1 $number_of_a9
+    
+    hps_instantiate_timer2 $number_of_a9
+    
+    hps_instantiate_timer3 $number_of_a9
+    
+    hps_instantiate_wd_timer0 $number_of_a9
+    
+    hps_instantiate_wd_timer1 $number_of_a9
+    
+    hps_instantiate_gpio0 $number_of_a9
+    
+    hps_instantiate_gpio1 $number_of_a9
+    
+    hps_instantiate_gpio2 $number_of_a9
+    
+    hps_instantiate_i2c0 $number_of_a9 "I2C0_PinMuxing"
+    
+    hps_instantiate_i2c1 $number_of_a9 "I2C1_PinMuxing"
+    
+    hps_instantiate_i2c2 $number_of_a9 "I2C2_PinMuxing"
+    
+    hps_instantiate_i2c3 $number_of_a9 "I2C3_PinMuxing"
+    
+    hps_instantiate_nand0 $number_of_a9 "NAND_PinMuxing"
+    
+    hps_instantiate_spim0 $number_of_a9 "SPIM0_PinMuxing"
+    
+    hps_instantiate_spim1 $number_of_a9 "SPIM1_PinMuxing"
+    
+    hps_instantiate_qspi $number_of_a9 "QSPI_PinMuxing"
+    
+    hps_instantiate_sdmmc $number_of_a9 "SDIO_PinMuxing"
+    
+    hps_instantiate_usb0 $number_of_a9 "USB0_PinMuxing"
+    
+    hps_instantiate_usb1 $number_of_a9 "USB1_PinMuxing"
+    
+    hps_instantiate_gmac0 $number_of_a9 "EMAC0_PinMuxing"
+    
+    hps_instantiate_gmac1 $number_of_a9 "EMAC1_PinMuxing"
+
+    hps_instantiate_dcan0 $number_of_a9 "CAN0_PinMuxing"
+    
+    hps_instantiate_dcan1 $number_of_a9 "CAN1_PinMuxing"
+
+    hps_instantiate_l3regs $number_of_a9
+
+    hps_instantiate_sdrctl $number_of_a9
+
+    hps_instantiate_axi_ocram $number_of_a9
+
+    hps_instantiate_axi_sdram $number_of_a9
+    
+    hps_instantiate_timer $number_of_a9
+
+    hps_instantiate_scu $number_of_a9
+    
+    add_connection arm_gic_0.arm_gic_ppi timer.interrupt_sender
+    set_connection_parameter_value arm_gic_0.arm_gic_ppi/timer.interrupt_sender irqNumber 13
+    
+    if { $f2h_present } {
+        hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave0 {0xfffed000}
+        hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave1 {0xfffec100}
+        hps_utils_add_slave_interface bridges.axi_f2h L2.axi_slave0 {0xfffef000}
+        hps_utils_add_slave_interface bridges.axi_f2h dma.axi_slave0 {0xffe01000}
+        hps_utils_add_slave_interface bridges.axi_f2h sysmgr.axi_slave0 {0xffd08000}
+        hps_utils_add_slave_interface bridges.axi_f2h clkmgr.axi_slave0 {0xffd04000}
+        hps_utils_add_slave_interface bridges.axi_f2h rstmgr.axi_slave0 {0xffd05000}
+        hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave0 {0xff706000}
+        hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave1 {0xffb90000}
+        hps_utils_add_slave_interface bridges.axi_f2h uart0.axi_slave0 {0xffc02000}
+        hps_utils_add_slave_interface bridges.axi_f2h uart1.axi_slave0 {0xffc03000}
+        hps_utils_add_slave_interface bridges.axi_f2h timer0.axi_slave0 {0xffc08000}
+        hps_utils_add_slave_interface bridges.axi_f2h timer1.axi_slave0 {0xffc09000}
+        hps_utils_add_slave_interface bridges.axi_f2h timer2.axi_slave0 [hps_timer2_base]
+        hps_utils_add_slave_interface bridges.axi_f2h timer3.axi_slave0 [hps_timer3_base]
+        hps_utils_add_slave_interface bridges.axi_f2h gpio0.axi_slave0 {0xff708000}
+        hps_utils_add_slave_interface bridges.axi_f2h gpio1.axi_slave0 {0xff709000}
+        hps_utils_add_slave_interface bridges.axi_f2h gpio2.axi_slave0 {0xff70a000}
+        hps_utils_add_slave_interface bridges.axi_f2h i2c0.axi_slave0 {0xffc04000}
+        hps_utils_add_slave_interface bridges.axi_f2h i2c1.axi_slave0 {0xffc05000}
+        hps_utils_add_slave_interface bridges.axi_f2h i2c2.axi_slave0 {0xffc06000}
+        hps_utils_add_slave_interface bridges.axi_f2h i2c3.axi_slave0 {0xffc07000}
+        hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave0 {0xff900000}
+        hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave1 {0xffb80000}
+        hps_utils_add_slave_interface bridges.axi_f2h spim0.axi_slave0 [hps_spim0_base]
+        hps_utils_add_slave_interface bridges.axi_f2h spim1.axi_slave0 [hps_spim1_base]
+        hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave0 {0xff705000}
+        hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave1 {0xffa00000}
+        hps_utils_add_slave_interface bridges.axi_f2h sdmmc.axi_slave0 {0xff704000}
+        hps_utils_add_slave_interface bridges.axi_f2h usb0.axi_slave0 {0xffb00000}
+        hps_utils_add_slave_interface bridges.axi_f2h usb1.axi_slave0 {0xffb40000}
+        hps_utils_add_slave_interface bridges.axi_f2h gmac0.axi_slave0 {0xff700000}
+        hps_utils_add_slave_interface bridges.axi_f2h gmac1.axi_slave0 {0xff702000}
+        hps_utils_add_slave_interface bridges.axi_f2h axi_ocram.axi_slave0 {0xffff0000}
+        hps_utils_add_slave_interface bridges.axi_f2h axi_sdram.axi_slave0 [hps_sdram_base]
+        hps_utils_add_slave_interface bridges.axi_f2h timer.axi_slave0 {0xfffec600}
+        hps_utils_add_slave_interface bridges.axi_f2h dcan0.axi_slave0 [hps_dcan0_base]
+        hps_utils_add_slave_interface bridges.axi_f2h dcan1.axi_slave0 [hps_dcan1_base]
+        hps_utils_add_slave_interface bridges.axi_f2h l3regs.axi_slave0 [hps_l3regs_base]
+        hps_utils_add_slave_interface bridges.axi_f2h sdrctl.axi_slave0 [hps_sdrctl_base]
+    }
+
+    ##### F2H #####
+    if [is_enabled F2SINTERRUPT_Enable] {
+	set any_interrupt_enabled 1
+	set iname "f2h_irq"
+	set pname "f2h_irq"
+	    add_interface      "${iname}0"  interrupt receiver
+	    set_interface_property f2h_irq0 EXPORT_OF arm_gic_0.f2h_irq_0_irq_rx_offset_40
+	    set_interface_property f2h_irq0 PORT_NAME_MAP "f2h_irq_p0 irq_siq_40"
+
+	    add_interface      "${iname}1"  interrupt receiver
+	    set_interface_property f2h_irq1 EXPORT_OF arm_gic_0.f2h_irq_32_irq_rx_offset_72
+	    set_interface_property f2h_irq1 PORT_NAME_MAP "f2h_irq_p1 irq_siq_72"
+    }
+}
+
+set_module_property OPAQUE_ADDRESS_MAP false
+set_module_property STRUCTURAL_COMPOSITION_CALLBACK compose_logicalview
+proc compose_logicalview {} {
+    # synchronize device families between the EMIF and HPS parameter sets
+    set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY]
+    fpga_interfaces::init
+    fpga_interfaces::set_bfm_types [array get DB_bfm_types]
+    
+    hps_io::init
+    validate
+    elab 1
+
+    update_hps_to_fpga_clock_frequency_parameters
+
+
+    fpga_interfaces::serialize fpga_interfaces_data
+
+    add_instance fpga_interfaces altera_interface_generator
+    set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data]
+    
+    expose_border fpga_interfaces $fpga_interfaces_data(interfaces)
+
+    #declare_cmsis_svd $fpga_interfaces_data(interfaces)
+
+    logicalview_dtg
+}
+
+proc declare_cmsis_svd {interfaces_str} {
+    array set interfaces $interfaces_str
+    set interface_names $interfaces([ORDERED_NAMES])
+    
+    set h2f_exists   0
+    set lwh2f_exists 0
+    foreach interface_name $interface_names {
+	if {[string compare $interface_name "h2f_axi_master"] == 0} {
+	    set h2f_exists   1
+	} elseif {[string compare $interface_name "h2f_lw_axi_master"] == 0} {
+	    set lwh2f_exists 1
+	}
+    }
+    
+    set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd]
+    set address_group hps
+    set declared_svd_file 0
+
+    if {$h2f_exists} {
+	if {!$declared_svd_file} {
+	    set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path
+	    set declared_svd_file 1
+	}
+	set_interface_property h2f_axi_master SVD_ADDRESS_GROUP  $address_group
+	set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000
+    }
+    if {$lwh2f_exists} {
+	if {!$declared_svd_file} {
+	    set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path
+	    set declared_svd_file 1
+	}
+	set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP  $address_group
+	set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000
+    }
+    if {!$declared_svd_file} {
+	set_module_assignment "cmsis.svd.file"   $svd_path
+	set_module_assignment "cmsis.svd.suffix" $address_group
+    }
+}
+
+
+######################
+##### Validation #####
+######################
+
+proc validate {} {
+    set device_family [get_parameter_value hps_device_family]
+    set device [get_device]
+    ensure_pin_muxing_data $device_family
+    update_table_derived_parameters
+
+    validate_F2SDRAM
+    update_S2F_CLK_mux_options
+    update_pin_muxing_ui $device_family 
+
+    # funset placement_by_pin
+    validate_pin_muxing $device_family placement_by_pin
+    update_gpio_ui placement_by_pin
+
+    validate_TEST
+
+    validate_interrupt $device_family
+    
+    validate_clocks
+
+}
+
+proc validate_TEST {} {
+    set ini [get_parameter_value quartus_ini_hps_ip_enable_test_interface]
+    set_parameter_property TEST_Enable visible $ini
+}
+
+proc hide_param { paramName hide} {
+
+}
+proc update_hps_to_fpga_clock_frequency_parameters {} {
+    set u0 [get_parameter_value S2FCLK_USER0CLK_Enable]
+    set u1 [get_parameter_value S2FCLK_USER1CLK_Enable]
+    #set u2 [get_parameter_value S2FCLK_USER2CLK_Enable]
+
+    for { set i 0 } { $i < 2 } { incr i } {
+	set_parameter_property "S2FCLK_USER${i}CLK_FREQ" enabled [expr "\$u${i}"]
+
+	if { [string compare true [expr "\$u${i}"] ] == 0 } {
+	    fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRateKnown true
+	    fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRate [expr [get_parameter_value "S2FCLK_USER${i}CLK_FREQ"] * 1000000 ]
+	}
+    }
+}
+
+proc update_table_derived_parameters {} {
+    update_f2sdram_names
+    update_dma_peripheral_ids
+}
+
+proc update_f2sdram_names {} {
+    set num_rows [llength [get_parameter_value F2SDRAM_Width]]
+    set names [list]
+    
+    for {set index 0} {$index < $num_rows} {incr index} {
+	set name "f2h_sdram${index}"
+	lappend names $name
+    }
+    set_parameter_value F2SDRAM_Name_DERIVED ${names}
+}
+
+proc update_dma_peripheral_ids {} {
+    set periph_id_list {0 1 2 3 4 5 6 7}
+    set_parameter_value DMA_PeriphId_DERIVED $periph_id_list
+}
+
+proc is_enabled {parameter} {
+    if { [string compare [get_parameter_value $parameter] "true" ] == 0 } {
+	return 1
+    } else {
+	return 0
+    }
+}
+
+proc validate_F2SDRAM {} {
+    set type_list  [get_parameter_value F2SDRAM_Type]
+    set width_list [get_parameter_value F2SDRAM_Width]
+    set rows [llength $width_list]
+
+    set command_ports_bit 0
+    set read_ports_bit    0
+    set write_ports_bit   0
+
+    set command_ports_mask 0
+    set read_ports_mask    0
+    set write_ports_mask   0
+    set reset_ports_mask   0
+    
+    for {set index 0} {${index} < ${rows}} {incr index} {
+	# check for invalid combinations of type/width
+	set mytype  [lindex $type_list  $index]
+	set mywidth [lindex $width_list $index]
+	
+	if {$mywidth < 64} {
+	    send_message warning "Setting the slave port width of interface <b>f2h_sdram${index}</b> to ${mywidth} results in bandwidth under-utilization.  Altera recommends you set the interface data width to 64-bit or greater."
+	}
+
+	# count used ports
+	# command
+	if { [string compare $mytype [F2HSDRAM_AXI3]] == 0 } {
+	    if { [ expr $command_ports_bit % 2 ] } {
+	        incr command_ports_bit 1
+	    }
+	    set command_ports_mask [ expr $command_ports_mask | ( 3 << $command_ports_bit) ]
+	    incr command_ports_bit 2
+	} else {
+	    set command_ports_mask [ expr $command_ports_mask | ( 1 << $command_ports_bit) ]
+	    incr command_ports_bit 1
+	}
+	
+	# read
+	if {$mytype != [F2HSDRAM_AVM_WRITEONLY]} {
+	    if {$mywidth <= 64} {
+	    set read_ports_mask [ expr $read_ports_mask | ( 1 << $read_ports_bit) ]
+		incr read_ports_bit 1
+	    } elseif {$mywidth == 128} {
+	    set read_ports_mask [ expr $read_ports_mask | ( 3 << $read_ports_bit) ]
+		incr read_ports_bit 2
+	    } else {
+	    set read_ports_mask [ expr $read_ports_mask | ( 15 << $read_ports_bit) ]
+		incr read_ports_bit 4
+	    }
+	}
+
+	# write
+	if {$mytype != [F2HSDRAM_AVM_READONLY]} {
+	    if {$mywidth <= 64} {
+	    set write_ports_mask [ expr $write_ports_mask | ( 1 << $write_ports_bit) ]
+		incr write_ports_bit 1
+	    } elseif {$mywidth == 128} {
+	    set write_ports_mask [ expr $write_ports_mask | ( 3 << $write_ports_bit) ]
+		incr write_ports_bit 2
+	    } else {
+	    set write_ports_mask [ expr $write_ports_mask | ( 15 << $write_ports_bit) ]
+		incr write_ports_bit 4
+	    }
+	}
+	
+	# reset
+	set reset_ports_mask [ expr ($command_ports_mask << 8) | ($write_ports_mask << 4) | ($read_ports_mask) ]
+	
+    }
+    # check for port over-use
+    if {$command_ports_bit > 6} {
+	send_message error "The current FPGA to SDRAM configuration is using more command ports than are available."
+    }
+    if {$read_ports_bit > 4} {
+	send_message error "The current FPGA to SDRAM configuration is using more read ports than are available."
+    }
+    if {$write_ports_bit > 4} {
+	send_message error "The current FPGA to SDRAM configuration is using more write ports than are available."
+    }
+
+    # Store ports used & number of elements to determine when new rows are added
+    set_parameter_value F2SDRAM_Width_Last_Size $rows
+    set_parameter_value F2SDRAM_CMD_PORT_USED   [ format "0x%X" $command_ports_mask ]
+    set_parameter_value F2SDRAM_RD_PORT_USED    [ format "0x%X" $read_ports_mask ]
+    set_parameter_value F2SDRAM_WR_PORT_USED    [ format "0x%X" $write_ports_mask ]
+    set_parameter_value F2SDRAM_RST_PORT_USED   [ format "0x%X" $reset_ports_mask ]
+
+    # Bonding_out signals will be exported if f2sdram selected
+    if { ${rows} > 0 } {
+    	set param [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out]
+    	set_parameter_property BONDING_OUT_ENABLED visible $param
+    	set_parameter_property BONDING_OUT_ENABLED enabled $param
+    } else {
+    	set_parameter_property BONDING_OUT_ENABLED enabled false
+    }
+
+}
+
+proc update_S2F_CLK_mux_options {} {
+    # TODO: retrieve mux options
+    # TODO: set allowed_ranges on muxes
+}
+
+proc dec2bin {i} {
+    set res {}
+    while {$i>0} {
+        set res [ expr {$i%2} ]$res
+        set i [expr {$i/2}]
+    }
+    if {$res == {}} {
+        set res 0
+    }
+    return $res
+}
+
+#####################################################################
+#
+# Gets valid modes for a peripheral with a given pin muxing option.
+# Parameters: * peripheral_ref: name of an array pointing to the
+#                               Peripheral HPS I/O Data
+#
+# Update parameter value with label 
+proc get_valid_modes {peripheral_name pin_muxing_option peripheral_ref fpga_available} {
+#####################################################################
+    upvar 1 $peripheral_ref peripheral
+    
+    if {[info exists peripheral(pin_sets)]} {
+	array set pin_sets $peripheral(pin_sets)
+    }
+    
+    if {[info exists pin_sets($pin_muxing_option)]} {
+	array set pin_set $pin_sets($pin_muxing_option)
+	set pin_set_modes $pin_set(valid_modes)
+	if {[string match -nocase "trace"  $peripheral_name]} {
+	    set valid_modes [list "HPS:8-bit Data" "HPSx4:4-bit Data"]
+	} elseif {[string match -nocase "usb*"  $peripheral_name]} {
+	    set valid_modes [list "SDR:SDR with PHY clock output mode" "SDR without external clock:SDR with PHY clock input mode"]
+	} else {
+	    set valid_modes [lsort -ascii -increasing $pin_set_modes]
+	}
+    } elseif {$fpga_available && [string compare $pin_muxing_option [FPGA_MUX_VALUE]] == 0} {
+	set valid_modes [list "Full"]
+    } else {
+	set valid_modes [list [NA_MODE_VALUE]]
+    }
+    return $valid_modes
+}
+
+proc is_peripheral_low_speed_serial_interface {peripheral_name} {
+    if {[string match -nocase "i2c*"  $peripheral_name] ||
+	[string match -nocase "can*"  $peripheral_name] ||
+	[string match -nocase "spi*"  $peripheral_name] ||
+	[string match -nocase "uart*" $peripheral_name]
+    } {
+	return 1
+    }
+    return 0
+}
+
+# updates the _PinMuxing and _Mode parameter allowed ranges
+# -uses a data structure to keep track of choices
+# -allowed ranges can come from FPGA Peripheral Interfaces or IOs
+# -when a pin muxing option is selected, the mode allowed ranges are
+#  set according to what's specified from the source (FPGA or pin i/o)
+proc update_pin_muxing_ui {device_family} {
+    
+    set peripheral_names [list_peripheral_names]
+    foreach peripheral $peripheral_names {
+	
+	get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral\
+	    selected_pin_muxing_option pin_muxing_options mode_options
+	
+	set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral]
+	set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral]
+	
+	set pin_muxing_options [lsort -ascii $pin_muxing_options]
+	set pin_muxing_options [linsert $pin_muxing_options 0 [UNUSED_MUX_VALUE]]
+	set_parameter_property $pin_muxing_param_name enabled true
+	set_parameter_property $pin_muxing_param_name visible true
+	set_parameter_property $pin_muxing_param_name allowed_ranges $pin_muxing_options
+	set_parameter_property $mode_param_name       visible true
+	
+
+	set selected_mode_option [get_parameter_value $mode_param_name]
+	
+	# Disable I2C parameters so they can only be changed by altering EMAC parameters
+	# in the HPS IP GUI
+	if {([string compare $peripheral "I2C2" ] == 0  || [string compare $peripheral "I2C3" ] == 0)
+	    && [string match "*EMAC*" $selected_mode_option]} {
+	    set_parameter_property $pin_muxing_param_name enabled false
+	    set_parameter_property $mode_param_name       enabled false                                  
+	} else {
+	    set_parameter_property $mode_param_name enabled true
+	}
+	set_parameter_property $mode_param_name allowed_ranges $mode_options
+	
+	# Disabled peripherals that not supported by certain device family
+        if {[check_device_family_equivalence $device_family ARRIAV]} {
+            foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] {
+                if {[string compare $excluded_peripheral $peripheral] == 0} { 
+                    set_parameter_property $pin_muxing_param_name enabled false
+	            set_parameter_property $pin_muxing_param_name visible false
+	            set_parameter_property $mode_param_name       enabled false
+	            set_parameter_property $mode_param_name       visible false
+                }
+            }
+        }
+    }
+    
+    # Only show I2C's "Used by EMACx" modes when EMAC is using I2C
+    if {[is_pin_mux_data_available hps_ip_pin_muxing_model]} {
+	foreach emac {EMAC0 EMAC1} {
+	    set emac_pin_set [get_parameter_value [format [PIN_MUX_PARAM_FORMAT] $emac]]
+	    set emac_mode    [get_parameter_value [format    [MODE_PARAM_FORMAT] $emac]]
+
+	    funset i2c_name
+	    get_linked_peripheral hps_ip_pin_muxing_model $emac $emac_pin_set\
+		i2c_name i2c_pin_set i2c_mode
+	    
+	    if {[info exists i2c_name] && ![string match "*${i2c_name}*" $emac_mode]} {
+		# remove EMAC mode
+		set i2c_mode_param  [format [MODE_PARAM_FORMAT] $i2c_name]
+		set i2c_valid_modes [get_parameter_property $i2c_mode_param ALLOWED_RANGES]
+		
+		set new_i2c_valid_modes [list]
+		foreach mode $i2c_valid_modes {
+		    if {![string match "*${emac}*" $mode]} {
+			lappend new_i2c_valid_modes $mode
+		    }
+		}
+		set_parameter_property $i2c_mode_param ALLOWED_RANGES $new_i2c_valid_modes
+	    }
+	}
+    }
+}
+
+proc validate_interrupt {device_family} {
+    set interrupt_groups [list_h2f_interrupt_groups]
+    set excluded "CAN"
+    foreach interrupt_group $interrupt_groups {
+	set parameter "S2FINTERRUPT_${interrupt_group}_Enable"		
+	set_parameter_property $parameter enabled      true
+	set_parameter_property $parameter visible      true
+	if {[check_device_family_equivalence $device_family ARRIAV] && [string compare $excluded $interrupt_group] == 0} {
+			set_parameter_property $parameter enabled      false
+			set_parameter_property $parameter visible      false
+    	}
+    }
+}
+
+proc update_gpio_ui {placement_by_pin_ref} {
+    upvar 1 $placement_by_pin_ref placement_by_pin
+    # TODO: caching of what needs to be updated?
+    set customer_pin_names  [list]
+    set gpio_names          [list]
+    set loanio_names        [list]
+    set conflicts           [list]
+
+    set customer_pin_names [hps_ip_pin_muxing_model::get_customer_pin_names]
+    
+    foreach_gpio_entry hps_ip_pin_muxing_model\
+	entry gpio_index gpio_name pin gplin_used gplin_select\
+    {
+	lappend gpio_names $gpio_name
+
+	set conflict ""
+	if {[info exists placement_by_pin($pin)]} {
+	    set conflict [join $placement_by_pin($pin) ", "]
+	}
+	lappend conflicts $conflict
+    }
+    foreach_loan_io_entry hps_ip_pin_muxing_model\
+	entry loanio_index loanio_name pin gplin_used gplin_select\
+    {
+	lappend loanio_names $loanio_name                
+    }             
+    set_parameter_value Customer_Pin_Name_DERIVED $customer_pin_names
+    set_parameter_value GPIO_Name_DERIVED         $gpio_names
+    set_parameter_value LOANIO_Name_DERIVED       $loanio_names
+    set_parameter_value GPIO_Conflict_DERIVED     $conflicts
+}
+
+proc peripheral_to_wys_atom_name {device_family peripheral} {
+    set generic_atom_name [hps_io_peripheral_to_generic_atom_name $peripheral]
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $generic_atom_name]
+    return $wys_atom_name
+}
+
+# TODO: deal with going out of bounds (gpio_index > 70)
+proc gpio_index_to_gpio_port_index {gpio_index} {
+    set group      [expr {$gpio_index / 29}]
+    set port_index [expr {$gpio_index % 29}]
+
+    set result [list $group $port_index]
+    return $result
+}
+
+                                     
+
+proc validate_pin_muxing {device_family placement_by_pin_ref} {
+    upvar 1 $placement_by_pin_ref placement_by_pin
+
+    # see which pins are being used more than once
+    # peripherals
+    funset pin_to_peripheral ;# pin names to peripheral that is occupying
+    funset conflict_pin_list ;
+    
+    foreach peripheral_name [list_peripheral_names] {
+	set pins_used 0
+	set mapping_msg "Peripheral $peripheral_name pin mapping:"
+	set comma " "
+	set periph_inst [string tolower "${peripheral_name}_inst"]
+	foreach_used_peripheral_pin hps_ip_pin_muxing_model $peripheral_name\
+	    signal_name\
+	    map\
+	    pin\
+	    location\
+	    mux_select\
+	{
+	    # Validate
+	    set entry_exists [info exists pin_to_peripheral($pin)]
+	    if {$entry_exists == 1} {
+		set conflicting_peripheral $pin_to_peripheral($pin)
+		# only emit an error once per unique pair of conflicting peripherals
+		if {[info exists known_conflicts($conflicting_peripheral)] == 0} {
+		    set known_conflicts($conflicting_peripheral) 1
+		    # TODO: more detailed error message e.g. which pins? explicitly say the bank and modes?
+		    send_message error "Refer to the Peripherals Mux Table for more details. The selected peripherals '$conflicting_peripheral' and '$peripheral_name' are conflicting. "	 
+		}
+		set conflict_pin_list($pin) 1
+	    } else {
+		set pin_to_peripheral($pin) $peripheral_name
+	    }
+	    
+	    # Render pins
+	    lassign $map in_port out_port oe_port
+	    set goes_out 0
+	    set goes_in 0
+
+	    # by default, all signals are assumed to be from the same instance
+	    if {$in_port != ""} {
+		set in_port "${periph_inst}:${in_port}"
+		set goes_in 1
+	    }
+	    if {$out_port != ""} {
+		set out_port "${periph_inst}:${out_port}"
+		set goes_out 1
+	    }
+	    if {$oe_port != ""} {
+		set oe_port "${periph_inst}:${oe_port}"
+		set goes_out 1
+	    }
+
+	    if {$goes_in && $goes_out} {
+		set dir bidir
+	    } elseif {$goes_out} {
+		set dir output
+	    } else {
+		set dir input
+	    } 
+	    
+	    hps_io::add_pin $periph_inst $signal_name $dir $location $in_port $out_port $oe_port
+
+	    if {[info exists placement_by_pin($pin)] == 0} {             
+		set placement_by_pin($pin) [list]          
+	    }
+	    lappend placement_by_pin($pin) "${peripheral_name}.${signal_name}"
+
+	    set mapping_msg "${mapping_msg}${comma}${signal_name}:${pin}"
+	    set comma ", "
+	    set pins_used 1
+	}
+	if {$pins_used} {
+	    # send_message info $mapping_msg
+	    set wys_atom_name [peripheral_to_wys_atom_name $device_family $peripheral_name]
+	    set location [locations::get_hps_io_peripheral_location $peripheral_name]
+	    hps_io::add_peripheral ${periph_inst} $wys_atom_name $location
+	}
+    }
+    
+    # HLGPI input only pins
+    set hlgpi_pins [hps_ip_pin_muxing_model::get_hlgpi_pins]
+    set hlgpi_count [llength $hlgpi_pins]
+    set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"]
+    set periph_inst "gpio_inst"
+    set gpio_unused 1
+    set device [get_device]
+    
+    if { [ string range $device 0 3 ] == "5CSE" && [ string range $device 8 9 ] == "19" } {
+    	send_message info "HLGPI is not available for Device $device (484 pins)"    
+        set_parameter_property   HLGPI_Enable      enabled        false
+    } else {
+        set_parameter_property   HLGPI_Enable      enabled        true
+    }
+    
+    if { [is_enabled HLGPI_Enable] && [get_parameter_property HLGPI_Enable enabled] } {
+        for {set hlgpi_pin_index 0} {$hlgpi_pin_index < $hlgpi_count} {incr hlgpi_pin_index} {    
+            # HLGPI connected to gpio[26:13]
+            set gpio_port_index [ expr {$hlgpi_pin_index + 13} ]     
+            set hlgpi_pin       [ lindex $hlgpi_pins $hlgpi_pin_index]
+        	
+            if {$gpio_unused} {
+                set atom_location [locations::get_hps_io_peripheral_location "GPIO"]
+                hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location
+                set gpio_unused 0
+            }
+            
+            set signal_name "HLGPI${hlgpi_pin_index}"
+            set pin_location [::pin_mux_db::get_location_of_pin $hlgpi_pin]
+            set in_port  "${periph_inst}:GPIO2_PORTA_I($gpio_port_index:$gpio_port_index)"
+            set out_port ""
+            set oe_port  ""
+          
+            hps_io::add_pin ${periph_inst} $signal_name input $pin_location $in_port $out_port $oe_port
+        }
+    }
+                                                  
+    # gpio
+    funset gpio_port_placement_set ;# set of gpio ports that are being used
+    set enable_list [get_parameter_value GPIO_Enable]
+    set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"]
+    set periph_inst "gpio_inst"
+    
+    # check and set GPIO_Pin_Used_DERIVED parameter 
+    set_parameter_value GPIO_Pin_Used_DERIVED false
+    
+    foreach_gpio_entry hps_ip_pin_muxing_model\
+	entry gpio_index gpio_name pin gplin_used gplin_select\
+    {
+	set enabled 0                          
+	set enable_value  [lindex $enable_list $entry]
+	if { [string compare $enable_value "Yes" ] == 0 } {
+	    set enabled 1
+	}
+	if {$enabled} {
+	    set entry_exists [info exists pin_to_peripheral($pin)]
+	    if {$entry_exists} {
+		set conflicting_peripheral $pin_to_peripheral($pin)
+		send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral '$conflicting_peripheral' and '${gpio_name}' are conflicting."
+		set conflict_pin_list($pin) 1
+	    } else {
+		set pin_to_peripheral($pin) $gpio_name
+	    }
+
+	    if {[info exists gpio_port_placement_set($gpio_index)]} {
+		send_message error "Refer to the Peripherals Mux Table for more details. GPIO${gpio_index} cannot be used twice."
+		set conflict_pin_list($pin) 1
+	    } else {
+		set gpio_port_placement_set($gpio_index) 1
+	    }
+	    
+	    if {$gpio_unused} {
+		set atom_location [locations::get_hps_io_peripheral_location "GPIO"]
+		hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location
+		set gpio_unused 0
+	    }
+	    
+	    lassign [gpio_index_to_gpio_port_index $gpio_index] gpio_group gpio_port_index
+	    set in_port  "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)"
+	    set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)"
+	    set oe_port  "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)"
+
+	    set pin_location [::pin_mux_db::get_location_of_pin $pin]
+	    hps_io::add_pin $periph_inst $gpio_name bidir $pin_location $in_port $out_port $oe_port
+	    
+	    # set GPIO_Pin_Used_DERIVED to true if GPIO pins used 
+	    set_parameter_value GPIO_Pin_Used_DERIVED true
+	}
+    }
+    
+    # loan i/o
+    set enable_list [get_parameter_value LOANIO_Enable]
+    set loanio_used 0
+    set loanio_count 0
+    foreach_loan_io_entry hps_ip_pin_muxing_model\
+        entry loanio_index loanio_name pin gplin_used gplin_select\
+    {
+        if {$loanio_count < $loanio_index} {
+    	set loanio_count $loanio_index
+        }
+        set enabled 0
+        set enable_value  [lindex $enable_list $entry]
+        if { [string compare $enable_value "Yes" ] == 0 } {
+    	set enabled 1
+        }
+        
+        if {$enabled} {
+    	set entry_exists [info exists pin_to_peripheral($pin)]
+    	if {$entry_exists} {
+    	    set conflicting_peripheral $pin_to_peripheral($pin)
+    	    send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral for '$conflicting_peripheral' and '${loanio_name}' are conflicting."
+    	    set conflict_pin_list($pin) 1
+    	} else {
+    	    set pin_to_peripheral($pin) $loanio_name
+    	}
+    
+    	if {[info exists gpio_port_placement_set($loanio_index)]} {
+    	    send_message error "Refer to the Peripherals Mux Table for more details. GPIO${loanio_index} cannot be used twice."
+    	    set conflict_pin_list($pin) 1
+    	} else {
+    	    set gpio_port_placement_set($loanio_index) 1
+    	}
+    	
+    	set loanio_used 1
+    	if {$gpio_unused} {
+    	    set atom_location [locations::get_hps_io_peripheral_location "GPIO"]
+    	    hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location
+    	    set gpio_unused 0
+    	}
+    	
+    	lassign [gpio_index_to_gpio_port_index $loanio_index] gpio_group gpio_port_index
+    	set in_port  "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)"
+    	set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)"
+    	set oe_port  "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)"
+    	
+    	set pin_location [::pin_mux_db::get_location_of_pin $pin]
+    	hps_io::add_pin $periph_inst $loanio_name bidir $pin_location $in_port $out_port $oe_port
+    	
+        }
+    }     
+    incr loanio_count ;# count is one greater than the highest index
+    if $loanio_used {
+        set wys_atom_name [peripheral_to_wys_atom_name $device_family "LOANIO"]
+        set location {}
+        set periph_inst "loan_io_inst"
+        set iface_name  "h2f_loan_io"
+        set z           "h2f_loan_"
+        fpga_interfaces::add_module_instance ${periph_inst} $wys_atom_name $location
+        fpga_interfaces::add_interface       $iface_name conduit Input
+        set pin_muxing   [get_parameter_value pin_muxing]
+        fpga_interfaces::add_interface_port  $iface_name "${z}in"  in  Output ${loanio_count}  $periph_inst loanio_in
+        fpga_interfaces::add_interface_port  $iface_name "${z}out" out Input  ${loanio_count}  $periph_inst loanio_out
+        fpga_interfaces::add_interface_port  $iface_name "${z}oe"  oe  Input  ${loanio_count}  $periph_inst loanio_oe
+        
+        # add loanIO to GPIO atom connection
+        set loanio_periph_inst  "loan_io_inst"
+        set loanio_iface_name   "loanio_gpio"
+        set loanio_z            "loanio_gpio_"
+        set gpio_periph_inst    "gpio_inst"
+        set gpio_iface_name     "gpio_loanio"
+        set gpio_z              "gpio_loanio_"
+        set gpio_port_size 29
+        set start_index 0
+        
+        if {$gpio_unused} {
+            set gpio_wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"]
+            set gpio_atom_location [locations::get_hps_io_peripheral_location "GPIO"]
+            hps_io::add_peripheral ${gpio_periph_inst} ${gpio_wys_atom_name} ${gpio_atom_location}
+            set gpio_unused 0
+        }
+        
+        fpga_interfaces::add_interface       $loanio_iface_name conduit Input "NO_EXPORT"
+        ::hps_io::internal::add_interface $gpio_iface_name conduit Output "NO_EXPORT"
+        
+        for {set i 0} {$i <= 2} {incr i} {
+            if {[expr ($loanio_count - $start_index)] < $gpio_port_size} {
+                set gpio_port_size [expr ($loanio_count - $start_index)]
+            }
+            set end_index   [expr ($start_index + $gpio_port_size - 1)]
+            
+            fpga_interfaces::add_interface_port  $loanio_iface_name "${loanio_z}loanio${i}_i"  "loanio${i}_i"  Input  ${gpio_port_size}
+            fpga_interfaces::add_interface_port  $loanio_iface_name "${loanio_z}loanio${i}_oe" "loanio${i}_oe" Output ${gpio_port_size}
+            fpga_interfaces::add_interface_port  $loanio_iface_name "${loanio_z}loanio${i}_o"  "loanio${i}_o"  Output ${gpio_port_size}
+            
+            fpga_interfaces::set_port_fragments  $loanio_iface_name "${loanio_z}loanio${i}_i"  "${loanio_periph_inst}:GPIO_IN($end_index:$start_index)"
+            fpga_interfaces::set_port_fragments  $loanio_iface_name "${loanio_z}loanio${i}_oe" "${loanio_periph_inst}:GPIO_OE($end_index:$start_index)"
+            fpga_interfaces::set_port_fragments  $loanio_iface_name "${loanio_z}loanio${i}_o"  "${loanio_periph_inst}:GPIO_OUT($end_index:$start_index)"
+            
+            ::hps_io::internal::add_interface_port  $gpio_iface_name "${gpio_z}loanio${i}_i"  "loanio${i}_i"  Output ${gpio_port_size}  $gpio_periph_inst "LOANIO${i}_I"
+            ::hps_io::internal::add_interface_port  $gpio_iface_name "${gpio_z}loanio${i}_oe" "loanio${i}_oe" Input ${gpio_port_size}   $gpio_periph_inst  "LOANIO${i}_OE"
+            ::hps_io::internal::add_interface_port  $gpio_iface_name "${gpio_z}loanio${i}_o"  "loanio${i}_o"  Input  ${gpio_port_size}  $gpio_periph_inst "LOANIO${i}_O"
+            
+            set start_index [expr ($end_index + 1)]
+        }
+    }
+     set conflicts           [list]
+    set pins           [list]
+    foreach_gpio_entry hps_ip_pin_muxing_model\
+    entry gpio_index gpio_name pin gplin_used gplin_select\
+    {
+        set entry_exists [info exists conflict_pin_list($pin)]
+        if {$entry_exists} {
+            set conflict "Yes"
+        } else {                              
+            set conflict "No"
+        }
+        lappend conflicts $conflict
+        lappend pins $pin
+    }
+   set_parameter_value JAVA_CONFLICT_PIN $conflicts
+  set_parameter_value JAVA_GUI_PIN_LIST $pins
+}
+                                                                                     
+#####################################################
+#
+# Sets a valid mode for the peripheral when its pin
+# muxing option changes. Will try to retain the
+# original mode if available.
+#                                                                                                                                            
+proc on_altered_peripheral_pin_muxing {peripheral_name} {
+#####################################################
+    set mode_param_name       "${peripheral_name}_Mode"
+    set mode_option       [get_parameter_value $mode_param_name]                  
+
+    get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral_name\
+	selected_pin_muxing_option pin_muxing_options new_valid_modes   
+    
+    # filter the label name of the parameter value if exist
+    if {[lsearch $new_valid_modes $mode_option] == -1} {
+	regsub ":.*" [lindex $new_valid_modes 0] "" new_mode_option
+    } else {
+	set new_mode_option $mode_option
+    }
+    set_parameter_value $mode_param_name $new_mode_option
+    
+    if {[string match "*EMAC*" $peripheral_name]} {
+	on_emac_mode_switch_internal $peripheral_name
+    }
+}
+
+# Adds the pin muxing model argument
+proc on_emac_mode_switch_internal {peripheral_name} {
+    on_emac_mode_switch hps_ip_pin_muxing_model $peripheral_name
+}
+
+proc validate_and_update_ddr {} {
+    set desired_operational_freq [get_parameter_value DDR_DesiredFreq]
+    if {$desired_operational_freq < 0.0} {
+	send_message error "The operational frequency of the DDR Controller cannot be negative."
+    } else {
+	send_message warning "The recommended DDR Controller clock frequency and phase shift information is not correct."
+
+	set_parameter_value DDR_PLLC0RecommendedFreq_DERIVED $desired_operational_freq
+	set_parameter_value DDR_PLLC1RecommendedFreq_DERIVED [expr $desired_operational_freq * 2.0]
+	set_parameter_value DDR_PLLC2RecommendedFreq_DERIVED $desired_operational_freq
+	set_parameter_value DDR_PLLC3RecommendedFreq_DERIVED $desired_operational_freq
+
+	set_parameter_value DDR_PLLC0RecommendedPhase_DERIVED 0.0
+	set_parameter_value DDR_PLLC1RecommendedPhase_DERIVED 1.0
+	set_parameter_value DDR_PLLC2RecommendedPhase_DERIVED 2.0
+	set_parameter_value DDR_PLLC3RecommendedPhase_DERIVED 3.0
+    }
+
+    for {set index 0} {${index} < 4} {incr index} {
+	set p_name "DDR_PLLC${index}ActualFreq"
+	set value [get_parameter_value $p_name]
+	if {$value < 0.0} {
+	    send_message error "DDR PLL Output C${index} cannot have a negative clock frequency."
+	}
+
+	set p_name "DDR_PLLC${index}ActualPhase"
+	set value [get_parameter_value $p_name]
+	if {$value < 0.0} {
+	    send_message error "DDR PLL Output C${index} cannot have a negative clock phase shift."
+	}
+    }
+}
+
+
+######################
+##### Elaboration #####
+######################
+
+proc elab {logical_view} {
+    # TODO: add RTL information for each
+    set device_family [get_parameter_value hps_device_family]
+
+    elab_clocks_resets		  $device_family
+    
+    elab_MPU_EVENTS               $device_family
+    elab_DEBUGAPB                 $device_family
+    elab_STM                      $device_family
+    elab_CTI			  $device_family
+    elab_TPIUFPGA                 $device_family
+    elab_GP			  $device_family
+    elab_BOOTFROMFPGA		  $device_family
+    
+    if {$logical_view == 0} {
+        elab_F2S			  $device_family
+        elab_LWH2F			  $device_family
+        elab_S2F			  $device_family
+        elab_F2SDRAM		  $device_family
+        
+    }
+
+    elab_DMA			  $device_family
+    elab_INTERRUPTS		  $device_family $logical_view
+
+    elab_emac_ptp          $device_family
+
+    elab_TEST                     $device_family
+
+    # Handle Special Case EMAC signal... ptp_ref_clk
+    set emac0_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC0]
+    set emac1_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC1]
+    set emac0_pin_mux_value [get_parameter_value $emac0_pin_mux_param_name]
+    set emac1_pin_mux_value [get_parameter_value $emac1_pin_mux_param_name]
+    set emac0_pin_mux_allowed_ranges [get_parameter_property $emac0_pin_mux_param_name allowed_ranges]
+    set emac1_pin_mux_allowed_ranges [get_parameter_property $emac1_pin_mux_param_name allowed_ranges]
+
+    set emac0_ptp_enabled [expr {[string compare $emac0_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac0_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}]
+    set emac1_ptp_enabled [expr {[string compare $emac1_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac1_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}]
+    
+    set emac0_io_enabled [expr {[string compare $emac0_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac0_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}]
+    set emac1_io_enabled [expr {[string compare $emac1_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac1_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}]
+    
+    set emac0_ptp           [get_parameter_value EMAC0_PTP]
+    set emac1_ptp           [get_parameter_value EMAC1_PTP]
+    
+    if {$emac0_ptp &&  $emac0_io_enabled} {
+        set emac0_ptp_enabled 1
+    }
+    if {$emac1_ptp &&  $emac1_io_enabled} {
+        set emac1_ptp_enabled 1
+    }
+    
+    if {$emac0_ptp_enabled || $emac1_ptp_enabled } {
+        set instance_name clocks_resets
+        fpga_interfaces::add_interface      emac_ptp_ref_clock                    clock  Input
+        fpga_interfaces::add_interface_port emac_ptp_ref_clock  emac_ptp_ref_clk  clk    Input  1     $instance_name ptp_ref_clk
+    }
+
+    # TODO: elab peripherals that mux signals to the fpga
+    elab_FPGA_Peripheral_Signals  $device_family
+
+	set_parameter_value DEVICE_FAMILY [get_parameter_value SYS_INFO_DEVICE_FAMILY]
+}
+
+proc elab_MPU_EVENTS {device_family} {
+    if [is_enabled MPU_EVENTS_Enable] {
+	set instance_name mpu_events
+	set atom_name hps_interface_mpu_event_standby
+	set location [locations::get_fpga_location $instance_name $atom_name]
+	
+	set iface_name "h2f_mpu_events"
+	set z          "h2f_mpu_"
+	fpga_interfaces::add_interface       $iface_name conduit Input
+	fpga_interfaces::add_interface_port  $iface_name ${z}eventi      eventi      Input  1  $instance_name eventi
+	fpga_interfaces::add_interface_port  $iface_name ${z}evento      evento      Output 1  $instance_name evento
+	fpga_interfaces::add_interface_port  $iface_name ${z}standbywfe  standbywfe  Output 2  $instance_name standbywfe
+	fpga_interfaces::add_interface_port  $iface_name ${z}standbywfi  standbywfi  Output 2  $instance_name standbywfi
+
+	set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    }
+}
+
+proc elab_DEBUGAPB {device_family} {
+    set instance_name debug_apb
+    set atom_name hps_interface_dbg_apb
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    
+    if [is_enabled DEBUGAPB_Enable] {
+	set clock_name "h2f_debug_apb_clock"
+	fpga_interfaces::add_interface       $clock_name clock Input
+	fpga_interfaces::add_interface_port  $clock_name "h2f_dbg_apb_clk"  clk Input 1 $instance_name P_CLK
+
+	set reset_name "h2f_debug_apb_reset"
+	fpga_interfaces::add_interface           $reset_name reset Output
+	fpga_interfaces::add_interface_port      $reset_name "h2f_dbg_apb_rst_n"  reset_n Output 1 $instance_name P_RESET_N
+	fpga_interfaces::set_interface_property  $reset_name associatedClock $clock_name
+	
+	set iface_name "h2f_debug_apb"
+	set z          "h2f_dbg_apb_"
+	fpga_interfaces::add_interface               $iface_name apb master
+	fpga_interfaces::add_interface_port  $iface_name "${z}PADDR"           paddr           Output 18 $instance_name P_ADDR
+	fpga_interfaces::add_interface_port  $iface_name "${z}PADDR31"         paddr31         Output 1  $instance_name P_ADDR_31
+	fpga_interfaces::add_interface_port  $iface_name "${z}PENABLE"         penable         Output 1  $instance_name P_ENABLE
+	fpga_interfaces::add_interface_port  $iface_name "${z}PRDATA"          prdata          Input  32 $instance_name P_RDATA
+	fpga_interfaces::add_interface_port  $iface_name "${z}PREADY"          pready          Input  1  $instance_name P_READY
+	fpga_interfaces::add_interface_port  $iface_name "${z}PSEL"            psel            Output 1  $instance_name P_SEL
+	fpga_interfaces::add_interface_port  $iface_name "${z}PSLVERR"         pslverr         Input  1  $instance_name P_SLV_ERR
+	fpga_interfaces::add_interface_port  $iface_name "${z}PWDATA"          pwdata          Output 32 $instance_name P_WDATA
+	fpga_interfaces::add_interface_port  $iface_name "${z}PWRITE"          pwrite          Output 1  $instance_name P_WRITE
+	fpga_interfaces::set_interface_property      $iface_name associatedClock $clock_name
+	fpga_interfaces::set_interface_property      $iface_name associatedReset $reset_name
+
+	set iface_name "h2f_debug_apb_sideband"
+	set z          "h2f_dbg_apb_"
+	fpga_interfaces::add_interface       $iface_name conduit Input
+	fpga_interfaces::add_interface_port  $iface_name "${z}PCLKEN"          pclken          Input  1  $instance_name P_CLK_EN
+	fpga_interfaces::add_interface_port  $iface_name "${z}DBG_APB_DISABLE" dbg_apb_disable Input  1  $instance_name DBG_APB_DISABLE
+	fpga_interfaces::set_interface_property      $iface_name associatedClock $clock_name
+	fpga_interfaces::set_interface_property      $iface_name associatedReset $reset_name
+
+    } else {
+	# Tie low when FPGA debug apb not being used
+	fpga_interfaces::set_instance_port_termination ${instance_name} "P_CLK_EN" 1 0 0:0 0
+	fpga_interfaces::set_instance_port_termination ${instance_name} "DBG_APB_DISABLE" 1 0 0:0 0
+    }
+}
+
+proc elab_STM {device_family} {
+    if [is_enabled STM_Enable] {
+	set instance_name stm_event
+	set atom_name hps_interface_stm_event
+	set location [locations::get_fpga_location $instance_name $atom_name]
+	
+	fpga_interfaces::add_interface       f2h_stm_hw_events conduit Input
+	fpga_interfaces::add_interface_port  f2h_stm_hw_events f2h_stm_hwevents stm_hwevents Input 28  $instance_name stm_event
+
+	set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    }
+}
+
+proc elab_CTI {device_family} {
+    set instance_name cross_trigger_interface
+    set atom_name hps_interface_cross_trigger
+    set location [locations::get_fpga_location $instance_name $atom_name]
+
+    if [is_enabled CTI_Enable] {
+	set iface_name "h2f_cti"
+	set z          "h2f_cti_"
+	fpga_interfaces::add_interface          $iface_name conduit Input
+	fpga_interfaces::add_interface_port     $iface_name ${z}trig_in         trig_in         Input  8 $instance_name trig_in
+	fpga_interfaces::add_interface_port     $iface_name ${z}trig_in_ack     trig_in_ack     Output 8 $instance_name trig_inack
+	fpga_interfaces::add_interface_port     $iface_name ${z}trig_out        trig_out        Output 8 $instance_name trig_out
+	fpga_interfaces::add_interface_port     $iface_name ${z}trig_out_ack    trig_out_ack    Input  8 $instance_name trig_outack
+	# case:105603 hide asicctl output signal
+	# fpga_interfaces::add_interface_port     $iface_name ${z}asicctl         asicctl         Output 8 $instance_name asicctl
+	fpga_interfaces::add_interface_port     $iface_name ${z}fpga_clk_en     fpga_clk_en Input  1 $instance_name clk_en
+	fpga_interfaces::set_interface_property $iface_name associatedClock h2f_cti_clock
+	fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset
+
+	fpga_interfaces::add_interface       h2f_cti_clock  clock Input
+	fpga_interfaces::add_interface_port  h2f_cti_clock  h2f_cti_clk clk Input 1                 $instance_name clk
+
+	set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    }
+}
+
+proc elab_TPIUFPGA {device_family} {
+    set instance_name tpiu
+    set atom_name hps_interface_tpiu_trace
+    set location [locations::get_fpga_location $instance_name $atom_name]
+
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+
+    if { [string compare [get_parameter_value TPIUFPGA_Enable] "true" ] == 0 } {
+    	set_parameter_property   TPIUFPGA_alt   enabled        true
+	set iface_name "h2f_tpiu"
+	set z          "h2f_tpiu_"
+	fpga_interfaces::add_interface       $iface_name conduit input
+	fpga_interfaces::add_interface_port  $iface_name ${z}clk_ctl   clk_ctl  Input  1  $instance_name traceclk_ctl
+	fpga_interfaces::add_interface_port  $iface_name ${z}data      data     Output 32 $instance_name trace_data
+    	
+    	# case 245159
+    	if {[string compare [get_parameter_value TPIUFPGA_alt] "true" ] == 0} {
+	    fpga_interfaces::add_interface_port  $iface_name ${z}clkin    clkin      Input  1  $instance_name traceclkin
+    	} else {
+	    set iface_name "h2f_tpiu_clock_in"
+	    fpga_interfaces::add_interface       $iface_name clock input
+	    fpga_interfaces::add_interface_port  $iface_name ${z}clk_in    clk      Input  1  $instance_name traceclkin
+	}
+
+	set clock_in_rate [get_parameter_value H2F_TPIU_CLOCK_IN_FREQ]
+	set clock_rate [expr {$clock_in_rate / 2}]
+	set iface_name "h2f_tpiu_clock"
+       	fpga_interfaces::add_interface          $iface_name clock output
+	fpga_interfaces::add_interface_port     $iface_name ${z}clk       clk      Output 1  $instance_name traceclk
+	fpga_interfaces::set_interface_property $iface_name clockRateKnown true
+	fpga_interfaces::set_interface_property $iface_name clockRate $clock_rate
+
+	add_clock_constraint_if_valid $clock_rate "*|fpga_interfaces|${instance_name}|traceclk"
+
+    } else {
+    	set_parameter_property   TPIUFPGA_alt   enabled        false
+	fpga_interfaces::set_instance_port_termination ${instance_name} "traceclk_ctl" 1 1 0:0 1
+    }
+}
+
+proc elab_GP {device_family} {
+    if [is_enabled GP_Enable] {
+	set instance_name h2f_gp
+	set atom_name hps_interface_mpu_general_purpose
+	set location [locations::get_fpga_location $instance_name $atom_name]
+	
+	set iface_name "h2f_gp"
+	set z          "h2f_gp_"
+	fpga_interfaces::add_interface       $iface_name  conduit Input
+	fpga_interfaces::add_interface_port  $iface_name  ${z}in   gp_in  Input  32  $instance_name gp_in
+	fpga_interfaces::add_interface_port  $iface_name  ${z}out  gp_out Output 32  $instance_name gp_out
+
+	set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    }
+}
+
+proc elab_BOOTFROMFPGA {device_family} {
+    set instance_name boot_from_fpga
+    set atom_name hps_interface_boot_from_fpga
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    
+    set bsel_en               [expr { [string compare [get_parameter_value BSEL_EN] "true" ] == 0 } ]
+    set bsel                  [get_parameter_value BSEL]
+    set csel_en               [expr { [string compare [get_parameter_value CSEL_EN] "true" ] == 0 } ]
+    set csel                  [get_parameter_value CSEL]
+    set boot_from_fpga_enable [expr { [string compare [get_parameter_value BOOTFROMFPGA_Enable] "true" ] == 0 } ]            
+    set ini_string            [get_parameter_value quartus_ini_hps_ip_enable_bsel_csel]
+    set ini_enabled           [expr { [string compare $ini_string "true" ] == 0 } ]
+                                                                                                  
+    # force disable bsel/csel by default
+    if {!$ini_enabled} {
+	set bsel_en 0
+	set bsel    1                                                                            
+	set csel_en 0
+	set csel    1
+    }
+
+    # when INI enabled, the controls should appear in the GUI
+    foreach parameter {BSEL BSEL_EN CSEL CSEL_EN} {
+	set_parameter_property $parameter visible $ini_string
+	set_parameter_property $parameter enabled $ini_string
+    }
+    
+    fpga_interfaces::set_instance_port_termination ${instance_name} "bsel" 3 0 2:0 $bsel
+    fpga_interfaces::set_instance_port_termination ${instance_name} "csel" 2 0 1:0 $csel
+    
+    if {$bsel_en} {
+        fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 1
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 0
+    }
+
+    if {$csel_en} {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 1
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 0
+    }
+    
+    if {$boot_from_fpga_enable} {
+	set iface_name "f2h_boot_from_fpga"
+	set z          "f2h_boot_from_fpga_"
+	fpga_interfaces::add_interface       $iface_name  conduit Input
+	fpga_interfaces::add_interface_port  $iface_name  "${z}ready"       boot_from_fpga_ready       Input 1  $instance_name boot_from_fpga_ready
+	fpga_interfaces::add_interface_port  $iface_name  "${z}on_failure"  boot_from_fpga_on_failure  Input 1  $instance_name boot_from_fpga_on_failure
+    } else {
+        fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_ready" 1 0 0:0 0
+        fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_on_failure" 1 0 0:0 0
+    }
+    
+    if {$boot_from_fpga_enable} {
+        send_message info "Ensure that valid Cortex A9 boot code is available to the HPS system when enabling boot from FPGA and h2f_axi_master interface is connecting to slave component start at address 0x0."
+    }
+    
+    if {$bsel_en && $bsel == 1 && !$boot_from_fpga_enable} {
+        send_message warning "Boot from FPGA ready must be enabled to correctly boot from the FPGA." 
+    } 
+}
+
+
+proc elab_F2S {device_family} {
+    set instance_name fpga2hps
+    set atom_name hps_interface_fpga2hps
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    set termination_value 3
+
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    
+    set addr_width 32
+    set width [get_parameter_value F2S_Width]
+    if {$width > 0} {
+	set data_width 32
+	set strb_width 4
+	set termination_value 0
+	if {$width == 2} {
+	    set data_width 64
+	    set strb_width 8
+	    set termination_value 1
+	} elseif {$width == 3} {
+	    set data_width 128
+	    set strb_width 16
+	    set termination_value 2
+	}
+
+	set clock_name "f2h_axi_clock"
+	fpga_interfaces::add_interface       $clock_name   clock              Input
+	fpga_interfaces::add_interface_port  $clock_name   f2h_axi_clk        clk      Input  1    $instance_name clk
+	
+	set iface_name "f2h_axi_slave"
+	set z          "f2h_"
+   
+	fpga_interfaces::add_interface               $iface_name axi slave
+	fpga_interfaces::set_interface_property      $iface_name associatedClock $clock_name
+	fpga_interfaces::set_interface_property      $iface_name associatedReset h2f_reset
+	fpga_interfaces::set_interface_property      $iface_name readAcceptanceCapability 8
+	fpga_interfaces::set_interface_property      $iface_name writeAcceptanceCapability 8
+	fpga_interfaces::set_interface_property      $iface_name combinedAcceptanceCapability 16
+	fpga_interfaces::set_interface_property      $iface_name readDataReorderingDepth 16
+	fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width
+	fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width
+
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWID     awid     Input  8           $instance_name awid
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWADDR   awaddr   Input  $addr_width $instance_name awaddr
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWLEN    awlen    Input  4           $instance_name awlen
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWSIZE   awsize   Input  3           $instance_name awsize
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWBURST  awburst  Input  2           $instance_name awburst
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWLOCK   awlock   Input  2           $instance_name awlock
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWCACHE  awcache  Input  4           $instance_name awcache
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWPROT   awprot   Input  3           $instance_name awprot
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWVALID  awvalid  Input  1           $instance_name awvalid
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWREADY  awready  Output 1           $instance_name awready
+	fpga_interfaces::add_interface_port  $iface_name ${z}AWUSER   awuser   Input  5           $instance_name awuser
+
+	fpga_interfaces::add_interface_port  $iface_name ${z}WID      wid      Input  8           $instance_name wid
+	fpga_interfaces::add_interface_port  $iface_name ${z}WDATA    wdata    Input  $data_width $instance_name wdata
+	fpga_interfaces::add_interface_port  $iface_name ${z}WSTRB    wstrb    Input  $strb_width $instance_name wstrb
+	fpga_interfaces::add_interface_port  $iface_name ${z}WLAST    wlast    Input  1           $instance_name wlast
+	fpga_interfaces::add_interface_port  $iface_name ${z}WVALID   wvalid   Input  1           $instance_name wvalid
+	fpga_interfaces::add_interface_port  $iface_name ${z}WREADY   wready   Output 1           $instance_name wready
+
+	fpga_interfaces::add_interface_port  $iface_name ${z}BID      bid      Output 8           $instance_name bid
+	fpga_interfaces::add_interface_port  $iface_name ${z}BRESP    bresp    Output 2           $instance_name bresp
+	fpga_interfaces::add_interface_port  $iface_name ${z}BVALID   bvalid   Output 1           $instance_name bvalid
+	fpga_interfaces::add_interface_port  $iface_name ${z}BREADY   bready   Input  1           $instance_name bready
+
+
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARID     arid     Input  8           $instance_name arid
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARADDR   araddr   Input  $addr_width $instance_name araddr
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARLEN    arlen    Input  4           $instance_name arlen
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARSIZE   arsize   Input  3           $instance_name arsize
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARBURST  arburst  Input  2           $instance_name arburst
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARLOCK   arlock   Input  2           $instance_name arlock
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARCACHE  arcache  Input  4           $instance_name arcache
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARPROT   arprot   Input  3           $instance_name arprot
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARVALID  arvalid  Input  1           $instance_name arvalid
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARREADY  arready  Output 1           $instance_name arready
+	fpga_interfaces::add_interface_port  $iface_name ${z}ARUSER   aruser   Input  5           $instance_name aruser
+
+	fpga_interfaces::add_interface_port  $iface_name ${z}RID      rid      Output 8           $instance_name rid
+	fpga_interfaces::add_interface_port  $iface_name ${z}RDATA    rdata    Output $data_width $instance_name rdata
+	fpga_interfaces::add_interface_port  $iface_name ${z}RRESP    rresp    Output 2           $instance_name rresp
+	fpga_interfaces::add_interface_port  $iface_name ${z}RLAST    rlast    Output 1           $instance_name rlast
+	fpga_interfaces::add_interface_port  $iface_name ${z}RVALID   rvalid   Output 1           $instance_name rvalid
+	fpga_interfaces::add_interface_port  $iface_name ${z}RREADY   rready   Input  1           $instance_name rready
+    }
+    fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0  1:0 $termination_value
+}
+
+proc elab_S2F {device_family} {
+    set instance_name hps2fpga
+    set atom_name hps_interface_hps2fpga
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    set termination_value 3
+    
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+
+    set addr_width 30
+    set id_width   12
+    set width [get_parameter_value S2F_Width]
+    if {$width > 0} {
+	set data_width 32
+	set strb_width 4
+	set termination_value 0
+
+	if {$width == 2} {
+	    set data_width 64
+	    set strb_width 8
+	    set termination_value 1
+
+	} elseif {$width == 3} {
+	    set data_width 128
+	    set strb_width 16
+	    set termination_value 2
+	}
+
+	set clock_name "h2f_axi_clock"
+	fpga_interfaces::add_interface      $clock_name    clock              Input
+	fpga_interfaces::add_interface_port $clock_name    h2f_axi_clk        clk      Input  1     $instance_name clk
+   
+	set iface_name "h2f_axi_master"
+	set z          "h2f_"
+	
+	fpga_interfaces::add_interface               $iface_name  axi master
+	fpga_interfaces::set_interface_property      $iface_name associatedClock $clock_name
+	fpga_interfaces::set_interface_property      $iface_name associatedReset h2f_reset
+	fpga_interfaces::set_interface_property      $iface_name readIssuingCapability 8
+	fpga_interfaces::set_interface_property      $iface_name writeIssuingCapability 8
+	fpga_interfaces::set_interface_property      $iface_name combinedIssuingCapability 16
+	
+#	set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps golden_ref_design_CMSIS_1_1_to_arm_v2.svd]
+#	send_message info "REMOVE! SVD_PATH = $svd_path"
+#	fpga_interfaces::set_interface_property      $iface_name CMSIS_SVD_FILE     $svd_path
+#	fpga_interfaces::set_interface_property      $iface_name SVD_ADDRESS_GROUP  hps
+#	fpga_interfaces::set_interface_property      $iface_name SVD_ADDRESS_OFFSET [expr {0xC0000000}]
+	fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width
+	fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width
+	fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width
+	
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWID     awid     Output $id_width   $instance_name awid
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWADDR   awaddr   Output $addr_width $instance_name awaddr
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWLEN    awlen    Output 4           $instance_name awlen
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWSIZE   awsize   Output 3           $instance_name awsize
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWBURST  awburst  Output 2           $instance_name awburst
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWLOCK   awlock   Output 2           $instance_name awlock
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWCACHE  awcache  Output 4           $instance_name awcache
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWPROT   awprot   Output 3           $instance_name awprot
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWVALID  awvalid  Output 1           $instance_name awvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWREADY  awready  Input  1           $instance_name awready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}WID      wid      Output $id_width   $instance_name wid
+	fpga_interfaces::add_interface_port $iface_name  ${z}WDATA    wdata    Output $data_width $instance_name wdata
+	fpga_interfaces::add_interface_port $iface_name  ${z}WSTRB    wstrb    Output $strb_width $instance_name wstrb
+	fpga_interfaces::add_interface_port $iface_name  ${z}WLAST    wlast    Output 1           $instance_name wlast
+	fpga_interfaces::add_interface_port $iface_name  ${z}WVALID   wvalid   Output 1           $instance_name wvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}WREADY   wready   Input  1           $instance_name wready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}BID      bid      Input  $id_width   $instance_name bid
+	fpga_interfaces::add_interface_port $iface_name  ${z}BRESP    bresp    Input  2           $instance_name bresp
+	fpga_interfaces::add_interface_port $iface_name  ${z}BVALID   bvalid   Input  1           $instance_name bvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}BREADY   bready   Output 1           $instance_name bready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARID     arid     Output $id_width   $instance_name arid
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARADDR   araddr   Output $addr_width $instance_name araddr
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARLEN    arlen    Output 4           $instance_name arlen
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARSIZE   arsize   Output 3           $instance_name arsize
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARBURST  arburst  Output 2           $instance_name arburst
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARLOCK   arlock   Output 2           $instance_name arlock
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARCACHE  arcache  Output 4           $instance_name arcache
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARPROT   arprot   Output 3           $instance_name arprot
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARVALID  arvalid  Output 1           $instance_name arvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARREADY  arready  Input  1           $instance_name arready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}RID      rid      Input  $id_width   $instance_name rid
+	fpga_interfaces::add_interface_port $iface_name  ${z}RDATA    rdata    Input  $data_width $instance_name rdata
+	fpga_interfaces::add_interface_port $iface_name  ${z}RRESP    rresp    Input  2           $instance_name rresp
+	fpga_interfaces::add_interface_port $iface_name  ${z}RLAST    rlast    Input  1           $instance_name rlast
+	fpga_interfaces::add_interface_port $iface_name  ${z}RVALID   rvalid   Input  1           $instance_name rvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}RREADY   rready   Output 1           $instance_name rready
+       
+    }
+    fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0  1:0 $termination_value
+}
+
+proc elab_LWH2F {device_family} {
+    set instance_name hps2fpga_light_weight
+    set atom_name hps_interface_hps2fpga_light_weight
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    
+    if [is_enabled LWH2F_Enable] {
+	set addr_width 21
+	set data_width 32
+	set strb_width 4
+	set id_width   12
+	set clock_name "h2f_lw_axi_clock"
+	fpga_interfaces::add_interface      $clock_name    clock              Input
+	fpga_interfaces::add_interface_port $clock_name    h2f_lw_axi_clk     clk      Input  1     $instance_name clk
+   
+	set iface_name "h2f_lw_axi_master"
+	set z "h2f_lw_"
+	fpga_interfaces::add_interface               $iface_name axi master
+#	fpga_interfaces::set_interface_property      $iface_name SVD_ADDRESS_GROUP  hps
+#	fpga_interfaces::set_interface_property      $iface_name SVD_ADDRESS_OFFSET [expr {0xFC000000}]
+	fpga_interfaces::set_interface_property      $iface_name associatedClock $clock_name
+	fpga_interfaces::set_interface_property      $iface_name associatedReset h2f_reset
+	fpga_interfaces::set_interface_property      $iface_name readIssuingCapability 8
+	fpga_interfaces::set_interface_property      $iface_name writeIssuingCapability 8
+	fpga_interfaces::set_interface_property      $iface_name combinedIssuingCapability 16
+	fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width
+	fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width
+	fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width
+	
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWID     awid     Output $id_width   $instance_name awid
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWADDR   awaddr   Output $addr_width $instance_name awaddr
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWLEN    awlen    Output 4           $instance_name awlen
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWSIZE   awsize   Output 3           $instance_name awsize
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWBURST  awburst  Output 2           $instance_name awburst
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWLOCK   awlock   Output 2           $instance_name awlock
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWCACHE  awcache  Output 4           $instance_name awcache
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWPROT   awprot   Output 3           $instance_name awprot
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWVALID  awvalid  Output 1           $instance_name awvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}AWREADY  awready  Input  1           $instance_name awready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}WID      wid      Output $id_width   $instance_name wid
+	fpga_interfaces::add_interface_port $iface_name  ${z}WDATA    wdata    Output $data_width $instance_name wdata
+	fpga_interfaces::add_interface_port $iface_name  ${z}WSTRB    wstrb    Output $strb_width $instance_name wstrb
+	fpga_interfaces::add_interface_port $iface_name  ${z}WLAST    wlast    Output 1           $instance_name wlast
+	fpga_interfaces::add_interface_port $iface_name  ${z}WVALID   wvalid   Output 1           $instance_name wvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}WREADY   wready   Input  1           $instance_name wready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}BID      bid      Input  $id_width   $instance_name bid
+	fpga_interfaces::add_interface_port $iface_name  ${z}BRESP    bresp    Input  2           $instance_name bresp
+	fpga_interfaces::add_interface_port $iface_name  ${z}BVALID   bvalid   Input  1           $instance_name bvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}BREADY   bready   Output 1           $instance_name bready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARID     arid     Output $id_width   $instance_name arid
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARADDR   araddr   Output $addr_width $instance_name araddr
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARLEN    arlen    Output 4           $instance_name arlen
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARSIZE   arsize   Output 3           $instance_name arsize
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARBURST  arburst  Output 2           $instance_name arburst
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARLOCK   arlock   Output 2           $instance_name arlock
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARCACHE  arcache  Output 4           $instance_name arcache
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARPROT   arprot   Output 3           $instance_name arprot
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARVALID  arvalid  Output 1           $instance_name arvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}ARREADY  arready  Input  1           $instance_name arready
+
+	fpga_interfaces::add_interface_port $iface_name  ${z}RID      rid      Input  $id_width   $instance_name rid
+	fpga_interfaces::add_interface_port $iface_name  ${z}RDATA    rdata    Input  $data_width $instance_name rdata
+	fpga_interfaces::add_interface_port $iface_name  ${z}RRESP    rresp    Input  2           $instance_name rresp
+	fpga_interfaces::add_interface_port $iface_name  ${z}RLAST    rlast    Input  1           $instance_name rlast
+	fpga_interfaces::add_interface_port $iface_name  ${z}RVALID   rvalid   Input  1           $instance_name rvalid
+	fpga_interfaces::add_interface_port $iface_name  ${z}RREADY   rready   Output 1           $instance_name rready
+
+	set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    }
+}
+
+proc elab_F2SDRAM {device_family} {
+    f2sdram::init_registers
+
+    set instance_name f2sdram
+    set atom_name hps_interface_fpga2sdram
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+
+    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+
+    set use_fast_sim_model [expr { [string compare [get_parameter_value quartus_ini_hps_ip_fast_f2sdram_sim_model] "true" ] == 0 }]
+    set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}]
+        #newly added
+    set width_list [get_parameter_value F2SDRAM_Width]
+    set rows [llength $width_list]
+    if {$rows > 0} {
+	# TODO: move outside of 'if' once registers are rendered
+	
+
+	set type_list [get_parameter_value F2SDRAM_Type]
+	for {set i 0} {${i} < $rows} {incr i} {
+	    set width [lindex $width_list $i]
+	    set type_choice  [lindex $type_list  $i]
+
+	    set type "axi"
+	    set type_id 0
+	    if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } {
+		set type "avalon"
+		set type_id 1
+	    } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } {
+		set type "avalon"
+		set type_id 2
+	    } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } {    
+		set type "avalon"                                              
+		set type_id 3                                              
+	    }
+                                                                    
+	    set sim_is_synth [expr !$use_fast_sim_model]
+	    
+	    # To make sure bonding_out_signal only being added once even thought there are more than one f2sdram
+   	    if {$i == 0 } {
+		set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] 
+	    } else {
+		set bonding_out_signal 0
+	    }
+
+	    f2sdram::add_port registers $i $type_id $width $instance_name $sim_is_synth $bonding_out_signal
+	}
+        f2sdram::add_sdc $use_fast_sim_model
+        fpga_interfaces::set_property IMPLEMENT_F2SDRAM_MEMORY_BACKED_SIM $use_fast_sim_model
+	
+    }
+    # write the registers out
+    f2sdram::render_registers registers $instance_name
+}
+
+proc elab_clocks_resets {device_family} {
+    set instance_name clocks_resets
+    set atom_name hps_interface_clocks_resets
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    
+    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+
+    fpga_interfaces::add_interface          h2f_reset             reset    Output
+    fpga_interfaces::add_interface_port     h2f_reset  h2f_rst_n  reset_n  Output  1     $instance_name
+    fpga_interfaces::set_interface_property h2f_reset  synchronousEdges  none
+    fpga_interfaces::set_interface_property h2f_reset associatedResetSinks none
+
+    if [is_enabled S2FCLK_COLDRST_Enable] {    
+	fpga_interfaces::add_interface          h2f_cold_reset      reset               Output
+	fpga_interfaces::add_interface_port     h2f_cold_reset      h2f_cold_rst_n      reset_n  Output  1     $instance_name
+	fpga_interfaces::set_interface_property h2f_cold_reset      synchronousEdges    none
+	fpga_interfaces::set_interface_property h2f_cold_reset      associatedResetSinks none
+    }
+
+    if [is_enabled F2SCLK_COLDRST_Enable] {
+	fpga_interfaces::add_interface          f2h_cold_reset_req  reset               Input
+	fpga_interfaces::add_interface_port     f2h_cold_reset_req  f2h_cold_rst_req_n  reset_n  Input   1     $instance_name
+	fpga_interfaces::set_interface_property f2h_cold_reset_req  synchronousEdges    none
+	fpga_interfaces::set_interface_property h2f_reset associatedResetSinks f2h_cold_reset_req
+	if [is_enabled S2FCLK_COLDRST_Enable] {
+	    fpga_interfaces::set_interface_property h2f_cold_reset      associatedResetSinks f2h_cold_reset_req
+	}
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_cold_rst_req_n" 1 1 0:0 1
+    }
+
+    if [is_enabled S2FCLK_PENDINGRST_Enable] {
+	fpga_interfaces::add_interface          h2f_warm_reset_handshake conduit               Output
+	fpga_interfaces::add_interface_port     h2f_warm_reset_handshake h2f_pending_rst_req_n h2f_pending_rst_req_n  Output  1     $instance_name
+	fpga_interfaces::add_interface_port     h2f_warm_reset_handshake f2h_pending_rst_ack_n f2h_pending_rst_ack_n  Input   1     $instance_name f2h_pending_rst_ack
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_pending_rst_ack" 1 1 0:0 1
+    }
+	
+    if [is_enabled F2SCLK_DBGRST_Enable] {
+	fpga_interfaces::add_interface          f2h_debug_reset_req                     reset    Input
+	fpga_interfaces::add_interface_port     f2h_debug_reset_req  f2h_dbg_rst_req_n  reset_n  Input  1     $instance_name
+	fpga_interfaces::set_interface_property f2h_debug_reset_req  synchronousEdges   none
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_dbg_rst_req_n" 1 1 0:0 1
+    }
+
+    if [is_enabled F2SCLK_WARMRST_Enable] {
+	fpga_interfaces::add_interface          f2h_warm_reset_req                      reset    Input
+	fpga_interfaces::add_interface_port     f2h_warm_reset_req  f2h_warm_rst_req_n  reset_n  Input  1     $instance_name
+	fpga_interfaces::set_interface_property f2h_warm_reset_req  synchronousEdges    none
+
+	if [is_enabled F2SCLK_COLDRST_Enable] {
+	    fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req f2h_cold_reset_req}
+	} else {
+	    fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req}
+	}
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_warm_rst_req_n" 1 1 0:0 1
+    }
+
+    if [is_enabled S2FCLK_USER0CLK_Enable] {
+	fpga_interfaces::add_interface          h2f_user0_clock                 clock  Output
+	fpga_interfaces::add_interface_port     h2f_user0_clock  h2f_user0_clk  clk    Output  1     $instance_name
+	set frequency [get_parameter_value S2FCLK_USER0CLK_FREQ]
+	set frequency [expr {$frequency * [MHZ_TO_HZ]}]
+	fpga_interfaces::set_interface_property h2f_user0_clock clockRateKnown true
+	fpga_interfaces::set_interface_property h2f_user0_clock clockRate      $frequency
+	add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user0_clk"
+    }
+    
+    if [is_enabled S2FCLK_USER1CLK_Enable] {
+	fpga_interfaces::add_interface          h2f_user1_clock                 clock  Output
+	fpga_interfaces::add_interface_port     h2f_user1_clock  h2f_user1_clk  clk    Output  1     $instance_name
+	set frequency [get_parameter_value S2FCLK_USER1CLK_FREQ]
+	set frequency [expr {$frequency * [MHZ_TO_HZ]}]
+	fpga_interfaces::set_interface_property h2f_user1_clock clockRateKnown true
+	fpga_interfaces::set_interface_property h2f_user1_clock clockRate      $frequency
+	add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user1_clk"
+    }
+	
+    set_parameter_property S2FCLK_USER2CLK enabled false
+	
+    if [is_enabled F2SCLK_PERIPHCLK_Enable] {    
+	fpga_interfaces::add_interface          f2h_periph_ref_clock                      clock  Input
+	fpga_interfaces::add_interface_port     f2h_periph_ref_clock  f2h_periph_ref_clk  clk    Input  1     $instance_name
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_periph_ref_clk" 1 0
+    }
+
+	
+    if [is_enabled F2SCLK_SDRAMCLK_Enable] {
+	fpga_interfaces::add_interface          f2h_sdram_ref_clock                     clock  Input
+	fpga_interfaces::add_interface_port     f2h_sdram_ref_clock  f2h_sdram_ref_clk  clk    Input  1     $instance_name
+    } else {
+	fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_sdram_ref_clk" 1 0
+    }
+}
+
+# Elaborate peripheral request interfaces for the fpga and
+# the clk/reset per pair
+# TODO: Make sure the DMA RTL contains the wrapper
+proc elab_DMA {device_family} {
+    set instance_name dma
+    set atom_name hps_interface_dma
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    
+    set can_message 0
+    set available_list [get_parameter_value DMA_Enable]
+    if {[llength $available_list] > 0} {
+	set dma_used 0
+	set periph_id 0
+	foreach entry $available_list {
+	    if {[string compare $entry "Yes" ] == 0} {
+		elab_DMA_entry $periph_id $instance_name
+		set dma_used 1
+		if {$periph_id >= 4} {
+		    set can_message 1
+		}
+	    }
+	    incr periph_id
+	}
+	if $dma_used {
+	    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+	}
+	if $can_message {
+	    send_message info "DMA Peripheral Request Interfaces 4-7 may be consumed by an HPS CAN Controller"
+	}
+    }
+}
+
+proc elab_DMA_make_conduit_name {periph_id} {
+    return "f2h_dma_req${periph_id}"
+}
+
+proc elab_DMA_entry {periph_id instance_name} {
+    set iname [elab_DMA_make_conduit_name $periph_id]
+    set atom_signal_prefix "channel${periph_id}"
+    fpga_interfaces::add_interface      $iname conduit Output
+    fpga_interfaces::add_interface_port $iname "${iname}_req"    "dma_req"    Input  1  $instance_name  ${atom_signal_prefix}_req
+    fpga_interfaces::add_interface_port $iname "${iname}_single" "dma_single" Input  1  $instance_name  ${atom_signal_prefix}_single
+    fpga_interfaces::add_interface_port $iname "${iname}_ack"    "dma_ack"    Output 1  $instance_name  ${atom_signal_prefix}_xx_ack
+}
+
+
+proc elab_emac_ptp {device_family} {
+    # added for case http://fogbugz.altera.com/default.asp?307450 
+    for {set i 0} {$i < 2} {incr i} {
+        set emac_fpga_enabled   false
+        set emac_io_enabled     false
+
+        set emac_pin_mux_value [get_parameter_value EMAC${i}_PinMuxing]
+        set emac_ptp           [get_parameter_value EMAC${i}_PTP]
+
+        if {[string compare $emac_pin_mux_value [FPGA_MUX_VALUE]] == 0} {
+            set emac_fpga_enabled true
+        }
+        if {[string compare $emac_pin_mux_value "HPS I/O Set 0"]   == 0} {
+            set emac_io_enabled   true
+        }
+        
+        set_parameter_property   EMAC${i}_PTP  enabled        $emac_io_enabled
+        
+        if {$emac_io_enabled && $emac_ptp } {
+            set instance_name  peripheral_emac${i}
+            set atom_name      hps_interface_peripheral_emac
+            set wys_atom_name  arriav_hps_interface_peripheral_emac
+            set location       [locations::get_fpga_location $instance_name $atom_name]
+            
+            set iface_name    "emac${i}"
+
+            fpga_interfaces::add_interface       $iface_name conduit input
+            fpga_interfaces::add_interface_port  $iface_name emac${i}_ptp_aux_ts_trig_i  ptp_aux_ts_trig_i  Input  1  $instance_name ptp_aux_ts_trig_i
+            fpga_interfaces::add_interface_port  $iface_name emac${i}_ptp_pps_o          ptp_pps_o          Output 1  $instance_name ptp_pps_o
+
+            
+            fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+        }
+        
+    }
+}
+
+proc elab_INTERRUPTS {device_family logical_view} {
+    set instance_name interrupts
+    set atom_name hps_interface_interrupts
+    set location [locations::get_fpga_location $instance_name $atom_name]
+    set any_interrupt_enabled 0
+
+    ##### F2H #####
+    if [is_enabled F2SINTERRUPT_Enable] {
+	set any_interrupt_enabled 1
+	set iname "f2h_irq"
+	set pname "f2h_irq"
+	if { $logical_view == 0 } {
+	    fpga_interfaces::add_interface      "${iname}0"  interrupt receiver
+	    fpga_interfaces::add_interface_port "${iname}0" "${pname}_p0"    irq Input 32
+	    fpga_interfaces::set_port_fragments "${iname}0" "${pname}_p0" "${instance_name}:irq(31:0)" 
+	    
+	    fpga_interfaces::add_interface      "${iname}1"  interrupt receiver
+	    fpga_interfaces::add_interface_port "${iname}1" "${pname}_p1"    irq Input 32
+	    fpga_interfaces::set_port_fragments "${iname}1" "${pname}_p1" "${instance_name}:irq(63:32)"
+	}
+    }
+
+    ##### H2F #####
+    load_h2f_interrupt_table\
+	functions_by_group width_by_function inverted_by_function
+
+    set interrupt_groups [list_h2f_interrupt_groups]
+    foreach group $interrupt_groups {
+	set parameter "S2FINTERRUPT_${group}_Enable"
+	set enabled [is_enabled $parameter]
+
+	if {!$enabled} {
+	    continue
+	}
+	set any_interrupt_enabled 1
+	
+	foreach function $functions_by_group($group) {
+	    set width 1
+	    if {[info exists width_by_function($function)]} {
+		set width $width_by_function($function)
+	    }
+	    
+	    set suffix ""
+	    set inverted [info exists inverted_by_function($function)]
+	    if {$inverted} {
+		set suffix "_n"
+	    }
+	    
+	    #skip fpga_interfaces interrupt declaration for uart 
+	    if { ($logical_view == 1) && (
+	         $function == "uart0" || 
+	         $function == "uart1" )} {
+	    	    continue
+	    }
+	    
+	    set prefix    "h2f_${function}_"
+	    set interface "${prefix}interrupt"
+	    set port      "${prefix}irq"
+	    
+	    if {$width > 1} { ;# for buses, use index in interface/port names
+		for {set i 0} {$i < $width} {incr i} {
+		    set indexed_interface "${interface}${i}"
+		    set indexed_port      "${port}${i}${suffix}"
+		    fpga_interfaces::add_interface\
+			$indexed_interface interrupt sender
+		    fpga_interfaces::add_interface_port\
+			$indexed_interface $indexed_port irq Output 1\
+			$instance_name $indexed_port
+		}
+	    } else {
+		set port "$port${suffix}"
+		fpga_interfaces::add_interface\
+		    $interface interrupt sender
+		fpga_interfaces::add_interface_port\
+		    $interface $port irq Output 1  $instance_name $port
+	    }
+	}
+    }
+    
+    if {$any_interrupt_enabled}  {
+	set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+        fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    }
+}
+
+proc elab_TEST {device_family} {
+    set parameter_enabled [expr {[string compare [get_parameter_value TEST_Enable] "true" ] == 0}]
+    set ini_enabled       [expr {[string compare [get_parameter_value quartus_ini_hps_ip_enable_test_interface] "true" ] == 0}]
+    
+    if {$parameter_enabled && $ini_enabled} {
+	set instance_name test_interface
+	set atom_name hps_interface_test
+	set location [locations::get_fpga_location $instance_name $atom_name]
+	
+	set iname "test"
+	set z     "test_"
+	
+	set data [get_parameter_value test_iface_definition]
+	
+	fpga_interfaces::add_interface      $iname  conduit input
+	foreach {port width dir} $data {
+	    fpga_interfaces::add_interface_port $iname "${z}${port}" $port $dir $width $instance_name $port
+	}
+
+	set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+    }
+}
+
+# TODO: Mode usage data
+proc elab_FPGA_Peripheral_Signals {device_family} {
+    # disable and hide all parameters related to fpga outputs
+    set emac0_fpga [get_parameter_value quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface]
+    set lssis_fpga [get_parameter_value quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces]
+    set all_fpga   "true"
+
+    set peripherals [list_peripheral_names]
+    foreach peripheral $peripherals {
+	if { [string compare $peripheral "SDIO" ] == 0 } {
+	    continue
+	}
+	set visible false
+	if {[string compare $all_fpga "true" ] == 0} {
+	    set visible true
+	} elseif {[string compare $emac0_fpga "true" ] == 0 && [string compare -nocase $peripheral "emac0"] == 0} {
+	    set visible true
+	} elseif {[string compare $lssis_fpga "true" ] == 0 && [is_peripheral_low_speed_serial_interface $peripheral_name]} {
+	    set visible true
+	}
+	if {[string compare -nocase $peripheral "emac0" ] == 0 || [string compare -nocase $peripheral "emac1" ] == 0} {
+	    set visible true
+	}
+	set clocks [get_peripheral_fpga_output_clocks $peripheral]
+	foreach clock $clocks {
+	    set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock]
+	    set_parameter_property $parameter enabled  false
+	    set_parameter_property $parameter visible  $visible
+	    set clock_output_set($clock) 1
+	}
+
+	set clocks [get_peripheral_fpga_input_clocks $peripheral]
+	foreach clock $clocks {
+	    set clock_input_set($clock) 1
+	}
+    }
+
+    array set fpga_ifaces [get_parameter_value DB_periph_ifaces]
+    array set iface_ports [get_parameter_value DB_iface_ports]
+    array set port_pins   [get_parameter_value DB_port_pins]
+    foreach peripheral_name $fpga_ifaces([ORDERED_NAMES]) { ;# Peripherals
+	set pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name]
+	set pin_mux_value  [get_parameter_value    $pin_mux_param_name]
+	set allowed_ranges [get_parameter_property $pin_mux_param_name allowed_ranges]
+
+	if {[string compare $pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $allowed_ranges [FPGA_MUX_VALUE]] != -1} {
+	    funset peripheral
+	    array set peripheral $fpga_ifaces($peripheral_name)
+	    funset interfaces
+	    array set interfaces $peripheral(interfaces)
+	    
+	    set instance_name [invent_peripheral_instance_name $peripheral_name]
+
+	    foreach interface_name $interfaces([ORDERED_NAMES]) { ;# Interfaces
+		funset interface
+		array set interface $interfaces($interface_name)
+		fpga_interfaces::add_interface $interface_name $interface(type) $interface(direction)
+		foreach {property_key property_value} $interface(properties) {
+		    fpga_interfaces::set_interface_property $interface_name $property_key $property_value
+		}
+		#send_message info "NEA: peripheral_name $peripheral_name interface_name $interface_name "
+		
+		if { [string match "EMAC?" $peripheral_name] && [string match  "*x_reset" $interface_name ] } {
+		    fpga_interfaces::set_interface_property $interface_name associatedResetSinks none
+		}
+
+		foreach {meta_property} [array names interface] {
+		    # Meta Property if leading with an @
+		    if {[string compare [string index ${meta_property} 0] "@"] == 0} {
+			fpga_interfaces::set_interface_meta_property $interface_name [string replace ${meta_property} 0 0] $interface($meta_property)
+		    }
+		}
+
+		set once_per_clock 1
+		funset ports
+		array set ports $iface_ports($interface_name)
+		foreach port_name $ports([ORDERED_NAMES]) { ;# Ports
+		    funset port
+		    array set port $ports($port_name)
+		    
+		    # TODO: determine width based on pins available via mode
+		    set width [calculate_port_width $port_pins($port_name)]
+
+		    fpga_interfaces::add_interface_port $interface_name $port_name $port(role) $port(direction) $width $instance_name $port(atom_signal_name)
+		    
+		    set frequency 0
+		    # enable and show clock frequency parameters for outputs
+		    if {[info exists clock_output_set($interface_name)]} {
+			set parameter [form_peripheral_fpga_output_clock_frequency_parameter $interface_name]
+			set_parameter_property $parameter enabled  true
+			set frequency [get_parameter_value $parameter]
+			set frequency [expr {$frequency * [MHZ_TO_HZ]}]
+			fpga_interfaces::set_interface_property $interface_name clockRateKnown true
+			fpga_interfaces::set_interface_property $interface_name clockRate      $frequency
+		    }
+		    
+		    if {[string compare -nocase $interface(type) "clock"] == 0 && $once_per_clock} {
+			set once_per_clock 0
+			add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|[string tolower $port(atom_signal_name)]"
+		    }
+		}
+	    }
+	    
+	    # device-specific atom
+	    set atom_name     $peripheral(atom_name)
+	    set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name]
+	    set location [locations::get_fpga_location $peripheral_name $atom_name]
+
+	    fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location
+	}
+    }
+}
+
+# derives the WYS (device family-specific) atom name from the generic one
+proc generic_atom_to_wys_atom {device_family atom_name} {
+    # TODO: base this on a table of data instead of on code
+    set result ""
+    if {[check_device_family_equivalence $device_family CYCLONEV]} {
+	set result "cyclonev_${atom_name}"
+    } elseif {[check_device_family_equivalence $device_family ARRIAV]} {
+	set result "arriav_${atom_name}"
+		}
+    return $result
+}
+
+# invents an instance name from the peripheral's name
+# assumes that the instance name is the same across a peripheral
+proc invent_peripheral_instance_name {peripheral_name} {
+    return "peripheral_[string tolower $peripheral_name]"
+}
+
+# TODO: do width calculation at db load time so we don't do it every elaboration!
+#       then make it accessible by a mode to width array for every peripheral with fpga periph interface
+# TODO: also validate the static data, checking if the mode signals make sense aka only contiguous, 0-indexed mappings
+proc calculate_port_width {pin_array_string} {
+    array set pins $pin_array_string
+    # TODO: -do we need to be able to support ports that don't start with pins at 0?
+    #       -e.g. pins D0-D7 are indexed 0-7. if want D4-D7, can we do indexes 4-7?
+    #       -for now, no!
+    set bit_index 0
+    while {[info exists pins($bit_index)]} {
+	incr bit_index
+    }
+    return $bit_index
+}
+
+proc pin_to_bank {pin} {
+    set io_index [string first "IO" $pin]
+    return [string range $pin 0 [expr {$io_index - 1}]]
+}
+
+proc sort_pins {pins} {
+    set pin_suffixes [list]
+    foreach pin $pins {
+	set io_index [string first "IO" $pin]
+	set suffix_start [expr {$io_index + 2}]
+	set length [string length $pin]
+	set suffix [string range $pin $suffix_start [expr {$length - 1}]]
+	lappend pin_suffixes $suffix
+    }
+    set result [list]
+    set indices [lsort-indices -increasing -integer $pin_suffixes]
+    foreach index $indices {
+	lappend result [lindex $pins $index]
+    }
+    return $result
+}
+
+proc set_peripheral_pin_muxing_description {peripheral_name pin_muxing_description mode_description} {
+    set parameter "[string toupper $peripheral_name]_PinMuxing"
+    set_display_item_property $parameter DESCRIPTION $pin_muxing_description
+
+    set parameter "[string toupper $peripheral_name]_Mode"
+    set_display_item_property $parameter DESCRIPTION $mode_description
+}
+
+# Expects same set of keys between both parameters
+proc create_pin_muxing_description_table_html {signals_by_option_str pins_by_option_str} {
+    array set pins_by_option $pins_by_option_str
+
+    set options [list]
+    foreach {option signals} $signals_by_option_str {
+	lappend options $option
+
+	set pins $pins_by_option($option)
+	
+	foreach signal $signals pin $pins {
+	    set key "${option}.${signal}"
+	    set pins_by_option_and_signal($key) $pin
+	    set signal_set($signal) 1
+	}
+    }
+    
+    set sorted_signals [lsort -increasing -ascii [array names signal_set]]
+    set sorted_options [lsort -increasing -ascii $options]
+    
+    set ALIGN_CENTER {align="center"}
+
+    set html "<table border=\"1\"><tr><td></td>" ;# start of table, first row cell empty for signal column
+    foreach option $sorted_options {
+	set html "${html}<th $ALIGN_CENTER>${option}</th>"
+    }
+    set html "${html}</tr>"
+    foreach signal $sorted_signals {
+	set html "${html}<tr><th $ALIGN_CENTER>${signal}</th>" ;# new row w/ first cell (header) being the signal name
+	foreach option $sorted_options {
+	    set key "${option}.${signal}"
+	    if {[info exists pins_by_option_and_signal($key)]} {
+		set pin $pins_by_option_and_signal($key)
+	    } else {
+		set pin ""
+	    }
+	    set html "${html}<td $ALIGN_CENTER>${pin}</td>"
+	}
+	set html "${html}</tr>"
+    }
+    set html "${html}</table>"
+    return $html
+}
+
+proc create_mode_description_table_html {signals_by_mode_str} {
+    set modes [list]
+    
+    foreach {mode signals} $signals_by_mode_str {
+	lappend modes $mode
+	foreach signal $signals {
+	    set key "${mode}.${signal}"
+	    set membership_by_mode_and_signal($key) 1
+	    set signal_set($signal) 1
+	}
+    }
+    
+    set sorted_signals [lsort -increasing -ascii [array names signal_set]]
+    set sorted_modes   [lsort -increasing -ascii $modes]
+    
+    set ALIGN_CENTER {align="center"}
+    
+    set html "<table border=\"1\"><tr><td></td>" ;# start of table, first row cell empty for signal column
+    foreach mode $sorted_modes {
+	set html "${html}<th $ALIGN_CENTER>${mode}</th>"
+    }
+    set html "${html}</tr>"
+    foreach signal $sorted_signals {
+	set html "${html}<tr><th $ALIGN_CENTER>${signal}</th>" ;# new row w/ first cell (header) being the signal name
+
+	foreach mode $sorted_modes {
+	    set key "${mode}.${signal}"
+	    if {[info exists membership_by_mode_and_signal($key)]} {
+		set member_marker "X"
+	    } else {
+		set member_marker ""
+	    }
+	    set html "${html}<td $ALIGN_CENTER>${member_marker}</td>"
+	}
+	set html "${html}</tr>"
+    }
+    set html "${html}</table>"
+    return $html
+}
+
+proc get_quartus_edition {} {
+    set code {
+	set version ""
+	regexp {([a-zA-Z]+) (Edition|Version)$} $quartus(version) total version
+	return $version
+    }
+    set safe_code [string map {\n ; \t ""} $code]
+    set package_name "advanced_device"
+    set result [lindex [run_quartus_tcl_command "${package_name}:${safe_code}"] 0]
+    return $result
+}
+
+proc is_soc_device {device} {
+    return [::pin_mux_db::verify_soc_device $device]
+}
+
+proc set_peripheral_pin_muxing_descriptions {peripherals_ref} {
+    upvar 1 $peripherals_ref peripherals
+
+    foreach peripheral_name [array names peripherals] {
+	set signals_by_option [list]
+	set pins_by_option    [list]
+	
+	funset peripheral
+	array set peripheral $peripherals($peripheral_name)
+	funset pin_sets
+	array set pin_sets $peripheral(pin_sets)
+	
+	foreach pin_set_name [array names pin_sets] {
+	    funset pin_set
+	    array set pin_set $pin_sets($pin_set_name)
+	    set signals $pin_set(signals)
+	    lappend signals_by_option $pin_set_name $signals
+	    set pins $pin_set(pins)
+	    lappend pins_by_option $pin_set_name $pins
+	}
+	set signals_by_mode $peripheral(signals_by_mode)
+
+	set table_html [create_pin_muxing_description_table_html $signals_by_option $pins_by_option]
+	set pin_muxing_description ""
+	
+	set table_html [create_mode_description_table_html $signals_by_mode]
+	set mode_description "Signal Membership Per Mode Usage Option: <br />${table_html}"
+	set_peripheral_pin_muxing_description $peripheral_name $pin_muxing_description $mode_description
+    }
+}
+
+# Add pin muxing details to soc_io peripheral/signal data
+add_storage_parameter pin_muxing {}
+add_storage_parameter pin_muxing_check ""
+proc ensure_pin_muxing_data {device_family} {
+    if {[check_device_family_equivalence $device_family [get_module_property SUPPORTED_DEVICE_FAMILIES]] == 0} {
+	return
+    }
+    
+    set device [get_device]
+
+    if {![is_soc_device $device]} {
+	send_message error "Selected device '${device}' is not an SoC device. Please choose a valid SoC device to use the Hard Processor System."
+	return
+    }
+
+    set device_configuration "${device_family}+${device}"
+
+  set old_device_configuration [get_parameter_value pin_muxing_check]
+  if {$old_device_configuration == $device_configuration} {
+	return
+  }
+    
+    set load_rc [::pin_mux_db::load $device]
+    if {!$load_rc} {                           
+	send_message error "The pin information for the Hard Processor System could not be determined. Please check whether your edition of Quartus Prime supports the selected device."
+	return          
+    }              
+    locations::load $device    
+                                                      
+    load_peripherals_pin_muxing_model pin_muxing_peripherals
+    set_peripheral_pin_muxing_descriptions pin_muxing_peripherals
+                                   
+    set gpio_pins [::pin_mux_db::get_gpio_pins]
+    set loanio_pins [::pin_mux_db::get_loan_io_pins]        
+    set customer_pin_names [::pin_mux_db::get_customer_pin_names]
+    set hlgpi_pins [::pin_mux_db::get_hlgpi_pins]
+                                                     
+    set pin_muxing [list [array get pin_muxing_peripherals] $gpio_pins $loanio_pins $customer_pin_names $hlgpi_pins]
+    set_parameter_value pin_muxing $pin_muxing
+    set_parameter_value pin_muxing_check $device_configuration
+      
+    ####  update pin_muxing data to use in java GUI  ####
+        set pinmux_peripherals [array get pin_muxing_peripherals]
+        array set periph_key_value $pinmux_peripherals  
+        
+        foreach {key value} [array get periph_key_value] {
+        	set_parameter_value JAVA_${key}_DATA "$key \{$value\}"            
+        }                                                   
+}  
+ 
+proc get_device {} {
+
+    set device_name [get_parameter_value device_name]
+    return $device_name
+}
+
+proc construct_hps_parameter_map {} {
+    set parameters [get_parameters]
+    foreach parameter $parameters {
+	set value [get_parameter_value $parameter]
+	set result($parameter) $value
+    }
+    return [array get result]
+}
+
+################################################################################
+# Implements interface of util/pin_mux.tcl
+#                                                          
+namespace eval hps_ip_pin_muxing_model {
+################################################################################
+    proc get_peripherals_model {} {
+	set pin_muxing [get_parameter_value pin_muxing]
+	set peripherals [lindex $pin_muxing 0]
+	return $peripherals
+    }
+    proc get_emac0_fpga_ini {} {
+ 	return [is_enabled quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface]
+    }
+    proc get_lssis_fpga_ini {} {
+ 	return [is_enabled quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces]
+    }
+    proc get_all_fpga_ini {} {
+ 	return [is_enabled quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces] 
+    }
+    proc get_peripheral_pin_muxing_selection {peripheral_name} {
+	set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name]
+	set selection [get_parameter_value $pin_muxing_param_name]
+	return $selection
+    }
+    proc get_peripheral_mode_selection {peripheral_name} {
+	set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral_name]
+	set selection [get_parameter_value $mode_param_name]
+	return $selection
+    }
+    proc get_gpio_pins {} {
+	set pin_muxing [get_parameter_value pin_muxing] 
+	set pins [lindex $pin_muxing 1] 
+	return $pins
+    }
+    proc get_loanio_pins {} {
+	set pin_muxing [get_parameter_value pin_muxing]
+	set pins [lindex $pin_muxing 2]
+	return $pins
+    }
+    proc get_customer_pin_names {} {
+	set pin_muxing [get_parameter_value pin_muxing]                                                                
+	set pins [lindex $pin_muxing 3]
+	return $pins
+    }
+    proc get_hlgpi_pins {} {
+	set pin_muxing [get_parameter_value pin_muxing]                                                                
+	set pins [lindex $pin_muxing 4]
+	return $pins
+    }
+    proc get_unsupported_peripheral {peripheral_name} {
+	set device_family [get_parameter_value hps_device_family]
+	set skip 0
+	if {[check_device_family_equivalence $device_family ARRIAV]} {
+            foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] {
+                if {[string compare $excluded_peripheral $peripheral_name] == 0} { 
+                    set skip 1 
+                }
+            }
+        }
+	return $skip
+    }
+}
+
+
+## Add documentation links for user guide and/or release notes
+add_documentation_link "User Guide" https://www.altera.com/products/soc/overview.html
diff --git a/sys/ip/in_split.v b/sys/ip/in_split.v
new file mode 100644
index 0000000..e750ff9
--- /dev/null
+++ b/sys/ip/in_split.v
@@ -0,0 +1,52 @@
+// in_split.v
+
+
+`timescale 1 ps / 1 ps
+module in_split (
+		input  wire        clk,                //  input.clk
+		input  wire        ce,                 //       .ce
+		input  wire        de,                 //       .de
+		input  wire        h_sync,             //       .h_sync
+		input  wire        v_sync,             //       .v_sync
+		input  wire        f,                  //       .f
+		input  wire [23:0] data,               //       .data
+		output wire        vid_clk,            // Output.vid_clk
+		output reg         vid_datavalid,      //       .vid_datavalid
+		output reg  [1:0]  vid_de,             //       .vid_de
+		output reg  [1:0]  vid_f,              //       .vid_f
+		output reg  [1:0]  vid_h_sync,         //       .vid_h_sync
+		output reg  [1:0]  vid_v_sync,         //       .vid_v_sync
+		output reg  [47:0] vid_data,           //       .vid_data
+		output wire        vid_locked,         //       .vid_locked
+		output wire [7:0]  vid_color_encoding, //       .vid_color_encoding
+		output wire [7:0]  vid_bit_width,      //       .vid_bit_width
+		input  wire        clipping,           //       .clipping
+		input  wire        overflow,           //       .overflow
+		input  wire        sof,                //       .sof
+		input  wire        sof_locked,         //       .sof_locked
+		input  wire        refclk_div,         //       .refclk_div
+		input  wire        padding             //       .padding
+	);
+
+	assign vid_bit_width = 0;
+	assign vid_color_encoding = 0;
+	assign vid_locked = 1;
+	assign vid_clk = clk;
+
+	always @(posedge clk) begin
+		reg odd = 0;
+		
+		vid_datavalid <= 0;
+		if(ce) begin
+			vid_de[odd] <= de;
+			vid_f[odd] <= f;
+			vid_h_sync[odd] <= h_sync;
+			vid_v_sync[odd] <= v_sync;
+			if(odd) vid_data[47:24] <= data;
+				else vid_data[23:0] <= data;
+			
+			odd <= ~odd;
+			vid_datavalid <= odd;
+		end
+	end
+endmodule
diff --git a/sys/ip/in_split_hw.tcl b/sys/ip/in_split_hw.tcl
new file mode 100644
index 0000000..403555a
--- /dev/null
+++ b/sys/ip/in_split_hw.tcl
@@ -0,0 +1,104 @@
+# TCL File Generated by Component Editor 17.0
+# Thu Jan 25 18:50:29 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# in_split "Input Splitter" v17.0
+# Sorgelig 2018.01.25.18:50:29
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module in_split
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME in_split
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME "Input Splitter"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point input
+# 
+add_interface input conduit end
+set_interface_property input associatedClock ""
+set_interface_property input associatedReset ""
+set_interface_property input ENABLED true
+set_interface_property input EXPORT_OF ""
+set_interface_property input PORT_NAME_MAP ""
+set_interface_property input CMSIS_SVD_VARIABLES ""
+set_interface_property input SVD_ADDRESS_GROUP ""
+
+add_interface_port input clk clk Input 1
+add_interface_port input ce ce Input 1
+add_interface_port input de de Input 1
+add_interface_port input h_sync h_sync Input 1
+add_interface_port input v_sync v_sync Input 1
+add_interface_port input f f Input 1
+add_interface_port input data data Input 24
+
+
+# 
+# connection point Output
+# 
+add_interface Output conduit end
+set_interface_property Output associatedClock ""
+set_interface_property Output associatedReset ""
+set_interface_property Output ENABLED true
+set_interface_property Output EXPORT_OF ""
+set_interface_property Output PORT_NAME_MAP ""
+set_interface_property Output CMSIS_SVD_VARIABLES ""
+set_interface_property Output SVD_ADDRESS_GROUP ""
+
+add_interface_port Output vid_clk vid_clk Output 1
+add_interface_port Output vid_datavalid vid_datavalid Output 1
+add_interface_port Output vid_de vid_de Output 2
+add_interface_port Output vid_f vid_f Output 2
+add_interface_port Output vid_h_sync vid_h_sync Output 2
+add_interface_port Output vid_v_sync vid_v_sync Output 2
+add_interface_port Output vid_data vid_data Output 48
+add_interface_port Output vid_locked vid_locked Output 1
+add_interface_port Output vid_color_encoding vid_color_encoding Output 8
+add_interface_port Output vid_bit_width vid_bit_width Output 8
+add_interface_port Output clipping clipping Input 1
+add_interface_port Output overflow overflow Input 1
+add_interface_port Output sof sof Input 1
+add_interface_port Output sof_locked sof_locked Input 1
+add_interface_port Output refclk_div refclk_div Input 1
+add_interface_port Output padding padding Input 1
+
diff --git a/sys/ip/out_mix.v b/sys/ip/out_mix.v
new file mode 100644
index 0000000..e135b1c
--- /dev/null
+++ b/sys/ip/out_mix.v
@@ -0,0 +1,44 @@
+// out_mix.v
+
+`timescale 1 ps / 1 ps
+module out_mix (
+		input  wire        clk,             // Output.clk
+		output reg         de,              //       .de
+		output reg         h_sync,          //       .h_sync
+		output reg         v_sync,          //       .v_sync
+		output reg  [23:0] data,            //       .data
+		output reg         vid_clk,         //  input.vid_clk
+		input  wire [1:0]  vid_datavalid,   //       .vid_datavalid
+		input  wire [1:0]  vid_h_sync,      //       .vid_h_sync
+		input  wire [1:0]  vid_v_sync,      //       .vid_v_sync
+		input  wire [47:0] vid_data,        //       .vid_data
+		input  wire        underflow,       //       .underflow
+		input  wire        vid_mode_change, //       .vid_mode_change
+		input  wire [1:0]  vid_std,         //       .vid_std
+		input  wire [1:0]  vid_f,           //       .vid_f
+		input  wire [1:0]  vid_h,           //       .vid_h
+		input  wire [1:0]  vid_v            //       .vid_v
+	);
+
+	reg        r_de;
+	reg        r_h_sync;
+	reg        r_v_sync;
+	reg [23:0] r_data;
+	
+	always @(posedge clk) begin
+		vid_clk <= ~vid_clk;
+		
+		if(~vid_clk) begin
+			{r_de,de} <= vid_datavalid;
+			{r_h_sync, h_sync} <= vid_h_sync;
+			{r_v_sync, v_sync} <= vid_v_sync;
+			{r_data, data} <= vid_data;
+		end else begin
+			de <= r_de;
+			h_sync <= r_h_sync;
+			v_sync <= r_v_sync;
+			data <= r_data;
+		end
+	end
+
+endmodule
diff --git a/sys/ip/out_mix_hw.tcl b/sys/ip/out_mix_hw.tcl
new file mode 100644
index 0000000..b388891
--- /dev/null
+++ b/sys/ip/out_mix_hw.tcl
@@ -0,0 +1,97 @@
+# TCL File Generated by Component Editor 17.0
+# Thu Jan 25 06:51:26 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# out_mix "Output Mixer" v1.0
+# Sorgelig 2018.01.25.06:51:26
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module out_mix
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME out_mix
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME "Output Mixer"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point Output
+# 
+add_interface Output conduit end
+set_interface_property Output associatedClock ""
+set_interface_property Output associatedReset ""
+set_interface_property Output ENABLED true
+set_interface_property Output EXPORT_OF ""
+set_interface_property Output PORT_NAME_MAP ""
+set_interface_property Output CMSIS_SVD_VARIABLES ""
+set_interface_property Output SVD_ADDRESS_GROUP ""
+
+add_interface_port Output clk clk Input 1
+add_interface_port Output de de Output 1
+add_interface_port Output h_sync h_sync Output 1
+add_interface_port Output v_sync v_sync Output 1
+add_interface_port Output data data Output 24
+
+
+# 
+# connection point input
+# 
+add_interface input conduit end
+set_interface_property input associatedClock ""
+set_interface_property input associatedReset ""
+set_interface_property input ENABLED true
+set_interface_property input EXPORT_OF ""
+set_interface_property input PORT_NAME_MAP ""
+set_interface_property input CMSIS_SVD_VARIABLES ""
+set_interface_property input SVD_ADDRESS_GROUP ""
+
+add_interface_port input vid_clk vid_clk Output 1
+add_interface_port input vid_datavalid vid_datavalid Input 2
+add_interface_port input vid_h_sync vid_h_sync Input 2
+add_interface_port input vid_v_sync vid_v_sync Input 2
+add_interface_port input vid_data vid_data Input 48
+add_interface_port input underflow underflow Input 1
+add_interface_port input vid_mode_change vid_mode_change Input 1
+add_interface_port input vid_std vid_std Input 2
+add_interface_port input vid_f vid_f Input 2
+add_interface_port input vid_h vid_h Input 2
+add_interface_port input vid_v vid_v Input 2
+
diff --git a/sys/ip/reset_source.v b/sys/ip/reset_source.v
new file mode 100644
index 0000000..1b81394
--- /dev/null
+++ b/sys/ip/reset_source.v
@@ -0,0 +1,50 @@
+// reset_source.v
+
+// This file was auto-generated as a prototype implementation of a module
+// created in component editor.  It ties off all outputs to ground and
+// ignores all inputs.  It needs to be edited to make it do something
+// useful.
+// 
+// This file will not be automatically regenerated.  You should check it in
+// to your version control system if you want to keep it.
+
+`timescale 1 ps / 1 ps
+module reset_source
+(
+	input  wire  clk,        //      clock.clk
+	input  wire  reset_hps,  //  reset_hps.reset
+	output wire  reset_sys,  //  reset_sys.reset
+	output wire  reset_cold, // reset_cold.reset
+	input  wire  cold_req,   //  reset_ctl.cold_req
+	output wire  reset,      //           .reset
+	input  wire  reset_req,  //           .reset_req
+	input  wire  reset_vip,  //           .reset_vip
+	input  wire  warm_req,   //           .warm_req
+	output wire  reset_warm  // reset_warm.reset
+);
+
+assign reset_cold = cold_req;
+assign reset_warm = warm_req;
+
+wire   reset_m    = sys_reset | reset_hps | reset_req;
+assign reset      = reset_m;
+assign reset_sys  = reset_m | reset_vip;
+
+reg  sys_reset = 1;
+always @(posedge clk) begin
+	integer timeout = 0;
+	reg reset_lock = 0;
+
+	reset_lock <= reset_lock | cold_req;
+
+	if(timeout < 2000000) begin
+		sys_reset <= 1;
+		timeout <= timeout + 1;
+		reset_lock <= 0;
+	end
+	else begin 
+		sys_reset <= reset_lock;
+	end
+end
+
+endmodule
diff --git a/sys/ip/reset_source_hw.tcl b/sys/ip/reset_source_hw.tcl
new file mode 100644
index 0000000..cba39f7
--- /dev/null
+++ b/sys/ip/reset_source_hw.tcl
@@ -0,0 +1,152 @@
+# TCL File Generated by Component Editor 17.0
+# Tue Feb 20 07:55:55 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# reset_source "reset_source" v17.0
+# Sorgelig 2018.02.20.07:55:55
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module reset_source
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME reset_source
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME reset_source
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset_hps
+# 
+add_interface reset_hps reset end
+set_interface_property reset_hps associatedClock ""
+set_interface_property reset_hps synchronousEdges NONE
+set_interface_property reset_hps ENABLED true
+set_interface_property reset_hps EXPORT_OF ""
+set_interface_property reset_hps PORT_NAME_MAP ""
+set_interface_property reset_hps CMSIS_SVD_VARIABLES ""
+set_interface_property reset_hps SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_hps reset_hps reset Input 1
+
+
+# 
+# connection point reset_sys
+# 
+add_interface reset_sys reset start
+set_interface_property reset_sys associatedClock ""
+set_interface_property reset_sys associatedDirectReset ""
+set_interface_property reset_sys associatedResetSinks ""
+set_interface_property reset_sys synchronousEdges NONE
+set_interface_property reset_sys ENABLED true
+set_interface_property reset_sys EXPORT_OF ""
+set_interface_property reset_sys PORT_NAME_MAP ""
+set_interface_property reset_sys CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sys SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sys reset_sys reset Output 1
+
+
+# 
+# connection point reset_ctl
+# 
+add_interface reset_ctl conduit end
+set_interface_property reset_ctl associatedClock ""
+set_interface_property reset_ctl associatedReset ""
+set_interface_property reset_ctl ENABLED true
+set_interface_property reset_ctl EXPORT_OF ""
+set_interface_property reset_ctl PORT_NAME_MAP ""
+set_interface_property reset_ctl CMSIS_SVD_VARIABLES ""
+set_interface_property reset_ctl SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_ctl cold_req cold_req Input 1
+add_interface_port reset_ctl reset reset Output 1
+add_interface_port reset_ctl reset_req reset_req Input 1
+add_interface_port reset_ctl warm_req warm_req Input 1
+add_interface_port reset_ctl reset_vip reset_vip Input 1
+
+
+# 
+# connection point reset_warm
+# 
+add_interface reset_warm reset start
+set_interface_property reset_warm associatedClock ""
+set_interface_property reset_warm associatedDirectReset ""
+set_interface_property reset_warm associatedResetSinks ""
+set_interface_property reset_warm synchronousEdges NONE
+set_interface_property reset_warm ENABLED true
+set_interface_property reset_warm EXPORT_OF ""
+set_interface_property reset_warm PORT_NAME_MAP ""
+set_interface_property reset_warm CMSIS_SVD_VARIABLES ""
+set_interface_property reset_warm SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_warm reset_warm reset Output 1
+
+
+# 
+# connection point reset_cold
+# 
+add_interface reset_cold reset start
+set_interface_property reset_cold associatedClock ""
+set_interface_property reset_cold associatedDirectReset ""
+set_interface_property reset_cold associatedResetSinks ""
+set_interface_property reset_cold synchronousEdges NONE
+set_interface_property reset_cold ENABLED true
+set_interface_property reset_cold EXPORT_OF ""
+set_interface_property reset_cold PORT_NAME_MAP ""
+set_interface_property reset_cold CMSIS_SVD_VARIABLES ""
+set_interface_property reset_cold SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_cold reset_cold reset Output 1
+
diff --git a/sys/lpf48k.sv b/sys/lpf48k.sv
new file mode 100644
index 0000000..2a32981
--- /dev/null
+++ b/sys/lpf48k.sv
@@ -0,0 +1,100 @@
+//   low pass filter
+//   Revision 1.00
+// 
+// Copyright (c) 2008 Takayuki Hara.
+// All rights reserved.
+// 
+// Redistribution and use of this source code or any derivative works, are 
+// permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice, 
+//    this list of conditions and the following disclaimer.
+// 2. Redistributions in binary form must reproduce the above copyright 
+//    notice, this list of conditions and the following disclaimer in the 
+//    documentation and/or other materials provided with the distribution.
+// 3. Redistributions may not be sold, nor may they be used in a commercial 
+//    product or activity without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 
+// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//
+//	LPF (cut off 48kHz at 3.58MHz)
+
+module lpf48k #(parameter MSB = 15)
+(
+   input          RESET,
+   input          CLK,
+   input          CE,
+	input          ENABLE,
+
+   input  [MSB:0] IDATA,
+   output [MSB:0] ODATA
+);
+
+wire [7:0] LPF_TAP_DATA[0:71] =
+'{
+	8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09,
+	8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B,
+	8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D,
+	8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
+	8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
+	8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D,
+	8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B,
+	8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09,
+	8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51
+};
+
+reg      [7:0] FF_ADDR = 0;
+reg [MSB+10:0] FF_INTEG = 0;
+wire [MSB+8:0] W_DATA;
+wire           W_ADDR_END;
+
+assign W_ADDR_END = ((FF_ADDR == 71));
+
+reg [MSB:0] OUT;
+
+assign ODATA = ENABLE ? OUT : IDATA;
+
+always @(posedge RESET or posedge CLK) begin
+	if (RESET) FF_ADDR <= 0;
+	else 
+	begin
+		if (CE) begin
+			if (W_ADDR_END) FF_ADDR <= 0;
+				else FF_ADDR <= FF_ADDR + 1'd1;
+		end
+	end
+end
+
+assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA;
+
+always @(posedge RESET or posedge CLK) begin
+	if (RESET) FF_INTEG <= 0;
+	else 
+	begin
+		if (CE) begin
+			if (W_ADDR_END) FF_INTEG <= 0;
+				else FF_INTEG <= FF_INTEG + W_DATA;
+		end
+	end
+end
+
+always @(posedge RESET or posedge CLK) begin
+	if (RESET) OUT <= 0;
+	else
+	begin
+		if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10];
+	end
+end
+
+endmodule
diff --git a/sys/osd.v b/sys/osd.v
new file mode 100644
index 0000000..f6e8915
--- /dev/null
+++ b/sys/osd.v
@@ -0,0 +1,199 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd
+(
+	input         clk_sys,
+
+	input         io_osd,
+	input         io_strobe,
+	input  [15:0] io_din,
+
+	input         clk_video,
+	input  [23:0] din,
+	output [23:0] dout,
+	input         de_in,
+	output reg    de_out
+);
+
+parameter  OSD_COLOR    =  3'd4;
+parameter  OSD_X_OFFSET = 12'd0;
+parameter  OSD_Y_OFFSET = 12'd0;
+
+localparam OSD_WIDTH    = 12'd256;
+localparam OSD_HEIGHT   = 12'd64;
+
+reg osd_enable;
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[4096];
+
+reg        highres = 0;
+reg        info = 0;
+reg  [8:0] infoh;
+reg  [8:0] infow;
+reg [11:0] infox;
+reg [21:0] infoy;
+
+always@(posedge clk_sys) begin
+	reg [11:0] bcnt;
+	reg  [7:0] cmd;
+	reg        has_cmd;
+	reg        old_strobe;
+
+	old_strobe <= io_strobe;
+
+	if(~io_osd) begin
+		bcnt <= 0;
+		has_cmd <= 0;
+		cmd <= 0;
+		if(cmd[7:4] == 4) osd_enable <= cmd[0];
+	end else begin
+		if(~old_strobe & io_strobe) begin
+			if(!has_cmd) begin
+				has_cmd <= 1;
+				cmd <= io_din[7:0];
+				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+				if(io_din[7:4] == 4) begin
+					if(!io_din[0]) highres <= 0;
+					info <= io_din[2];
+					bcnt  <= 0;
+				end
+				// command 0x20: OSDCMDWRITE
+				if(io_din[7:4] == 2) begin
+					if(io_din[3]) highres <= 1;
+					bcnt <= {io_din[3:0], 8'h00};
+				end
+			end else begin
+				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+				if(cmd[7:4] == 4) begin
+					if(bcnt == 0) infox <= io_din[11:0];
+					if(bcnt == 1) infoy <= io_din[11:0];
+					if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
+					if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
+				end
+
+				// command 0x20: OSDCMDWRITE
+				if(cmd[7:4] == 2) osd_buffer[bcnt] <= io_din[7:0];
+
+				bcnt <= bcnt + 1'd1;
+			end
+		end
+	end
+end
+
+reg ce_pix;
+always @(negedge clk_video) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg deD;
+
+	cnt <= cnt + 1;
+	deD <= de_in;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(~deD && de_in) cnt <= 0;
+
+	if(deD && ~de_in) begin
+		pixsz  <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
+		pixcnt <= 0;
+	end
+end
+
+reg  [23:0] h_cnt;
+reg  [21:0] v_cnt;
+reg  [21:0] dsp_width;
+reg  [21:0] dsp_height;
+reg   [7:0] osd_byte; 
+reg  [21:0] osd_vcnt;
+reg  [21:0] fheight;
+
+reg  [21:0] finfoy;
+wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT<<highres);
+
+always @(posedge clk_video) begin
+	reg       deD;
+	reg [1:0] osd_div;
+	reg [1:0] multiscan;
+	
+	if(ce_pix) begin
+
+		deD <= de_in;
+		if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
+
+		// falling edge of de
+		if(!de_in && deD) dsp_width <= h_cnt[21:0];
+
+		// rising edge of de
+		if(de_in && !deD) begin
+			v_cnt <= v_cnt + 1'd1;
+			if(h_cnt > {dsp_width, 2'b00}) begin
+				v_cnt <= 0;
+				dsp_height <= v_cnt;
+
+				if(osd_enable) begin
+					if(v_cnt<320) begin
+						multiscan <= 0;
+						fheight <= hrheight;
+						finfoy <= infoy;
+					end
+					else if(v_cnt<640) begin
+						multiscan <= 1;
+						fheight <= hrheight << 1;
+						finfoy <= infoy << 1;
+					end
+					else if(v_cnt<960) begin
+						multiscan <= 2;
+						fheight <= hrheight + (hrheight<<1);
+						finfoy <= infoy + (infoy << 1);
+					end
+					else begin
+						multiscan <= 3;
+						fheight <= hrheight << 2;
+						finfoy <= infoy << 2;
+					end
+				end
+				else begin
+					fheight <= 0;
+				end
+			end
+			h_cnt <= 0;
+			
+			osd_div <= osd_div + 1'd1;
+			if(osd_div == multiscan) begin
+				osd_div <= 0;
+				osd_vcnt <= osd_vcnt + 1'd1;
+			end
+			if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
+		end
+		
+		osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
+	end
+end
+
+// area in which OSD is being displayed
+wire [21:0] h_osd_start = info ? infox  : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
+wire [21:0] h_osd_end   = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH);
+wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
+wire [21:0] v_osd_end   = v_osd_start + fheight;
+
+wire [21:0] osd_hcnt    = h_cnt[21:0] - h_osd_start + 1'd1;
+
+wire osd_de = osd_enable && fheight &&
+              (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
+              (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
+
+wire osd_pixel = osd_byte[osd_vcnt[2:0]];
+
+reg [23:0] rdout;
+assign dout = rdout;
+									 
+always @(posedge clk_video) begin
+	rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
+                               {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
+                               {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
+	de_out <= de_in;
+end
+
+endmodule
diff --git a/sys/pattern_vg.v b/sys/pattern_vg.v
new file mode 100644
index 0000000..1392e1b
--- /dev/null
+++ b/sys/pattern_vg.v
@@ -0,0 +1,120 @@
+module pattern_vg
+#(
+	parameter B=8, // number of bits per channel
+	X_BITS=13,
+	Y_BITS=13,
+	FRACTIONAL_BITS = 12
+)
+
+(
+	input reset, clk_in,
+	input wire [X_BITS-1:0] x,
+	input wire [Y_BITS-1:0] y,
+	input wire vn_in, hn_in, dn_in,
+	input wire [B-1:0] r_in, g_in, b_in,
+	output reg vn_out, hn_out, den_out,
+	output reg [B-1:0] r_out, g_out, b_out,
+	input wire [X_BITS-1:0] total_active_pix,
+	input wire [Y_BITS-1:0] total_active_lines,
+	input wire [7:0] pattern,
+	input wire [B+FRACTIONAL_BITS-1:0] ramp_step
+);
+	
+reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values
+
+
+//wire bar_0 = y<90;
+wire bar_1 = y>=90 & y<180;
+wire bar_2 = y>=180 & y<270;
+wire bar_3 = y>=270 & y<360;
+wire bar_4 = y>=360 & y<450;
+wire bar_5 = y>=450 & y<540;
+wire bar_6 = y>=540 & y<630;
+wire bar_7 = y>=630 & y<720;
+
+
+wire red_enable = bar_1 | bar_3 | bar_5 | bar_7;
+wire green_enable = bar_2 | bar_3 | bar_6 | bar_7;
+wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7;
+	
+always @(posedge clk_in)
+	begin
+		vn_out <= vn_in;
+		hn_out <= hn_in;
+		den_out <= dn_in;
+	if (reset)
+		ramp_values <= 0;
+	else if (pattern == 8'b0) // no pattern
+	begin
+		r_out <= r_in;
+		g_out <= g_in;
+		b_out <= b_in;
+	end
+	else if (pattern == 8'b1) // border
+	begin
+		if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
+		begin
+			r_out <= 8'hFF;
+			g_out <= 8'hFF;
+			b_out <= 8'hFF;
+		end
+		else	// Double-border (OzOnE)...
+		if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
+		begin
+			r_out <= 8'hD0;
+			g_out <= 8'hB0;
+			b_out <= 8'hB0;
+		end
+		else
+		begin
+			r_out <= r_in;
+			g_out <= g_in;
+			b_out <= b_in;
+		end
+	end
+	else if (pattern == 8'd2) // moireX
+	begin
+		if ((dn_in) && x[0] == 1'b1)
+		begin
+			r_out <= 8'hFF;
+			g_out <= 8'hFF;
+			b_out <= 8'hFF;
+		end
+		else
+		begin
+			r_out <= 8'b0;
+			g_out <= 8'b0;
+			b_out <= 8'b0;
+		end
+	end
+	else if (pattern == 8'd3) // moireY
+	begin
+		if ((dn_in) && y[0] == 1'b1)
+		begin
+			r_out <= 8'hFF;
+			g_out <= 8'hFF;
+			b_out <= 8'hFF;
+		end
+		else
+		begin
+			r_out <= 8'b0;
+			g_out <= 8'b0;
+			b_out <= 8'b0;
+		end
+	end
+	else if (pattern == 8'd4) // Simple RAMP
+	begin
+		r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
+		g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
+		b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
+		
+		if ((x == total_active_pix - 1) && (dn_in))
+			ramp_values <= 0;
+		else if ((x == 0) && (dn_in))
+			ramp_values <= ramp_step;
+		else if (dn_in)
+			ramp_values <= ramp_values + ramp_step;
+	end
+end
+
+endmodule
diff --git a/sys/scandoubler.v b/sys/scandoubler.v
new file mode 100644
index 0000000..46274f5
--- /dev/null
+++ b/sys/scandoubler.v
@@ -0,0 +1,189 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	output            ce_pix_out,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             hb_in,
+	input             vb_in,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output            hb_out,
+	output            vb_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+
+localparam DWIDTH = HALF_DEPTH ? 3 : 7;
+
+assign vs_out = vso[3];
+assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
+
+//Compensate picture shift after HQ2x
+assign vb_out = vbo[2];
+assign hb_out = hbo[6];
+
+reg  [7:0] pix_len = 0;
+wire [7:0] pl = pix_len + 1'b1;
+
+reg ce_x1, ce_x4, ce_x2;
+always @(negedge clk_sys) begin
+	reg old_ce;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz2, pixsz4 = 0;
+
+	old_ce <= ce_pix;
+	if(~&pix_len) pix_len <= pix_len + 1'd1;
+
+	ce_x4 <= 0;
+	ce_x2 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4.
+	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
+		ce_x4 <= 1;
+	end
+
+	if(pl == pixsz2) begin
+		ce_x2 <= 1;
+	end
+
+	if(~old_ce & ce_pix) begin
+		pixsz2 <= {1'b0,  pl[7:1]};
+		pixsz4 <= {2'b00, pl[7:2]};
+		ce_x1 <= 1;
+		ce_x2 <= 1;
+		ce_x4 <= 1;
+		pix_len <= 0;
+	end
+end
+
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4),
+	.inputpixel({b_d,g_d,r_d}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vs_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.hblank(hbo[0]&hbo[4]),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg  [1:0] sd_line;
+reg  [2:0] vbo;
+reg  [6:0] hbo;
+
+reg [DWIDTH:0] r_d;
+reg [DWIDTH:0] g_d;
+reg [DWIDTH:0] b_d;
+
+reg [3:0] vso;
+
+reg req_line_reset;
+always @(posedge clk_sys) begin
+
+	reg [11:0] hs_max,hs_rise;
+	reg [10:0] hcnt;
+	reg [11:0] sd_hcnt;
+	reg [11:0] hde_start, hde_end;
+
+	reg hs, hs2, vs, hb;
+
+	if(ce_x1) begin
+		hs <= hs_in;
+		hb <= hb_in;
+		
+		req_line_reset <= hb_in;
+
+		r_d <= r_in;
+		g_d <= g_in;
+		b_d <= b_in;
+
+		if(hb && !hb_in) begin
+			hde_start <= {hcnt,1'b0};
+			vbo <= {vbo[1:0], vb_in};
+		end
+		if(!hb && hb_in) hde_end <= {hcnt,1'b0};
+
+		// falling edge of hsync indicates start of line
+		if(hs && !hs_in) begin
+			vso <= (vso<<1) | vs_in;
+			hs_max <= {hcnt,1'b1};
+			hcnt <= 0;
+		end else begin
+			hcnt <= hcnt + 1'd1;
+		end
+
+		// save position of rising edge
+		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
+
+		vs <= vs_in;
+		if(vs && ~vs_in) sd_line <= 0;
+	end
+
+	if(ce_x4) begin
+		hs2 <= hs_in;
+		hbo[6:1] <= hbo[5:0];
+
+		// output counter synchronous to input and at twice the rate
+		sd_hcnt <= sd_hcnt + 1'd1;
+
+		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
+		if(sd_hcnt == hs_max) sd_hcnt <= 0;
+
+
+		//prepare to read in advance
+		if(sd_hcnt == (hde_start-2)) begin
+			sd_line <= sd_line + 1'd1;
+		end
+
+		if(sd_hcnt == hde_start) hbo[0] <= 0;
+		if(sd_hcnt == hde_end)   hbo[0] <= 1;
+
+		// replicate horizontal sync at twice the speed
+		if(sd_hcnt == hs_max)  hs_out <= 0;
+		if(sd_hcnt == hs_rise) hs_out <= 1;
+	end
+end
+
+endmodule
diff --git a/sys/sigma_delta_dac.v b/sys/sigma_delta_dac.v
new file mode 100644
index 0000000..d0d6be0
--- /dev/null
+++ b/sys/sigma_delta_dac.v
@@ -0,0 +1,33 @@
+//
+// PWM DAC
+//
+// MSBI is the highest bit number. NOT amount of bits!
+//
+module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1)
+(
+   output reg      DACout, //Average Output feeding analog lowpass
+   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
+   input           CLK,
+   input           RESET
+);
+
+reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
+reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
+reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
+reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
+
+always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
+always @(*) DeltaAdder = DACin + DeltaB;
+always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
+
+always @(posedge CLK or posedge RESET) begin
+   if(RESET) begin
+      SigmaLatch <= 1'b1 << (MSBI+1);
+      DACout <= INV;
+   end else begin
+      SigmaLatch <= SigmaAdder;
+      DACout <= SigmaLatch[MSBI+2] ^ INV;
+   end
+end
+
+endmodule
diff --git a/sys/spdif.v b/sys/spdif.v
new file mode 100644
index 0000000..671dcb2
--- /dev/null
+++ b/sys/spdif.v
@@ -0,0 +1,426 @@
+//-----------------------------------------------------------------
+//                        SPDIF Transmitter
+//                              V0.1
+//                        Ultra-Embedded.com
+//                          Copyright 2012
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: GPL
+// If you would like a version with a more permissive license for
+// use in closed source commercial applications please contact me
+// for details.
+//-----------------------------------------------------------------
+//
+// This file is open source HDL; you can redistribute it and/or 
+// modify it under the terms of the GNU General Public License as 
+// published by the Free Software Foundation; either version 2 of 
+// the License, or (at your option) any later version.
+//
+// This file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public 
+// License along with this file; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//-----------------------------------------------------------------
+// altera message_off 10762
+// altera message_off 10240
+
+module spdif
+
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+    parameter CLK_RATE              = 50000000,
+    parameter AUDIO_RATE            = 48000,
+
+    // Generated params
+    parameter WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*128),
+    parameter ERROR_BASE            = 10000,
+    parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
+)
+
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+    input        clk_i,
+    input        rst_i,
+    input        half_rate,
+
+    // Output
+    output       spdif_o,
+
+    // Audio interface (16-bit x 2 = RL)
+    input [15:0] audio_r,
+    input [15:0] audio_l,
+    output       sample_req_o
+);
+
+reg lpf_ce;
+always @(negedge clk_i) begin
+	reg [3:0] div;
+
+	div <= div + 1'd1;
+	if(div == 13) div <= 0;
+
+	lpf_ce <= !div;
+end
+
+wire [15:0] al, ar;
+
+lpf48k #(15) lpf_l
+(
+   .RESET(rst_i),
+   .CLK(clk_i),
+   .CE(lpf_ce),
+	.ENABLE(1),
+
+   .IDATA(audio_l),
+   .ODATA(al)
+);
+
+lpf48k #(15) lpf_r
+(
+   .RESET(rst_i),
+   .CLK(clk_i),
+   .CE(lpf_ce),
+	.ENABLE(1),
+
+   .IDATA(audio_r),
+   .ODATA(ar)
+);
+
+reg         bit_clk_q;
+
+// Clock pulse generator
+always @ (posedge rst_i or posedge clk_i) begin
+	reg [31:0]  count_q;
+	reg [31:0]  error_q;
+	reg ce;
+
+	if (rst_i) begin
+		count_q   <= 0;
+		error_q   <= 0;
+		bit_clk_q <= 1;
+		ce        <= 0;
+	end
+	else
+	begin
+		if(count_q == WHOLE_CYCLES-1) begin
+			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0];
+				count_q <= 0;
+			end else begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
+				count_q <= count_q + 1;
+			end
+		end else if(count_q == WHOLE_CYCLES) begin
+			count_q <= 0;
+		end else begin
+			count_q <= count_q + 1;
+		end
+
+		bit_clk_q <= 0;
+		if(!count_q) begin
+			ce <= ~ce;
+			if(~half_rate || ce) bit_clk_q <= 1;
+		end
+	end
+end
+
+//-----------------------------------------------------------------
+// Core SPDIF
+//-----------------------------------------------------------------
+
+wire [31:0] sample_i = {ar, al};
+
+spdif_core
+u_core
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+
+    .bit_out_en_i(bit_clk_q),
+
+    .spdif_o(spdif_o),
+
+    .sample_i(sample_i),
+    .sample_req_o(sample_req_o)
+);
+
+endmodule
+
+module spdif_core
+(
+    input           clk_i,
+    input           rst_i,
+
+    // SPDIF bit output enable
+    // Single cycle pulse synchronous to clk_i which drives
+    // the output bit rate.
+    // For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
+    // For 48KHz,   48000×32×2×2 = 6,144,000Hz
+    input           bit_out_en_i,
+
+    // Output
+    output          spdif_o,
+
+    // Audio interface (16-bit x 2 = RL)
+    input [31:0]    sample_i,
+    output reg      sample_req_o
+);
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+reg [15:0]  audio_sample_q;
+reg [8:0]   subframe_count_q;
+
+reg         load_subframe_q;
+reg [7:0]   preamble_q;
+wire [31:0] subframe_w;
+
+reg [5:0]   bit_count_q;
+reg         bit_toggle_q;
+
+reg         spdif_out_q;
+
+reg [5:0]   parity_count_q;
+
+//-----------------------------------------------------------------
+// Subframe Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i )
+begin
+    if (rst_i == 1'b1)
+        subframe_count_q    <= 9'd0;
+    else if (load_subframe_q)
+    begin
+        // 192 frames (384 subframes) in an audio block
+        if (subframe_count_q == 9'd383)
+            subframe_count_q <= 9'd0;
+        else
+            subframe_count_q <= subframe_count_q + 9'd1;
+    end
+end
+
+//-----------------------------------------------------------------
+// Sample capture
+//-----------------------------------------------------------------
+reg [15:0] sample_buf_q;
+
+always @ (posedge rst_i or posedge clk_i )
+begin
+   if (rst_i == 1'b1)
+   begin
+        audio_sample_q      <= 16'h0000;
+        sample_buf_q        <= 16'h0000;
+        sample_req_o        <= 1'b0;
+   end
+   else if (load_subframe_q)
+   begin
+        // Start of frame (first subframe)?
+        if (subframe_count_q[0] == 1'b0)
+        begin
+            // Use left sample
+            audio_sample_q <= sample_i[15:0];
+
+            // Store right sample
+            sample_buf_q <= sample_i[31:16];
+
+            // Request next sample
+            sample_req_o <= 1'b1;
+        end
+        else
+        begin
+            // Use right sample
+            audio_sample_q <= sample_buf_q;
+
+            sample_req_o <= 1'b0;
+        end
+   end
+   else
+        sample_req_o <= 1'b0;
+end
+
+// Timeslots 3 - 0 = Preamble
+assign subframe_w[3:0] = 4'b0000;
+
+// Timeslots 7 - 4 = 24-bit audio LSB
+assign subframe_w[7:4] = 4'b0000;
+
+// Timeslots 11 - 8 = 20-bit audio LSB
+assign subframe_w[11:8] = 4'b0000;
+
+// Timeslots 27 - 12 = 16-bit audio
+assign subframe_w[27:12] = audio_sample_q;
+
+// Timeslots 28 = Validity
+assign subframe_w[28] = 1'b0; // Valid
+
+// Timeslots 29 = User bit
+assign subframe_w[29] = 1'b0;
+
+// Timeslots 30 = Channel status bit
+assign subframe_w[30] = 1'b0;
+
+// Timeslots 31 = Even Parity bit (31:4)
+assign subframe_w[31] = 1'b0;
+
+//-----------------------------------------------------------------
+// Preamble
+//-----------------------------------------------------------------
+localparam PREAMBLE_Z = 8'b00010111;
+localparam PREAMBLE_Y = 8'b00100111;
+localparam PREAMBLE_X = 8'b01000111;
+
+reg [7:0] preamble_r;
+
+always @ *
+begin
+    // Start of audio block?
+    // Z(B) - Left channel
+    if (subframe_count_q == 9'd0)
+        preamble_r = PREAMBLE_Z; // Z(B)
+    // Right Channel?
+    else if (subframe_count_q[0] == 1'b1)
+        preamble_r = PREAMBLE_Y; // Y(W)
+    // Left Channel (but not start of block)?
+    else
+        preamble_r = PREAMBLE_X; // X(M)
+end
+
+always @ (posedge rst_i or posedge clk_i )
+if (rst_i == 1'b1)
+    preamble_q  <= 8'h00;
+else if (load_subframe_q)
+    preamble_q  <= preamble_r;
+
+//-----------------------------------------------------------------
+// Parity Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i )
+begin
+   if (rst_i == 1'b1)
+   begin
+        parity_count_q  <= 6'd0;
+   end
+   // Time to output a bit?
+   else if (bit_out_en_i)
+   begin
+        // Preamble bits?
+        if (bit_count_q < 6'd8)
+        begin
+            parity_count_q  <= 6'd0;
+        end
+        // Normal timeslots
+        else if (bit_count_q < 6'd62)
+        begin
+            // On first pass through this timeslot, count number of high bits
+            if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
+                parity_count_q <= parity_count_q + 6'd1;
+        end
+   end
+end
+
+//-----------------------------------------------------------------
+// Bit Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i)
+begin
+    if (rst_i == 1'b1)
+    begin
+        bit_count_q     <= 6'b0;
+        load_subframe_q <= 1'b1;
+    end
+    // Time to output a bit?
+    else if (bit_out_en_i)
+    begin
+        // 32 timeslots (x2 for double frequency)
+        if (bit_count_q == 6'd63)
+        begin
+            bit_count_q     <= 6'd0;
+            load_subframe_q <= 1'b1;
+        end
+        else
+        begin
+            bit_count_q     <= bit_count_q + 6'd1;
+            load_subframe_q <= 1'b0;
+        end
+    end
+    else
+        load_subframe_q <= 1'b0;
+end
+
+//-----------------------------------------------------------------
+// Bit half toggle
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i)
+if (rst_i == 1'b1)
+    bit_toggle_q    <= 1'b0;
+// Time to output a bit?
+else if (bit_out_en_i)
+    bit_toggle_q <= ~bit_toggle_q;
+
+//-----------------------------------------------------------------
+// Output bit (BMC encoded)
+//-----------------------------------------------------------------
+reg bit_r;
+
+always @ *
+begin
+    bit_r = spdif_out_q;
+
+    // Time to output a bit?
+    if (bit_out_en_i)
+    begin
+        // Preamble bits?
+        if (bit_count_q < 6'd8)
+        begin
+            bit_r = preamble_q[bit_count_q[2:0]];
+        end
+        // Normal timeslots
+        else if (bit_count_q < 6'd62)
+        begin
+            if (subframe_w[bit_count_q / 2] == 1'b0)
+            begin
+                if (bit_toggle_q == 1'b0)
+                    bit_r = ~spdif_out_q;
+                else
+                    bit_r = spdif_out_q;
+            end
+            else
+                bit_r = ~spdif_out_q;
+        end
+        // Parity timeslot
+        else
+        begin
+            // Even number of high bits, make odd
+            if (parity_count_q[0] == 1'b0)
+            begin
+                if (bit_toggle_q == 1'b0)
+                    bit_r = ~spdif_out_q;
+                else
+                    bit_r = spdif_out_q;
+            end
+            else
+                bit_r = ~spdif_out_q;
+        end
+    end
+end
+
+always @ (posedge rst_i or posedge clk_i )
+if (rst_i == 1'b1)
+    spdif_out_q <= 1'b0;
+else
+    spdif_out_q <= bit_r;
+
+assign spdif_o  = spdif_out_q;
+
+endmodule
diff --git a/sys/sync_vg.v b/sys/sync_vg.v
new file mode 100644
index 0000000..caaf681
--- /dev/null
+++ b/sys/sync_vg.v
@@ -0,0 +1,78 @@
+module sync_vg
+#(
+	parameter X_BITS=12, Y_BITS=12
+)
+(
+	input wire clk,
+	input wire reset,
+
+	input wire [Y_BITS-1:0] v_total,
+	input wire [Y_BITS-1:0] v_fp,
+	input wire [Y_BITS-1:0] v_bp,
+	input wire [Y_BITS-1:0] v_sync,
+	input wire [X_BITS-1:0] h_total,
+	input wire [X_BITS-1:0] h_fp,
+	input wire [X_BITS-1:0] h_bp,
+	input wire [X_BITS-1:0] h_sync,
+	input wire [X_BITS-1:0] hv_offset,
+
+	output reg vs_out,
+	output reg hs_out,
+	output reg hde_out,
+	output reg vde_out,
+	output reg [Y_BITS-1:0] v_count_out,
+	output reg [X_BITS-1:0] h_count_out,
+	output reg [X_BITS-1:0] x_out,
+	output reg [Y_BITS-1:0] y_out
+);
+
+reg [X_BITS-1:0] h_count;
+reg [Y_BITS-1:0] v_count;
+
+/* horizontal counter */
+always @(posedge clk)
+	if (reset)
+		h_count <= 0;
+	else
+	if (h_count < h_total - 1)
+		h_count <= h_count + 1'd1;
+	else
+		h_count <= 0;
+		
+/* vertical counter */
+always @(posedge clk)
+	if (reset)
+		v_count <= 0;
+	else
+	if (h_count == h_total - 1)
+	begin
+		if (v_count == v_total - 1)
+			v_count <= 0;
+		else
+			v_count <= v_count + 1'd1;
+	end
+
+always @(posedge clk)
+	if (reset)
+		{ vs_out, hs_out, hde_out, vde_out } <= 0;
+	else begin
+		hs_out <= ((h_count < h_sync));
+
+		hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1);
+		vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1);
+
+		if ((v_count == 0) && (h_count == hv_offset))
+			vs_out <= 1'b1;
+		else if ((v_count == v_sync) && (h_count == hv_offset))
+			vs_out <= 1'b0;
+
+		/* H_COUNT_OUT and V_COUNT_OUT */
+		h_count_out <= h_count;
+		v_count_out <= v_count;
+
+		/* X and Y coords for a backend pattern generator */
+		x_out <= h_count - (h_sync + h_bp);
+		y_out <= v_count - (v_sync + v_bp);
+	end
+
+endmodule
diff --git a/sys/sys.qip b/sys/sys.qip
new file mode 100644
index 0000000..0d7b675
--- /dev/null
+++ b/sys/sys.qip
@@ -0,0 +1,24 @@
+set_global_assignment -name VERILOG_FILE sys/sys_top.v
+#set_global_assignment -name SDC_FILE sys/sys_top.sdc
+#set_global_assignment -name QIP_FILE sys/pll.qip
+#set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
+#set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip
+set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
+set_global_assignment -name VERILOG_FILE sys/scandoubler.v
+set_global_assignment -name SYSTEMVERILOG_FILE sys/video_cleaner.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
+set_global_assignment -name VERILOG_FILE sys/osd.v
+set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv
+set_global_assignment -name VERILOG_FILE sys/sync_vg.v
+set_global_assignment -name VERILOG_FILE sys/pattern_vg.v
+set_global_assignment -name VERILOG_FILE sys/i2c.v
+set_global_assignment -name VERILOG_FILE sys/i2s.v
+set_global_assignment -name VERILOG_FILE sys/spdif.v
+set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
+set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
+set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v
+set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
+set_global_assignment -name VERILOG_FILE sys/hps_io.v
diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc
new file mode 100644
index 0000000..f8f6de6
--- /dev/null
+++ b/sys/sys_top.sdc
@@ -0,0 +1,53 @@
+# Specify root clocks
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
+create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] 
+
+derive_pll_clocks
+
+# Specify PLL-generated clock(s)
+#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+#                       -name SDRAM_CLK [get_ports {SDRAM_CLK}]
+
+#create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+#                       -name HDMI_CLK [get_ports HDMI_TX_CLK]
+
+#create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+#                       -name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
+
+
+derive_clock_uncertainty
+
+
+# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) 
+#set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
+#set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
+
+#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
+#                    -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+#                                                  -setup 2
+
+#set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+#set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+# Decouple different clock groups (to simplify routing)
+#   -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+#  -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
+set_clock_groups -asynchronous \
+   -group [get_clocks { *|h2f_user0_clk}] \
+   -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
+
+#set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+#set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+
+# Put constraints on input ports
+set_false_path -from [get_ports {KEY*}] -to *
+set_false_path -from [get_ports {BTN_*}] -to *
+
+# Put constraints on output ports
+set_false_path -from * -to [get_ports {LED_*}]
+set_false_path -from * -to [get_ports {VGA_*}]
+set_false_path -from * -to [get_ports {AUDIO_SPDIF}]
+set_false_path -from * -to [get_ports {AUDIO_L}]
+set_false_path -from * -to [get_ports {AUDIO_R}]
diff --git a/sys/sys_top.v b/sys/sys_top.v
new file mode 100644
index 0000000..9818319
--- /dev/null
+++ b/sys/sys_top.v
@@ -0,0 +1,1004 @@
+//============================================================================
+//
+//  MiSTer hardware abstraction module
+//  (c)2017,2018 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
+//============================================================================
+
+module sys_top
+(
+    /////////// CLOCK //////////
+    input         FPGA_CLK1_50,
+    input         FPGA_CLK2_50,
+    input         FPGA_CLK3_50,
+
+    //////////// VGA ///////////
+    output  [5:0] VGA_R,
+    output  [5:0] VGA_G,
+    output  [5:0] VGA_B,
+    inout         VGA_HS,  // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive)
+    output        VGA_VS,
+    input         VGA_EN,  // active low
+
+    /////////// AUDIO //////////
+    output        AUDIO_L,
+    output        AUDIO_R,
+    output        AUDIO_SPDIF,
+
+    //////////// HDMI //////////
+`ifndef LITE
+    output        HDMI_I2C_SCL,
+    inout         HDMI_I2C_SDA,
+
+    output        HDMI_MCLK,
+    output        HDMI_SCLK,
+    output        HDMI_LRCLK,
+    output        HDMI_I2S,
+
+    output        HDMI_TX_CLK,
+    output        HDMI_TX_DE,
+    output [23:0] HDMI_TX_D,
+    output        HDMI_TX_HS,
+    output        HDMI_TX_VS,
+    
+    input         HDMI_TX_INT,
+`endif
+
+    //////////// SDR ///////////
+`ifndef LITE
+    output [12:0] SDRAM_A,
+    inout  [15:0] SDRAM_DQ,
+    output        SDRAM_DQML,
+    output        SDRAM_DQMH,
+    output        SDRAM_nWE,
+    output        SDRAM_nCAS,
+    output        SDRAM_nRAS,
+    output        SDRAM_nCS,
+    output  [1:0] SDRAM_BA,
+    output        SDRAM_CLK,
+    output        SDRAM_CKE,
+`else
+    input         UART_RX,
+    output        UART_TX,
+`endif
+
+    //////////// I/O ///////////
+    output        LED_USER,
+    output        LED_HDD,
+    output        LED_POWER,
+    input         BTN_USER,
+    input         BTN_OSD,
+    input         BTN_RESET,
+
+    //////////// SDIO ///////////
+    inout   [3:0] SDIO_DAT,
+    inout         SDIO_CMD,
+    output        SDIO_CLK,
+    input         SDIO_CD,
+
+    ////////// MB KEY ///////////
+    input   [1:0] KEY,
+
+    ////////// MB SWITCH ////////
+    input   [3:0] SW,
+
+    ////////// MB LED ///////////
+    output  [7:0] LED
+);
+
+
+assign SDIO_DAT[2:1] = 2'bZZ;
+
+
+//////////////////////////  LEDs  ///////////////////////////////////////
+
+reg [7:0] led_overtake = 0;
+reg [7:0] led_state    = 0;
+
+wire led_p =  led_power[1] ? ~led_power[0] : 1'b0;
+wire led_d =  led_disk[1]  ? ~led_disk[0]  : ~(led_disk[0] | gp_out[29]);
+wire led_u = ~led_user;
+wire [7:0] led_mb;
+
+assign LED       = led_mb;
+assign LED_POWER = led_p ? 1'bZ : 1'b0;
+assign LED_HDD   = led_d ? 1'bZ : 1'b0;
+assign LED_USER  = led_u ? 1'bZ : 1'b0;
+
+//LEDs on main board
+//assign LED = (led_overtake & led_state) | (~led_overtake & {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
+
+
+//////////////////////////  Buttons  ///////////////////////////////////
+reg btn_user, btn_osd;
+always @(posedge FPGA_CLK2_50) begin
+    integer div;
+    reg [7:0] deb_user;
+    reg [7:0] deb_osd;
+
+    div <= div + 1'b1;
+    if(div > 100000) div <= 0;
+    
+    if(!div) begin
+        deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])};
+        if(&deb_user) btn_user <= 1;
+        if(!deb_user) btn_user <= 0;
+
+        deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])};
+        if(&deb_osd) btn_osd <= 1;
+        if(!deb_osd) btn_osd <= 0;
+    end
+end
+
+reg btn_reset = 1;
+always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET;
+
+
+/////////////////////////  HPS I/O  /////////////////////////////////////
+
+// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode)
+//                 used to avoid lockups while JTAG loading
+wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout};
+wire [31:0] gp_out;
+
+wire  [1:0] io_ver    = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future.
+wire        io_wait;
+wire        io_wide;
+wire [15:0] io_dout;                  
+wire [15:0] io_din    = gp_outr[15:0];
+wire        io_clk    = gp_outr[17];
+wire        io_fpga   = gp_outr[18];
+wire        io_osd    = gp_outr[19];
+wire        io_uio    = gp_outr[20];
+//wire        io_sdd    = gp_outr[21]; // used only in ST core
+
+reg  io_ack;
+reg  rack;
+wire io_strobe = ~rack & io_clk;
+
+always @(posedge clk_sys) begin
+    if(~io_wait | io_strobe) begin
+        rack <= io_clk;
+        io_ack <= rack;
+    end
+end
+
+reg [31:0] gp_outr;
+always @(posedge clk_sys) begin
+    reg [31:0] gp_outd;
+    gp_outr <= gp_outd;
+    gp_outd <= gp_out;
+end
+
+wire  [7:0] core_type  = 'hA7; // A7 - Sharp MZ series core.
+
+// HPS will not communicate to core if magic is different
+wire [31:0] core_magic = {24'h5CA623, core_type};
+
+cyclonev_hps_interface_mpu_general_purpose h2f_gp
+(
+    .gp_in({~gp_out[31] ? core_magic : gp_in}),
+    .gp_out(gp_out)
+);
+
+
+reg [15:0] cfg;
+
+reg        cfg_got   = 0;
+reg        cfg_set   = 0;
+//wire [2:0] hdmi_res  = cfg[10:8];
+wire       dvi_mode  = cfg[7];
+wire       audio_96k = cfg[6];
+wire       ypbpr_en  = cfg[5];
+wire       csync     = cfg[3];
+
+wire vga_scaler= cfg[2];
+
+reg        cfg_custom_t = 0;
+reg  [5:0] cfg_custom_p1;
+reg [31:0] cfg_custom_p2;
+
+reg  [4:0] vol_att = 0;
+
+reg        vip_newcfg = 0;
+always@(posedge clk_sys) begin
+    reg  [7:0] cmd;
+    reg        has_cmd;
+    reg        old_strobe;
+    reg  [7:0] cnt = 0;
+
+    old_strobe <= io_strobe;
+
+    if(~io_uio) has_cmd <= 0;
+    else
+    if(~old_strobe & io_strobe) begin
+        if(!has_cmd) begin
+            has_cmd <= 1;
+            cmd <= io_din[7:0];
+            cnt <= 0;
+        end
+        else begin
+            if(cmd == 1) begin
+                cfg <= io_din;
+                cfg_set <= 1;
+            end
+            if(cmd == 'h20) begin
+                cfg_set <= 0;
+                cnt <= cnt + 1'd1;
+                if(cnt<8) begin
+                    if(!cnt) vip_newcfg <= ~cfg_ready;
+                    case(cnt)
+                        0: if(WIDTH  != io_din[11:0]) begin WIDTH  <= io_din[11:0]; vip_newcfg <= 1; end
+                        1: if(HFP    != io_din[11:0]) begin HFP    <= io_din[11:0]; vip_newcfg <= 1; end
+                        2: if(HS     != io_din[11:0]) begin HS     <= io_din[11:0]; vip_newcfg <= 1; end
+                        3: if(HBP    != io_din[11:0]) begin HBP    <= io_din[11:0]; vip_newcfg <= 1; end
+                        4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; vip_newcfg <= 1; end
+                        5: if(VFP    != io_din[11:0]) begin VFP    <= io_din[11:0]; vip_newcfg <= 1; end
+                        6: if(VS     != io_din[11:0]) begin VS     <= io_din[11:0]; vip_newcfg <= 1; end
+                        7: if(VBP    != io_din[11:0]) begin VBP    <= io_din[11:0]; vip_newcfg <= 1; end
+                    endcase
+                    if(cnt == 1) begin
+                        cfg_custom_p1 <= 0;
+                        cfg_custom_p2 <= 0;
+                        cfg_custom_t <= ~cfg_custom_t;
+                    end
+                end
+                else begin
+                    if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0];
+                    if(cnt[1:0]==1) cfg_custom_p2[15:0]  <= io_din;
+                    if(cnt[1:0]==2) begin
+                        cfg_custom_p2[31:16] <= io_din;
+                        cfg_custom_t <= ~cfg_custom_t;
+                        cnt[1:0] <= 0;
+                    end
+                end
+            end
+            if(cmd == 'h25) {led_overtake, led_state} <= io_din;
+            if(cmd == 'h26) vol_att <= io_din[4:0];
+            if(cmd == 'h27) VSET    <= io_din[11:0];
+        end
+    end
+end
+
+`ifndef LITE
+always @(posedge clk_sys) begin
+    reg vsd, vsd2;
+    if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
+    else begin
+        vsd  <= HDMI_TX_VS;
+        vsd2 <= vsd;
+        if(~vsd2 & vsd) cfg_got <= cfg_set;
+    end
+end
+`endif
+
+///////////////////////////  RESET  ///////////////////////////////////
+
+reg reset_req = 0;
+always @(posedge FPGA_CLK2_50) begin
+    reg [1:0] resetd, resetd2;
+    reg       old_reset;
+
+    //latch the reset
+    old_reset <= reset;
+    if(~old_reset & reset) reset_req <= 1;
+
+    //special combination to set/clear the reset
+    //preventing of accidental reset control
+    if(resetd==1) reset_req <= 1;
+    if(resetd==2 && resetd2==0) reset_req <= 0;
+
+    resetd  <= gp_out[31:30];
+    resetd2 <= resetd;
+end
+
+wire clk_ctl;
+
+`ifndef LITE
+///////////////////////// VIP version  ///////////////////////////////
+wire iHdmiClk = ~HDMI_TX_CLK;            // Internal HDMI clock, inverted in relation to external clock
+wire reset;
+
+vip vip
+(
+    //Reset/Clock
+    .reset_reset_req(reset_req | ~cfg_ready),
+    .reset_reset(reset),
+    .reset_reset_vip(0),
+
+    //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
+    .reset_cold_req(~btn_reset),
+    .reset_warm_req(0),
+
+    //control
+    .ctl_address(ctl_address),
+    .ctl_write(ctl_write),
+    .ctl_writedata(ctl_writedata),
+    .ctl_waitrequest(ctl_waitrequest),
+    .ctl_clock(clk_ctl),
+    .ctl_reset(ctl_reset),
+
+    //64-bit DDR3 RAM access
+    .ramclk1_clk(ram_clk),
+    .ram1_address(ram_address),
+    .ram1_burstcount(ram_burstcount),
+    .ram1_waitrequest(ram_waitrequest),
+    .ram1_readdata(ram_readdata),
+    .ram1_readdatavalid(ram_readdatavalid),
+    .ram1_read(ram_read),
+    .ram1_writedata(ram_writedata),
+    .ram1_byteenable(ram_byteenable),
+    .ram1_write(ram_write),
+
+    //Spare 64-bit DDR3 RAM access
+    //currently unused
+    //can combine with ram1 to make a wider RAM bus (although will increase the latency)
+    .ramclk2_clk(0),
+    .ram2_address(0),
+    .ram2_burstcount(0),
+    .ram2_waitrequest(),
+    .ram2_readdata(),
+    .ram2_readdatavalid(),
+    .ram2_read(0),
+    .ram2_writedata(0),
+    .ram2_byteenable(0),
+    .ram2_write(0),
+
+    //Video input
+    .in_clk(clk_vid),
+    .in_data({r_out, g_out, b_out}),
+    .in_de(de),
+    .in_v_sync(vs),
+    .in_h_sync(hs),
+    .in_ce(ce_pix),
+    .in_f(0),
+
+    //HDMI output
+    .hdmi_clk(iHdmiClk),
+    .hdmi_data(hdmi_data),
+    .hdmi_de(hdmi_de),
+    .hdmi_v_sync(HDMI_TX_VS),
+    .hdmi_h_sync(HDMI_TX_HS)
+);
+
+wire  [8:0] ctl_address;
+wire        ctl_write;
+wire [31:0] ctl_writedata;
+wire        ctl_waitrequest;
+wire        ctl_reset;
+wire  [7:0] ARX, ARY;
+
+vip_config vip_config
+(
+    .clk(clk_ctl),
+    .reset(ctl_reset),
+
+    .ARX(ARX),
+    .ARY(ARY),
+    .CFG_SET(vip_newcfg & cfg_got),
+
+    .WIDTH(WIDTH),
+    .HFP(HFP),
+    .HBP(HBP),
+    .HS(HS),
+    .HEIGHT(HEIGHT),
+    .VFP(VFP),
+    .VBP(VBP),
+    .VS(VS),
+    .VSET(VSET),
+
+    .address(ctl_address),
+    .write(ctl_write),
+    .writedata(ctl_writedata),
+    .waitrequest(ctl_waitrequest)
+);
+`endif
+
+
+/////////////////////////  Lite version  ////////////////////////////////
+
+//`ifdef LITE
+
+`ifndef LITE
+wire [11:0] x;
+wire [11:0] y;
+
+sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
+(
+    .clk(iHdmiClk),
+    .reset(reset),
+    .v_total(HEIGHT+VFP+VBP+VS),
+    .v_fp(VFP),
+    .v_bp(VBP),
+    .v_sync(VS),
+    .h_total(WIDTH+HFP+HBP+HS),
+    .h_fp(HFP),
+    .h_bp(HBP),
+    .h_sync(HS),
+    .hv_offset(0),
+    .vde_out(vde),
+    .hde_out(hde),
+    .vs_out(vs_hdmi),
+    .v_count_out(),
+    .h_count_out(),
+    .x_out(x),
+    .y_out(y),
+    .hs_out(hs_hdmi)
+);
+
+wire vde, hde;
+wire vs_hdmi;
+wire hs_hdmi;
+
+/*
+pattern_vg
+#(
+    .B(8), // Bits per channel
+    .X_BITS(12),
+    .Y_BITS(12),
+    .FRACTIONAL_BITS(12) // Number of fractional bits for ramp pattern
+)
+pattern_vg
+(
+    .reset(reset),
+    .clk_in(iHdmiClk),
+    .x(x),
+    .y(y),
+    .vn_in(vs_hdmi),
+    .hn_in(hs_hdmi),
+    .dn_in(vde & hde),
+    .r_in(0),
+    .g_in(0),
+    .b_in(0),
+    .vn_out(HDMI_TX_VS),
+    .hn_out(HDMI_TX_HS),
+    .den_out(HDMI_TX_DE),
+    .r_out(hdmi_data[23:16]),
+    .g_out(hdmi_data[15:8]),
+    .b_out(hdmi_data[7:0]),
+    .total_active_pix(WIDTH),
+    .total_active_lines(HEIGHT),
+    .pattern(4),
+    .ramp_step(20'h0333)
+);
+*/
+
+`endif
+
+wire reset;
+sysmem_lite sysmem
+(
+    //Reset/Clock
+    .reset_reset_req(reset_req),
+    .reset_reset(reset),
+    .ctl_clock(clk_ctl),
+
+    //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
+    .reset_cold_req(~btn_reset),
+    .reset_warm_req(0),
+
+    //64-bit DDR3 RAM access
+    .ramclk1_clk(ram_clk),
+    .ram1_address(ram_address),
+    .ram1_burstcount(ram_burstcount),
+    .ram1_waitrequest(ram_waitrequest),
+    .ram1_readdata(ram_readdata),
+    .ram1_readdatavalid(ram_readdatavalid),
+    .ram1_read(ram_read),
+    .ram1_writedata(ram_writedata),
+    .ram1_byteenable(ram_byteenable),
+    .ram1_write(ram_write),
+
+    //Spare 64-bit DDR3 RAM access
+    //currently unused
+    //can combine with ram1 to make a wider RAM bus (although will increase the latency)
+    .ramclk2_clk(0),
+    .ram2_address(0),
+    .ram2_burstcount(0),
+    .ram2_waitrequest(),
+    .ram2_readdata(),
+    .ram2_readdatavalid(),
+    .ram2_read(0),
+    .ram2_writedata(0),
+    .ram2_byteenable(0),
+    .ram2_write(0)
+
+`ifndef LITE
+    ,
+    // HDMI frame buffer
+    .vbuf_clk(clk_ctl),
+    .vbuf_address(vbuf_address),
+    .vbuf_burstcount(vbuf_burstcount),
+    .vbuf_waitrequest(vbuf_waitrequest),
+    .vbuf_writedata(vbuf_writedata),
+    .vbuf_byteenable(vbuf_byteenable),
+    .vbuf_write(vbuf_write),
+    .vbuf_readdata(vbuf_readdata),
+    .vbuf_readdatavalid(vbuf_readdatavalid),
+    .vbuf_read(vbuf_read)
+`endif
+);
+
+`ifndef LITE
+wire  [27:0] vbuf_address;
+wire   [7:0] vbuf_burstcount;
+wire         vbuf_waitrequest;
+wire [127:0] vbuf_readdata;
+wire         vbuf_readdatavalid;
+wire         vbuf_read;
+wire [127:0] vbuf_writedata;
+wire  [15:0] vbuf_byteenable;
+wire         vbuf_write;
+
+assign HDMI_TX_VS = vs_hdmi;
+assign HDMI_TX_HS = hs_hdmi;
+
+hdmi_lite hdmi_lite
+(
+    .reset(reset),
+
+    .clk_video(clk_vid),
+    .ce_pixel(ce_pix),
+    .video_vs(vs),
+    .video_de(de),
+    .video_d({r_out,g_out,b_out}),
+
+    .clk_hdmi(HDMI_TX_CLK),
+    .hdmi_hde(hde),
+    .hdmi_vde(vde),
+    .hdmi_d(hdmi_data),
+    .hdmi_de(hdmi_de),
+
+    .screen_w(WIDTH),
+    .screen_h(HEIGHT),
+    .quadbuf(1),
+    .scale_x(0),
+    .scale_y(0),
+    .scale_auto(1),
+
+    .clk_vbuf(clk_ctl),
+    .vbuf_address(vbuf_address),
+    .vbuf_burstcount(vbuf_burstcount),
+    .vbuf_waitrequest(vbuf_waitrequest),
+    .vbuf_writedata(vbuf_writedata),
+    .vbuf_byteenable(vbuf_byteenable),
+    .vbuf_write(vbuf_write),
+    .vbuf_readdata(vbuf_readdata),
+    .vbuf_readdatavalid(vbuf_readdatavalid),
+    .vbuf_read(vbuf_read)
+);
+
+`endif
+
+
+/////////////////////////  HDMI output  /////////////////////////////////
+
+`ifndef LITE
+pll_hdmi pll_hdmi
+(
+    .refclk(FPGA_CLK1_50),
+    .rst(reset_req),
+    .reconfig_to_pll(reconfig_to_pll),
+    .reconfig_from_pll(reconfig_from_pll),
+    .outclk_0(HDMI_TX_CLK)
+);
+`endif
+
+//1920x1080@60 PCLK=148.5MHz CEA
+reg  [11:0] WIDTH  = 1920;
+reg  [11:0] HFP    = 88;
+reg  [11:0] HS     = 48;
+reg  [11:0] HBP    = 148;
+reg  [11:0] HEIGHT = 1080;
+reg  [11:0] VFP    = 4;
+reg  [11:0] VS     = 5;
+reg  [11:0] VBP    = 36;
+reg  [11:0] VSET   = 0;
+
+`ifndef LITE
+wire [63:0] reconfig_to_pll;
+wire [63:0] reconfig_from_pll;
+`endif
+reg         cfg_write;
+reg   [5:0] cfg_address;
+reg  [31:0] cfg_data;
+
+`ifndef LITE
+pll_hdmi_cfg pll_hdmi_cfg
+(
+    .mgmt_clk(FPGA_CLK1_50),
+    .mgmt_reset(reset_req),
+    .mgmt_waitrequest(cfg_waitrequest),
+    .mgmt_read(0),
+    .mgmt_readdata(),
+    .mgmt_write(cfg_write),
+    .mgmt_address(cfg_address),
+    .mgmt_writedata(cfg_data),
+    .reconfig_to_pll(reconfig_to_pll),
+    .reconfig_from_pll(reconfig_from_pll)
+);
+`endif
+
+`ifndef LITE
+reg cfg_ready = 0;
+wire        cfg_waitrequest;
+`else
+reg cfg_ready = 1;
+wire        cfg_waitrequest = 1;
+`endif
+
+always @(posedge FPGA_CLK1_50) begin
+    reg gotd = 0, gotd2 = 0;
+    reg custd = 0, custd2 = 0;
+    reg old_wait = 0;
+
+    gotd  <= cfg_got;
+    gotd2 <= gotd;
+    
+    cfg_write <= 0;
+    
+    custd <= cfg_custom_t;
+    custd2 <= custd;
+    if(custd2 != custd & ~gotd) begin
+        cfg_address <= cfg_custom_p1;
+        cfg_data <= cfg_custom_p2;
+        cfg_write <= 1;
+    end
+
+    if(~gotd2 & gotd) begin
+        cfg_address <= 2;
+        cfg_data <= 0;
+        cfg_write <= 1;
+    end
+
+    old_wait <= cfg_waitrequest;
+    if(old_wait & ~cfg_waitrequest & gotd) cfg_ready <= 1;
+end
+
+`ifndef LITE
+hdmi_config hdmi_config
+(
+    .iCLK(FPGA_CLK1_50),
+    .iRST_N(cfg_ready & ~HDMI_TX_INT),
+
+    .I2C_SCL(HDMI_I2C_SCL),
+    .I2C_SDA(HDMI_I2C_SDA),
+
+    .dvi_mode(dvi_mode),
+    .audio_96k(audio_96k)
+);
+
+wire [23:0] hdmi_data;
+wire        hdmi_de;
+
+osd hdmi_osd
+(
+    .clk_sys(clk_sys),
+
+    .io_osd(io_osd),
+    .io_strobe(io_strobe),
+    .io_din(io_din),
+
+    .clk_video(iHdmiClk),
+    .din(hdmi_data),
+    .dout(HDMI_TX_D),
+    .de_in(hdmi_de),
+    .de_out(HDMI_TX_DE)
+);
+
+assign HDMI_MCLK = 0;
+i2s i2s
+(
+    .reset(~cfg_ready),
+    .clk_sys(FPGA_CLK3_50),
+    .half_rate(~audio_96k),
+
+    .sclk(HDMI_SCLK),
+    .lrclk(HDMI_LRCLK),
+    .sdata(HDMI_I2S),
+
+    //Could inverse the MSB but it will shift 0 level to -MAX level
+    .left_chan (audio_l >> !audio_s),
+    .right_chan(audio_r >> !audio_s)
+);
+`endif
+
+
+/////////////////////////  VGA output  //////////////////////////////////
+
+wire [23:0] vga_q;
+osd vga_osd
+(
+    .clk_sys(clk_sys),
+
+    .io_osd(io_osd),
+    .io_strobe(io_strobe),
+    .io_din(io_din),
+
+    .clk_video(clk_vid),
+    .din(de ? {r_out, g_out, b_out} : 24'd0),
+    .dout(vga_q),
+    .de_in(de)
+);
+
+wire [23:0] vga_o;
+
+vga_out vga_out
+(
+    .ypbpr_full(1),
+    .ypbpr_en(ypbpr_en),
+    .dout(vga_o),
+`ifdef LITE
+    .din(vga_q)
+`else
+    .din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q)
+`endif
+);
+
+`ifdef LITE
+    wire vs1 = vs;
+    wire hs1 = hs;
+`else
+    wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
+    wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
+`endif
+
+assign VGA_VS = VGA_EN ? 1'bZ      : csync ?     1'b1     : ~vs1;
+assign VGA_HS = VGA_EN ? 1'bZ      : csync ? ~(vs1 ^ hs1) : ~hs1;
+assign VGA_R  = VGA_EN ? 6'bZZZZZZ : vga_o[23:18];
+assign VGA_G  = VGA_EN ? 6'bZZZZZZ : vga_o[15:10];
+assign VGA_B  = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
+//assign VGA_VS = ~vs1;
+//assign VGA_HS = ~hs1;
+//assign VGA_R  = vga_o[23:18];
+//assign VGA_G  = vga_o[15:10];
+//assign VGA_B  = vga_o[7:2];
+
+// For core -> VGA direct connectivity, comment out vga_osd, vga_out and the above assign statements, then
+// uncomment these signals for direct core -> VGA connectivity.
+//
+//assign VGA_VS = ~vs;
+//assign VGA_HS = ~hs;
+//assign VGA_R  = r_out;
+//assign VGA_G  = g_out;
+//assign VGA_B  = b_out;
+
+/////////////////////////  Audio output  ////////////////////////////////
+
+wire al, ar, aspdif;
+
+sigma_delta_dac #(15) dac_l
+(
+    .CLK(FPGA_CLK3_50),
+    .RESET(reset),
+    .DACin({audio_l[15] ^ audio_s, audio_l[14:0]}),
+    .DACout(al)
+);
+
+sigma_delta_dac #(15) dac_r
+(
+    .CLK(FPGA_CLK3_50),
+    .RESET(reset),
+    .DACin({audio_r[15] ^ audio_s, audio_r[14:0]}),
+    .DACout(ar)
+);
+
+spdif toslink
+(
+    .clk_i(FPGA_CLK3_50),
+
+    .rst_i(reset),
+    .half_rate(0),
+
+    .audio_l(audio_l >> !audio_s),
+    .audio_r(audio_r >> !audio_s),
+
+    .spdif_o(aspdif)
+);
+
+`ifndef LITE
+assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif;
+assign AUDIO_R     = SW[0] ? HDMI_I2S   : ar;
+assign AUDIO_L     = SW[0] ? HDMI_SCLK  : al;
+`else
+assign AUDIO_SPDIF = aspdif;
+assign AUDIO_R     = ar;
+assign AUDIO_L     = al;
+`endif
+
+reg [15:0] audio_l; 
+reg [15:0] audio_r;
+
+always @(posedge FPGA_CLK3_50) begin
+    reg signed [15:0] al;
+    reg signed [15:0] ar;
+
+    case({audio_s,audio_mix})
+        'b000: al <= audio_ls;
+        'b001: al <= audio_ls - (audio_ls >> 3) + (audio_rs >> 3);
+        'b010: al <= audio_ls - (audio_ls >> 2) + (audio_rs >> 2);
+        'b011: al <= (audio_ls >> 1) + (audio_rs >> 1);
+        'b100: al <= audio_ls;
+        'b101: al <= audio_ls - (audio_ls >>> 3) + (audio_rs >>> 3);
+        'b110: al <= audio_ls - (audio_ls >>> 2) + (audio_rs >>> 2);
+        'b111: al <= (audio_ls >>> 1) + (audio_rs >>> 1);
+    endcase
+
+    case({audio_s,audio_mix})
+        'b000: ar <= audio_rs;
+        'b001: ar <= audio_rs - (audio_rs >> 3) + (audio_ls >> 3);
+        'b010: ar <= audio_rs - (audio_rs >> 2) + (audio_ls >> 2);
+        'b011: ar <= (audio_rs >> 1) + (audio_ls >> 1);
+        'b100: ar <= audio_rs;
+        'b101: ar <= audio_rs - (audio_rs >>> 3) + (audio_ls >>> 3);
+        'b110: ar <= audio_rs - (audio_rs >>> 2) + (audio_ls >>> 2);
+        'b111: ar <= (audio_rs >>> 1) + (audio_ls >>> 1);
+    endcase
+    
+    if(vol_att[4]) begin
+        audio_l <= 0;
+        audio_r <= 0;
+    end
+    else
+    if(audio_s) begin
+        audio_l <= al >>> vol_att[3:0];
+        audio_r <= ar >>> vol_att[3:0];
+    end
+    else
+    begin
+        audio_l <= al >> vol_att[3:0];
+        audio_r <= ar >> vol_att[3:0];
+    end
+end
+
+///////////////////  User module connection ////////////////////////////
+
+wire signed [15:0] audio_ls, audio_rs;
+wire        audio_s;
+wire  [1:0] audio_mix;
+wire  [7:0] r_out, g_out, b_out;
+wire        vs, hs, de;
+wire        clk_sys, clk_vid, ce_pix;
+
+wire        ram_clk;
+wire [28:0] ram_address;
+wire [7:0]  ram_burstcount;
+wire        ram_waitrequest;
+wire [63:0] ram_readdata;
+wire        ram_readdatavalid;
+wire        ram_read;
+wire [63:0] ram_writedata;
+wire [7:0]  ram_byteenable;
+wire        ram_write;
+
+wire        led_user;
+wire  [1:0] led_power;
+wire  [1:0] led_disk;
+
+wire vs_emu, hs_emu;
+sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs);
+sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs);
+
+emu emu
+(
+        .CLK_50M(FPGA_CLK3_50),
+        .RESET(reset),
+
+        //         1b         1b       1b       1b      1b  1b  1b  1b       1b       1b       1b      1b         1b       16b     16b
+        //         44         43       42       41      40  39  38  37       36       35       34      33         32       31:16   15:0
+        .HPS_BUS({HDMI_TX_VS, clk_ctl, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
+
+        .CLK_VIDEO(clk_vid),
+        .CE_PIXEL(ce_pix),
+
+        .VGA_R(r_out),
+        .VGA_G(g_out),
+        .VGA_B(b_out),
+        .VGA_HS(hs_emu),
+        .VGA_VS(vs_emu),
+        .VGA_DE(de),
+
+        .LED_USER(led_user),
+        .LED_POWER(led_power),
+        .LED_DISK(led_disk),
+        .LED_MB(led_mb),
+
+    `ifndef LITE
+        .VIDEO_ARX(ARX),
+        .VIDEO_ARY(ARY),
+    `endif
+
+        .AUDIO_L(audio_ls),
+        .AUDIO_R(audio_rs),
+        .AUDIO_S(audio_s),
+        .AUDIO_MIX(audio_mix),
+        //.TAPE_IN(0),
+
+        // SCK  -> CLK
+        // MOSI -> CMD
+        // MISO <- DAT0
+        //    Z -> DAT1
+        //    Z -> DAT2
+        // CS   -> DAT3
+        .SD_SCK(SDIO_CLK),
+        .SD_MOSI(SDIO_CMD),
+        .SD_MISO(SDIO_DAT[0]),
+        .SD_CS(SDIO_DAT[3]),
+        .SD_CD(VGA_EN ? VGA_HS : SDIO_CD),
+
+        
+
+        .DDRAM_CLK(ram_clk),
+        .DDRAM_ADDR(ram_address),
+        .DDRAM_BURSTCNT(ram_burstcount),
+        .DDRAM_BUSY(ram_waitrequest),
+        .DDRAM_DOUT(ram_readdata),
+        .DDRAM_DOUT_READY(ram_readdatavalid),
+        .DDRAM_RD(ram_read),
+        .DDRAM_DIN(ram_writedata),
+        .DDRAM_BE(ram_byteenable),
+        .DDRAM_WE(ram_write)
+
+`ifndef LITE
+        ,
+        .SDRAM_DQ(SDRAM_DQ),
+        .SDRAM_A(SDRAM_A),
+        .SDRAM_DQML(SDRAM_DQML),
+        .SDRAM_DQMH(SDRAM_DQMH),
+        .SDRAM_BA(SDRAM_BA),
+        .SDRAM_nCS(SDRAM_nCS),
+        .SDRAM_nWE(SDRAM_nWE),
+        .SDRAM_nRAS(SDRAM_nRAS),
+        .SDRAM_nCAS(SDRAM_nCAS),
+        .SDRAM_CLK(SDRAM_CLK),
+        .SDRAM_CKE(SDRAM_CKE)
+`else
+        ,.UART_RX(UART_RX),
+        .UART_TX(UART_TX)
+`endif
+    );
+
+    endmodule
+
+    module sync_fix
+    (
+        input clk,
+        
+        input sync_in,
+        output sync_out
+    );
+
+    assign sync_out = sync_in ^ pol;
+
+    reg pol;
+    always @(posedge clk) begin
+        integer pos = 0, neg = 0, cnt = 0;
+        reg s1,s2;
+
+        s1 <= sync_in;
+        s2 <= s1;
+
+        if(~s2 & s1) neg <= cnt;
+        if(s2 & ~s1) pos <= cnt;
+
+        cnt <= cnt + 1;
+        if(s2 != s1) cnt <= 0;
+
+        pol <= pos > neg;
+    end
+
+endmodule
diff --git a/sys/sysmem.sv b/sys/sysmem.sv
new file mode 100644
index 0000000..886b9b3
--- /dev/null
+++ b/sys/sysmem.sv
@@ -0,0 +1,531 @@
+`timescale 1 ps / 1 ps
+module sysmem_lite
+(
+	input          ramclk1_clk,           //   ramclk1.clk
+	input   [28:0] ram1_address,          //      ram1.address
+	input    [7:0] ram1_burstcount,       //          .burstcount
+	output         ram1_waitrequest,      //          .waitrequest
+	output  [63:0] ram1_readdata,         //          .readdata
+	output         ram1_readdatavalid,    //          .readdatavalid
+	input          ram1_read,             //          .read
+	input   [63:0] ram1_writedata,        //          .writedata
+	input    [7:0] ram1_byteenable,       //          .byteenable
+	input          ram1_write,            //          .write
+
+	input          ramclk2_clk,           //   ramclk2.clk
+	input   [28:0] ram2_address,          //      ram2.address
+	input    [7:0] ram2_burstcount,       //          .burstcount
+	output         ram2_waitrequest,      //          .waitrequest
+	output  [63:0] ram2_readdata,         //          .readdata
+	output         ram2_readdatavalid,    //          .readdatavalid
+	input          ram2_read,             //          .read
+	input   [63:0] ram2_writedata,        //          .writedata
+	input    [7:0] ram2_byteenable,       //          .byteenable
+	input          ram2_write,            //          .write
+
+	output         ctl_clock,
+	input          reset_cold_req,        //     reset.cold_req
+	output         reset_reset,           //          .reset
+	input          reset_reset_req,       //          .reset_req
+	input          reset_warm_req,        //          .warm_req
+
+	input          vbuf_clk,              //      vbuf.clk
+	input   [27:0] vbuf_address,          //      vbuf.address
+	input    [7:0] vbuf_burstcount,       //          .burstcount
+	output         vbuf_waitrequest,      //          .waitrequest
+	output [127:0] vbuf_readdata,         //          .readdata
+	output         vbuf_readdatavalid,    //          .readdatavalid
+	input          vbuf_read,             //          .read
+	input  [127:0] vbuf_writedata,        //          .writedata
+	input   [15:0] vbuf_byteenable,       //          .byteenable
+	input          vbuf_write             //          .write
+);
+
+assign ctl_clock = clk_vip_clk;
+
+wire hps_h2f_reset_reset;           // HPS:h2f_rst_n -> Reset_Source:reset_hps
+wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
+wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
+wire clk_vip_clk;
+
+sysmem_HPS_fpga_interfaces fpga_interfaces (
+	.f2h_cold_rst_req_n       (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
+	.f2h_warm_rst_req_n       (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
+	.h2f_user0_clk            (clk_vip_clk),                    //    h2f_user0_clock.clk
+	.h2f_rst_n                (hps_h2f_reset_reset),            //          h2f_reset.reset_n
+	.f2h_sdram0_clk           (vbuf_clk),                       //   f2h_sdram0_clock.clk
+	.f2h_sdram0_ADDRESS       (vbuf_address),                   //    f2h_sdram0_data.address
+	.f2h_sdram0_BURSTCOUNT    (vbuf_burstcount),                //                   .burstcount
+	.f2h_sdram0_WAITREQUEST   (vbuf_waitrequest),               //                   .waitrequest
+	.f2h_sdram0_READDATA      (vbuf_readdata),                  //                   .readdata
+	.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),             //                   .readdatavalid
+	.f2h_sdram0_READ          (vbuf_read),                      //                   .read
+	.f2h_sdram0_WRITEDATA     (vbuf_writedata),                 //                   .writedata
+	.f2h_sdram0_BYTEENABLE    (vbuf_byteenable),                //                   .byteenable
+	.f2h_sdram0_WRITE         (vbuf_write),                     //                   .write
+	.f2h_sdram1_clk           (ramclk1_clk),                    //   f2h_sdram1_clock.clk
+	.f2h_sdram1_ADDRESS       (ram1_address),                   //    f2h_sdram1_data.address
+	.f2h_sdram1_BURSTCOUNT    (ram1_burstcount),                //                   .burstcount
+	.f2h_sdram1_WAITREQUEST   (ram1_waitrequest),               //                   .waitrequest
+	.f2h_sdram1_READDATA      (ram1_readdata),                  //                   .readdata
+	.f2h_sdram1_READDATAVALID (ram1_readdatavalid),             //                   .readdatavalid
+	.f2h_sdram1_READ          (ram1_read),                      //                   .read
+	.f2h_sdram1_WRITEDATA     (ram1_writedata),                 //                   .writedata
+	.f2h_sdram1_BYTEENABLE    (ram1_byteenable),                //                   .byteenable
+	.f2h_sdram1_WRITE         (ram1_write),                     //                   .write
+	.f2h_sdram2_clk           (ramclk2_clk),                    //   f2h_sdram2_clock.clk
+	.f2h_sdram2_ADDRESS       (ram2_address),                   //    f2h_sdram2_data.address
+	.f2h_sdram2_BURSTCOUNT    (ram2_burstcount),                //                   .burstcount
+	.f2h_sdram2_WAITREQUEST   (ram2_waitrequest),               //                   .waitrequest
+	.f2h_sdram2_READDATA      (ram2_readdata),                  //                   .readdata
+	.f2h_sdram2_READDATAVALID (ram2_readdatavalid),             //                   .readdatavalid
+	.f2h_sdram2_READ          (ram2_read),                      //                   .read
+	.f2h_sdram2_WRITEDATA     (ram2_writedata),                 //                   .writedata
+	.f2h_sdram2_BYTEENABLE    (ram2_byteenable),                //                   .byteenable
+	.f2h_sdram2_WRITE         (ram2_write)                      //                   .write
+);
+
+reset_source reset_source (
+	.clk        (clk_vip_clk),                   //      clock.clk
+	.reset_hps  (~hps_h2f_reset_reset),          //  reset_hps.reset
+	.reset_sys  (),                              //  reset_sys.reset
+	.cold_req   (reset_cold_req),                //  reset_ctl.cold_req
+	.reset      (reset_reset),                   //           .reset
+	.reset_req  (reset_reset_req),               //           .reset_req
+	.reset_vip  (0),                             //           .reset_vip
+	.warm_req   (reset_warm_req),                //           .warm_req
+	.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
+	.reset_cold (reset_source_reset_cold_reset)  // reset_cold.reset
+);
+
+endmodule
+
+`timescale 1 ps / 1 ps
+module sysmem
+(
+	input          ramclk1_clk,           //   ramclk1.clk
+	input   [28:0] ram1_address,          //      ram1.address
+	input    [7:0] ram1_burstcount,       //          .burstcount
+	output         ram1_waitrequest,      //          .waitrequest
+	output  [63:0] ram1_readdata,         //          .readdata
+	output         ram1_readdatavalid,    //          .readdatavalid
+	input          ram1_read,             //          .read
+	input   [63:0] ram1_writedata,        //          .writedata
+	input    [7:0] ram1_byteenable,       //          .byteenable
+	input          ram1_write,            //          .write
+
+	input          ramclk2_clk,           //   ramclk2.clk
+	input   [28:0] ram2_address,          //      ram2.address
+	input    [7:0] ram2_burstcount,       //          .burstcount
+	output         ram2_waitrequest,      //          .waitrequest
+	output  [63:0] ram2_readdata,         //          .readdata
+	output         ram2_readdatavalid,    //          .readdatavalid
+	input          ram2_read,             //          .read
+	input   [63:0] ram2_writedata,        //          .writedata
+	input    [7:0] ram2_byteenable,       //          .byteenable
+	input          ram2_write,            //          .write
+
+	input          reset_cold_req,        //     reset.cold_req
+	output         reset_reset,           //          .reset
+	input          reset_reset_req,       //          .reset_req
+	input          reset_warm_req,        //          .warm_req
+
+	input   [27:0] ram_vip_address,       //   ram_vip.address
+	input    [7:0] ram_vip_burstcount,    //          .burstcount
+	output         ram_vip_waitrequest,   //          .waitrequest
+	output [127:0] ram_vip_readdata,      //          .readdata
+	output         ram_vip_readdatavalid, //          .readdatavalid
+	input          ram_vip_read,          //          .read
+	input  [127:0] ram_vip_writedata,     //          .writedata
+	input   [15:0] ram_vip_byteenable,    //          .byteenable
+	input          ram_vip_write,         //          .write
+
+	output         clk_vip_clk,           //   clk_vip.clk
+	output         reset_vip_reset        // reset_vip.reset
+);
+
+wire    hps_h2f_reset_reset;           // HPS:h2f_rst_n -> Reset_Source:reset_hps
+wire    reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
+wire    reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
+
+sysmem_HPS_fpga_interfaces fpga_interfaces (
+	.f2h_cold_rst_req_n       (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
+	.f2h_warm_rst_req_n       (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
+	.h2f_user0_clk            (clk_vip_clk),                    //    h2f_user0_clock.clk
+	.h2f_rst_n                (hps_h2f_reset_reset),            //          h2f_reset.reset_n
+	.f2h_sdram0_clk           (clk_vip_clk),                    //   f2h_sdram0_clock.clk
+	.f2h_sdram0_ADDRESS       (ram_vip_address),                //    f2h_sdram0_data.address
+	.f2h_sdram0_BURSTCOUNT    (ram_vip_burstcount),             //                   .burstcount
+	.f2h_sdram0_WAITREQUEST   (ram_vip_waitrequest),            //                   .waitrequest
+	.f2h_sdram0_READDATA      (ram_vip_readdata),               //                   .readdata
+	.f2h_sdram0_READDATAVALID (ram_vip_readdatavalid),          //                   .readdatavalid
+	.f2h_sdram0_READ          (ram_vip_read),                   //                   .read
+	.f2h_sdram0_WRITEDATA     (ram_vip_writedata),              //                   .writedata
+	.f2h_sdram0_BYTEENABLE    (ram_vip_byteenable),             //                   .byteenable
+	.f2h_sdram0_WRITE         (ram_vip_write),                  //                   .write
+	.f2h_sdram1_clk           (ramclk1_clk),                    //   f2h_sdram1_clock.clk
+	.f2h_sdram1_ADDRESS       (ram1_address),                   //    f2h_sdram1_data.address
+	.f2h_sdram1_BURSTCOUNT    (ram1_burstcount),                //                   .burstcount
+	.f2h_sdram1_WAITREQUEST   (ram1_waitrequest),               //                   .waitrequest
+	.f2h_sdram1_READDATA      (ram1_readdata),                  //                   .readdata
+	.f2h_sdram1_READDATAVALID (ram1_readdatavalid),             //                   .readdatavalid
+	.f2h_sdram1_READ          (ram1_read),                      //                   .read
+	.f2h_sdram1_WRITEDATA     (ram1_writedata),                 //                   .writedata
+	.f2h_sdram1_BYTEENABLE    (ram1_byteenable),                //                   .byteenable
+	.f2h_sdram1_WRITE         (ram1_write),                     //                   .write
+	.f2h_sdram2_clk           (ramclk2_clk),                    //   f2h_sdram2_clock.clk
+	.f2h_sdram2_ADDRESS       (ram2_address),                   //    f2h_sdram2_data.address
+	.f2h_sdram2_BURSTCOUNT    (ram2_burstcount),                //                   .burstcount
+	.f2h_sdram2_WAITREQUEST   (ram2_waitrequest),               //                   .waitrequest
+	.f2h_sdram2_READDATA      (ram2_readdata),                  //                   .readdata
+	.f2h_sdram2_READDATAVALID (ram2_readdatavalid),             //                   .readdatavalid
+	.f2h_sdram2_READ          (ram2_read),                      //                   .read
+	.f2h_sdram2_WRITEDATA     (ram2_writedata),                 //                   .writedata
+	.f2h_sdram2_BYTEENABLE    (ram2_byteenable),                //                   .byteenable
+	.f2h_sdram2_WRITE         (ram2_write)                      //                   .write
+);
+
+reset_source reset_source (
+	.clk        (clk_vip_clk),                   //      clock.clk
+	.reset_hps  (~hps_h2f_reset_reset),          //  reset_hps.reset
+	.reset_sys  (reset_vip_reset),               //  reset_sys.reset
+	.cold_req   (reset_cold_req),                //  reset_ctl.cold_req
+	.reset      (reset_reset),                   //           .reset
+	.reset_req  (reset_reset_req),               //           .reset_req
+	.warm_req   (reset_warm_req),                //           .warm_req
+	.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
+	.reset_cold (reset_source_reset_cold_reset)  // reset_cold.reset
+);
+
+endmodule
+
+module sysmem_HPS_fpga_interfaces
+(
+	// h2f_reset
+	output wire [1 - 1 : 0 ] h2f_rst_n
+
+	// f2h_cold_reset_req
+	,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
+
+	// f2h_warm_reset_req
+	,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
+
+	// h2f_user0_clock
+	,output wire [1 - 1 : 0 ] h2f_user0_clk
+
+	// f2h_sdram0_data
+	,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
+	,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram0_READ
+	,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
+	,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
+
+	// f2h_sdram0_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram0_clk
+
+	// f2h_sdram1_data
+	,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
+	,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram1_READ
+	,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
+	,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
+
+	// f2h_sdram1_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram1_clk
+
+	// f2h_sdram2_data
+	,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
+	,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram2_READ
+	,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
+	,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
+
+	// f2h_sdram2_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram2_clk
+);
+
+
+wire [29 - 1 : 0] intermediate;
+assign intermediate[0:0] = ~intermediate[1:1];
+assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
+assign intermediate[2:2] = intermediate[9:9];
+assign intermediate[3:3] = intermediate[9:9];
+assign intermediate[5:5] = intermediate[9:9];
+assign intermediate[6:6] = intermediate[9:9];
+assign intermediate[10:10] = intermediate[9:9];
+assign intermediate[11:11] = ~intermediate[12:12];
+assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
+assign intermediate[13:13] = intermediate[18:18];
+assign intermediate[15:15] = intermediate[18:18];
+assign intermediate[19:19] = intermediate[18:18];
+assign intermediate[20:20] = ~intermediate[21:21];
+assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
+assign intermediate[22:22] = intermediate[27:27];
+assign intermediate[24:24] = intermediate[27:27];
+assign intermediate[28:28] = intermediate[27:27];
+assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
+assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
+assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
+assign intermediate[4:4] = f2h_sdram0_READ[0:0];
+assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
+assign intermediate[9:9] = f2h_sdram0_clk[0:0];
+assign intermediate[14:14] = f2h_sdram1_READ[0:0];
+assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
+assign intermediate[18:18] = f2h_sdram1_clk[0:0];
+assign intermediate[23:23] = f2h_sdram2_READ[0:0];
+assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
+assign intermediate[27:27] = f2h_sdram2_clk[0:0];
+
+cyclonev_hps_interface_clocks_resets clocks_resets(
+ .f2h_warm_rst_req_n({
+    f2h_warm_rst_req_n[0:0] // 0:0
+  })
+,.f2h_pending_rst_ack({
+    1'b1 // 0:0
+  })
+,.f2h_dbg_rst_req_n({
+    1'b1 // 0:0
+  })
+,.h2f_rst_n({
+    h2f_rst_n[0:0] // 0:0
+  })
+,.f2h_cold_rst_req_n({
+    f2h_cold_rst_req_n[0:0] // 0:0
+  })
+,.h2f_user0_clk({
+    h2f_user0_clk[0:0] // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_dbg_apb debug_apb(
+ .DBG_APB_DISABLE({
+    1'b0 // 0:0
+  })
+,.P_CLK_EN({
+    1'b0 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_tpiu_trace tpiu(
+ .traceclk_ctl({
+    1'b1 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
+ .boot_from_fpga_ready({
+    1'b0 // 0:0
+  })
+,.boot_from_fpga_on_failure({
+    1'b0 // 0:0
+  })
+,.bsel_en({
+    1'b0 // 0:0
+  })
+,.csel_en({
+    1'b0 // 0:0
+  })
+,.csel({
+    2'b01 // 1:0
+  })
+,.bsel({
+    3'b001 // 2:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2hps fpga2hps(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_hps2fpga hps2fpga(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2sdram f2sdram(
+ .cfg_rfifo_cport_map({
+    16'b0010000100000000 // 15:0
+  })
+,.cfg_wfifo_cport_map({
+    16'b0010000100000000 // 15:0
+  })
+,.rd_ready_3({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_2({
+    intermediate[28:28] // 0:0
+  })
+,.rd_ready_2({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_1({
+    intermediate[19:19] // 0:0
+  })
+,.rd_ready_1({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_0({
+    intermediate[10:10] // 0:0
+  })
+,.rd_ready_0({
+    1'b1 // 0:0
+  })
+,.wrack_ready_2({
+    1'b1 // 0:0
+  })
+,.wrack_ready_1({
+    1'b1 // 0:0
+  })
+,.wrack_ready_0({
+    1'b1 // 0:0
+  })
+,.cmd_ready_2({
+    intermediate[21:21] // 0:0
+  })
+,.cmd_ready_1({
+    intermediate[12:12] // 0:0
+  })
+,.cmd_ready_0({
+    intermediate[1:1] // 0:0
+  })
+,.cfg_port_width({
+    12'b000000010110 // 11:0
+  })
+,.rd_valid_3({
+    f2h_sdram2_READDATAVALID[0:0] // 0:0
+  })
+,.rd_valid_2({
+    f2h_sdram1_READDATAVALID[0:0] // 0:0
+  })
+,.rd_valid_1({
+    f2h_sdram0_READDATAVALID[0:0] // 0:0
+  })
+,.rd_clk_3({
+    intermediate[22:22] // 0:0
+  })
+,.rd_data_3({
+    f2h_sdram2_READDATA[63:0] // 63:0
+  })
+,.rd_clk_2({
+    intermediate[13:13] // 0:0
+  })
+,.rd_data_2({
+    f2h_sdram1_READDATA[63:0] // 63:0
+  })
+,.rd_clk_1({
+    intermediate[3:3] // 0:0
+  })
+,.rd_data_1({
+    f2h_sdram0_READDATA[127:64] // 63:0
+  })
+,.rd_clk_0({
+    intermediate[2:2] // 0:0
+  })
+,.rd_data_0({
+    f2h_sdram0_READDATA[63:0] // 63:0
+  })
+,.cfg_axi_mm_select({
+    6'b000000 // 5:0
+  })
+,.cmd_valid_2({
+    intermediate[26:26] // 0:0
+  })
+,.cmd_valid_1({
+    intermediate[17:17] // 0:0
+  })
+,.cmd_valid_0({
+    intermediate[8:8] // 0:0
+  })
+,.cfg_cport_rfifo_map({
+    18'b000000000011010000 // 17:0
+  })
+,.wr_data_3({
+    2'b00 // 89:88
+   ,f2h_sdram2_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram2_WRITEDATA[63:0] // 63:0
+  })
+,.wr_data_2({
+    2'b00 // 89:88
+   ,f2h_sdram1_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram1_WRITEDATA[63:0] // 63:0
+  })
+,.wr_data_1({
+    2'b00 // 89:88
+   ,f2h_sdram0_BYTEENABLE[15:8] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram0_WRITEDATA[127:64] // 63:0
+  })
+,.cfg_cport_type({
+    12'b000000111111 // 11:0
+  })
+,.wr_data_0({
+    2'b00 // 89:88
+   ,f2h_sdram0_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram0_WRITEDATA[63:0] // 63:0
+  })
+,.cfg_cport_wfifo_map({
+    18'b000000000011010000 // 17:0
+  })
+,.wr_clk_3({
+    intermediate[24:24] // 0:0
+  })
+,.wr_clk_2({
+    intermediate[15:15] // 0:0
+  })
+,.wr_clk_1({
+    intermediate[6:6] // 0:0
+  })
+,.wr_clk_0({
+    intermediate[5:5] // 0:0
+  })
+,.cmd_data_2({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
+   ,3'b000 // 33:31
+   ,f2h_sdram2_ADDRESS[28:0] // 30:2
+   ,intermediate[25:25] // 1:1
+   ,intermediate[23:23] // 0:0
+  })
+,.cmd_data_1({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
+   ,3'b000 // 33:31
+   ,f2h_sdram1_ADDRESS[28:0] // 30:2
+   ,intermediate[16:16] // 1:1
+   ,intermediate[14:14] // 0:0
+  })
+,.cmd_data_0({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
+   ,4'b0000 // 33:30
+   ,f2h_sdram0_ADDRESS[27:0] // 29:2
+   ,intermediate[7:7] // 1:1
+   ,intermediate[4:4] // 0:0
+  })
+);
+
+endmodule
diff --git a/sys/vga_out.sv b/sys/vga_out.sv
new file mode 100644
index 0000000..e316000
--- /dev/null
+++ b/sys/vga_out.sv
@@ -0,0 +1,65 @@
+
+module vga_out
+(
+	input         ypbpr_full,
+	input         ypbpr_en,
+
+	input  [23:0] din,
+	output [23:0] dout
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+wire [5:0] red   = din[23:18];
+wire [5:0] green = din[15:10];
+wire [5:0] blue  = din[7:2];
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16];
+assign dout[15:8]  = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]), 2'b00} : din[15:8];
+assign dout[7:0]   = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0];
+
+
+endmodule
diff --git a/sys/video_cleaner.sv b/sys/video_cleaner.sv
new file mode 100644
index 0000000..36227ba
--- /dev/null
+++ b/sys/video_cleaner.sv
@@ -0,0 +1,91 @@
+//
+//
+// Copyright (c) 2018 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+module video_cleaner
+(
+	input            clk_vid,
+	input            ce_pix,
+
+	input      [7:0] R,
+	input      [7:0] G,
+	input      [7:0] B,
+
+	input            HSync,
+	input            VSync,
+	input            HBlank,
+	input            VBlank,
+
+	// video output signals
+	output reg [7:0] VGA_R,
+	output reg [7:0] VGA_G,
+	output reg [7:0] VGA_B,
+	output reg       VGA_VS,
+	output reg       VGA_HS,
+	output           VGA_DE,
+	
+	// optional aligned blank
+	output reg       HBlank_out,
+	output reg       VBlank_out
+);
+
+wire hs, vs;
+s_fix sync_v(clk_vid, HSync, hs);
+s_fix sync_h(clk_vid, VSync, vs);
+
+wire hbl = hs | HBlank;
+wire vbl = vs | VBlank;
+
+assign VGA_DE = ~(HBlank_out | VBlank_out);
+
+always @(posedge clk_vid) begin
+	if(ce_pix) begin
+		HBlank_out <= hbl;
+
+		VGA_VS <= vs;
+		VGA_HS <= hs;
+		VGA_R  <= R;
+		VGA_G  <= G;
+		VGA_B  <= B;
+
+		if(HBlank_out & ~hbl) VBlank_out <= vbl;
+	end
+end
+
+endmodule
+
+module s_fix
+(
+	input clk,
+	
+	input sync_in,
+	output sync_out
+);
+
+assign sync_out = sync_in ^ pol;
+
+reg pol;
+always @(posedge clk) begin
+	integer pos = 0, neg = 0, cnt = 0;
+	reg s1,s2;
+
+	s1 <= sync_in;
+	s2 <= s1;
+
+	if(~s2 & s1) neg <= cnt;
+	if(s2 & ~s1) pos <= cnt;
+
+	cnt <= cnt + 1;
+	if(s2 != s1) cnt <= 0;
+
+	pol <= pos > neg;
+end
+
+endmodule
diff --git a/sys/video_mixer.sv b/sys/video_mixer.sv
new file mode 100644
index 0000000..c9d358d
--- /dev/null
+++ b/sys/video_mixer.sv
@@ -0,0 +1,167 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 4 bits per component
+//              For half depth 8 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input            clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input            ce_pix,
+	output           ce_pix_out,
+
+	input            scandoubler,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input      [1:0] scanlines,
+
+	// High quality 2x scaling
+	input            hq2x,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// Positive pulses.
+	input            HSync,
+	input            VSync,
+	input            HBlank,
+	input            VBlank,
+
+	// video output signals
+	output reg [7:0] VGA_R,
+	output reg [7:0] VGA_G,
+	output reg [7:0] VGA_B,
+	output reg       VGA_VS,
+	output reg       VGA_HS,
+	output reg       VGA_DE
+);
+
+localparam DWIDTH = HALF_DEPTH ? 3 : 7;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
+
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.hb_in(HBlank),
+	.vb_in(VBlank),
+	.r_in(R),
+	.g_in(G),
+	.b_in(B),
+
+	.ce_pix_out(ce_pix_sd),
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.hb_out(hb_sd),
+	.vb_out(vb_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler ? R_sd : R);
+wire [DWIDTH:0] gt  = (scandoubler ? G_sd : G);
+wire [DWIDTH:0] bt  = (scandoubler ? B_sd : B);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [7:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [7:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [7:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [7:0] r  = rt;
+		wire [7:0] g  = gt;
+		wire [7:0] b  = bt;
+	end
+endgenerate
+
+wire hs = (scandoubler ? hs_sd : HSync);
+wire vs = (scandoubler ? vs_sd : VSync);
+
+assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
+
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire hde = scandoubler ? ~hb_sd : ~HBlank;
+wire vde = scandoubler ? ~vb_sd : ~VBlank;
+
+always @(posedge clk_sys) begin
+	reg old_hde;
+
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
+			VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
+			VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			VGA_R <= {1'b0, r[7:1]};
+			VGA_G <= {1'b0, g[7:1]};
+			VGA_B <= {1'b0, b[7:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			VGA_R <= {2'b00, r[7:2]};
+			VGA_G <= {2'b00, g[7:2]};
+			VGA_B <= {2'b00, b[7:2]};
+		end
+
+		default: begin
+			VGA_R <= r;
+			VGA_G <= g;
+			VGA_B <= b;
+		end
+	endcase
+
+	VGA_VS <= vs;
+	VGA_HS <= hs;
+
+	old_hde <= hde;
+	if(~old_hde && hde) VGA_DE <= vde;
+	if(old_hde && ~hde) VGA_DE <= 0;
+end
+
+endmodule
diff --git a/sys/vip.qsys b/sys/vip.qsys
new file mode 100644
index 0000000..1f8a5d7
--- /dev/null
+++ b/sys/vip.qsys
@@ -0,0 +1,1177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element Controller
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element Frame_Buffer
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element HPS
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element Input
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element Mixer
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element Output
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element Reset_Source
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element Scaler
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element Video_Input
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element Video_Output
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element soc_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5CSEBA6U23I7" />
+ <parameter name="deviceFamily" value="Cyclone V" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="ctl" internal="Controller.control" type="conduit" dir="end" />
+ <interface name="finish" internal="Reset_Source.reset_cold_req" />
+ <interface name="hdmi" internal="Output.Output" type="conduit" dir="end" />
+ <interface name="in" internal="Input.input" type="conduit" dir="end" />
+ <interface name="out_mix_0_Output" internal="Output.Output1" />
+ <interface name="out_mix_0_input" internal="Output.input1" />
+ <interface name="ram1" internal="HPS.f2h_sdram1_data" type="avalon" dir="end" />
+ <interface name="ram2" internal="HPS.f2h_sdram2_data" type="avalon" dir="end" />
+ <interface name="ramclk1" internal="HPS.f2h_sdram1_clock" type="clock" dir="end" />
+ <interface name="ramclk2" internal="HPS.f2h_sdram2_clock" type="clock" dir="end" />
+ <interface
+   name="reset"
+   internal="Reset_Source.reset_ctl"
+   type="conduit"
+   dir="end" />
+ <module name="Controller" kind="avalon_combiner" version="17.0" enabled="1" />
+ <module name="Frame_Buffer" kind="alt_vip_cl_vfb" version="17.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="BITS_PER_SYMBOL" value="8" />
+  <parameter name="BURST_ALIGNMENT" value="1" />
+  <parameter name="CLOCKS_ARE_SEPARATE" value="0" />
+  <parameter name="COLOR_PLANES_ARE_IN_PARALLEL" value="1" />
+  <parameter name="CONTROLLED_DROP_REPEAT" value="0" />
+  <parameter name="DROP_FRAMES" value="1" />
+  <parameter name="DROP_INVALID_FIELDS" value="1" />
+  <parameter name="DROP_REPEAT_USER" value="0" />
+  <parameter name="FAMILY" value="Cyclone V" />
+  <parameter name="INTERLACED_SUPPORT" value="0" />
+  <parameter name="IS_FRAME_READER" value="0" />
+  <parameter name="IS_FRAME_WRITER" value="0" />
+  <parameter name="IS_SYNC_MASTER" value="0" />
+  <parameter name="IS_SYNC_SLAVE" value="0" />
+  <parameter name="MAX_HEIGHT" value="1080" />
+  <parameter name="MAX_SYMBOLS_PER_PACKET" value="10" />
+  <parameter name="MAX_WIDTH" value="1920" />
+  <parameter name="MEM_BASE_ADDR" value="536870912" />
+  <parameter name="MEM_BUFFER_OFFSET" value="16777216" />
+  <parameter name="MEM_PORT_WIDTH" value="128" />
+  <parameter name="MULTI_FRAME_DELAY" value="1" />
+  <parameter name="NUMBER_OF_COLOR_PLANES" value="3" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
+  <parameter name="READER_RUNTIME_CONTROL" value="0" />
+  <parameter name="READY_LATENCY" value="1" />
+  <parameter name="READ_BURST_TARGET" value="64" />
+  <parameter name="READ_FIFO_DEPTH" value="512" />
+  <parameter name="REPEAT_FRAMES" value="1" />
+  <parameter name="TEST_INIT" value="0" />
+  <parameter name="USER_PACKETS_MAX_STORAGE" value="1" />
+  <parameter name="USE_BUFFER_OFFSET" value="0" />
+  <parameter name="WRITER_RUNTIME_CONTROL" value="0" />
+  <parameter name="WRITE_BURST_TARGET" value="64" />
+  <parameter name="WRITE_FIFO_DEPTH" value="512" />
+ </module>
+ <module name="HPS" kind="altera_hps_lite" version="17.0" enabled="1">
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="BONDING_OUT_ENABLED" value="false" />
+  <parameter name="BOOTFROMFPGA_Enable" value="false" />
+  <parameter name="BSEL" value="1" />
+  <parameter name="BSEL_EN" value="false" />
+  <parameter name="CAN0_Mode" value="N/A" />
+  <parameter name="CAN0_PinMuxing" value="Unused" />
+  <parameter name="CAN1_Mode" value="N/A" />
+  <parameter name="CAN1_PinMuxing" value="Unused" />
+  <parameter name="CSEL" value="0" />
+  <parameter name="CSEL_EN" value="false" />
+  <parameter name="CTI_Enable" value="false" />
+  <parameter name="DEBUGAPB_Enable" value="false" />
+  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
+  <parameter name="EMAC0_Mode" value="N/A" />
+  <parameter name="EMAC0_PTP" value="false" />
+  <parameter name="EMAC0_PinMuxing" value="Unused" />
+  <parameter name="EMAC1_Mode" value="N/A" />
+  <parameter name="EMAC1_PTP" value="false" />
+  <parameter name="EMAC1_PinMuxing" value="Unused" />
+  <parameter name="F2H_AXI_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100000000" />
+  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="0" />
+  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="0" />
+  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
+  <parameter name="F2SCLK_COLDRST_Enable" value="true" />
+  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
+  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
+  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
+  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
+  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
+  <parameter name="F2SCLK_WARMRST_Enable" value="true" />
+  <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional,Avalon-MM Bidirectional,Avalon-MM Bidirectional</parameter>
+  <parameter name="F2SDRAM_Width" value="128,64,64" />
+  <parameter name="F2SINTERRUPT_Enable" value="false" />
+  <parameter name="F2S_Width" value="0" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
+  <parameter
+     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
+     value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="125" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="125" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
+  <parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="GP_Enable" value="false" />
+  <parameter name="H2F_AXI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
+  <parameter name="HLGPI_Enable" value="false" />
+  <parameter name="I2C0_Mode" value="N/A" />
+  <parameter name="I2C0_PinMuxing" value="Unused" />
+  <parameter name="I2C1_Mode" value="N/A" />
+  <parameter name="I2C1_PinMuxing" value="Unused" />
+  <parameter name="I2C2_Mode" value="N/A" />
+  <parameter name="I2C2_PinMuxing" value="Unused" />
+  <parameter name="I2C3_Mode" value="N/A" />
+  <parameter name="I2C3_PinMuxing" value="Unused" />
+  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="LWH2F_Enable" value="false" />
+  <parameter name="MPU_EVENTS_Enable" value="false" />
+  <parameter name="NAND_Mode" value="N/A" />
+  <parameter name="NAND_PinMuxing" value="Unused" />
+  <parameter name="QSPI_Mode" value="N/A" />
+  <parameter name="QSPI_PinMuxing" value="Unused" />
+  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
+  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
+  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
+  <parameter name="S2FCLK_USER1CLK_Enable" value="false" />
+  <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" />
+  <parameter name="S2FCLK_USER2CLK" value="5" />
+  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
+  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
+  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
+  <parameter name="S2F_Width" value="0" />
+  <parameter name="SDIO_Mode" value="N/A" />
+  <parameter name="SDIO_PinMuxing" value="Unused" />
+  <parameter name="SPIM0_Mode" value="N/A" />
+  <parameter name="SPIM0_PinMuxing" value="Unused" />
+  <parameter name="SPIM1_Mode" value="N/A" />
+  <parameter name="SPIM1_PinMuxing" value="Unused" />
+  <parameter name="SPIS0_Mode" value="N/A" />
+  <parameter name="SPIS0_PinMuxing" value="Unused" />
+  <parameter name="SPIS1_Mode" value="N/A" />
+  <parameter name="SPIS1_PinMuxing" value="Unused" />
+  <parameter name="STM_Enable" value="false" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="TEST_Enable" value="false" />
+  <parameter name="TPIUFPGA_Enable" value="false" />
+  <parameter name="TPIUFPGA_alt" value="false" />
+  <parameter name="TRACE_Mode" value="N/A" />
+  <parameter name="TRACE_PinMuxing" value="Unused" />
+  <parameter name="UART0_Mode" value="N/A" />
+  <parameter name="UART0_PinMuxing" value="Unused" />
+  <parameter name="UART1_Mode" value="N/A" />
+  <parameter name="UART1_PinMuxing" value="Unused" />
+  <parameter name="USB0_Mode" value="N/A" />
+  <parameter name="USB0_PinMuxing" value="Unused" />
+  <parameter name="USB1_Mode" value="N/A" />
+  <parameter name="USB1_PinMuxing" value="Unused" />
+  <parameter name="can0_clk_div" value="1" />
+  <parameter name="can1_clk_div" value="1" />
+  <parameter name="configure_advanced_parameters" value="false" />
+  <parameter name="customize_device_pll_info" value="false" />
+  <parameter name="dbctrl_stayosc1" value="true" />
+  <parameter name="dbg_at_clk_div" value="0" />
+  <parameter name="dbg_clk_div" value="1" />
+  <parameter name="dbg_trace_clk_div" value="0" />
+  <parameter name="desired_can0_clk_mhz" value="100.0" />
+  <parameter name="desired_can1_clk_mhz" value="100.0" />
+  <parameter name="desired_cfg_clk_mhz" value="100.0" />
+  <parameter name="desired_emac0_clk_mhz" value="250.0" />
+  <parameter name="desired_emac1_clk_mhz" value="250.0" />
+  <parameter name="desired_gpio_db_clk_hz" value="32000" />
+  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
+  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
+  <parameter name="desired_mpu_clk_mhz" value="800.0" />
+  <parameter name="desired_nand_clk_mhz" value="12.5" />
+  <parameter name="desired_qspi_clk_mhz" value="400.0" />
+  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
+  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
+  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
+  <parameter name="device_name" value="5CSEBA6U23I7" />
+  <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter>
+  <parameter name="eosc1_clk_mhz" value="25.0" />
+  <parameter name="eosc2_clk_mhz" value="25.0" />
+  <parameter name="gpio_db_clk_div" value="6249" />
+  <parameter name="l3_mp_clk_div" value="1" />
+  <parameter name="l3_sp_clk_div" value="1" />
+  <parameter name="l4_mp_clk_div" value="1" />
+  <parameter name="l4_mp_clk_source" value="1" />
+  <parameter name="l4_sp_clk_div" value="1" />
+  <parameter name="l4_sp_clk_source" value="1" />
+  <parameter name="main_pll_c3" value="3" />
+  <parameter name="main_pll_c4" value="3" />
+  <parameter name="main_pll_c5" value="15" />
+  <parameter name="main_pll_m" value="63" />
+  <parameter name="main_pll_n" value="0" />
+  <parameter name="nand_clk_source" value="2" />
+  <parameter name="periph_pll_c0" value="3" />
+  <parameter name="periph_pll_c1" value="3" />
+  <parameter name="periph_pll_c2" value="1" />
+  <parameter name="periph_pll_c3" value="19" />
+  <parameter name="periph_pll_c4" value="4" />
+  <parameter name="periph_pll_c5" value="9" />
+  <parameter name="periph_pll_m" value="79" />
+  <parameter name="periph_pll_n" value="1" />
+  <parameter name="periph_pll_source" value="0" />
+  <parameter name="qspi_clk_source" value="1" />
+  <parameter name="quartus_ini_hps_emif_pll" value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
+     value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
+  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
+  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
+  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
+  <parameter name="sdmmc_clk_source" value="2" />
+  <parameter name="show_advanced_parameters" value="false" />
+  <parameter name="show_debug_info_as_warning_msg" value="false" />
+  <parameter name="show_warning_as_error_msg" value="false" />
+  <parameter name="spi_m_clk_div" value="0" />
+  <parameter name="usb_mp_clk_div" value="0" />
+  <parameter name="use_default_mpu_clk" value="true" />
+ </module>
+ <module name="Input" kind="in_split" version="17.0" enabled="1" />
+ <module name="Mixer" kind="alt_vip_cl_mixer" version="17.0" enabled="1">
+  <parameter name="ALPHA_ENABLE" value="0" />
+  <parameter name="ALPHA_STREAMS_ENABLE" value="0" />
+  <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="BITS_PER_SYMBOL" value="8" />
+  <parameter name="COLOR_PLANES_ARE_IN_PARALLEL" value="1" />
+  <parameter name="COLOR_SPACE" value="RGB" />
+  <parameter name="FAMILY" value="Cyclone V" />
+  <parameter name="IS_422" value="1" />
+  <parameter name="LAYER_POSITION_ENABLE" value="0" />
+  <parameter name="MAX_HEIGHT" value="1080" />
+  <parameter name="MAX_WIDTH" value="1920" />
+  <parameter name="NO_OF_INPUTS" value="1" />
+  <parameter name="NUMBER_OF_COLOR_PLANES" value="2" />
+  <parameter name="PATTERN" value="uniform" />
+  <parameter name="PIPELINE_READY" value="0" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
+  <parameter name="UNIFORM_VALUE_BCR" value="0" />
+  <parameter name="UNIFORM_VALUE_GCB" value="0" />
+  <parameter name="UNIFORM_VALUE_RY" value="0" />
+  <parameter name="USER_PACKET_FIFO_DEPTH" value="0" />
+  <parameter name="USER_PACKET_SUPPORT" value="DISCARD" />
+ </module>
+ <module name="Output" kind="out_mix" version="17.0" enabled="1" />
+ <module name="Reset_Source" kind="reset_source" version="17.0" enabled="1" />
+ <module name="Scaler" kind="alt_vip_cl_scl" version="17.0" enabled="1">
+  <parameter name="ALGORITHM_NAME" value="POLYPHASE" />
+  <parameter name="ALWAYS_DOWNSCALE" value="0" />
+  <parameter name="ARE_IDENTICAL" value="1" />
+  <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="BITS_PER_SYMBOL" value="8" />
+  <parameter name="DEFAULT_EDGE_THRESH" value="7" />
+  <parameter name="DEFAULT_LOWER_BLUR" value="0" />
+  <parameter name="DEFAULT_UPPER_BLUR" value="0" />
+  <parameter name="ENABLE_FIR" value="0" />
+  <parameter name="EXTRA_PIPELINING" value="1" />
+  <parameter name="FAMILY" value="Cyclone V" />
+  <parameter name="H_BANKS" value="1" />
+  <parameter name="H_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
+  <parameter name="H_FRACTION_BITS" value="7" />
+  <parameter name="H_FUNCTION" value="LANCZOS_3" />
+  <parameter name="H_INTEGER_BITS" value="1" />
+  <parameter name="H_PHASES" value="16" />
+  <parameter name="H_SIGNED" value="1" />
+  <parameter name="H_SYMMETRIC" value="0" />
+  <parameter name="H_TAPS" value="4" />
+  <parameter name="IS_420" value="0" />
+  <parameter name="IS_422" value="0" />
+  <parameter name="LIMITED_READBACK" value="0" />
+  <parameter name="LOAD_AT_RUNTIME" value="0" />
+  <parameter name="MAX_IN_HEIGHT" value="1080" />
+  <parameter name="MAX_IN_WIDTH" value="1920" />
+  <parameter name="MAX_OUT_HEIGHT" value="1080" />
+  <parameter name="MAX_OUT_WIDTH" value="1920" />
+  <parameter name="NO_BLANKING" value="0" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
+  <parameter name="PRESERVE_BITS" value="0" />
+  <parameter name="RUNTIME_CONTROL" value="1" />
+  <parameter name="SYMBOLS_IN_PAR" value="3" />
+  <parameter name="SYMBOLS_IN_SEQ" value="1" />
+  <parameter name="USER_PACKET_FIFO_DEPTH" value="0" />
+  <parameter name="USER_PACKET_SUPPORT" value="PASSTHROUGH" />
+  <parameter name="V_BANKS" value="1" />
+  <parameter name="V_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
+  <parameter name="V_FRACTION_BITS" value="7" />
+  <parameter name="V_FUNCTION" value="LANCZOS_2" />
+  <parameter name="V_INTEGER_BITS" value="1" />
+  <parameter name="V_PHASES" value="32" />
+  <parameter name="V_SIGNED" value="1" />
+  <parameter name="V_SYMMETRIC" value="0" />
+  <parameter name="V_TAPS" value="4" />
+ </module>
+ <module name="Video_Input" kind="alt_vip_cl_cvi" version="17.0" enabled="1">
+  <parameter name="ACCEPT_COLOURS_IN_SEQ" value="0" />
+  <parameter name="ANC_DEPTH" value="1" />
+  <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="BPS" value="8" />
+  <parameter name="CLOCKS_ARE_SAME" value="0" />
+  <parameter name="COLOUR_PLANES_ARE_IN_PARALLEL" value="1" />
+  <parameter name="EXTRACT_TOTAL_RESOLUTION" value="1" />
+  <parameter name="FIFO_DEPTH" value="2048" />
+  <parameter name="GENERATE_ANC" value="0" />
+  <parameter name="GENERATE_VID_F" value="0" />
+  <parameter name="H_ACTIVE_PIXELS_F0" value="1920" />
+  <parameter name="INTERLACED" value="0" />
+  <parameter name="MATCH_CTRLDATA_PKT_CLIP_BASIC" value="0" />
+  <parameter name="MATCH_CTRLDATA_PKT_PAD_ADV" value="0" />
+  <parameter name="NO_OF_CHANNELS" value="1" />
+  <parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
+  <parameter name="OVERFLOW_HANDLING" value="0" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
+  <parameter name="STD_WIDTH" value="1" />
+  <parameter name="SYNC_TO" value="2" />
+  <parameter name="USE_CONTROL" value="0" />
+  <parameter name="USE_EMBEDDED_SYNCS" value="0" />
+  <parameter name="USE_HDMI_DEPRICATION" value="0" />
+  <parameter name="USE_STD" value="0" />
+  <parameter name="V_ACTIVE_LINES_F0" value="1080" />
+  <parameter name="V_ACTIVE_LINES_F1" value="480" />
+ </module>
+ <module name="Video_Output" kind="alt_vip_cl_cvo" version="17.0" enabled="1">
+  <parameter name="ACCEPT_COLOURS_IN_SEQ" value="0" />
+  <parameter name="ANC_LINE" value="0" />
+  <parameter name="AP_LINE" value="0" />
+  <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="BPS" value="8" />
+  <parameter name="CLOCKS_ARE_SAME" value="0" />
+  <parameter name="COLOUR_PLANES_ARE_IN_PARALLEL" value="1" />
+  <parameter name="CONTEXT_WIDTH" value="8" />
+  <parameter name="DST_WIDTH" value="8" />
+  <parameter name="FIELD0_ANC_LINE" value="0" />
+  <parameter name="FIELD0_V_BACK_PORCH" value="0" />
+  <parameter name="FIELD0_V_BLANK" value="0" />
+  <parameter name="FIELD0_V_FRONT_PORCH" value="0" />
+  <parameter name="FIELD0_V_RISING_EDGE" value="0" />
+  <parameter name="FIELD0_V_SYNC_LENGTH" value="0" />
+  <parameter name="FIFO_DEPTH" value="2000" />
+  <parameter name="F_FALLING_EDGE" value="0" />
+  <parameter name="F_RISING_EDGE" value="0" />
+  <parameter name="GENERATE_SYNC" value="0" />
+  <parameter name="H_ACTIVE_PIXELS" value="1920" />
+  <parameter name="H_BACK_PORCH" value="148" />
+  <parameter name="H_BLANK" value="0" />
+  <parameter name="H_FRONT_PORCH" value="88" />
+  <parameter name="H_SYNC_LENGTH" value="44" />
+  <parameter name="INTERLACED" value="0" />
+  <parameter name="LOW_LATENCY" value="1" />
+  <parameter name="NO_OF_CHANNELS" value="1" />
+  <parameter name="NO_OF_MODES" value="1" />
+  <parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
+  <parameter name="SRC_WIDTH" value="8" />
+  <parameter name="STD_WIDTH" value="1" />
+  <parameter name="TASK_WIDTH" value="8" />
+  <parameter name="THRESHOLD" value="1999" />
+  <parameter name="USE_CONTROL" value="1" />
+  <parameter name="USE_EMBEDDED_SYNCS" value="0" />
+  <parameter name="V_ACTIVE_LINES" value="1080" />
+  <parameter name="V_BACK_PORCH" value="15" />
+  <parameter name="V_BLANK" value="0" />
+  <parameter name="V_FRONT_PORCH" value="2" />
+  <parameter name="V_SYNC_LENGTH" value="5" />
+ </module>
+ <connection
+   kind="avalon"
+   version="17.0"
+   start="Controller.ctl_mixer"
+   end="Mixer.control">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="17.0"
+   start="Controller.ctl_scaler"
+   end="Scaler.control">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="17.0"
+   start="Controller.ctl_video"
+   end="Video_Output.control">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="17.0"
+   start="Frame_Buffer.mem_master_rd"
+   end="HPS.f2h_sdram0_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="17.0"
+   start="Frame_Buffer.mem_master_wr"
+   end="HPS.f2h_sdram0_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="17.0"
+   start="Mixer.dout"
+   end="Video_Output.din" />
+ <connection
+   kind="avalon_streaming"
+   version="17.0"
+   start="Frame_Buffer.dout"
+   end="Scaler.din" />
+ <connection
+   kind="avalon_streaming"
+   version="17.0"
+   start="Scaler.dout"
+   end="Mixer.din0" />
+ <connection
+   kind="avalon_streaming"
+   version="17.0"
+   start="Video_Input.dout_0"
+   end="Frame_Buffer.din" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Reset_Source.clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Controller.clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="HPS.f2h_sdram0_clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Video_Input.main_clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Frame_Buffer.main_clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Scaler.main_clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Mixer.main_clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Video_Output.main_clock" />
+ <connection
+   kind="conduit"
+   version="17.0"
+   start="Video_Input.clocked_video"
+   end="Input.Output">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="17.0"
+   start="Video_Output.clocked_video"
+   end="Output.input">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="17.0"
+   start="HPS.h2f_reset"
+   end="Reset_Source.reset_hps" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_cold"
+   end="HPS.f2h_cold_reset_req" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_sys"
+   end="Video_Input.main_reset" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_sys"
+   end="Scaler.main_reset" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_sys"
+   end="Mixer.main_reset" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_sys"
+   end="Frame_Buffer.main_reset" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_sys"
+   end="Video_Output.main_reset" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_sys"
+   end="Controller.reset" />
+ <connection
+   kind="reset"
+   version="17.0"
+   start="Reset_Source.reset_warm"
+   end="HPS.f2h_warm_reset_req" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/sys/vip_config.sv b/sys/vip_config.sv
new file mode 100644
index 0000000..b003798
--- /dev/null
+++ b/sys/vip_config.sv
@@ -0,0 +1,159 @@
+
+module vip_config
+(
+	input             clk,
+	input             reset,
+	
+	input       [7:0] ARX,
+	input       [7:0] ARY,
+	input             CFG_SET,
+
+	input      [11:0] WIDTH,
+	input      [11:0] HFP,
+	input      [11:0] HBP,
+	input      [11:0] HS,
+	input      [11:0] HEIGHT,
+	input      [11:0] VFP,
+	input      [11:0] VBP,
+	input      [11:0] VS,
+	
+	input      [11:0] VSET,
+
+	output reg  [8:0] address,
+	output reg        write,
+	output reg [31:0] writedata,
+	input             waitrequest
+);
+
+
+reg         newres = 1;
+
+wire [21:0] init[23] =
+'{
+	//video mode
+	{newres, 2'd2, 7'd04, 12'd0  }, //Bank
+	{newres, 2'd2, 7'd30, 12'd0  }, //Valid
+	{newres, 2'd2, 7'd05, 12'd0  }, //Progressive/Interlaced
+	{newres, 2'd2, 7'd06, w      }, //Active pixel count
+	{newres, 2'd2, 7'd07, h      }, //Active line count
+	{newres, 2'd2, 7'd09, hfp    }, //Horizontal Front Porch
+	{newres, 2'd2, 7'd10, hs     }, //Horizontal Sync Length
+	{newres, 2'd2, 7'd11, hb     }, //Horizontal Blanking (HFP+HBP+HSync)
+	{newres, 2'd2, 7'd12, vfp    }, //Vertical Front Porch
+	{newres, 2'd2, 7'd13, vs     }, //Vertical Sync Length
+	{newres, 2'd2, 7'd14, vb     }, //Vertical blanking (VFP+VBP+VSync)
+	{newres, 2'd2, 7'd30, 12'd1  }, //Valid
+	{newres, 2'd2, 7'd00, 12'd1  }, //Go
+
+	//mixer
+	{  1'd1, 2'd1, 7'd03, w      }, //Bkg Width
+	{  1'd1, 2'd1, 7'd04, h      }, //Bkg Height
+	{  1'd1, 2'd1, 7'd08, posx   }, //Pos X
+	{  1'd1, 2'd1, 7'd09, posy   }, //Pos Y
+	{  1'd1, 2'd1, 7'd10, 12'd1  }, //Enable Video 0
+	{  1'd1, 2'd1, 7'd00, 12'd1  }, //Go
+
+	//scaler
+	{  1'd1, 2'd0, 7'd03, videow }, //Output Width
+	{  1'd1, 2'd0, 7'd04, videoh }, //Output Height
+	{  1'd1, 2'd0, 7'd00, 12'd1  }, //Go
+
+	22'h3FFFFF
+};
+
+reg [11:0] w;
+reg [11:0] hfp;
+reg [11:0] hbp;
+reg [11:0] hs;
+reg [11:0] hb;
+reg [11:0] h;
+reg [11:0] vfp;
+reg [11:0] vbp;
+reg [11:0] vs;
+reg [11:0] vb;
+
+reg [11:0] videow;
+reg [11:0] videoh;
+
+reg [11:0] posx;
+reg [11:0] posy;
+
+always @(posedge clk) begin
+	reg  [7:0] state = 0;
+	reg  [7:0] arx, ary;
+	reg  [7:0] arxd, aryd;
+	reg [11:0] vset, vsetd;
+	reg        cfg, cfgd;
+	reg [31:0] wcalc;
+	reg [31:0] hcalc;
+	reg [12:0] timeout = 0;
+
+	arxd  <= ARX;
+	aryd  <= ARY;
+	vsetd <= VSET;
+	
+	cfg   <= CFG_SET;
+	cfgd  <= cfg;
+
+	write <= 0;
+	if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin
+		arx <= arxd;
+		ary <= aryd;
+		vset <= vsetd;
+		timeout <= '1;
+		state <= 0;
+		if(reset || (~cfgd && cfg)) newres <= 1;
+	end
+	else
+	if(timeout > 0)
+	begin
+		timeout <= timeout - 1'd1;
+		state <= 1;
+		if(!(timeout & 'h1f)) case(timeout>>5)
+			5:	begin
+					w   <= WIDTH;
+					hfp <= HFP;
+					hbp <= HBP;
+					hs  <= HS;
+					h   <= HEIGHT;
+					vfp <= VFP;
+					vbp <= VBP;
+					vs  <= VS;
+				end
+			4: begin
+					hb  <= hfp+hbp+hs;
+					vb  <= vfp+vbp+vs;
+				end
+			3: begin
+					wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary;
+					hcalc <= (w*ary)/arx;
+				end
+			2: begin
+					videow <= (!vset && (wcalc > w))    ? w : wcalc[11:0];
+					videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0];
+				end
+			1: begin
+					posx <= (w - videow)>>1;
+					posy <= (h - videoh)>>1;
+				end
+		endcase
+	end
+	else
+	if(~waitrequest && state)
+	begin
+		state <= state + 1'd1;
+		write <= 0;
+		if((state&3)==3) begin
+			if(init[state>>2] == 22'h3FFFFF) begin
+				state  <= 0;
+				newres <= 0;
+			end
+			else begin
+				writedata <= 0;
+				{write, address, writedata[11:0]} <= init[state>>2];
+			end
+		end
+	end
+end
+
+endmodule
diff --git a/sysid.vhd b/sysid.vhd
new file mode 100644
index 0000000..c5a67a6
--- /dev/null
+++ b/sysid.vhd
@@ -0,0 +1,50 @@
+--Legal Notice: (C)2018 Altera Corporation. All rights reserved.  Your
+--use of Altera Corporation's design tools, logic functions and other
+--software and tools, and its AMPP partner logic functions, and any
+--output files any of the foregoing (including device programming or
+--simulation files), and any associated documentation or information are
+--expressly subject to the terms and conditions of the Altera Program
+--License Subscription Agreement or other applicable license agreement,
+--including, without limitation, that your use is for the sole purpose
+--of programming logic devices manufactured by Altera and sold by Altera
+--or its authorized distributors.  Please refer to the applicable
+--agreement for further details.
+
+
+-- turn off superfluous VHDL processor warnings 
+-- altera message_level Level1 
+-- altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+library altera;
+use altera.altera_europa_support_lib.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity sysid is 
+        port (
+              -- inputs:
+                 signal address : IN STD_LOGIC;
+                 signal clock : IN STD_LOGIC;
+                 signal reset_n : IN STD_LOGIC;
+
+              -- outputs:
+                 signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+              );
+end entity sysid;
+
+
+architecture europa of sysid is
+
+begin
+
+  --control_slave, which is an e_avalon_slave
+  readdata <= A_WE_StdLogicVector((std_logic'(address) = '1'), std_logic_vector'("01011011000101101111000000111011"), std_logic_vector'("00000000000000000000000000000000"));
+
+end europa;
+
diff --git a/tools/ConvertToMif.sh b/tools/ConvertToMif.sh
new file mode 100755
index 0000000..7af0139
--- /dev/null
+++ b/tools/ConvertToMif.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+BASE=`basename $1`
+
+echo "Converting ${BASE}.bin to Memory Initialization File ${BASE}.mif..."
+srec_cat ${BASE}.bin -binary  -Output ${BASE}.mif -Memory_Initialization_File
+
diff --git a/tools/Terminal.exe b/tools/Terminal.exe
new file mode 100755
index 0000000..9d60d8c
Binary files /dev/null and b/tools/Terminal.exe differ
diff --git a/tools/Z80Assembler.jar b/tools/Z80Assembler.jar
new file mode 100755
index 0000000..1ec9364
Binary files /dev/null and b/tools/Z80Assembler.jar differ
diff --git a/tools/assemble_roms.sh b/tools/assemble_roms.sh
new file mode 100755
index 0000000..efe1a84
--- /dev/null
+++ b/tools/assemble_roms.sh
@@ -0,0 +1,62 @@
+#!/bin/bash
+#########################################################################################################
+##
+## Name:            assemble_roms.sh
+## Created:         August 2018
+## Author(s):       Philip Smart
+## Description:     Sharp MZ series ROM assembly tool
+##                  This script takes Sharp MZ ROMS in assembler format and compiles/assembles them
+##                  into a ROM file using the GLASS Z80 assembler.
+##
+## Credits:         
+## Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+##
+## History:         August 2018   - Initial script written.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+JARDIR=../tools
+ASM=glass.jar
+BUILDROMLIST="IPL monitor_SA1510 monitor_80c_SA1510 monitor_mz-1r12 quickdisk_mz-1e05 quickdisk_mz-1e14 monitor_1Z-013A monitor_80c_1Z-013A"
+BUILDMZFLIST="hi-ramcheck sharpmz-test"
+ASMDIR=../software/asm
+ROMDIR=../software/roms
+MZFDIR=../software/mzf
+
+# Go through list and build image.
+#
+for f in ${BUILDROMLIST} ${BUILDMZFLIST}
+do
+    echo "Assembling: $f..."
+
+    # Assemble the source.
+    echo "java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMDIR}/${f}.obj ${ASMDIR}/${f}.sym"
+    java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMDIR}/${f}.obj ${ASMDIR}/${f}.sym
+
+    # On successful compile, perform post actions else go onto next build.
+    #
+    if [ $? = 0 ]
+    then
+        # The object file is binary, no need to link, copy according to build group.
+        if [[ ${BUILDROMLIST} = *"${f}"* ]]; then
+            echo "Copy ${ASMDIR}/${f}.obj to ${ROMDIR}/${f}.rom"
+            cp ${ASMDIR}/${f}.obj ${ROMDIR}/${f}.rom
+        else
+            echo "Copy ${ASMDIR}/${f}.obj to ${MZFDIR}/${f}.mzf"
+            cp ${ASMDIR}/${f}.obj ${MZFDIR}/${f}.mzf
+        fi
+    fi
+done
diff --git a/tools/build_meminitfiles.sh b/tools/build_meminitfiles.sh
new file mode 100755
index 0000000..e21950d
--- /dev/null
+++ b/tools/build_meminitfiles.sh
@@ -0,0 +1,101 @@
+#!/bin/bash
+#########################################################################################################
+##
+## Name:            build_meminitfiles.sh
+## Created:         August 2018
+## Author(s):       Philip Smart
+## Description:     Sharp MZ series combined rom build script.
+##                  This script takes the necessary ROM files and builds the required combined
+##                  rom files for the emulator and converts them to MIF format.
+##                  Change the names below if you want this script to build combined MIF files with
+##                  different content.
+##
+## Credits:         
+## Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+##
+## History:         August 2018   - Initial script written.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+ROMTOOL=../tools/romtool.pl
+ROMDIR=../software/roms
+MIFDIR=../software/mif
+MZFDIR=../software/mzf
+ASMDIR=../software/asm
+
+${ROMTOOL} --command=KEYMAP                                 \
+           --a_keymap=${ROMDIR}/key_80a.rom                 \
+           --b_keymap=${ROMDIR}/key_80b.rom                 \
+           --c_keymap=${ROMDIR}/key_80c.rom                 \
+           --k_keymap=${ROMDIR}/key_80k.rom                 \
+           --7_keymap=${ROMDIR}/key_700.rom                 \
+           --8_keymap=${ROMDIR}/key_700.rom                 \
+           --12_keymap=${ROMDIR}/key_1200.rom               \
+           --20_keymap=${ROMDIR}/key_80b.rom                \
+           --binout=${ROMDIR}/combined_keymap.rom           \
+           --mifout=${MIFDIR}/combined_keymap.mif
+${ROMTOOL} --command=64KRAM                                 \
+           --ramchecker=${MZFDIR}/hi-ramcheck.mzf           \
+           --a_mrom=${ROMDIR}/monitor_SA1510.rom            \
+           --mzf=${MZFDIR}/tapecheck.mzf                    \
+           --binout=${ROMDIR}/combined_mainmemory.rom       \
+           --mifout=${MIFDIR}/combined_mainmemory.mif
+${ROMTOOL} --command=MONROM                                 \
+           --a_mrom=${ROMDIR}/monitor_SA1510.rom            \
+           --b_mrom=${ROMDIR}/IPL.rom                       \
+           --c_mrom=${ROMDIR}/NEWMON.rom                    \
+           --k_mrom=${ROMDIR}/SP1002.rom                    \
+           --7_mrom=${ROMDIR}/monitor_1Z-013A.rom           \
+           --8_mrom=${ROMDIR}/monitor_1Z-013A.rom           \
+           --12_mrom=${ROMDIR}/SP1002.rom                   \
+           --20_mrom=${ROMDIR}/IPL.rom                     \
+           --a_80c_mrom=${ROMDIR}/monitor_80c_SA1510.rom    \
+           --b_80c_mrom=${ROMDIR}/IPL.rom                   \
+           --c_80c_mrom=${ROMDIR}/NEWMON.rom                \
+           --k_80c_mrom=${ROMDIR}/SP1002.rom                \
+           --7_80c_mrom=${ROMDIR}/monitor_80c_1Z-013A.rom   \
+           --8_80c_mrom=${ROMDIR}/monitor_80c_1Z-013A.rom   \
+           --12_80c_mrom=${ROMDIR}/SP1002.rom               \
+           --20_80c_mrom=${ROMDIR}/IPL.rom                  \
+           --a_userrom=${ROMDIR}/userrom.rom                \
+           --b_userrom=${ROMDIR}/userrom.rom                \
+           --c_userrom=${ROMDIR}/userrom.rom                \
+           --k_userrom=${ROMDIR}/userrom.rom                \
+           --7_userrom=${ROMDIR}/userrom.rom                \
+           --8_userrom=${ROMDIR}/userrom.rom                \
+           --12_userrom=${ROMDIR}/userrom.rom               \
+           --20_userrom=${ROMDIR}/userrom.rom               \
+           --a_fdcrom=${ROMDIR}/fdcrom.rom                  \
+           --b_fdcrom=${ROMDIR}/fdcrom.rom                  \
+           --c_fdcrom=${ROMDIR}/fdcrom.rom                  \
+           --k_fdcrom=${ROMDIR}/fdcrom.rom                  \
+           --7_fdcrom=${ROMDIR}/fdcrom.rom                  \
+           --8_fdcrom=${ROMDIR}/fdcrom.rom                  \
+           --12_fdcrom=${ROMDIR}/fdcrom.rom                 \
+           --20_fdcrom=${ROMDIR}/fdcrom.rom                 \
+           --binout=${ROMDIR}/combined_mrom.rom             \
+           --mifout=${MIFDIR}/combined_mrom.mif
+${ROMTOOL} --command=CGROM                                  \
+           --a_cgrom=${ROMDIR}/mz-80acg.rom                 \
+           --b_cgrom=${ROMDIR}/MZFONT.rom                   \
+           --c_cgrom=${ROMDIR}/MZ80K_cgrom.rom              \
+           --k_cgrom=${ROMDIR}/MZ80K_cgrom.rom              \
+           --7_cgrom=${ROMDIR}/MZ700_cgrom.rom              \
+           --8_cgrom=${ROMDIR}/MZ700_cgrom.rom              \
+           --12_cgrom=${ROMDIR}/mz-80acg.rom                \
+           --20_cgrom=${ROMDIR}/MZFONT.rom                  \
+           --binout=${ROMDIR}/combined_cgrom.rom            \
+           --mifout=${MIFDIR}/combined_cgrom.mif
diff --git a/tools/dz80 b/tools/dz80
new file mode 100755
index 0000000..bc59a66
Binary files /dev/null and b/tools/dz80 differ
diff --git a/tools/elfsplitter b/tools/elfsplitter
new file mode 100755
index 0000000..9acbf4c
Binary files /dev/null and b/tools/elfsplitter differ
diff --git a/tools/elfsplitter.sol b/tools/elfsplitter.sol
new file mode 100755
index 0000000..4ba8174
Binary files /dev/null and b/tools/elfsplitter.sol differ
diff --git a/tools/glass.jar b/tools/glass.jar
new file mode 100755
index 0000000..7cb301c
Binary files /dev/null and b/tools/glass.jar differ
diff --git a/tools/mzftool.pl b/tools/mzftool.pl
new file mode 100755
index 0000000..aa70ada
--- /dev/null
+++ b/tools/mzftool.pl
@@ -0,0 +1,665 @@
+#! /usr/bin/perl
+#########################################################################################################
+##
+## Name:            mzftool.pl
+## Created:         August 2018
+## Author(s):       Philip Smart
+## Description:     Sharp MZ series MZF (Sharp Tape File)  management tool.
+##                  This script identifies the type of MZF file and can add or delete headers as required.
+##                  Useful for seperating MZF compilations into Basic/Pascal/Machine Code etc.
+##                  Also useful to add headers to homegrow machine code programs.
+##
+## Credits:         
+## Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+##
+## History:         August 2018   - Initial script written.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+# Title and Versioning.
+#
+$TITLE                  = "MZF Tool";
+$VERSION                = "0.1";
+$VERSIONDATE            = "25.09.2018";
+
+# Global Modules.
+#
+#use strict
+use Getopt::Long;
+use IO::File;
+use File::stat;
+use File::Copy;
+use Time::localtime;
+use POSIX qw(tmpnam);
+use Env qw(KPLUSHOME3 SYBASE SYBASE_OCS DSQUERY);
+use sigtrap qw(die normal-signals);
+
+# Error return codes.
+#
+$ERR_BADFILENAME        = 1;
+$ERR_BADFILEDATA        = 2;
+$ERR_BADFILECREATE      = 3;
+$ERR_BADFUNCARGS        = 4;
+$ERR_BADSYSCALL         = 5;
+$ERR_BADCHECK           = 6;
+$ERR_BADENV             = 7;
+$ERR_SYBSERVER          = 8;
+$ERR_BADARGUMENTS       = 9;
+
+# Run-time constants.
+#
+$PROGNAME               = $0;
+
+# Run-time globals. Although in Perl you can just specify variables, keeping with most
+# high-order languages it is good practise to  specify non-local variables in a global header
+# which aids visual variable tracking etc.
+#
+$dbh                    = 0;                        # Handle to a Sybase object.
+$logh                   = 0;                        # Handle to open log file.
+$logName                = "";                       # Temporary name of log file.
+$logMode                = "terminal";               # Default logging mode for logger.
+
+
+# Configurables!!
+#
+$SENDMAIL               = "/usr/lib/sendmail -t";
+@errorMailRecipients    = ( "philip.smart\@net2net.org" );
+$errorMailFrom          = "error\@localhost";
+$errorMailSubject       = "MZF Tool Errors...";
+$PERL                   = "perl";
+$PERLFLAGS              = "";
+
+
+##################################################################################
+# GENERIC SUB-ROUTINES
+##################################################################################
+
+# Sub-routine to close the log file and email its contents to required participants.
+#
+sub logClose
+{
+    # Locals.
+    local( $idx, $line, @mailRecipients, $mailFrom, $mailSubject, $mailHeader );
+
+    # No point closing log if one wasnt created!!
+    #
+    if($logName eq "" || $sendEmail == 0)
+    {
+        return;
+    }
+
+    # Back to beginning of file, to copy into email.
+    #
+    seek($logh, 0, 0);
+
+    # Build up an email to required recipients and send.
+    #
+    open(SENDMAIL, "|$SENDMAIL") or die "Cannot open $SENDMAIL: $!";
+    for($idx=0; $idx < @errorMailRecipients; $idx++)
+    {
+        print SENDMAIL "To: $errorMailRecipients[$idx]\n";
+    }
+    print SENDMAIL "Reply-to: $errorMailFrom\n";
+    print SENDMAIL "From: $errorMailFrom\n";
+    print SENDMAIL "Subject: $errorMailSubject\n";
+    print SENDMAIL "Content-type: text/plain\n\n";
+    while( $line = <$logh> )
+    {
+        chomp($line);
+        print SENDMAIL "$line\n";
+    }
+    close(SENDMAIL);
+
+    # Delete the logfile, not needed.
+    #
+    unlink($logName) or die "Couldn't unlink Error File $logName : $!";
+}
+
+# Function to write a message into a log file. The logfile is a temporary buffer, used
+# to store all messages until program end. Upon completion, the buffer is emailed to required
+# participants.
+#
+sub logWrite
+{
+    # Get parameters, define locals.
+    local( $mode, $text ) = @_;
+    local( $date );
+
+    # Get current date and time for timestamping the log message.
+    #
+    $date = `date +'%Y.%m.%d %H:%M:%S'`;
+    chomp($date);
+
+    # In terminal mode (=interactive mode), always log to STDOUT.
+    #
+    if($logMode eq "terminal")
+    {
+        if(index($mode, "ND") == -1)
+        {
+            print "$date ";
+        }
+        print "$text";
+        if(index($mode, "NR") == -1)
+        {
+            print "\n";
+        }
+
+        # Die if required.
+        #
+        if (index($mode, 'die') != -1)
+        {
+            print "$date Terminating at program request.\n";
+            exit 1;
+        }
+        return;
+    }
+
+    # If the logfile hasnt been opened, open it.
+    #
+    if($logName eq "")
+    {
+        # Try new temporary filenames until we get one that doesnt already exist.
+        do {
+            $logName = tmpnam();
+        } until $logh = IO::File->new($logName, O_RDWR|O_CREAT|O_EXCL);
+
+        # Automatically flush out log.
+        $logh->autoflush(1);
+
+        # Only send email if we explicitly die.
+        #
+        $sendEmail = 0;
+
+        # Install an atexit-style handler so that when we exit or die,
+        # we automatically dispatch the log.
+        END { logClose($logh, $logName); }
+    }
+
+    # Print to log with date and time stamp.
+    #
+    print $logh "$date $text\n";
+
+    # Print to stdout for user view if in debug mode.
+    #
+    if($debugMode > 0)
+    {
+        print "$date $text\n";
+    }
+
+    # If requested, log termination message and abort program.
+    #
+    if (index($mode, 'die') != -1)
+    {
+        print $logh "$date Terminating at program request.\n";
+        $sendEmail = 1;
+        exit 1;
+    }
+}
+
+# Sub-routine to truncate whitespace at the front (left) of a string, returning the
+# truncated string.
+#
+sub cutWhiteSpace
+{
+    local( $srcString ) = @_;
+    local( $c, $dstString, $idx );
+    $dstString = "";
+
+    for($idx=0; $idx < length($srcString); $idx++)
+    {
+        # If the character is a space or tab, delete.
+        #
+        $c = substr($srcString, $idx, 1);
+        if(length($dstString) == 0)
+        {
+            if($c ne " " && $c ne "\t")
+            {
+                $dstString = $dstString . $c;
+            }
+        } else
+        {
+            $dstString = $dstString . $c;
+        }
+    }
+    return($dstString);
+}
+
+# Perl trim function to remove whitespace from the start and end of the string
+#
+sub trim($)
+{
+    my $string = shift;
+    $string =~ s/^\s+//;
+    $string =~ s/\s+$//;
+    return $string;
+}
+
+# Left trim function to remove leading whitespace
+#
+sub ltrim($)
+{
+    my $string = shift;
+    $string =~ s/^\s+//;
+    return $string;
+}
+
+# Right trim function to remove trailing whitespace
+#
+sub rtrim($)
+{
+    my $string = shift;
+    $string =~ s/\s+$//;
+    return $string;
+}
+
+# Sub-routine to test if a string is empty, and if so, replace
+# with an alternative string. The case of the returned string
+# can be adjusted according to the $convertCase parameter.
+#
+sub trString
+{
+    local( $tstString, $replaceString, $convertCase ) = @_;
+    local( $dstString );
+
+    $tstString=cutWhitespace($tstString);
+    $replaceString=cutWhitespace($replaceString);
+    if($tstString eq "")
+    {
+        $dstString = $replaceString;
+    } else
+    {
+        $dstString = $tstString;
+    }
+
+    # Convert to Lower Case?
+    #
+    if($convertCase == 1)
+    {
+        $dstString =~ lc($dstString);
+    }
+    # Convert to Upper Case?
+    #
+    elsif($convertCase == 2)
+    {
+        $dstString =~ uc($dstString);
+    }
+    return($dstString);
+}
+
+# Sub-routine to test if a numeric is empty, and if so, set to a
+# given value.
+#
+sub trNumeric
+{
+    local( $tstNumber, $replaceNumber ) = @_;
+    local( $dstNumber );
+
+    if(!defined($tstNumber) || $tstNumber eq "" || cutWhitespace($tstNumber) eq "")
+    {
+        $dstNumber = $replaceNumber;
+    } else
+    {
+        $dstNumber = $tstNumber;
+    }
+
+    return($dstNumber);
+}
+
+# Function to look at a string and decide wether its contents
+# indicate Yes or No. If the subroutine cannot determine a Yes,
+# then it defaults to No.
+#
+sub yesNo
+{
+    local( $srcString ) = @_;
+    local( $dstString, $yesNo );
+    $yesNo = "N";
+
+    $dstString=lc(cutWhiteSpace($srcString));
+    if($dstString eq "y" || $dstString eq "yes" || $dstString eq "ye")
+    {
+        $yesNo = "Y";
+    }
+    return( $yesNo );
+}
+
+# Sub-routine to encrypt an input string, typically a password,
+# using the Collateral Management Encrypt utility.
+#
+sub encrypt
+{
+    local( $srcPasswd ) = @_;
+    local( $encPasswd );
+    $encPasswd="";
+
+    # Call external function to perform the encryption.
+    #
+    if($srcPasswd ne "")
+    {
+        $encPasswd=`$PROG_ENCRYPT -p $srcPasswd 2>&1`;
+        chomp($encPasswd);
+    }
+    return($encPasswd);
+}
+
+# Sub-routine to test if a string is empty, and if so, replace
+# with an alternative string. The case of the returned string
+# can be adjusted according to the $convertCase parameter.
+#
+sub testAndReplace
+{
+    local( $tstString, $replaceString, $convertCase ) = @_;
+    local( $dstString );
+#printf("Input:$tstString,$replaceString\n");
+    $tstString=cutWhiteSpace($tstString);
+    $replaceString=cutWhiteSpace($replaceString);
+    if($tstString eq "")
+    {
+        $dstString = $replaceString;
+    } else
+    {
+        $dstString = $tstString;
+    }
+
+    # Convert to Lower Case?
+    #
+    if($convertCase == 1)
+    {
+        $dstString =~ lc($dstString);
+    }
+    # Convert to Upper Case?
+    #
+    elsif($convertCase == 2)
+    {
+        $dstString =~ uc($dstString);
+    }
+#printf("Output:$dstString:\n");
+    return($dstString);
+}
+
+# Subroutine to generate a unique name by adding 2 digits onto the end of it. A hash of existing
+# names is given to compare the new value against.
+#
+sub getUniqueName
+{
+    local( $cnt, $uniqueName ) = ( 0, "" );
+    local( $startName, $maxLen, $usedNames ) = @_;
+
+    # Go through looping, adding a unique number onto the end of the string, then looking it
+    # up to see if it already exists.
+    #
+    $uniqueName = substr($startName, 0, $maxLen);
+    while(defined($$usedNames{$uniqueName}))
+    {
+        $uniqueName = substr($uniqueName, 0, $maxLen-2) . sprintf("%02d", $cnt);
+        $cnt++;
+        if($cnt > 99)
+        {
+            logWrite("die", "Unique identifier > 99: $uniqueName");
+        }
+    }
+
+    # Return unique name.
+    #
+    return($uniqueName);
+}
+
+# Sub-routine to process command line arguments. New style POSIX argument format used.
+#
+sub argOptions
+{
+    local ( $writeUsage, $msg, $exitCode ) = @_;
+
+    if( $writeUsage == 1 )
+    {
+        print STDOUT "Usage: $PROGNAME <commands> [<options>]                                     \n";
+        print STDOUT "           commands= --help                                                |\n";
+        print STDOUT "                     --verbose                                             |\n";
+        print STDOUT "                     --command=<IDENT|ADDHEADER|DELHEADER>                 |\n";
+        print STDOUT "                     --mzffile=<file>          {IDENT|ADDHEADER|DELHEADER} |\n";
+        print STDOUT "                     --srcfile=<file>                        {ADDHEADER}   |\n";
+        print STDOUT "                     --dstfile=<file>                        {DELHEADER}   |\n";
+        print STDOUT "                     --filename=<name of tape file>          (ADDHEADER}   |\n";
+        print STDOUT "                     --loadaddr=<addr tape should load @>    (ADDHEADER}   |\n";
+        print STDOUT "                     --execaddr=<auto exec addr>             (ADDHEADER}   |\n";
+        print STDOUT "                     --tapetype=<1 byte type value>          (ADDHEADER}   |\n";
+        print STDOUT "                     --comment=<comment string>              (ADDHEADER}   |\n";
+        print STDOUT "           options = --debug=<1=ON, 0=OFF>\n";
+        print STDOUT "\n";
+    }
+    if($msg ne "")
+    {
+        print STDOUT "Error: $msg\n";
+    }
+    exit( $exitCode );
+}
+
+
+##################################################################################
+# END OF GENERIC SUB-ROUTINES
+##################################################################################
+
+
+##################################################################################
+#
+# MAIN PROGRAM
+#
+##################################################################################
+
+# Locals.
+#
+local( $time, $date, $mzfExists, $a_mromExists, $b_mromExists, $k_mromExists, $m7_mromExists, $m8_mromExists, $m12_mromExists, $m20_mromExists,
+       $a_80c_mromExists, $b_80c_mromExists, $k_80c_mromExists, $m7_80c_mromExists, $m8_80c_mromExists, $m12_80c_mromExists, $m20_80c_mromExists,
+       $mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr, $mzf_comment);
+
+# Get current time and date.
+#
+$time = `date +'%H:%M:%S'`;
+$date = `date +'%d.%m.%Y'`;
+chomp($time);
+chomp($date);
+
+# Sign-on.
+#
+print STDOUT "$TITLE (v$VERSION) \@ ${VERSIONDATE}\n\n";
+
+# Parse arguments and put into required variables.
+#
+$verbose = 0;
+$fileName = "";
+$s_loadAddr = "";
+$s_execAddr = "";
+$s_tapeType = "";
+$comment = "";
+GetOptions( "debug=n"               => \$debugMode,            # Debug Mode?
+            "verbose"               => \$verbose,              # Show details?
+            "mzffile=s"             => \$mzfFile,              # MZF file.
+            "dstfile=s"             => \$dstFile,              # Destination file (for header removal).
+            "srcfile=s"             => \$srcFile,              # Source file (for header adding).
+            "filename=s"            => \$fileName,             # Filename to insert into header.
+            "loadaddr=s"            => \$s_loadAddr,           # Tape load address.
+            "execaddr=s"            => \$s_execAddr,           # Tape execution address.
+            "tapetype=s"            => \$s_tapeType,           # Tape type (ie. 01 = Machine Code).
+            "comment=s"             => \$comment,              # Tape comment string.
+            "command=s"             => \$command,              # Command to execute.
+            "help"                  => \$help,                 # Help required on commands/options?
+          );
+
+# Help required?
+#
+if(defined($help))
+{
+    argOptions(1, "");
+} 
+
+# Convert number arguments from string to decimal.
+#
+if($s_loadAddr ne "")
+{
+    $loadAddr = oct($s_loadAddr);
+}
+if($s_execAddr ne "")
+{
+    $execAddr = oct($s_execAddr);
+}
+if($s_tapeType ne "")
+{
+    $tapeType = oct($s_tapeType);
+}
+
+# Verify command.
+#
+if($command eq "IDENT" || $command eq "ADDHEADER" || $command eq "DELHEADER")
+{
+    1;
+}
+else
+{
+    argOptions(1, "Illegal command given on command line:$command.\n",$ERR_BADARGUMENTS);
+}
+
+# Check that the additional parameters have been provided for the ADDHEADER command.
+if($command eq "ADDHEADER" && ($fileName eq "" || !defined($loadAddr) || !defined($execAddr) || !defined($tapeType)) )
+{
+    argOptions(3, "ADDHEADER command requires the following parameters to be provided: --filename, --loadaddr, --execaddr, --tapetype\n",$ERR_BADARGUMENTS);
+}
+
+# For ident or delete header commands, we need to open and read the mzf file.
+#
+if(($command eq "IDENT" || $command eq "DELHEADER") && defined($mzfFile) && $mzfFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( ! open(MZFFILE, "<".$mzfFile) )
+    {
+        argOptions(1, "Cannot open MZF file: $mzfFile.\n",$ERR_BADFILENAME);
+    }
+
+    @MZF = ();
+    binmode(MZFFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <MZFFILE> )
+    {
+        $MZF[$cnt] = $byte;
+        $cnt++;
+    }
+    $MZF_SIZE = $cnt;
+
+    # Once the MZF is in memory, analyse the details and output.
+    #
+    $mzf_header = pack('a'x128, @MZF);
+    ($mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr, $mzf_comment) = unpack 'c1 a17 v4 v4 v4 a104', $mzf_header;
+    $mzf_filename =~ s/\r|\n//g;
+
+    # Output detail if requested.
+    #
+    if($verbose)
+    {
+        printf STDOUT "File Name          : %s\n",   $mzf_filename;
+        printf STDOUT "File Type          : %02x\n", $mzf_type;
+        printf STDOUT "File Size          : %04x\n", $mzf_size;
+        printf STDOUT "File Load Address  : %04x\n", $mzf_loadaddr;
+        printf STDOUT "File Exec Address  : %04x\n", $mzf_execaddr;
+        printf STDOUT "Comment            : %s\n",   $mzf_comment;
+    }
+
+    # For the DELHEADER command, a destination needs to be provided and opened.
+    if($command eq "DELHEADER" && defined($dstFile) && $dstFile ne "")
+    {
+        if( ! open(DSTFILE, ">".$dstFile) )
+        {
+            argOptions(1, "Cannot open the destination file: $dstFile.\n",$ERR_BADFILENAME);
+        }
+    }
+} 
+elsif($command eq "ADDHEADER" && defined($mzfFile) && $mzfFile ne "") 
+{
+    # If defined, can we create it?
+    #
+    if( ! open(MZFFILE, ">".$mzfFile) )
+    {
+        argOptions(1, "Cannot create MZF file: $mzfFile.\n",$ERR_BADFILENAME);
+    }
+
+    # For this command, a source file needs to exist and opened.
+    if(defined($srcFile) && $srcFile ne "")
+    {
+        if( ! open(SRCFILE, "<".$srcFile) )
+        {
+            argOptions(1, "Cannot open the source file: $srcFile.\n",$ERR_BADFILENAME);
+        }
+
+        @SRC = ();
+        binmode(SRCFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <SRCFILE> )
+        {
+            $SRC[$cnt] = $byte;
+            $cnt++;
+        }
+        $SRC_SIZE = $cnt;
+    }
+}
+else
+{
+    argOptions(2, "No MZF file given, use --mzffile=<file>.\n");
+}
+
+# Process command as necessary.
+#
+if($command eq "ADDHEADER")
+{
+    # Build the header based on given information and size of src file.
+    $mzf_size = scalar @SRC;
+    $mzf_type = $tapeType; # For exit code.
+    $mzf_header  = pack('c1 a17 v v v', $tapeType, $fileName, $mzf_size, $loadAddr, $execAddr);
+    $mzf_header .=  pack('a104', $comment) ;
+
+    # Store in file.
+    print MZFFILE $mzf_header;
+    
+    # Now add the source data.
+    foreach my $byte (@SRC) { print MZFFILE $byte; }
+
+    # All done.
+    close MZFFILE;
+
+    # Output detail if requested.
+    #
+    if($verbose)
+    {
+        printf STDOUT "File Name          : %s\n",   $fileName;
+        printf STDOUT "File Type          : %02x\n", $tapeType;
+        printf STDOUT "File Size          : %04x\n", $mzf_size;
+        printf STDOUT "File Load Address  : %04x\n", $loadAddr;
+        printf STDOUT "File Exec Address  : %04x\n", $execAddr;
+        printf STDOUT "Comment            : %s\n",   $comment;
+    }
+}
+# For delete, simply write out the tape contents less the header (first 128 bytes).
+elsif($command eq "DELHEADER")
+{
+    my $cnt = 0;
+    foreach my $byte (@MZF) { if($cnt++ >= 128) { print DSTFILE $byte; } }
+    close DSTFILE;
+}
+
+# Exit code is the type of MZF file.
+exit $mzf_type;
diff --git a/tools/romtool.pl b/tools/romtool.pl
new file mode 100755
index 0000000..b0ec91f
--- /dev/null
+++ b/tools/romtool.pl
@@ -0,0 +1,2813 @@
+#! /usr/bin/perl
+#########################################################################################################
+##
+## Name:            romtool.pl
+## Created:         July 2018
+## Author(s):       Philip Smart
+## Description:     Sharp MZ series rom management tool.
+##                  This script takes a set of roms and creates the necessary MIF image for embedding
+##                  into the FPGA during compilation.
+##                  It can also be used to create a binary image if needed for upload via the HPS.
+##
+## Credits:         
+## Copyright:       (c) 2018 Philip Smart <philip.smart@net2net.org>
+##
+## History:         July 2018   - Initial script written.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+# Title and Versioning.
+#
+$TITLE                  = "ROM Tool";
+$VERSION                = "0.5";
+$VERSIONDATE            = "12.10.2018";
+
+# Global Modules.
+#
+#use strict
+use Getopt::Long;
+use IO::File;
+use File::stat;
+use File::Copy;
+use Time::localtime;
+use POSIX qw(tmpnam);
+use Env qw(KPLUSHOME3 SYBASE SYBASE_OCS DSQUERY);
+use sigtrap qw(die normal-signals);
+
+# Error return codes.
+#
+$ERR_BADFILENAME        = 1;
+$ERR_BADFILEDATA        = 2;
+$ERR_BADFILECREATE      = 3;
+$ERR_BADFUNCARGS        = 4;
+$ERR_BADSYSCALL         = 5;
+$ERR_BADCHECK           = 6;
+$ERR_BADENV             = 7;
+$ERR_SYBSERVER          = 8;
+$ERR_BADARGUMENTS       = 9;
+
+# Run-time constants.
+#
+$PROGNAME               = $0;
+
+# Run-time globals. Although in Perl you can just specify variables, keeping with most
+# high-order languages it is good practise to  specify non-local variables in a global header
+# which aids visual variable tracking etc.
+#
+$dbh                    = 0;                        # Handle to a Sybase object.
+$logh                   = 0;                        # Handle to open log file.
+$logName                = "";                       # Temporary name of log file.
+$logMode                = "terminal";               # Default logging mode for logger.
+
+
+# Configurables!!
+#
+$SENDMAIL               = "/usr/lib/sendmail -t";
+@errorMailRecipients    = ( "philip.smart\@net2net.org" );
+$errorMailFrom          = "error\@localhost";
+$errorMailSubject       = "Rom tool patch Errors...";
+$PERL                   = "perl";
+$PERLFLAGS              = "";
+
+
+##################################################################################
+# GENERIC SUB-ROUTINES
+##################################################################################
+
+# Sub-routine to close the log file and email its contents to required participants.
+#
+sub logClose
+{
+    # Locals.
+    local( $idx, $line, @mailRecipients, $mailFrom, $mailSubject, $mailHeader );
+
+    # No point closing log if one wasnt created!!
+    #
+    if($logName eq "" || $sendEmail == 0)
+    {
+        return;
+    }
+
+    # Back to beginning of file, to copy into email.
+    #
+    seek($logh, 0, 0);
+
+    # Build up an email to required recipients and send.
+    #
+    open(SENDMAIL, "|$SENDMAIL") or die "Cannot open $SENDMAIL: $!";
+    for($idx=0; $idx < @errorMailRecipients; $idx++)
+    {
+        print SENDMAIL "To: $errorMailRecipients[$idx]\n";
+    }
+    print SENDMAIL "Reply-to: $errorMailFrom\n";
+    print SENDMAIL "From: $errorMailFrom\n";
+    print SENDMAIL "Subject: $errorMailSubject\n";
+    print SENDMAIL "Content-type: text/plain\n\n";
+    while( $line = <$logh> )
+    {
+        chomp($line);
+        print SENDMAIL "$line\n";
+    }
+    close(SENDMAIL);
+
+    # Delete the logfile, not needed.
+    #
+    unlink($logName) or die "Couldn't unlink Error File $logName : $!";
+}
+
+# Function to write a message into a log file. The logfile is a temporary buffer, used
+# to store all messages until program end. Upon completion, the buffer is emailed to required
+# participants.
+#
+sub logWrite
+{
+    # Get parameters, define locals.
+    local( $mode, $text ) = @_;
+    local( $date );
+
+    # Get current date and time for timestamping the log message.
+    #
+    $date = `date +'%Y.%m.%d %H:%M:%S'`;
+    chomp($date);
+
+    # In terminal mode (=interactive mode), always log to STDOUT.
+    #
+    if($logMode eq "terminal")
+    {
+        if(index($mode, "ND") == -1)
+        {
+            print "$date ";
+        }
+        print "$text";
+        if(index($mode, "NR") == -1)
+        {
+            print "\n";
+        }
+
+        # Die if required.
+        #
+        if (index($mode, 'die') != -1)
+        {
+            print "$date Terminating at program request.\n";
+            exit 1;
+        }
+        return;
+    }
+
+    # If the logfile hasnt been opened, open it.
+    #
+    if($logName eq "")
+    {
+        # Try new temporary filenames until we get one that doesnt already exist.
+        do {
+            $logName = tmpnam();
+        } until $logh = IO::File->new($logName, O_RDWR|O_CREAT|O_EXCL);
+
+        # Automatically flush out log.
+        $logh->autoflush(1);
+
+        # Only send email if we explicitly die.
+        #
+        $sendEmail = 0;
+
+        # Install an atexit-style handler so that when we exit or die,
+        # we automatically dispatch the log.
+        END { logClose($logh, $logName); }
+    }
+
+    # Print to log with date and time stamp.
+    #
+    print $logh "$date $text\n";
+
+    # Print to stdout for user view if in debug mode.
+    #
+    if($debugMode > 0)
+    {
+        print "$date $text\n";
+    }
+
+    # If requested, log termination message and abort program.
+    #
+    if (index($mode, 'die') != -1)
+    {
+        print $logh "$date Terminating at program request.\n";
+        $sendEmail = 1;
+        exit 1;
+    }
+}
+
+# Sub-routine to truncate whitespace at the front (left) of a string, returning the
+# truncated string.
+#
+sub cutWhiteSpace
+{
+    local( $srcString ) = @_;
+    local( $c, $dstString, $idx );
+    $dstString = "";
+
+    for($idx=0; $idx < length($srcString); $idx++)
+    {
+        # If the character is a space or tab, delete.
+        #
+        $c = substr($srcString, $idx, 1);
+        if(length($dstString) == 0)
+        {
+            if($c ne " " && $c ne "\t")
+            {
+                $dstString = $dstString . $c;
+            }
+        } else
+        {
+            $dstString = $dstString . $c;
+        }
+    }
+    return($dstString);
+}
+
+# Perl trim function to remove whitespace from the start and end of the string
+#
+sub trim($)
+{
+    my $string = shift;
+    $string =~ s/^\s+//;
+    $string =~ s/\s+$//;
+    return $string;
+}
+
+# Left trim function to remove leading whitespace
+#
+sub ltrim($)
+{
+    my $string = shift;
+    $string =~ s/^\s+//;
+    return $string;
+}
+
+# Right trim function to remove trailing whitespace
+#
+sub rtrim($)
+{
+    my $string = shift;
+    $string =~ s/\s+$//;
+    return $string;
+}
+
+# Sub-routine to test if a string is empty, and if so, replace
+# with an alternative string. The case of the returned string
+# can be adjusted according to the $convertCase parameter.
+#
+sub trString
+{
+    local( $tstString, $replaceString, $convertCase ) = @_;
+    local( $dstString );
+
+    $tstString=cutWhitespace($tstString);
+    $replaceString=cutWhitespace($replaceString);
+    if($tstString eq "")
+    {
+        $dstString = $replaceString;
+    } else
+    {
+        $dstString = $tstString;
+    }
+
+    # Convert to Lower Case?
+    #
+    if($convertCase == 1)
+    {
+        $dstString =~ lc($dstString);
+    }
+    # Convert to Upper Case?
+    #
+    elsif($convertCase == 2)
+    {
+        $dstString =~ uc($dstString);
+    }
+    return($dstString);
+}
+
+# Sub-routine to test if a numeric is empty, and if so, set to a
+# given value.
+#
+sub trNumeric
+{
+    local( $tstNumber, $replaceNumber ) = @_;
+    local( $dstNumber );
+
+    if(!defined($tstNumber) || $tstNumber eq "" || cutWhitespace($tstNumber) eq "")
+    {
+        $dstNumber = $replaceNumber;
+    } else
+    {
+        $dstNumber = $tstNumber;
+    }
+
+    return($dstNumber);
+}
+
+# Function to look at a string and decide wether its contents
+# indicate Yes or No. If the subroutine cannot determine a Yes,
+# then it defaults to No.
+#
+sub yesNo
+{
+    local( $srcString ) = @_;
+    local( $dstString, $yesNo );
+    $yesNo = "N";
+
+    $dstString=lc(cutWhiteSpace($srcString));
+    if($dstString eq "y" || $dstString eq "yes" || $dstString eq "ye")
+    {
+        $yesNo = "Y";
+    }
+    return( $yesNo );
+}
+
+# Sub-routine to encrypt an input string, typically a password,
+# using the Collateral Management Encrypt utility.
+#
+sub encrypt
+{
+    local( $srcPasswd ) = @_;
+    local( $encPasswd );
+    $encPasswd="";
+
+    # Call external function to perform the encryption.
+    #
+    if($srcPasswd ne "")
+    {
+        $encPasswd=`$PROG_ENCRYPT -p $srcPasswd 2>&1`;
+        chomp($encPasswd);
+    }
+    return($encPasswd);
+}
+
+# Sub-routine to test if a string is empty, and if so, replace
+# with an alternative string. The case of the returned string
+# can be adjusted according to the $convertCase parameter.
+#
+sub testAndReplace
+{
+    local( $tstString, $replaceString, $convertCase ) = @_;
+    local( $dstString );
+#printf("Input:$tstString,$replaceString\n");
+    $tstString=cutWhiteSpace($tstString);
+    $replaceString=cutWhiteSpace($replaceString);
+    if($tstString eq "")
+    {
+        $dstString = $replaceString;
+    } else
+    {
+        $dstString = $tstString;
+    }
+
+    # Convert to Lower Case?
+    #
+    if($convertCase == 1)
+    {
+        $dstString =~ lc($dstString);
+    }
+    # Convert to Upper Case?
+    #
+    elsif($convertCase == 2)
+    {
+        $dstString =~ uc($dstString);
+    }
+#printf("Output:$dstString:\n");
+    return($dstString);
+}
+
+# Subroutine to generate a unique name by adding 2 digits onto the end of it. A hash of existing
+# names is given to compare the new value against.
+#
+sub getUniqueName
+{
+    local( $cnt, $uniqueName ) = ( 0, "" );
+    local( $startName, $maxLen, $usedNames ) = @_;
+
+    # Go through looping, adding a unique number onto the end of the string, then looking it
+    # up to see if it already exists.
+    #
+    $uniqueName = substr($startName, 0, $maxLen);
+    while(defined($$usedNames{$uniqueName}))
+    {
+        $uniqueName = substr($uniqueName, 0, $maxLen-2) . sprintf("%02d", $cnt);
+        $cnt++;
+        if($cnt > 99)
+        {
+            logWrite("die", "Unique identifier > 99: $uniqueName");
+        }
+    }
+
+    # Return unique name.
+    #
+    return($uniqueName);
+}
+
+# Sub-routine to process command line arguments. New style POSIX argument format used.
+#
+sub argOptions
+{
+    local ( $writeUsage, $msg, $exitCode ) = @_;
+
+    if( $writeUsage == 1 )
+    {
+        print STDOUT "Usage: $PROGNAME <commands> [<options>]                                     \n";
+        print STDOUT "           commands= --help                                                |\n";
+        print STDOUT "                     --command=<64KRAM|MONROM|CGROM|KEYMAP>                |\n";
+        print STDOUT "                     --binout=<file>                                       |\n";
+        print STDOUT "                     --mifout=<file>                                       |\n";
+        print STDOUT "                     --a_mrom=<file>                                       |\n";
+        print STDOUT "                     --b_mrom=<file>                                       |\n";
+        print STDOUT "                     --c_mrom=<file>                                       |\n";
+        print STDOUT "                     --k_mrom=<file>                                       |\n";
+        print STDOUT "                     --7_mrom=<file>                                       |\n";
+        print STDOUT "                     --8_mrom=<file>                                       |\n";
+        print STDOUT "                     --12_mrom=<file>                                      |\n";
+        print STDOUT "                     --20_mrom=<file>                                      |\n";
+        print STDOUT "                     --a_80c_mrom=<file>                                   |\n";
+        print STDOUT "                     --b_80c_mrom=<file>                                   |\n";
+        print STDOUT "                     --c_80c_mrom=<file>                                   |\n";
+        print STDOUT "                     --k_80c_mrom=<file>                                   |\n";
+        print STDOUT "                     --7_80c_mrom=<file>                                   |\n";
+        print STDOUT "                     --8_80c_mrom=<file>                                   |\n";
+        print STDOUT "                     --12_80c_mrom=<file>                                  |\n";
+        print STDOUT "                     --20_80c_mrom=<file>                                  |\n";
+        print STDOUT "                     --a_userrom=<file>                                    |\n";
+        print STDOUT "                     --b_userrom=<file>                                    |\n";
+        print STDOUT "                     --c_userrom=<file>                                    |\n";
+        print STDOUT "                     --k_userrom=<file>                                    |\n";
+        print STDOUT "                     --7_userrom=<file>                                    |\n";
+        print STDOUT "                     --8_userrom=<file>                                    |\n";
+        print STDOUT "                     --12_userrom=<file>                                   |\n";
+        print STDOUT "                     --20_userrom=<file>                                   |\n";
+        print STDOUT "                     --a_fdcrom=<file>                                     |\n";
+        print STDOUT "                     --b_fdcrom=<file>                                     |\n";
+        print STDOUT "                     --c_fdcrom=<file>                                     |\n";
+        print STDOUT "                     --k_fdcrom=<file>                                     |\n";
+        print STDOUT "                     --7_fdcrom=<file>                                     |\n";
+        print STDOUT "                     --8_fdcrom=<file>                                     |\n";
+        print STDOUT "                     --12_fdcrom=<file>                                    |\n";
+        print STDOUT "                     --20_fdcrom=<file>                                    |\n";
+        print STDOUT "                     --mzffile=<file>                                      |\n";
+        print STDOUT "                     --ramchecker=<file>                                   |\n";
+        print STDOUT "                     --a_cgrom=<file>                                      |\n";
+        print STDOUT "                     --b_cgrom=<file>                                      |\n";
+        print STDOUT "                     --c_cgrom=<file>                                      |\n";
+        print STDOUT "                     --k_cgrom=<file>                                      |\n";
+        print STDOUT "                     --7_cgrom=<file>                                      |\n";
+        print STDOUT "                     --12_cgrom=<file>                                     |\n";
+        print STDOUT "                     --20_cgrom=<file>                                     |\n";
+        print STDOUT "                     --a_keymap=<file>                                     |\n";
+        print STDOUT "                     --b_keymap=<file>                                     |\n";
+        print STDOUT "                     --c_keymap=<file>                                     |\n";
+        print STDOUT "                     --k_keymap=<file>                                     |\n";
+        print STDOUT "                     --7_keymap=<file>                                     |\n";
+        print STDOUT "                     --8_keymap=<file>                                     |\n";
+        print STDOUT "                     --12_keymap=<file>                                    |\n";
+        print STDOUT "                     --20_keymap=<file>                                    |\n";
+        print STDOUT "           options = --debug=<1=ON, 0=OFF>\n";
+        print STDOUT "\n";
+    }
+    if($msg ne "")
+    {
+        print STDOUT "Error: $msg\n";
+    }
+    exit( $exitCode );
+}
+
+# Subroutine to create a Memory Initialization File.
+#
+sub createMIF
+{
+    local ($Memory, $OUTPUT) = @_;
+#local @Memory = @{$_[0]};
+#    local $OUTPUT = $_[1];
+
+    $addr = 0x0000;
+    $depth = scalar @$Memory;
+    $width = 8;
+
+    print $OUTPUT "DEPTH = $depth;\n";
+    print $OUTPUT "WIDTH = $width;\n";
+    print $OUTPUT "ADDRESS_RADIX = HEX;\n";
+    print $OUTPUT "DATA_RADIX = HEX;\n";
+    print $OUTPUT "CONTENT BEGIN\n";
+
+    for($addr=0; $addr < $depth; $addr+=16)
+    {
+        my $thisLineCount = ($depth > $addr + 16) ? 16 : $depth - $addr;
+        printf $OUTPUT "%04x: ", $addr;
+        $line = "";
+        for(my $byteaddr=0; $byteaddr < $thisLineCount; $byteaddr++)
+        {
+            if($byteaddr > 0) { $line .= " "; }
+            $line .= unpack("H2", @$Memory[$byteaddr + $addr]);
+        }
+        print $OUTPUT "$line;\n";
+    }
+
+    print $OUTPUT "END;\n";
+ }
+
+##################################################################################
+# END OF GENERIC SUB-ROUTINES
+##################################################################################
+
+
+##################################################################################
+#
+# MAIN PROGRAM
+#
+##################################################################################
+
+# Locals.
+#
+local( $time, $date, $mzfExists, $a_mromExists, $b_mromExists, $k_mromExists, $m7_mromExists, $m8_mromExists, $m12_mromExists, $m20_mromExists,
+       $a_80c_mromExists, $b_80c_mromExists, $k_80c_mromExists, $m7_80c_mromExists, $m8_80c_mromExists, $m12_80c_mromExists, $m20_80c_mromExists,
+       $mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr, $mzf_comment);
+
+# Get current time and date.
+#
+$time = `date +'%H:%M:%S'`;
+$date = `date +'%d.%m.%Y'`;
+chomp($time);
+chomp($date);
+
+# Sign-on.
+#
+print STDOUT "$TITLE (v$VERSION) \@ ${VERSIONDATE}\n\n";
+
+# Parse arguments and put into required variables.
+#
+GetOptions( "debug=n"               => \$debugMode,            # Debug Mode?
+            "command=s"             => \$command,              # Command to execute.
+            "binout=s"              => \$outFile,              # Binary output file to be created.
+            "mifout=s"              => \$mifoutFile,           # MIF output file to be created.
+            "a_mrom=s"              => \$modelA_mromFile,      # MZ80A Monitor ROM file.
+            "b_mrom=s"              => \$modelB_mromFile,      # MZ80B Monitor ROM file.
+            "c_mrom=s"              => \$modelC_mromFile,      # MZ80C Monitor ROM file.
+            "k_mrom=s"              => \$modelK_mromFile,      # MZ80K Monitor ROM file.
+            "7_mrom=s"              => \$model7_mromFile,      # MZ700 Monitor ROM file.
+            "8_mrom=s"              => \$model8_mromFile,      # MZ800 Monitor ROM file.
+            "12_mrom=s"             => \$model12_mromFile,     # MZ1200 Monitor ROM file.
+            "20_mrom=s"             => \$model20_mromFile,     # MZ2000 Monitor ROM file.
+            "a_80c_mrom=s"          => \$modelA_80c_mromFile,  # MZ80A Monitor 80x25 Display ROM file.
+            "b_80c_mrom=s"          => \$modelB_80c_mromFile,  # MZ80B Monitor 80x25 Display ROM file.
+            "c_80c_mrom=s"          => \$modelC_80c_mromFile,  # MZ80C Monitor 80x25 Display ROM file.
+            "k_80c_mrom=s"          => \$modelK_80c_mromFile,  # MZ80K Monitor 80x25 Display ROM file.
+            "7_80c_mrom=s"          => \$model7_80c_mromFile,  # MZ700 Monitor 80x25 Display ROM file.
+            "8_80c_mrom=s"          => \$model8_80c_mromFile,  # MZ800 Monitor 80x25 Display ROM file.
+            "12_80c_mrom=s"         => \$model12_80c_mromFile, # MZ1200 Monitor 80x25 Display ROM file.
+            "20_80c_mrom=s"         => \$model20_80c_mromFile, # MZ2000 Monitor 80x25 Display ROM file.
+            "a_userrom=s"           => \$modelA_userromFile,   # MZ80A User ROM file.
+            "b_userrom=s"           => \$modelB_userromFile,   # MZ80B User ROM file.
+            "c_userrom=s"           => \$modelC_userromFile,   # MZ80C User ROM file.
+            "k_userrom=s"           => \$modelK_userromFile,   # MZ80K User ROM file.
+            "7_userrom=s"           => \$model7_userromFile,   # MZ700 User ROM file.
+            "8_userrom=s"           => \$model8_userromFile,   # MZ800 User ROM file.
+            "12_userrom=s"          => \$model12_userromFile,  # MZ1200 User ROM file.
+            "20_userrom=s"          => \$model20_userromFile,  # MZ2000 User ROM file.
+            "a_fdcrom=s"            => \$modelA_fdcromFile,    # MZ80A FDC ROM file.
+            "b_fdcrom=s"            => \$modelB_fdcromFile,    # MZ80B FDC ROM file.
+            "c_fdcrom=s"            => \$modelC_fdcromFile,    # MZ80C FDC ROM file.
+            "k_fdcrom=s"            => \$modelK_fdcromFile,    # MZ80K FDC ROM file.
+            "7_fdcrom=s"            => \$model7_fdcromFile,    # MZ700 FDC ROM file.
+            "8_fdcrom=s"            => \$model8_fdcromFile,    # MZ800 FDC ROM file.
+            "12_fdcrom=s"           => \$model12_fdcromFile,   # MZ1200 User ROM file.
+            "20_fdcrom=s"           => \$model20_fdcromFile,   # MZ2000 User ROM file.
+            "mzffile=s"             => \$mzfFile,              # MZF file.
+            "ramchecker=s"          => \$ramcheckFile,         # Ram Tester program.
+            "a_cgrom=s"             => \$modelA_CGFile,        # Model 80A CG Rom.
+            "b_cgrom=s"             => \$modelB_CGFile,        # Model 80B CG Rom.
+            "c_cgrom=s"             => \$modelC_CGFile,        # Model 80C CG Rom.
+            "k_cgrom=s"             => \$modelK_CGFile,        # Model 80K CG Rom.
+            "7_cgrom=s"             => \$model7_CGFile,        # Model 700 CG Rom.
+            "8_cgrom=s"             => \$model8_CGFile,        # Model 800 CG Rom.
+            "12_cgrom=s"            => \$model12_CGFile,       # Model 1200 CG Rom.
+            "20_cgrom=s"            => \$model20_CGFile,       # Model 2000 CG Rom.
+            "a_keymap=s"            => \$modelA_KeyFile,       # Model 80A Key Map File
+            "b_keymap=s"            => \$modelB_KeyFile,       # Model 80B Key Map File
+            "c_keymap=s"            => \$modelC_KeyFile,       # Model 80C Key Map File
+            "k_keymap=s"            => \$modelK_KeyFile,       # Model 80K Key Map File
+            "7_keymap=s"            => \$model7_KeyFile,       # Model 700 Key Map File
+            "8_keymap=s"            => \$model8_KeyFile,       # Model 800 Key Map File
+            "12_keymap=s"           => \$model12_KeyFile,      # Model 1200 Key Map File
+            "20_keymap=s"           => \$model20_KeyFile,      # Model 2000 Key Map File
+            "help"                  => \$help,                 # Help required on commands/options?
+          );
+
+# Help required?
+#
+if(defined($help))
+{
+    argOptions(1, "");
+} 
+
+# Verify command.
+#
+if($command eq "64KRAM" || $command eq "MONROM" || $command eq "CGROM" || $command eq "KEYMAP")
+{
+    logWrite("", "Creating binary output file for command:$command.");
+}
+else
+{
+    argOptions(1, "Illegal command given on command line:$command.\n",$ERR_BADARGUMENTS);
+}
+
+# Output file.
+# #
+if(defined($outFile) && $outFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $outFile ne "" && ! open(OUTFILE, ">".$outFile) )
+    {
+        argOptions(1, "Cannot create output file: $outFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    argOptions(1, "No output file given.\n",$ERR_BADARGUMENTS);
+}
+binmode(OUTFILE);
+
+# MIF Output file.
+# #
+if(defined($mifoutFile) && $mifoutFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $mifoutFile ne "" && ! open(MIFOUTFILE, ">".$mifoutFile) )
+    {
+        argOptions(1, "Cannot create MIF output file: $mifoutFile.\n",$ERR_BADFILENAME);
+    }
+    $createMIF=1;
+} else
+{
+    $createMIF=0;
+}
+
+# An MZF file is not mandatory, if it exists then we must be able to open and read, if it
+# doesnt exist, zero's will be used in the initialization image.
+#
+if(defined($mzfFile) && $mzfFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $mzfFile ne "" && ! open(MZFFILE, "<".$mzfFile) )
+    {
+        argOptions(1, "Cannot open MZF file: $mzfFile.\n",$ERR_BADFILENAME);
+    }
+
+    $mzfExists = 1;
+} else
+{
+    $mzfExists = 0;
+}
+
+# A Ram Checker program loaded into high memory.
+#
+if(defined($ramcheckFile) && $ramcheckFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $ramcheckFile ne "" && ! open(RAMCHECKFILE, "<".$ramcheckFile) )
+    {
+        argOptions(1, "Cannot open MZF file: $ramcheckFile.\n",$ERR_BADFILENAME);
+    }
+
+    $ramcheckExists = 1;
+} else
+{
+    $ramcheckExists = 0;
+}
+
+# Verify all options, easier to use tool at a later stage when memory of the project fades!!
+#
+if(defined($modelA_mromFile) && $modelA_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelA_mromFile ne "" && ! open(A_MROMFILE, "<".$modelA_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $modelA_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $a_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80A Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $a_mromExists = 0;
+}
+if(defined($modelB_mromFile) && $modelB_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelB_mromFile ne "" && ! open(B_MROMFILE, "<".$modelB_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $modelB_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $b_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80B Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $b_mromExists = 0;
+}
+if(defined($modelC_mromFile) && $modelC_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelC_mromFile ne "" && ! open(C_MROMFILE, "<".$modelC_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $modelC_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80C Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $c_mromExists = 0;
+}
+if(defined($modelK_mromFile) && $modelK_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelK_mromFile ne "" && ! open(K_MROMFILE, "<".$modelK_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $modelK_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $k_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80K Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $k_mromExists = 0;
+}
+if(defined($model7_mromFile) && $model7_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model7_mromFile ne "" && ! open(M7_MROMFILE, "<".$model7_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $model7_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m7_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ700 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m7_mromExists = 0;
+}
+if(defined($model8_mromFile) && $model8_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model8_mromFile ne "" && ! open(M8_MROMFILE, "<".$model8_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $model8_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m8_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ800 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m8_mromExists = 0;
+}
+if(defined($model12_mromFile) && $model12_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model12_mromFile ne "" && ! open(M12_MROMFILE, "<".$model12_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $model12_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m12_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ1200 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m12_mromExists = 0;
+}
+if(defined($model20_mromFile) && $model20_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model20_mromFile ne "" && ! open(M20_MROMFILE, "<".$model20_mromFile) )
+    {
+        argOptions(1, "Cannot open Monitor ROM file: $model20_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m20_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ2000 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m20_mromExists = 0;
+}
+#
+if(defined($modelA_80c_mromFile) && $modelA_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelA_80c_mromFile ne "" && ! open(A_80C_MROMFILE, "<".$modelA_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $modelA_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $a_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80A 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $a_80c_mromExists = 0;
+}
+if(defined($modelB_80c_mromFile) && $modelB_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelB_80c_mromFile ne "" && ! open(B_80C_MROMFILE, "<".$modelB_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $modelB_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $b_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80B 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $b_80c_mromExists = 0;
+}
+if(defined($modelC_80c_mromFile) && $modelC_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelC_80c_mromFile ne "" && ! open(C_80C_MROMFILE, "<".$modelC_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $modelC_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $c_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80C 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $c_80c_mromExists = 0;
+}
+if(defined($modelK_80c_mromFile) && $modelK_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelK_80c_mromFile ne "" && ! open(K_80C_MROMFILE, "<".$modelK_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $modelK_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $k_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80K 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $k_80c_mromExists = 0;
+}
+if(defined($model7_80c_mromFile) && $model7_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model7_80c_mromFile ne "" && ! open(M7_80C_MROMFILE, "<".$model7_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $model7_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m7_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ700 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m7_80c_mromExists = 0;
+}
+if(defined($model8_80c_mromFile) && $model8_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model8_80c_mromFile ne "" && ! open(M8_80C_MROMFILE, "<".$model8_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $model8_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m8_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ700 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m8_80c_mromExists = 0;
+}
+if(defined($model12_80c_mromFile) && $model12_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model12_80c_mromFile ne "" && ! open(M12_80C_MROMFILE, "<".$model12_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $model12_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m12_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ1200 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m12_80c_mromExists = 0;
+}
+if(defined($model20_80c_mromFile) && $model20_80c_mromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model20_80c_mromFile ne "" && ! open(M20_80C_MROMFILE, "<".$model20_80c_mromFile) )
+    {
+        argOptions(1, "Cannot open 80x25 Monitor ROM file: $model20_80c_mromFile.\n",$ERR_BADFILENAME);
+    }
+    $m20_80c_mromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ1200 80x25 Monitor ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m20_80c_mromExists = 0;
+}
+#
+# User Rom
+#
+if(defined($modelA_userromFile) && $modelA_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelA_userromFile ne "" && ! open(A_USERROMFILE, "<".$modelA_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $modelA_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $a_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80A User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $a_userromExists = 0;
+}
+if(defined($modelB_userromFile) && $modelB_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelB_userromFile ne "" && ! open(B_USERROMFILE, "<".$modelB_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $modelB_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $b_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80B User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $b_userromExists = 0;
+}
+if(defined($modelC_userromFile) && $modelC_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelC_userromFile ne "" && ! open(C_USERROMFILE, "<".$modelC_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $modelC_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $c_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80C User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $c_userromExists = 0;
+}
+if(defined($modelK_userromFile) && $modelK_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelK_userromFile ne "" && ! open(K_USERROMFILE, "<".$modelK_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $modelK_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $k_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80K User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $k_userromExists = 0;
+}
+if(defined($model7_userromFile) && $model7_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model7_userromFile ne "" && ! open(M7_USERROMFILE, "<".$model7_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $model7_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $m7_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ700 User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m7_userromExists = 0;
+}
+if(defined($model8_userromFile) && $model8_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model8_userromFile ne "" && ! open(M8_USERROMFILE, "<".$model8_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $model8_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $m8_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ800 User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m8_userromExists = 0;
+}
+if(defined($model12_userromFile) && $model12_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model12_userromFile ne "" && ! open(M12_USERROMFILE, "<".$model12_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $model12_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $m12_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ1200 User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m12_userromExists = 0;
+}
+if(defined($model20_userromFile) && $model20_userromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model20_userromFile ne "" && ! open(M20_USERROMFILE, "<".$model20_userromFile) )
+    {
+        argOptions(1, "Cannot open User ROM file: $model20_userromFile.\n",$ERR_BADFILENAME);
+    }
+    $m20_userromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ2000 User ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m20_userromExists = 0;
+}
+# 
+# Floppy Disk Controller Rom
+#
+if(defined($modelA_fdcromFile) && $modelA_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelA_fdcromFile ne "" && ! open(A_FDCROMFILE, "<".$modelA_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $modelA_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $a_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80A FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $a_fdcromExists = 0;
+}
+if(defined($modelB_fdcromFile) && $modelB_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelB_fdcromFile ne "" && ! open(B_FDCROMFILE, "<".$modelB_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $modelB_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $b_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80B FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $b_fdcromExists = 0;
+}
+if(defined($modelC_fdcromFile) && $modelC_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelC_fdcromFile ne "" && ! open(C_FDCROMFILE, "<".$modelC_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $modelC_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $c_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80C FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $c_fdcromExists = 0;
+}
+if(defined($modelK_fdcromFile) && $modelK_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelK_fdcromFile ne "" && ! open(K_FDCROMFILE, "<".$modelK_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $modelK_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $k_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ80K FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $k_fdcromExists = 0;
+}
+if(defined($model7_fdcromFile) && $model7_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model7_fdcromFile ne "" && ! open(M7_FDCROMFILE, "<".$model7_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $model7_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $m7_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ700 FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m7_fdcromExists = 0;
+}
+if(defined($model8_fdcromFile) && $model8_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model8_fdcromFile ne "" && ! open(M8_FDCROMFILE, "<".$model8_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $model8_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $m8_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ800 FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m8_fdcromExists = 0;
+}
+if(defined($model12_fdcromFile) && $model12_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model12_fdcromFile ne "" && ! open(M12_FDCROMFILE, "<".$model12_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $model12_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $m12_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ1200 FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m12_fdcromExists = 0;
+}
+if(defined($model20_fdcromFile) && $model20_fdcromFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model20_fdcromFile ne "" && ! open(M20_FDCROMFILE, "<".$model20_fdcromFile) )
+    {
+        argOptions(1, "Cannot open FDC ROM file: $model20_fdcromFile.\n",$ERR_BADFILENAME);
+    }
+    $m20_fdcromExists = 1;
+} else
+{
+    if($command eq "MONROM")
+    {
+        argOptions(1, "No MZ2000 FDC ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+    $m20_fdcromExists = 0;
+}
+#
+# Checks
+#
+if($command eq "64KRAM" && $a_mromExists == 0 && $b_mromExists && $c_mromExists && $k_mromExists && $m7_mromExists && $m8_mromExists && $m12_mromExists && $m20_mromExists &&
+                           $a_80c_mromExists == 0 && $b_80c_mromExists && $c_80c_mromExists && $k_80c_mromExists && $m7_80c_mromExists && $m8_80c_mromExists && $m12_80c_mromExists && $m20_80c_mromExists &&
+                           $a_userromExists == 0 && $b_userromExists && $c_userromExists && $k_userromExists && $m7_userromExists && $m8_userromExists && $m12_userromExists && $m20_userromExists &&
+                           $a_fdcromExists == 0 && $b_fdcromExists && $c_fdcromExists && $k_fdcromExists && $m7_fdcromExists && $m8_fdcromExists && $m12_fdcromExists && $m20_fdcromExists
+  )
+{
+    argOptions(1, "No Monitor ROM file given for 64K RAM mode..\n",$ERR_BADARGUMENTS);
+}
+#
+if($command eq "64KRAM" && ($a_mromExists + $b_mromExists + $c_mromExists + $k_mromExists + $m7_mromExists + $m8_mromExists + $m12_mromExists + $m20_mromExists +
+                            $a_80c_mromExists + $b_80c_mromExists + $c_80c_mromExists + $k_80c_mromExists + $m7_80c_mromExists + $m8_80c_mromExists + $m12_80c_mromExists + $m20_80c_mromExists
+                           ) > 1)
+{
+    argOptions(1, "You must only specify one Monitor ROM for 64K RAM mode..\n",$ERR_BADARGUMENTS);
+}
+if($command eq "64KRAM" && ($a_userromExists + $b_userromExists + $c_userromExists + $k_userromExists + $m7_userromExists + $m8_userromExists + $m12_userromExists + $m20_userromExists
+                           ) > 1)
+{
+    argOptions(1, "You must only specify one User ROM for 64K RAM mode..\n",$ERR_BADARGUMENTS);
+}
+if($command eq "64KRAM" && ($a_fdcromExists + $b_fdcromExists + $c_fdcromExists + $k_fdcromExists + $m7_fdcromExists + $m8_fdcromExists + $m12_fdcromExists + $m20_fdcromExists
+                           ) > 1)
+{
+    argOptions(1, "You must only specify one FDC ROM for 64K RAM mode..\n",$ERR_BADARGUMENTS);
+}
+
+if(defined($modelA_CGFile) && $modelA_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelA_CGFile ne "" && ! open(A_CGFILE, "<".$modelA_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $modelA_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ80A CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($modelB_CGFile) && $modelB_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelB_CGFile ne "" && ! open(B_CGFILE, "<".$modelB_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $modelB_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ80B CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($modelC_CGFile) && $modelC_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelC_CGFile ne "" && ! open(C_CGFILE, "<".$modelC_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $modelC_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ80C CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($modelK_CGFile) && $modelK_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelK_CGFile ne "" && ! open(K_CGFILE, "<".$modelK_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $modelK_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ80K CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model7_CGFile) && $model7_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model7_CGFile ne "" && ! open(M7_CGFILE, "<".$model7_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $model7_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ700 CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model8_CGFile) && $model8_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model8_CGFile ne "" && ! open(M8_CGFILE, "<".$model8_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $model8_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ800 CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model12_CGFile) && $model12_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model12_CGFile ne "" && ! open(M12_CGFILE, "<".$model12_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $model12_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ1200 CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model20_CGFile) && $model20_CGFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model20_CGFile ne "" && ! open(M20_CGFILE, "<".$model20_CGFile) )
+    {
+        argOptions(1, "Cannot open CG ROM file: $model20_CGFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "CGROM")
+    {
+        argOptions(1, "No MZ2000 CG ROM file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+
+if(defined($modelA_KeyFile) && $modelA_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelA_KeyFile ne "" && ! open(A_KEYFILE, "<".$modelA_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $modelA_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ80A Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($modelB_KeyFile) && $modelB_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelB_KeyFile ne "" && ! open(B_KEYFILE, "<".$modelB_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $modelB_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ80B Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($modelC_KeyFile) && $modelC_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelC_KeyFile ne "" && ! open(C_KEYFILE, "<".$modelC_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $modelC_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ80C Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($modelK_KeyFile) && $modelK_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $modelK_KeyFile ne "" && ! open(K_KEYFILE, "<".$modelK_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $modelK_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ80K Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model7_KeyFile) && $model7_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model7_KeyFile ne "" && ! open(M7_KEYFILE, "<".$model7_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $model7_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ700 Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model8_KeyFile) && $model8_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model8_KeyFile ne "" && ! open(M8_KEYFILE, "<".$model8_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $model8_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ800 Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model12_KeyFile) && $model12_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model12_KeyFile ne "" && ! open(M12_KEYFILE, "<".$model12_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $model12_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ1200 Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+if(defined($model20_KeyFile) && $model20_KeyFile ne "")
+{
+    # If defined, can we open it?
+    #
+    if( $model20_KeyFile ne "" && ! open(M20_KEYFILE, "<".$model20_KeyFile) )
+    {
+        argOptions(1, "Cannot open Key Map file: $model20_KeyFile.\n",$ERR_BADFILENAME);
+    }
+} else
+{
+    if($command eq "KEYMAP")
+    {
+        argOptions(1, "No MZ2000 Key Map file given.\n",$ERR_BADARGUMENTS);
+    }
+}
+
+##############################################################################################################
+# Commands:
+#           64KRAM = Create Image for 64K RAM initialisation. 
+#                    MROM + MZF + ZERO
+#           MONROM = Create Image for Monitor ROM initialisation.
+#                    MROM(K) + MROM(C) + MROM(1200) + MROM(A) + MROM(700) + MROM(B)
+#           CGROM  = Create Image for Character Generator ROM initialisation.
+#                    CGROM(K) + CGROM(C) + CGROM(1200) + CGROM(A) + CGROM(700) + CGROM(B)
+#           KEYMAP = Create Image for Key Map ROM initialization.
+#                    KEYMAP(K) + KEYMAP(C) + KEYMAP(1200) + KEYMAP(A) + KEYMAP(700) + KEYMAP(B)
+##############################################################################################################
+
+# Read all opened files into memory, dirty but easier to process.
+#
+if($command eq "64KRAM" || $command eq "MONROM")
+{
+    # Read in MZF file if given.
+    if($mzfExists == 1)
+    {
+        @A_MZF = ();
+        binmode(MZFFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <MZFFILE> )
+        {
+            $A_MZF[$cnt] = $byte;
+            $cnt++;
+        }
+        $A_MZF_SIZE = $cnt;
+    }
+
+    # Read in MZF file if given.
+    if($ramcheckExists == 1)
+    {
+        @RAMCHECK = ();
+        binmode(RAMCHECKFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <RAMCHECKFILE> )
+        {
+            $RAMCHECK[$cnt] = $byte;
+            $cnt++;
+        }
+        $RAMCHECK_SIZE = $cnt;
+    }
+
+    if($a_mromExists == 1)
+    {
+        @A_MROM = ();
+        binmode(A_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <A_MROMFILE> )
+        {
+            $A_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $A_MROM_SIZE = $cnt;
+    }
+
+    if($b_mromExists == 1)
+    {
+        @B_MROM = ();
+        binmode(B_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <B_MROMFILE> )
+        {
+            $B_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $B_MROM_SIZE = $cnt;
+    }
+
+    if($c_mromExists == 1)
+    {
+        @C_MROM = ();
+        binmode(C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <C_MROMFILE> )
+        {
+            $C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $C_MROM_SIZE = $cnt;
+    }
+
+    if($k_mromExists == 1)
+    {
+        @K_MROM = ();
+        binmode(K_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <K_MROMFILE> )
+        {
+            $K_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $K_MROM_SIZE = $cnt;
+    }
+
+    if($m7_mromExists == 1)
+    {
+        @M7_MROM = ();
+        binmode(M7_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M7_MROMFILE> )
+        {
+            $M7_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M7_MROM_SIZE = $cnt;
+    }
+
+    if($m8_mromExists == 1)
+    {
+        @M8_MROM = ();
+        binmode(M8_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M8_MROMFILE> )
+        {
+            $M8_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M8_MROM_SIZE = $cnt;
+    }
+
+    if($m12_mromExists == 1)
+    {
+        @M12_MROM = ();
+        binmode(M12_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M12_MROMFILE> )
+        {
+            $M12_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M12_MROM_SIZE = $cnt;
+    }
+
+    if($m20_mromExists == 1)
+    {
+        @M20_MROM = ();
+        binmode(M20_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M20_MROMFILE> )
+        {
+            $M20_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M20_MROM_SIZE = $cnt;
+    }
+
+    if($a_80c_mromExists == 1)
+    {
+        @A_80C_MROM = ();
+        binmode(A_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <A_80C_MROMFILE> )
+        {
+            $A_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $A_80C_MROM_SIZE = $cnt;
+    }
+
+    if($b_80c_mromExists == 1)
+    {
+        @B_80C_MROM = ();
+        binmode(B_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <B_80C_MROMFILE> )
+        {
+            $B_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $B_80C_MROM_SIZE = $cnt;
+    }
+
+    if($c_80c_mromExists == 1)
+    {
+        @C_80C_MROM = ();
+        binmode(C_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <C_80C_MROMFILE> )
+        {
+            $C_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $C_80C_MROM_SIZE = $cnt;
+    }
+
+    if($k_80c_mromExists == 1)
+    {
+        @K_80C_MROM = ();
+        binmode(K_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <K_80C_MROMFILE> )
+        {
+            $K_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $K_80C_MROM_SIZE = $cnt;
+    }
+
+    if($m7_80c_mromExists == 1)
+    {
+        @M7_80C_MROM = ();
+        binmode(M7_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M7_80C_MROMFILE> )
+        {
+            $M7_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M7_80C_MROM_SIZE = $cnt;
+    }
+
+    if($m8_80c_mromExists == 1)
+    {
+        @M8_80C_MROM = ();
+        binmode(M8_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M8_80C_MROMFILE> )
+        {
+            $M8_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M8_80C_MROM_SIZE = $cnt;
+    }
+
+    if($m12_80c_mromExists == 1)
+    {
+        @M12_80C_MROM = ();
+        binmode(M12_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M12_80C_MROMFILE> )
+        {
+            $M12_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M12_80C_MROM_SIZE = $cnt;
+    }
+
+    if($m20_80c_mromExists == 1)
+    {
+        @M20_80C_MROM = ();
+        binmode(M20_80C_MROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M20_80C_MROMFILE> )
+        {
+            $M20_80C_MROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M20_80C_MROM_SIZE = $cnt;
+    }
+
+    if($a_userromExists == 1)
+    {
+        @A_USERROM = ();
+        binmode(A_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <A_USERROMFILE> )
+        {
+            $A_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $A_USERROM_SIZE = $cnt;
+    }
+
+    if($b_userromExists == 1)
+    {
+        @B_USERROM = ();
+        binmode(B_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <B_USERROMFILE> )
+        {
+            $B_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $B_USERROM_SIZE = $cnt;
+    }
+
+    if($c_userromExists == 1)
+    {
+        @C_USERROM = ();
+        binmode(C_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <C_USERROMFILE> )
+        {
+            $C_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $C_USERROM_SIZE = $cnt;
+    }
+
+    if($k_userromExists == 1)
+    {
+        @K_USERROM = ();
+        binmode(K_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <K_USERROMFILE> )
+        {
+            $K_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $K_USERROM_SIZE = $cnt;
+    }
+
+    if($m7_userromExists == 1)
+    {
+        @M7_USERROM = ();
+        binmode(M7_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M7_USERROMFILE> )
+        {
+            $M7_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M7_USERROM_SIZE = $cnt;
+    }
+
+    if($m8_userromExists == 1)
+    {
+        @M8_USERROM = ();
+        binmode(M8_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M8_USERROMFILE> )
+        {
+            $M8_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M8_USERROM_SIZE = $cnt;
+    }
+
+    if($m12_userromExists == 1)
+    {
+        @M12_USERROM = ();
+        binmode(M12_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M12_USERROMFILE> )
+        {
+            $M12_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M12_USERROM_SIZE = $cnt;
+    }
+
+    if($m20_userromExists == 1)
+    {
+        @M20_USERROM = ();
+        binmode(M20_USERROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M20_USERROMFILE> )
+        {
+            $M20_USERROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M20_USERROM_SIZE = $cnt;
+    }
+
+    if($a_fdcromExists == 1)
+    {
+        @A_FDCROM = ();
+        binmode(A_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <A_FDCROMFILE> )
+        {
+            $A_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $A_FDCROM_SIZE = $cnt;
+    }
+
+    if($b_fdcromExists == 1)
+    {
+        @B_FDCROM = ();
+        binmode(B_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <B_FDCROMFILE> )
+        {
+            $B_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $B_FDCROM_SIZE = $cnt;
+    }
+
+    if($c_fdcromExists == 1)
+    {
+        @C_FDCROM = ();
+        binmode(C_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <C_FDCROMFILE> )
+        {
+            $C_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $C_FDCROM_SIZE = $cnt;
+    }
+
+    if($k_fdcromExists == 1)
+    {
+        @K_FDCROM = ();
+        binmode(K_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <K_FDCROMFILE> )
+        {
+            $K_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $K_FDCROM_SIZE = $cnt;
+    }
+
+    if($m7_fdcromExists == 1)
+    {
+        @M7_FDCROM = ();
+        binmode(M7_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M7_FDCROMFILE> )
+        {
+            $M7_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M7_FDCROM_SIZE = $cnt;
+    }
+
+    if($m8_fdcromExists == 1)
+    {
+        @M8_FDCROM = ();
+        binmode(M8_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M8_FDCROMFILE> )
+        {
+            $M8_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M8_FDCROM_SIZE = $cnt;
+    }
+
+    if($m12_fdcromExists == 1)
+    {
+        @M12_FDCROM = ();
+        binmode(M12_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M12_FDCROMFILE> )
+        {
+            $M12_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M12_FDCROM_SIZE = $cnt;
+    }
+
+    if($m20_fdcromExists == 1)
+    {
+        @M20_FDCROM = ();
+        binmode(M20_FDCROMFILE); 
+        local $/ = \1;
+        $cnt = 0;
+        $skip = 0;
+        while ( my $byte = <M20_FDCROMFILE> )
+        {
+            $M20_FDCROM[$cnt] = $byte;
+            $cnt++;
+        }
+        $M20_FDCROM_SIZE = $cnt;
+    }
+}
+
+if($command eq "CGROM")
+{
+    @A_CGROM = ();
+    binmode(A_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <A_CGFILE> )
+    {
+        $A_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $A_CGROM_SIZE = $cnt;
+
+    @B_CGROM = ();
+    binmode(B_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <B_CGFILE> )
+    {
+        $B_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $B_CGROM_SIZE = $cnt;
+
+    @C_CGROM = ();
+    binmode(C_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <C_CGFILE> )
+    {
+        $C_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $C_CGROM_SIZE = $cnt;
+
+    @K_CGROM = ();
+    binmode(K_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <K_CGFILE> )
+    {
+        $K_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $K_CGROM_SIZE = $cnt;
+
+    @M7_CGROM = ();
+    binmode(M7_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M7_CGFILE> )
+    {
+        $M7_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $M7_CGROM_SIZE = $cnt;
+
+    @M8_CGROM = ();
+    binmode(M8_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M8_CGFILE> )
+    {
+        $M8_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $M8_CGROM_SIZE = $cnt;
+
+    @M12_CGROM = ();
+    binmode(M12_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M12_CGFILE> )
+    {
+        $M12_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $M12_CGROM_SIZE = $cnt;
+
+    @M20_CGROM = ();
+    binmode(M20_CGFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M20_CGFILE> )
+    {
+        $M20_CGROM[$cnt] = $byte;
+        $cnt++;
+    }
+    $M20_CGROM_SIZE = $cnt;
+}
+
+if($command eq "KEYMAP")
+{
+    @A_KEYMAP = ();
+    binmode(A_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <A_KEYFILE> )
+    {
+        $A_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $A_KEYMAP_SIZE = $cnt;
+
+    @B_KEYMAP = ();
+    binmode(B_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <B_KEYFILE> )
+    {
+        $B_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $B_KEYMAP_SIZE = $cnt;
+
+    @C_KEYMAP = ();
+    binmode(C_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <C_KEYFILE> )
+    {
+        $C_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $C_KEYMAP_SIZE = $cnt;
+
+    @K_KEYMAP = ();
+    binmode(K_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <K_KEYFILE> )
+    {
+        $K_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $K_KEYMAP_SIZE = $cnt;
+
+    @M7_KEYMAP = ();
+    binmode(M7_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M7_KEYFILE> )
+    {
+        $M7_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $M7_KEYMAP_SIZE = $cnt;
+
+    @M8_KEYMAP = ();
+    binmode(M8_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M8_KEYFILE> )
+    {
+        $M8_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $M8_KEYMAP_SIZE = $cnt;
+
+    @M12_KEYMAP = ();
+    binmode(M12_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M12_KEYFILE> )
+    {
+        $M12_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $M12_KEYMAP_SIZE = $cnt;
+
+    @M20_KEYMAP = ();
+    binmode(M20_KEYFILE); 
+    local $/ = \1;
+    $cnt = 0;
+    $skip = 0;
+    while ( my $byte = <M20_KEYFILE> )
+    {
+        $M20_KEYMAP[$cnt] = $byte;
+        $cnt++;
+    }
+    $M20_KEYMAP_SIZE = $cnt;
+}
+
+if($command eq "64KRAM")
+{
+    # Location    Loc. in    Location in    Length    Meaning
+    # in tape    monitor's    S-BASIC        
+    # header     work area    1Z-013B        
+    # $00 (0)     $10F0       $0FFC           1      attribute of the file:
+    #                                                 01 machine code program file
+    #                                                 02 MZ-80 BASIC program file
+    #                                                 03 MZ-80 data file
+    #                                                 04 MZ-700 data file
+    #                                                 05 MZ-700 BASIC program file
+    # $01 (1)     $10F1       $0FFD           17     file name ( end = $0D )
+    # $12 (18)    $1102       $100E           2      byte size of the file
+    # $14 (20)    $1104       $1010           2      load address of a program file
+    # $16 (22)    $1106       $1012           2      execution address of a program file
+    # $18 (24)    $1108       $1014           104    comment
+
+    # Initialize in memory image.
+    @MainMemory = ();
+
+    
+    # First up, write out the Monitor ROM to output file.
+    #
+    if($a_mromExists == 1)       { $mrom_size = scalar @A_MROM;          foreach my $byte (@A_MROM)       { push @MainMemory, $byte; } };
+    if($a_80c_mromExists == 1)   { $mrom_size = scalar @A_80C_MROM;      foreach my $byte (@A_80C_MROM)   { push @MainMemory, $byte; } };
+    if($b_mromExists == 1)       { $mrom_size = scalar @B_MROM;          foreach my $byte (@B_MROM)       { push @MainMemory, $byte; } };
+    if($b_80c_mromExists == 1)   { $mrom_size = scalar @B_80C_MROM;      foreach my $byte (@B_80C_MROM)   { push @MainMemory, $byte; } };
+    if($c_mromExists == 1)       { $mrom_size = scalar @C_MROM;          foreach my $byte (@C_MROM)       { push @MainMemory, $byte; } };
+    if($c_80c_mromExists == 1)   { $mrom_size = scalar @C_80C_MROM;      foreach my $byte (@C_80C_MROM)   { push @MainMemory, $byte; } };
+    if($k_mromExists == 1)       { $mrom_size = scalar @K_MROM;          foreach my $byte (@K_MROM)       { push @MainMemory, $byte; } };
+    if($k_80c_mromExists == 1)   { $mrom_size = scalar @K_80C_MROM;      foreach my $byte (@K_80C_MROM)   { push @MainMemory, $byte; } };
+    if($m7_mromExists == 1)      { $mrom_size = scalar @M7_MROM;         foreach my $byte (@M7_MROM)      { push @MainMemory, $byte; } };
+    if($m7_80c_mromExists == 1)  { $mrom_size = scalar @M7_80C_MROM;     foreach my $byte (@M7_80C_MROM)  { push @MainMemory, $byte; } };
+    if($m8_mromExists == 1)      { $mrom_size = scalar @M8_MROM;         foreach my $byte (@M8_MROM)      { push @MainMemory, $byte; } };
+    if($m8_80c_mromExists == 1)  { $mrom_size = scalar @M8_80C_MROM;     foreach my $byte (@M8_80C_MROM)  { push @MainMemory, $byte; } };
+    if($m12_mromExists == 1)     { $mrom_size = scalar @M12_MROM;        foreach my $byte (@M12_MROM)     { push @MainMemory, $byte; } };
+    if($m12_80c_mromExists == 1) { $mrom_size = scalar @M12_80C_MROM;    foreach my $byte (@M12_80C_MROM) { push @MainMemory, $byte; } };
+    if($m20_mromExists == 1)     { $mrom_size = scalar @M20_MROM;        foreach my $byte (@M20_MROM)     { push @MainMemory, $byte; } };
+    if($m20_80c_mromExists == 1) { $mrom_size = scalar @M20_80C_MROM;    foreach my $byte (@M20_80C_MROM) { push @MainMemory, $byte; } };
+
+
+    # If a Tape Program has been provided, process it.
+    #
+    if($mzfExists == 1)
+    {
+        # Process the header to get key information.
+        #
+        $mzf_header = pack('a'x128, @A_MZF);
+        ($mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr, $mzf_comment) = unpack 'c1 a17 v4 v4 v4 a104', $mzf_header;
+        $mzf_filename =~ s/\r|\n//g;
+
+        # Next, 1000 - 10EF as zero's (Monitor scratch area).
+        for(my $idx=0; $idx < 240; $idx++) { push @MainMemory, "\x00"; };
+    
+        # Next, write out the Tape Header 10F0 - 116F.
+        for(my $idx=0; $idx < 128; $idx++) { push @MainMemory, $A_MZF[$idx]; };
+    
+        # Next, write out zero's up until the load address.
+        for(my $idx=0x1170; $idx < $mzf_loadaddr; $idx++) { push @MainMemory, "\x00";  };
+        for(my $idx=128; $idx < $A_MZF_SIZE; $idx++) { push @MainMemory, $A_MZF[$idx]; };
+
+        # Next, 1000 - 10EF as zero's (Monitor scratch area).
+        # Positions for easy reference.
+        $romStartPosition        = 0;
+        $romEndPosition          = $mrom_size;
+        $romScratchStartPosition = $mrom_size;
+        $romScratchEndPosition   = 0x10EF;
+        $tapeHeaderStartPosition = 0x10F0;
+        $tapeHeaderEndPosition   = 0x116F;
+        $romStackStartPosition   = 0x1170;
+        $romStackEndPosition     = $mzf_loadaddr;
+        $programStartPosition    = $mzf_loadaddr;
+        $programEndPosition      = $mzf_loadaddr + $mzf_size;
+        $lowerUsedMemoryPosition = scalar @MainMemory;
+        $ramcheckMemoryPosition  = 0xCE00;
+        $userrom_size            = 0x0000;
+        $fdcrom_size             = 0x0000;
+        $userRomMemoryPosition   = 0xE800;
+        $fdcRomMemoryPosition    = 0xF000;
+        $upperMemoryPosition     = 65536;
+
+        # Next, write out zero's from scratch area to end of ramchecker or userrom.
+        if($ramcheckExists == 1)
+        {
+            for(my $idx=$lowerUsedMemoryPosition; $idx < $ramcheckMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+            for(my $idx=0; $idx < $RAMCHECK_SIZE; $idx++) { push @MainMemory, $RAMCHECK[$idx]; };
+            for(my $idx=$ramcheckMemoryPosition + $RAMCHECK_SIZE; $idx < $userRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+        } else
+        {
+            for(my $idx=$lowerUsedMemoryPosition; $idx < $userRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+        }
+        
+        # User Rom
+        if($a_userromExists == 1)    { $userrom_size = scalar @A_USERROM;    foreach my $byte (@A_USERROM)    { push @MainMemory, $byte; } };
+        if($b_userromExists == 1)    { $userrom_size = scalar @B_USERROM;    foreach my $byte (@B_USERROM)    { push @MainMemory, $byte; } };
+        if($c_userromExists == 1)    { $userrom_size = scalar @C_USERROM;    foreach my $byte (@C_USERROM)    { push @MainMemory, $byte; } };
+        if($k_userromExists == 1)    { $userrom_size = scalar @K_USERROM;    foreach my $byte (@K_USERROM)    { push @MainMemory, $byte; } };
+        if($m7_userromExists == 1)   { $userrom_size = scalar @M7_USERROM;   foreach my $byte (@M7_USERROM)   { push @MainMemory, $byte; } };
+        if($m8_userromExists == 1)   { $userrom_size = scalar @M8_USERROM;   foreach my $byte (@M8_USERROM)   { push @MainMemory, $byte; } };
+        if($m12_userromExists == 1)  { $userrom_size = scalar @M12_USERROM;  foreach my $byte (@M12_USERROM)  { push @MainMemory, $byte; } };
+        if($m20_userromExists == 1)  { $userrom_size = scalar @M20_USERROM;  foreach my $byte (@M20_USERROM)  { push @MainMemory, $byte; } };
+        
+        # Pad with zeros to end of block.
+        for(my $idx=$userRomMemoryPosition + $userrom_size; $idx < $userRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+
+        # FDC Rom
+        if($a_fdcromExists == 1)     { $fdcrom_size = scalar @A_FDCROM;      foreach my $byte (@A_FDCROM)     { push @MainMemory, $byte; } };
+        if($b_fdcromExists == 1)     { $fdcrom_size = scalar @B_FDCROM;      foreach my $byte (@B_FDCROM)     { push @MainMemory, $byte; } };
+        if($c_fdcromExists == 1)     { $fdcrom_size = scalar @C_FDCROM;      foreach my $byte (@C_FDCROM)     { push @MainMemory, $byte; } };
+        if($k_fdcromExists == 1)     { $fdcrom_size = scalar @K_FDCROM;      foreach my $byte (@K_FDCROM)     { push @MainMemory, $byte; } };
+        if($m7_fdcromExists == 1)    { $fdcrom_size = scalar @M7_FDCROM;     foreach my $byte (@M7_FDCROM)    { push @MainMemory, $byte; } };
+        if($m8_fdcromExists == 1)    { $fdcrom_size = scalar @M8_FDCROM;     foreach my $byte (@M8_FDCROM)    { push @MainMemory, $byte; } };
+        if($m12_fdcromExists == 1)   { $fdcrom_size = scalar @M12_FDCROM;    foreach my $byte (@M12_FDCROM)   { push @MainMemory, $byte; } };
+        if($m20_fdcromExists == 1)   { $fdcrom_size = scalar @M20_FDCROM;    foreach my $byte (@M20_FDCROM)   { push @MainMemory, $byte; } };
+
+        # Pad with zeros to end of block.
+        for(my $idx=$fdcRomMemoryPosition + $fdcrom_size; $idx < $fdcRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+    } else
+    {
+
+        # Positions for easy reference.
+        $romStartPosition        = 0;
+        $romEndPosition          = $mrom_size;
+        $romScratchStartPosition = $mrom_size;
+        $romScratchEndPosition   = 0x116F;
+        $tapeHeaderStartPosition = 0x0000;
+        $tapeHeaderEndPosition   = 0x0000;
+        $romStackStartPosition   = 0x1170;
+        $romStackEndPosition     = 0x11FF;
+        $programStartPosition    = 0x0000;
+        $programEndPosition      = 0x0000;
+        $lowerUsedMemoryPosition = scalar @MainMemory;
+        $ramcheckMemoryPosition  = 0xCE00;
+        $userrom_size            = 0x0000;
+        $fdcrom_size             = 0x0000;
+        $userRomMemoryPosition   = 0xE800;
+        $fdcRomMemoryPosition    = 0xF000;
+        $upperMemoryPosition     = 65536;
+
+        # Next, write out zero's from scratch area to end of memory or ramchecker..
+        if($ramcheckExists == 1)
+        {
+            for(my $idx=$lowerUsedMemoryPosition; $idx < $ramcheckMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+            for(my $idx=0; $idx < $RAMCHECK_SIZE; $idx++) { push @MainMemory, $RAMCHECK[$idx]; };
+            for(my $idx=$ramcheckMemoryPosition + $RAMCHECK_SIZE; $idx < $userRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+        } else
+        {
+            for(my $idx=$lowerUsedMemoryPosition; $idx < $userRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+        }
+
+        # User Rom
+        if($a_userromExists == 1)    { $userrom_size = scalar @A_USERROM;    foreach my $byte (@A_USERROM)    { push @MainMemory, $byte; } };
+        if($b_userromExists == 1)    { $userrom_size = scalar @B_USERROM;    foreach my $byte (@B_USERROM)    { push @MainMemory, $byte; } };
+        if($c_userromExists == 1)    { $userrom_size = scalar @C_USERROM;    foreach my $byte (@C_USERROM)    { push @MainMemory, $byte; } };
+        if($k_userromExists == 1)    { $userrom_size = scalar @K_USERROM;    foreach my $byte (@K_USERROM)    { push @MainMemory, $byte; } };
+        if($m7_userromExists == 1)   { $userrom_size = scalar @M7_USERROM;   foreach my $byte (@M7_USERROM)   { push @MainMemory, $byte; } };
+        if($m8_userromExists == 1)   { $userrom_size = scalar @M8_USERROM;   foreach my $byte (@M8_USERROM)   { push @MainMemory, $byte; } };
+        if($m12_userromExists == 1)  { $userrom_size = scalar @M12_USERROM;  foreach my $byte (@M12_USERROM)  { push @MainMemory, $byte; } };
+        if($m20_userromExists == 1)  { $userrom_size = scalar @M20_USERROM;  foreach my $byte (@M20_USERROM)  { push @MainMemory, $byte; } };
+        
+        # Pad with zeros to end of block.
+        for(my $idx=$userRomMemoryPosition + $userrom_size; $idx < $userRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+
+        # FDC Rom
+        if($a_fdcromExists == 1)     { $fdcrom_size = scalar @A_FDCROM;      foreach my $byte (@A_FDCROM)     { push @MainMemory, $byte; } };
+        if($b_fdcromExists == 1)     { $fdcrom_size = scalar @B_FDCROM;      foreach my $byte (@B_FDCROM)     { push @MainMemory, $byte; } };
+        if($c_fdcromExists == 1)     { $fdcrom_size = scalar @C_FDCROM;      foreach my $byte (@C_FDCROM)     { push @MainMemory, $byte; } };
+        if($k_fdcromExists == 1)     { $fdcrom_size = scalar @K_FDCROM;      foreach my $byte (@K_FDCROM)     { push @MainMemory, $byte; } };
+        if($m7_fdcromExists == 1)    { $fdcrom_size = scalar @M7_FDCROM;     foreach my $byte (@M7_FDCROM)    { push @MainMemory, $byte; } };
+        if($m8_fdcromExists == 1)    { $fdcrom_size = scalar @M8_FDCROM;     foreach my $byte (@M8_FDCROM)    { push @MainMemory, $byte; } };
+        if($m12_fdcromExists == 1)   { $fdcrom_size = scalar @M12_FDCROM;    foreach my $byte (@M12_FDCROM)   { push @MainMemory, $byte; } };
+        if($m20_fdcromExists == 1)   { $fdcrom_size = scalar @M20_FDCROM;    foreach my $byte (@M20_FDCROM)   { push @MainMemory, $byte; } };
+
+        # Pad with zeros to end of block.
+        for(my $idx=$fdcRomMemoryPosition + $fdcrom_size; $idx < $fdcRomMemoryPosition; $idx++) { push @MainMemory, "\x00"; };
+    }
+
+    # Finally, print out details for confirmation.
+    #
+    logWrite("", sprintf "Main Memory Map:\n");
+    logWrite("", sprintf "                     MROM           = %04x:%04x %04x bytes", $romStartPosition,        $romEndPosition,        $romEndPosition - $romStartPosition);
+    logWrite("", sprintf "                     MROM (Scratch) = %04x:%04x %04x bytes", $romScratchStartPosition, $romScratchEndPosition, $romScratchEndPosition - $romScratchStartPosition);
+    logWrite("", sprintf "              Tape Header           = %04x:%04x %04x bytes", $tapeHeaderStartPosition, $tapeHeaderEndPosition, $tapeHeaderEndPosition - $tapeHeaderStartPosition,);
+    logWrite("", sprintf "                     MROM (Stack)   = %04x:%04x %04x bytes", $romStackStartPosition,   $romStackEndPosition,   $romStackEndPosition - $romStackStartPosition);
+    logWrite("", sprintf "                  Program           = %04x:%04x %04x bytes", $programStartPosition,    $programEndPosition,    $programEndPosition - $programStartPosition);
+    if($ramcheckExists == 1)
+    {
+        logWrite("", sprintf "              Ram Checker           = %04x:%04x %04x bytes", $ramcheckMemoryPosition,    $ramcheckMemoryPosition + $RAMCHECK_SIZE,    $RAMCHECK_SIZE);
+    }
+    if($a_userromExists == 1 || $b_userromExists == 1 || $c_userromExists == 1 || $k_userromExists == 1 || $m7_userromExists == 1 || $m8_userromExists == 1 || $m12_userromExists == 1 || $m20_userromExists == 1)
+    {
+        logWrite("", sprintf "              User Rom              = %04x:%04x %04x bytes", $userRomMemoryPosition,    $userRomMemoryPosition + $userrom_size,    $userrom_size);
+    }
+    if($a_fdcromExists == 1 || $b_fdcromExists == 1 || $c_fdcromExists == 1 || $k_fdcromExists == 1 || $m7_fdcromExists == 1 || $m8_fdcromExists == 1 || $m12_fdcromExists == 1 || $m20_fdcromExists == 1)
+    {
+        logWrite("", sprintf "              FDC Rom               = %04x:%04x %04x bytes", $fdcRomMemoryPosition,    $fdcRomMemoryPosition + $fdcrom_size,    $fdcrom_size);
+    }
+    logWrite("", sprintf "End of Program Memory               = %04x", $programEndPosition);
+}
+elsif($command eq "MONROM")
+{
+    # Initialize in memory image.
+    @MonitorMemory = ();
+
+    # Max ROM Sizes.
+    $A_MROM_MAX_SIZE        = 4096;
+    $A_80C_MROM_MAX_SIZE    = 4096;
+    $A_USERROM_MAX_SIZE     = 2048;
+    $A_FDCROM_MAX_SIZE      = 4096;
+    $K_MROM_MAX_SIZE        = 4096;
+    $K_80C_MROM_MAX_SIZE    = 4096;
+    $K_USERROM_MAX_SIZE     = 2048;
+    $K_FDCROM_MAX_SIZE      = 4096;
+    $C_MROM_MAX_SIZE        = 4096;
+    $C_80C_MROM_MAX_SIZE    = 4096;
+    $C_USERROM_MAX_SIZE     = 2048;
+    $C_FDCROM_MAX_SIZE      = 4096;
+    $M12_MROM_MAX_SIZE      = 4096;
+    $M12_80C_MROM_MAX_SIZE  = 4096;
+    $M12_USERROM_MAX_SIZE   = 2048;
+    $M12_FDCROM_MAX_SIZE    = 4096;
+    $M20_MROM_MAX_SIZE      = 2048;
+    $M20_80C_MROM_MAX_SIZE  = 2048;
+    $M20_USERROM_MAX_SIZE   = 2048;
+    $M20_FDCROM_MAX_SIZE    = 4096;
+    $M7_MROM_MAX_SIZE       = 4096;
+    $M7_80C_MROM_MAX_SIZE   = 4096;
+    $M7_USERROM_MAX_SIZE    = 2048;
+    $M7_FDCROM_MAX_SIZE     = 4096;
+    $M8_MROM_MAX_SIZE       = 4096;
+    $M8_80C_MROM_MAX_SIZE   = 4096;
+    $M8_USERROM_MAX_SIZE    = 2048;
+    $M8_FDCROM_MAX_SIZE     = 4096;
+    $B_MROM_MAX_SIZE        = 2048;
+    $B_80C_MROM_MAX_SIZE    = 2048;
+    $B_USERROM_MAX_SIZE     = 2048;
+    $B_FDCROM_MAX_SIZE      = 4096;
+    $M20_MROM_MAX_SIZE      = 2048;
+    $M20_80C_MROM_MAX_SIZE  = 2048;
+    $M20_USERROM_MAX_SIZE   = 2048;
+    $M20_FDCROM_MAX_SIZE    = 4096;
+
+    # Fill the memory image with equisize images, zero padding as necessary.
+    foreach my $byte (@K_MROM)       { push @MonitorMemory, $byte; };  for(my $idx=$K_MROM_SIZE;       $idx < $K_MROM_MAX_SIZE; $idx++)       { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@K_80C_MROM)   { push @MonitorMemory, $byte; };  for(my $idx=$K_80C_MROM_SIZE;   $idx < $K_80C_MROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@K_USERROM)    { push @MonitorMemory, $byte; };  for(my $idx=$K_USERROM_SIZE;    $idx < $K_USERROM_MAX_SIZE; $idx++)    { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@K_FDCROM)     { push @MonitorMemory, $byte; };  for(my $idx=$K_FDCROM_SIZE;     $idx < $K_FDCROM_MAX_SIZE; $idx++)     { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@C_MROM)       { push @MonitorMemory, $byte; };  for(my $idx=$C_MROM_SIZE;       $idx < $C_MROM_MAX_SIZE; $idx++)       { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@C_80C_MROM)   { push @MonitorMemory, $byte; };  for(my $idx=$C_80C_MROM_SIZE;   $idx < $C_80C_MROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@C_USERROM)    { push @MonitorMemory, $byte; };  for(my $idx=$C_USERROM_SIZE;    $idx < $C_USERROM_MAX_SIZE; $idx++)    { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@C_FDCROM)     { push @MonitorMemory, $byte; };  for(my $idx=$C_FDCROM_SIZE;     $idx < $C_FDCROM_MAX_SIZE; $idx++)     { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M12_MROM)     { push @MonitorMemory, $byte; };  for(my $idx=$M12_MROM_SIZE;     $idx < $M12_MROM_MAX_SIZE; $idx++)     { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M12_80C_MROM) { push @MonitorMemory, $byte; };  for(my $idx=$M12_80C_MROM_SIZE; $idx < $M12_80C_MROM_MAX_SIZE; $idx++) { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M12_USERROM)  { push @MonitorMemory, $byte; };  for(my $idx=$M12_USERROM_SIZE;  $idx < $M12_USERROM_MAX_SIZE; $idx++)  { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M12_FDCROM)   { push @MonitorMemory, $byte; };  for(my $idx=$M12_FDCROM_SIZE;   $idx < $M12_FDCROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@A_MROM)       { push @MonitorMemory, $byte; };  for(my $idx=$A_MROM_SIZE;       $idx < $A_MROM_MAX_SIZE; $idx++)       { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@A_80C_MROM)   { push @MonitorMemory, $byte; };  for(my $idx=$A_80C_MROM_SIZE;   $idx < $A_80C_MROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@A_USERROM)    { push @MonitorMemory, $byte; };  for(my $idx=$A_USERROM_SIZE;    $idx < $A_USERROM_MAX_SIZE; $idx++)    { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@A_FDCROM)     { push @MonitorMemory, $byte; };  for(my $idx=$A_FDCROM_SIZE;     $idx < $A_FDCROM_MAX_SIZE; $idx++)     { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M7_MROM)      { push @MonitorMemory, $byte; };  for(my $idx=$M7_MROM_SIZE;      $idx < $M7_MROM_MAX_SIZE; $idx++)      { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M7_80C_MROM)  { push @MonitorMemory, $byte; };  for(my $idx=$M7_80C_MROM_SIZE;  $idx < $M7_80C_MROM_MAX_SIZE; $idx++)  { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M7_USERROM)   { push @MonitorMemory, $byte; };  for(my $idx=$M7_USERROM_SIZE;   $idx < $M7_USERROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M7_FDCROM)    { push @MonitorMemory, $byte; };  for(my $idx=$M7_FDCROM_SIZE;    $idx < $M7_FDCROM_MAX_SIZE; $idx++)    { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M8_MROM)      { push @MonitorMemory, $byte; };  for(my $idx=$M8_MROM_SIZE;      $idx < $M8_MROM_MAX_SIZE; $idx++)      { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M8_80C_MROM)  { push @MonitorMemory, $byte; };  for(my $idx=$M8_80C_MROM_SIZE;  $idx < $M8_80C_MROM_MAX_SIZE; $idx++)  { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M8_USERROM)   { push @MonitorMemory, $byte; };  for(my $idx=$M8_USERROM_SIZE;   $idx < $M8_USERROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M8_FDCROM)    { push @MonitorMemory, $byte; };  for(my $idx=$M8_FDCROM_SIZE;    $idx < $M8_FDCROM_MAX_SIZE; $idx++)    { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@B_MROM)       { push @MonitorMemory, $byte; };  for(my $idx=$B_MROM_SIZE;       $idx < $B_MROM_MAX_SIZE; $idx++)       { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@B_80C_MROM)   { push @MonitorMemory, $byte; };  for(my $idx=$B_80C_MROM_SIZE;   $idx < $B_80C_MROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@B_USERROM)    { push @MonitorMemory, $byte; };  for(my $idx=$B_USERROM_SIZE;    $idx < $B_USERROM_MAX_SIZE; $idx++)    { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@B_FDCROM)     { push @MonitorMemory, $byte; };  for(my $idx=$B_FDCROM_SIZE;     $idx < $B_FDCROM_MAX_SIZE; $idx++)     { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M20_MROM)     { push @MonitorMemory, $byte; };  for(my $idx=$M20_MROM_SIZE;     $idx < $M20_MROM_MAX_SIZE; $idx++)     { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M20_80C_MROM) { push @MonitorMemory, $byte; };  for(my $idx=$M20_80C_MROM_SIZE; $idx < $M20_80C_MROM_MAX_SIZE; $idx++) { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M20_USERROM)  { push @MonitorMemory, $byte; };  for(my $idx=$M20_USERROM_SIZE;  $idx < $M20_USERROM_MAX_SIZE; $idx++)  { push @MonitorMemory, "\x00"; };
+    foreach my $byte (@M20_FDCROM)   { push @MonitorMemory, $byte; };  for(my $idx=$M20_FDCROM_SIZE;   $idx < $M20_FDCROM_MAX_SIZE; $idx++)   { push @MonitorMemory, "\x00"; };
+
+    # Positions for easy reference.
+    $k_romStartPosition        = 0;
+    $k_romEndPosition          = $K_MROM_MAX_SIZE -1;
+    $k_romPadding              = $K_MROM_MAX_SIZE - $K_MROM_SIZE;
+    $k_80c_romStartPosition    = $k_romEndPosition + 1;
+    $k_80c_romEndPosition      = $k_80c_romStartPosition + $K_80C_MROM_MAX_SIZE -1;
+    $k_80c_romPadding          = $K_80C_MROM_MAX_SIZE - $K_80C_MROM_SIZE;
+    $k_userromStartPosition    = $k_80c_romEndPosition + 1;
+    $k_userromEndPosition      = $k_userromStartPosition + $K_USERROM_MAX_SIZE -1;
+    $k_userromPadding          = $K_USERROM_MAX_SIZE - $K_USERROM_SIZE;
+    $k_fdcromStartPosition     = $k_userromEndPosition + 1;
+    $k_fdcromEndPosition       = $k_fdcromStartPosition + $K_FDCROM_MAX_SIZE -1;
+    $k_fdcromPadding           = $K_FDCROM_MAX_SIZE - $K_FDCROM_SIZE;
+    $c_romStartPosition        = $k_fdcromEndPosition + 1;
+    $c_romEndPosition          = $c_romStartPosition + $C_MROM_MAX_SIZE -1;
+    $c_romPadding              = $C_MROM_MAX_SIZE - $C_MROM_SIZE;
+    $c_80c_romStartPosition    = $c_romEndPosition + 1;
+    $c_80c_romEndPosition      = $c_80c_romStartPosition + $C_80C_MROM_MAX_SIZE -1;
+    $c_80c_romPadding          = $C_80C_MROM_MAX_SIZE - $C_80C_MROM_SIZE;
+    $c_userromStartPosition    = $c_80c_romEndPosition + 1;
+    $c_userromEndPosition      = $c_userromStartPosition + $C_USERROM_MAX_SIZE -1;
+    $c_userromPadding          = $C_USERROM_MAX_SIZE - $C_USERROM_SIZE;
+    $c_fdcromStartPosition     = $c_userromEndPosition + 1;
+    $c_fdcromEndPosition       = $c_fdcromStartPosition + $C_FDCROM_MAX_SIZE -1;
+    $c_fdcromPadding           = $C_FDCROM_MAX_SIZE - $C_FDCROM_SIZE;
+    $m12_romStartPosition      = $c_fdcromEndPosition + 1;
+    $m12_romEndPosition        = $m12_romStartPosition + $M12_MROM_MAX_SIZE -1;
+    $m12_romPadding            = $M12_MROM_MAX_SIZE - $M12_MROM_SIZE;
+    $m12_80c_romStartPosition  = $m12_romEndPosition + 1;
+    $m12_80c_romEndPosition    = $m12_80c_romStartPosition + $M12_80C_MROM_MAX_SIZE -1;
+    $m12_80c_romPadding        = $M12_80C_MROM_MAX_SIZE - $M12_80C_MROM_SIZE;
+    $m12_userromStartPosition  = $m12_80c_romEndPosition + 1;
+    $m12_userromEndPosition    = $m12_userromStartPosition + $M12_USERROM_MAX_SIZE -1;
+    $m12_userromPadding        = $M12_USERROM_MAX_SIZE - $M12_USERROM_SIZE;
+    $m12_fdcromStartPosition   = $m12_userromEndPosition + 1;
+    $m12_fdcromEndPosition     = $m12_fdcromStartPosition + $M12_FDCROM_MAX_SIZE -1;
+    $m12_fdcromPadding         = $M12_FDCROM_MAX_SIZE - $M12_FDCROM_SIZE;
+    $a_romStartPosition        = $m12_fdcromEndPosition + 1;
+    $a_romEndPosition          = $a_romStartPosition + $A_MROM_MAX_SIZE -1;
+    $a_romPadding              = $A_MROM_MAX_SIZE - $A_MROM_SIZE;
+    $a_80c_romStartPosition    = $a_romEndPosition + 1;
+    $a_80c_romEndPosition      = $a_80c_romStartPosition + $A_80C_MROM_MAX_SIZE -1;
+    $a_80c_romPadding          = $A_80C_MROM_MAX_SIZE - $A_80C_MROM_SIZE;
+    $a_userromStartPosition    = $a_80c_romEndPosition + 1;
+    $a_userromEndPosition      = $a_userromStartPosition + $A_USERROM_MAX_SIZE -1;
+    $a_userromPadding          = $A_USERROM_MAX_SIZE - $A_USERROM_SIZE;
+    $a_fdcromStartPosition     = $a_userromEndPosition + 1;
+    $a_fdcromEndPosition       = $a_fdcromStartPosition + $A_FDCROM_MAX_SIZE -1;
+    $a_fdcromPadding           = $A_FDCROM_MAX_SIZE - $A_FDCROM_SIZE;
+    $m7_romStartPosition       = $a_fdcromEndPosition + 1;
+    $m7_romEndPosition         = $m7_romStartPosition + $M7_MROM_MAX_SIZE -1;
+    $m7_romPadding             = $M7_MROM_MAX_SIZE - $M7_MROM_SIZE;
+    $m7_80c_romStartPosition   = $m7_romEndPosition + 1;
+    $m7_80c_romEndPosition     = $m7_80c_romStartPosition + $M7_80C_MROM_MAX_SIZE -1;
+    $m7_80c_romPadding         = $M7_80C_MROM_MAX_SIZE - $M7_80C_MROM_SIZE;
+    $m7_userromStartPosition   = $m7_80c_romEndPosition + 1;
+    $m7_userromEndPosition     = $m7_userromStartPosition + $M7_USERROM_MAX_SIZE -1;
+    $m7_userromPadding         = $M7_USERROM_MAX_SIZE - $M7_USERROM_SIZE;
+    $m7_fdcromStartPosition    = $m7_userromEndPosition + 1;
+    $m7_fdcromEndPosition      = $m7_fdcromStartPosition + $M7_FDCROM_MAX_SIZE -1;
+    $m7_fdcromPadding          = $M7_FDCROM_MAX_SIZE - $M7_FDCROM_SIZE;
+    $m8_romStartPosition       = $m7_fdcromEndPosition + 1;
+    $m8_romEndPosition         = $m8_romStartPosition + $M8_MROM_MAX_SIZE -1;
+    $m8_romPadding             = $M8_MROM_MAX_SIZE - $M8_MROM_SIZE;
+    $m8_80c_romStartPosition   = $m8_romEndPosition + 1;
+    $m8_80c_romEndPosition     = $m8_80c_romStartPosition + $M8_80C_MROM_MAX_SIZE -1;
+    $m8_80c_romPadding         = $M8_80C_MROM_MAX_SIZE - $M8_80C_MROM_SIZE;
+    $m8_userromStartPosition   = $m8_80c_romEndPosition + 1;
+    $m8_userromEndPosition     = $m8_userromStartPosition + $M8_USERROM_MAX_SIZE -1;
+    $m8_userromPadding         = $M8_USERROM_MAX_SIZE - $M8_USERROM_SIZE;
+    $m8_fdcromStartPosition    = $m8_userromEndPosition + 1;
+    $m8_fdcromEndPosition      = $m8_fdcromStartPosition + $M8_FDCROM_MAX_SIZE -1;
+    $m8_fdcromPadding          = $M8_FDCROM_MAX_SIZE - $M8_FDCROM_SIZE;
+    $b_romStartPosition        = $m8_fdcromEndPosition + 1;
+    $b_romEndPosition          = $b_romStartPosition + $B_MROM_MAX_SIZE -1;
+    $b_romPadding              = $B_MROM_MAX_SIZE - $B_MROM_SIZE;
+    $b_80c_romStartPosition    = $b_romEndPosition + 1;
+    $b_80c_romEndPosition      = $b_80c_romStartPosition + $B_80C_MROM_MAX_SIZE -1;
+    $b_80c_romPadding          = $B_80C_MROM_MAX_SIZE - $B_80C_MROM_SIZE;
+    $b_userromStartPosition    = $b_80c_romEndPosition + 1;
+    $b_userromEndPosition      = $b_userromStartPosition + $B_USERROM_MAX_SIZE -1;
+    $b_userromPadding          = $B_USERROM_MAX_SIZE - $B_USERROM_SIZE;
+    $b_fdcromStartPosition     = $b_userromEndPosition + 1;
+    $b_fdcromEndPosition       = $b_fdcromStartPosition + $B_FDCROM_MAX_SIZE -1;
+    $b_fdcromPadding           = $B_FDCROM_MAX_SIZE - $B_FDCROM_SIZE;
+    $m20_romStartPosition      = $b_fdcromEndPosition + 1;
+    $m20_romEndPosition        = $m20_romStartPosition + $M20_MROM_MAX_SIZE -1;
+    $m20_romPadding            = $M20_MROM_MAX_SIZE - $M20_MROM_SIZE;
+    $m20_80c_romStartPosition  = $m20_romEndPosition + 1;
+    $m20_80c_romEndPosition    = $m20_80c_romStartPosition + $M20_80C_MROM_MAX_SIZE -1;
+    $m20_80c_romPadding        = $M20_80C_MROM_MAX_SIZE - $M20_80C_MROM_SIZE;
+    $m20_userromStartPosition  = $m20_80c_romEndPosition + 1;
+    $m20_userromEndPosition    = $m20_userromStartPosition + $M20_USERROM_MAX_SIZE -1;
+    $m20_userromPadding        = $M20_USERROM_MAX_SIZE - $M20_USERROM_SIZE;
+    $m20_fdcromStartPosition   = $m20_userromEndPosition + 1;
+    $m20_fdcromEndPosition     = $m20_fdcromStartPosition + $M20_FDCROM_MAX_SIZE -1;
+    $m20_fdcromPadding         = $M20_FDCROM_MAX_SIZE - $M20_FDCROM_SIZE;
+    for(my $idx=$m20_fdcromEndPosition; $idx < 131071; $idx++) { push @MonitorMemory, "\x00"; };
+
+    # Finally, print out details for confirmation.
+    #
+    logWrite("", sprintf "Monitor ROM Map:\n");
+    logWrite("", sprintf "                  80K MROM           =%04x:%04x %04x bytes padding", $k_romStartPosition,       $k_romEndPosition,       $k_romPadding);
+    logWrite("", sprintf "           80x25  80K MROM           =%04x:%04x %04x bytes padding", $k_80c_romStartPosition,   $k_80c_romEndPosition,   $k_80c_romPadding);
+    logWrite("", sprintf "            USER  80K  ROM           =%04x:%04x %04x bytes padding", $k_userromStartPosition,   $k_userromEndPosition,   $k_userromPadding);
+    logWrite("", sprintf "            FDC   80K  ROM           =%04x:%04x %04x bytes padding", $k_fdcromStartPosition,    $k_fdcromEndPosition,    $k_fdcromPadding);
+    logWrite("", sprintf "                  80C MROM           =%04x:%04x %04x bytes padding", $c_romStartPosition,       $c_romEndPosition,       $c_romPadding);
+    logWrite("", sprintf "           80x25  80C MROM           =%04x:%04x %04x bytes padding", $c_80c_romStartPosition,   $c_80c_romEndPosition,   $c_80c_romPadding);
+    logWrite("", sprintf "            USER  80C  ROM           =%04x:%04x %04x bytes padding", $c_userromStartPosition,   $c_userromEndPosition,   $c_userromPadding);
+    logWrite("", sprintf "            FDC   80C  ROM           =%04x:%04x %04x bytes padding", $c_fdcromStartPosition,    $c_fdcromEndPosition,    $c_fdcromPadding);
+    logWrite("", sprintf "                 1200 MROM           =%04x:%04x %04x bytes padding", $m12_romStartPosition,     $m12_romEndPosition,     $m12_romPadding);
+    logWrite("", sprintf "           80x25 1200 MROM           =%04x:%04x %04x bytes padding", $m12_80c_romStartPosition, $m12_80c_romEndPosition, $m12_80c_romPadding);
+    logWrite("", sprintf "            USER 1200  ROM           =%04x:%04x %04x bytes padding", $m12_userromStartPosition, $m12_userromEndPosition, $m12_userromPadding);
+    logWrite("", sprintf "            FDC  1200  ROM           =%04x:%04x %04x bytes padding", $m12_fdcromStartPosition,  $m12_fdcromEndPosition,  $m12_fdcromPadding);
+    logWrite("", sprintf "                  80A MROM           =%04x:%04x %04x bytes padding", $a_romStartPosition,       $a_romEndPosition,       $a_romPadding);
+    logWrite("", sprintf "           80x25  80A MROM           =%04x:%04x %04x bytes padding", $a_80c_romStartPosition,   $a_80c_romEndPosition,   $a_80c_romPadding);
+    logWrite("", sprintf "            USER  80A  ROM           =%04x:%04x %04x bytes padding", $a_userromStartPosition,   $a_userromEndPosition,   $a_userromPadding);
+    logWrite("", sprintf "            FDC   80A  ROM           =%04x:%04x %04x bytes padding", $a_fdcromStartPosition,    $a_fdcromEndPosition,    $a_fdcromPadding);
+    logWrite("", sprintf "                  700 MROM           =%04x:%04x %04x bytes padding", $m7_romStartPosition,      $m7_romEndPosition,      $m7_romPadding);
+    logWrite("", sprintf "           80x25  700 MROM           =%04x:%04x %04x bytes padding", $m7_80c_romStartPosition,  $m7_80c_romEndPosition,  $m7_80c_romPadding);
+    logWrite("", sprintf "            USER  700  ROM           =%04x:%04x %04x bytes padding", $m7_userromStartPosition,  $m7_userromEndPosition,  $m7_userromPadding);
+    logWrite("", sprintf "            FDC   700  ROM           =%04x:%04x %04x bytes padding", $m7_fdcromStartPosition,   $m7_fdcromEndPosition,   $m7_fdcromPadding);
+    logWrite("", sprintf "                  800 MROM           =%04x:%04x %04x bytes padding", $m8_romStartPosition,      $m8_romEndPosition,      $m8_romPadding);
+    logWrite("", sprintf "           80x25  800 MROM           =%04x:%04x %04x bytes padding", $m8_80c_romStartPosition,  $m8_80c_romEndPosition,  $m8_80c_romPadding);
+    logWrite("", sprintf "            USER  800  ROM           =%04x:%04x %04x bytes padding", $m8_userromStartPosition,  $m8_userromEndPosition,  $m8_userromPadding);
+    logWrite("", sprintf "            FDC   800  ROM           =%04x:%04x %04x bytes padding", $m8_fdcromStartPosition,   $m8_fdcromEndPosition,   $m8_fdcromPadding);
+    logWrite("", sprintf "                  80B MROM           =%04x:%04x %04x bytes padding", $b_romStartPosition,       $b_romEndPosition,       $b_romPadding);
+    logWrite("", sprintf "           80x25  80B MROM           =%04x:%04x %04x bytes padding", $b_80c_romStartPosition,   $b_80c_romEndPosition,   $b_romPadding);
+    logWrite("", sprintf "            USER  80B  ROM           =%04x:%04x %04x bytes padding", $b_userromStartPosition,   $b_userromEndPosition,   $b_userromPadding);
+    logWrite("", sprintf "            FDC   80B  ROM           =%04x:%04x %04x bytes padding", $b_fdcromStartPosition,    $b_fdcromEndPosition,    $b_fdcromPadding);
+    logWrite("", sprintf "                 2000 MROM           =%04x:%04x %04x bytes padding", $m20_romStartPosition,     $m20_romEndPosition,     $m20_romPadding);
+    logWrite("", sprintf "           80x25 2000 MROM           =%04x:%04x %04x bytes padding", $m20_80c_romStartPosition, $m20_80c_romEndPosition, $m20_romPadding);
+    logWrite("", sprintf "            USER 2000  ROM           =%04x:%04x %04x bytes padding", $m20_userromStartPosition, $m20_userromEndPosition, $m20_userromPadding);
+    logWrite("", sprintf "            FDC  2000  ROM           =%04x:%04x %04x bytes padding", $m20_fdcromStartPosition,  $m20_fdcromEndPosition,  $m20_fdcromPadding);
+}
+elsif($command eq "CGROM")
+{
+    # Initialize in memory image.
+    @CGMemory = ();
+
+    # Fill the memory image with equisize images.=.
+    foreach my $byte (@K_CGROM)   { push @CGMemory, $byte; };  
+    foreach my $byte (@C_CGROM)   { push @CGMemory, $byte; };  
+    foreach my $byte (@M12_CGROM) { push @CGMemory, $byte; }; 
+    foreach my $byte (@A_CGROM)   { push @CGMemory, $byte; };  
+    foreach my $byte (@M7_CGROM)  { push @CGMemory, $byte; }; 
+    foreach my $byte (@M8_CGROM)  { push @CGMemory, $byte; }; 
+    foreach my $byte (@B_CGROM)   { push @CGMemory, $byte; }; 
+    foreach my $byte (@M20_CGROM) { push @CGMemory, $byte; }; 
+
+    # Positions for easy reference.
+    $k_romStartPosition        = 0;
+    $k_romEndPosition          = $K_CGROM_SIZE -1;
+    $c_romStartPosition        = $k_romEndPosition + 1;
+    $c_romEndPosition          = $c_romStartPosition + $C_CGROM_SIZE -1;
+    $m12_romStartPosition      = $c_romEndPosition + 1;
+    $m12_romEndPosition        = $m12_romStartPosition + $M12_CGROM_SIZE -1;
+    $a_romStartPosition        = $m12_romEndPosition + 1;
+    $a_romEndPosition          = $a_romStartPosition + $A_CGROM_SIZE -1;
+    $m7_romStartPosition       = $a_romEndPosition + 1;
+    $m7_romEndPosition         = $m7_romStartPosition + $M7_CGROM_SIZE  -1;
+    $m8_romStartPosition       = $m7_romEndPosition + 1;
+    $m8_romEndPosition         = $m8_romStartPosition + $M8_CGROM_SIZE  -1;
+    $b_romStartPosition        = $m8_romEndPosition + 1;
+    $b_romEndPosition          = $b_romStartPosition + $B_CGROM_SIZE  -1;
+    $m20_romStartPosition      = $b_romEndPosition + 1;
+    $m20_romEndPosition        = $m20_romStartPosition + $M20_CGROM_SIZE  -1;
+
+    # Finally, print out details for confirmation.
+    #
+    logWrite("", sprintf "Character Generator ROM Map:\n");
+    logWrite("", sprintf "                 80K CGROM           =%04x:%04x", $k_romStartPosition,    $k_romEndPosition);
+    logWrite("", sprintf "                 80C CGROM           =%04x:%04x", $c_romStartPosition,    $c_romEndPosition);
+    logWrite("", sprintf "                1200 CGROM           =%04x:%04x", $m12_romStartPosition,  $m12_romEndPosition);
+    logWrite("", sprintf "                 80A CGROM           =%04x:%04x", $a_romStartPosition,    $a_romEndPosition);
+    logWrite("", sprintf "                 700 CGROM           =%04x:%04x", $m7_romStartPosition,   $m7_romEndPosition);
+    logWrite("", sprintf "                 800 CGROM           =%04x:%04x", $m8_romStartPosition,   $m8_romEndPosition);
+    logWrite("", sprintf "                 80B CGROM           =%04x:%04x", $b_romStartPosition,    $b_romEndPosition);
+    logWrite("", sprintf "                2000 CGROM           =%04x:%04x", $m20_romStartPosition,  $m20_romEndPosition);
+}
+elsif($command eq "KEYMAP")
+{
+    # Initialize in memory image.
+    @KeyMemory = ();
+
+    $maxSize = $A_KEYMAP_SIZE;
+    if($K_KEYMAP_SIZE > $maxSize)   { $maxSize = $K_KEYMAP_SIZE; }
+    if($C_KEYMAP_SIZE > $maxSize)   { $maxSize = $C_KEYMAP_SIZE; }
+    if($M12_KEYMAP_SIZE > $maxSize) { $maxSize = $M12_KEYMAP_SIZE; }
+    if($M7_KEYMAP_SIZE > $maxSize)  { $maxSize = $M7_KEYMAP_SIZE; }
+    if($M8_KEYMAP_SIZE > $maxSize)  { $maxSize = $M8_KEYMAP_SIZE; }
+    if($B_KEYMAP_SIZE > $maxSize)   { $maxSize = $B_KEYMAP_SIZE; }
+    if($M20_KEYMAP_SIZE > $maxSize) { $maxSize = $M20_KEYMAP_SIZE; }
+
+    # Fill the memory image with equisize images, zero padding as necessary.
+    foreach my $byte (@K_KEYMAP)   { push @KeyMemory, $byte; }; for(my $idx=$K_KEYMAP_SIZE; $idx < $maxSize; $idx++)   { push @KeyMemory, "\x00"; };
+    foreach my $byte (@C_KEYMAP)   { push @KeyMemory, $byte; }; for(my $idx=$C_KEYMAP_SIZE; $idx < $maxSize; $idx++)   { push @KeyMemory, "\x00"; };
+    foreach my $byte (@M12_KEYMAP) { push @KeyMemory, $byte; }; for(my $idx=$M12_KEYMAP_SIZE; $idx < $maxSize; $idx++) { push @KeyMemory, "\x00"; };
+    foreach my $byte (@A_KEYMAP)   { push @KeyMemory, $byte; }; for(my $idx=$A_KEYMAP_SIZE; $idx < $maxSize; $idx++)   { push @KeyMemory, "\x00"; };
+    foreach my $byte (@M7_KEYMAP)  { push @KeyMemory, $byte; }; for(my $idx=$M7_KEYMAP_SIZE; $idx < $maxSize; $idx++)  { push @KeyMemory, "\x00"; };
+    foreach my $byte (@M8_KEYMAP)  { push @KeyMemory, $byte; }; for(my $idx=$M8_KEYMAP_SIZE; $idx < $maxSize; $idx++)  { push @KeyMemory, "\x00"; };
+    foreach my $byte (@B_KEYMAP)   { push @KeyMemory, $byte; }; for(my $idx=$B_KEYMAP_SIZE; $idx < $maxSize; $idx++)   { push @KeyMemory, "\x00"; };
+    foreach my $byte (@M20_KEYMAP) { push @KeyMemory, $byte; }; for(my $idx=$M20_KEYMAP_SIZE; $idx < $maxSize; $idx++) { push @KeyMemory, "\x00"; };
+
+    # Positions for easy reference.
+    $k_romStartPosition        = 0;
+    $k_romEndPosition          = $K_KEYMAP_SIZE + ($maxSize - $K_KEYMAP_SIZE) -1;
+    $k_romPadding              = $maxSize - $K_KEYMAP_SIZE;
+    $c_romStartPosition        = $k_romEndPosition + 1;
+    $c_romEndPosition          = $c_romStartPosition + $C_KEYMAP_SIZE + ($maxSize - $C_KEYMAP_SIZE) -1;
+    $c_romPadding              = $maxSize - $C_KEYMAP_SIZE;
+    $m12_romStartPosition      = $c_romEndPosition + 1;
+    $m12_romEndPosition        = $m12_romStartPosition + $M12_KEYMAP_SIZE + ($maxSize - $M12_KEYMAP_SIZE) -1;
+    $m12_romPadding            = $maxSize - $M12_KEYMAP_SIZE;
+    $a_romStartPosition        = $m12_romEndPosition + 1;
+    $a_romEndPosition          = $a_romStartPosition + $A_KEYMAP_SIZE + ($maxSize - $A_KEYMAP_SIZE) -1;
+    $a_romPadding              = $maxSize - $A_KEYMAP_SIZE;
+    $m7_romStartPosition       = $a_romEndPosition + 1;
+    $m7_romEndPosition         = $m7_romStartPosition + $M7_KEYMAP_SIZE + ($maxSize - $M7_KEYMAP_SIZE) -1;
+    $m7_romPadding             = $maxSize - $M7_KEYMAP_SIZE;
+    $m8_romStartPosition       = $m7_romEndPosition + 1;
+    $m8_romEndPosition         = $m8_romStartPosition + $M8_KEYMAP_SIZE + ($maxSize - $M8_KEYMAP_SIZE) -1;
+    $m8_romPadding             = $maxSize - $M8_KEYMAP_SIZE;
+    $b_romStartPosition        = $m7_romEndPosition + 1;
+    $b_romEndPosition          = $b_romStartPosition + $B_KEYMAP_SIZE + ($maxSize - $B_KEYMAP_SIZE) -1;
+    $b_romPadding              = $maxSize - $B_KEYMAP_SIZE;
+    $m20_romStartPosition      = $b_romEndPosition + 1;
+    $m20_romEndPosition        = $m20_romStartPosition + $M20_KEYMAP_SIZE + ($maxSize - $M20_KEYMAP_SIZE) -1;
+    $m20_romPadding            = $maxSize - $M20_KEYMAP_SIZE;
+
+    # Finally, print out details for confirmation.
+    #
+    logWrite("", sprintf "Key Mapping ROM Map:\n");
+    logWrite("", sprintf "                80K KEYMAP           =%04x:%04x %04x bytes padding", $k_romStartPosition,   $k_romEndPosition,   $k_romPadding);
+    logWrite("", sprintf "                80C KEYMAP           =%04x:%04x %04x bytes padding", $c_romStartPosition,   $c_romEndPosition,   $c_romPadding);
+    logWrite("", sprintf "               1200 KEYMAP           =%04x:%04x %04x bytes padding", $m12_romStartPosition, $m12_romEndPosition, $m12_romPadding);
+    logWrite("", sprintf "                80A KEYMAP           =%04x:%04x %04x bytes padding", $a_romStartPosition,   $a_romEndPosition,   $a_romPadding);
+    logWrite("", sprintf "                700 KEYMAP           =%04x:%04x %04x bytes padding", $m7_romStartPosition,  $m7_romEndPosition,  $m7_romPadding);
+    logWrite("", sprintf "                800 KEYMAP           =%04x:%04x %04x bytes padding", $m8_romStartPosition,  $m8_romEndPosition,  $m8_romPadding);
+    logWrite("", sprintf "                80B KEYMAP           =%04x:%04x %04x bytes padding", $b_romStartPosition,   $b_romEndPosition,   $b_romPadding);
+    logWrite("", sprintf "               2000 KEYMAP           =%04x:%04x %04x bytes padding", $m20_romStartPosition, $m20_romEndPosition, $m20_romPadding);
+}
+else
+{
+    argOptions(1, "Illegal command given on command line:$command.\n",$ERR_BADARGUMENTS);
+}
+
+# Output the memory image to the output file.
+#
+if   (scalar @MainMemory > 0)
+{
+    foreach my $byte (@MainMemory) { print OUTFILE $byte; }
+}
+elsif(scalar @MonitorMemory > 0)
+{
+    foreach my $byte (@MonitorMemory) { print OUTFILE $byte; }
+}
+elsif(scalar @CGMemory > 0)
+{
+    foreach my $byte (@CGMemory) { print OUTFILE $byte; }
+}
+elsif(scalar @KeyMemory > 0)
+{
+    foreach my $byte (@KeyMemory) { print OUTFILE $byte; }
+}
+
+# If a MIF file is required, create it.
+#
+if($createMIF == 1)
+{
+    if   (scalar @MainMemory > 0)
+    {
+        createMIF(\@MainMemory, MIFOUTFILE);
+    }
+    elsif(scalar @MonitorMemory > 0)
+    {
+        createMIF(\@MonitorMemory, MIFOUTFILE);
+    }
+    elsif(scalar @CGMemory > 0)
+    {
+        createMIF(\@CGMemory, MIFOUTFILE);
+    }
+    elsif(scalar @KeyMemory > 0)
+    {
+        createMIF(\@KeyMemory, MIFOUTFILE);
+    }
+}
+
+exit 0;
diff --git a/wiki.txt b/wiki.txt
new file mode 100644
index 0000000..5068b0a
--- /dev/null
+++ b/wiki.txt
@@ -0,0 +1,41 @@
+# Welcome to the MiSTer wiki!
+
+_DISCLAIMER: this is an open project without focus on sales. Base hardware (Terasic DE10-Nano) can be bought from major electronic component resellers and will run a few cores out of the box. No soldering is needed_ 
+
+_DISCLAIMER2: Many cores require RAM expansion hardware which can be assembled or bought from a few sources in the forums. The author of this project and contributors are NOT affiliated to these vendors and do not derive any income from it. Please direct any inquiries or concerns about expansion hardware to relevant third parties_
+
+![photo](pictures/MiSTer.jpg)
+
+## What is it?
+
+	MiSTer is a port of well known MiST project to a larger FPGA and faster ARM. MiSTer provides modern video output through HDMI (VGA and analog audio are still available on daughter board). It's based on [**Terasic DE10-nano**](http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046) board.
+	Here are some improvement over the MiST board:
+
+	* Altera Cyclone V SE FPGA with 110,000LE (41,500ALM) and 5,570Kbit of Block RAM.
+	* ARM Cortex A9 dual-core CPU at 800MHz.
+	* HDMI video and audio allowing connect to any modern monitor/TV.
+	* DDR3 1GB available for both ARM and FPGA.
+	* High speed ARM<->FPGA interconnect due to both are in the same chip.
+	* Linux on ARM provides support for many I/O devices and file systems.
+	* Board is mass produced by a big manufactured and freely available for a relatively cheap price 130USD (99USD for students/professors).
+
+	Due to a larger FPGA, bigger systems can be created. It's also possible to add more support from ARM side. For example TZX tape format can be parsed on ARM and then send to FPGA. Firmware is not limited by code size or available RAM. It'e even possible to emulate some parts of system on ARM which is not available in FPGA (so-called hybrid emulator). 
+
+	MiSTer scales original video resolution to a standard HDMI resolution (usually 1280x720p60), so you don't need to look for some ancient monitor with VGA input supporting non-standard resolution and frame rates. For purists VGA is still available and it outputs original video resolution.
+
+## How does it work?
+
+	MiSTer adds several [daughter boards](https://github.com/MiSTer-devel/Hardware_MiSTer) to original DE10-nano board. **You don't need to install all boards.** MiSTer starts from entry level as a bare DE10-nano board. With just one additional board (SDRAM), you will be able to use almost all cores.
+	* **SDRAM board** _(recommended expansion)_ This small board plugs into the GPIO0 connector of the DE10-nano board. Whilst the DE10-nano has fast DDR3 memory, it cannot be used to emulate a retro EDO DRAM due to a high latency and shared usage from ARM side. This SDR SDRAM on daughter board is required for most cores to emulate a retro memory module.
+	* **I/O board** _(optional expansion)_ This board plugs into the GPIO1 connector of the DE10-nano board. It provides a legacy VGA output (6 bits per component), analog audio (3.5mm phone jack), digital optical audio, buttons, LEDs. This board is useful if you prefer VGA over HDMI or you want to put the MiSTer inside a case. This board also helps for  core development (HDMI scaler code requires around twice more time to compile). Compiling for VGA-only will speed up the development. This board is not required to run most cores.
+	* **RTC board** _(optional expansion)_ This board is plugged into LTC connector and provides a real time clock. You still can have a real time clock without the board if MiSTer is connected to internet via Ethernet. Only two cores use this feature, so it is only for enthusiasts.
+	* **USB hub board** _(optional expansion)_ This board adds 7-port USB hub sitting under the main board.
+
+	Schematics and gerber files are available to download. Boards are considered as DIY(do it yourself). There are no restrictions who and how these board will be manufactured and sold, any 3rd party is welcome to manufacture and sell them.
+
+## Linux?
+
+	DE10 uses Linux for house-keeping duties such as loading data from the SD card. It may feel that Linux may take considerable time to boot, but it isn't the case. The version used by MiSTer has been optimized to only take a couple of seconds to boot. Most monitors and TV requires longer time to lock on the video signal and start to display, so the result is that the MiSTer feels instant-on like original hardware back in the day.
+
+## More info
+	Discussion about the project is [here](http://www.atari-forum.com/viewforum.php?f=117)
diff --git a/wiki_index.txt b/wiki_index.txt
new file mode 100644
index 0000000..c56c745
--- /dev/null
+++ b/wiki_index.txt
@@ -0,0 +1,131 @@
+Wiki
+### [Home](.)
+* [Why FPGA?](Why-FPGA)
+	* [How to start](How-to-start-with-MiSTer)
+	* [Setup Guide](Setup-Guide)
+	* [Input devices](Input-devices)
+	* [FTP, SSH/SFTP](Network-access)
+	* [Samba](https://github.com/MiSTer-devel/Main_MiSTer/wiki/Samba)
+	* [WiFi](WiFi-setup)
+	* [Console connection](Console-connection)
+	* [Internet for Amiga/ao486](Internet-and-console-connection-from-supported-cores)
+	* [Configuration Files](Configuration-Files)
+	* [Desktop Linux](https://github.com/MiSTer-devel/Main_MiSTer/wiki/Desktop-Linux)
+	* [Discussion](http://www.atari-forum.com/viewforum.php?f=117)
+	* [Donate](Donate)
+
+### Add-Ons
+	* [How to get boards?](How-to-get-your-own-addon-boards)
+	* [SDRAM Board](SDRAM-Board)
+	  * [ Assembly (DIY) ](SDRAM-Board-Assembly-(DIY))
+	  * [ Core support ](SDRAM-Requirement-by-cores)
+	* [IO Board](IO-Board)
+	  * [ Assembly (DIY) ](IO-Board-Assembly-(DIY))
+	  * [ Secondary SD card ](Secondary-SD-card)
+	* [RTC board](RTC-board)
+	  * [ Assembly (DIY) ](RTC-Board-Assembly-(DIY))
+	  * [ Core support ](Cores-supporting-RTC)
+	* [USB Hub](USB-Hub-daughter-board)
+	  * [ USB Hub Assembly (DIY) ](USB-Hub-Assembly-(DIY))
+	* Case
+	  * [3D-printed (DIY)](MiSTer-case)
+	  * [Pi-Top (v1)](Pi-Top-v1)
+
+### Cores
+	* [Boot Menu](https://github.com/MiSTer-devel/Menu_MiSTer)
+	* [Acorn Archimedes](https://github.com/MiSTer-devel/Archie_MiSTer)
+	* [Amiga](https://github.com/MiSTer-devel/Minimig-AGA_MiSTer)
+	* [Amstrad CPC 6128](https://github.com/MiSTer-devel/Amstrad_MiSTer)
+	* [ao486](https://github.com/MiSTer-devel/ao486_MiSTer)
+	* [Apogee](https://github.com/MiSTer-devel/Apogee_MiSTer)
+	* [Apple II+](https://github.com/MiSTer-devel/Apple-II_MiSTer)
+	* [Apple Macintosh Plus](https://github.com/MiSTer-devel/MacPlus_MiSTer)
+	* [Aquarius](https://github.com/MiSTer-devel/Aquarius_MISTer)
+	* [Atari 800XL, Atari 5200](https://github.com/MiSTer-devel/Atari800_MiSTer)
+	* [Atari 2600](https://github.com/MiSTer-devel/Atari2600_MiSTer)
+	* [BBC Micro B,Master](https://github.com/MiSTer-devel/BBCMicro_MiSTer)
+	* [BK0011M](https://github.com/MiSTer-devel/BK0011M_MiSTer)
+	* [ColecoVision](https://github.com/MiSTer-devel/ColecoVision_MiSTer)
+	* [Commodore 64, Ultimax](https://github.com/MiSTer-devel/C64_MiSTer)
+	* [Commodore 16, Plus/4](https://github.com/MiSTer-devel/C16_MiSTer)
+	* [Commodore PET](https://github.com/MiSTer-devel/PET2001_MiSTer)
+	* [Commodore VIC-20](https://github.com/MiSTer-devel/VIC20_MiSTer)
+	* [Gameboy](https://github.com/MiSTer-devel/Gameboy_MiSTer)
+	* [Jupiter Ace](https://github.com/MiSTer-devel/Jupiter_MiSTer)
+	* [MSX](https://github.com/MiSTer-devel/MSX_MiSTer)
+	* [MultiComp](https://github.com/MiSTer-devel/MultiComp_MiSTer)
+	* [NES](https://github.com/MiSTer-devel/NES_MiSTer)
+	* [SAM Coupe](https://github.com/MiSTer-devel/SAM-Coupe_MiSTer)
+	* [Sega Genesis/Megadrive](https://github.com/MiSTer-devel/Genesis_MiSTer)
+	* [Sega Master System](https://github.com/MiSTer-devel/SMS_MiSTer)
+	* [Sharp MZ Series](https://github.com/MiSTer-devel/SharpMZ_MiSTer)
+	* [Sinclair QL](https://github.com/MiSTer-devel/QL_MiSTer)
+	* [Specialist/MX](https://github.com/MiSTer-devel/Specialist_MiSTer)
+	* [TSConf](https://github.com/MiSTer-devel/TSConf_MiSTer)
+	* [TurboGrafx 16 / PC Engine](https://github.com/MiSTer-devel/TurboGrafx16_MiSTer)
+	* [Vectrex](https://github.com/MiSTer-devel/Vectrex_MiSTer)
+	* [Vector 06C](https://github.com/MiSTer-devel/Vector-06C_MiSTer)
+	* [X68000](https://github.com/MiSTer-devel/X68000_MiSTer)
+	* [ZX Spectrum](https://github.com/MiSTer-devel/ZX-Spectrum_MISTer)
+	* [ZX81](https://github.com/MiSTer-devel/ZX81_MiSTer)
+
+### Arcade Cores
+	* [Alibaba and 40 Thieves](https://github.com/MiSTer-devel/Arcade-Alibaba_MiSTer)
+	* [Azurian](https://github.com/MiSTer-devel/Arcade-Azurian_MiSTer)
+	* [Amidar](https://github.com/MiSTer-devel/Arcade-Amidar_MiSTer)
+	* [Bagman](https://github.com/MiSTer-devel/Arcade-Bagman_MiSTer)
+	* [Black Hole](https://github.com/MiSTer-devel/Arcade-BlackHole_MiSTer)
+	* [Bomb Jack](https://github.com/MiSTer-devel/Arcade-BombJack_MiSTer)
+	* [Burger Time](https://github.com/MiSTer-devel/Arcade-BurgerTime_MiSTer)
+	* [Burning Rubber](https://github.com/MiSTer-devel/Arcade-BurningRubber_MiSTer)
+	* [Catacomb](https://github.com/MiSTer-devel/Arcade-Catacomb_MiSTer)
+	* [Computer Space](https://github.com/MiSTer-devel/Arcade-ComputerSpace_MiSTer)
+	* [Cosmic Avenger](https://github.com/MiSTer-devel/Arcade-CosmicAvenger_MiSTer)
+	* [Crazy Climber](https://github.com/MiSTer-devel/Arcade-CrazyClimber_MiSTer)
+	* [Crazy Kong](https://github.com/MiSTer-devel/Arcade-CrazyKong_MiSTer)
+	* [Crush Roller](https://github.com/MiSTer-devel/Arcade-CrushRoller_MiSTer)
+	* [Defender](https://github.com/MiSTer-devel/Arcade-Defender_MiSTer)
+	* [Donkey Kong](https://github.com/MiSTer-devel/Arcade-DonkeyKong_MiSTer)
+	* [Dorodon](https://github.com/MiSTer-devel/Arcade-Dorodon_MiSTer)
+	* [Dream Shopper](https://github.com/MiSTer-devel/Arcade-DreamShopper_MiSTer)
+	* [Eeekk!](https://github.com/MiSTer-devel/Arcade-Eeekk_MiSTer)
+	* [Eyes](https://github.com/MiSTer-devel/Arcade-Eyes_MiSTer)
+	* [Frogger](https://github.com/MiSTer-devel/Arcade-Frogger_MiSTer)
+	* [Galaga](https://github.com/MiSTer-devel/Arcade-Galaga_MiSTer)
+	* [Galaxian](https://github.com/MiSTer-devel/Arcade-Galaxian_MiSTer)
+	* [Gorkans](https://github.com/MiSTer-devel/Arcade-Gorkans_MiSTer)
+	* [Lady Bug](https://github.com/MiSTer-devel/Arcade-LadyBug_MiSTer)
+	* [Lizard Wizard](https://github.com/MiSTer-devel/Arcade-LizardWizard_MiSTer)
+	* [Moon Cresta](https://github.com/MiSTer-devel/Arcade-MoonCresta_MiSTer)
+	* [Moon Patrol](https://github.com/MiSTer-devel/Arcade-MoonPatrol_MiSTer)
+	* [Mr.Do's Nightmare](https://github.com/MiSTer-devel/Arcade-MrDoNightmare_MiSTer)
+	* [Mr.TNT](https://github.com/MiSTer-devel/Arcade-MrTNT_MiSTer)
+	* [Ms.Pacman](https://github.com/MiSTer-devel/Arcade-MsPacman_MiSTer)
+	* [Omega](https://github.com/MiSTer-devel/Arcade-Omega_MiSTer)
+	* [Orbitron](https://github.com/MiSTer-devel/Arcade-Orbitron_MiSTer)
+	* [Pacman](https://github.com/MiSTer-devel/Arcade-Pacman_MiSTer)
+	* [Pacman Club](https://github.com/MiSTer-devel/Arcade-PacmanClub_MiSTer)
+	* [Pacman Plus](https://github.com/MiSTer-devel/Arcade-PacmanPlus_MiSTer)
+	* [Pacmanic Miner](https://github.com/MiSTer-devel/Arcade-PacmanicMiner_MiSTer)
+	* [Pengo](https://github.com/MiSTer-devel/Arcade-Pengo_MiSTer)
+	* [Phoenix](https://github.com/MiSTer-devel/Arcade-Phoenix_MiSTer)
+	* [Pisces](https://github.com/MiSTer-devel/Arcade-Pisces_MiSTer)
+	* [Ponpoko](https://github.com/MiSTer-devel/Arcade-Ponpoko_MiSTer)
+	* [Pooyan](https://github.com/MiSTer-devel/Arcade-Pooyan_MiSTer)
+	* [Scramble](https://github.com/MiSTer-devel/Arcade-Scramble_MiSTer)
+	* [Snap Jack](https://github.com/MiSTer-devel/Arcade-SnapJack_MiSTer)
+	* [Super Glob](https://github.com/MiSTer-devel/Arcade-SuperGlob_MiSTer)
+	* [The End](https://github.com/MiSTer-devel/Arcade-TheEnd_MiSTer)
+	* [Time Pilot](https://github.com/MiSTer-devel/Arcade-TimePilot_MiSTer)
+	* [Van-Van Car](https://github.com/MiSTer-devel/Arcade-VanVanCar_MiSTer)
+	* [War of the Bugs](https://github.com/MiSTer-devel/Arcade-WarOfTheBugs_MiSTer)
+	* [Woodpecker](https://github.com/MiSTer-devel/Arcade-Woodpecker_MiSTer)
+	* [Xevious](https://github.com/MiSTer-devel/Arcade-Xevious_MiSTer)
+
+### Service cores
+	* [SDRAM board test](https://github.com/MiSTer-devel/MemTest_MiSTer)
+
+### Development
+	* [Core porting notes](Core-porting-notes)
+	* [Core configuration string](Core-configuration-string)
+	* [USB Blaster (Debugging, SOF)](USB-Blaster-(debugging))