161 lines
7.0 KiB
VHDL
161 lines
7.0 KiB
VHDL
---------------------------------------------------------------------------------------------------------
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--
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-- Name: dprom.vhd
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-- Created: July 2018
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-- Author(s): Altera/Intel - refactored by Philip Smart
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-- Description: Dual Port ROM as provided by Altera in the Megafunctions suite.
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--
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-- Credits:
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-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
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--
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-- History: July 2018 - Initial module written.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY dprom IS
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GENERIC
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(
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init_file : string := "";
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widthad_a : natural;
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width_a : natural := 8;
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outdata_reg_a : string := "UNREGISTERED";
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outdata_reg_b : string := "UNREGISTERED"
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);
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PORT
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(
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address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock_a : IN STD_LOGIC ;
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data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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wren_a : IN STD_LOGIC;
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q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock_b : IN STD_LOGIC ;
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data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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wren_b : IN STD_LOGIC;
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q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
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);
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END dprom;
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ARCHITECTURE SYN OF dprom IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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COMPONENT altsyncram
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GENERIC (
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address_reg_b : STRING;
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clock_enable_input_a : STRING;
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clock_enable_input_b : STRING;
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clock_enable_output_a : STRING;
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clock_enable_output_b : STRING;
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indata_reg_b : STRING;
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init_file : STRING;
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intended_device_family : STRING;
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lpm_type : STRING;
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numwords_a : NATURAL;
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numwords_b : NATURAL;
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operation_mode : STRING;
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outdata_aclr_a : STRING;
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outdata_aclr_b : STRING;
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outdata_reg_a : STRING;
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outdata_reg_b : STRING;
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power_up_uninitialized : STRING;
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read_during_write_mode_port_a : STRING;
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read_during_write_mode_port_b : STRING;
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widthad_a : NATURAL;
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widthad_b : NATURAL;
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width_a : NATURAL;
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width_b : NATURAL;
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width_byteena_a : NATURAL;
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width_byteena_b : NATURAL;
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wrcontrol_wraddress_reg_b : STRING
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);
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PORT (
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address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock0 : IN STD_LOGIC ;
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data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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wren_a : IN STD_LOGIC ;
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q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock1 : IN STD_LOGIC ;
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data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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wren_b : IN STD_LOGIC ;
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q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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q_a <= sub_wire0(width_a-1 DOWNTO 0);
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q_b <= sub_wire1(width_a-1 DOWNTO 0);
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altsyncram_component : altsyncram
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GENERIC MAP (
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address_reg_b => "CLOCK1",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_b => "BYPASS",
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clock_enable_output_a => "BYPASS",
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clock_enable_output_b => "BYPASS",
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indata_reg_b => "CLOCK1",
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init_file => init_file,
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intended_device_family => "Cyclone V",
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lpm_type => "altsyncram",
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numwords_a => 2**widthad_a,
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numwords_b => 2**widthad_a,
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operation_mode => "BIDIR_DUAL_PORT",
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--operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_aclr_b => "NONE",
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outdata_reg_a => outdata_reg_a,
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outdata_reg_b => outdata_reg_b,
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power_up_uninitialized => "FALSE",
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read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
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read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
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widthad_a => widthad_a,
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widthad_b => widthad_a,
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width_a => width_a,
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width_b => width_a,
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width_byteena_a => 1,
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width_byteena_b => 1,
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wrcontrol_wraddress_reg_b => "CLOCK1"
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)
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PORT MAP (
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address_a => address_a,
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clock0 => clock_a,
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data_a => data_a,
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wren_a => wren_a,
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q_a => sub_wire0,
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address_b => address_b,
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clock1 => clock_b,
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data_b => data_b,
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wren_b => wren_b,
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q_b => sub_wire1
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);
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END SYN;
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