648 lines
31 KiB
VHDL
648 lines
31 KiB
VHDL
--
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-- mz80b_video.vhd
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--
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-- Video display signal generator
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-- for MZ-80B on FPGA
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--
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-- Nibbles Lab. 2013-2014
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity mz80b_video is
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Port (
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RST_n : in std_logic; -- Reset
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BOOTM : in std_logic; -- BOOT Mode
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-- Type of machine we are emulating.
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MODE_MZ80B : in std_logic;
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MODE_MZ2000 : in std_logic;
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-- Type of display to emulate.
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DISPLAY_NORMAL : in std_logic;
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DISPLAY_NIDECOM : in std_logic;
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DISPLAY_GAL5 : in std_logic;
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DISPLAY_COLOUR : in std_logic;
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-- Different operations modes.
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CONFIG_PCGRAM : in std_logic; -- PCG Mode Switch, 0 = CGROM, 1 = CGRAM.
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-- Clocks
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CK16M : in std_logic; -- 15.6kHz Dot Clock(16MHz)
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T80_CLK_n : in std_logic; -- Z80 Current Clock
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T80_CLK : in std_logic; -- Z80 Current Clock Inverted
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-- CPU Signals
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T80_A : in std_logic_vector(13 downto 0); -- CPU Address Bus
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CSV_n : in std_logic; -- CPU Memory Request(VRAM)
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CSG_n : in std_logic; -- CPU Memory Request(GRAM)
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T80_RD_n : in std_logic; -- CPU Read Signal
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T80_WR_n : in std_logic; -- CPU Write Signal
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T80_MREQ_n : in std_logic; -- CPU Memory Request
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T80_BUSACK_n : in std_logic; -- CPU Bus Acknowledge
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T80_WAIT_n : out std_logic; -- CPU Wait Request
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T80_DI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
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T80_DO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
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-- Graphic VRAM Access
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GCS_n : out std_logic; -- GRAM Request
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GADR : out std_logic_vector(20 downto 0); -- GRAM Address
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GT80_WR_n : out std_logic; -- GRAM Write Signal
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GBE_n : out std_logic_vector(3 downto 0); -- GRAM Byte Enable
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GDI : in std_logic_vector(31 downto 0); -- Data Bus Input from GRAM
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GDO : out std_logic_vector(31 downto 0); -- Data Bus Output to GRAM
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-- Video Control from outside
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INV : in std_logic; -- Reverse mode(8255 PA4)
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VGATE : in std_logic; -- Video Output Control(8255 PC0)
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CH80 : in std_logic; -- Text Character Width(Z80PIO A5)
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-- Video Signals
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VGATE_n : in std_logic; -- Video Output Control
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HBLANK : out std_logic; -- Horizontal Blanking
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VBLANK : out std_logic; -- Vertical Blanking
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HSYNC_n : out std_logic; -- Horizontal Sync
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VSYNC_n : out std_logic; -- Vertical Sync
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ROUT : out std_logic; -- Red Output
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GOUT : out std_logic; -- Green Output
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BOUT : out std_logic; -- Green Output
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-- HPS Interface
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IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
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IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
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IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
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IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
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IOCTL_DOUT : in std_logic_vector(15 downto 0) -- HPS Data to be written into FPGA.
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IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
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IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
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);
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end mz80b_video;
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architecture RTL of mz80b_video is
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--
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-- Registers
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--
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signal DIV : std_logic_vector(8 downto 0); -- Clock Divider
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signal HCOUNT : std_logic_vector(9 downto 0); -- Counter for Horizontal Signals
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signal VCOUNT : std_logic_vector(8 downto 0); -- Counter for Vertical Signals
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signal VADR : std_logic_vector(10 downto 0); -- VRAM Address(selected)
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signal VADRC : std_logic_vector(10 downto 0); -- VRAM Address
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signal GADRC : std_logic_vector(13 downto 0); -- GRAM Address
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signal GADRi : std_logic_vector(13 downto 0); -- GRAM Address(for GRAM Access)
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signal VADRL : std_logic_vector(10 downto 0); -- VRAM Address(latched)
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signal SDAT : std_logic_vector(7 downto 0); -- Shift Register to Display
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signal SDATB : std_logic_vector(7 downto 0); -- Shift Register to Display
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signal SDATR : std_logic_vector(7 downto 0); -- Shift Register to Display
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signal SDATG : std_logic_vector(7 downto 0); -- Shift Register to Display
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signal S2DAT : std_logic_vector(7 downto 0); -- Shift Register to Display(for 40-char)
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signal S2DAT0 : std_logic_vector(7 downto 0); -- Shift Register to Display(for 80B)
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signal S2DAT1 : std_logic_vector(7 downto 0); -- Shift Register to Display(for 80B)
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--
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-- CPU Access
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--
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signal MA : std_logic_vector(11 downto 0); -- Masked Address
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signal CSB4_x : std_logic; -- Chip Select (PIO-3039 Color Board)
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signal CSF4_x : std_logic; -- Chip Select (Background Color)
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signal CSF5_x : std_logic; -- Chip Select (Display Select for C-Monitor)
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signal CSF6_x : std_logic; -- Chip Select (Display Select for G-Monitor)
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signal CSF7_x : std_logic; -- Chip Select (GRAM Select)
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signal GCSi_x : std_logic; -- Chip Select (GRAM)
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signal RCSV : std_logic; -- Chip Select (VRAM, NiosII)
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signal RCSC : std_logic; -- Chip Select (CGROM, NiosII)
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signal VWEN : std_logic; -- WR + MREQ (VRAM)
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signal RVWEN : std_logic; -- WR + CS (VRAM, NiosII)
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signal RCWEN : std_logic; -- WR + CS (CGROM, NiosII)
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signal WAITi_n : std_logic; -- Wait
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signal WAITii_n : std_logic; -- Wait(delayed)
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signal ZGBE_n : std_logic_vector(3 downto 0); -- Byte Enable by Z80 access
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--
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-- Internal Signals
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--
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signal HDISPEN : std_logic; -- Display Enable for Horizontal, almost same as HBLANK
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signal HBLANKi : std_logic; -- Horizontal Blanking
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signal BLNK : std_logic; -- Horizontal Blanking (for wait)
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signal XBLNK : std_logic; -- Horizontal Blanking (for wait)
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signal VDISPEN : std_logic; -- Display Enable for Vertical, same as VBLANK
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signal MB : std_logic; -- Display Signal (Mono, Blue)
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signal MG : std_logic; -- Display Signal (Mono, Green)
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signal MR : std_logic; -- Display Signal (Mono, Red)
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signal BB : std_logic; -- Display Signal (Color, Blue)
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signal BG : std_logic; -- Display Signal (Color, Green)
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signal BR : std_logic; -- Display Signal (Color, Red)
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signal PBGR : std_logic_vector(2 downto 0); -- Display Signal (Color)
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signal POUT : std_logic_vector(2 downto 0); -- Display Signal (Color)
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signal VRAMDO : std_logic_vector(7 downto 0); -- Data Bus Output for VRAM
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signal DCODE : std_logic_vector(7 downto 0); -- Display Code, Read From VRAM
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signal CGDAT : std_logic_vector(7 downto 0); -- Font Data To Display
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signal CGADR : std_logic_vector(10 downto 0); -- Font Address To Display
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signal CCOL : std_logic_vector(2 downto 0); -- Character Color
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signal BCOL : std_logic_vector(2 downto 0); -- Background Color
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signal CCOLi : std_logic_vector(2 downto 0); -- Character Color(reg)
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signal BCOLi : std_logic_vector(2 downto 0); -- Background Color(reg)
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signal GPRI : std_logic;
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signal GPAGE : std_logic_vector(2 downto 0);
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signal GPAGEi : std_logic_vector(2 downto 0);
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signal GDISPEN : std_logic;
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signal GDISPENi : std_logic;
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signal GBANK : std_logic_vector(1 downto 0);
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signal INVi : std_logic;
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signal VGATEi : std_logic;
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signal GRAMBDI : std_logic_vector(7 downto 0); -- Data from GRAM(Blue)
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signal GRAMRDI : std_logic_vector(7 downto 0); -- Data from GRAM(Red)
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signal GRAMGDI : std_logic_vector(7 downto 0); -- Data from GRAM(Green)
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signal CH80i : std_logic;
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signal CDISPEN : std_logic;
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signal PALET0 : std_logic_vector(2 downto 0);
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signal PALET1 : std_logic_vector(2 downto 0);
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signal PALET2 : std_logic_vector(2 downto 0);
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signal PALET3 : std_logic_vector(2 downto 0);
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signal PALET4 : std_logic_vector(2 downto 0);
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signal PALET5 : std_logic_vector(2 downto 0);
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signal PALET6 : std_logic_vector(2 downto 0);
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signal PALET7 : std_logic_vector(2 downto 0);
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--
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-- Components
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--
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component dprom
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GENERIC (
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init_file : string;
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widthad_a : natural;
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width_a : natural
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);
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PORT
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(
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address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock_a : IN STD_LOGIC ;
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data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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wren_a : IN STD_LOGIC;
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q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock_b : IN STD_LOGIC ;
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data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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wren_b : IN STD_LOGIC;
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q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
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);
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end component;
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component dpram
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generic (
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init_file : string;
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widthad_a : natural;
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width_a : natural
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);
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Port (
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clock_a : in std_logic ;
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clocken_a : in std_logic := '1';
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address_a : in std_logic_vector (widthad_a-1 downto 0);
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data_a : in std_logic_vector (width_a-1 downto 0);
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wren_a : in std_logic;
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q_a : out std_logic_vector (width_a-1 downto 0);
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clock_b : in std_logic ;
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clocken_b : in std_logic := '1';
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address_b : in std_logic_vector (widthad_a-1 downto 0);
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data_b : in std_logic_vector (width_a-1 downto 0);
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wren_b : in std_logic;
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q_b : out std_logic_vector (width_a-1 downto 0)
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);
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end component;
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component cgrom
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PORT
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(
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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rdaddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
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rdclock : IN STD_LOGIC ;
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wraddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
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wrclock : IN STD_LOGIC := '1';
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wren : IN STD_LOGIC := '0';
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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);
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end component;
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component dpram2k
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PORT
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(
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address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
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address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
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clock_a : IN STD_LOGIC := '1';
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clock_b : IN STD_LOGIC ;
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data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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wren_a : IN STD_LOGIC := '0';
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wren_b : IN STD_LOGIC := '0';
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q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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);
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end component;
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begin
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--
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-- Instantiation
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--
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VRAM0 : dpram
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GENERIC MAP (
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init_file => "./roms/MZFONT.mif",
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widthad_a => 11,
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width_a => 8
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)
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PORT MAP (
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clock_a => CK8M,
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clocken_a => CK16M,
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address_a => VADR,
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data_a => T80_DI,
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wren_a => VWEN,
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q_a => VRAMDO,
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clock_b => CK16M,
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clocken_b => IOCTL_CSVVRAM_n,
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address_b => IOCTL_ADDR(10 DOWNTO 0),
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data_b => IOCTL_DOUT(7 DOWNTO 0),
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wren_b => RVWEN, --IOCTL_WR,
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q_b => open
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);
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CGROM0 : dprom
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GENERIC MAP (
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init_file => "./roms/MZ80K_cgrom.mif",
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widthad_a => 11,
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width_a => 8
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)
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PORT MAP (
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address_a => CGADR,
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clock_a => CK16M,
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data_a => IOCTL_DOUT(7 DOWNTO 0),
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wren_a => '0',
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q_a => CGDAT,
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address_b => IOCTL_ADDR(10 DOWNTO 0),
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clock_b => IOCTL_CSCGROM_n,
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data_b => IOCTL_DOUT(7 DOWNTO 0),
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wren_b => ROWEN,--IOCTL_WR
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q_b => open
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);
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--
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-- Blank & Sync Generation
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--
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process( RST_n, CK16M ) begin
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if RST_n='0' then
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HCOUNT <= "1111111000";
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HBLANKi <= '0';
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HDISPEN <= '0';
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BLNK <= '0';
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HSYNC_n <= '1';
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VDISPEN <= '1';
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VSYNC_n <= '1';
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GCSi_x <= '1';
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VADRC <= (others=>'0');
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GADRC <= (others=>'0');
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VADRL <= (others=>'0');
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elsif CK16M'event and CK16M='1' then
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-- Counters
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if HCOUNT=1015 then
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--HCOUNT<=(others=>'0');
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HCOUNT <= "1111111000";
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VADRC <= VADRL; -- Return to Most-Left-Column Address
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if VCOUNT=259 then
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VCOUNT <= (others=>'0');
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VADRC <= (others=>'0'); -- Home Position
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GADRC <= (others=>'0'); -- Home Position
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VADRL <= (others=>'0');
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else
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VCOUNT <= VCOUNT+'1';
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end if;
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else
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HCOUNT <= HCOUNT+'1';
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end if;
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-- Horizontal Signals Decode
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if HCOUNT=0 then
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HDISPEN <= VDISPEN; -- if V-DISP is Enable then H-DISP Start
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elsif HCOUNT=632 then
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HBLANKi <= '1'; -- H-Blank Start
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BLNK <= '1';
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elsif HCOUNT=640 then
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HDISPEN <= '0'; -- H-DISP End
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elsif HCOUNT=768 then
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HSYNC_n <= '0'; -- H-Sync Pulse Start
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elsif HCOUNT=774 and VCOUNT(2 downto 0)="111" then
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VADRL <= VADRC; -- Save Most-Left-Column Address
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elsif HCOUNT=859 then
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HSYNC_n <= '1'; -- H-Sync Pulse End
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elsif HCOUNT=992 then
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BLNK <= '0';
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elsif HCOUNT=1015 then
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HBLANKi <= '0'; -- H-Blank End
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end if;
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-- VRAM Address counter(per 8dot)
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if HBLANKi='0' then
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if (HCOUNT(2 downto 0)="111" and CH80i='1') or (HCOUNT(3 downto 0)="1111" and CH80i='0') then
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VADRC <= VADRC+'1';
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end if;
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if (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
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GADRC <= GADRC+'1';
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end if;
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end if;
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-- Graphics VRAM Access signal
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if HBLANKi='0' then
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if (HCOUNT(2 downto 0)="000" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1000" and MODE_MZ80B='1') then
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GCSi_x <= '0';
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elsif (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
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GCSi_x <= '1';
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end if;
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else
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GCSi_x <= '1';
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end if;
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-- Get Font/Pattern data and Shift
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if HCOUNT(3 downto 0)="0000" then
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if CH80i='1' then
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SDAT <= CGDAT;
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else
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SDAT <= CGDAT(7)&CGDAT(7)&CGDAT(6)&CGDAT(6)&CGDAT(5)&CGDAT(5)&CGDAT(4)&CGDAT(4);
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S2DAT <= CGDAT(3)&CGDAT(3)&CGDAT(2)&CGDAT(2)&CGDAT(1)&CGDAT(1)&CGDAT(0)&CGDAT(0);
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end if;
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if MODE_MZ2000='1' then
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SDATB <= GRAMBDI;
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SDATR <= GRAMRDI;
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SDATG <= GRAMGDI;
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else
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SDATB <= GRAMBDI(3)&GRAMBDI(3)&GRAMBDI(2)&GRAMBDI(2)&GRAMBDI(1)&GRAMBDI(1)&GRAMBDI(0)&GRAMBDI(0);
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S2DAT0 <= GRAMBDI(7)&GRAMBDI(7)&GRAMBDI(6)&GRAMBDI(6)&GRAMBDI(5)&GRAMBDI(5)&GRAMBDI(4)&GRAMBDI(4);
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SDATR <= GRAMRDI(3)&GRAMRDI(3)&GRAMRDI(2)&GRAMRDI(2)&GRAMRDI(1)&GRAMRDI(1)&GRAMRDI(0)&GRAMRDI(0);
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S2DAT1 <= GRAMRDI(7)&GRAMRDI(7)&GRAMRDI(6)&GRAMRDI(6)&GRAMRDI(5)&GRAMRDI(5)&GRAMRDI(4)&GRAMRDI(4);
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end if;
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elsif HCOUNT(3 downto 0)="1000" then
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if CH80i='1' then
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SDAT <= CGDAT;
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else
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SDAT <= S2DAT;
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end if;
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if MODE_MZ2000='1' then
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SDATB <= GRAMBDI;
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SDATR <= GRAMRDI;
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SDATG <= GRAMGDI;
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else
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SDATB <= S2DAT0;
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SDATR <= S2DAT1;
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end if;
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else
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SDAT <= SDAT(6 downto 0)&'0';
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SDATB <= '0'&SDATB(7 downto 1);
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SDATR <= '0'&SDATR(7 downto 1);
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SDATG <= '0'&SDATG(7 downto 1);
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end if;
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-- Vertical Signals Decode
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if VCOUNT=0 then
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VDISPEN <= '1'; -- V-DISP Start
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elsif VCOUNT=200 then
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VDISPEN <= '0'; -- V-DISP End
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elsif VCOUNT=219 then
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VSYNC_n <= '0'; -- V-Sync Pulse Start
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elsif VCOUNT=223 then
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VSYNC_n <= '1'; -- V-Sync Pulse End
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end if;
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end if;
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end process;
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--
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-- Control Registers
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--
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process( RST_n, T80_CLK ) begin
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if RST_n='0' then
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BCOLi <= (others=>'0');
|
|
CCOLi <= (others=>'1');
|
|
GPRI <= '0';
|
|
GPAGEi <= "000";
|
|
GDISPENi <= '0';
|
|
CDISPEN <= '1';
|
|
GBANK <= "00";
|
|
PALET0 <= "000";
|
|
PALET1 <= "111";
|
|
PALET2 <= "111";
|
|
PALET3 <= "111";
|
|
PALET4 <= "111";
|
|
PALET5 <= "111";
|
|
PALET6 <= "111";
|
|
PALET7 <= "111";
|
|
elsif T80_CLK'event and T80_CLK='0' then
|
|
if T80_WR_n='0' then
|
|
if MODE_MZ2000='1' then -- MZ-2000
|
|
-- Background Color
|
|
if CSF4_x='0' then
|
|
BCOLi <= T80_DI(2 downto 0);
|
|
end if;
|
|
-- Character Color and Priority
|
|
if CSF5_x='0' then
|
|
CCOLi <= T80_DI(2 downto 0);
|
|
GPRI <= T80_DI(3);
|
|
end if;
|
|
-- Display Graphics and Pages
|
|
if CSF6_x='0' then
|
|
GPAGEi <= T80_DI(2 downto 0);
|
|
GDISPENi <= not T80_DI(3);
|
|
end if;
|
|
-- Select Accessable Graphic Banks
|
|
if CSF7_x='0' then
|
|
GBANK <= T80_DI(1 downto 0);
|
|
end if;
|
|
else -- MZ-80B
|
|
-- Color Control(PIO-3039)
|
|
if CSB4_x='0' then
|
|
if T80_DI(6)='1' then
|
|
CDISPEN <= T80_DI(7);
|
|
else
|
|
case T80_DI(2 downto 0) is
|
|
when "000" => PALET0<=T80_DI(5 downto 3);
|
|
when "001" => PALET1<=T80_DI(5 downto 3);
|
|
when "010" => PALET2<=T80_DI(5 downto 3);
|
|
when "011" => PALET3<=T80_DI(5 downto 3);
|
|
when "100" => PALET4<=T80_DI(5 downto 3);
|
|
when "101" => PALET5<=T80_DI(5 downto 3);
|
|
when "110" => PALET6<=T80_DI(5 downto 3);
|
|
when "111" => PALET7<=T80_DI(5 downto 3);
|
|
when others => PALET0<=T80_DI(5 downto 3);
|
|
end case;
|
|
end if;
|
|
end if;
|
|
-- Select Accessable Graphic Banks and Outpu Pages
|
|
if CSF4_x='0' then
|
|
GBANK <= T80_DI(0)&(not T80_DI(0));
|
|
GPAGEi(1 downto 0)<=T80_DI(2 downto 1);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--
|
|
-- Timing Conditioning and Wait
|
|
--
|
|
process( T80_MREQ_n ) begin
|
|
if T80_MREQ_n'event and T80_MREQ_n='0' then
|
|
XBLNK<=BLNK;
|
|
end if;
|
|
end process;
|
|
|
|
process( T80_CLK ) begin
|
|
if T80_CLK'event and T80_CLK='1' then
|
|
WAITii_n<=WAITi_n;
|
|
end if;
|
|
end process;
|
|
WAITi_n<='0' when (CSV_n='0' or CSG_n='0') and XBLNK='0' and BLNK='0' else '1';
|
|
T80_WAIT_n<=WAITi_n and WAITii_n;
|
|
|
|
--
|
|
-- Mask by Mode
|
|
--
|
|
ZGBE_n <= "1110" when GBANK="01" else
|
|
"1101" when GBANK="10" else
|
|
"1011" when GBANK="11" else "1111";
|
|
GBE_n <= ZGBE_n when BLNK='1' else "1000";
|
|
GT80_WR_n <= T80_WR_n when BLNK='1' else '1';
|
|
GCS_n <= CSG_n when BLNK='1' else GCSi_x;
|
|
RCSV <= '0' when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11010" else '1';
|
|
RCSC <='0' when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11001" else '1';
|
|
VWEN <='1' when T80_WR_n='0' and CSV_n='0' and BLNK='1' else '0';
|
|
RVWEN <= not(IOCTL_WR='1' or RCSV);
|
|
RCWEN <= not(IOCTL_WR='1' or RCSC);
|
|
CSB4_x <= '0' when T80_A(7 downto 0)=X"B4" and T80_IORQ_n='0' else '1';
|
|
CSF4_x <= '0' when T80_A(7 downto 0)=X"F4" and T80_IORQ_n='0' else '1';
|
|
CSF5_x <= '0' when T80_A(7 downto 0)=X"F5" and T80_IORQ_n='0' else '1';
|
|
CSF6_x <= '0' when T80_A(7 downto 0)=X"F6" and T80_IORQ_n='0' else '1';
|
|
CSF7_x <= '0' when T80_A(7 downto 0)=X"F7" and T80_IORQ_n='0' else '1';
|
|
CCOL <= CCOLi when T80_BUSACK_n='1' else "111";
|
|
BCOL <= BCOLi when T80_BUSACK_n='1' else "000";
|
|
INVi <= INV when BOOTM='0' and T80_BUSACK_n='1' else '1';
|
|
VGATEi <= VGATE when BOOTM='0' and T80_BUSACK_n='1' else '0';
|
|
GPAGE <= GPAGEi when BOOTM='0' and T80_BUSACK_n='1' else "000";
|
|
GDISPEN <= '0' when BOOTM='1' or T80_BUSACK_n='0' else
|
|
'1' when MODE_MZ80B='1' else GDISPENi;
|
|
CH80i <= CH80 when BOOTM='0' and T80_BUSACK_n='1' else '0';
|
|
|
|
--
|
|
-- Bus Select
|
|
--
|
|
VADR <= T80_A(10 downto 0) when CSV_n='0' and BLNK='1' else VADRC;
|
|
GADRi <= T80_A(13 downto 0) when CSG_n='0' and BLNK='1' and MODE_MZ2000='1' else
|
|
'0'&T80_A(12 downto 0) when CSG_n='0' and BLNK='1' and MODE_MZ80B='1' else GADRC;
|
|
GADR <= "1111101"&GADRi; -- 0x7D0000
|
|
DCODE <= T80_DI when CSV_n='0' and BLNK='1' and T80_WR_n='0' else VRAMDO;
|
|
T80_DO <= VRAMDO when T80_RD_n='0' and CSV_n='0' else
|
|
GDI(7 downto 0) when T80_RD_n='0' and CSG_n='0' and GBANK="01" else
|
|
GDI(15 downto 8) when T80_RD_n='0' and CSG_n='0' and GBANK="10" else
|
|
GDI(23 downto 16) when T80_RD_n='0' and CSG_n='0' and GBANK="11" else (others=>'0');
|
|
CGADR <= DCODE&VCOUNT(2 downto 0);
|
|
GRAMBDI <= GDI(7 downto 0) when GPAGE(0)='1' else (others=>'0');
|
|
GRAMRDI <= GDI(15 downto 8) when GPAGE(1)='1' else (others=>'0');
|
|
GRAMGDI <= GDI(23 downto 16) when GPAGE(2)='1' else (others=>'0');
|
|
GDO <= "00000000"&T80_DI&T80_DI&T80_DI;
|
|
|
|
--
|
|
-- Color Decode
|
|
--
|
|
-- Monoclome Monitor
|
|
-- MB<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
|
|
-- MR<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
|
|
MB <= '0';
|
|
MR <= '0';
|
|
MG <= not (SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0)))) when HDISPEN='1' and VGATEi='0' and INVi='0' else
|
|
SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0))) when HDISPEN='1' and VGATEi='0' and INVi='1' else '0';
|
|
|
|
-- Color Monitor(MZ-2000)
|
|
process( HDISPEN, VGATEi, GPRI, SDAT(7), SDATB(0), SDATR(0), SDATG(0), CCOL, BCOL ) begin
|
|
if HDISPEN='1' and VGATEi='0' then
|
|
if SDAT(7)='0' and SDATB(0)='0' then
|
|
BB<=BCOL(0);
|
|
else
|
|
if GPRI='0' then
|
|
if SDAT(7)='1' then
|
|
BB<=CCOL(0);
|
|
else
|
|
BB<='1'; -- SDATB(0)='1'
|
|
end if;
|
|
else --GPRI='1'
|
|
if SDATB(0)='1' then
|
|
BB<='1';
|
|
else
|
|
BB<=CCOL(0); -- SDAT(7)='1'
|
|
end if;
|
|
end if;
|
|
end if;
|
|
if SDAT(7)='0' and SDATR(0)='0' then
|
|
BR<=BCOL(1);
|
|
else
|
|
if GPRI='0' then
|
|
if SDAT(7)='1' then
|
|
BR<=CCOL(1);
|
|
else
|
|
BR<='1'; -- SDATR(0)='1'
|
|
end if;
|
|
else --GPRI='1' then
|
|
if SDATR(0)='1' then
|
|
BR<='1';
|
|
else
|
|
BR<=CCOL(1); -- SDAT(7)='1'
|
|
end if;
|
|
end if;
|
|
end if;
|
|
if SDAT(7)='0' and SDATG(0)='0' then
|
|
BG<=BCOL(2);
|
|
else
|
|
if GPRI='0' then
|
|
if SDAT(7)='1' then
|
|
BG<=CCOL(2);
|
|
else
|
|
BG<='1'; -- SDATG(0)='1'
|
|
end if;
|
|
else --GPRI='1' then
|
|
if SDATG(0)='1' then
|
|
BG<='1';
|
|
else
|
|
BG<=CCOL(2); -- SDAT(7)='1'
|
|
end if;
|
|
end if;
|
|
end if;
|
|
else
|
|
BB<='0';
|
|
BR<='0';
|
|
BG<='0';
|
|
end if;
|
|
end process;
|
|
-- Color Monitor(PIO-3039)
|
|
POUT<=(SDAT(7) and CDISPEN)&SDATR(0)&SDATB(0);
|
|
process(POUT, PALET0, PALET1, PALET2, PALET3, PALET4, PALET5, PALET6, PALET7) begin
|
|
case POUT is
|
|
when "000" => PBGR<=PALET0;
|
|
when "001" => PBGR<=PALET1;
|
|
when "010" => PBGR<=PALET2;
|
|
when "011" => PBGR<=PALET3;
|
|
when "100" => PBGR<=PALET4;
|
|
when "101" => PBGR<=PALET5;
|
|
when "110" => PBGR<=PALET6;
|
|
when "111" => PBGR<=PALET7;
|
|
when others => PBGR<=PALET7;
|
|
end case;
|
|
end process;
|
|
|
|
--
|
|
-- Output
|
|
--
|
|
CK16M <= CK16M;
|
|
VBLANK <= VDISPEN;
|
|
HBLANK <= HBLANKi;
|
|
ROUT <= MR when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
|
|
BR when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(0);
|
|
GOUT <= MG when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
|
|
BG when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(1);
|
|
BOUT <= MB when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
|
|
BB when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(2);
|
|
|
|
end RTL;
|