170 lines
8.9 KiB
VHDL
170 lines
8.9 KiB
VHDL
---------------------------------------------------------------------------------------------------------
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--
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-- Name: mz80b.vhd
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-- Created: August 2018
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-- Author(s): Philip Smart
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-- Description: Sharp MZ series Business Computer:
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-- Models MZ-80B, MZ-2000
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--
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-- This module is the main (top level) container for the Business MZ Computer
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-- Emulation.
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--
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-- The design tries to work from top-down, where components which are common
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-- to the Business and Personal MZ series are at the top (ie. main memory,
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-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
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-- to the machine specific modules and components. Some components are common
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-- by their nature (ie. 8255 PIO) but these are instantiated within the lower
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-- tree branch as their design use is less generic.
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--
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-- The tree is as follows;-
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--
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-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
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-- |
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-- |
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-- | -> cmt.vhd (common)
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-- | -> keymatrix.vhd (common)
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-- | -> pll.v (common)
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-- | -> clkgen.vhd (common)
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-- | -> T80 (common)
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-- | -> i8255 (common)
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-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
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-- | -> i8253 (common)
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-- | -> dpram.vhd (common)
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-- | -> dprom.vhd (common)
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-- | -> mctrl.vhd (common)
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-- | -> video.vhd (common)
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-- |
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-- |
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-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development)
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--
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--
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-- Credits:
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-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
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--
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-- History: August 2018 - Initial module created.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library ieee;
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library pkgs;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use pkgs.clkgen_pkg.all;
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use pkgs.mctrl_pkg.all;
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entity mz80b is
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PORT (
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-- Clocks
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CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module.
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-- Resets.
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SYSTEM_RESET : in std_logic;
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-- Z80 CPU
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T80_RST_n : in std_logic;
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T80_CLK : in std_logic;
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T80_CLKEN : out std_logic;
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T80_WAIT_n : out std_logic;
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T80_INT_n : out std_logic;
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T80_NMI_n : out std_logic;
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T80_BUSRQ_n : out std_logic;
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T80_M1_n : in std_logic;
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T80_MREQ_n : in std_logic;
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T80_IORQ_n : in std_logic;
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T80_RD_n : in std_logic;
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T80_WR_n : in std_logic;
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T80_RFSH_n : in std_logic;
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T80_HALT_n : in std_logic;
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T80_BUSAK_n : in std_logic;
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T80_A16 : in std_logic_vector(15 downto 0);
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T80_DI : out std_logic_vector(7 downto 0);
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T80_DO : in std_logic_vector(7 downto 0);
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-- Chip selects to common resources.
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CS_ROM_n : out std_logic; -- ROM Select
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CS_RAM_n : out std_logic; -- RAM Select
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CS_VRAM_n : out std_logic; -- VRAM Select
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CS_MEM_G_n : out std_logic; -- Memory mapped Peripherals Select
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CS_GRAM_n : out std_logic; -- GRAM Select
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CS_GRAM_80B_n : out std_logic; -- GRAM Select
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CS_IO_G_n : out std_logic; -- Graphics FB IO Select range
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CS_SWP_MEMBANK_n : out std_logic;
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-- Audio.
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AUDIO_L : out std_logic;
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AUDIO_R : out std_logic;
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-- Different operations modes.
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CONFIG : in std_logic_vector(CONFIG_WIDTH);
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-- I/O -- I/O down to the core.
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KEYB_SCAN : out std_logic_vector(3 downto 0); -- Keyboard scan lines out.
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KEYB_DATA : in std_logic_vector(7 downto 0); -- Keyboard scan data in.
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KEYB_STALL : out std_logic; -- Keyboard Stall out.
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-- Cassette magnetic tape signals.
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CMT_BUS_OUT : in std_logic_vector(CMT_BUS_OUT_WIDTH);
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CMT_BUS_IN : out std_logic_vector(CMT_BUS_IN_WIDTH);
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-- Video signals
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VGATE_n : out std_logic; -- Video Gate enable.
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INVERSE : out std_logic; -- Invert video output.
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CHAR80 : out std_logic; --
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HBLANK : in std_logic; -- Horizontal Blanking Signal
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VBLANK : in std_logic; -- Vertical Blanking Signal
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-- HPS Interface
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IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
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IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
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IOCTL_CLK : in std_logic; -- HPS I/O Clock.
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IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
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IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
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IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
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IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
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IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
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-- Debug Status Leds
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DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status.
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);
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end mz80b;
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architecture rtl of mz80b is
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begin
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T80_CLKEN <= '1';
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T80_WAIT_n <= '1';
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T80_INT_n <= '1';
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T80_NMI_n <= '1';
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T80_BUSRQ_n <= '1';
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T80_DI <= (others => '0');
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CS_ROM_n <= '1';
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CS_RAM_n <= '1';
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CS_VRAM_n <= '1';
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CS_MEM_G_n <= '1';
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CS_GRAM_n <= '1';
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CS_GRAM_80B_n <= '1';
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CS_IO_G_n <= '1';
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CS_SWP_MEMBANK_n <= '1';
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AUDIO_L <= '1';
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AUDIO_R <= '1';
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VGATE_n <= '1';
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INVERSE <= '0';
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CHAR80 <= '0';
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CMT_BUS_IN(MOTORON)<= '0';
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CMT_BUS_IN(READBIT)<= '0';
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IOCTL_DIN <= (others => '0');
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DEBUG_STATUS_LEDS <= (others => '0');
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end rtl;
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