62 lines
2.1 KiB
VHDL
62 lines
2.1 KiB
VHDL
---------------------------------------------------------------------------------------------------------
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--
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-- Name: clk_div.vhd
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-- Created: July 2018
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-- Author(s): Philip Smart
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-- Description: A basic frequency divider module.
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-- This module takes an input frequency and divides it based on a provided divider.
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-- Credits:
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-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
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--
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-- History: July 2018 - Initial module written.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity clk_div is
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GENERIC (
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divider : natural
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);
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PORT (
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clk_in : in std_logic;
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reset : in std_logic;
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clk_out : out std_logic
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);
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end clk_div;
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architecture Behavioral of clk_div is
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signal temporal: std_logic;
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signal counter : integer range 0 to divider-1 := 0;
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begin
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process (reset, clk_in) begin
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if (reset = '1') then
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temporal <= '0';
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counter <= 0;
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elsif rising_edge(clk_in) then
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if (counter = divider-1) then
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temporal <= NOT(temporal);
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counter <= 0;
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else
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counter <= counter + 1;
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end if;
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end if;
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end process;
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clk_out <= temporal;
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end Behavioral;
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