jackyangantelope
084be9eff5
Update sys
2025-12-09 23:13:04 +08:00
Sorgelig
6627e7a75c
Release 20240502.
2024-05-02 16:47:11 +08:00
Sorgelig
04622d78d9
Update sys.
2024-05-02 16:47:10 +08:00
Sorgelig
a7d97edc43
Release 20231211.
2023-12-11 22:40:01 +08:00
Sorgelig
6c842905a1
Update sys.
2023-12-11 21:47:12 +08:00
Sorgelig
873b56bea5
Release 20220221.
2022-02-21 08:51:11 +08:00
Sorgelig
529f611074
vidc: delay pixel data.
2022-02-21 08:49:47 +08:00
Sorgelig
5bc3d70de4
fix: cmos change wasn't reported.
2022-02-21 08:32:02 +08:00
Sorgelig
1f2ecabcf7
Release 20220219.
2022-02-21 04:54:16 +08:00
Sorgelig
b2f0afa419
Update sys.
2022-02-21 04:53:38 +08:00
Alexey Melnikov
07e5a05c78
Merge pull request #17 from antireality/VIDC-Scroll-Fix
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Fix Scrolling in James Pond
2021-08-26 12:52:40 +08:00
Adam Hay
cc7f68d5ee
Fix scrolling in James Pond
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Use the border enable as a video enable signal to position the screen correctly. This fixes cases where the video display start/end are shifted into the border to scroll the screen.
2021-08-25 23:36:32 +02:00
Adam Hay
a62ec86102
Apply STM write fixes to other memory areas too
2021-08-25 23:35:12 +02:00
Adam Hay
610eec8d1b
Fix colour and screen Glitches in Twinworld ( #16 )
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cpu_load is only true for the first write of a STM instruction, so subsequent writes to the VIDC registers were being lost
2021-08-23 13:14:13 +08:00
sorgelig
d80a260918
Release 20210724.
2021-07-24 23:52:13 +08:00
sorgelig
27caaacdfa
Adjust FDC timings, some IOC tweaks/refactoring.
2021-07-24 16:29:34 +08:00
sorgelig
8b1b4c9c5f
Update FDC.
2021-07-22 07:16:21 +08:00
sorgelig
e1000fb687
Use standard IDE interface and module.
2021-07-22 04:23:04 +08:00
sorgelig
1315ed45e6
Update sys.
2021-07-21 23:37:01 +08:00
sorgelig
3a3c9e2517
Release 20210224.
2021-02-24 23:01:15 +08:00
sorgelig
2556c467a2
Update sys. HV-Integer.
2021-02-24 23:00:21 +08:00
sorgelig
30b2edfbfb
Update sys.
2021-01-19 02:24:11 +08:00
sorgelig
b596069c4a
Release 20201106.
2020-11-06 17:53:46 +08:00
sorgelig
86ed170a2c
Force enable VGA scaler.
2020-11-06 17:51:53 +08:00
sorgelig
2794f95698
Release 20201101.
2020-11-01 22:57:08 +08:00
sorgelig
c9b07c7327
Update sys. Support for custom AR.
2020-11-01 22:53:11 +08:00
sorgelig
b8827cd156
Release 20200821.
2020-08-21 21:36:34 +08:00
sorgelig
dcfebdc369
Update sys.
2020-08-21 21:35:05 +08:00
sorgelig
79936abbad
ide: some cleanup and simplifications.
2020-08-21 03:30:37 +08:00
sorgelig
021e770fb8
sdram: refactor to improve routability.
2020-08-21 01:42:31 +08:00
sorgelig
bc69807efd
Update ReadMe.
2020-08-20 18:59:00 +08:00
sorgelig
9ef12f81b6
Rework cmos/rtc. Clear RAM upon BIOS load.
2020-08-20 14:32:04 +08:00
sorgelig
7a7af7cc5f
Enable FDD activity LED.
2020-08-19 06:33:25 +08:00
sorgelig
2b8126d7d0
Sources re-organization.
2020-08-19 06:11:56 +08:00
sorgelig
69f0f56407
Add IDE, update FDC.
2020-08-19 05:39:54 +08:00
sorgelig
d42adec56a
Update sys.
2020-08-17 03:27:00 +08:00
Hackshed
11c5396bdd
Update ReadMe.md ( #6 )
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Added Wikipedia link to core name
2020-08-16 18:15:44 +08:00
RobertPeip
e272019a2e
add reset to cpu
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added more regs to reset for other modules
added simulation
some changes to be standard conform, mostly reordering of wire/reg defines
2020-08-08 22:53:38 +08:00
sorgelig
ef6c002371
Release 20200509.
2020-05-09 22:48:30 +08:00
sorgelig
d1d852dabe
Update sys. Re-organize the sources.
2020-05-09 22:46:59 +08:00
sorgelig
d71d821477
add missed file.
2020-04-19 00:18:23 +08:00
sorgelig
0f602a04fb
Extract core-specific I/O into hps_ext.
2020-04-19 00:12:27 +08:00
sorgelig
3a4c3217c0
Update sys.
2020-04-19 00:11:21 +08:00
sorgelig
6258b58076
Update SDRAM.
2019-12-21 02:24:13 +08:00
sorgelig
ec69ad10e1
Update sys.
2019-12-21 02:23:55 +08:00
sorgelig
0bfcdfc74c
Release 20191204.
2019-12-04 23:42:43 +08:00
sorgelig
077014ff66
Update SDRAM constraints.
2019-12-02 19:40:13 +08:00
sorgelig
c5dde685ef
Update SDRAM.
2019-12-01 00:09:30 +08:00
sorgelig
89df34df53
Rework SDRAM clocking.
2019-11-28 23:26:27 +08:00
sorgelig
80f56a2cbf
Update sys.
2019-11-28 20:28:35 +08:00