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ide: some cleanup and simplifications.

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sorgelig
2020-08-21 03:30:37 +08:00
parent 021e770fb8
commit 79936abbad
5 changed files with 129 additions and 197 deletions
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2
Archie.qsf
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@@ -30,7 +30,7 @@ set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

47
Archie.sv
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@@ -248,20 +248,15 @@ hps_ext hps_ext
.cmos_cnt ( cmos_cnt ),
.reset ( reset ),
.ide_reset ( reset ),
.ide_req ( ide_req ),
.ide_ack ( ide_ack ),
.ide_err ( ide_err ),
.ide_reg_o_adr ( ide_reg_i_adr ),
.ide_reg_o ( ide_reg_i ),
.ide_reg_we ( ide_reg_we ),
.ide_reg_i_adr ( ide_reg_o_adr ),
.ide_reg_i ( ide_reg_o ),
.ide_data_addr ( ide_data_addr ),
.ide_data_o ( ide_data_i ),
.ide_data_i ( ide_data_o ),
.ide_data_rd ( ide_data_rd ),
.ide_data_we ( ide_data_we )
.ide_adr ( ide_adr ),
.ide_dat_o ( ide_dat_i ),
.ide_dat_i ( ide_dat_o ),
.ide_rd ( ide_rd ),
.ide_we ( ide_we )
);
assign AUDIO_S = 1;
@@ -288,16 +283,11 @@ wire i2c_din, i2c_dout, i2c_clock;
wire ide_req;
wire ide_ack;
wire ide_err;
wire [2:0] ide_reg_o_adr;
wire [7:0] ide_reg_o;
wire ide_reg_we;
wire [2:0] ide_reg_i_adr;
wire [7:0] ide_reg_i;
wire [7:0] ide_data_addr;
wire [15:0] ide_data_o;
wire [15:0] ide_data_i;
wire ide_data_rd;
wire ide_data_we;
wire [8:0] ide_adr;
wire [15:0] ide_dat_o;
wire [15:0] ide_dat_i;
wire ide_rd;
wire ide_we;
wire fdd_led;
@@ -354,16 +344,11 @@ archimedes_top #(CLKSYS) ARCHIMEDES
.ide_req ( ide_req ),
.ide_ack ( ide_ack ),
.ide_err ( ide_err ),
.ide_reg_o_adr ( ide_reg_o_adr ),
.ide_reg_o ( ide_reg_o ),
.ide_reg_we ( ide_reg_we ),
.ide_reg_i_adr ( ide_reg_i_adr ),
.ide_reg_i ( ide_reg_i ),
.ide_data_addr ( ide_data_addr ),
.ide_data_o ( ide_data_o ),
.ide_data_i ( ide_data_i ),
.ide_data_rd ( ide_data_rd ),
.ide_data_we ( ide_data_we ),
.ide_adr ( ide_adr ),
.ide_dat_o ( ide_dat_o ),
.ide_dat_i ( ide_dat_i ),
.ide_rd ( ide_rd ),
.ide_we ( ide_we ),
.KBD_OUT_DATA ( kbd_out_data ),
.KBD_OUT_STROBE ( kbd_out_strobe ),

44
rtl/archimedes_top.v
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@@ -87,16 +87,11 @@ module archimedes_top #(parameter CLKCPU)
output ide_req, // new command request
input ide_err,
input ide_ack, // command finished on the IO controller side
input [2:0] ide_reg_o_adr,// requested task file register index
output [7:0] ide_reg_o, // task file register out
input ide_reg_we, // task file register write strobe from IO controller
input [2:0] ide_reg_i_adr,
input [7:0] ide_reg_i, // task file register input
input [7:0] ide_data_addr,
output [15:0] ide_data_o,
input [15:0] ide_data_i,
input ide_data_rd,
input ide_data_we,
input [8:0] ide_adr,
output [15:0] ide_dat_o,
input [15:0] ide_dat_i,
input ide_rd,
input ide_we,
// connection to keyboard controller
output [7:0] KBD_OUT_DATA,
@@ -386,31 +381,24 @@ fdc1772 #(CLKCPU) FDC1772 (
ide IDE (
.clk ( CLKCPU_I ),
.reset ( RESET_I ),
.ide_sel ( podule0_sel ),
.ide_we ( cpu_we ),
.ide_adr ( podule_adr ),
.ide_dat_o ( podule0_rdata ),
.ide_dat_i ( podule_wdata ),
.cpu_sel ( podule0_sel ),
.cpu_we ( cpu_we ),
.cpu_adr ( podule_adr ),
.cpu_dat_o ( podule0_rdata ),
.cpu_dat_i ( podule_wdata ),
.ide_req ( ide_req ),
.ide_ack ( ide_ack ),
.ide_err ( ide_err ),
.ide_reg_o_adr ( ide_reg_o_adr ),
.ide_reg_o ( ide_reg_o ),
.ide_reg_we ( ide_reg_we ),
.ide_reg_i_adr ( ide_reg_i_adr ),
.ide_reg_i ( ide_reg_i ),
.ide_data_addr ( ide_data_addr ),
.ide_data_o ( ide_data_o ),
.ide_data_i ( ide_data_i ),
.ide_data_rd ( ide_data_rd ),
.ide_data_we ( ide_data_we )
.ide_adr ( ide_adr ),
.ide_dat_o ( ide_dat_o ),
.ide_dat_i ( ide_dat_i ),
.ide_we ( ide_we ),
.ide_rd ( ide_rd )
);
wire [7:0] latches_dat_o;
@@ -432,7 +420,7 @@ latches LATCHES(
.floppy_motor ( floppy_motor ),
.floppy_inuse ( floppy_inuse ),
.floppy_side ( floppy_side ),
.floppy_density ( floppy_density ),
.floppy_density( floppy_density ),
.floppy_reset ( floppy_reset ),
.joy0 ( JOYSTICK0 ),

142
rtl/hps_ext.v
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@@ -30,20 +30,15 @@ module hps_ext
input [7:0] cmos_cnt,
input reset,
input ide_reset,
input ide_req,
output reg ide_ack,
output reg ide_err,
output reg [2:0] ide_reg_i_adr,
input [7:0] ide_reg_i,
output reg ide_reg_we,
output reg [2:0] ide_reg_o_adr,
output reg [7:0] ide_reg_o,
output reg [7:0] ide_data_addr,
output reg [15:0] ide_data_o,
input [15:0] ide_data_i,
output reg ide_data_rd,
output reg ide_data_we
output reg [8:0] ide_adr,
output reg [15:0] ide_dat_o,
input [15:0] ide_dat_i,
output reg ide_rd,
output reg ide_we
);
assign EXT_BUS[15:0] = fp_dout_en ? fp_dout : io_dout;
@@ -84,20 +79,18 @@ always@(posedge clk_sys) begin
end
else begin
case(cmd)
'h04: begin
if(byte_cnt == 1) begin
'h04: if(byte_cnt == 1) begin
io_dout[7:0] <= { 4'ha, 3'b000, kbd_out_data_available };
kbd_out_data_available <= 0;
end
else begin
io_dout[7:0] <= kbd_out_data;
end
end
'h05: begin
if(byte_cnt == 1) kbd_in_strobe <= 1;
kbd_in_data <= io_din[7:0];
end
if(byte_cnt == 1) kbd_in_strobe <= 1;
kbd_in_data <= io_din[7:0];
end
default: ;
endcase
end
@@ -105,33 +98,33 @@ always@(posedge clk_sys) begin
end
end
localparam CMD_IDE_REGS_RD = 8'h80;
localparam CMD_IDE_REGS_WR = 8'h90;
localparam CMD_IDE_DATA_WR = 8'hA0;
localparam CMD_IDE_DATA_RD = 8'hB0;
localparam CMD_IDE_STATUS_WR = 8'hF0;
localparam CMD_IDE_REGS_RD = 8'h80;
localparam CMD_IDE_REGS_WR = 8'h90;
localparam CMD_IDE_DATA_WR = 8'hA0;
localparam CMD_IDE_DATA_RD = 8'hB0;
localparam CMD_IDE_STATUS_WR = 8'hF0;
localparam CMD_IDECMD = 8'h04;
localparam CMD_IDEDAT = 8'h08;
localparam STATUS_CMD = 8'h04;
localparam STATUS_DAT = 8'h08;
reg [15:0] fp_dout;
reg fp_dout_en;
always@(posedge clk_sys) begin
reg [7:0] cmd;
reg [3:0] byte_cnt;
reg [1:0] byte_cnt;
reg write_start = 0;
reg newcmd = 0;
reg write_req = 0;
reg [7:0] ide_cmd;
ide_reg_we <= 0;
ide_data_we <= 0;
ide_data_rd <= 0;
ide_ack <= 0;
if(ide_data_we | ide_data_rd) ide_data_addr <= ide_data_addr + 1'd1;
ide_we <= 0;
ide_rd <= 0;
ide_ack <= 0;
if (reset) begin
if(ide_we | ide_rd) ide_adr <= ide_adr + 1'd1;
if(ide_rd && ide_adr == 9'h107) ide_cmd <= ide_dat_i[7:0];
if (ide_reset) begin
newcmd <= 0;
write_req <= 0;
write_start <= 0;
@@ -143,71 +136,44 @@ always@(posedge clk_sys) begin
write_start <= write_req;
end
if (ide_data_we) newcmd <= 0;
if (ide_data_rd) begin
write_req <= 0;
write_start <= 0;
if(~ide_adr[8]) begin
if (ide_we) newcmd <= 0;
if (ide_rd) begin
write_req <= 0;
write_start <= 0;
end
end
if(~fp_enable) begin
byte_cnt <= 0;
fp_dout <= 0;
fp_dout_en <= 0;
end
else begin
if(io_strobe) begin
else if(io_strobe) begin
fp_dout <= 0;
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
fp_dout <= 0;
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
if(byte_cnt == 0) begin
cmd <= io_din[15:8];
fp_dout_en <= (io_din[15:8] >= CMD_IDE_REGS_RD && io_din[15:8] <= CMD_IDE_STATUS_WR);
if(!io_din) begin
fp_dout <= {write_start ? CMD_IDEDAT : newcmd ? CMD_IDECMD : 8'h00, cmos_cnt};
fp_dout_en <= 1;
end
if(io_din[15:8] == CMD_IDE_STATUS_WR) begin
if (io_din[7]) ide_ack <= 1; // IDE_STATUS_END
if (io_din[4]) newcmd <= 0; // IDE_STATUS_IRQ
if (io_din[2] || ((ide_cmd == 8'h30 || ide_cmd == 8'hc5) && io_din[4] && ~io_din[7])) write_req <= 1;
if (io_din[1]) ide_err <= 1; // IDE_STATUS_ERR
end
ide_data_addr <= 0;
ide_reg_i_adr <= 0;
ide_reg_o_adr <= 0;
if(!byte_cnt) begin
cmd <= io_din[15:8];
fp_dout_en <= (io_din[15:8] >= CMD_IDE_REGS_RD && io_din[15:8] <= CMD_IDE_STATUS_WR);
if(!io_din) begin
fp_dout <= {write_start ? STATUS_DAT : newcmd ? STATUS_CMD : 8'h00, cmos_cnt};
fp_dout_en <= 1;
end
else begin
case(cmd)
CMD_IDE_REGS_WR:
if (byte_cnt >= 4 && byte_cnt <= 9) begin
ide_reg_o <= io_din[7:0];
ide_reg_o_adr <= ide_reg_o_adr + 1'd1;
ide_reg_we <= 1;
end
CMD_IDE_REGS_RD:
if(byte_cnt >= 3) begin
fp_dout <= ide_reg_i;
if (ide_reg_i_adr == 7) ide_cmd <= ide_reg_i;
ide_reg_i_adr <= ide_reg_i_adr + 1'd1;
end
CMD_IDE_DATA_WR:
if (byte_cnt >= 3) begin
ide_data_o <= io_din;
ide_data_we <= 1;
end
CMD_IDE_DATA_RD:
if (byte_cnt >= 3) begin
fp_dout <= ide_data_i;
ide_data_rd <= 1;
end
default: ;
endcase
if(io_din[15:8] == CMD_IDE_STATUS_WR) begin
if (io_din[7]) ide_ack <= 1; // IDE_STATUS_END
if (io_din[4]) newcmd <= 0; // IDE_STATUS_IRQ
if (io_din[2] || ((ide_cmd == 8'h30 || ide_cmd == 8'hc5) && io_din[4] && ~io_din[7])) write_req <= 1;
if (io_din[1]) ide_err <= 1; // IDE_STATUS_ERR
end
ide_adr <= {io_din[15:8] == CMD_IDE_REGS_RD || io_din[15:8] == CMD_IDE_REGS_WR, 8'h00};
end
if (&byte_cnt) begin
ide_dat_o <= io_din;
fp_dout <= ide_dat_i;
ide_we <= (cmd == CMD_IDE_REGS_WR) || (cmd == CMD_IDE_DATA_WR);
ide_rd <= (cmd == CMD_IDE_REGS_RD) || (cmd == CMD_IDE_DATA_RD);
end
end
end

91
rtl/ide.sv
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@@ -19,31 +19,24 @@
// altera message_off 10030
module ide (
input clk, // system clock.
input reset,
input clk, // system clock.
input reset,
input ide_sel,
input ide_we,
input [13:2] ide_adr,
input [15:0] ide_dat_i,
output reg [15:0] ide_dat_o,
input cpu_sel,
input cpu_we,
input [13:2] cpu_adr,
input [15:0] cpu_dat_i,
output [15:0] cpu_dat_o,
// place any signals that need to be passed up to the top after here.
output reg ide_req,
input ide_err,
input ide_ack,
input [2:0] ide_reg_o_adr,
output reg [7:0] ide_reg_o,
input ide_reg_we,
input [2:0] ide_reg_i_adr,
input [7:0] ide_reg_i,
input [7:0] ide_data_addr,
output [15:0] ide_data_o,
input [15:0] ide_data_i,
input ide_data_rd,
input ide_data_we
output ide_req,
input ide_err,
input ide_ack,
input [8:0] ide_adr,
output [15:0] ide_dat_o,
input [15:0] ide_dat_i,
input ide_we,
input ide_rd
);
assign ide_req = ide_cmd_req | ide_sector_req;
@@ -52,47 +45,46 @@ assign ide_req = ide_cmd_req | ide_sector_req;
reg [7:0] rd_rom[16384];
initial $readmemh("rtl/riscdevide_rom.hex", rd_rom);
wire reg_sel = ide_sel && ide_adr[13:10] == 4'hA;
wire page_sel = ide_sel && ide_adr[13:02] == 12'h800 && ide_we ;
wire reg_sel = cpu_sel && cpu_adr[13:10] == 4'hA;
wire page_sel = cpu_sel && cpu_adr[13:02] == 12'h800 && cpu_we ;
reg [2:0] rd_page;
always @(posedge clk) begin
if (reset) rd_page <= 0;
else if (page_sel) rd_page <= ide_dat_i[2:0];
else if (page_sel) rd_page <= cpu_dat_i[2:0];
end
reg [7:0] rd_rom_q;
always @(posedge clk) rd_rom_q <= rd_rom[{rd_page, ide_adr[12:2]}];
always @(posedge clk) rd_rom_q <= rd_rom[{rd_page, cpu_adr[12:2]}];
wire [2:0] ide_reg = ide_adr[4:2];
wire [2:0] ide_reg = cpu_adr[4:2];
reg [7:0] taskfile[8];
reg [7:0] status;
// read from Task File Registers
always @(*) begin
reg [7:0] ide_dat_b;
//cpu read
ide_dat_b = (ide_reg == 3'd7) ? { status[7:1], ide_err } : taskfile[ide_reg];
ide_dat_o = ~reg_sel ? {8'd0, rd_rom_q} : ((ide_reg == 3'd0) ? data_out : { ide_dat_b, ide_dat_b });
wire ide_reg_sel = ide_adr[8];
// IO controller read
ide_reg_o = taskfile[ide_reg_o_adr];
end
// read from Task File Registers
//cpu read
wire [7:0] ide_dat_b = (ide_reg == 3'd7) ? { status[7:1], ide_err } : taskfile[ide_reg];
assign cpu_dat_o = ~reg_sel ? {8'd0, rd_rom_q} : ((ide_reg == 3'd0) ? data_out : { ide_dat_b, ide_dat_b });
// IO controller read
assign ide_dat_o = ide_reg_sel ? taskfile[ide_adr[2:0]] : ide_sec_o;
reg ide_cmd_req;
// write to Task File Registers
always @(posedge clk) begin
ide_cmd_req <= 0;
// cpu write
if (reg_sel && ide_we) begin
taskfile[ide_reg] <= ide_dat_i[7:0];
if (reg_sel && cpu_we) begin
taskfile[ide_reg] <= cpu_dat_i[7:0];
// writing to the command register triggers the IO controller
if (ide_reg == 3'd7) ide_cmd_req <= 1;
end
// IO controller write
if (ide_reg_we) taskfile[ide_reg_i_adr] <= ide_reg_i;
if (ide_we & ide_reg_sel) taskfile[ide_adr[2:0]] <= ide_dat_i[7:0];
end
reg ide_sector_req;
@@ -107,7 +99,7 @@ always @(posedge clk) begin
sector_count <= 8'd1;
end else begin
// write to command register starts the execution
if (reg_sel && ide_we && ide_reg == 3'd7) begin
if (reg_sel && cpu_we && ide_reg == 3'd7) begin
sector_count <= taskfile[2];
case (taskfile[7])
8'h30, 8'hc5: status <= 8'h08; // request data
@@ -124,8 +116,8 @@ always @(posedge clk) begin
end
// sector buffer - IO controller side
if ((ide_data_rd | ide_data_we) & ide_data_addr == 8'hff) status <= 8'h08; // sector buffer consumed/filled, ready to transfer
if (ide_data_rd | ide_data_we) ide_sector_req <= 0;
if ((ide_rd | ide_we) && ide_adr == 9'hff) status <= 8'h08; // sector buffer consumed/filled, ready to transfer
if ((ide_rd | ide_we) && ~ide_reg_sel) ide_sector_req <= 0;
// sector buffer - CPU side
if (reg_sel_d && ~reg_sel && ide_reg == 3'd0 && data_addr == 8'hff) begin
@@ -155,22 +147,23 @@ reg reg_sel_d;
// read/write data register
always @(posedge clk) begin
reg_sel_d <= reg_sel;
if (reg_sel && ide_we && ide_reg == 3'd7) data_addr <= 0;
if (reg_sel && cpu_we && ide_reg == 3'd7) data_addr <= 0;
if (reg_sel_d && ~reg_sel && ide_reg == 3'd0) data_addr <= data_addr + 1'd1;
end
wire [15:0] ide_sec_o;
dpram #(8,16) ide_databuf (
.clock ( clk ),
.address_a ( data_addr ),
.data_a ( ide_dat_i ),
.wren_a ( reg_sel && ide_we && ide_reg == 3'd0 ),
.data_a ( cpu_dat_i ),
.wren_a ( reg_sel && cpu_we && ide_reg == 3'd0 ),
.q_a ( data_out ),
.address_b ( ide_data_addr ),
.data_b ( ide_data_i ),
.wren_b ( ide_data_we ),
.q_b ( ide_data_o )
.address_b ( ide_adr[7:0] ),
.data_b ( ide_dat_i ),
.wren_b ( ide_we & ~ide_reg_sel ),
.q_b ( ide_sec_o )
);
endmodule