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https://github.com/MiSTer-devel/Archie_MiSTer.git
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599 lines
14 KiB
Systemverilog
599 lines
14 KiB
Systemverilog
//============================================================================
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// Acorn Archimedes
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//
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// Port to MiSTer.
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// Copyright (C) 2017-2019 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign LED_USER = fdd_led;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
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assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3;
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`include "build_id.v"
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localparam CONF_STR = {
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"ARCHIE;;",
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"J,Fire;",
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"V,v",`BUILD_DATE
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};
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//////////////////// CLOCKS ///////////////////
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wire pll_ready;
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wire clk_mem;
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wire clk_sys;
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pll pll
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(
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.refclk(CLK_50M),
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.outclk_0(clk_mem),
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.outclk_1(clk_sys),
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.locked(pll_ready)
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);
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reg initReset_n = 0;
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always @(posedge clk_sys) if(riscos_dl) initReset_n <= 1;
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wire reset = status[0] | buttons[1] | RESET | ~initReset_n | riscos_dl;
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////////////////// HPS I/O ///////////////////
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wire [15:0] joyA;
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wire [15:0] joyB;
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wire [1:0] buttons;
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wire [31:0] status;
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wire [7:0] kbd_out_data;
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wire kbd_out_strobe;
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wire [7:0] kbd_in_data;
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wire kbd_in_strobe;
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wire ioctl_download;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [15:0] ioctl_dout;
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wire [15:0] ioctl_din;
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reg ioctl_wait = 0;
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wire [31:0] sd_lba;
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wire [1:0] sd_rd;
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wire [1:0] sd_wr;
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wire sd_ack;
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wire [7:0] sd_buff_addr;
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wire [15:0] sd_buff_dout;
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wire [15:0] sd_buff_din;
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wire sd_buff_wr;
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wire [1:0] img_mounted;
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wire [31:0] img_size;
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wire img_readonly;
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wire [21:0] gamma_bus;
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hps_io #(.STRLEN($size(CONF_STR)>>3), .WIDE(1), .VDNUM(2)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.joystick_0(joyA),
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.joystick_1(joyB),
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.buttons(buttons),
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.status(status),
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.new_vmode(new_vmode),
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.gamma_bus(gamma_bus),
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.ioctl_index(ioctl_index),
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.ioctl_download(ioctl_download),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_wr(ioctl_wr),
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.ioctl_wait(ioctl_wait|loader_stb),
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.ioctl_din(ioctl_din),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
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.sd_buff_wr(sd_buff_wr),
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.img_mounted(img_mounted),
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.img_size(img_size),
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.img_readonly(img_readonly),
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.EXT_BUS(EXT_BUS)
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);
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wire [35:0] EXT_BUS;
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hps_ext hps_ext
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(
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.clk_sys ( clk_sys ),
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.EXT_BUS ( EXT_BUS ),
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.kbd_out_data ( kbd_out_data ),
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.kbd_out_strobe ( kbd_out_strobe ),
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.kbd_in_data ( kbd_in_data ),
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.kbd_in_strobe ( kbd_in_strobe ),
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.cmos_cnt ( cmos_cnt ),
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.ide_reset ( reset ),
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.ide_req ( ide_req ),
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.ide_ack ( ide_ack ),
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.ide_err ( ide_err ),
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.ide_adr ( ide_adr ),
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.ide_dat_o ( ide_dat_i ),
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.ide_dat_i ( ide_dat_o ),
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.ide_rd ( ide_rd ),
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.ide_we ( ide_we )
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);
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assign AUDIO_S = 1;
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assign AUDIO_MIX = status[3:2];
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wire [3:0] core_r, core_g, core_b;
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wire core_hs, core_vs, core_de;
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wire core_ack_in;
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wire core_stb_out;
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wire core_cyc_out;
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wire core_we_o;
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wire [3:0] core_sel_o;
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wire [2:0] core_cti_o;
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wire [31:0] core_data_in, core_data_out;
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wire [31:0] ram_data_in;
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wire [23:2] core_address_out;
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wire [1:0] pixbaseclk_select;
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wire [1:0] selpix;
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wire i2c_din, i2c_dout, i2c_clock;
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wire ide_req;
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wire ide_ack;
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wire ide_err;
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wire [8:0] ide_adr;
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wire [15:0] ide_dat_o;
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wire [15:0] ide_dat_i;
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wire ide_rd;
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wire ide_we;
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wire fdd_led;
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archimedes_top #(CLKSYS) ARCHIMEDES
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(
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.CLKCPU_I ( clk_sys ),
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.CLKPIX_I ( CLK_VIDEO ),
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.CEPIX_I ( CE_PIXEL ),
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.SELPIX_O ( selpix ),
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.CEAUD_I ( ceaud ),
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.RESET_I (~ram_ready | reset),
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.MEM_ACK_I ( core_ack_in ),
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.MEM_DAT_I ( core_data_in ),
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.MEM_DAT_O ( core_data_out ),
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.MEM_ADDR_O ( core_address_out),
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.MEM_STB_O ( core_stb_out ),
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.MEM_CYC_O ( core_cyc_out ),
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.MEM_SEL_O ( core_sel_o ),
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.MEM_WE_O ( core_we_o ),
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.MEM_CTI_O ( core_cti_o ),
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.HSYNC ( core_hs ),
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.VSYNC ( core_vs ),
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.VIDEO_R ( core_r ),
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.VIDEO_G ( core_g ),
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.VIDEO_B ( core_b ),
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.VIDEO_EN ( core_de ),
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.AUDIO_L ( AUDIO_L ),
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.AUDIO_R ( AUDIO_R ),
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.I2C_DOUT ( i2c_din ),
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.I2C_DIN ( i2c_dout ),
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.I2C_CLOCK ( i2c_clock ),
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.FDD_LED ( fdd_led ),
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.sd_lba ( sd_lba ),
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.sd_rd ( sd_rd ),
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.sd_wr ( sd_wr ),
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.sd_ack ( sd_ack ),
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.sd_buff_addr ( sd_buff_addr ),
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.sd_buff_dout ( sd_buff_dout ),
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.sd_buff_din ( sd_buff_din ),
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.sd_buff_wr ( sd_buff_wr ),
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.img_mounted ( img_mounted ),
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.img_size ( img_size ),
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.img_wp ( img_readonly ),
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.ide_req ( ide_req ),
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.ide_ack ( ide_ack ),
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.ide_err ( ide_err ),
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.ide_adr ( ide_adr ),
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.ide_dat_o ( ide_dat_o ),
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.ide_dat_i ( ide_dat_i ),
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.ide_rd ( ide_rd ),
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.ide_we ( ide_we ),
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.KBD_OUT_DATA ( kbd_out_data ),
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.KBD_OUT_STROBE ( kbd_out_strobe ),
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.KBD_IN_DATA ( kbd_in_data ),
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.KBD_IN_STROBE ( kbd_in_strobe ),
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.JOYSTICK0 (~{joyA[4],joyA[0],joyA[1],joyA[2],joyA[3]}),
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.JOYSTICK1 (~{joyB[4],joyB[0],joyB[1],joyB[2],joyB[3]}),
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.VIDBASECLK_O ( pixbaseclk_select ),
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.VIDSYNCPOL_O ( )
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);
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wire [31:0] vratio[16] =
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'{
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8000000, 12000000, 16000000, 24000000,
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8391666, 12587500, 16783333, 25175000,
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1200000, 18000000, 24000000, 36000000,
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8000000, 12000000, 16000000, 24000000
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};
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wire [3:0] vmode = {pixbaseclk_select,selpix};
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localparam CLKSYS = 42000000;
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reg cepix;
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reg [31:0] vclk, vsum;
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wire [31:0] vsum_next = vsum + vclk;
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always @(posedge CLK_VIDEO) begin
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cepix <= 0;
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vsum <= vsum_next;
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if(vsum_next >= CLKSYS) begin
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vsum <= vsum_next - CLKSYS;
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cepix <= 1;
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end
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end
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always @(posedge CLK_VIDEO) begin
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reg [31:0] pixcnt = 0, pix60;
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reg old_sync = 0;
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reg [31:0] vclk1;
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reg allow60 = 0;
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if(vmode == 7) allow60 <= 1;
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if(reset) allow60 <= 0;
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if(reset || status[4] || !allow60) vclk1 <= vratio[vmode];
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else if(CE_PIXEL) begin
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old_sync <= VGA_VS;
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pixcnt <= pixcnt + 1;
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if(~old_sync & VGA_VS) begin
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pix60 <= {pixcnt[26:0],5'd0}+{pixcnt[27:0],4'd0}+{pixcnt[28:0],3'd0}+{pixcnt[29:0],2'd0};
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pixcnt <= 0;
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end
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if(pix60<5000000) vclk1 <= 5000000;
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else if(pix60>CLKSYS) vclk1 <= CLKSYS;
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else vclk1 <= pix60;
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end
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vclk <= vclk1;
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end
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assign CLK_VIDEO = clk_sys;
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assign CE_PIXEL = cepix;
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assign VGA_F1 = 0;
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assign VGA_SL = 0;
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gamma_fast gamma
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(
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.clk_vid(CLK_VIDEO),
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.ce_pix(CE_PIXEL),
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.gamma_bus(gamma_bus),
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.HSync(~core_hs),
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.VSync(~core_vs),
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.DE(core_de),
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.RGB_in({core_r,core_r,core_g,core_g,core_b,core_b}),
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.HSync_out(VGA_HS),
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.VSync_out(VGA_VS),
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.DE_out(VGA_DE),
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.RGB_out({VGA_R,VGA_G,VGA_B})
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);
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reg new_vmode;
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always @(posedge CLK_VIDEO) begin
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reg [4:0] old_mode;
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old_mode <= {status[4], vmode};
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if(old_mode != {status[4], vmode}) new_vmode <= ~new_vmode;
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end
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wire [31:0] aratio[4] =
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'{
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1000000, 1048958, 1500000, 1000000
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};
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reg ceaud;
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reg [31:0] asum, aclk;
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wire [31:0] asum_next = asum + aclk;
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always @(posedge CLK_VIDEO) begin
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reg [31:0] aclk1;
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aclk1 <= (status[5] && pixbaseclk_select == 1) ? 1000000 : aratio[pixbaseclk_select];
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aclk <= aclk1;
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ceaud <= 0;
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asum <= asum_next;
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if(asum_next >= CLKSYS) begin
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asum <= asum_next - CLKSYS;
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ceaud <= 1;
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end
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end
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wire ram_ack;
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wire ram_stb;
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wire ram_cyc;
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wire ram_we;
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wire [3:0] ram_sel;
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wire [25:2] ram_address;
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wire ram_ready;
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sdram SDRAM
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(
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// wishbone interface
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.wb_clk (clk_sys ),
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.wb_stb (ram_stb ),
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.wb_cyc (ram_cyc ),
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.wb_we (ram_we ),
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.wb_ack (ram_ack ),
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.wb_sel (ram_sel ),
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.wb_adr (ram_address ),
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.wb_dat_i (ram_data_in ),
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.wb_dat_o (core_data_in),
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.wb_cti (core_cti_o ),
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// SDRAM Interface
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.sd_clk (clk_mem ),
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.sd_rst (~pll_ready ),
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.sd_clk_out (SDRAM_CLK ),
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.sd_cke (SDRAM_CKE ),
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.sd_dq (SDRAM_DQ ),
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.sd_addr (SDRAM_A ),
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.sd_dqm ({SDRAM_DQMH,SDRAM_DQML}),
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.sd_cs_n (SDRAM_nCS ),
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.sd_ba (SDRAM_BA ),
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.sd_we_n (SDRAM_nWE ),
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.sd_ras_n (SDRAM_nRAS ),
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.sd_cas_n (SDRAM_nCAS ),
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.sd_ready (ram_ready )
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|
);
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|
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wire riscos_dl = (ioctl_index == 1) && ioctl_download;
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wire cmos_dl = (ioctl_index == 3) && ioctl_download;
|
|
|
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reg [21:2] erase_addr;
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reg loader_stb = 0;
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|
always @(posedge clk_sys) begin
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|
reg old_dl = 0;
|
|
|
|
if(ram_ack) loader_stb <= 0;
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if(riscos_dl & ioctl_wr) loader_stb <= 1;
|
|
|
|
old_dl <= riscos_dl;
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|
if(~old_dl & riscos_dl) begin
|
|
ioctl_wait <= 1;
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|
erase_addr <= 0;
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|
end
|
|
|
|
if(ioctl_wait) begin
|
|
if(ram_ack) begin
|
|
if(~&erase_addr) erase_addr <= erase_addr + 1'd1;
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|
else ioctl_wait <= 0;
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|
end
|
|
if(~loader_stb) loader_stb <= 1;
|
|
end
|
|
end
|
|
|
|
assign ram_we = riscos_dl ? 1'b1 : core_we_o;
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|
assign ram_sel = riscos_dl ? (ioctl_wait ? 4'b1111 : ioctl_addr[1] ? 4'b1100 : 4'b0011) : core_sel_o;
|
|
assign ram_address = riscos_dl ? (ioctl_wait ? erase_addr : {2'b01,ioctl_addr[21:2]}) : core_address_out;
|
|
assign ram_stb = riscos_dl ? loader_stb : core_stb_out;
|
|
assign ram_cyc = riscos_dl ? loader_stb : core_cyc_out;
|
|
assign ram_data_in = riscos_dl ? (ioctl_wait ? 32'd0 : {ioctl_dout,ioctl_dout}) : core_data_out;
|
|
assign core_ack_in = riscos_dl ? 1'b0 : ram_ack;
|
|
|
|
|
|
////////////////// RTC/CMOS ///////////////////
|
|
EEPROM_24C0x eeprom
|
|
(
|
|
.clk(clk_sys),
|
|
.ce(eep_ce),
|
|
.reset(reset),
|
|
|
|
.SCL(i2c_clock),
|
|
.SDA_in(i2c_din),
|
|
.SDA_out(i2c_dout),
|
|
|
|
.type_24C01(0),
|
|
.E_id(0),
|
|
.WC_n(0),
|
|
|
|
.data_from_ram(eep_dout),
|
|
.data_to_ram(eep_din),
|
|
.ram_addr(eep_addr),
|
|
.ram_read(eep_read),
|
|
.ram_write(eep_write),
|
|
.ram_done(1)
|
|
);
|
|
|
|
wire [7:0] eep_din;
|
|
wire [7:0] eep_dout;
|
|
wire [7:0] eep_addr;
|
|
wire eep_read;
|
|
wire eep_write;
|
|
|
|
reg eep_ce;
|
|
always @(posedge clk_sys) begin
|
|
reg [1:0] cnt;
|
|
cnt <= cnt + 1'd1;
|
|
eep_ce <= !cnt;
|
|
end
|
|
|
|
reg [7:0] cmos_cnt = 0;
|
|
always @(posedge clk_sys) if(eep_ce && eep_write && eep_addr >= 16) cmos_cnt <= cmos_cnt + 1'd1;
|
|
|
|
dpram_dif #(8,8,7,16,"rtl/cmos.mif") memory
|
|
(
|
|
.clock (clk_sys),
|
|
|
|
.address_a (eep_addr),
|
|
.data_a (eep_din),
|
|
.wren_a (eep_write),
|
|
.q_a (eep_dout),
|
|
|
|
.address_b (ioctl_addr[7:1]),
|
|
.data_b (ioctl_dout),
|
|
.wren_b (ioctl_wr & cmos_dl),
|
|
.q_b (ioctl_din)
|
|
);
|
|
|
|
endmodule
|