Update sys.

2026-05-24 03:03:10 +00:00 · 2022-02-21 04:53:38 +08:00
parent 07e5a05c78
commit b2f0afa419
9 changed files with 821 additions and 296 deletions
--- a/Archie.sv
+++ b/Archie.sv
@@ -29,7 +29,7 @@ module emu
 	input         RESET,

 	//Must be passed to hps_io module
-	inout  [45:0] HPS_BUS,
+	inout  [48:0] HPS_BUS,

 	//Base video clock. Usually equals to CLK_SYS.
 	output        CLK_VIDEO,
--- a/sys/arcade_video.v
+++ b/sys/arcade_video.v
@@ -174,15 +174,17 @@ module screen_rotate

 	input         rotate_ccw,
 	input         no_rotate,
+	input         flip,
+	output        video_rotated,

-	output        FB_EN,
-	output  [4:0] FB_FORMAT,
-	output [11:0] FB_WIDTH,
-	output [11:0] FB_HEIGHT,
-	output [31:0] FB_BASE,
-	output [13:0] FB_STRIDE,
-	input         FB_VBL,
-	input         FB_LL,
+	output            FB_EN,
+	output      [4:0] FB_FORMAT,
+	output reg [11:0] FB_WIDTH,
+	output reg [11:0] FB_HEIGHT,
+	output     [31:0] FB_BASE,
+	output     [13:0] FB_STRIDE,
+	input             FB_VBL,
+	input             FB_LL,

 	output        DDRAM_CLK,
 	input         DDRAM_BUSY,
@@ -196,6 +198,8 @@ module screen_rotate

 parameter MEM_BASE    = 7'b0010010; // buffer at 0x24000000, 3x8MB

+reg  do_flip;
+
 assign DDRAM_CLK      = CLK_VIDEO;
 assign DDRAM_BURSTCNT = 1;
 assign DDRAM_ADDR     = {MEM_BASE, i_fb, ram_addr[22:3]};
@@ -207,8 +211,6 @@ assign DDRAM_RD       = 0;
 assign FB_EN     = fb_en[2];
 assign FB_FORMAT = 5'b00110;
 assign FB_BASE   = {MEM_BASE,o_fb,23'd0};
-assign FB_WIDTH  = vsz;
-assign FB_HEIGHT = hsz;
 assign FB_STRIDE = stride;

 function [1:0] buf_next;
@@ -220,6 +222,19 @@ function [1:0] buf_next;
 	end
 endfunction

+assign video_rotated = ~no_rotate;
+
+always @(posedge CLK_VIDEO) begin
+	do_flip <= no_rotate && flip;
+	if( do_flip ) begin
+		FB_WIDTH  <= hsz;
+		FB_HEIGHT <= vsz;
+	end else begin
+		FB_WIDTH  <= vsz;
+		FB_HEIGHT <= hsz;
+	end
+end
+
 reg [1:0] i_fb,o_fb;
 always @(posedge CLK_VIDEO) begin
 	reg old_vbl,old_vs;
@@ -251,20 +266,23 @@ always @(posedge CLK_VIDEO) begin
 	if(CE_PIXEL) begin
 		old_vs <= VGA_VS;
 		old_de <= VGA_DE;
-		
+
 		hcnt <= hcnt + 1'd1;
 		if(~old_de & VGA_DE) begin
 			hcnt <= 1;
 			vcnt <= vcnt + 1'd1;
 		end
-		if(old_de & ~VGA_DE) hsz <= hcnt;
+		if(old_de & ~VGA_DE) begin
+			hsz <= hcnt;
+			if( do_flip ) bwidth <= hcnt + 2'd3;
+		end
 		if(~old_vs & VGA_VS) begin
 			vsz <= vcnt;
-			bwidth <= vcnt + 2'd3;
+			if( !do_flip ) bwidth <= vcnt + 2'd3;
 			vcnt <= 0;
-			fb_en <= {fb_en[1:0], ~no_rotate};
+			fb_en <= {fb_en[1:0], ~no_rotate | flip};
 		end
-		if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
+		if(old_vs & ~VGA_VS) bufsize <= (do_flip ? vsz : hsz ) * stride;
 	end
 end

@@ -278,21 +296,25 @@ always @(posedge CLK_VIDEO) begin
 	reg old_vs, old_de;

 	ram_wr <= 0;
-	if(CE_PIXEL) begin
+	if(CE_PIXEL && FB_EN) begin
 		old_vs <= VGA_VS;
 		old_de <= VGA_DE;

 		if(~old_vs & VGA_VS) begin
-			next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
+			next_addr <=
+				do_flip    ? bufsize-3'd4 :
+				rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
 			hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
 		end
 		if(VGA_DE) begin
 			ram_wr <= 1;
-			ram_data <= {VGA_B,VGA_G,VGA_R};
+			ram_data <= {8'd0,VGA_B,VGA_G,VGA_R};
 			ram_addr <= next_addr;
-			next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride);
+			next_addr <=
+				do_flip    ? next_addr-3'd4 :
+				rotate_ccw ? (next_addr - stride) : (next_addr + stride);
 		end
-		if(old_de & ~VGA_DE) begin
+		if(old_de & ~VGA_DE & ~do_flip) begin
 			next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
 			hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
 		end
--- a/sys/ascal.vhd
+++ b/sys/ascal.vhd
--- a/sys/hps_io.sv
+++ b/sys/hps_io.sv
@@ -24,13 +24,13 @@
 // Use buffer to access SD card. It's time-critical part.
 //
 // WIDE=1 for 16 bit file I/O
-// VDNUM 1..4
+// VDNUM 1..10
 // BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
 //
 module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
 (
 	input             clk_sys,
-	inout      [45:0] HPS_BUS,
+	inout      [48:0] HPS_BUS,

 	// buttons up to 32
 	output reg [31:0] joystick_0,
@@ -41,12 +41,19 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
 	output reg [31:0] joystick_5,
 	
 	// analog -127..+127, Y: [15:8], X: [7:0]
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output reg [15:0] joystick_analog_2,
-	output reg [15:0] joystick_analog_3,
-	output reg [15:0] joystick_analog_4,
-	output reg [15:0] joystick_analog_5,
+	output reg [15:0] joystick_l_analog_0,
+	output reg [15:0] joystick_l_analog_1,
+	output reg [15:0] joystick_l_analog_2,
+	output reg [15:0] joystick_l_analog_3,
+	output reg [15:0] joystick_l_analog_4,
+	output reg [15:0] joystick_l_analog_5,
+
+	output reg [15:0] joystick_r_analog_0,
+	output reg [15:0] joystick_r_analog_1,
+	output reg [15:0] joystick_r_analog_2,
+	output reg [15:0] joystick_r_analog_3,
+	output reg [15:0] joystick_r_analog_4,
+	output reg [15:0] joystick_r_analog_5,

 	// paddle 0..255
 	output reg  [7:0] paddle_0,
@@ -67,6 +74,10 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
 	output      [1:0] buttons,
 	output            forced_scandoubler,
 	output            direct_video,
+	input             video_rotated,
+
+	//toggle to force notify of video mode change
+	input             new_vmode,

 	output reg [63:0] status,
 	input      [63:0] status_in,
@@ -76,9 +87,6 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
 	input             info_req,
 	input       [7:0] info,

-	//toggle to force notify of video mode change
-	input             new_vmode,
-
 	// SD config
 	output reg [VD:0] img_mounted,  // signaling that new image has been mounted
 	output reg        img_readonly, // mounted as read only. valid only for active bit in img_mounted
@@ -104,6 +112,8 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
 	output reg [26:0] ioctl_addr,         // in WIDE mode address will be incremented by 2
 	output reg [DW:0] ioctl_dout,
 	output reg        ioctl_upload = 0,   // signal indicating an active upload
+	input             ioctl_upload_req,   // request to save (must be supported on HPS side for specific core)
+	input       [7:0] ioctl_upload_index,
 	input      [DW:0] ioctl_din,
 	output reg        ioctl_rd,
 	output reg [31:0] ioctl_file_ext,
@@ -207,6 +217,7 @@ video_calc video_calc
 	.vs_hdmi(HPS_BUS[44]),
 	.f1(HPS_BUS[45]),
 	.new_vmode(new_vmode),
+	.video_rotated(video_rotated),

 	.par_num(byte_cnt[3:0]),
 	.dout(vc_dout)
@@ -250,6 +261,8 @@ always@(posedge clk_sys) begin : uio_block
 	reg  [3:0] stflg = 0;
 	reg [63:0] status_req;
 	reg        old_status_set = 0;
+	reg        old_upload_req = 0;
+	reg        upload_req = 0;
 	reg        old_info = 0;
 	reg  [7:0] info_n = 0;
 	reg [15:0] tmp1;
@@ -261,6 +274,9 @@ always@(posedge clk_sys) begin : uio_block
 		stflg <= stflg + 1'd1;
 		status_req <= status_in;
 	end
+	
+	old_upload_req <= ioctl_upload_req;
+	if(~old_upload_req & ioctl_upload_req) upload_req <= 1;

 	old_info <= info_req;
 	if(~old_info & info_req) info_n <= info;
@@ -303,11 +319,17 @@ always@(posedge clk_sys) begin : uio_block
 				'h0X17,
 				'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end
 				  'h29: io_dout <= {4'hA, stflg};
-				  'h2B: io_dout <= 1;
+`ifdef MISTER_DISABLE_ADAPTIVE
+				  'h2B: io_dout <= {HPS_BUS[48:46],4'b0010};
+`else
+				  'h2B: io_dout <= {HPS_BUS[48:46],4'b0011};
+`endif
 				  'h2F: io_dout <= 1;
 				  'h32: io_dout <= gamma_bus[21];
 				  'h36: begin io_dout <= info_n; info_n <= 0; end
 				  'h39: io_dout <= 1;
+				  'h3C: if(upload_req) begin io_dout <= {ioctl_upload_index, 8'd1}; upload_req <= 0; end
+				  'h3E: io_dout <= 1; // shadow mask
 			endcase

 			sd_buff_addr <= 0;
@@ -380,17 +402,17 @@ always@(posedge clk_sys) begin : uio_block
 							io_dout <= sd_buff_din[sdn_ack];
 						end

-				// joystick analog
+				// joystick left analog
 				'h1a: if(!byte_cnt[MAX_W:2]) begin
 							case(byte_cnt[1:0])
 								1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
 								2: case(stick_idx)
-										 0: joystick_analog_0 <= io_din;
-										 1: joystick_analog_1 <= io_din;
-										 2: joystick_analog_2 <= io_din;
-										 3: joystick_analog_3 <= io_din;
-										 4: joystick_analog_4 <= io_din;
-										 5: joystick_analog_5 <= io_din;
+										 0: joystick_l_analog_0 <= io_din;
+										 1: joystick_l_analog_1 <= io_din;
+										 2: joystick_l_analog_2 <= io_din;
+										 3: joystick_l_analog_3 <= io_din;
+										 4: joystick_l_analog_4 <= io_din;
+										 5: joystick_l_analog_5 <= io_din;
 										15: case(pdsp_idx)
 												 0: paddle_0 <= io_din[7:0];
 												 1: paddle_1 <= io_din[7:0];
@@ -409,6 +431,21 @@ always@(posedge clk_sys) begin : uio_block
 							endcase
 						end

+				// joystick right analog
+				'h3d: if(!byte_cnt[MAX_W:2]) begin
+							case(byte_cnt[1:0])
+								1: stick_idx <= io_din[3:0]; // first byte is joystick index
+								2: case(stick_idx)
+										 0: joystick_r_analog_0 <= io_din;
+										 1: joystick_r_analog_1 <= io_din;
+										 2: joystick_r_analog_2 <= io_din;
+										 3: joystick_r_analog_3 <= io_din;
+										 4: joystick_r_analog_4 <= io_din;
+										 5: joystick_r_analog_5 <= io_din;
+									endcase
+							endcase
+						end
+
 				// notify image selection
 				'h1c: begin
 							img_mounted  <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
@@ -812,6 +849,7 @@ module video_calc
 	input vs_hdmi,
 	input f1,
 	input new_vmode,
+	input video_rotated,

 	input       [3:0] par_num,
 	output reg [15:0] dout
@@ -819,7 +857,7 @@ module video_calc

 always @(posedge clk_sys) begin
 	case(par_num)
-		1: dout <= {|vid_int, vid_nres};
+		1: dout <= {video_rotated, |vid_int, vid_nres};
 		2: dout <= vid_hcnt[15:0];
 		3: dout <= vid_hcnt[31:16];
 		4: dout <= vid_vcnt[15:0];
--- a/sys/scanlines.v
+++ b/sys/scanlines.v
@@ -5,11 +5,11 @@ module scanlines #(parameter v2=0)
 	input       [1:0] scanlines,
 	input      [23:0] din,
 	input             hs_in,vs_in,
-	input             de_in,
+	input             de_in,ce_in,

 	output reg [23:0] dout,
 	output reg        hs_out,vs_out,
-	output reg        de_out
+	output reg        de_out,ce_out
 );

 reg [1:0] scanline;
@@ -56,12 +56,13 @@ end

 always @(posedge clk) begin
 	reg [23:0] dout1, dout2;
-	reg de1,de2,vs1,vs2,hs1,hs2;
+	reg de1,de2,vs1,vs2,hs1,hs2,ce1,ce2;

 	dout   <= dout2; dout2 <= dout1; dout1 <= d;     
 	vs_out <= vs2;   vs2   <= vs1;   vs1   <= vs_in; 
 	hs_out <= hs2;   hs2   <= hs1;   hs1   <= hs_in; 
 	de_out <= de2;   de2   <= de1;   de1   <= de_in; 
+	ce_out <= ce2;   ce2   <= ce1;   ce1   <= ce_in; 
 end

 endmodule
--- a/sys/shadowmask.sv
+++ b/sys/shadowmask.sv
@@ -0,0 +1,136 @@
+module shadowmask
+(
+	input             clk,
+	input             clk_sys,
+
+	input             cmd_wr,
+	input      [15:0] cmd_in,
+
+	input      [23:0] din,
+	input             hs_in,vs_in,
+	input             de_in,
+	input             brd_in,
+	input             enable,
+
+	output reg [23:0] dout,
+	output reg        hs_out,vs_out,
+	output reg        de_out
+);
+
+
+reg  [4:0] hmax;
+reg  [4:0] vmax;
+reg  [7:0] mask_idx;
+reg        mask_2x;
+reg        mask_rotate;
+reg        mask_enable;
+reg [10:0] mask_lut[256];
+
+always @(posedge clk) begin
+	reg [4:0] hcount;
+	reg [4:0] vcount;
+	reg [3:0] hindex;
+	reg [3:0] vindex;
+	reg [4:0] hmax2;
+	reg [4:0] vmax2;
+	reg [11:0] pcnt,pde;
+	reg old_hs, old_vs, old_brd;
+	reg next_v;
+
+	old_hs <= hs_in;
+	old_vs <= vs_in;
+	old_brd<= brd_in;
+
+	// hcount and vcount counts pixel rows and columns
+	// hindex and vindex half the value of the counters for double size patterns
+	// hindex2, vindex2 swap the h and v counters for drawing rotated masks
+	hindex <= mask_2x ? hcount[4:1] : hcount[3:0];
+	vindex <= mask_2x ? vcount[4:1] : vcount[3:0];
+	mask_idx <= mask_rotate ? {hindex,vindex} : {vindex,hindex};
+
+	// hmax and vmax store these sizes
+	// hmax2 and vmax2 swap the values to handle rotation
+	hmax2 <= ((mask_rotate ? vmax : hmax) << mask_2x) | mask_2x;
+	vmax2 <= ((mask_rotate ? hmax : vmax) << mask_2x) | mask_2x;
+
+	pcnt <= pcnt+1'd1;
+	if(old_brd && ~brd_in) pde <= pcnt-4'd3;
+
+	hcount <= hcount+1'b1;
+	if(hcount == hmax2 || pde == pcnt) hcount <= 0;
+
+	if(~old_brd && brd_in) next_v <= 1;
+	if(old_vs && ~vs_in) vcount <= 0;
+	if(old_hs && ~hs_in) begin
+		vcount <= vcount + next_v;
+		next_v <= 0;
+		pcnt   <= 0;
+		if (vcount == vmax2) vcount <= 0;
+	end
+end
+
+reg [4:0] r_mul, g_mul, b_mul; // 1.4 fixed point multipliers
+always @(posedge clk) begin
+	reg [10:0] lut;
+
+	lut <= mask_lut[mask_idx];
+
+	r_mul <= 5'b10000; g_mul <= 5'b10000; b_mul <= 5'b10000; // default 100% to all channels
+	if (mask_enable) begin
+		r_mul <= lut[10] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
+		g_mul <= lut[9]  ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
+		b_mul <= lut[8]  ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
+	end
+end
+
+always @(posedge clk) begin
+	reg [11:0] vid;
+	reg  [7:0] r1,   g1,   b1;
+	reg  [7:0] r2,   g2,   b2;
+	reg  [7:0] r3_x, g3_x, b3_x; // 6.25% + 12.5%
+	reg  [8:0] r3_y, g3_y, b3_y; // 25% + 50% + 100%
+	reg  [8:0] r4,   g4,   b4;
+
+	// C1 - data input
+	{r1,g1,b1} <= din;
+	vid <= {vid[8:0],vs_in, hs_in, de_in};
+
+	// C2 - relax timings
+	{r2,g2,b2} <= {r1,g1,b1};
+
+	// C3 - perform multiplications
+	r3_x <= ({4{r_mul[0]}} & r2[7:4]) + ({8{r_mul[1]}} & r2[7:3]);
+	r3_y <= ({6{r_mul[2]}} & r2[7:2]) + ({7{r_mul[3]}} & r2[7:1]) + ({9{r_mul[4]}} & r2[7:0]);
+	g3_x <= ({4{g_mul[0]}} & g2[7:4]) + ({8{g_mul[1]}} & g2[7:3]);
+	g3_y <= ({6{g_mul[2]}} & g2[7:2]) + ({7{g_mul[3]}} & g2[7:1]) + ({9{g_mul[4]}} & g2[7:0]);
+	b3_x <= ({4{b_mul[0]}} & b2[7:4]) + ({8{b_mul[1]}} & b2[7:3]);
+	b3_y <= ({6{b_mul[2]}} & b2[7:2]) + ({7{b_mul[3]}} & b2[7:1]) + ({9{b_mul[4]}} & b2[7:0]);
+
+	// C4 - combine results
+	r4 <= r3_x + r3_y;
+	g4 <= g3_x + g3_y;
+	b4 <= b3_x + b3_y;
+
+	// C5 - clamp and output
+	dout <= {{8{r4[8]}} | r4[7:0], {8{g4[8]}} | g4[7:0], {8{b4[8]}} | b4[7:0]};
+	{vs_out,hs_out,de_out} <= vid[11:9];
+end
+
+// clock in mask commands
+always @(posedge clk_sys) begin
+	reg m_enable;
+	reg [7:0] idx;
+
+	if (cmd_wr) begin
+		case(cmd_in[15:13])
+		3'b000: begin {m_enable, mask_rotate, mask_2x} <= cmd_in[3:1]; idx <= 0; end
+		3'b001: vmax <= cmd_in[3:0];
+		3'b010: hmax <= cmd_in[3:0];
+		3'b011: begin mask_lut[idx] <= cmd_in[10:0]; idx <= idx + 1'd1; end
+		endcase
+	end
+
+	mask_enable <= m_enable & enable;
+end
+
+endmodule
--- a/sys/sys.qip
+++ b/sys/sys.qip
@@ -7,6 +7,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) m
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scandoubler.v ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scanlines.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) shadowmask.sv ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
--- a/sys/sys_dual_sdram.tcl
+++ b/sys/sys_dual_sdram.tcl
@@ -47,4 +47,4 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
 set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
 set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*

-set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1"
+set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"
--- a/sys/sys_top.v
+++ b/sys/sys_top.v
@@ -295,7 +295,7 @@ reg [31:0] cfg_custom_p2;
 reg  [4:0] vol_att;
 initial vol_att = 5'b11111;

-reg  [6:0] coef_addr;
+reg  [9:0] coef_addr;
 reg  [8:0] coef_data;
 reg        coef_wr = 0;

@@ -336,6 +336,10 @@ always@(posedge clk_sys) begin
 	old_strobe <= io_strobe;
 	coef_wr <= 0;

+`ifndef MISTER_DEBUG_NOHDMI
+	shadowmask_wr <= 0;
+`endif
+
 	if(~io_uio) begin
 		has_cmd <= 0;
 		cmd <= 0;
@@ -363,6 +367,7 @@ always@(posedge clk_sys) begin
 			end
 		end
 		else begin
+			cnt <= cnt + 1'd1;
 			if(cmd == 1) begin
 				cfg <= io_din;
 				cfg_set <= 1;
@@ -370,7 +375,6 @@ always@(posedge clk_sys) begin
 			end
 			if(cmd == 'h20) begin
 				cfg_set <= 0;
-				cnt <= cnt + 1'd1;
 				if(cnt<8) begin
 					case(cnt[2:0])
 						0: if(WIDTH  != io_din[11:0]) WIDTH  <= io_din[11:0];
@@ -402,7 +406,6 @@ always@(posedge clk_sys) begin
 				end
 			end
 			if(cmd == 'h2F) begin
-				cnt <= cnt + 1'd1;
 				case(cnt[3:0])
 					0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]};
 					1: LFB_BASE[15:0]  <= io_din[15:0];
@@ -419,12 +422,14 @@ always@(posedge clk_sys) begin
 			if(cmd == 'h25) {led_overtake, led_state} <= io_din;
 			if(cmd == 'h26) vol_att <= io_din[4:0];
 			if(cmd == 'h27) VSET <= io_din[11:0];
-			if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
+			if(cmd == 'h2A) begin
+				if(cnt[0]) {coef_wr,coef_data} <= {1'b1,io_din[8:0]};
+				else coef_addr <= io_din[9:0];
+			end
 			if(cmd == 'h2B) scaler_flt <= io_din[2:0];
 			if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
 			if(cmd == 'h38) vs_line <= io_din[11:0];
 			if(cmd == 'h39) begin
-				cnt <= cnt + 1'd1;
 				case(cnt[3:0])
 					 0: acx_att          <= io_din[4:0];
 					 1: aflt_rate[15:0]  <= io_din;
@@ -444,7 +449,6 @@ always@(posedge clk_sys) begin
 				endcase
 			end
 			if(cmd == 'h3A) begin
-				cnt <= cnt + 1'd1;
 				case(cnt[3:0])
 					 0: arc1x <= io_din[12:0];
 					 1: arc1y <= io_din[12:0];
@@ -452,6 +456,9 @@ always@(posedge clk_sys) begin
 					 3: arc2y <= io_din[12:0];
 				endcase
 			end
+`ifndef MISTER_DEBUG_NOHDMI
+			if(cmd == 'h3E) {shadowmask_wr,shadowmask_data} <= {1'b1, io_din};
+`endif
 		end
 	end

@@ -618,7 +625,7 @@ wire  [15:0] vbuf_byteenable;
 wire         vbuf_write;

 wire  [23:0] hdmi_data;
-wire         hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl;
+wire         hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd;
 wire         freeze;

 `ifndef MISTER_DEBUG_NOHDMI
@@ -634,6 +641,13 @@ ascal
 		.PALETTE2("false"),
 	`endif
 `endif
+`ifdef MISTER_DISABLE_ADAPTIVE
+	.ADAPTIVE("false"),
+`endif
+`ifdef MISTER_DOWNSCALE_NN
+	.DOWNSCALE_NN("true"),
+`endif
+	.FRAC(6),
 	.N_DW(128),
 	.N_AW(28)
 )
@@ -667,6 +681,7 @@ ascal
 	.o_vs     (hdmi_vs),
 	.o_de     (hdmi_de),
 	.o_vbl    (hdmi_vbl),
+	.o_brd    (hdmi_brd),
 	.o_lltune (lltune),
 	.htotal   (WIDTH + HFP + HBP + HS),
 	.hsstart  (WIDTH + HFP),
@@ -1049,34 +1064,43 @@ cyclonev_hps_interface_peripheral_i2c hdmi_i2c
 );

 `ifndef MISTER_DEBUG_NOHDMI
-wire [23:0] hdmi_data_sl;
-wire        hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl;

 `ifdef MISTER_FB
 reg dis_output;
 always @(posedge clk_hdmi) begin
 	reg dis;
-	dis <= fb_force_blank;
+	dis <= fb_force_blank & ~LFB_EN;
 	dis_output <= dis;
 end
 `else
 wire dis_output = 0;
 `endif

-scanlines #(1) HDMI_scanlines
+wire [23:0] hdmi_data_mask;
+wire        hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;
+
+reg [15:0] shadowmask_data;
+reg        shadowmask_wr = 0;
+
+shadowmask HDMI_shadowmask
 (
 	.clk(clk_hdmi),
+	.clk_sys(clk_sys),
+
+	.cmd_wr(shadowmask_wr),
+	.cmd_in(shadowmask_data),

-	.scanlines(scanlines),
 	.din(dis_output ? 24'd0 : hdmi_data),
 	.hs_in(hdmi_hs),
 	.vs_in(hdmi_vs),
 	.de_in(hdmi_de),
-	
-	.dout(hdmi_data_sl),
-	.hs_out(hdmi_hs_sl),
-	.vs_out(hdmi_vs_sl),
-	.de_out(hdmi_de_sl)
+	.brd_in(hdmi_brd),
+	.enable(~LFB_EN),
+
+	.dout(hdmi_data_mask),
+	.hs_out(hdmi_hs_mask),
+	.vs_out(hdmi_vs_mask),
+	.de_out(hdmi_de_mask)
 );

 wire [23:0] hdmi_data_osd;
@@ -1091,10 +1115,10 @@ osd hdmi_osd
 	.io_din(io_din),

 	.clk_video(clk_hdmi),
-	.din(hdmi_data_sl),
-	.hs_in(hdmi_hs_sl),
-	.vs_in(hdmi_vs_sl),
-	.de_in(hdmi_de_sl),
+	.din(hdmi_data_mask),
+	.hs_in(hdmi_hs_mask),
+	.vs_in(hdmi_vs_mask),
+	.de_in(hdmi_de_mask),

 	.dout(hdmi_data_osd),
 	.hs_out(hdmi_hs_osd),
@@ -1212,7 +1236,7 @@ assign HDMI_TX_D  = hdmi_out_d;
 /////////////////////////  VGA output  //////////////////////////////////

 wire [23:0] vga_data_sl;
-wire        vga_de_sl, vga_vs_sl, vga_hs_sl;
+wire        vga_de_sl, vga_ce_sl, vga_vs_sl, vga_hs_sl;
 scanlines #(0) VGA_scanlines
 (
 	.clk(clk_vid),
@@ -1222,11 +1246,13 @@ scanlines #(0) VGA_scanlines
 	.hs_in(hs_fix),
 	.vs_in(vs_fix),
 	.de_in(de_emu),
+	.ce_in(ce_pix),

 	.dout(vga_data_sl),
 	.hs_out(vga_hs_sl),
 	.vs_out(vga_vs_sl),
-	.de_out(vga_de_sl)
+	.de_out(vga_de_sl),
+	.ce_out(vga_ce_sl)
 );

 wire [23:0] vga_data_osd;
@@ -1461,13 +1487,13 @@ sync_fix sync_h(clk_vid, hs_emu, hs_fix);
 wire  [6:0] user_out, user_in;

 assign clk_ihdmi= clk_vid;
-assign ce_hpix  = ce_pix;
-assign hr_out   = r_out;
-assign hg_out   = g_out;
-assign hb_out   = b_out;
-assign hhs_fix  = hs_fix;
-assign hvs_fix  = vs_fix;
-assign hde_emu  = de_emu;
+assign ce_hpix  = vga_ce_sl;
+assign hr_out   = vga_data_sl[23:16];
+assign hg_out   = vga_data_sl[15:8];
+assign hb_out   = vga_data_sl[7:0];
+assign hhs_fix  = vga_hs_sl;
+assign hvs_fix  = vga_vs_sl;
+assign hde_emu  = vga_de_sl;

 wire uart_dtr;
 wire uart_dsr;
@@ -1504,11 +1530,15 @@ wire [13:0] fb_stride;
 	assign fb_stride = 0;
 `endif

+reg  [1:0] sl_r;
+wire [1:0] sl = sl_r;
+always @(posedge clk_sys) sl_r <= FB_EN ? 2'b00 : scanlines;
+
 emu emu
 (
 	.CLK_50M(FPGA_CLK2_50),
 	.RESET(reset),
-	.HPS_BUS({f1, HDMI_TX_VS, 
+	.HPS_BUS({fb_en, sl, f1, HDMI_TX_VS, 
 				 clk_100m, clk_ihdmi,
 				 ce_hpix, hde_emu, hhs_fix, hvs_fix, 
 				 io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),