Sources re-organization.

files.qip

@@ -1,24 +1,15 @@
 set_global_assignment -name QIP_FILE rtl/amber/amber.qip
+set_global_assignment -name QIP_FILE rtl/vidc/vidc.qip
+set_global_assignment -name QIP_FILE rtl/fdc/fdc.qip
+set_global_assignment -name QIP_FILE rtl/rtc/rtc.qip
 set_global_assignment -name VERILOG_FILE rtl/sdram.v
-set_global_assignment -name VERILOG_FILE rtl/vidc_audio.v
-set_global_assignment -name VERILOG_FILE rtl/vidc_dmachannel.v
-set_global_assignment -name VERILOG_FILE rtl/vidc_fifo.v
-set_global_assignment -name VERILOG_FILE rtl/vidc_timing.v
-set_global_assignment -name VERILOG_FILE rtl/vidc.v
-set_global_assignment -name VERILOG_FILE rtl/fdc1772.v
-set_global_assignment -name VERILOG_FILE rtl/floppy.v
+set_global_assignment -name VHDL_FILE rtl/bram.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/ide.sv
 set_global_assignment -name VERILOG_FILE rtl/latches.v
-set_global_assignment -name VERILOG_FILE rtl/serialInterface.v
-set_global_assignment -name VERILOG_FILE rtl/registerInterface.v
-set_global_assignment -name VERILOG_FILE rtl/i2cSlave.v
 set_global_assignment -name VERILOG_FILE rtl/ioc_irq.v
 set_global_assignment -name VERILOG_FILE rtl/ioc.v
 set_global_assignment -name VERILOG_FILE rtl/memc_translator.v
 set_global_assignment -name VERILOG_FILE rtl/memc.v
-set_global_assignment -name VERILOG_FILE rtl/sram_line_en.v
-set_global_assignment -name VERILOG_FILE rtl/sram_byte_en.v
-set_global_assignment -name VHDL_FILE rtl/bram.vhd
 set_global_assignment -name VERILOG_FILE rtl/archimedes_top.v
 set_global_assignment -name VERILOG_FILE rtl/hps_ext.v
 set_global_assignment -name SDC_FILE Archie.sdc

rtl/amber/amber.qip

@@ -1,3 +1,4 @@
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_config_defines.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_barrel_shift.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_wishbone.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_register_bank.v ]
@@ -5,8 +6,9 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_mul
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_fetch.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_execute.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_decode.v ]
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_core.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_coprocessor.v ]
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_config_defines.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_cache.v ]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_alu.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sram_byte_en.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sram_line_en.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a23_core.v ]

rtl/audio.v

@@ -1,47 +0,0 @@
-//
-// audio.v
-// 
-// Archie audio subsystem implementation for the MiST board
-// http://code.google.com/p/mist-board/
-// 
-// Copyright (c) 2015 Stephen Leary <stephen@vavi.co.uk> 
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-module audio(
-	input  	rst,
-	input 	clk,      // 32 MHz
-
-	input	[15:0] audio_data_r,
-	input	[15:0] audio_data_l,
-	
-	output 	audio_r,
-	output 	audio_l
-);
-
-sigma_delta_dac sigma_delta_dac_l (
-	.DACout 		(audio_l),
-	.DACin		(audio_data_l[15:0]),
-	.CLK 			(clk),
-	.RESET 		(rst)
-);
-
-sigma_delta_dac sigma_delta_dac_r (
-	.DACout     (audio_r),
-	.DACin    	(audio_data_r[15:0]),
-	.CLK      	(clk),
-	.RESET    	(rst)
-);
-
-endmodule

rtl/fdc/fdc.qip

@@ -0,0 +1,2 @@
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) floppy.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) fdc1772.v ]

rtl/ide.sv

@@ -17,6 +17,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+// altera message_off 10030
 module ide (
 	input             clk, // system clock.
 	input             reset,

rtl/rtc/registerInterface.v

@@ -56,7 +56,7 @@ module registerInterface
 );
 
 wire [7:0] mem_out;
-spram #(8,8,"rtl/cmos.mif","CMOS") memory
+spram #(8,8,"rtl/rtc/cmos.mif","CMOS") memory
 (
 	.clock(clk),
 	.address(addr),

rtl/rtc/rtc.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2cSlave.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2cSlave_define.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) serialInterface.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) registerInterface.v ]

rtl/rtc/serialInterface.v

@@ -52,7 +52,6 @@
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 //
-`include "timescale.v"
 `include "i2cSlave_define.v"
 
 module serialInterface (clearStartStopDet, clk, dataIn, dataOut, regAddr, rst, scl, sdaIn, sdaOut, startStopDetState, writeEn);

rtl/timescale.v

@@ -1,5 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-// timescale.v                                              
-//////////////////////////////////////////////////////////////////////
-`timescale 1ns / 1ps
-

rtl/vidc/vidc.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) vidc_dmachannel.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) vidc_fifo.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) vidc_timing.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) vidc_audio.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) vidc.v ]