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Latest updates adding soft processors

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This commit is contained in:
Philip Smart
2021-02-06 11:31:15 +00:00
parent 290ae9aadd
commit 13d5438dc7
139 changed files with 177486 additions and 89734 deletions
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21
.gitignore vendored
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@@ -214,4 +214,25 @@ FPGA/SW700/v1.2/build/output_files/
FPGA/SW700/v1.3/XX
FPGA/SW700/v1.3/build/output_files/
FPGA/SW700/v1.3/devices.old/
CPLD/SW700/v1.3.bak/
FPGA/SW700/v1.3.bak/
FPGA/SW700/v1.3/PLL/Video_Clock.BAK.vhd
FPGA/SW700/v1.3/PLL/Video_Clock_II.BAK.vhd
FPGA/SW700/v1.3/PLL/Video_Clock_III.BAK.vhd
FPGA/SW700/v1.3/PLL/Video_Clock_IV.BAK.vhd
FPGA/SW700/v1.3/VideoController.vhd.prechangegputobram
FPGA/SW700/v1.3/build/VideoController_constraints.sdc
FPGA/SW700/v1.3/build/coreMZ_E115_description.txt
FPGA/SW700/v1.3/coreMZ_constraints.sdc.old
FPGA/SW700/v1.3/prechange.vhd
FPGA/SW700/v1.3/prechange2.vhd
FPGA/SW700/v1.3/softT80/constraints_t80_ok
FPGA/a-z80/
FPGA/a-z80_latest.tar.gz
FPGA/nextz80/
FPGA/nextz80_latest.tar.gz
FPGA/SW700/v1.3/VideoController/VideoController_constraints.sdc.orig
SD/
devices/sysbus/BRAM/TZSW_DualPort32-64BootBRAM.vhd
devices/sysbus/BRAM/TZSW_DualPort3264BootBRAM.vhd

22
CPLD/SW700/v1.3/build/tranZPUterSW700.qsf
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@@ -56,6 +56,11 @@ set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
# Z80 Address Bus
# ===============
set_location_assignment PIN_41 -to Z80_HI_ADDR[23]
set_location_assignment PIN_42 -to Z80_HI_ADDR[22]
set_location_assignment PIN_43 -to Z80_HI_ADDR[21]
set_location_assignment PIN_44 -to Z80_HI_ADDR[20]
set_location_assignment PIN_45 -to Z80_HI_ADDR[19]
set_location_assignment PIN_107 -to Z80_HI_ADDR[18]
set_location_assignment PIN_102 -to Z80_HI_ADDR[17]
set_location_assignment PIN_108 -to Z80_HI_ADDR[16]
@@ -130,13 +135,13 @@ set_location_assignment PIN_26 -to VZ80_MREQn
# FPGA Video and Control signals.
# ===============================
set_location_assignment PIN_10 -to VWAITn_V_CSYNC
set_location_assignment PIN_12 -to VZ80_RFSHn_V_HSYNC
set_location_assignment PIN_14 -to VZ80_HALTn_V_VSYNC
set_location_assignment PIN_10 -to VWAITn_A21_V_CSYNC
set_location_assignment PIN_12 -to VZ80_A20_RFSHn_V_HSYNC
set_location_assignment PIN_14 -to VZ80_A19_HALTn_V_VSYNC
set_location_assignment PIN_15 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_16 -to VZ80_WAITn_V_B
set_location_assignment PIN_18 -to VZ80_INTn_V_R
set_location_assignment PIN_19 -to VZ80_NMIn_V_COLR
set_location_assignment PIN_16 -to VZ80_A16_WAITn_V_B
set_location_assignment PIN_18 -to VZ80_A18_INTn_V_R
set_location_assignment PIN_19 -to VZ80_A17_NMIn_V_COLR
# RAM control
# ===========
@@ -158,11 +163,6 @@ set_location_assignment PIN_128 -to CTLCLK
set_location_assignment PIN_47 -to CTL_M1n
set_location_assignment PIN_54 -to CTL_MBSEL
set_location_assignment PIN_55 -to CTL_BUSRQn
set_location_assignment PIN_41 -to Z80_MEM[4]
set_location_assignment PIN_42 -to Z80_MEM[3]
set_location_assignment PIN_43 -to Z80_MEM[2]
set_location_assignment PIN_44 -to Z80_MEM[1]
set_location_assignment PIN_45 -to Z80_MEM[0]
# Z80 Control signals.
# ====================

65
CPLD/SW700/v1.3/build/tranZPUterSW700_constraints.sdc
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@@ -72,7 +72,7 @@ create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [ get_po
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSELn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSEL}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}]
@@ -108,9 +108,9 @@ set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RFSHn_V_HSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_HALTn_V_VSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}]
#**************************************************************
# Set Output Delay
@@ -130,7 +130,6 @@ set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}]
@@ -144,13 +143,15 @@ set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ8
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_RDn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_WRn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_INTn_V_R}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A18_INTn_V_R}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSRQn_V_G}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WAITn_V_B}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_NMIn_V_COLR}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RFSHn_V_HSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_HALTn_V_VSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A16_WAITn_V_B}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A17_NMIn_V_COLR}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HALTn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RFSHn}]
# For K64F
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}]
@@ -167,39 +168,46 @@ set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n}
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 30.000
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 30.000
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 30.000
set_max_delay -from [get_ports {VZ80_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000
set_max_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000
set_max_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 30.000
set_max_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 30.000
set_max_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 30.000
set_max_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 30.000
set_max_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 30.000
set_max_delay -from [get_ports {VZ80_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000
set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 40.000
set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 40.000
set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 40.000
set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 30.000
set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 30.000
set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 30.000
set_max_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 45.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 45.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 30.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 45.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 50.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 45.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 60.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 45.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 60.000
#**************************************************************
# Set Max Delay
# Set Min Delay
#**************************************************************
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 1.000
@@ -207,12 +215,19 @@ set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n}
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 1.000
set_min_delay -from [get_ports {VZ80_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 1.000
set_min_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 1.000
set_min_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 1.000
set_min_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 1.000
set_min_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 1.000
set_min_delay -from [get_ports {VZ80_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000
set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 1.000
set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 1.000
set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 1.000
set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 1.000
set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 1.000
set_min_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 1.000
@@ -273,7 +288,7 @@ set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2
#**************************************************************
# Set Maximum Delay

337
CPLD/SW700/v1.3/tranZPUterSW700.vhd
View File

@@ -39,6 +39,10 @@
-- The keyboard mapping has been removed as more complex signal switching is
-- needed and this logic will be placed in the FPGA. The CPLD still remains
-- the central memory management for both hard and soft CPU's.
-- Jan 2021 - Better control of the external Asyn BUSRQ/BUSACK was needed, bringing in
-- the async K64F CTL_BUSRQ into the Z80 clocked domain and adjustment of
-- mux lines. Adjustment of timing to better support processors running
-- inside the FPGA.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
@@ -66,7 +70,7 @@ entity cpld512 is
--);
port (
-- Z80 Address and Data.
Z80_HI_ADDR : inout std_logic_vector(18 downto 16); -- Hi address. These are the upper bank bits allowing 512K of address space. They are directly set by the K64F when accessing RAM or FPGA and set by the FPGA according to memory mode.
Z80_HI_ADDR : inout std_logic_vector(23 downto 16); -- Hi address. These are the upper bank bits allowing 512K of address space. They are directly set by the K64F when accessing RAM or FPGA and set by the FPGA according to memory mode.
Z80_RA_ADDR : out std_logic_vector(15 downto 12); -- Row address - RAM is subdivided into 4K blocks which can be remapped as needed. This is required for the MZ80B emulation where memory changes location according to mode.
Z80_ADDR : inout std_logic_vector(15 downto 0);
Z80_DATA : inout std_logic_vector( 7 downto 0);
@@ -96,7 +100,6 @@ entity cpld512 is
CTL_RFSHn : out std_logic;
CTL_WAITn : in std_logic;
SVCREQn : out std_logic;
Z80_MEM : out std_logic_vector(4 downto 0);
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
SYS_BUSACKn : out std_logic;
@@ -122,13 +125,13 @@ entity cpld512 is
VIDEO_WRn : out std_logic;
-- FPGA control signals muxed with Graphics signals from the mainboard.
VWAITn_V_CSYNC : inout std_logic; -- Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_RFSHn_V_HSYNC : inout std_logic; -- Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_HALTn_V_VSYNC : inout std_logic; -- Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VWAITn_A21_V_CSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_A20_RFSHn_V_HSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_A19_HALTn_V_VSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VZ80_BUSRQn_V_G : out std_logic; -- Voltage translated Z80 BUSRQ / Mainboard Video Green signal.
VZ80_WAITn_V_B : out std_logic; -- Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_INTn_V_R : out std_logic; -- Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_NMIn_V_COLR : out std_logic; -- Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
VZ80_A16_WAITn_V_B : out std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_A18_INTn_V_R : out std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_A17_NMIn_V_COLR : out std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
CSYNC_IN : in std_logic; -- Mainboard Video Composite Sync.
HSYNC_IN : in std_logic; -- Mainboard Video Horizontal Sync.
VSYNC_IN : in std_logic; -- Mainboard Video Vertical Sync.
@@ -222,7 +225,8 @@ architecture rtl of cpld512 is
signal VZ80_A18_INTn : std_logic; -- Multi-function, normally INTn to the soft CPU but VZ80_A18 during K64F access.
signal VZ80_A17_NMIn : std_logic; -- Multi-function, normally NMIn to the soft CPU but VZ80_A17 during K64F access.
signal VZ80_A16_WAITn : std_logic; -- Multi-function, normally WAITn to the soft CPU but VZ80_A16 during K64F access.
signal CPLD_HI_ADDR : std_logic_vector(18 downto 16); -- Tri-state ability on upper address bits.
signal VZ80_HI_ADDR : std_logic_vector(23 downto 16); -- Upper address bits on FPGA side.
signal CPLD_HI_ADDR : std_logic_vector(23 downto 16); -- Tri-state ability on upper address bits.
signal CPLD_RA_ADDR : std_logic_vector(15 downto 12); -- Address lines 15:12 to the RAM are reconfigurable to allow different memory organisation.
signal CPLD_ADDR : std_logic_vector(15 downto 0); --
signal CPLD_DATA_IN : std_logic_vector(7 downto 0); --
@@ -234,7 +238,9 @@ architecture rtl of cpld512 is
signal CPLD_M1n : std_logic; --
signal CPLD_RFSHn : std_logic; --
signal CPLD_HALTn : std_logic; --
signal CTL_BUSRQni : std_logic; --
signal CTL_BUSACKni : std_logic; --
signal CTL_BUSGRANTn : std_logic; --
-- RAM select and write signals.
signal RAM_OEni : std_logic;
@@ -286,14 +292,16 @@ begin
-- [4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
-- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there
-- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator.
-- [7] - R/W - Preserve configuration over reset (=1) or set to default on reset (=0).
--
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPU_CFGn, CS_CPLD_CFGn, CPLD_ADDR, CPLD_DATA_IN )
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPU_CFGn, CS_CPLD_CFGn, CPLD_ADDR, CPLD_DATA_IN, CPLD_CFG_DATA, CPU_CFG_DATA )
begin
if(Z80_RESETn = '0') then
MODE_CPLD_SWITCH <= '0';
CPLD_CFG_DATA <= "00000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
CPU_CFG_DATA(7 downto 6) <= "00"; -- Dont reset soft CPU selection flag on a reset.
if CPLD_CFG_DATA(7) = '0' or CPU_CFG_DATA(5 downto 0) = "000000" then
CPLD_CFG_DATA <= "10000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
end if;
elsif(rising_edge(Z80_CLKi)) then
@@ -303,7 +311,7 @@ begin
-- Store the new value into the register, used for read operations.
CPU_CFG_DATA <= CPLD_DATA_IN;
-- Check to ensure only one CPU selected, if more than one default to hard CPU. Also check to ensure only instantiated CPU's selected, otherwise default to hard CPU.
-- Check to ensure only one CPU selected, if more than one default to hard CPU.
--
if (unsigned(CPLD_DATA_IN(5 downto 0)) and (unsigned(CPLD_DATA_IN(5 downto 0))-1)) /= 0 or (CPLD_DATA_IN(5 downto 2) and "1111") /= "0000" then
CPU_CFG_DATA(5 downto 0) <= (others => '0');
@@ -327,7 +335,7 @@ begin
-- Memory mode latch. This latch stores the current memory mode (or Bank Paging Scheme) according to the running software.
--
MEMORYMODE: process( Z80_CLKi, Z80_RESETn, CS_MEM_CFGn, VZ80_MREQn, VZ80_IORQn, VZ80_BUSACKn, CPLD_IORQn, CPLD_WRn, CPLD_ADDR, CPLD_DATA_IN, CPU_CFG_DATA, MODE_CPU_SOFT )
MEMORYMODE: process( Z80_CLKi, Z80_RESETn, CS_MEM_CFGn, MODE_CPU_SOFT, VZ80_IORQn, VZ80_MREQn, VZ80_M1n, CTL_BUSACKni, CPLD_IORQn, CPLD_WRn, CPLD_ADDR, CPLD_DATA_IN, CPU_CFG_DATA )
variable mz700_LOWER_RAM : std_logic;
variable mz700_UPPER_RAM : std_logic;
variable mz700_INHIBIT : std_logic;
@@ -336,18 +344,28 @@ begin
if(Z80_RESETn = '0') then
-- Initialise memory mode if running on hard cpu, soft cpu remains on current selection.
MEM_MODE_LATCH <= "00000";
-- If a soft CPU is running, force the reset memory mode to TZMM_TZFS - this is to accommodate the Z80 which runs original software. For alternate processors it is still
-- important they can access the 512K RAM in case they boot out of it but there coding should change the memory mode to one more suited for its requirements.
if MODE_CPU_SOFT = '1' then
MEM_MODE_LATCH(1) <= '1';
end if;
mz700_LOWER_RAM := '0';
mz700_UPPER_RAM := '0';
mz700_INHIBIT := '0';
-- Special case for soft CPU's wanting to address the entire 512k RAM or the 64K address space of the mainboard. The MREQn and IORQn are held low and data[7] and data[2:0] indicate required memory access.
-- data[7] = 1 - Access 64K address space of mainboard. data[7] = 0 - Access 512K RAM with high address bits stored in data[2:0]. These bits are mapped into a memory mode
-- and the memory management logic handles any future requests accordingly.
elsif (VZ80_MREQn = '0' and VZ80_IORQn = '0' and MODE_CPU_SOFT = '1' and VZ80_BUSACKn = '1') then
-- Special case for soft CPU's wanting to address the entire 16M address space (currently 512 RAM) or the 64K address space of the mainboard.
-- Using the IORQ, HMREQ and M1 signals out of the FPGA when in FPGA video mode (including soft cpu mode) in various non standard combinations we latch the upper address
-- or the fixed mainboard access modes.
-- IORQ = '0', MREQ = '0', M1 = '1' latch data to memory mode, [7] = 1 - Access 64K address space of mainboard. [7] = 0
-- IORQ = '0', MREQ = '0', M1 = '0' latch the upper address bits [23:16]. This allows access to the full 16M address space, currently only 512K is populated.
elsif (MODE_CPU_SOFT = '1' and VZ80_IORQn = '0' and VZ80_MREQn = '0' and VZ80_M1n = '0' and CTL_BUSACKni = '1') then
VZ80_HI_ADDR <= CPLD_DATA_IN;
MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_TZPU, 5));
elsif (MODE_CPU_SOFT = '1' and VZ80_IORQn = '0' and VZ80_MREQn = '0' and VZ80_M1n = '1' and CTL_BUSACKni = '1') then
if CPLD_DATA_IN(7) = '1' then
MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_TZPUM, 5));
else
MEM_MODE_LATCH <= "11" & CPLD_DATA_IN(2 downto 0);
end if;
-- A direct write to the memory latch stores the required memory mode into the latch.
@@ -603,7 +621,7 @@ begin
-- 12 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
-- 13 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
-- 14 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
-- 21 - Access the FPGA memory by passing through the full 19bit Z80 address, typically from the K64F.
-- 21 - Access the FPGA memory by passing through the full 24bit Z80 address, typically from the K64F.
-- 22 - Access to the host mainboard 64K address space only.
-- 23 - Access all memory and IO on the tranZPUter board with the K64F addressing the full 512K RAM.
-- 24 - All memory and IO are on the tranZPUter board, 64K block 0 selected.
@@ -614,7 +632,7 @@ begin
-- 29 - All memory and IO are on the tranZPUter board, 64K block 5 selected.
-- 30 - All memory and IO are on the tranZPUter board, 64K block 6 selected.
-- 31 - All memory and IO are on the tranZPUter board, 64K block 7 selected.
MEMORYMGMT: process(CPLD_ADDR, CPLD_WRn, CPLD_RDn, CPLD_IORQn, CPLD_MREQn, CPLD_M1n, Z80_HI_ADDR, MEM_MODE_LATCH, SYS_BUSACKni, CS_VIDEOn, CS_VIDEO_IOn, CS_IO_DXXn, CS_IO_EXXn, CS_IO_FXXn, CS_CPU_CFGn, CS_CPU_INFOn, MODE_CPLD_MB_VIDEOn)
MEMORYMGMT: process(CPLD_ADDR, CPLD_WRn, CPLD_RDn, CPLD_IORQn, CPLD_MREQn, CPLD_M1n, Z80_HI_ADDR, VZ80_HI_ADDR, MEM_MODE_LATCH, SYS_BUSACKni, CS_VIDEOn, CS_VIDEO_IOn, CS_IO_DXXn, CS_IO_EXXn, CS_IO_FXXn, CS_CPU_CFGn, CS_CPU_INFOn, MODE_CPLD_MB_VIDEOn)
begin
-- Memory action according to the configured memory mode. Not synchronous as we need to detect and act on address or signals long before a rising edge.
@@ -624,7 +642,7 @@ begin
-- Set 0 - default, no tranZPUter RAM access so hold the DISABLE_BUS signal inactive to ensure the CPU has continuous access to the
-- mainboard resources, especially for Refresh of DRAM.
when TZMM_ORIG =>
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '1';
RAM_WEni <= '1';
@@ -641,7 +659,7 @@ begin
when TZMM_BOOT =>
RAM_CSni <= '0';
CS_VIDEO_MEMn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
if CS_VIDEOn = '0' then
DISABLE_BUSn <= '0';
@@ -670,7 +688,7 @@ begin
when TZMM_TZFS =>
RAM_CSni <= '0';
CS_VIDEO_MEMn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
if CS_VIDEOn = '0' then
@@ -702,7 +720,7 @@ begin
if CS_VIDEOn = '0' then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -710,7 +728,7 @@ begin
elsif(((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000") or (unsigned(CPLD_ADDR(15 downto 0)) >= X"E800" and unsigned(CPLD_ADDR(15 downto 0)) < X"F000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
if unsigned(CPLD_ADDR(15 downto 0)) = X"E800" then
@@ -721,14 +739,14 @@ begin
elsif (unsigned(CPLD_ADDR(15 downto 0)) >= X"F000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF" and not std_match(CPLD_ADDR(15 downto 1), "11110-111111111")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "001";
CPLD_HI_ADDR <= "00000001";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -742,7 +760,7 @@ begin
if CS_VIDEOn = '0' then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -750,7 +768,7 @@ begin
elsif( ((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000") or (unsigned(CPLD_ADDR(15 downto 0)) >= X"E800" and unsigned(CPLD_ADDR(15 downto 0)) < X"F000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
if unsigned(CPLD_ADDR(15 downto 0)) = X"E800" then
@@ -761,14 +779,14 @@ begin
elsif((unsigned(CPLD_ADDR(15 downto 0)) >= X"F000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "010";
CPLD_HI_ADDR <= "00000010";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -782,7 +800,7 @@ begin
if CS_VIDEOn = '0' then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -790,7 +808,7 @@ begin
elsif( ((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000") or (unsigned(CPLD_ADDR(15 downto 0)) >= X"E800" and unsigned(CPLD_ADDR(15 downto 0)) < X"F000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
if unsigned(CPLD_ADDR(15 downto 0)) = X"E800" then
@@ -801,14 +819,14 @@ begin
elsif((unsigned(CPLD_ADDR(15 downto 0)) >= X"F000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "011";
CPLD_HI_ADDR <= "00000011";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -822,14 +840,14 @@ begin
if (unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF" and not std_match(CPLD_ADDR(15 downto 1), "11110-111111111")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "100";
CPLD_HI_ADDR <= "00000100";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -844,7 +862,7 @@ begin
if CS_VIDEOn = '0' then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -852,21 +870,21 @@ begin
elsif ((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"0100") or (unsigned(CPLD_ADDR(15 downto 0)) >= X"F000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF" and not std_match(CPLD_ADDR(15 downto 1), "11110-111111111"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "100";
CPLD_HI_ADDR <= "00000100";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif(((unsigned(CPLD_ADDR(15 downto 0)) >= X"0100" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000") or (unsigned(CPLD_ADDR(15 downto 0)) >= X"E800" and unsigned(CPLD_ADDR(15 downto 0)) < X"F000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "101";
CPLD_HI_ADDR <= "00000101";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -877,7 +895,7 @@ begin
when TZMM_COMPAT =>
RAM_CSni <= '0';
CS_VIDEO_MEMn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
if CS_VIDEOn = '0' then
@@ -904,7 +922,7 @@ begin
if CS_VIDEOn = '0' then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -912,21 +930,21 @@ begin
elsif(((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"1000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "110";
CPLD_HI_ADDR <= "00000110";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif((unsigned(CPLD_ADDR(15 downto 0)) >= X"1000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -939,28 +957,28 @@ begin
if(((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"1000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif((unsigned(CPLD_ADDR(15 downto 0)) >= X"1000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif(((unsigned(CPLD_ADDR(15 downto 0)) >= X"D000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "110";
CPLD_HI_ADDR <= "00000110";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -973,28 +991,28 @@ begin
if(((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"1000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "110";
CPLD_HI_ADDR <= "00000110";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif((unsigned(CPLD_ADDR(15 downto 0)) >= X"1000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif(((unsigned(CPLD_ADDR(15 downto 0)) >= X"D000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "110";
CPLD_HI_ADDR <= "00000110";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -1007,28 +1025,28 @@ begin
if(((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"1000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif((unsigned(CPLD_ADDR(15 downto 0)) >= X"1000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif(((unsigned(CPLD_ADDR(15 downto 0)) >= X"D000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF"))) then
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
@@ -1041,46 +1059,45 @@ begin
if(((unsigned(CPLD_ADDR(15 downto 0)) >= X"0000" and unsigned(CPLD_ADDR(15 downto 0)) < X"1000"))) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "110";
CPLD_HI_ADDR <= "00000110";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif((unsigned(CPLD_ADDR(15 downto 0)) >= X"1000" and unsigned(CPLD_ADDR(15 downto 0)) < X"D000")) then
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_OEni <= CPLD_RDn;
RAM_WEni <= CPLD_WRn;
elsif(((unsigned(CPLD_ADDR(15 downto 0)) >= X"D000" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF"))) then
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
else
DISABLE_BUSn <= '1';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_WEni <= '1';
RAM_OEni <= '1';
end if;
-- Set 21 - Access the FPGA memory by passing through the full 19bit Z80 address, typically from the K64F.
-- Set 21 - Access the FPGA memory by passing through the full 24bit Z80 address, typically from the K64F.
when TZMM_FPGA =>
CPLD_HI_ADDR <= "000"; -- Hi bits directly driven by external source, ie. K64F in this mode.
DISABLE_BUSn <= '0';
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '1';
RAM_WEni <= '1';
RAM_OEni <= '1';
CS_VIDEO_MEMn <= '1';
DISABLE_BUSn <= '0';
-- Set 22 - Access to the host mainboard 64K address space.
when TZMM_TZPUM =>
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '1';
RAM_WEni <= '1';
@@ -1091,7 +1108,7 @@ begin
-- Set 23 - Access all memory and IO on the tranZPUter board with the K64F addressing the full 512K RAM.
when TZMM_TZPU =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000"; -- Hi bits directly driven by external source, ie. K64F in this mode.
CPLD_HI_ADDR <= VZ80_HI_ADDR; -- Hi bits directly driven by external source, ie. FPGA soft cpu in this mode.
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1101,7 +1118,7 @@ begin
-- Set 24 - All memory and IO are on the tranZPUter board, 64K block 0 selected.
when TZMM_TZPU0 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1111,7 +1128,7 @@ begin
-- Set 25 - All memory and IO are on the tranZPUter board, 64K block 1 selected.
when TZMM_TZPU1 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "001";
CPLD_HI_ADDR <= "00000001";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1121,7 +1138,7 @@ begin
-- Set 26 - All memory and IO are on the tranZPUter board, 64K block 2 selected.
when TZMM_TZPU2 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "010";
CPLD_HI_ADDR <= "00000010";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1131,7 +1148,7 @@ begin
-- Set 27 - All memory and IO are on the tranZPUter board, 64K block 3 selected.
when TZMM_TZPU3 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "011";
CPLD_HI_ADDR <= "00000011";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1141,7 +1158,7 @@ begin
-- Set 28 - All memory and IO are on the tranZPUter board, 64K block 4 selected.
when TZMM_TZPU4 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "100";
CPLD_HI_ADDR <= "00000100";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1151,7 +1168,7 @@ begin
-- Set 29 - All memory and IO are on the tranZPUter board, 64K block 5 selected.
when TZMM_TZPU5 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "101";
CPLD_HI_ADDR <= "00000101";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1161,7 +1178,7 @@ begin
-- Set 30 - All memory and IO are on the tranZPUter board, 64K block 6 selected.
when TZMM_TZPU6 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "110";
CPLD_HI_ADDR <= "00000110";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1171,7 +1188,7 @@ begin
-- Set 31 - All memory and IO are on the tranZPUter board, 64K block 7 selected.
when TZMM_TZPU7 =>
DISABLE_BUSn <= '0';
CPLD_HI_ADDR <= "111";
CPLD_HI_ADDR <= "00000111";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '0';
RAM_OEni <= CPLD_RDn;
@@ -1180,7 +1197,7 @@ begin
-- Uncoded modes default to the original machine settings.
when others =>
CPLD_HI_ADDR <= "000";
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
RAM_CSni <= '1';
RAM_WEni <= '1';
@@ -1220,8 +1237,27 @@ begin
end if;
end process;
-- Latch output so the K64F can determine current status.
Z80_MEM <= MEM_MODE_LATCH(4 downto 0);
-- A process to bring the external K64F control signals into this domain. The K64F can request the bus asynchronously so it is important the system state is known before
-- passing the request onto the internal processes and FPGA.
--
SIGNALSYNC: process( Z80_CLKi, Z80_RESETn, CTL_BUSRQn )
begin
if(Z80_RESETn = '0') then
CTL_BUSRQni <= '1';
elsif rising_edge(Z80_CLKi) then
-- When a Bus request comes in, ensure that the state is idle before passing it on as this signal is used to enable/disable or mux control other signals.
if CTL_BUSRQn = '0' and MODE_CPU_SOFT = '1' then
CTL_BUSRQni <= '0';
elsif CTL_BUSRQn = '0' and MODE_CPU_SOFT = '0' then
CTL_BUSRQni <= '0';
end if;
if CTL_BUSRQn = '1' then
CTL_BUSRQni <= '1';
end if;
end if;
end process;
-- Clock frequency switching. Depending on the state of the flip flops either the system (mainboard) clocks is selected (default and selected when accessing
-- the mainboard) and the programmable frequency generated by the K64F timers.
@@ -1229,9 +1265,15 @@ begin
Z80_CLK <= Z80_CLKi;
-- Wait states, added by the mainboard video circuitry, FPGA video circuitry or the K64F.
Z80_WAITn <= '0' when MODE_CPU_SOFT = '0' and CTL_BUSRQn = '1' and (SYS_WAITn = '0' or CTL_WAITn = '0' or ((VWAITn = '0' and MODE_CPLD_MB_VIDEOn = '1') and MODE_CPLD_VIDEO_WAIT = '1'))
Z80_WAITn <= '0' when MODE_CPU_SOFT = '0' and (SYS_WAITn = '0' and DISABLE_BUSn = '1')
else
'1' when MODE_CPU_SOFT = '0' and CTL_BUSRQn = '1' and SYS_WAITn = '1' and CTL_WAITn = '1' and (VWAITn = '1' or MODE_CPLD_MB_VIDEOn = '0')
'0' when MODE_CPU_SOFT = '0' and CTL_BUSRQni = '1' and ((VWAITn = '0' and MODE_CPLD_MB_VIDEOn = '1') and MODE_CPLD_VIDEO_WAIT = '1')
else
'0' when CTL_WAITn = '0'
else
'1' when MODE_CPU_SOFT = '0' and (SYS_WAITn = '1' and DISABLE_BUSn = '1')
else
'1' when MODE_CPU_SOFT = '0' and CTL_BUSRQni = '1' and (VWAITn = '1' or MODE_CPLD_MB_VIDEOn = '0')
else 'Z';
-- Z80 signals passed to the mainboard, if the K64F has control of the bus then the Z80 signals are disabled as they are not tri-stated during a BUSRQ state.
@@ -1242,24 +1284,26 @@ begin
CTL_HALTn <= CPLD_HALTn when Z80_BUSACKn = '1'
else 'Z';
-- Bus control logic, SYS_BUSACKni directly controls the mainboard tri-state buffers, enabling will disable the mainboard..
-- Bus control logic, SYS_BUSACKni directly controls the mainboard tri-state buffers, enabling will disable the mainboard.
SYS_BUSACKni <= '0' when DISABLE_BUSn = '0' or (Z80_BUSACKn = '0' and CTL_MBSEL = '0')
else '1';
SYS_BUSACKn <= SYS_BUSACKni;
-- Request hard Z80 bus. SYS_BUSRQ = mainboard requesting bus, CTL_BUSRQ = K64F requesting bus, MODE_CPU_SOFT = when set, soft CPU is running so hard CPU is permanently tri-stated.
Z80_BUSRQn <= '0' when MODE_CPU_SOFT = '1' or SYS_BUSRQn = '0' or CTL_BUSRQn = '0'
Z80_BUSRQn <= '0' when MODE_CPU_SOFT = '1' or SYS_BUSRQn = '0' or CTL_BUSRQni = '0'
else '1';
-- Soft CPU bus request, ie, disable the Soft CPU, whenever enabled and the K64F requests the bus.
VZ80_BUSRQn <= '0' when MODE_CPU_SOFT = '1' and CTL_BUSRQn = '0'
VZ80_BUSRQn <= '0' when MODE_CPLD_MB_VIDEOn='1' and CTL_BUSRQni = '0'
else '1';
-- Acknowlegde to the K64F, if soft CPU is running then the soft CPU must acknowledge otherwise base on the hard Z80 acknowledge.
CTL_BUSACKni <= '0' when MODE_CPU_SOFT = '1' and CTL_BUSRQn = '0' and Z80_BUSACKn = '0' and VZ80_BUSACKn = '0'
CTL_BUSACKni <= '0' when MODE_CPU_SOFT = '1' and CTL_BUSRQni = '0' and Z80_BUSACKn = '0' and VZ80_BUSACKn = '0'
else
'0' when MODE_CPU_SOFT = '0' and CTL_BUSRQn = '0' and Z80_BUSACKn = '0'
'0' when MODE_CPU_SOFT = '0' and CTL_BUSRQni = '0' and Z80_BUSACKn = '0'
else
'1';
CTL_BUSACKn <= CTL_BUSACKni;
CTL_BUSGRANTn <= '0' when CTL_BUSRQni = '0' and VZ80_BUSACKn = '0'
else '1';
-- Register read values.
CLK_STATUS_DATA <= "0000000" & SYSCLK_Q;
@@ -1294,6 +1338,8 @@ begin
else
VZ80_DATA when CS_VIDEO_RDn = '0' and Z80_RDn = '0' -- Read video memory inside FPGA when using FPGA based video.
else
VZ80_DATA when CTL_BUSACKni = '0' and Z80_RDn = '0' and Z80_HI_ADDR(23 downto 19) /= "00000" -- Any memory address outside the first 512K page should be read from the FPGA bus.
else
VZ80_DATA when MODE_CPU_SOFT = '1' and VZ80_WRn = '0' -- Output T80 data to tranZPUter/mainboard when writing and T80 active.
else
(others => 'Z'); -- Default is to tristate the Z80 data bus output when not being used.
@@ -1306,104 +1352,118 @@ begin
else
MEM_MODE_DATA when MODE_CPU_SOFT = '1' and CS_MEM_CFGn = '0' and VZ80_RDn = '0' -- Read the memory mode latch.
else
Z80_DATA when MODE_CPU_SOFT = '1' and CTL_BUSRQn = '1' and VZ80_RDn = '0' -- Copy the Z80 data if being read by the T80.
Z80_DATA when MODE_CPU_SOFT = '1' and CTL_BUSACKni = '1' and VZ80_RDn = '0' -- Copy the Z80 data if being read by the T80.
else
Z80_DATA when MODE_CPU_SOFT = '0' and Z80_WRn = '0' -- Copy the Z80 data if being written by the Z80.
else
Z80_DATA when CTL_BUSRQn = '0' and VZ80_BUSACKn = '0' and Z80_WRn = '0' -- Copy the Z80 data if the K64F is writing on the bus.
Z80_DATA when CTL_BUSRQni = '0' and VZ80_BUSACKn = '0' and Z80_WRn = '0' -- Copy the Z80 data if the K64F is writing on the bus.
else
(others => 'Z'); -- Default is to tristate the VZ80 data bus output when not being used.
-- External/FPGA -> CPLD
CPLD_DATA_IN <= Z80_DATA when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_DATA_IN <= Z80_DATA when MODE_CPU_SOFT = '0' or (CTL_BUSRQni = '0' and VZ80_BUSACKn = '0')
else
VZ80_DATA;
--
-- Core CPLD signals - depending on mode, the control signals are either taken from the hard CPU or soft CPU.
--
CPLD_ADDR <= Z80_ADDR when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_ADDR <= Z80_ADDR when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_ADDR;
CPLD_RDn <= Z80_RDn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_RDn <= Z80_RDn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_RDn;
CPLD_WRn <= Z80_WRn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_WRn <= Z80_WRn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_WRn;
CPLD_MREQn <= Z80_MREQn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_MREQn <= Z80_MREQn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_MREQn;
CPLD_IORQn <= Z80_IORQn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_IORQn <= Z80_IORQn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_IORQn;
CPLD_M1n <= Z80_M1n when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_M1n <= Z80_M1n when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_M1n;
CPLD_RFSHn <= Z80_RFSHn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_RFSHn <= Z80_RFSHn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_RFSHn;
CPLD_HALTn <= Z80_HALTn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
CPLD_HALTn <= Z80_HALTn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else
VZ80_HALTn;
--
-- Address Bus and Control Multiplexing on the hard CPU side.
--
Z80_HI_ADDR <= CPLD_HI_ADDR when CTL_BUSACKni = '1' -- New addition, pass through the upper address bits directly. K64F directly drives A16-A18 to RAM and into CPLD.
Z80_HI_ADDR <= CPLD_HI_ADDR when CTL_BUSACKni = '1' -- New addition, pass through the upper address bits directly. K64F directly drives A16-A23 to RAM and into CPLD.
else (others => 'Z');
Z80_RA_ADDR <= CPLD_RA_ADDR;
Z80_ADDR <= VZ80_ADDR when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1') -- In soft cpu mode, if the K64F hasnt taken control of the bus, always output the soft CPU address.
Z80_RA_ADDR <= CPLD_RA_ADDR; -- Row address, to be used for bank remapping to accommodate machines such as the MZ80B where memory is remapped.
Z80_ADDR <= VZ80_ADDR when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1') -- In soft cpu mode, if the K64F hasnt taken control of the bus, always output the soft CPU address.
else (others => 'Z');
Z80_WRn <= VZ80_WRn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1')
Z80_WRn <= VZ80_WRn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1')
else 'Z';
Z80_RDn <= VZ80_RDn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1')
Z80_RDn <= VZ80_RDn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1')
else 'Z';
Z80_MREQn <= VZ80_MREQn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1')
Z80_MREQn <= '1' when MODE_CPU_SOFT = '1' and VZ80_IORQn = '0' -- Block the IORQ/MREQ low combination going externally.
else
VZ80_MREQn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1')
else 'Z';
Z80_IORQn <= VZ80_IORQn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1')
Z80_IORQn <= '1' when MODE_CPU_SOFT = '1' and VZ80_MREQn = '0' -- Block the IORQ/MREQ low combination going externally.
else
VZ80_IORQn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1')
else 'Z';
Z80_RFSHn <= VZ80_RFSHn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1')
Z80_RFSHn <= VZ80_RFSHn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1')
else 'Z';
Z80_M1n <= VZ80_M1n when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1')
Z80_M1n <= VZ80_M1n when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1')
else 'Z';
Z80_HALTn <= VZ80_HALTn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and CTL_BUSRQn = '1')
Z80_HALTn <= VZ80_HALTn when MODE_CPU_SOFT = '1' and (Z80_BUSACKn = '0' and VZ80_BUSACKn = '1')
else 'Z';
--
-- Address Bus and Control Multiplexing on the soft CPU (FPGA) side.
--
VZ80_ADDR <= Z80_ADDR(15 downto 0) when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_ADDR <= Z80_ADDR(15 downto 0) when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else (others => 'Z');
VZ80_MREQn <= Z80_MREQn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_MREQn <= Z80_MREQn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else 'Z';
VZ80_IORQn <= Z80_IORQn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_IORQn <= Z80_IORQn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else 'Z';
VZ80_RDn <= Z80_RDn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_RDn <= Z80_RDn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else 'Z';
VZ80_WRn <= Z80_WRn when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_WRn <= Z80_WRn when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else 'Z';
VZ80_M1n <= Z80_M1n when MODE_CPU_SOFT = '0' or (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_M1n <= Z80_M1n when MODE_CPU_SOFT = '0' or CTL_BUSGRANTn = '0'
else 'Z';
-- Z80 control signals, enabled when the FPGA video is enabled, the signals share the same physical wire as the mainboard video signals and
-- when the FPGA video is used the mainboard video signals are not needed.
VWAITn <= VWAITn_A21_V_CSYNC when MODE_CPLD_MB_VIDEOn = '1' and CTL_BUSACKni = '1' -- VWAITn signal output by FPGA during access to memory during Framebuffer rendering.
else '1';
VZ80_RFSHn <= VZ80_A20_RFSHn_V_HSYNC when MODE_CPLD_MB_VIDEOn = '1' and CTL_BUSACKni = '1' -- Z80 RFSH signal output by soft CPU.
else '1';
VZ80_HALTn <= VZ80_A19_HALTn_V_VSYNC when MODE_CPLD_MB_VIDEOn = '1' and CTL_BUSACKni = '1' -- Z80 HALT signal output by soft CPU.
else '1';
-- Inputs, they share signal lines with the mainboard video and K64F addressing, so only route them if a soft CPU in the FPGA is enabled (which also implies FPGA video is in use).
VZ80_A16_WAITn <= Z80_HI_ADDR(16) when MODE_CPU_SOFT = '1' and (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_A16_WAITn <= Z80_WAITn when MODE_CPU_SOFT = '1' and CTL_BUSACKni = '1'
else
Z80_WAITn when MODE_CPU_SOFT = '1' and CTL_BUSRQn = '1'
Z80_HI_ADDR(16) when CTL_BUSACKni = '0'
else '1';
VZ80_A17_NMIn <= Z80_HI_ADDR(17) when MODE_CPU_SOFT = '1' and (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_A17_NMIn <= Z80_NMIn when MODE_CPU_SOFT = '1' and CTL_BUSACKni = '1'
else
Z80_NMIn when MODE_CPU_SOFT = '1' and CTL_BUSRQn = '1'
Z80_HI_ADDR(17) when CTL_BUSACKni = '0'
else '1';
VZ80_A18_INTn <= Z80_HI_ADDR(18) when MODE_CPU_SOFT = '1' and (CTL_BUSRQn = '0' and VZ80_BUSACKn = '0')
VZ80_A18_INTn <= Z80_INTn when MODE_CPU_SOFT = '1' and CTL_BUSACKni = '1'
else
Z80_INTn when MODE_CPU_SOFT = '1' and CTL_BUSRQn = '1'
Z80_HI_ADDR(18) when CTL_BUSACKni = '0'
else '1';
-- Clock, route the clock which is composed of the hard CPU mainboard clock and the K64F secondary clock. The T80 will be clocked with this clock.
VZ80_CLK <= Z80_CLKi;
-- Video Read/Write signals. Enabled whenever the video controller is selected. When both VIDEO RDn/WRn are low (an impossible state under normal conditions), a reset is triggered inside the FPGA.
@@ -1453,7 +1513,7 @@ begin
else '1';
CS_SCK_RDn <= '0' when CS_IO_6XXn = '0' and CPLD_ADDR(3 downto 1) = "011" -- IO 66
else '1';
SVCREQn <= '0' when CS_IO_6XXn = '0' and CPLD_ADDR(3 downto 1) = "100" -- IO 68
SVCREQn <= '0' when CS_IO_6XXn = '0' and CPLD_ADDR(3 downto 1) = "100" and CPLD_WRn = '0' -- IO 68
else '1';
CS_CPU_CFGn <= '0' when CS_IO_6XXn = '0' and CPLD_ADDR(3 downto 0) = "1100" -- IO 6C
else '1';
@@ -1492,15 +1552,14 @@ begin
CS_FB_PAGEn <= '0' when CS_IO_FXXn = '0' and CPLD_ADDR(3 downto 0) = "1101"
else '1';
-- Flag to indicate Soft CPU is running,
MODE_CPU_SOFT <= '1' when CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Set the video wait state generator, 0 = disabled, 1 = enabled.
MODE_CPLD_VIDEO_WAIT <= CPLD_CFG_DATA(4);
-- Set the mainboard video state, 0 = enabled, 1 = disabled. Signal set to enabled if the soft cpu is enabled.
MODE_CPLD_MB_VIDEOn <= '1' when CPLD_CFG_DATA(3) = '1' or CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Flag to indicate Soft CPU is running,
MODE_CPU_SOFT <= '1' when CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Set CPLD mode flag according to value given in config 2:0
MODE_CPLD_MZ80K <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80K
else '0';
@@ -1519,33 +1578,31 @@ begin
MODE_CPLD_MZ2000 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ2000
else '0';
-- Graphics signal out, enabled when the FPGA video is disabled.
VWAITn_V_CSYNC <= CSYNC_IN when MODE_CPLD_MB_VIDEOn = '0' -- Composite sync from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
VWAITn_A21_V_CSYNC <= CSYNC_IN when MODE_CPLD_MB_VIDEOn = '0' -- Composite sync from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
else
Z80_HI_ADDR(21) when CTL_BUSACKni = '0'
else 'Z';
VZ80_RFSHn_V_HSYNC <= HSYNC_IN when MODE_CPLD_MB_VIDEOn = '0' -- Horizontal sync from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
VZ80_A20_RFSHn_V_HSYNC<= HSYNC_IN when MODE_CPLD_MB_VIDEOn = '0' -- Horizontal sync from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
else
Z80_HI_ADDR(20) when CTL_BUSACKni = '0'
else 'Z';
VZ80_HALTn_V_VSYNC <= VSYNC_IN when MODE_CPLD_MB_VIDEOn = '0' -- Vertical sync from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
VZ80_A19_HALTn_V_VSYNC<= VSYNC_IN when MODE_CPLD_MB_VIDEOn = '0' -- Vertical sync from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
else
Z80_HI_ADDR(19) when CTL_BUSACKni = '0'
else 'Z';
VZ80_BUSRQn_V_G <= G_IN when MODE_CPLD_MB_VIDEOn = '0' -- Green video from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
else
VZ80_BUSRQn; -- Z80 BUSRQ generated by CPLD to tri-state the soft CPU.
VZ80_WAITn_V_B <= B_IN when MODE_CPLD_MB_VIDEOn = '0' -- Blue video from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
VZ80_A16_WAITn_V_B <= B_IN when MODE_CPLD_MB_VIDEOn = '0' -- Blue video from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
else
VZ80_A16_WAITn; -- Z80 WAIT generated by system or CPLD to force the soft CPU to wait and VZ80_A16 from the K64F during memory access.
VZ80_NMIn_V_COLR <= COLR_IN when MODE_CPLD_MB_VIDEOn = '0' -- Colour modulation frequency for generation of external composite video and RF signals.
VZ80_A17_NMIn_V_COLR <= COLR_IN when MODE_CPLD_MB_VIDEOn = '0' -- Colour modulation frequency for generation of external composite video and RF signals.
else
VZ80_A17_NMIn; -- Z80 NMI generated by external sources to interrupt the soft CPU and VZ80_A17 from the K64F during memory access.
VZ80_INTn_V_R <= R_IN when MODE_CPLD_MB_VIDEOn = '0' -- Red video from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
VZ80_A18_INTn_V_R <= R_IN when MODE_CPLD_MB_VIDEOn = '0' -- Red video from mainboard to the FPGA which then outputs to the external devices if FPGA video disabled.
else
VZ80_A18_INTn; -- Z80 INT generated by external sources to interrupt the soft CPU and VZ80_A18 from the K64F during memory access.
-- Z80 control signals, enabled when the FPGA video is enabled, the signals share the same physical wire as the mainboard video signals and
-- when the FPGA video is used the mainboard video signals are not needed.
VWAITn <= VWAITn_V_CSYNC when MODE_CPLD_MB_VIDEOn = '1' -- VWAITn signal output by FPGA during access to memory during Framebuffer rendering.
else '1';
VZ80_RFSHn <= VZ80_RFSHn_V_HSYNC when MODE_CPLD_MB_VIDEOn = '1' -- Z80 RFSH signal output by soft CPU.
else '1';
VZ80_HALTn <= VZ80_HALTn_V_VSYNC when MODE_CPLD_MB_VIDEOn = '1' -- Z80 HALT signal output by soft CPU.
else '1';
end architecture;

28
CPLD/SW700/v1.3/tranZPUterSW700_Toplevel.vhd
View File

@@ -45,7 +45,7 @@ use altera.altera_syn_attributes.all;
entity tranZPUterSW700 is
port (
-- Z80 Address and Data.
Z80_HI_ADDR : inout std_logic_vector(18 downto 16); -- Hi address. These are the upper bank bits allowing 512K of address space. They are directly set by the K64F when accessing RAM or FPGA and set by the FPGA according to memory mode.
Z80_HI_ADDR : inout std_logic_vector(23 downto 16); -- Hi address. These are the upper bank bits allowing 512K of address space. They are directly set by the K64F when accessing RAM or FPGA and set by the FPGA according to memory mode.
Z80_RA_ADDR : out std_logic_vector(15 downto 12); -- Row address - RAM is subdivided into 4K blocks which can be remapped as needed. This is required for the MZ80B emulation where memory changes location according to mode.
Z80_ADDR : inout std_logic_vector(15 downto 0);
Z80_DATA : inout std_logic_vector(7 downto 0);
@@ -75,7 +75,6 @@ entity tranZPUterSW700 is
CTL_RFSHn : out std_logic;
CTL_WAITn : in std_logic;
SVCREQn : out std_logic;
Z80_MEM : out std_logic_vector(4 downto 0);
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
SYS_BUSACKn : out std_logic;
@@ -101,13 +100,13 @@ entity tranZPUterSW700 is
VIDEO_WRn : out std_logic;
-- FPGA control signals muxed with Graphics signals from the mainboard.
VWAITn_V_CSYNC : inout std_logic; -- Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_RFSHn_V_HSYNC : inout std_logic; -- Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_HALTn_V_VSYNC : inout std_logic; -- Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VWAITn_A21_V_CSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_A20_RFSHn_V_HSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_A19_HALTn_V_VSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VZ80_BUSRQn_V_G : out std_logic; -- Voltage translated Z80 BUSRQ / Mainboard Video Green signal.
VZ80_WAITn_V_B : out std_logic; -- Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_INTn_V_R : out std_logic; -- Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_NMIn_V_COLR : out std_logic; -- Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
VZ80_A16_WAITn_V_B : out std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_A18_INTn_V_R : out std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_A17_NMIn_V_COLR : out std_logic; -- Upper address bit for access to FPGA resources / Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
CSYNC_IN : in std_logic; -- Mainboard Video Composite Sync.
HSYNC_IN : in std_logic; -- Mainboard Video Horizontal Sync.
VSYNC_IN : in std_logic; -- Mainboard Video Vertical Sync.
@@ -162,7 +161,6 @@ begin
CTL_RFSHn => CTL_RFSHn,
CTL_WAITn => CTL_WAITn,
SVCREQn => SVCREQn,
Z80_MEM => Z80_MEM,
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
SYS_BUSACKn => SYS_BUSACKn,
@@ -188,13 +186,13 @@ begin
VIDEO_WRn => VIDEO_WRn,
-- FPGA control signals muxed with Graphics signals from the mainboard.
VWAITn_V_CSYNC => VWAITn_V_CSYNC, -- Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_RFSHn_V_HSYNC => VZ80_RFSHn_V_HSYNC, -- Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_HALTn_V_VSYNC => VZ80_HALTn_V_VSYNC, -- Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VWAITn_A21_V_CSYNC => VWAITn_A21_V_CSYNC, -- Upper address bit for access to FPGA resources / Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_A20_RFSHn_V_HSYNC => VZ80_A20_RFSHn_V_HSYNC, -- Upper address bit for access to FPGA resources / Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_A19_HALTn_V_VSYNC => VZ80_A19_HALTn_V_VSYNC, -- Upper address bit for access to FPGA resources / Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VZ80_BUSRQn_V_G => VZ80_BUSRQn_V_G, -- Voltage translated Z80 BUSRQ / Mainboard Video Green signal.
VZ80_WAITn_V_B => VZ80_WAITn_V_B, -- Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_INTn_V_R => VZ80_INTn_V_R, -- Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_NMIn_V_COLR => VZ80_NMIn_V_COLR, -- Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
VZ80_A16_WAITn_V_B => VZ80_A16_WAITn_V_B, -- Upper address bit for access to FPGA resources / Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_A18_INTn_V_R => VZ80_A18_INTn_V_R, -- Upper address bit for access to FPGA resources / Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_A17_NMIn_V_COLR => VZ80_A17_NMIn_V_COLR, -- Upper address bit for access to FPGA resources / Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
CSYNC_IN => CSYNC_IN, -- Mainboard Video Composite Sync.
HSYNC_IN => HSYNC_IN, -- Mainboard Video Horizontal Sync.
VSYNC_IN => VSYNC_IN, -- Mainboard Video Vertical Sync.

4
CPLD/SW700/v1.3/tranZPUterSW700_pkg.vhd
View File

@@ -102,9 +102,9 @@ package tranZPUterSW700_pkg is
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
constant CPLD_VERSION : integer := 2;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
-- Clock source for the secondary clock. If a K64F is installed then enable it otherwise use the onboard oscillator.
--
constant USE_K64F_CTL_CLOCK : integer := 1;

0
FPGA/SW700/v1.3/build/Video_Clock.cmp → FPGA/SW700/v1.3/PLL/Video_Clock.cmp
View File

0
FPGA/SW700/v1.3/build/Video_Clock.ppf → FPGA/SW700/v1.3/PLL/Video_Clock.ppf
View File

2
FPGA/SW700/v1.3/build/Video_Clock.qip → FPGA/SW700/v1.3/PLL/Video_Clock.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock.cmp"]

6
FPGA/SW700/v1.3/build/Video_Clock.vhd → FPGA/SW700/v1.3/PLL/Video_Clock.vhd
View File

@@ -14,7 +14,7 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
@@ -318,7 +318,7 @@ END SYN;
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
@@ -370,7 +370,7 @@ END SYN;
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "694"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"

0
FPGA/SW700/v1.3/build/Video_Clock_II.cmp → FPGA/SW700/v1.3/PLL/Video_Clock_II.cmp
View File

0
FPGA/SW700/v1.3/build/Video_Clock_II.ppf → FPGA/SW700/v1.3/PLL/Video_Clock_II.ppf
View File

3
FPGA/SW700/v1.3/build/Video_Clock_II.qip → FPGA/SW700/v1.3/PLL/Video_Clock_II.qip
View File

@@ -1,5 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_II.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II.cmp"]

2
FPGA/SW700/v1.3/build/Video_Clock_II.vhd → FPGA/SW700/v1.3/PLL/Video_Clock_II.vhd
View File

@@ -156,7 +156,7 @@ BEGIN
clk1_multiply_by => 5051,
clk1_phase_shift => "0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_II",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",

1
FPGA/SW700/v1.3/build/Video_Clock_III.cmp → FPGA/SW700/v1.3/PLL/Video_Clock_III.cmp
View File

@@ -20,6 +20,7 @@ component Video_Clock_III
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

1
FPGA/SW700/v1.3/build/Video_Clock_III.ppf → FPGA/SW700/v1.3/PLL/Video_Clock_III.ppf
View File

@@ -6,6 +6,7 @@
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>

3
FPGA/SW700/v1.3/build/Video_Clock_III.qip → FPGA/SW700/v1.3/PLL/Video_Clock_III.qip
View File

@@ -1,5 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_III.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III.cmp"]

54
FPGA/SW700/v1.3/build/Video_Clock_III.vhd → FPGA/SW700/v1.3/PLL/Video_Clock_III.vhd
View File

@@ -46,6 +46,7 @@ ENTITY Video_Clock_III IS
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Video_Clock_III;
@@ -58,9 +59,10 @@ ARCHITECTURE SYN OF video_clock_iii IS
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -75,6 +77,10 @@ ARCHITECTURE SYN OF video_clock_iii IS
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
@@ -135,15 +141,17 @@ ARCHITECTURE SYN OF video_clock_iii IS
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
@@ -156,9 +164,13 @@ BEGIN
clk1_duty_cycle => 50,
clk1_multiply_by => 11084,
clk1_phase_shift => "0",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 2,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_III",
lpm_type => "altpll",
operation_mode => "NORMAL",
@@ -190,7 +202,7 @@ BEGIN
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
@@ -209,7 +221,7 @@ BEGIN
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
@@ -239,10 +251,13 @@ END SYN;
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "17.734400"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "35.468800"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -264,25 +279,33 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "17.73440000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "35.46880000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -306,13 +329,16 @@ END SYN;
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -325,6 +351,10 @@ END SYN;
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11084"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -358,7 +388,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@@ -379,6 +409,7 @@ END SYN;
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
@@ -386,6 +417,7 @@ END SYN;
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.ppf TRUE

1
FPGA/SW700/v1.3/build/Video_Clock_III_inst.vhd → FPGA/SW700/v1.3/PLL/Video_Clock_III_inst.vhd
View File

@@ -3,5 +3,6 @@ Video_Clock_III_inst : Video_Clock_III PORT MAP (
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
c2 => c2_sig,
locked => locked_sig
);

0
FPGA/SW700/v1.3/build/Video_Clock_II_inst.vhd → FPGA/SW700/v1.3/PLL/Video_Clock_II_inst.vhd
View File

7
FPGA/SW700/v1.3/build/SFL_IV.cmp → FPGA/SW700/v1.3/PLL/Video_Clock_IV.cmp
View File

@@ -13,9 +13,12 @@
--applicable agreement for further details.
component SFL_IV
component Video_Clock_IV
PORT
(
noe_in : IN STD_LOGIC
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

11
FPGA/SW700/v1.3/PLL/Video_Clock_IV.ppf Normal file
View File

@@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="Video_Clock_IV" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

6
FPGA/SW700/v1.3/PLL/Video_Clock_IV.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_IV.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_IV.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_IV.ppf"]

365
FPGA/SW700/v1.3/PLL/Video_Clock_IV.vhd Normal file
View File

@@ -0,0 +1,365 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Video_Clock_IV.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Video_Clock_IV IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Video_Clock_IV;
ARCHITECTURE SYN OF video_clock_iv IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 3,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_IV",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "75.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "75.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Video_Clock_II.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

0
FPGA/SW700/v1.3/build/Video_Clock_inst.vhd → FPGA/SW700/v1.3/PLL/Video_Clock_inst.vhd
View File

0
FPGA/SW700/v1.3/build/SFL.cmp → FPGA/SW700/v1.3/SFL/SFL.cmp
View File

0
FPGA/SW700/v1.3/build/SFL.qip → FPGA/SW700/v1.3/SFL/SFL.qip
View File

0
FPGA/SW700/v1.3/build/SFL.vhd → FPGA/SW700/v1.3/SFL/SFL.vhd
View File

21
FPGA/SW700/v1.3/SFL/SFL_IV.cmp Normal file
View File

@@ -0,0 +1,21 @@
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
component SFL_IV
PORT
(
noe_in : IN STD_LOGIC
);
end component;

3
FPGA/SW700/v1.3/build/SFL_IV.qip → FPGA/SW700/v1.3/SFL/SFL_IV.qip
View File

@@ -1,5 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "Serial Flash Loader"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "SFL_IV.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL_IV_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL_IV.cmp"]

26
FPGA/SW700/v1.3/build/SFL_IV.vhd → FPGA/SW700/v1.3/SFL/SFL_IV.vhd
View File

@@ -9,28 +9,28 @@
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
@@ -58,6 +58,7 @@ ARCHITECTURE SYN OF sfl_iv IS
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
ncso_width : NATURAL;
lpm_type : STRING
);
PORT (
@@ -73,6 +74,7 @@ BEGIN
enable_shared_access => "OFF",
enhanced_mode => 1,
intended_device_family => "Cyclone IV E",
ncso_width => 1,
lpm_type => "altserial_flash_loader"
)
PORT MAP (
@@ -92,6 +94,7 @@ END SYN;
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: NCSO_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV.vhd TRUE
@@ -99,4 +102,3 @@ END SYN;
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

0
FPGA/SW700/v1.3/build/SFL_IV_inst.vhd → FPGA/SW700/v1.3/SFL/SFL_IV_inst.vhd
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0
FPGA/SW700/v1.3/build/SFL_inst.vhd → FPGA/SW700/v1.3/SFL/SFL_inst.vhd
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1094
FPGA/SW700/v1.3/T80/T80.vhd
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File diff suppressed because it is too large Load Diff

10
FPGA/SW700/v1.3/VideoController.qip Normal file
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@@ -0,0 +1,10 @@
set_global_assignment -name IP_TOOL_NAME "Sharp MZ Video Controller"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) VideoController/VideoController.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) VideoController/VideoController_pkg.vhd]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) VideoController/VideoController_constraints.sdc]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) devices/sysbus/RAM/dpram.vhd]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) PLL/Video_Clock.qip]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) PLL/Video_Clock_II.qip]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) PLL/Video_Clock_III.qip]

836
FPGA/SW700/v1.3/VideoController.vhd → FPGA/SW700/v1.3/VideoController/VideoController.vhd
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File diff suppressed because it is too large Load Diff

193
FPGA/SW700/v1.3/VideoController/VideoController_constraints.sdc Normal file
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@@ -0,0 +1,193 @@
## Generated SDC file "VideoController_constraints.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
create_generated_clock -name {SYS_CLK} -source [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_8MHZ} -source [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_16MHZ} -source [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 25 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
create_generated_clock -name {VIDCLK_40MHZ} -source [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
create_generated_clock -name {VIDCLK_65MHZ} -source [get_pins {vcCoreVideo|VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 5 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_25_175MHZ} -source [get_pins {vcCoreVideo|VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 91 -divide_by 90 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL2|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_8_86719MHZ} -source [get_pins {vcCoreVideo|VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 324 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_17_7344MHZ} -source [get_pins {vcCoreVideo|VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 162 -phase 0.00 -master_clock {CLOCK_50} [get_pins {vcCoreVideo|VCPLL3|altpll_component|auto_generated|pll1|clk[1]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
# # There is no relationship between the different video frequencies, only one is used at a time and they are switched through synchronised D-Type flip flops.
set_false_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
# Clock 50MHZ, the input oscillator is only used for the PLL input and does not directly drive registers.
set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {SYS_CLK VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {CLOCK_50}] -setup -end 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {CLOCK_50}] -hold -end 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_8MHZ}] -setup -end 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_8MHZ}] -hold -end 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_8_86719MHZ}] -setup -end 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_8_86719MHZ}] -hold -end 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_16MHZ}] -setup -end 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_16MHZ}] -hold -end 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_17_7344MHZ}] -setup -end 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_17_7344MHZ}] -hold -end 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_25_175MHZ}] -setup -end 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_25_175MHZ}] -hold -end 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_40MHZ}] -setup -end 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_40MHZ}] -hold -end 1
#set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_65MHZ}] -setup -end 2
#set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VIDCLK_65MHZ}] -hold -end 1
set_multicycle_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {SYS_CLK}] -setup -end 2
set_multicycle_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {SYS_CLK}] -hold -end 1
set_multicycle_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {SYS_CLK}] -setup -end 2
set_multicycle_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {SYS_CLK}] -hold -end 1
set_multicycle_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {SYS_CLK}] -setup -end 2
set_multicycle_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {SYS_CLK}] -hold -end 1
set_multicycle_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {SYS_CLK}] -setup -end 2
set_multicycle_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {SYS_CLK}] -hold -end 1
set_multicycle_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {SYS_CLK}] -setup -end 3
set_multicycle_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {SYS_CLK}] -hold -end 2
set_multicycle_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {SYS_CLK}] -setup -end 2
set_multicycle_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {SYS_CLK}] -hold -end 1
set_multicycle_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {SYS_CLK}] -setup -end 2
set_multicycle_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {SYS_CLK}] -hold -end 1
# GPU control and run variables have at least 1 clock between them being setup and used.
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}] -hold -end 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -hold -end 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

184
FPGA/SW700/v1.3/VideoController/VideoController_pkg.vhd Normal file
View File

@@ -0,0 +1,184 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: VideoController_pkg.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ700 Video Module v1.1 FPGA configuration file.
--
-- This module contains parameters for the Sharp MZ series Video Module found on the
-- tranZPUter700 card.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Oct 2020 - Split off from the Sharp MZ80A Video Module, the Video Module for the
-- Sharp MZ700 has the same roots but different control functionality. The
-- MZ700 version resides within the tranZPUter memory and not the mainboard
-- allowing for generally easier control. The MZ80A and MZ700 graphics logic
-- should be pretty much identical.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package VideoController_pkg is
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Target hardware modes.
constant MODE_MZ80K : integer := 0;
constant MODE_MZ80C : integer := 1;
constant MODE_MZ1200 : integer := 2;
constant MODE_MZ80A : integer := 3;
constant MODE_MZ700 : integer := 4;
constant MODE_MZ800 : integer := 5;
constant MODE_MZ80B : integer := 6;
constant MODE_MZ2000 : integer := 7;
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Target hardware.
constant CPLD_HOST_HW : integer := MODE_MZ700;
-- Target video hardware.
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
-- Version of hdl.
constant CPLD_VERSION : integer := 2;
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
-- Function to reverse the order of the bits in a standard logic vector.
-- ie. 1010 becomes 0101
function reverse_vector(slv:std_logic_vector) return std_logic_vector;
-- Function to convert an integer (0 or 1) into std_logic.
--
function to_std_logic(i : in integer) return std_logic;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural;
------------------------------------------------------------
-- Records
------------------------------------------------------------
------------------------------------------------------------
-- Components
------------------------------------------------------------
end VideoController_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body VideoController_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then
return 0;
end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer is
variable ticks : real;
variable fracTicks : real;
begin
ticks := (Real(period) * Real(clock)) / 1000000000.0;
fracTicks := ticks - CEIL(ticks);
if fracTicks > 0.0001 then
return Integer(CEIL(ticks + 1.0));
else
return Integer(CEIL(ticks));
end if;
end function;
function reverse_vector(slv:std_logic_vector) return std_logic_vector is
variable target : std_logic_vector(slv'high downto slv'low);
begin
for idx in slv'high downto slv'low loop
target(idx) := slv(slv'low + (slv'high-idx));
end loop;
return target;
end reverse_vector;
function to_std_logic(i : in integer) return std_logic is
begin
if i = 0 then
return '0';
end if;
return '1';
end function;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
end package body;

1
FPGA/SW700/v1.3/ZPU/zpu_core_evo.vhd
View File

@@ -1 +0,0 @@
../../../../cpu/zpu_core_evo.vhd

1
FPGA/SW700/v1.3/ZPU/zpu_core_evo_L2.vhd
View File

@@ -1 +0,0 @@
../../../../cpu/zpu_core_evo_L2.vhd

1
FPGA/SW700/v1.3/ZPU/zpu_uart_debug.vhd
View File

@@ -1 +0,0 @@
../../../../cpu/zpu_uart_debug.vhd

29
FPGA/SW700/v1.3/build/coreMZ.qpf
View File

@@ -1,30 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 10:43:30 January 29, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "16:29:32 June 24, 2020"
QUARTUS_VERSION = "17.1"
DATE = "10:43:30 January 29, 2021"
# Revisions
PROJECT_REVISION = "coreMZ"
PROJECT_REVISION = "coreMZ_E115"

75
FPGA/SW700/v1.3/build/coreMZ.qsf
View File

@@ -1,4 +1,3 @@
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
@@ -41,9 +40,9 @@ set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
set_global_assignment -name DEVICE EP4CE75F23I7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY coreMZ
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
@@ -51,7 +50,7 @@ set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthe
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
@@ -180,20 +179,20 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSACKn
# Composite video multiplexed with Soft CPU input signals.
# ========================================================
set_location_assignment PIN_R1 -to VWAITn_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_HALTn_V_VSYNCn
set_location_assignment PIN_R1 -to VWAITn_A21_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_A20_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_A19_HALTn_V_VSYNCn
set_location_assignment PIN_N1 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_N2 -to VZ80_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_HALTn_V_VSYNCn
set_location_assignment PIN_N2 -to VZ80_A16_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_A18_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_A17_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_A21_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A20_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A19_HALTn_V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSRn_V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A16_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A18_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A17_NMIn_V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
@@ -260,46 +259,34 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_C
# Files in project.
# =================
set_global_assignment -name VHDL_FILE ../coreMZ.vhd
#set_global_assignment -name QIP_FILE Clock_50to100.qip
set_global_assignment -name QIP_FILE SFL_IV.qip
set_global_assignment -name QIP_FILE Video_Clock.qip
set_global_assignment -name QIP_FILE Video_Clock_II.qip
set_global_assignment -name QIP_FILE Video_Clock_III.qip
set_global_assignment -name VHDL_FILE ../coreMZ_pkg.vhd
set_global_assignment -name VHDL_FILE ../VideoController.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
set_global_assignment -name SDC_FILE coreMZ_constraints.sdc
# Latest T80 CPU
# ==============
set_global_assignment -name VHDL_FILE ../softT80.vhd
set_global_assignment -name VHDL_FILE ../T80/T80.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE ../T80/T80a.vhd
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name VHDL_FILE ../softZPU.vhd
set_global_assignment -name VHDL_FILE ../softZPU_pkg.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_core_evo.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_core_evo_L2.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_uart_debug.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_pkg.vhd
#set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/TZSW_DualPortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/TZSW_SinglePortBRAM.vhd
#set_global_assignment -name VHDL_FILE ../T80/T80a.vhd
set_global_assignment -name SEARCH_PATH ../AZ80
set_global_assignment -name VHDL_FILE ../coreMZ.vhd
set_global_assignment -name VHDL_FILE ../coreMZ_pkg.vhd
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
set_global_assignment -name QIP_FILE ../PLL/Video_Clock_IV.qip
set_global_assignment -name SDC_FILE ../coreMZ_constraints.sdc
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# T80 CPU definitions.
set_global_assignment -name QIP_FILE ../softT80.qip
# ZPU Evo CPU definitions
set_global_assignment -name QIP_FILE ../softZPU.qip
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF

294
FPGA/SW700/v1.3/build/coreMZ_E115.qsf Normal file
View File

@@ -0,0 +1,294 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# coreMZ_E115_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name DEVICE EP4CE115F23I7
#set_global_assignment -name DEVICE EP4CE75F23I7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY coreMZ
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:26:39 JANUARY 29, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
# Clocks.
# =======
set_location_assignment PIN_T21 -to CLOCK_50
set_location_assignment PIN_T22 -to CLOCK_50_2
set_location_assignment PIN_T2 -to CTLCLK
set_location_assignment PIN_T1 -to SYSCLK
set_location_assignment PIN_U1 -to VZ80_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CTL_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SYS_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_CLK
# Video Interface/Soft CPU Address Bus
# ====================================
set_location_assignment PIN_AB10 -to VZ80_ADDR[15]
set_location_assignment PIN_AA10 -to VZ80_ADDR[14]
set_location_assignment PIN_AB9 -to VZ80_ADDR[13]
set_location_assignment PIN_AA9 -to VZ80_ADDR[12]
set_location_assignment PIN_AB8 -to VZ80_ADDR[11]
set_location_assignment PIN_AA8 -to VZ80_ADDR[10]
set_location_assignment PIN_AB7 -to VZ80_ADDR[9]
set_location_assignment PIN_AA7 -to VZ80_ADDR[8]
set_location_assignment PIN_AB6 -to VZ80_ADDR[7]
set_location_assignment PIN_AA6 -to VZ80_ADDR[6]
set_location_assignment PIN_AB5 -to VZ80_ADDR[5]
set_location_assignment PIN_AA5 -to VZ80_ADDR[4]
set_location_assignment PIN_AA4 -to VZ80_ADDR[3]
set_location_assignment PIN_AA1 -to VZ80_ADDR[2]
set_location_assignment PIN_Y2 -to VZ80_ADDR[1]
set_location_assignment PIN_Y1 -to VZ80_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[0]
# Video/Soft CPU Data Bus
# =======================
set_location_assignment PIN_AB16 -to VZ80_DATA[7]
set_location_assignment PIN_AA16 -to VZ80_DATA[6]
set_location_assignment PIN_AB15 -to VZ80_DATA[5]
set_location_assignment PIN_AA15 -to VZ80_DATA[4]
set_location_assignment PIN_AB14 -to VZ80_DATA[3]
set_location_assignment PIN_AA14 -to VZ80_DATA[2]
set_location_assignment PIN_AB13 -to VZ80_DATA[1]
set_location_assignment PIN_AA13 -to VZ80_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[0]
# Video/Soft CPU control signals.
# ===============================
set_location_assignment PIN_W1 -to VIDEO_RDn
set_location_assignment PIN_V1 -to VIDEO_WRn
set_location_assignment PIN_V2 -to VZ80_IORQn
set_location_assignment PIN_C1 -to VZ80_MREQn
set_location_assignment PIN_R2 -to VZ80_M1n
set_location_assignment PIN_F1 -to VZ80_RDn
set_location_assignment PIN_H1 -to VZ80_WRn
set_location_assignment PIN_J1 -to VZ80_BUSACKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_MREQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_M1n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSACKn
# Composite video multiplexed with Soft CPU input signals.
# ========================================================
set_location_assignment PIN_R1 -to VWAITn_A21_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_A20_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_A19_HALTn_V_VSYNCn
set_location_assignment PIN_N1 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_N2 -to VZ80_A16_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_A18_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_A17_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_A21_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A20_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A19_HALTn_V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSRn_V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A16_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A18_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A17_NMIn_V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
set_location_assignment PIN_A20 -to COLR_OUT
set_location_assignment PIN_A14 -to CSYNC_OUTn
set_location_assignment PIN_A13 -to CSYNC_OUT
set_location_assignment PIN_A9 -to VSYNC_OUTn
set_location_assignment PIN_A10 -to HSYNC_OUTn
set_location_assignment PIN_H22 -to VGA_R[0]
set_location_assignment PIN_J22 -to VGA_R[1]
set_location_assignment PIN_K22 -to VGA_R[2]
set_location_assignment PIN_L22 -to VGA_R[3]
set_location_assignment PIN_M22 -to VGA_R_COMPOSITE
set_location_assignment PIN_A15 -to VGA_G[0]
set_location_assignment PIN_A16 -to VGA_G[1]
set_location_assignment PIN_A17 -to VGA_G[2]
set_location_assignment PIN_A18 -to VGA_G[3]
set_location_assignment PIN_A19 -to VGA_G_COMPOSITE
set_location_assignment PIN_B22 -to VGA_B[0]
set_location_assignment PIN_C22 -to VGA_B[1]
set_location_assignment PIN_D22 -to VGA_B[2]
set_location_assignment PIN_E22 -to VGA_B[3]
set_location_assignment PIN_F22 -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to COLR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
# Files in project.
# =================
#set_global_assignment -name QIP_FILE Clock_50to100.qip
# Latest T80 CPU
# ==============
# Latest ZPU EVO CPU
# ==================
#set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
#set_global_assignment -name VHDL_FILE ../T80/T80a.vhd
set_global_assignment -name SEARCH_PATH ../AZ80
set_global_assignment -name VHDL_FILE ../coreMZ.vhd
set_global_assignment -name VHDL_FILE ../coreMZ_pkg.vhd
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
set_global_assignment -name QIP_FILE ../PLL/Video_Clock_IV.qip
set_global_assignment -name SDC_FILE ../coreMZ_constraints.sdc
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# T80 CPU definitions.
set_global_assignment -name QIP_FILE ../softT80.qip
# ZPU Evo CPU definitions
set_global_assignment -name QIP_FILE ../softZPU.qip
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

281
FPGA/SW700/v1.3/build/coreMZ_constraints.sdc
View File

@@ -1,281 +0,0 @@
## Generated SDC file "VideoController700_constraints.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {VZ80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {VZ80_CLK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
create_generated_clock -name {SYS_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_8MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_16MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
create_generated_clock -name {VIDCLK_40MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
create_generated_clock -name {VIDCLK_65MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 5 -phase 0.00 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_25_175MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 91 -divide_by 90 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_8_86719MHZ} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 324 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_17_7344MHZ} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 162 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[1]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
set_input_delay -add_delay -clock [get_clocks {VZ80_CLK}] 1.000 [get_ports {VZ80_CLK}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VIDEO_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VIDEO_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_M1n}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[0]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[1]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[2]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[3]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[4]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[5]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[6]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[7]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VWAITn_V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_RFSHn_V_HSYNCn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_HALTn_V_VSYNCn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_BUSRQn_V_G}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_WAITn_V_B}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_INTn_V_R}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_NMIn_V_COLR}]
# Required for the Serial Flash Loader.
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tck}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tms}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[4]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[5]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[6]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[7]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_WRn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RDn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_IORQn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_M1n}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VWAITn_V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RFSHn_V_HSYNCn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_HALTn_V_VSYNCn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {HSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {COLR_OUT}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC_OUT}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC_OUTn}]
# Required for the Serial Flash Loader.
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
# There is no relationship between the different video frequencies, only one is used at a time and they are switched through synchronised D-Type flip flops.
set_false_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
# Z80 clock has no relationship to the video frequencies, it is used only for latching data asynchronous to the FPGA clocks.
set_false_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# The system clock has no real relationship with the video frequencies, rendering and display. The only place they meet is in the dual port BRAM.
set_false_path -from [get_clocks {SYS_CLK}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# Clock 50MHZ, the input oscillator is only used for the PLL input and as I/O input/output latch which is detached from the video block
set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# The Z80 data, address and control lines do not go to the video block (except the parameter update which is not critical) so set it as a false path so as not to consider.
set_false_path -from [get_ports {VZ80_DATA[*]}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
set_false_path -from [get_ports {VZ80_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}]
set_false_path -from [get_ports {VZ80_WRn VZ80_RDn VZ80_IORQn}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|DSP_PARAM_SEL[*]}] -to [get_ports {VZ80_DATA[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|DSP_PARAM_SEL[*]}] -to [get_ports {VZ80_DATA[*]}] -setup -start 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VZ80_CLK}] -hold -start 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VZ80_CLK}] -setup -start 2
set_multicycle_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {SYS_CLK}] -hold -start 2
set_multicycle_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {SYS_CLK}] -setup -start 3
# GPU control and run variables have at least 1 clock between them being setup and used.
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -hold -start 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

29
FPGA/SW700/v1.3/build/vbuffer.cmp
View File

@@ -1,29 +0,0 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component vbuffer
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
end component;

5
FPGA/SW700/v1.3/build/vbuffer.qip
View File

@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "vbuffer.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vbuffer_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vbuffer.cmp"]

204
FPGA/SW700/v1.3/build/vbuffer.vhd
View File

@@ -1,204 +0,0 @@
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: vbuffer.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY vbuffer IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END vbuffer;
ARCHITECTURE SYN OF vbuffer IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(7 DOWNTO 0);
rdempty <= sub_wire2;
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 8192,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 13,
overflow_checking => "OFF",
rdsync_delaypipe => 3,
read_aclr_synch => "OFF",
underflow_checking => "OFF",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 3
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "4096"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

11
FPGA/SW700/v1.3/build/vbuffer_inst.vhd
View File

@@ -1,11 +0,0 @@
vbuffer_inst : vbuffer PORT MAP (
aclr => aclr_sig,
data => data_sig,
rdclk => rdclk_sig,
rdreq => rdreq_sig,
wrclk => wrclk_sig,
wrreq => wrreq_sig,
q => q_sig,
rdempty => rdempty_sig,
wrfull => wrfull_sig
);

635
FPGA/SW700/v1.3/coreMZ.vhd
View File

@@ -22,6 +22,9 @@
-- with it's much larger FPGA, it is now possible to add Soft CPU's in
-- addition to the Video Controller logic. This required a restructuring
-- of the VHDL to seperate the Video from the Soft CPUs.
-- Dec 2020 - ZPU Evo added into the framework.
-- Jan 2021 - Z80 (T80, AZ80, NextZ80) and ZPU Evolution processors added into the
-- framework.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
@@ -42,7 +45,6 @@ library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.coreMZ_pkg.all;
--use work.zpu_pkg.all;
use altera.altera_syn_attributes.all;
entity coreMZ is
@@ -84,81 +86,71 @@ entity coreMZ is
CSYNC_OUT : out std_logic; -- Composite sync (positive).
-- RGB & Composite input signals.
VWAITn_V_CSYNC : inout std_logic; -- Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
VZ80_RFSHn_V_HSYNCn : inout std_logic; -- Soft CPU RFSH out / Horizontal sync (negative) from mainboard.
VZ80_HALTn_V_VSYNCn : inout std_logic; -- Soft CPU HALT out / Video memory selected / Vertical sync (negative) from mainboard.
VZ80_NMIn_V_COLR : in std_logic; -- Soft CPU NMIn in / Composite and RF base frequency from mainboard.
VWAITn_A21_V_CSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
VZ80_A20_RFSHn_V_HSYNCn : inout std_logic; -- Upper address bit for access to FPGA resources / Soft CPU RFSH out / Horizontal sync (negative) from mainboard.
VZ80_A19_HALTn_V_VSYNCn : inout std_logic; -- Upper address bit for access to FPGA resources / Soft CPU HALT out / Video memory selected / Vertical sync (negative) from mainboard.
VZ80_A17_NMIn_V_COLR : in std_logic; -- Upper address bit for access to FPGA resources / Soft CPU NMIn in / Composite and RF base frequency from mainboard.
VZ80_BUSRQn_V_G : in std_logic; -- Soft CPU BUSRQn in / Digital Green (on/off) from mainboard.
VZ80_WAITn_V_B : in std_logic; -- Soft CPU WAITn in / Digital Blue (on/off) from mainboard.
VZ80_INTn_V_R : in std_logic -- Soft CPU INTn in / Digital Red (on/off) from mainboard.
VZ80_A16_WAITn_V_B : in std_logic; -- Upper address bit for access to FPGA resources / Soft CPU WAITn in / Digital Blue (on/off) from mainboard.
VZ80_A18_INTn_V_R : in std_logic -- Upper address bit for access to FPGA resources / Soft CPU INTn in / Digital Red (on/off) from mainboard.
);
END entity;
architecture rtl of coreMZ is
signal SYS_CLK : std_logic;
signal VIDCLK_8MHZ : std_logic;
signal VIDCLK_16MHZ : std_logic;
signal VIDCLK_25_175MHZ : std_logic;
signal VIDCLK_40MHZ : std_logic;
signal VIDCLK_65MHZ : std_logic;
signal VIDCLK_8_86719MHZ : std_logic;
signal VIDCLK_17_7344MHZ : std_logic;
signal CPUCLK_75MHZ : std_logic;
signal PLL_LOCKED : std_logic;
signal PLL_LOCKED2 : std_logic;
signal PLL_LOCKED3 : std_logic;
signal RESETn : std_logic := '0';
signal RESET_COUNTER : unsigned(3 downto 0) := (others => '1');
signal CTRLREG_RESET : std_logic := '1'; -- Flag to indicate when a hard reset occurs so that registers can be preloaded based on conditions.
signal MODE_CPLD_VIDEO_WAIT : std_logic; -- FPGA video display period wait flag, 1 = enabled, 0 = disabled.
signal CPU_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPU Configuration register.
signal CPU_INFO_DATA : std_logic_vector(7 downto 0); -- CPU configuration information register.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD configuration register.
signal MODE_CPLD_SWITCH : std_logic := '1'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the machine mode has changed. Flag is active for 1 clock cycle.
signal MODE_CPU_CHANGED : std_logic; -- Flag to indicate the CPU has been changed.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPLD configuration register.
signal MODE_CPU_SOFT : std_logic; -- Control signal to enable the Soft CPU and support logic.
signal MODE_SOFTCPU_RESET : std_logic; -- Software controlled reset signal to reset a soft cpu.
signal MODE_SOFTCPU_CLKEN : std_logic; -- Enable the soft cpu clock (1).
signal MODE_CPLD_MB_VIDEOn : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the mainboard video logic is enabled, disabling or blending with the FPGA graphics.
signal MODE_SOFTCPU_Z80 : std_logic; -- Flag to indicate the Z80 module is available and active.
signal MODE_SOFTCPU_ZPUEVO : std_logic; -- Flag to indicate the ZPU Evo module is available and active.
signal CS_IO_6XXn : std_logic; -- Chip select for CPLD configuration registers.
signal CS_CPU_CFGn : std_logic; -- Select to set the CPU configuration register.
signal CS_CPU_INFOn : std_logic; -- Select to read the CPU information register.
signal CS_CPLD_CFGn : std_logic; -- Chip Select to write to the CPLD configuration register at 0x6E.
signal VZ80_HI_ADDR : std_logic_vector(23 downto 16); -- Upper address bits (to 16M) are multiplexed and only available during external access of the FPGA resources.
signal VZ80_BUSACKni : std_logic; -- Internal combination of BUSACK signals.
signal COLOUR_CARRIER_FREQ : std_logic; -- Modulator colour carrier frequency output by video module.
-- T80
-- T80 - General identifier for Z80 based Soft CPU's, the T80 being the primary but also AZ80 and NextZ80 are available via config flag.
--
signal T80_MREQn : std_logic;
signal T80_BUSRQn : std_logic;
signal T80_IORQn : std_logic;
signal T80_WRn : std_logic;
signal T80_RDn : std_logic;
signal T80_WAITn : std_logic;
signal T80_M1n : std_logic;
signal T80_RFSHn : std_logic;
signal T80_ADDR : std_logic_vector(15 downto 0);
signal T80_INTn : std_logic;
signal T80_DATA_IN : std_logic_vector(7 downto 0);
signal T80_DATA_OUT : std_logic_vector(7 downto 0);
signal T80_BUSACKn : std_logic;
signal T80_NMIn : std_logic;
signal T80_HALTn : std_logic;
-- ZPU
signal ZPU_MREQn : std_logic;
signal ZPU_BUSRQn : std_logic;
signal ZPU_IORQn : std_logic;
signal ZPU_WRn : std_logic;
signal ZPU_RDn : std_logic;
signal ZPU_WAITn : std_logic;
signal ZPU_M1n : std_logic;
signal ZPU_RFSHn : std_logic;
signal ZPU_VIDEO_WRn : std_logic;
signal ZPU_VIDEO_RDn : std_logic;
signal ZPU_ADDR : std_logic_vector(15 downto 0);
signal ZPU_VIDEO_ADDR : std_logic_vector(2 downto 0);
signal ZPU_INTn : std_logic;
signal ZPU_DATA_IN : std_logic_vector(7 downto 0);
signal ZPU_DATA_OUT : std_logic_vector(7 downto 0);
signal ZPU_BUSACKn : std_logic;
signal ZPU_NMIn : std_logic;
signal ZPU_HALTn : std_logic;
signal ZPU80_MREQn : std_logic;
signal ZPU80_IORQn : std_logic;
signal ZPU80_WRn : std_logic;
signal ZPU80_RDn : std_logic;
signal ZPU80_M1n : std_logic;
signal ZPU80_RFSHn : std_logic;
signal ZPU80_ADDR : std_logic_vector(15 downto 0);
signal ZPU80_VIDEO_ADDR : std_logic_vector(7 downto 0);
signal ZPU80_DATA_OUT : std_logic_vector(7 downto 0);
signal ZPU80_HALTn : std_logic;
signal ZPU_DATA_OUT : std_logic_vector(31 downto 0); -- External RAM block data to write to RAM.
signal ZPU_ADDR : std_logic_vector(23 downto 0); -- 24bit address bus to address RAM.
signal ZPU_WRITE_EN : std_logic; -- Write to external RAM.
signal ZPU_MEM_BUSACK : std_logic; -- Memory bus acknowledge signal.
signal ZPU_VIDEO_WRn : std_logic; -- Dedicated video channel write signal, bypasses the CPLD.
signal ZPU_VIDEO_RDn : std_logic; -- Dedicated video channel read signal, bypasses the CPLD.
-- Internal core signals, muxed or demuxed physical connections.
--
@@ -173,53 +165,32 @@ architecture rtl of coreMZ is
signal CORE_VIDEO_WRn : std_logic; -- FPGA video write. Normally from the CPLD memory manager but overriden by soft CPU's such as the ZPU.
signal CORE_VIDEO_RDn : std_logic; -- FPGA video read. Normally from the CPLD memory manager but overriden by soft CPU's such as the ZPU.
signal CORE_ADDR : std_logic_vector(15 downto 0); --
signal CORE_VIDEO_ADDR : std_logic_vector(2 downto 0); --
signal CORE_HI_ADDR : std_logic_vector(7 downto 0); -- Upper address bits of the 24bit address bus used to access video memory and BRAM devices of soft CPU's.
signal CORE_DATA_OUT : std_logic_vector(7 downto 0); --
signal CORE_DATA_IN : std_logic_vector(7 downto 0); --
signal CORE_V_HSYNCn : std_logic; --
signal CORE_V_VSYNCn : std_logic; --
signal CORE_V_COLR : std_logic; --
signal CORE_V_R : std_logic; --
signal CORE_V_G : std_logic; --
signal CORE_V_B : std_logic; --
signal VZ80_CLK_LAST : std_logic_vector(2 downto 0);
signal VZ80_BUSRQn : std_logic;
begin
-- Instantiate a PLL to generate the system clock and base video clocks.
------------------------------------------------------------------------------------
-- PLL System generation.
------------------------------------------------------------------------------------
-- Instantiate a PLL to generate the clocks required by soft processors.
--
VCPLL1 : entity work.Video_Clock
COREMZPLL1 : entity work.Video_Clock_IV
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => SYS_CLK,
c1 => VIDCLK_8MHZ,
c2 => VIDCLK_16MHZ,
c3 => VIDCLK_40MHZ,
c0 => CPUCLK_75MHZ,
locked => PLL_LOCKED
);
-- Instantiate a 2nd PLL to generate additional video clocks for VGA and Sharp MZ700 modes.
VCPLL2 : entity work.Video_Clock_II
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => VIDCLK_65MHZ,
c1 => VIDCLK_25_175MHZ,
locked => PLL_LOCKED2
);
-- Instantiate a 3rd PLL to generate clock for pseudo monochrome generation on internal monitor.
VCPLL3 : entity work.Video_Clock_III
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => VIDCLK_8_86719MHZ,
c1 => VIDCLK_17_7344MHZ,
locked => PLL_LOCKED3
);
------------------------------------------------------------------------------------
-- Serial Flash Loader for updating the EPCS64 via Altera Quartus.
------------------------------------------------------------------------------------
SERIALFLASHLOADER: if IMPL_SFL = true generate
-- Add the Serial Flash Loader megafunction to enable in-situ programming of the EPCS16 configuration memory.
--
SFL : entity work.sfl_iv
@@ -227,29 +198,35 @@ begin
(
noe_in => '0'
);
end generate;
------------------------------------------------------------------------------------
-- System Reset
------------------------------------------------------------------------------------
-- Process to reset the FPGA based on the external RESET trigger, PLL's being locked
-- and a counter to set minimum width.
--
FPGARESET: process(CLOCK_50, PLL_LOCKED, PLL_LOCKED2, PLL_LOCKED3)
FPGARESET: process(CLOCK_50, PLL_LOCKED)
begin
if PLL_LOCKED = '0' or PLL_LOCKED2 = '0' or PLL_LOCKED3 = '0' then
if PLL_LOCKED = '0' then
RESET_COUNTER <= (others => '1');
RESETn <= '0';
elsif PLL_LOCKED = '1' and PLL_LOCKED2 = '1' and PLL_LOCKED3 = '1' then
elsif PLL_LOCKED = '1' then
if rising_edge(CLOCK_50) then
if RESET_COUNTER /= 0 then
RESET_COUNTER <= RESET_COUNTER - 1;
elsif VIDEO_WRn = '0' and VIDEO_RDn = '0' then
RESETn <= '0';
elsif VIDEO_WRn = '1' or VIDEO_RDn = '1' then
elsif (VIDEO_WRn = '1' or VIDEO_RDn = '1') and RESET_COUNTER = 0 then
RESETn <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------
-- Video Controller
------------------------------------------------------------------------------------
@@ -261,30 +238,13 @@ begin
port map
(
-- Primary and video clocks.
SYS_CLK => SYS_CLK, -- 120MHz main FPGA clock.
CLOCK_50 => CLOCK_50, -- 50MHz main FPGA clock.
VZ80_CLK => VZ80_CLK, -- Z80 runtime clock (product of SYSCLK and CTLCLK - variable frequency).
VIDCLK_8MHZ => VIDCLK_8MHZ, -- 2x 8MHz base clock for video timing and gate clocking.
VIDCLK_16MHZ => VIDCLK_16MHZ, -- 2x 16MHz base clock for video timing and gate clocking.
VIDCLK_65MHZ => VIDCLK_65MHZ, -- 2x 65MHz base clock for video timing and gate clocking.
VIDCLK_25_175MHZ => VIDCLK_25_175MHZ, -- 2x 25.175MHz base clock for video timing and gate clocking.
VIDCLK_40MHZ => VIDCLK_40MHZ, -- 2x 40MHz base clock for video timing and gate clocking.
VIDCLK_8_86719MHZ => VIDCLK_8_86719MHZ, -- 2x original MZ700 video clock.
VIDCLK_17_7344MHZ => VIDCLK_17_7344MHZ, -- 2x original MZ700 colour modulator clock.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Address Bus
VIDEO_ADDR => CORE_ADDR, -- Z80 Address bus.
-- Direct addressing Bus. Normally this is set to 0 during standard Sharp MZ operation, when > 0 then direct addressing of the various video
-- memory's is required.
-- 000 - Normal
-- 001 - Video RAM..
-- 010 - Attribute RAM.
-- 011 - Character Generator RAM
-- 100 - Red framebuffer.
-- 101 - Blue framebuffer.
-- 110 - Green framebuffer.
VIDEO_HI_ADDR => CORE_VIDEO_ADDR, -- Direct Addressing bus.
VIDEO_HI_ADDR => CORE_HI_ADDR, -- Direct Addressing bus.
-- Data Bus
VIDEO_DATA_IN => CORE_DATA_IN, -- Z80 Data bus from CPU into video module.
@@ -304,43 +264,50 @@ begin
VGA_B_COMPOSITE => VGA_B_COMPOSITE, -- RGB Blue override for composite output.
HSYNC_OUTn => HSYNC_OUTn, -- Horizontal sync.
VSYNC_OUTn => VSYNC_OUTn, -- Vertical sync.
COLR_OUT => COLR_OUT, -- Composite and RF base frequency.
COLR_OUT => COLOUR_CARRIER_FREQ, -- Composite colour and RF base frequency.
CSYNC_OUTn => CSYNC_OUTn, -- Composite sync (negative).
CSYNC_OUT => CSYNC_OUT, -- Composite sync (positive).
-- RGB & Composite input signals.
VWAITn_V_CSYNC => VWAITn_V_CSYNC, -- Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
V_HSYNCn => CORE_V_HSYNCn, -- Horizontal sync (negative) from mainboard.
V_VSYNCn => CORE_V_VSYNCn, -- Vertical sync (negative) from mainboard.
V_COLR => CORE_V_COLR, -- Soft CPU NMIn / Composite and RF base frequency from mainboard.
V_G => CORE_V_G, -- Soft CPU BUSRQn / Digital Green (on/off) from mainboard.
V_B => CORE_V_B, -- Soft CPU WAITn / Digital Blue (on/off) from mainboard.
V_R => CORE_V_R, -- Soft CPU INTn / Digital Red (on/off) from mainboard.
VWAITn_V_CSYNC => VWAITn_A21_V_CSYNC, -- Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
V_HSYNCn => VZ80_A20_RFSHn_V_HSYNCn, -- Horizontal sync (negative) from mainboard.
V_VSYNCn => VZ80_A19_HALTn_V_VSYNCn, -- Vertical sync (negative) from mainboard.
V_COLR => VZ80_A17_NMIn_V_COLR, -- Soft CPU NMIn / Composite and RF base frequency from mainboard.
V_G => VZ80_BUSRQn_V_G, -- Soft CPU BUSRQn / Digital Green (on/off) from mainboard.
V_B => VZ80_A16_WAITn_V_B, -- Soft CPU WAITn / Digital Blue (on/off) from mainboard.
V_R => VZ80_A18_INTn_V_R, -- Soft CPU INTn / Digital Red (on/off) from mainboard.
-- Reset.
VRESETn => CORE_RESETn, -- Internal reset.
-- Configuration.
CPLD_CFG_DATA => CPLD_CFG_DATA, -- CPLD internal settings register.
VIDEO_MODE => CPLD_CFG_DATA(2 downto 0), -- Video mode the controller should emulate.
MB_VIDEO_ENABLEn => MODE_CPLD_MB_VIDEOn -- Mainboard video enabled (=0) or FPGA advanced video (=1).
);
------------------------------------------------------------------------------------
-- T80 CPU
------------------------------------------------------------------------------------
CPU0 : entity work.softT80
CPU0: if IMPL_SOFTCPU_Z80 = true generate
signal T80_INTn : std_logic;
signal T80_NMIn : std_logic;
signal T80_BUSRQn : std_logic;
signal T80_WAITn : std_logic;
signal T80_DATA_IN : std_logic_vector(7 downto 0);
begin
T80CPU : entity work.softT80
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
SYS_CLK => SYS_CLK, -- System logic clock ~120MHz
SYS_CLK => CLOCK_50, -- System logic clock ~50MHz
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => CPU_CFG_DATA(7), -- Software controlled reset.
SW_ENABLE => MODE_CPU_SOFT, -- Software controlled CPU enable.
CPU_CHANGED => MODE_CPU_CHANGED, -- Flag to indicate when software selects a different CPU.
SW_RESET => MODE_SOFTCPU_RESET, -- Software controlled reset.
SW_CLKEN => MODE_SOFTCPU_CLKEN, -- Software controlled clock enable.
SW_CPUEN => MODE_SOFTCPU_Z80, -- Software controlled CPU enable.
-- Core Sharp MZ signals.
T80_WAITn => T80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
@@ -360,48 +327,148 @@ begin
T80_DATA_OUT => T80_DATA_OUT -- 8 bit data bus out.
);
-- Soft CPU data input. Read directly from the Video Controller if selected, at all other times read from the CPLD which in turn reads from the tranZPUter or mainboard.
T80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when CORE_VIDEO_RDn = '0'
else
VZ80_DATA when MODE_SOFTCPU_Z80 = '1' and T80_RDn = '0'
else (others => '0');
-- Direct routed signals to the T80 when not using mainboard video.
T80_INTn <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
T80_NMIn <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
T80_BUSRQn <= VZ80_BUSRQn when MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_WAITn <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
else generate
T80_WRn <= '1';
T80_RDn <= '1';
T80_M1n <= '1';
T80_HALTn <= '1';
T80_MREQn <= '1';
T80_IORQn <= '1';
T80_BUSACKn <= '1';
T80_ADDR <= (others => 'X');
T80_DATA_OUT <= (others => 'X');
end generate;
------------------------------------------------------------------------------------
-- ZPU Evolution CPU
------------------------------------------------------------------------------------
CPU1 : entity work.softZPU
CPU1: if IMPL_SOFTCPU_ZPUEVO = true generate
signal ZPU80_INTn : std_logic;
signal ZPU80_NMIn : std_logic;
signal ZPU80_WAITn : std_logic;
signal ZPU80_DATA_IN : std_logic_vector(7 downto 0);
signal ZPU_MEM_BUSRQ : std_logic; -- Memory bus request signal.
begin
ZPUCPU : entity work.softZPU
generic map (
SYSCLK_FREQUENCY => 50000000 -- Speed of clock used for the ZPU.
SYSCLK_FREQUENCY => 75000000 -- Speed of clock used for the ZPU.
)
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
SYS_CLK => SYS_CLK, -- System logic clock ~120MHz
ZPU_CLK => CLOCK_50, -- ZPU clock.
ZPU_CLK => CPUCLK_75MHZ, -- ZPU clock.
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => CPU_CFG_DATA(7), -- Software controlled reset.
SW_ENABLE => MODE_CPU_SOFT, -- Software controlled CPU enable.
CPU_CHANGED => MODE_CPU_CHANGED, -- Flag to indicate when software selects a different CPU.
SW_RESET => MODE_SOFTCPU_RESET, -- Software controlled reset.
SW_CLKEN => MODE_SOFTCPU_CLKEN, -- Software controlled clock enable.
SW_CPUEN => MODE_SOFTCPU_ZPUEVO, -- Software controlled CPU enable.
-- Direct access to the video controller, bypassing the CPLD Memory management.
VIDEO_WRn => ZPU_VIDEO_WRn, -- Direct video write from ZPU, bypass CPLD memory manager.
VIDEO_RDn => ZPU_VIDEO_RDn, -- Direct video read from ZPU, bypass CPLD memory manager.
VIDEO_DIRECT_ADDR => ZPU_VIDEO_ADDR, -- Direct addressing of video memory (bypassing register configuration needed by Sharp MZ host to maintain compatibility or address space restrictions).
-- External Direct addressing Bus. Ability to read and write to the internal ZPU memory for uploading new programs/debugging.
-- When BUSRQ is asserted, the external system can drive the signals to query memory.
-- A23 -A16
-- 00000000 - Normal Sharp MZ behaviour
-- 00001XXX - Video Controller
-- 00010000 ->
-- 00011000 - ZPU 128K Block. Boot and stack memory.
-- Access to internal BRAM access signals, become active when bus granted.
INT_MEM_DATA_IN => X"000000" & VZ80_DATA(7 downto 0), -- Internal RAM block data to write to RAM.
INT_MEM_DATA_OUT => ZPU_DATA_OUT, -- Internal RAM block data read from RAM.
INT_MEM_ADDR => VZ80_HI_ADDR & VZ80_ADDR, -- 24bit address bus to address RAM.
INT_MEM_WRITE_EN => not VZ80_WRn, -- Write to internal RAM.
INT_MEM_WRITE_BYTE_EN => '1', -- Write is 1 byte wide.
INT_MEM_WRITE_HWORD_EN => '0', -- Write is 1 half word wide.
-- Bus request/ack mechanism.
MEM_BUSRQ => ZPU_MEM_BUSRQ, -- Bus request signal. Set to 1 when external control is needed of the memory bus.
MEM_BUSACK => ZPU_MEM_BUSACK, -- Bus acknowledge signal, set to 1 when control of the bus is granted.
-- Core Sharp MZ signals.
ZPU_WAITn => ZPU_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
ZPU_INTn => ZPU_INTn, -- INTn signal for maskable interrupts.
ZPU_NMIn => ZPU_NMIn, -- NMIn non maskable interrupt input.
ZPU_BUSRQn => ZPU_BUSRQn, -- BUSRQn signal to request CPU go into tristate and relinquish bus.
ZPU_M1n => ZPU_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
ZPU_MREQn => ZPU_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
ZPU_IORQn => ZPU_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
ZPU_RDn => ZPU_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
ZPU_WRn => ZPU_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
ZPU_RFSHn => ZPU_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
ZPU_HALTn => ZPU_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
ZPU_BUSACKn => ZPU_BUSACKn, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
ZPU_ADDR => ZPU_ADDR, -- 16 bit address lines.
ZPU_DATA_IN => ZPU_DATA_IN, -- 8 bit data bus in.
ZPU_DATA_OUT => ZPU_DATA_OUT -- 8 bit data bus out.
ZPU80_WAITn => ZPU80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
ZPU80_INTn => ZPU80_INTn, -- INTn signal for maskable interrupts.
ZPU80_NMIn => ZPU80_NMIn, -- NMIn non maskable interrupt input.
ZPU80_BUSRQn => '1', -- BUSRQn signal to request CPU go into tristate and relinquish bus. Not used in this design
ZPU80_M1n => ZPU80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
ZPU80_MREQn => ZPU80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
ZPU80_IORQn => ZPU80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
ZPU80_RDn => ZPU80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
ZPU80_WRn => ZPU80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
ZPU80_RFSHn => ZPU80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
ZPU80_HALTn => ZPU80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
ZPU80_BUSACKn => open, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
ZPU80_ADDR => ZPU80_ADDR, -- 16 bit address lines.
ZPU80_HI_ADDR => ZPU80_VIDEO_ADDR, -- Direct addressing of video memory (bypassing register configuration needed by Sharp MZ host to maintain compatibility or address space restrictions).
ZPU80_DATA_IN => ZPU80_DATA_IN, -- 8 bit data bus in.
ZPU80_DATA_OUT => ZPU80_DATA_OUT, -- 8 bit data bus out.
-- Debug.
DEBUG_TXD_IN => COLOUR_CARRIER_FREQ, -- Serial debug loop, used as output when debug not enabled.
DEBUG_TXD_OUT => COLR_OUT -- Debug serial output when debug enabled. / DEBUG_TXD_IN when debug disabled.
);
-- Direct routed signals to the ZPU when not using mainboard video.
ZPU80_INTn <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_NMIn <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_WAITn <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and ZPU80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and ZPU80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when CORE_VIDEO_RDn = '0'
else
VZ80_DATA when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_RDn = '0'
else (others => '0');
ZPU_MEM_BUSRQ <= '1' when VZ80_BUSRQn = '0' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1') -- Incoming BUSRQ from the K64F requests the ZPU Bus as well.
else '0';
else generate
ZPU80_M1n <= '1';
ZPU80_MREQn <= '1';
ZPU80_IORQn <= '1';
ZPU80_RDn <= '1';
ZPU80_WRn <= '1';
ZPU80_RFSHn <= '1';
ZPU80_HALTn <= '1';
ZPU80_ADDR <= (others => '0');
ZPU80_DATA_OUT <= (others => '0');
ZPU_ADDR <= (others => '0');
ZPU_WRITE_EN <= '0';
ZPU_MEM_BUSACK <= '0';
ZPU_VIDEO_WRn <= '1';
ZPU_VIDEO_RDn <= '1';
end generate;
------------------------------------------------------------------------------------
-- Core Logic
------------------------------------------------------------------------------------
@@ -409,17 +476,34 @@ begin
-- Common Control Registers
--
--
CTRLREGISTERS: process( RESETn, VZ80_CLK, CS_CPU_CFGn, CS_CPLD_CFGn, VZ80_WRn, VZ80_RDn )
variable CPU_CHANGED : unsigned(3 downto 0); -- Flag to indicate the CPU has been changed.
CTRLREGISTERS: process( RESETn, CLOCK_50, VZ80_CLK, CS_CPU_CFGn, CS_CPLD_CFGn, VZ80_WRn, VZ80_RDn )
variable SOFT_RESET_COUNTER : unsigned(3 downto 0); -- Down counter to set reset pulse width.
begin
-- Ensure default values at reset.
if RESETn='0' then
MODE_CPLD_SWITCH <= '0';
CPLD_CFG_DATA <= "00000100";
CPU_CFG_DATA(7 downto 6) <= "00"; -- Dont reset soft CPU selection flag on a reset.
CPU_CHANGED := (others => '0');
CTRLREG_RESET <= '1';
CPU_CFG_DATA(7 downto 6) <= "01"; -- Dont reset soft CPU selection flag on a reset.
MODE_SOFTCPU_RESET <= '0';
SOFT_RESET_COUNTER := (others => '0');
VZ80_CLK_LAST <= (others => '0');
elsif rising_edge(VZ80_CLK) then
elsif rising_edge(CLOCK_50) then
-- Hard reset we must return registers to the same as the CPLD.
if CTRLREG_RESET = '1' then
CTRLREG_RESET <= '0';
if CPLD_CFG_DATA(7) = '0' or CPU_CFG_DATA(5 downto 0) = "000000" then
CPLD_CFG_DATA <= "10000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
end if;
end if;
-- Detect clean edges.
VZ80_CLK_LAST <= VZ80_CLK_LAST(1 downto 0) & VZ80_CLK;
-- As the Z80 clock is originating in the CPLD and it is a mux between the mainboard generated clock and the K64F variable frequency clock, we need to bring it into this FPGA clock
-- domain for better sync and timing. We act on the negative edge as the T80 has slightly different timing thus to remain compatible with the Z80/T80 we clock on the negative edge.
--
if VZ80_CLK_LAST = "000" and VZ80_CLK = '1' then
-- CPLD/CPU Configuration registers.
--
@@ -436,7 +520,8 @@ begin
-- 010000 = Future CPU AAA
-- 100000 = Future CPU AAA
-- All other configurations reserved and default to Hard CPU.
-- [7] - R/W - CPU Reset. When active ('1'), hold the CPU in reset, when inactive, commence the reset completion and CPU run.
-- [6] - R/W - Clock enable. Enable (1) or disable the soft CPU clock.
-- [7] - R/W - CPU Reset. When set to active ('1'), a reset pulse is generated and the bit state returned to 0.
--
-- CPLD:
-- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used
@@ -456,6 +541,7 @@ begin
-- [4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
-- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there
-- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator.
-- [7] - R/W - Preserve configuration over reset (=1) or set to default on reset (=0).
--
if(CS_CPU_CFGn = '0' and VZ80_WRn = '0') then
@@ -464,36 +550,48 @@ begin
-- Check to ensure only one CPU selected, if more than one default to hard CPU. Also check to ensure only instantiated CPU's selected, otherwise default to hard CPU.
--
if (unsigned(VZ80_DATA(5 downto 0)) and (unsigned(VZ80_DATA(5 downto 0))-1)) /= 0 or (VZ80_DATA(5 downto 2) and "1111") /= "0000" then
if (unsigned(VZ80_DATA(5 downto 0)) and (unsigned(VZ80_DATA(5 downto 0))-1)) /= 0 or (VZ80_DATA(5 downto 2) and "1111") /= "0000" or (IMPL_SOFTCPU_Z80 = false and VZ80_DATA(0) = '1') or (IMPL_SOFTCPU_ZPUEVO = false and VZ80_DATA(1) = '1') then
CPU_CFG_DATA(5 downto 0) <= (others => '0');
end if;
-- If the CPU bit has changed, raise the flag to force a reset.
CPU_CHANGED(0) := '1';
elsif(CS_CPLD_CFGn = '0' and VZ80_WRn = '0') then
-- Set the mode switch event flag if the mode changes.
if CPLD_CFG_DATA(2 downto 0) /= VZ80_DATA(2 downto 0) then
MODE_CPLD_SWITCH <= '1';
end if;
-- Store the new value into the register, used for read operations.
CPLD_CFG_DATA <= VZ80_DATA;
else
MODE_CPLD_SWITCH <= '0';
CPU_CHANGED := CPU_CHANGED(2 downto 0) & '0';
end if;
end if;
-- Flag to indicate when a soft CPU has been changed.
if CPU_CHANGED /= 0 then
MODE_CPU_CHANGED <= '1';
-- Soft reset mechanism. If the reset flag was set on the previous cycle, toggle reset active and start a down counter. On zero, toggle reset to inactive.
if CPU_CFG_DATA(7) = '1' then
MODE_SOFTCPU_RESET <= '1';
SOFT_RESET_COUNTER := (others => '1');
CPU_CFG_DATA(7) <= '0';
end if;
if SOFT_RESET_COUNTER /= 0 then
SOFT_RESET_COUNTER := SOFT_RESET_COUNTER - 1;
else
MODE_CPU_CHANGED <= '0';
MODE_SOFTCPU_RESET <= '0';
end if;
end if;
end if;
end process;
-- Mode flags to indicate a CPU is available and selected.
MODEZ80: if IMPL_SOFTCPU_Z80 = true generate
MODE_SOFTCPU_Z80 <= '1' when CPU_CFG_DATA(0) = '1'
else '0';
else generate
MODE_SOFTCPU_Z80 <= '0';
end generate;
MODEEVO: if IMPL_SOFTCPU_ZPUEVO = true generate
MODE_SOFTCPU_ZPUEVO <= '1' when CPU_CFG_DATA(1) = '1'
else '0';
else generate
MODE_SOFTCPU_ZPUEVO <= '0';
end generate;
--
MODE_SOFTCPU_CLKEN <= CPU_CFG_DATA(6);
-- CPU information register.
-- [5:0] - R/O - CPU Availability.
-- 000000 = Hard CPU
@@ -505,7 +603,13 @@ begin
-- 100000 = Future CPU AAA
-- [7:6] - R/O - Soft CPU capable, 01 = capable, /01 = not capable (value to cater for non-FPGA reads which return 11 or 00).
--
CPU_INFO_DATA <= "01" & "000011";
CPU_INFO_DATA <= "01000001" when IMPL_SOFTCPU_Z80 = true and IMPL_SOFTCPU_ZPUEVO = false
else
"01000010" when IMPL_SOFTCPU_Z80 = false and IMPL_SOFTCPU_ZPUEVO = true
else
"01000011" when IMPL_SOFTCPU_Z80 = true and IMPL_SOFTCPU_ZPUEVO = true
else
"00000000";
-- CPLD configuration register range.
CS_IO_6XXn <= '0' when CORE_IORQn = '0' and CORE_ADDR(7 downto 4) = "0110"
@@ -530,74 +634,81 @@ begin
-- Mux the main Z80 control signals for internal use, either use the hard Z80 on the tranZPUter or the soft CPU in the FPGA.
--
CORE_MREQn <= VZ80_MREQn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
CORE_MREQn <= VZ80_MREQn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_MREQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
T80_MREQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_MREQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_MREQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_IORQn <= VZ80_IORQn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
CORE_IORQn <= VZ80_IORQn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_IORQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
T80_IORQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_IORQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_IORQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_RDn <= VZ80_RDn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
CORE_RDn <= VZ80_RDn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_RDn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
T80_RDn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_RDn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_WRn <= VZ80_WRn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
CORE_WRn <= VZ80_WRn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_WRn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
T80_WRn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_WRn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_M1n <= VZ80_M1n when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
CORE_M1n <= VZ80_M1n when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_M1n when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
T80_M1n when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_M1n when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_M1n when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_RFSHn <= VZ80_RFSHn_V_HSYNCn when MODE_CPU_SOFT = '1' or MODE_CPLD_MB_VIDEOn = '1'
CORE_RFSHn <= T80_RFSHn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
T80_RFSHn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_RFSHn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_RFSHn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_HALTn <= VZ80_HALTn_V_VSYNCn when MODE_CPU_SOFT = '1' or MODE_CPLD_MB_VIDEOn = '1'
CORE_HALTn <= T80_HALTn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
T80_HALTn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_HALTn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_HALTn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_VIDEO_WRn <= ZPU_VIDEO_WRn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
CORE_VIDEO_WRn <= '0' when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_WRn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
ZPU_VIDEO_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else
VIDEO_WRn;
CORE_VIDEO_RDn <= ZPU_VIDEO_RDn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
CORE_VIDEO_RDn <= '0' when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
ZPU_VIDEO_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else
VIDEO_RDn;
-- Internal reset dependent on external reset or a change of the SOFT CPU.
CORE_RESETn <= '0' when RESETn = '0'
else '1';
-- Address lines driven according to the CPU being used. Hard CPU = address via CPLD, Soft CPU = address direct.
CORE_ADDR <= VZ80_ADDR when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
CORE_ADDR <= VZ80_ADDR when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_ADDR when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
T80_ADDR when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_ADDR when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else (others => '0');
-- Direct addressing of video memory devices for soft CPU's.
CORE_VIDEO_ADDR <= (others => '0') when CPU_CFG_DATA(1) = '0' or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
-- Hi address lines used for direct external addressing of video memory or BRAM devices for soft CPU's.
CORE_HI_ADDR <= VZ80_HI_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0'
else
ZPU_VIDEO_ADDR;
ZPU80_VIDEO_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else
(others => '0');
-- Data into the core, generally the Video Controller, comes from the CPLD (hard CPU or mainboard) if the soft CPU is disabled else from the soft CPU.
CORE_DATA_IN <= VZ80_DATA when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
CORE_DATA_IN <= VZ80_DATA when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_DATA_OUT when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
T80_DATA_OUT when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_DATA_OUT when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else (others => '0');
-- tranZPUter, hard CPU or mainboard data input. Read directly from the Video Controller if selected, else the data being output from the soft CPU if enabled otherwise
-- tri-state as data is coming from the CPLD.
@@ -605,105 +716,81 @@ begin
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and VZ80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when VIDEO_RDn = '0'
CORE_DATA_OUT when CORE_VIDEO_RDn = '0' -- If the video resources are being read, either by the hard cpu or the K64f, output requested data.
else
T80_DATA_OUT when CPU_CFG_DATA(0) = '1' and T80_WRn = '0' and T80_BUSACKn = '1'
T80_DATA_OUT when MODE_SOFTCPU_Z80 = '1' and T80_WRn = '0' and VZ80_BUSACKni = '1' -- T80 has control over writing data when enabled and bus not requested.
else
ZPU_DATA_OUT when CPU_CFG_DATA(1) = '1' and ZPU_WRn = '0' and ZPU_BUSACKn = '1'
ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_WRn = '0' and VZ80_BUSACKni = '1' -- ZPU Evo Z80 Bus controller has control over writing data when enabled and bus not requested.
else
ZPU_DATA_OUT when CPU_CFG_DATA(1) = '1' and ZPU_MREQn = '0' and ZPU_IORQn = '0' and ZPU_BUSACKn = '1'
ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_MREQn = '0' and ZPU80_IORQn = '0' and VZ80_BUSACKni = '1' -- ZPU has control when writing special control word to CPLD to enable memory mode.
-- When bus requested, K64F has control, reading data from the ZPU BRAM if selected.
else
ZPU_DATA_OUT(7 downto 0) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "11"
else
ZPU_DATA_OUT(15 downto 8) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "10"
else
ZPU_DATA_OUT(23 downto 16) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "01"
else
ZPU_DATA_OUT(31 downto 24) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "00"
else (others => 'Z');
-- Soft CPU data input. Read directly from the Video Controller if selected, at all other times read from the CPLD which in turn reads from the tranZPUter or mainboard.
T80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when VIDEO_RDn = '0'
else
VZ80_DATA when CPU_CFG_DATA(0) = '1' and T80_RDn = '0'
else (others => '0');
ZPU_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and ZPU_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and ZPU_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when VIDEO_RDn = '0'
else
VZ80_DATA when CPU_CFG_DATA(1) = '1' and ZPU_RDn = '0'
else (others => '0');
-- Direct routed signals to the T80 when not using mainboard video.
T80_INTn <= VZ80_INTn_V_R when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_NMIn <= VZ80_NMIn_V_COLR when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_BUSRQn <= VZ80_BUSRQn_V_G when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_WAITn <= VZ80_WAITn_V_B when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
-- Direct routed signals to the ZPU when not using mainboard video.
ZPU_INTn <= VZ80_INTn_V_R when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
ZPU_NMIn <= VZ80_NMIn_V_COLR when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
ZPU_BUSRQn <= VZ80_BUSRQn_V_G when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
ZPU_WAITn <= VZ80_WAITn_V_B when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
-- Internal reset dependent on external reset or a change of the SOFT CPU.
CORE_RESETn <= '0' when RESETn = '0'
else '1';
VZ80_HI_ADDR(16) <= VZ80_A16_WAITn_V_B when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(17) <= VZ80_A17_NMIn_V_COLR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(18) <= VZ80_A18_INTn_V_R when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(19) <= VZ80_A19_HALTn_V_VSYNCn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(20) <= VZ80_A20_RFSHn_V_HSYNCn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(21) <= VWAITn_A21_V_CSYNC when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(22) <= '0';
VZ80_HI_ADDR(23) <= '0';
-- Tri-state controls. If the hard Z80 is being used then tri-state output signals.
VZ80_MREQn <= T80_MREQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_MREQn <= T80_MREQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1' -- When the T80 is selected and not under K64F control, drive the MREQ line output by the T80.
else
ZPU_MREQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_MREQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' -- When the ZPU Evo is selected and not under K64F control, drive the MREQ line output by the T80.
else 'Z';
VZ80_IORQn <= T80_IORQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_IORQn <= T80_IORQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_IORQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_IORQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_RDn <= T80_RDn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_RDn <= T80_RDn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_RDn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_WRn <= T80_WRn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_WRn <= T80_WRn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_WRn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_M1n <= T80_M1n when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_M1n <= T80_M1n when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_M1n when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_M1n when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_RFSHn_V_HSYNCn <= T80_RFSHn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_A20_RFSHn_V_HSYNCn<=T80_RFSHn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_RFSHn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_RFSHn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_HALTn_V_VSYNCn <= T80_HALTn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_A19_HALTn_V_VSYNCn<=T80_HALTn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_HALTn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_HALTn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_ADDR <= T80_ADDR when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
VZ80_ADDR <= T80_ADDR when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_ADDR when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
ZPU80_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else (others => 'Z');
VZ80_BUSACKn <= T80_BUSACKn when CPU_CFG_DATA(0) = '1'
VZ80_BUSACKni <= '0' when MODE_CPU_SOFT = '0' and VZ80_BUSRQn = '0' and MODE_CPLD_MB_VIDEOn = '1' -- When soft CPU's are disabled, generate a BUSACK when FPGA video is enabled and BUSRQ is asserted.
else
ZPU_BUSACKn when CPU_CFG_DATA(1) = '1'
'0' when MODE_SOFTCPU_Z80 = '1' and T80_BUSACKn = '0'
else
'0' when MODE_SOFTCPU_ZPUEVO = '1' and ZPU_MEM_BUSACK = '1' -- The ZPU has priority, when it acknowledges then the Z80 BUS is already idle.
else '1';
VZ80_BUSRQn <= VZ80_BUSRQn_V_G when MODE_CPU_SOFT = '1' or MODE_CPLD_MB_VIDEOn = '1' -- Just a wire, demux of the VZ80_BUSRQn_V_G signal.
else '1';
VZ80_BUSACKn <= VZ80_BUSACKni;
-- Demux the mainboard video signals, these are used when the FPGA video is disabled and the Soft CPU is disabled.
CORE_V_HSYNCn <= VZ80_RFSHn_V_HSYNCn when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_VSYNCn <= VZ80_HALTn_V_VSYNCn when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_COLR <= VZ80_NMIn_V_COLR when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_R <= VZ80_INTn_V_R when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_G <= VZ80_BUSRQn_V_G when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_B <= VZ80_WAITn_V_B when MODE_CPLD_MB_VIDEOn = '0'
else '1';
end architecture;

186
FPGA/SW700/v1.3/coreMZ_constraints.sdc Normal file
View File

@@ -0,0 +1,186 @@
## Generated SDC file "VideoController700_constraints.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {VZ80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {VZ80_CLK}]
create_clock -name {softT80:\CPU0:T80CPU|T80_CLK} -period 50
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
create_generated_clock -name {CPUCLK_75MHZ} -source [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 3 -divide_by 2 -phase 0.00 -master_clock {CLOCK_50} [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|clk[0]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
set_input_delay -add_delay -clock [get_clocks {VZ80_CLK}] 1.000 [get_ports {VZ80_CLK}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIDEO_WRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIDEO_RDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_M1n}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_ADDR[*]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_DATA[*]}]
# set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
# set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
# set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn_A21_V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A20_RFSHn_V_HSYNCn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A19_HALTn_V_VSYNCn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_BUSRQn_V_G}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A16_WAITn_V_B}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A18_INTn_V_R}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A17_NMIn_V_COLR}]
# # Required for the Serial Flash Loader.
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tck}]
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tms}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_DATA[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_M1n}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn_A21_V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A20_RFSHn_V_HSYNCn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A19_HALTn_V_VSYNCn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {HSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {COLR_OUT}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC_OUT}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC_OUTn}]
# # Required for the Serial Flash Loader.
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -setup -end 3
set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -hold -end 2
#**************************************************************
# Set Maximum Delay
#**************************************************************
set_max_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_ADDR[*]}] 100.00
set_max_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 100.00
set_max_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 100.00
set_max_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 100.00
set_max_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 100.00
set_max_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_RDn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_IORQn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VIDEO_RDn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_ADDR[*]} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VWAITn_A21_V_CSYNC} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A20_RFSHn_V_HSYNCn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A19_HALTn_V_VSYNCn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A18_INTn_V_R} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A17_NMIn_V_COLR} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A16_WAITn_V_B} -to [get_ports {VZ80_DATA[*]}] 50.00
#**************************************************************
# Set Minimum Delay
#**************************************************************
set_min_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_ADDR[*]}] 1.00
set_min_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 1.00
set_min_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 1.00
set_min_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_RDn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_IORQn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VIDEO_RDn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_ADDR[*]} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VWAITn_A21_V_CSYNC} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A20_RFSHn_V_HSYNCn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A19_HALTn_V_VSYNCn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A18_INTn_V_R} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A17_NMIn_V_COLR} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A16_WAITn_V_B} -to [get_ports {VZ80_DATA[*]}] 1.00
#
set_false_path -from {softT80:\CPU0:T80CPU|T80_RESETn} -to {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}
set_false_path -from {softT80:\CPU0:T80CPU|T80se:\CPU0:T80CPU|T80:u0|BusAck} -to {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}
set_false_path -from [get_registers {softT80:\CPU0:T80CPU|*}] -to [get_registers {softZPU:\CPU1:ZPUCPU|zpu_core_evo:ZPU0|*}]
set_false_path -from {VZ80_BUSRQn_V_G} -to [get_registers {softZPU:\CPU1:ZPUCPU|zpu_core_evo:ZPU0|*}]
#**************************************************************
# Set Input Transition
#**************************************************************

32
FPGA/SW700/v1.3/coreMZ_pkg.vhd
View File

@@ -1,12 +1,12 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: VideoController700_pkg.vhd
-- Name: coreMZ_pkg.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ700 Video Module v1.0 FPGA configuration file.
-- Description: Share MZ series FPGA core logic.
--
-- This module contains parameters for the Sharp MZ700 Video Module found on the
-- tranZPUter700 card.
-- This module contains parameters for the Sharp MZ series core logic found on the
-- Cyclone IV FPGA in the tranZPUter700 card.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
@@ -54,31 +54,17 @@ package coreMZ_pkg is
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Target hardware modes.
constant MODE_MZ80K : integer := 0;
constant MODE_MZ80C : integer := 1;
constant MODE_MZ1200 : integer := 2;
constant MODE_MZ80A : integer := 3;
constant MODE_MZ700 : integer := 4;
constant MODE_MZ800 : integer := 5;
constant MODE_MZ80B : integer := 6;
constant MODE_MZ2000 : integer := 7;
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Target hardware.
constant CPLD_HOST_HW : integer := MODE_MZ700;
-- Target video hardware.
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
-- Add the Serial Flash Loader megafunction to enable programming of the EPCS64 NV FPGA Boot ROM.
constant IMPL_SFL : boolean := true;
-- Version of hdl.
constant CPLD_VERSION : integer := 2;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
-- Soft CPU's to embed in the core.
--
constant USE_K64F_CTL_CLOCK : integer := 1;
constant IMPL_SOFTCPU_Z80 : boolean := true;
constant IMPL_SOFTCPU_ZPUEVO : boolean := true;
------------------------------------------------------------
-- Function prototypes

53
FPGA/SW700/v1.3/softT80.qip Normal file
View File

@@ -0,0 +1,53 @@
set_global_assignment -name IP_TOOL_NAME "Soft Z80 Processor"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/softT80.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/softT80_pkg.vhd]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) softT80/softT80_constraints.sdc]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/T80/T80.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/T80/T80_ALU.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/T80/T80_MCode.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/T80/T80_Pack.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/T80/T80_Reg.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) softT80/T80/T80se.vhd]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) softT80/AZ80]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/address_latch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/address_mux.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/address_pins.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_bit_select.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_control.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_core.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_flags.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_mux_2.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_mux_2z.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_mux_3z.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_mux_4.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_mux_8.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_prep_daa.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_select.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_shifter_core.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu_slice.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/alu.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/bus_control.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/bus_switch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/clk_delay.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/control_pins_n.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/data_pins.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/data_switch_mask.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/data_switch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/decode_state.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/execute.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/inc_dec_2bit.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/inc_dec.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/interrupts.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/ir.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/memory_ifc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/pin_control.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/pla_decode.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/reg_control.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/reg_file.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/reg_latch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/resets.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/sequencer.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/AZ80/AZ80.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) softT80/NextZ80/NextZ80CPU.v]

194
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@@ -1,194 +0,0 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: softT80.vhd
-- Created: December 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ Series FPGA soft cpu module - T80.
--
-- This module provides a soft CPU to the Sharp MZ Core running on a Sharp MZ-700 with
-- the tranZPUter SW-700 v1.3-> board and will be migrated to the pure FPGA tranZPUter
-- v2.2 board in due course.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: Dec 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library altera;
library altera_mf;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.coreMZ_pkg.all;
use altera.altera_syn_attributes.all;
use altera_mf.all;
entity softT80 is
--generic (
--);
Port (
-- System signals and clocks.
SYS_RESETn : in std_logic; -- System reset.
SYS_CLK : in std_logic; -- System logic clock ~120MHz
Z80_CLK : in std_logic; -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET : in std_logic; -- Software controlled reset.
SW_ENABLE : in std_logic; -- Software controlled CPU enable.
CPU_CHANGED : in std_logic; -- Flag to indicate when software selects a different CPU.
-- Core Sharp MZ signals.
T80_WAITn : in std_logic; -- WAITn signal into the CPU to prolong a memory cycle.
T80_INTn : in std_logic; -- INTn signal for maskable interrupts.
T80_NMIn : in std_logic; -- NMIn non maskable interrupt input.
T80_BUSRQn : in std_logic; -- BUSRQn signal to request CPU go into tristate and relinquish bus.
T80_M1n : out std_logic; -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
T80_MREQn : out std_logic; -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
T80_IORQn : out std_logic; -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
T80_RDn : out std_logic; -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
T80_WRn : out std_logic; -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
T80_RFSHn : out std_logic; -- RFSHn signal to indicate dynamic memory refresh can take place.
T80_HALTn : out std_logic; -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
T80_BUSACKn : out std_logic; -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
T80_ADDR : out std_logic_vector(15 downto 0); -- 16 bit address lines.
T80_DATA_IN : in std_logic_vector(7 downto 0); -- 8 bit data bus in.
T80_DATA_OUT : out std_logic_vector(7 downto 0) -- 8 bit data bus out.
);
END entity;
architecture rtl of softT80 is
-- T80
--
signal T80_RESETn : std_logic;
signal T80_CLK : std_logic;
signal T80_CLKEN : std_logic;
signal T80_BUSACKni : std_logic;
component T80a
generic (
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
Port (
RESET_n : in std_logic;
CLK_n : in std_logic; -- NB. Clock is high active.
CLK_EN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0)
);
end component;
begin
-- Process to clean up the Z80 clock originating from the CPLD to drive the T80.
--
process(SYS_RESETn, SYS_CLK, Z80_CLK)
begin
if SYS_RESETn = '0' then
T80_CLK <= '0';
elsif rising_edge(SYS_CLK) then
if Z80_CLK = '0' then
T80_CLK <= '0';
elsif Z80_CLK = '1' then
T80_CLK <= '1';
end if;
end if;
end process;
-- Process to reliably reset the T80. The T80 is disabled whilst in hard CPU mode, once switched to soft CPU, the reset is
-- activated and held low whilst the CPLD changes its state, the clock is then enabled so that the synchronous reset is latched
-- and then the reset is deactivated.
process(SYS_RESETn, T80_CLK)
variable T80_RESET_COUNTER: unsigned(3 downto 0) := (others => '1');
begin
if SYS_RESETn = '0' then
T80_RESET_COUNTER := (others => '1');
T80_RESETn <= '0';
T80_CLKEN <= '0';
elsif rising_edge(T80_CLK) then
if CPU_CHANGED = '1' or SW_RESET = '1' then
T80_RESET_COUNTER := (others => '1');
T80_RESETn <= '0';
T80_CLKEN <= '0';
end if;
if T80_RESET_COUNTER = 5 and SW_ENABLE = '1' then
T80_CLKEN <= '1';
elsif T80_RESET_COUNTER = 0 then
T80_RESETn <= '1';
end if;
if T80_BUSRQn = '1' and T80_RESET_COUNTER /= 0 then
T80_RESET_COUNTER := T80_RESET_COUNTER - 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------
-- T80 CPU
------------------------------------------------------------------------------------
CPU0 : T80a
generic map (
Mode => 0, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait => 1 --
)
port map (
RESET_n => T80_RESETn, -- Reset signal.
CLK_n => T80_CLK, -- T80a clock, sane as the hardware clock but synchronised to the system clock.
CLK_EN => T80_CLKEN, -- Only clock the T80 when enabled.
WAIT_n => T80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
INT_n => T80_INTn, -- INTn signal for maskable interrupts.
NMI_n => T80_NMIn, -- NMIn non maskable interrupt input.
BUSRQ_n => T80_BUSRQn, -- BUSRQn signal to request CPU go into tristate and relinquish bus.
M1_n => T80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
MREQ_n => T80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
IORQ_n => T80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
RD_n => T80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
WR_n => T80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
RFSH_n => T80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
HALT_n => T80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
BUSAK_n => T80_BUSACKni, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
A => T80_ADDR, -- 16 bit address lines.
DIN => T80_DATA_IN, -- 8 bit data bus in.
DOUT => T80_DATA_OUT -- 8 bit data bus out.
);
-- Combine RESET into BUSACK signal.
T80_BUSACKn <= '0' when T80_RESETn = '0'
else
T80_BUSACKni when T80_RESETn = '1'
else '1';
end architecture;

98
FPGA/SW700/v1.3/softT80/AZ80/AZ80.v Normal file
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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
//============================================================================
// Z80 Top level using the direct module declaration
//============================================================================
`timescale 1us/ 100 ns
module AZ80 (
output wire nM1,
output wire nMREQ,
output wire nIORQ,
output wire nRD,
output wire nWR,
output wire nRFSH,
output wire nHALT,
output wire nBUSACK,
input wire nWAIT,
input wire nINT,
input wire nNMI,
input wire nRESET,
input wire nBUSRQ,
input wire CLK,
output wire [15:0] A,
inout wire [7:0] D
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Include core A-Z80 level connecting all internal modules
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "core.vh"
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Address, Data and Control bus drivers connecting to external pins
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
address_pins address_pins_(
.clk (clk),
.bus_ab_pin_we (bus_ab_pin_we),
.pin_control_oe (pin_control_oe),
.address (address),
.abus (A)
);
data_pins data_pins_(
.bus_db_pin_oe (bus_db_pin_oe),
.bus_db_pin_re (bus_db_pin_re),
.ctl_bus_db_we (ctl_bus_db_we),
.ctl_bus_db_oe (ctl_bus_db_oe),
.clk (clk),
.db (db0),
.D (D)
);
control_pins_n control_pins_(
.busack (busack),
.CPUCLK (CLK),
.pin_control_oe(pin_control_oe),
.in_halt (in_halt),
.pin_nWAIT (nWAIT),
.pin_nBUSRQ (nBUSRQ),
.pin_nINT (nINT),
.pin_nNMI (nNMI),
.pin_nRESET (nRESET),
.nM1_out (nM1_out),
.nRFSH_out (nRFSH_out),
.nRD_out (nRD_out),
.nWR_out (nWR_out),
.nIORQ_out (nIORQ_out),
.nMREQ_out (nMREQ_out),
.nmi (nmi),
.busrq (busrq),
.clk (clk),
.intr (intr),
.mwait (mwait),
.reset_in (reset_in),
.pin_nM1 (nM1),
.pin_nMREQ (nMREQ),
.pin_nIORQ (nIORQ),
.pin_nRD (nRD),
.pin_nWR (nWR),
.pin_nRFSH (nRFSH),
.pin_nHALT (nHALT),
.pin_nBUSACK (nBUSACK)
);
endmodule

141
FPGA/SW700/v1.3/softT80/AZ80/address_latch.v Normal file
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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Feb 27 08:13:14 2016"
module address_latch(
ctl_inc_cy,
ctl_inc_dec,
ctl_al_we,
ctl_inc_limit6,
ctl_bus_inc_oe,
clk,
ctl_apin_mux,
ctl_apin_mux2,
clrpc,
nreset,
address_is_1,
abus,
address
);
input wire ctl_inc_cy;
input wire ctl_inc_dec;
input wire ctl_al_we;
input wire ctl_inc_limit6;
input wire ctl_bus_inc_oe;
input wire clk;
input wire ctl_apin_mux;
input wire ctl_apin_mux2;
input wire clrpc;
input wire nreset;
output wire address_is_1;
inout wire [15:0] abus;
output wire [15:0] address;
wire [15:0] abusz;
reg [15:0] Q;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire [15:0] SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_4;
wire [15:0] SYNTHESIZED_WIRE_5;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
Q[15:0] <= 16'b0000000000000000;
end
else
if (ctl_al_we)
begin
Q[15:0] <= abusz[15:0];
end
end
assign address_is_1 = ~(SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1);
assign abusz = {SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2} & abus;
assign abus[15] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[15] : 1'bz;
assign abus[14] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[14] : 1'bz;
assign abus[13] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[13] : 1'bz;
assign abus[12] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[12] : 1'bz;
assign abus[11] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[11] : 1'bz;
assign abus[10] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[10] : 1'bz;
assign abus[9] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[9] : 1'bz;
assign abus[8] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[8] : 1'bz;
assign abus[7] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[7] : 1'bz;
assign abus[6] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[6] : 1'bz;
assign abus[5] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[5] : 1'bz;
assign abus[4] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[4] : 1'bz;
assign abus[3] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[3] : 1'bz;
assign abus[2] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[2] : 1'bz;
assign abus[1] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[1] : 1'bz;
assign abus[0] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[0] : 1'bz;
assign SYNTHESIZED_WIRE_0 = Q[7] | Q[5] | Q[6] | Q[4] | Q[2] | Q[3] | Q[1] | SYNTHESIZED_WIRE_4;
assign SYNTHESIZED_WIRE_1 = Q[15] | Q[13] | Q[14] | Q[12] | Q[10] | Q[11] | Q[9] | Q[8];
address_mux b2v_inst7(
.select(ctl_apin_mux2),
.in0(SYNTHESIZED_WIRE_5),
.in1(Q),
.out(address));
assign SYNTHESIZED_WIRE_2 = ~clrpc;
inc_dec b2v_inst_inc_dec(
.limit6(ctl_inc_limit6),
.decrement(ctl_inc_dec),
.carry_in(ctl_inc_cy),
.d(Q),
.address(SYNTHESIZED_WIRE_7));
address_mux b2v_mux(
.select(ctl_apin_mux),
.in0(abusz),
.in1(SYNTHESIZED_WIRE_7),
.out(SYNTHESIZED_WIRE_5));
assign SYNTHESIZED_WIRE_4 = ~Q[0];
endmodule

61
FPGA/SW700/v1.3/softT80/AZ80/address_mux.v Normal file
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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Nov 08 09:37:58 2014"
module address_mux(
select,
in0,
in1,
out
);
input wire select;
input wire [15:0] in0;
input wire [15:0] in1;
output wire [15:0] out;
wire SYNTHESIZED_WIRE_0;
wire [15:0] SYNTHESIZED_WIRE_1;
wire [15:0] SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_1 = in0 & {SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0};
assign SYNTHESIZED_WIRE_2 = in1 & {select,select,select,select,select,select,select,select,select,select,select,select,select,select,select,select};
assign SYNTHESIZED_WIRE_0 = ~select;
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
endmodule

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FPGA/SW700/v1.3/softT80/AZ80/address_pins.v Normal file
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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 16 16:56:05 2014"
module address_pins(
clk,
bus_ab_pin_we,
pin_control_oe,
address,
abus
);
input wire clk;
input wire bus_ab_pin_we;
input wire pin_control_oe;
input wire [15:0] address;
output wire [15:0] abus;
wire SYNTHESIZED_WIRE_0;
reg [15:0] DFFE_apin_latch;
always@(posedge SYNTHESIZED_WIRE_0)
begin
if (bus_ab_pin_we)
begin
DFFE_apin_latch[15:0] <= address[15:0];
end
end
assign abus[15] = pin_control_oe ? DFFE_apin_latch[15] : 1'bz;
assign abus[14] = pin_control_oe ? DFFE_apin_latch[14] : 1'bz;
assign abus[13] = pin_control_oe ? DFFE_apin_latch[13] : 1'bz;
assign abus[12] = pin_control_oe ? DFFE_apin_latch[12] : 1'bz;
assign abus[11] = pin_control_oe ? DFFE_apin_latch[11] : 1'bz;
assign abus[10] = pin_control_oe ? DFFE_apin_latch[10] : 1'bz;
assign abus[9] = pin_control_oe ? DFFE_apin_latch[9] : 1'bz;
assign abus[8] = pin_control_oe ? DFFE_apin_latch[8] : 1'bz;
assign abus[7] = pin_control_oe ? DFFE_apin_latch[7] : 1'bz;
assign abus[6] = pin_control_oe ? DFFE_apin_latch[6] : 1'bz;
assign abus[5] = pin_control_oe ? DFFE_apin_latch[5] : 1'bz;
assign abus[4] = pin_control_oe ? DFFE_apin_latch[4] : 1'bz;
assign abus[3] = pin_control_oe ? DFFE_apin_latch[3] : 1'bz;
assign abus[2] = pin_control_oe ? DFFE_apin_latch[2] : 1'bz;
assign abus[1] = pin_control_oe ? DFFE_apin_latch[1] : 1'bz;
assign abus[0] = pin_control_oe ? DFFE_apin_latch[0] : 1'bz;
assign SYNTHESIZED_WIRE_0 = ~clk;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Nov 07 19:44:45 2014"
module alu(
alu_core_R,
alu_core_V,
alu_core_S,
alu_bs_oe,
alu_parity_in,
alu_oe,
alu_shift_oe,
alu_core_cf_in,
alu_op2_oe,
alu_op1_oe,
alu_res_oe,
alu_op1_sel_low,
alu_op1_sel_zero,
alu_op1_sel_bus,
alu_op2_sel_zero,
alu_op2_sel_bus,
alu_op2_sel_lq,
alu_op_low,
alu_shift_in,
alu_sel_op2_neg,
alu_sel_op2_high,
alu_shift_left,
alu_shift_right,
clk,
bsel,
alu_zero,
alu_parity_out,
alu_high_eq_9,
alu_high_gt_9,
alu_low_gt_9,
alu_shift_db0,
alu_shift_db7,
alu_core_cf_out,
alu_sf_out,
alu_yf_out,
alu_xf_out,
alu_vf_out,
db,
test_db_high,
test_db_low
);
input wire alu_core_R;
input wire alu_core_V;
input wire alu_core_S;
input wire alu_bs_oe;
input wire alu_parity_in;
input wire alu_oe;
input wire alu_shift_oe;
input wire alu_core_cf_in;
input wire alu_op2_oe;
input wire alu_op1_oe;
input wire alu_res_oe;
input wire alu_op1_sel_low;
input wire alu_op1_sel_zero;
input wire alu_op1_sel_bus;
input wire alu_op2_sel_zero;
input wire alu_op2_sel_bus;
input wire alu_op2_sel_lq;
input wire alu_op_low;
input wire alu_shift_in;
input wire alu_sel_op2_neg;
input wire alu_sel_op2_high;
input wire alu_shift_left;
input wire alu_shift_right;
input wire clk;
input wire [2:0] bsel;
output wire alu_zero;
output wire alu_parity_out;
output wire alu_high_eq_9;
output wire alu_high_gt_9;
output wire alu_low_gt_9;
output wire alu_shift_db0;
output wire alu_shift_db7;
output wire alu_core_cf_out;
output wire alu_sf_out;
output wire alu_yf_out;
output wire alu_xf_out;
output wire alu_vf_out;
inout wire [7:0] db;
output wire [3:0] test_db_high;
output wire [3:0] test_db_low;
wire [3:0] alu_op1;
wire [3:0] alu_op2;
wire [3:0] db_high;
wire [3:0] db_low;
reg [3:0] op1_high;
reg [3:0] op1_low;
reg [3:0] op2_high;
reg [3:0] op2_low;
wire [3:0] result_hi;
reg [3:0] result_lo;
wire [3:0] SYNTHESIZED_WIRE_0;
wire [3:0] SYNTHESIZED_WIRE_1;
wire [3:0] SYNTHESIZED_WIRE_2;
wire [3:0] SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_35;
wire [3:0] SYNTHESIZED_WIRE_5;
wire [3:0] SYNTHESIZED_WIRE_7;
wire [3:0] SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire [3:0] SYNTHESIZED_WIRE_10;
wire [3:0] SYNTHESIZED_WIRE_11;
wire [3:0] SYNTHESIZED_WIRE_12;
wire [3:0] SYNTHESIZED_WIRE_13;
wire [3:0] SYNTHESIZED_WIRE_14;
wire [3:0] SYNTHESIZED_WIRE_15;
wire [3:0] SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire [3:0] SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_36;
wire SYNTHESIZED_WIRE_20;
wire [3:0] SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_23;
wire [3:0] SYNTHESIZED_WIRE_24;
wire SYNTHESIZED_WIRE_37;
wire SYNTHESIZED_WIRE_26;
wire [3:0] SYNTHESIZED_WIRE_27;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;
wire SYNTHESIZED_WIRE_32;
wire [3:0] SYNTHESIZED_WIRE_33;
wire [3:0] SYNTHESIZED_WIRE_34;
assign db_low[3] = alu_bs_oe ? SYNTHESIZED_WIRE_0[3] : 1'bz;
assign db_low[2] = alu_bs_oe ? SYNTHESIZED_WIRE_0[2] : 1'bz;
assign db_low[1] = alu_bs_oe ? SYNTHESIZED_WIRE_0[1] : 1'bz;
assign db_low[0] = alu_bs_oe ? SYNTHESIZED_WIRE_0[0] : 1'bz;
assign db_high[3] = alu_bs_oe ? SYNTHESIZED_WIRE_1[3] : 1'bz;
assign db_high[2] = alu_bs_oe ? SYNTHESIZED_WIRE_1[2] : 1'bz;
assign db_high[1] = alu_bs_oe ? SYNTHESIZED_WIRE_1[1] : 1'bz;
assign db_high[0] = alu_bs_oe ? SYNTHESIZED_WIRE_1[0] : 1'bz;
alu_core b2v_core(
.cy_in(alu_core_cf_in),
.S(alu_core_S),
.V(alu_core_V),
.R(alu_core_R),
.op1(alu_op1),
.op2(alu_op2),
.cy_out(alu_core_cf_out),
.vf_out(alu_vf_out),
.result(result_hi));
assign db[3] = alu_oe ? db_low[3] : 1'bz;
assign db[2] = alu_oe ? db_low[2] : 1'bz;
assign db[1] = alu_oe ? db_low[1] : 1'bz;
assign db[0] = alu_oe ? db_low[0] : 1'bz;
assign db[7] = alu_oe ? db_high[3] : 1'bz;
assign db[6] = alu_oe ? db_high[2] : 1'bz;
assign db[5] = alu_oe ? db_high[1] : 1'bz;
assign db[4] = alu_oe ? db_high[0] : 1'bz;
alu_bit_select b2v_input_bit_select(
.bsel(bsel),
.bs_out_high(SYNTHESIZED_WIRE_1),
.bs_out_low(SYNTHESIZED_WIRE_0));
alu_shifter_core b2v_input_shift(
.shift_in(alu_shift_in),
.shift_left(alu_shift_left),
.shift_right(alu_shift_right),
.db(db),
.shift_db0(alu_shift_db0),
.shift_db7(alu_shift_db7),
.out_high(SYNTHESIZED_WIRE_34),
.out_low(SYNTHESIZED_WIRE_33));
always@(posedge clk)
begin
if (alu_op_low)
begin
result_lo[3:0] <= result_hi[3:0];
end
end
assign alu_op1 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_17 = ~alu_op_low;
assign db_low[3] = alu_op2_oe ? op2_low[3] : 1'bz;
assign db_low[2] = alu_op2_oe ? op2_low[2] : 1'bz;
assign db_low[1] = alu_op2_oe ? op2_low[1] : 1'bz;
assign db_low[0] = alu_op2_oe ? op2_low[0] : 1'bz;
assign db_high[3] = alu_op2_oe ? op2_high[3] : 1'bz;
assign db_high[2] = alu_op2_oe ? op2_high[2] : 1'bz;
assign db_high[1] = alu_op2_oe ? op2_high[1] : 1'bz;
assign db_high[0] = alu_op2_oe ? op2_high[0] : 1'bz;
assign SYNTHESIZED_WIRE_5 = ~op2_low;
assign SYNTHESIZED_WIRE_7 = ~op2_high;
assign SYNTHESIZED_WIRE_12 = op2_low & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
assign SYNTHESIZED_WIRE_11 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_5;
assign SYNTHESIZED_WIRE_14 = op2_high & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
assign SYNTHESIZED_WIRE_13 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_8 & {SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9};
assign SYNTHESIZED_WIRE_15 = {alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high} & SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
assign alu_op2 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
assign SYNTHESIZED_WIRE_35 = ~alu_sel_op2_neg;
assign SYNTHESIZED_WIRE_9 = ~alu_sel_op2_high;
assign db_low[3] = alu_res_oe ? result_lo[3] : 1'bz;
assign db_low[2] = alu_res_oe ? result_lo[2] : 1'bz;
assign db_low[1] = alu_res_oe ? result_lo[1] : 1'bz;
assign db_low[0] = alu_res_oe ? result_lo[0] : 1'bz;
assign db_high[3] = alu_res_oe ? result_hi[3] : 1'bz;
assign db_high[2] = alu_res_oe ? result_hi[2] : 1'bz;
assign db_high[1] = alu_res_oe ? result_hi[1] : 1'bz;
assign db_high[0] = alu_res_oe ? result_hi[0] : 1'bz;
assign SYNTHESIZED_WIRE_3 = op1_low & {alu_op_low,alu_op_low,alu_op_low,alu_op_low};
assign SYNTHESIZED_WIRE_2 = {SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17} & op1_high;
always@(posedge SYNTHESIZED_WIRE_36)
begin
if (SYNTHESIZED_WIRE_20)
begin
op1_high[3:0] <= SYNTHESIZED_WIRE_18[3:0];
end
end
always@(posedge SYNTHESIZED_WIRE_36)
begin
if (SYNTHESIZED_WIRE_23)
begin
op1_low[3:0] <= SYNTHESIZED_WIRE_21[3:0];
end
end
always@(posedge SYNTHESIZED_WIRE_37)
begin
if (SYNTHESIZED_WIRE_26)
begin
op2_high[3:0] <= SYNTHESIZED_WIRE_24[3:0];
end
end
always@(posedge SYNTHESIZED_WIRE_37)
begin
if (SYNTHESIZED_WIRE_29)
begin
op2_low[3:0] <= SYNTHESIZED_WIRE_27[3:0];
end
end
assign db_low[3] = alu_op1_oe ? op1_low[3] : 1'bz;
assign db_low[2] = alu_op1_oe ? op1_low[2] : 1'bz;
assign db_low[1] = alu_op1_oe ? op1_low[1] : 1'bz;
assign db_low[0] = alu_op1_oe ? op1_low[0] : 1'bz;
assign db_high[3] = alu_op1_oe ? op1_high[3] : 1'bz;
assign db_high[2] = alu_op1_oe ? op1_high[2] : 1'bz;
assign db_high[1] = alu_op1_oe ? op1_high[1] : 1'bz;
assign db_high[0] = alu_op1_oe ? op1_high[0] : 1'bz;
assign SYNTHESIZED_WIRE_36 = ~clk;
assign SYNTHESIZED_WIRE_37 = ~clk;
alu_mux_2z b2v_op1_latch_mux_high(
.sel_a(alu_op1_sel_bus),
.sel_zero(alu_op1_sel_zero),
.a(db_high),
.ena(SYNTHESIZED_WIRE_20),
.Q(SYNTHESIZED_WIRE_18));
alu_mux_3z b2v_op1_latch_mux_low(
.sel_a(alu_op1_sel_bus),
.sel_b(alu_op1_sel_low),
.sel_zero(alu_op1_sel_zero),
.a(db_low),
.b(db_high),
.ena(SYNTHESIZED_WIRE_23),
.Q(SYNTHESIZED_WIRE_21));
alu_mux_3z b2v_op2_latch_mux_high(
.sel_a(alu_op2_sel_bus),
.sel_b(alu_op2_sel_lq),
.sel_zero(alu_op2_sel_zero),
.a(db_high),
.b(db_low),
.ena(SYNTHESIZED_WIRE_26),
.Q(SYNTHESIZED_WIRE_24));
alu_mux_3z b2v_op2_latch_mux_low(
.sel_a(alu_op2_sel_bus),
.sel_b(alu_op2_sel_lq),
.sel_zero(alu_op2_sel_zero),
.a(db_low),
.b(alu_op1),
.ena(SYNTHESIZED_WIRE_29),
.Q(SYNTHESIZED_WIRE_27));
assign alu_parity_out = SYNTHESIZED_WIRE_30 ^ result_hi[0];
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_31 ^ result_hi[1];
assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_32 ^ result_hi[2];
assign SYNTHESIZED_WIRE_32 = alu_parity_in ^ result_hi[3];
alu_prep_daa b2v_prep_daa(
.high(op1_high),
.low(op1_low),
.low_gt_9(alu_low_gt_9),
.high_gt_9(alu_high_gt_9),
.high_eq_9(alu_high_eq_9));
assign db_low[3] = alu_shift_oe ? SYNTHESIZED_WIRE_33[3] : 1'bz;
assign db_low[2] = alu_shift_oe ? SYNTHESIZED_WIRE_33[2] : 1'bz;
assign db_low[1] = alu_shift_oe ? SYNTHESIZED_WIRE_33[1] : 1'bz;
assign db_low[0] = alu_shift_oe ? SYNTHESIZED_WIRE_33[0] : 1'bz;
assign db_high[3] = alu_shift_oe ? SYNTHESIZED_WIRE_34[3] : 1'bz;
assign db_high[2] = alu_shift_oe ? SYNTHESIZED_WIRE_34[2] : 1'bz;
assign db_high[1] = alu_shift_oe ? SYNTHESIZED_WIRE_34[1] : 1'bz;
assign db_high[0] = alu_shift_oe ? SYNTHESIZED_WIRE_34[0] : 1'bz;
assign alu_zero = ~(db_low[2] | db_low[1] | db_low[3] | db_high[1] | db_high[0] | db_high[2] | db_low[0] | db_high[3]);
assign alu_sf_out = db_high[3];
assign alu_yf_out = db_high[1];
assign alu_xf_out = db_low[3];
assign test_db_high = db_high;
assign test_db_low = db_low;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:21:31 2014"
module alu_bit_select(
bsel,
bs_out_high,
bs_out_low
);
input wire [2:0] bsel;
output wire [3:0] bs_out_high;
output wire [3:0] bs_out_low;
wire [3:0] bs_out_high_ALTERA_SYNTHESIZED;
wire [3:0] bs_out_low_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14;
assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2];
assign SYNTHESIZED_WIRE_12 = ~bsel[0];
assign SYNTHESIZED_WIRE_13 = ~bsel[1];
assign SYNTHESIZED_WIRE_14 = ~bsel[2];
assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED;
assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Oct 21 20:41:52 2014"
module alu_control(
alu_shift_db0,
alu_shift_db7,
ctl_shift_en,
alu_low_gt_9,
alu_high_gt_9,
alu_high_eq_9,
ctl_daa_oe,
ctl_alu_op_low,
alu_parity_out,
flags_cf,
flags_zf,
flags_pf,
flags_sf,
ctl_cond_short,
alu_vf_out,
iff2,
ctl_alu_core_hf,
ctl_eval_cond,
repeat_en,
flags_cf_latch,
flags_hf2,
flags_hf,
ctl_66_oe,
clk,
ctl_pf_sel,
op543,
alu_shift_in,
alu_shift_right,
alu_shift_left,
shift_cf_out,
alu_parity_in,
flags_cond_true,
daa_cf_out,
pf_sel,
alu_op_low,
alu_core_cf_in,
db
);
input wire alu_shift_db0;
input wire alu_shift_db7;
input wire ctl_shift_en;
input wire alu_low_gt_9;
input wire alu_high_gt_9;
input wire alu_high_eq_9;
input wire ctl_daa_oe;
input wire ctl_alu_op_low;
input wire alu_parity_out;
input wire flags_cf;
input wire flags_zf;
input wire flags_pf;
input wire flags_sf;
input wire ctl_cond_short;
input wire alu_vf_out;
input wire iff2;
input wire ctl_alu_core_hf;
input wire ctl_eval_cond;
input wire repeat_en;
input wire flags_cf_latch;
input wire flags_hf2;
input wire flags_hf;
input wire ctl_66_oe;
input wire clk;
input wire [1:0] ctl_pf_sel;
input wire [2:0] op543;
output wire alu_shift_in;
output wire alu_shift_right;
output wire alu_shift_left;
output wire shift_cf_out;
output wire alu_parity_in;
output reg flags_cond_true;
output wire daa_cf_out;
output wire pf_sel;
output wire alu_op_low;
output wire alu_core_cf_in;
output wire [7:0] db;
wire condition;
wire [7:0] out;
wire [1:0] sel;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
reg DFFE_latch_pf_tmp;
wire SYNTHESIZED_WIRE_20;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_22;
wire SYNTHESIZED_WIRE_18;
assign alu_op_low = ctl_alu_op_low;
assign daa_cf_out = SYNTHESIZED_WIRE_21;
assign SYNTHESIZED_WIRE_22 = 0;
assign SYNTHESIZED_WIRE_18 = 1;
assign condition = SYNTHESIZED_WIRE_0 ^ SYNTHESIZED_WIRE_1;
assign db[7] = SYNTHESIZED_WIRE_2 ? out[7] : 1'bz;
assign db[6] = SYNTHESIZED_WIRE_2 ? out[6] : 1'bz;
assign db[5] = SYNTHESIZED_WIRE_2 ? out[5] : 1'bz;
assign db[4] = SYNTHESIZED_WIRE_2 ? out[4] : 1'bz;
assign db[3] = SYNTHESIZED_WIRE_2 ? out[3] : 1'bz;
assign db[2] = SYNTHESIZED_WIRE_2 ? out[2] : 1'bz;
assign db[1] = SYNTHESIZED_WIRE_2 ? out[1] : 1'bz;
assign db[0] = SYNTHESIZED_WIRE_2 ? out[0] : 1'bz;
assign alu_shift_right = ctl_shift_en & op543[0];
assign alu_parity_in = ctl_alu_op_low | DFFE_latch_pf_tmp;
assign SYNTHESIZED_WIRE_2 = ctl_66_oe | ctl_daa_oe;
assign sel[0] = op543[1];
assign out[1] = SYNTHESIZED_WIRE_20;
assign out[2] = SYNTHESIZED_WIRE_20;
assign out[5] = SYNTHESIZED_WIRE_21;
assign out[6] = SYNTHESIZED_WIRE_21;
assign alu_shift_left = ctl_shift_en & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_21 = ctl_66_oe | alu_high_gt_9 | flags_cf_latch | SYNTHESIZED_WIRE_8;
assign SYNTHESIZED_WIRE_9 = flags_hf2 | alu_low_gt_9;
assign SYNTHESIZED_WIRE_8 = alu_low_gt_9 & alu_high_eq_9;
assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_9 | ctl_66_oe;
assign SYNTHESIZED_WIRE_0 = ~op543[0];
assign sel[1] = op543[2] & SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_12 = alu_shift_db0 & op543[0];
assign SYNTHESIZED_WIRE_13 = alu_shift_db7 & SYNTHESIZED_WIRE_11;
assign shift_cf_out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;
assign SYNTHESIZED_WIRE_16 = ctl_alu_core_hf & flags_hf;
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_14 & flags_cf;
assign alu_core_cf_in = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
assign SYNTHESIZED_WIRE_14 = ~ctl_alu_core_hf;
always@(posedge clk)
begin
if (ctl_eval_cond)
begin
flags_cond_true <= condition;
end
end
alu_mux_4 b2v_inst_cond_mux(
.in0(flags_zf),
.in1(flags_cf),
.in2(flags_pf),
.in3(flags_sf),
.sel(sel),
.out(SYNTHESIZED_WIRE_1));
alu_mux_4 b2v_inst_pf_sel(
.in0(alu_parity_out),
.in1(alu_vf_out),
.in2(iff2),
.in3(repeat_en),
.sel(ctl_pf_sel),
.out(pf_sel));
alu_mux_8 b2v_inst_shift_mux(
.in0(alu_shift_db7),
.in1(alu_shift_db0),
.in2(flags_cf_latch),
.in3(flags_cf_latch),
.in4(SYNTHESIZED_WIRE_22),
.in5(alu_shift_db7),
.in6(SYNTHESIZED_WIRE_18),
.in7(SYNTHESIZED_WIRE_22),
.sel(op543),
.out(alu_shift_in));
always@(posedge clk)
begin
if (ctl_alu_op_low)
begin
DFFE_latch_pf_tmp <= alu_parity_out;
end
end
assign SYNTHESIZED_WIRE_7 = ~op543[0];
assign SYNTHESIZED_WIRE_11 = ~op543[0];
assign SYNTHESIZED_WIRE_10 = ~ctl_cond_short;
assign out[3] = 0;
assign out[7] = 0;
assign out[0] = 0;
assign out[4] = 0;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:17:04 2014"
module alu_core(
cy_in,
S,
V,
R,
op1,
op2,
cy_out,
vf_out,
result
);
input wire cy_in;
input wire S;
input wire V;
input wire R;
input wire [3:0] op1;
input wire [3:0] op2;
output wire cy_out;
output wire vf_out;
output wire [3:0] result;
wire [3:0] result_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_3;
assign cy_out = SYNTHESIZED_WIRE_3;
alu_slice b2v_alu_slice_bit_0(
.cy_in(cy_in),
.op1(op1[0]),
.op2(op2[0]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[0]),
.cy_out(SYNTHESIZED_WIRE_0));
alu_slice b2v_alu_slice_bit_1(
.cy_in(SYNTHESIZED_WIRE_0),
.op1(op1[1]),
.op2(op2[1]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[1]),
.cy_out(SYNTHESIZED_WIRE_1));
alu_slice b2v_alu_slice_bit_2(
.cy_in(SYNTHESIZED_WIRE_1),
.op1(op1[2]),
.op2(op2[2]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[2]),
.cy_out(SYNTHESIZED_WIRE_5));
alu_slice b2v_alu_slice_bit_3(
.cy_in(SYNTHESIZED_WIRE_5),
.op1(op1[3]),
.op2(op2[3]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[3]),
.cy_out(SYNTHESIZED_WIRE_3));
assign vf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5;
assign result = result_ALTERA_SYNTHESIZED;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 09:01:30 2016"
module alu_flags(
ctl_flags_oe,
ctl_flags_bus,
ctl_flags_alu,
alu_sf_out,
alu_yf_out,
alu_xf_out,
ctl_flags_nf_set,
alu_zero,
shift_cf_out,
alu_core_cf_out,
daa_cf_out,
ctl_flags_cf_set,
ctl_flags_cf_cpl,
pf_sel,
ctl_flags_cf_we,
ctl_flags_sz_we,
ctl_flags_xy_we,
ctl_flags_hf_we,
ctl_flags_pf_we,
ctl_flags_nf_we,
ctl_flags_cf2_we,
ctl_flags_hf_cpl,
ctl_flags_use_cf2,
ctl_flags_hf2_we,
ctl_flags_nf_clr,
ctl_alu_zero_16bit,
clk,
ctl_flags_cf2_sel_shift,
ctl_flags_cf2_sel_daa,
nhold_clk_wait,
flags_sf,
flags_zf,
flags_hf,
flags_pf,
flags_cf,
flags_nf,
flags_cf_latch,
flags_hf2,
db
);
input wire ctl_flags_oe;
input wire ctl_flags_bus;
input wire ctl_flags_alu;
input wire alu_sf_out;
input wire alu_yf_out;
input wire alu_xf_out;
input wire ctl_flags_nf_set;
input wire alu_zero;
input wire shift_cf_out;
input wire alu_core_cf_out;
input wire daa_cf_out;
input wire ctl_flags_cf_set;
input wire ctl_flags_cf_cpl;
input wire pf_sel;
input wire ctl_flags_cf_we;
input wire ctl_flags_sz_we;
input wire ctl_flags_xy_we;
input wire ctl_flags_hf_we;
input wire ctl_flags_pf_we;
input wire ctl_flags_nf_we;
input wire ctl_flags_cf2_we;
input wire ctl_flags_hf_cpl;
input wire ctl_flags_use_cf2;
input wire ctl_flags_hf2_we;
input wire ctl_flags_nf_clr;
input wire ctl_alu_zero_16bit;
input wire clk;
input wire ctl_flags_cf2_sel_shift;
input wire ctl_flags_cf2_sel_daa;
input wire nhold_clk_wait;
output wire flags_sf;
output wire flags_zf;
output wire flags_hf;
output wire flags_pf;
output wire flags_cf;
output wire flags_nf;
output wire flags_cf_latch;
output reg flags_hf2;
inout wire [7:0] db;
reg flags_xf;
reg flags_yf;
wire [1:0] sel;
reg DFFE_inst_latch_hf;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
reg SYNTHESIZED_WIRE_39;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_20;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_22;
reg DFFE_inst_latch_sf;
wire SYNTHESIZED_WIRE_23;
reg DFFE_inst_latch_pf;
reg DFFE_inst_latch_nf;
wire SYNTHESIZED_WIRE_24;
wire SYNTHESIZED_WIRE_25;
wire SYNTHESIZED_WIRE_26;
wire SYNTHESIZED_WIRE_27;
wire SYNTHESIZED_WIRE_28;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_40;
wire SYNTHESIZED_WIRE_32;
wire SYNTHESIZED_WIRE_33;
wire SYNTHESIZED_WIRE_34;
wire SYNTHESIZED_WIRE_35;
wire SYNTHESIZED_WIRE_36;
wire SYNTHESIZED_WIRE_37;
reg DFFE_inst_latch_cf;
reg DFFE_inst_latch_cf2;
wire SYNTHESIZED_WIRE_38;
assign flags_sf = DFFE_inst_latch_sf;
assign flags_zf = SYNTHESIZED_WIRE_39;
assign flags_hf = SYNTHESIZED_WIRE_23;
assign flags_pf = DFFE_inst_latch_pf;
assign flags_cf = SYNTHESIZED_WIRE_24;
assign flags_nf = DFFE_inst_latch_nf;
assign flags_cf_latch = DFFE_inst_latch_cf;
assign SYNTHESIZED_WIRE_38 = 0;
assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
assign SYNTHESIZED_WIRE_8 = ~ctl_flags_cf2_we;
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;
assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39;
assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;
assign SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;
assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
assign SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;
assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;
assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;
assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
always@(posedge clk)
begin
if (SYNTHESIZED_WIRE_27)
begin
DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
end
end
always@(posedge clk)
begin
if (SYNTHESIZED_WIRE_29)
begin
DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
end
end
always@(posedge clk)
begin
if (ctl_flags_hf_we)
begin
DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;
end
end
always@(posedge clk)
begin
if (ctl_flags_hf2_we)
begin
flags_hf2 <= SYNTHESIZED_WIRE_40;
end
end
always@(posedge clk)
begin
if (ctl_flags_nf_we)
begin
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;
end
end
always@(posedge clk)
begin
if (ctl_flags_pf_we)
begin
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;
end
end
always@(posedge clk)
begin
if (ctl_flags_sz_we)
begin
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;
end
end
always@(posedge clk)
begin
if (ctl_flags_xy_we)
begin
flags_xf <= SYNTHESIZED_WIRE_35;
end
end
always@(posedge clk)
begin
if (ctl_flags_xy_we)
begin
flags_yf <= SYNTHESIZED_WIRE_36;
end
end
always@(posedge clk)
begin
if (ctl_flags_sz_we)
begin
SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;
end
end
alu_mux_2 b2v_inst_mux_cf(
.in0(DFFE_inst_latch_cf),
.in1(DFFE_inst_latch_cf2),
.sel1(ctl_flags_use_cf2),
.out(SYNTHESIZED_WIRE_25));
alu_mux_4 b2v_inst_mux_cf2(
.in0(alu_core_cf_out),
.in1(shift_cf_out),
.in2(daa_cf_out),
.in3(SYNTHESIZED_WIRE_38),
.sel(sel),
.out(SYNTHESIZED_WIRE_28));
assign sel[0] = ctl_flags_cf2_sel_shift;
assign sel[1] = ctl_flags_cf2_sel_daa;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:10:35 2014"
module alu_mux_2(
sel1,
in1,
in0,
out
);
input wire sel1;
input wire in1;
input wire in0;
output wire out;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_2 = in0 & SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_1 = in1 & sel1;
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_0 = ~sel1;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Oct 31 21:18:33 2014"
module alu_mux_2z(
sel_a,
sel_zero,
a,
ena,
Q
);
input wire sel_a;
input wire sel_zero;
input wire [3:0] a;
output wire ena;
output wire [3:0] Q;
wire [3:0] SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_0 = a & {sel_a,sel_a,sel_a,sel_a};
assign ena = sel_a | sel_zero;
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
assign SYNTHESIZED_WIRE_1 = ~sel_zero;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Oct 31 21:08:42 2014"
module alu_mux_3z(
sel_zero,
sel_a,
sel_b,
a,
b,
ena,
Q
);
input wire sel_zero;
input wire sel_a;
input wire sel_b;
input wire [3:0] a;
input wire [3:0] b;
output wire ena;
output wire [3:0] Q;
wire [3:0] SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire [3:0] SYNTHESIZED_WIRE_2;
wire [3:0] SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_3 = a & {sel_a,sel_a,sel_a,sel_a};
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
assign SYNTHESIZED_WIRE_1 = ~sel_zero;
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
assign ena = sel_a | sel_b | sel_zero;
assign SYNTHESIZED_WIRE_2 = b & {sel_b,sel_b,sel_b,sel_b};
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:05:38 2014"
module alu_mux_4(
in0,
in1,
in2,
in3,
sel,
out
);
input wire in0;
input wire in1;
input wire in2;
input wire in3;
input wire [1:0] sel;
output wire out;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9 & in0;
assign SYNTHESIZED_WIRE_7 = sel[0] & SYNTHESIZED_WIRE_9 & in1;
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 & sel[1] & in2;
assign SYNTHESIZED_WIRE_6 = sel[0] & sel[1] & in3;
assign out = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_8 = ~sel[0];
assign SYNTHESIZED_WIRE_9 = ~sel[1];
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:04:13 2014"
module alu_mux_8(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
input wire in0;
input wire in1;
input wire in2;
input wire in3;
input wire in4;
input wire in5;
input wire in6;
input wire in7;
input wire [2:0] sel;
output wire out;
wire SYNTHESIZED_WIRE_20;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_22;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in0;
assign SYNTHESIZED_WIRE_14 = sel[0] & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in1;
assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_20 & sel[1] & SYNTHESIZED_WIRE_22 & in2;
assign SYNTHESIZED_WIRE_15 = sel[0] & sel[1] & SYNTHESIZED_WIRE_22 & in3;
assign SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & sel[2] & in4;
assign SYNTHESIZED_WIRE_16 = sel[0] & SYNTHESIZED_WIRE_21 & sel[2] & in5;
assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 & sel[1] & sel[2] & in6;
assign SYNTHESIZED_WIRE_19 = sel[0] & sel[1] & sel[2] & in7;
assign out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_20 = ~sel[0];
assign SYNTHESIZED_WIRE_21 = ~sel[1];
assign SYNTHESIZED_WIRE_22 = ~sel[2];
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:01:36 2014"
module alu_prep_daa(
high,
low,
low_gt_9,
high_eq_9,
high_gt_9
);
input wire [3:0] high;
input wire [3:0] low;
output wire low_gt_9;
output wire high_eq_9;
output wire high_gt_9;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
assign SYNTHESIZED_WIRE_4 = ~high[2];
assign SYNTHESIZED_WIRE_1 = low[3] & low[2];
assign SYNTHESIZED_WIRE_3 = high[3] & high[2];
assign SYNTHESIZED_WIRE_0 = low[3] & low[1];
assign low_gt_9 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_2 = high[3] & high[1];
assign high_gt_9 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_5 = ~high[1];
assign high_eq_9 = high[3] & high[0] & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 11:59:39 2014"
module alu_select(
ctl_alu_oe,
ctl_alu_shift_oe,
ctl_alu_op2_oe,
ctl_alu_res_oe,
ctl_alu_op1_oe,
ctl_alu_bs_oe,
ctl_alu_op1_sel_bus,
ctl_alu_op1_sel_low,
ctl_alu_op1_sel_zero,
ctl_alu_op2_sel_zero,
ctl_alu_op2_sel_bus,
ctl_alu_op2_sel_lq,
ctl_alu_sel_op2_neg,
ctl_alu_sel_op2_high,
ctl_alu_core_R,
ctl_alu_core_V,
ctl_alu_core_S,
alu_oe,
alu_shift_oe,
alu_op2_oe,
alu_res_oe,
alu_op1_oe,
alu_bs_oe,
alu_op1_sel_bus,
alu_op1_sel_low,
alu_op1_sel_zero,
alu_op2_sel_zero,
alu_op2_sel_bus,
alu_op2_sel_lq,
alu_sel_op2_neg,
alu_sel_op2_high,
alu_core_R,
alu_core_V,
alu_core_S
);
input wire ctl_alu_oe;
input wire ctl_alu_shift_oe;
input wire ctl_alu_op2_oe;
input wire ctl_alu_res_oe;
input wire ctl_alu_op1_oe;
input wire ctl_alu_bs_oe;
input wire ctl_alu_op1_sel_bus;
input wire ctl_alu_op1_sel_low;
input wire ctl_alu_op1_sel_zero;
input wire ctl_alu_op2_sel_zero;
input wire ctl_alu_op2_sel_bus;
input wire ctl_alu_op2_sel_lq;
input wire ctl_alu_sel_op2_neg;
input wire ctl_alu_sel_op2_high;
input wire ctl_alu_core_R;
input wire ctl_alu_core_V;
input wire ctl_alu_core_S;
output wire alu_oe;
output wire alu_shift_oe;
output wire alu_op2_oe;
output wire alu_res_oe;
output wire alu_op1_oe;
output wire alu_bs_oe;
output wire alu_op1_sel_bus;
output wire alu_op1_sel_low;
output wire alu_op1_sel_zero;
output wire alu_op2_sel_zero;
output wire alu_op2_sel_bus;
output wire alu_op2_sel_lq;
output wire alu_sel_op2_neg;
output wire alu_sel_op2_high;
output wire alu_core_R;
output wire alu_core_V;
output wire alu_core_S;
assign alu_oe = ctl_alu_oe;
assign alu_shift_oe = ctl_alu_shift_oe;
assign alu_op2_oe = ctl_alu_op2_oe;
assign alu_res_oe = ctl_alu_res_oe;
assign alu_op1_oe = ctl_alu_op1_oe;
assign alu_bs_oe = ctl_alu_bs_oe;
assign alu_op1_sel_bus = ctl_alu_op1_sel_bus;
assign alu_op1_sel_low = ctl_alu_op1_sel_low;
assign alu_op1_sel_zero = ctl_alu_op1_sel_zero;
assign alu_op2_sel_zero = ctl_alu_op2_sel_zero;
assign alu_op2_sel_bus = ctl_alu_op2_sel_bus;
assign alu_op2_sel_lq = ctl_alu_op2_sel_lq;
assign alu_sel_op2_neg = ctl_alu_sel_op2_neg;
assign alu_sel_op2_high = ctl_alu_sel_op2_high;
assign alu_core_R = ctl_alu_core_R;
assign alu_core_V = ctl_alu_core_V;
assign alu_core_S = ctl_alu_core_S;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 11:55:31 2014"
module alu_shifter_core(
shift_in,
shift_right,
shift_left,
db,
shift_db0,
shift_db7,
out_high,
out_low
);
input wire shift_in;
input wire shift_right;
input wire shift_left;
input wire [7:0] db;
output wire shift_db0;
output wire shift_db7;
output wire [3:0] out_high;
output wire [3:0] out_low;
wire [3:0] out_high_ALTERA_SYNTHESIZED;
wire [3:0] out_low_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_32;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_20;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_22;
wire SYNTHESIZED_WIRE_23;
wire SYNTHESIZED_WIRE_24;
wire SYNTHESIZED_WIRE_25;
wire SYNTHESIZED_WIRE_26;
wire SYNTHESIZED_WIRE_27;
wire SYNTHESIZED_WIRE_28;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;
assign shift_db0 = db[0];
assign shift_db7 = db[7];
assign SYNTHESIZED_WIRE_9 = shift_in & shift_left;
assign SYNTHESIZED_WIRE_8 = db[0] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_10 = db[1] & shift_right;
assign SYNTHESIZED_WIRE_12 = db[0] & shift_left;
assign SYNTHESIZED_WIRE_11 = db[1] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_13 = db[2] & shift_right;
assign SYNTHESIZED_WIRE_15 = db[1] & shift_left;
assign SYNTHESIZED_WIRE_14 = db[2] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_16 = db[3] & shift_right;
assign SYNTHESIZED_WIRE_18 = db[2] & shift_left;
assign SYNTHESIZED_WIRE_17 = db[3] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_19 = db[4] & shift_right;
assign SYNTHESIZED_WIRE_21 = db[3] & shift_left;
assign SYNTHESIZED_WIRE_20 = db[4] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_22 = db[5] & shift_right;
assign SYNTHESIZED_WIRE_24 = db[4] & shift_left;
assign SYNTHESIZED_WIRE_23 = db[5] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_25 = db[6] & shift_right;
assign SYNTHESIZED_WIRE_27 = db[5] & shift_left;
assign SYNTHESIZED_WIRE_26 = db[6] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_28 = db[7] & shift_right;
assign SYNTHESIZED_WIRE_30 = db[6] & shift_left;
assign SYNTHESIZED_WIRE_29 = db[7] & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_31 = shift_in & shift_right;
assign SYNTHESIZED_WIRE_32 = ~(shift_right | shift_left);
assign out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
assign out_low_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;
assign out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
assign out_low_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;
assign out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_20 | SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
assign out_high_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24 | SYNTHESIZED_WIRE_25;
assign out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_26 | SYNTHESIZED_WIRE_27 | SYNTHESIZED_WIRE_28;
assign out_high_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_29 | SYNTHESIZED_WIRE_30 | SYNTHESIZED_WIRE_31;
assign out_high = out_high_ALTERA_SYNTHESIZED;
assign out_low = out_low_ALTERA_SYNTHESIZED;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 11:51:12 2014"
module alu_slice(
op2,
op1,
cy_in,
R,
S,
V,
cy_out,
result
);
input wire op2;
input wire op1;
input wire cy_in;
input wire R;
input wire S;
input wire V;
output wire cy_out;
output wire result;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
assign SYNTHESIZED_WIRE_0 = op2 | cy_in | op1;
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_4 = cy_in & op2 & op1;
assign result = ~SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_2 = ~(SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4);
assign SYNTHESIZED_WIRE_5 = op2 | op1;
assign SYNTHESIZED_WIRE_7 = cy_in & SYNTHESIZED_WIRE_5;
assign SYNTHESIZED_WIRE_8 = op1 & op2;
assign cy_out = ~(R | SYNTHESIZED_WIRE_10);
assign SYNTHESIZED_WIRE_10 = ~(SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8 | S);
assign SYNTHESIZED_WIRE_1 = V | SYNTHESIZED_WIRE_10;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Feb 26 22:25:37 2016"
module bus_control(
ctl_bus_ff_oe,
ctl_bus_zero_oe,
db
);
input wire ctl_bus_ff_oe;
input wire ctl_bus_zero_oe;
inout wire [7:0] db;
wire [7:0] bus;
wire [7:0] vcc;
wire SYNTHESIZED_WIRE_0;
assign db[7] = SYNTHESIZED_WIRE_0 ? bus[7] : 1'bz;
assign db[6] = SYNTHESIZED_WIRE_0 ? bus[6] : 1'bz;
assign db[5] = SYNTHESIZED_WIRE_0 ? bus[5] : 1'bz;
assign db[4] = SYNTHESIZED_WIRE_0 ? bus[4] : 1'bz;
assign db[3] = SYNTHESIZED_WIRE_0 ? bus[3] : 1'bz;
assign db[2] = SYNTHESIZED_WIRE_0 ? bus[2] : 1'bz;
assign db[1] = SYNTHESIZED_WIRE_0 ? bus[1] : 1'bz;
assign db[0] = SYNTHESIZED_WIRE_0 ? bus[0] : 1'bz;
assign bus = {ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe} & vcc;
assign SYNTHESIZED_WIRE_0 = ctl_bus_ff_oe | ctl_bus_zero_oe;
assign vcc = 8'b11111111;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
//============================================================================
// Bus switch in bus A-Z80 CPU
//
// Copyright 2014, 2016 Goran Devic
//
// This module provides control data bus switch signals. The sole purpose of
// having these wires defined in this module is to get all control signals
// (which are processed by genglobals.py) to appear in the list of global
// control signals ("globals.vh") for consistency.
//============================================================================
module bus_switch
(
input wire ctl_sw_1u, // Control input for the SW1 upstream
input wire ctl_sw_1d, // Control input for the SW1 downstream
input wire ctl_sw_2u, // Control input for the SW2 upstream
input wire ctl_sw_2d, // Control input for the SW2 downstream
input wire ctl_sw_mask543_en, // Enables masking [5:3] on the data bus switch 1
//--------------------------------------------------------------------
output wire bus_sw_1u, // SW1 upstream
output wire bus_sw_1d, // SW1 downstream
output wire bus_sw_2u, // SW2 upstream
output wire bus_sw_2d, // SW2 downstream
output wire bus_sw_mask543_en // Affects SW1 downstream
);
assign bus_sw_1u = ctl_sw_1u;
assign bus_sw_1d = ctl_sw_1d;
assign bus_sw_2u = ctl_sw_2u;
assign bus_sw_2d = ctl_sw_2d;
assign bus_sw_mask543_en = ctl_sw_mask543_en;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:59:31 2016"
module clk_delay(
clk,
in_intr,
nreset,
T1,
latch_wait,
mwait,
M1,
busrq,
setM1,
hold_clk_iorq,
hold_clk_wait,
iorq_Tw,
busack,
pin_control_oe,
hold_clk_busrq,
nhold_clk_wait
);
input wire clk;
input wire in_intr;
input wire nreset;
input wire T1;
input wire latch_wait;
input wire mwait;
input wire M1;
input wire busrq;
input wire setM1;
output wire hold_clk_iorq;
output wire hold_clk_wait;
output wire iorq_Tw;
output wire busack;
output wire pin_control_oe;
output wire hold_clk_busrq;
output wire nhold_clk_wait;
reg hold_clk_busrq_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_1;
reg DFF_inst5;
reg SYNTHESIZED_WIRE_7;
reg SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
reg SYNTHESIZED_WIRE_9;
assign hold_clk_wait = SYNTHESIZED_WIRE_9;
assign iorq_Tw = DFF_inst5;
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_9 <= 0;
end
else
if (SYNTHESIZED_WIRE_1)
begin
SYNTHESIZED_WIRE_9 <= mwait;
end
end
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_8 <= 0;
end
else
begin
SYNTHESIZED_WIRE_8 <= busrq;
end
end
assign hold_clk_iorq = DFF_inst5 | SYNTHESIZED_WIRE_7;
assign busack = SYNTHESIZED_WIRE_8 & hold_clk_busrq_ALTERA_SYNTHESIZED;
assign pin_control_oe = SYNTHESIZED_WIRE_3 & nreset;
assign SYNTHESIZED_WIRE_5 = hold_clk_busrq_ALTERA_SYNTHESIZED | setM1;
assign SYNTHESIZED_WIRE_3 = ~hold_clk_busrq_ALTERA_SYNTHESIZED;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_7 <= 0;
end
else
begin
SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_4;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
hold_clk_busrq_ALTERA_SYNTHESIZED <= 0;
end
else
if (SYNTHESIZED_WIRE_5)
begin
hold_clk_busrq_ALTERA_SYNTHESIZED <= SYNTHESIZED_WIRE_8;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFF_inst5 <= 0;
end
else
begin
DFF_inst5 <= SYNTHESIZED_WIRE_7;
end
end
assign SYNTHESIZED_WIRE_4 = in_intr & M1 & T1;
assign SYNTHESIZED_WIRE_1 = latch_wait | SYNTHESIZED_WIRE_9;
assign nhold_clk_wait = ~SYNTHESIZED_WIRE_9;
assign SYNTHESIZED_WIRE_6 = ~clk;
assign hold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 16 23:06:14 2014"
module control_pins_n(
busack,
CPUCLK,
pin_control_oe,
in_halt,
pin_nWAIT,
pin_nBUSRQ,
pin_nINT,
pin_nNMI,
pin_nRESET,
nM1_out,
nRFSH_out,
nRD_out,
nWR_out,
nIORQ_out,
nMREQ_out,
nmi,
busrq,
clk,
intr,
mwait,
reset_in,
pin_nM1,
pin_nMREQ,
pin_nIORQ,
pin_nRD,
pin_nWR,
pin_nRFSH,
pin_nHALT,
pin_nBUSACK
);
input wire busack;
input wire CPUCLK;
input wire pin_control_oe;
input wire in_halt;
input wire pin_nWAIT;
input wire pin_nBUSRQ;
input wire pin_nINT;
input wire pin_nNMI;
input wire pin_nRESET;
input wire nM1_out;
input wire nRFSH_out;
input wire nRD_out;
input wire nWR_out;
input wire nIORQ_out;
input wire nMREQ_out;
output wire nmi;
output wire busrq;
output wire clk;
output wire intr;
output wire mwait;
output wire reset_in;
output wire pin_nM1;
output wire pin_nMREQ;
output wire pin_nIORQ;
output wire pin_nRD;
output wire pin_nWR;
output wire pin_nRFSH;
output wire pin_nHALT;
output wire pin_nBUSACK;
assign clk = CPUCLK;
assign pin_nM1 = nM1_out;
assign pin_nRFSH = nRFSH_out;
assign pin_nMREQ = pin_control_oe ? nMREQ_out : 1'bz;
assign pin_nIORQ = pin_control_oe ? nIORQ_out : 1'bz;
assign pin_nRD = pin_control_oe ? nRD_out : 1'bz;
assign pin_nWR = pin_control_oe ? nWR_out : 1'bz;
assign busrq = ~pin_nBUSRQ;
assign pin_nHALT = ~in_halt;
assign mwait = ~pin_nWAIT;
assign pin_nBUSACK = ~busack;
assign intr = ~pin_nINT;
assign nmi = ~pin_nNMI;
assign reset_in = ~pin_nRESET;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
//============================================================================
// A-Z80 core, instantiates and connects all internal blocks.
//
// This file is included by the "z80_top_ifc_n" and "z80_top_direct" providing
// interface binding and direct (no interface) binding.
//============================================================================
// Include a list of top-level signal wires
`include "globals.vh"
// Specific to simulation, some modules in the schematics need to be pre-initialized
// to avoid starting simulations with unknown values in selected flip flops.
reg fpga_reset = 1;
always @(posedge clk)
begin
fpga_reset <= 0;
end
// Define internal data bus partitions segmented by data bus switches
wire [7:0] db0; // Segment connecting data pins and IR
wire [7:0] db1; // Segment leading to the ALU
wire [7:0] db2; // Segment with msb part of the register address-side interface
wire [7:0] db_hi_as; // Register file data bus segment high byte
wire [7:0] db_lo_as; // Register file data bus segment low byte
wire [6:0] prefix; // Instruction decode PLA prefix bitfield
assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };
wire nM1_int; // External pins timing control
assign nM1_int = !(setM1 | (fFetch & T1));
`include "coremodules.vh"
// Data path within the CPU in various forms, ending with data pins
data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
// Data switch SW1 with the data mask
data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
/* This SystemVerilog-style code is kept for future reference
// Control block
clk_delay clk_delay_( .* );
decode_state decode_state_( .* );
execute execute_( .* );
interrupts interrupts_( .*, .db(db0[4:3]) );
ir ir_( .*, .db(db0[7:0]) );
pin_control pin_control_( .* );
pla_decode pla_decode_( .* );
resets resets_( .* );
sequencer sequencer_( .* );
// ALU and ALU control, including the flags
alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );
alu_select alu_select_( .* );
alu_flags alu_flags_( .*, .db(db1[7:0]) );
alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );
// Register file and register control
reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );
reg_control reg_control_( .* );
// Address latch and the incrementer
address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );
// Misc bus
bus_control bus_control_( .*, .db(db0[7:0]) );
bus_switch bus_switch_( .* );
// Timing control of the external pins
memory_ifc memory_ifc_( .* );
*/

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Automatically generated by gencoremodules.py
clk_delay clk_delay_(
.clk (clk),
.in_intr (in_intr),
.nreset (nreset),
.T1 (T1),
.latch_wait (latch_wait),
.mwait (mwait),
.M1 (M1),
.busrq (busrq),
.setM1 (setM1),
.hold_clk_iorq (hold_clk_iorq),
.hold_clk_wait (hold_clk_wait),
.iorq_Tw (iorq_Tw),
.busack (busack),
.pin_control_oe (pin_control_oe),
.hold_clk_busrq (hold_clk_busrq),
.nhold_clk_wait (nhold_clk_wait)
);
decode_state decode_state_(
.ctl_state_iy_set (ctl_state_iy_set),
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
.ctl_state_ixiy_we (ctl_state_ixiy_we),
.ctl_state_halt_set (ctl_state_halt_set),
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
.ctl_state_alu (ctl_state_alu),
.clk (clk),
.address_is_1 (address_is_1),
.ctl_repeat_we (ctl_repeat_we),
.in_intr (in_intr),
.in_nmi (in_nmi),
.nreset (nreset),
.ctl_state_tbl_we (ctl_state_tbl_we),
.nhold_clk_wait (nhold_clk_wait),
.in_halt (in_halt),
.table_cb (table_cb),
.table_ed (table_ed),
.table_xx (table_xx),
.use_ix (use_ix),
.use_ixiy (use_ixiy),
.in_alu (in_alu),
.repeat_en (repeat_en)
);
execute execute_(
.ctl_state_iy_set (ctl_state_iy_set),
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
.ctl_state_ixiy_we (ctl_state_ixiy_we),
.ctl_state_halt_set (ctl_state_halt_set),
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
.ctl_state_alu (ctl_state_alu),
.ctl_repeat_we (ctl_repeat_we),
.ctl_state_tbl_we (ctl_state_tbl_we),
.ctl_iff1_iff2 (ctl_iff1_iff2),
.ctl_iffx_we (ctl_iffx_we),
.ctl_iffx_bit (ctl_iffx_bit),
.ctl_im_we (ctl_im_we),
.ctl_no_ints (ctl_no_ints),
.ctl_ir_we (ctl_ir_we),
.ctl_mRead (ctl_mRead),
.ctl_mWrite (ctl_mWrite),
.ctl_iorw (ctl_iorw),
.ctl_shift_en (ctl_shift_en),
.ctl_daa_oe (ctl_daa_oe),
.ctl_alu_op_low (ctl_alu_op_low),
.ctl_cond_short (ctl_cond_short),
.ctl_alu_core_hf (ctl_alu_core_hf),
.ctl_eval_cond (ctl_eval_cond),
.ctl_66_oe (ctl_66_oe),
.ctl_pf_sel (ctl_pf_sel),
.ctl_alu_oe (ctl_alu_oe),
.ctl_alu_shift_oe (ctl_alu_shift_oe),
.ctl_alu_op2_oe (ctl_alu_op2_oe),
.ctl_alu_res_oe (ctl_alu_res_oe),
.ctl_alu_op1_oe (ctl_alu_op1_oe),
.ctl_alu_bs_oe (ctl_alu_bs_oe),
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
.ctl_alu_core_R (ctl_alu_core_R),
.ctl_alu_core_V (ctl_alu_core_V),
.ctl_alu_core_S (ctl_alu_core_S),
.ctl_flags_oe (ctl_flags_oe),
.ctl_flags_bus (ctl_flags_bus),
.ctl_flags_alu (ctl_flags_alu),
.ctl_flags_nf_set (ctl_flags_nf_set),
.ctl_flags_cf_set (ctl_flags_cf_set),
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
.ctl_flags_cf_we (ctl_flags_cf_we),
.ctl_flags_sz_we (ctl_flags_sz_we),
.ctl_flags_xy_we (ctl_flags_xy_we),
.ctl_flags_hf_we (ctl_flags_hf_we),
.ctl_flags_pf_we (ctl_flags_pf_we),
.ctl_flags_nf_we (ctl_flags_nf_we),
.ctl_flags_cf2_we (ctl_flags_cf2_we),
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
.ctl_flags_hf2_we (ctl_flags_hf2_we),
.ctl_flags_nf_clr (ctl_flags_nf_clr),
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
.ctl_sw_4u (ctl_sw_4u),
.ctl_reg_in_hi (ctl_reg_in_hi),
.ctl_reg_in_lo (ctl_reg_in_lo),
.ctl_reg_out_lo (ctl_reg_out_lo),
.ctl_reg_out_hi (ctl_reg_out_hi),
.ctl_reg_exx (ctl_reg_exx),
.ctl_reg_ex_af (ctl_reg_ex_af),
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
.ctl_reg_use_sp (ctl_reg_use_sp),
.ctl_reg_sel_pc (ctl_reg_sel_pc),
.ctl_reg_sel_ir (ctl_reg_sel_ir),
.ctl_reg_sel_wz (ctl_reg_sel_wz),
.ctl_reg_gp_we (ctl_reg_gp_we),
.ctl_reg_not_pc (ctl_reg_not_pc),
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
.ctl_reg_sys_we (ctl_reg_sys_we),
.ctl_sw_4d (ctl_sw_4d),
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
.ctl_reg_gp_sel (ctl_reg_gp_sel),
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
.ctl_inc_cy (ctl_inc_cy),
.ctl_inc_dec (ctl_inc_dec),
.ctl_al_we (ctl_al_we),
.ctl_inc_limit6 (ctl_inc_limit6),
.ctl_bus_inc_oe (ctl_bus_inc_oe),
.ctl_apin_mux (ctl_apin_mux),
.ctl_apin_mux2 (ctl_apin_mux2),
.ctl_bus_ff_oe (ctl_bus_ff_oe),
.ctl_bus_zero_oe (ctl_bus_zero_oe),
.ctl_sw_1u (ctl_sw_1u),
.ctl_sw_1d (ctl_sw_1d),
.ctl_sw_2u (ctl_sw_2u),
.ctl_sw_2d (ctl_sw_2d),
.ctl_sw_mask543_en (ctl_sw_mask543_en),
.ctl_bus_db_we (ctl_bus_db_we),
.ctl_bus_db_oe (ctl_bus_db_oe),
.nextM (nextM),
.setM1 (setM1),
.fFetch (fFetch),
.fMRead (fMRead),
.fMWrite (fMWrite),
.fIORead (fIORead),
.fIOWrite (fIOWrite),
.pla (pla),
.in_intr (in_intr),
.in_nmi (in_nmi),
.in_halt (in_halt),
.im1 (im1),
.im2 (im2),
.use_ixiy (use_ixiy),
.flags_cond_true (flags_cond_true),
.repeat_en (repeat_en),
.flags_zf (flags_zf),
.flags_nf (flags_nf),
.flags_sf (flags_sf),
.flags_cf (flags_cf),
.M1 (M1),
.M2 (M2),
.M3 (M3),
.M4 (M4),
.M5 (M5),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.T4 (T4),
.T5 (T5),
.T6 (T6)
);
interrupts interrupts_(
.ctl_iff1_iff2 (ctl_iff1_iff2),
.nmi (nmi),
.setM1 (setM1),
.intr (intr),
.ctl_iffx_we (ctl_iffx_we),
.ctl_iffx_bit (ctl_iffx_bit),
.ctl_im_we (ctl_im_we),
.clk (clk),
.ctl_no_ints (ctl_no_ints),
.nreset (nreset),
.db (db0[4:3]),
.iff2 (iff2),
.im1 (im1),
.im2 (im2),
.in_nmi (in_nmi),
.in_intr (in_intr)
);
ir ir_(
.ctl_ir_we (ctl_ir_we),
.clk (clk),
.nreset (nreset),
.nhold_clk_wait (nhold_clk_wait),
.db (db0[7:0]),
.opcode (opcode)
);
pin_control pin_control_(
.fFetch (fFetch),
.fMRead (fMRead),
.fMWrite (fMWrite),
.fIORead (fIORead),
.fIOWrite (fIOWrite),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.T4 (T4),
.bus_ab_pin_we (bus_ab_pin_we),
.bus_db_pin_oe (bus_db_pin_oe),
.bus_db_pin_re (bus_db_pin_re)
);
pla_decode pla_decode_(
.prefix (prefix),
.opcode (opcode),
.pla (pla)
);
resets resets_(
.reset_in (reset_in),
.clk (clk),
.M1 (M1),
.T2 (T2),
.fpga_reset (fpga_reset),
.nhold_clk_wait (nhold_clk_wait),
.clrpc (clrpc),
.nreset (nreset)
);
memory_ifc memory_ifc_(
.clk (clk),
.nM1_int (nM1_int),
.ctl_mRead (ctl_mRead),
.ctl_mWrite (ctl_mWrite),
.in_intr (in_intr),
.nreset (nreset),
.fIORead (fIORead),
.fIOWrite (fIOWrite),
.setM1 (setM1),
.ctl_iorw (ctl_iorw),
.timings_en (timings_en),
.iorq_Tw (iorq_Tw),
.nhold_clk_wait (nhold_clk_wait),
.nM1_out (nM1_out),
.nRFSH_out (nRFSH_out),
.nMREQ_out (nMREQ_out),
.nRD_out (nRD_out),
.nWR_out (nWR_out),
.nIORQ_out (nIORQ_out),
.latch_wait (latch_wait),
.wait_m1 (wait_m1)
);
sequencer sequencer_(
.clk (clk),
.nextM (nextM),
.setM1 (setM1),
.nreset (nreset),
.hold_clk_iorq (hold_clk_iorq),
.hold_clk_wait (hold_clk_wait),
.hold_clk_busrq (hold_clk_busrq),
.M1 (M1),
.M2 (M2),
.M3 (M3),
.M4 (M4),
.M5 (M5),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.T4 (T4),
.T5 (T5),
.T6 (T6),
.timings_en (timings_en)
);
alu_control alu_control_(
.alu_shift_db0 (alu_shift_db0),
.alu_shift_db7 (alu_shift_db7),
.ctl_shift_en (ctl_shift_en),
.alu_low_gt_9 (alu_low_gt_9),
.alu_high_gt_9 (alu_high_gt_9),
.alu_high_eq_9 (alu_high_eq_9),
.ctl_daa_oe (ctl_daa_oe),
.ctl_alu_op_low (ctl_alu_op_low),
.alu_parity_out (alu_parity_out),
.flags_cf (flags_cf),
.flags_zf (flags_zf),
.flags_pf (flags_pf),
.flags_sf (flags_sf),
.ctl_cond_short (ctl_cond_short),
.alu_vf_out (alu_vf_out),
.iff2 (iff2),
.ctl_alu_core_hf (ctl_alu_core_hf),
.ctl_eval_cond (ctl_eval_cond),
.repeat_en (repeat_en),
.flags_cf_latch (flags_cf_latch),
.flags_hf2 (flags_hf2),
.flags_hf (flags_hf),
.ctl_66_oe (ctl_66_oe),
.clk (clk),
.ctl_pf_sel (ctl_pf_sel),
.op543 ({pla[104],pla[103],pla[102]}),
.alu_shift_in (alu_shift_in),
.alu_shift_right (alu_shift_right),
.alu_shift_left (alu_shift_left),
.shift_cf_out (shift_cf_out),
.alu_parity_in (alu_parity_in),
.flags_cond_true (flags_cond_true),
.daa_cf_out (daa_cf_out),
.pf_sel (pf_sel),
.alu_op_low (alu_op_low),
.alu_core_cf_in (alu_core_cf_in),
.db (db1[7:0])
);
alu_select alu_select_(
.ctl_alu_oe (ctl_alu_oe),
.ctl_alu_shift_oe (ctl_alu_shift_oe),
.ctl_alu_op2_oe (ctl_alu_op2_oe),
.ctl_alu_res_oe (ctl_alu_res_oe),
.ctl_alu_op1_oe (ctl_alu_op1_oe),
.ctl_alu_bs_oe (ctl_alu_bs_oe),
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
.ctl_alu_core_R (ctl_alu_core_R),
.ctl_alu_core_V (ctl_alu_core_V),
.ctl_alu_core_S (ctl_alu_core_S),
.alu_oe (alu_oe),
.alu_shift_oe (alu_shift_oe),
.alu_op2_oe (alu_op2_oe),
.alu_res_oe (alu_res_oe),
.alu_op1_oe (alu_op1_oe),
.alu_bs_oe (alu_bs_oe),
.alu_op1_sel_bus (alu_op1_sel_bus),
.alu_op1_sel_low (alu_op1_sel_low),
.alu_op1_sel_zero (alu_op1_sel_zero),
.alu_op2_sel_zero (alu_op2_sel_zero),
.alu_op2_sel_bus (alu_op2_sel_bus),
.alu_op2_sel_lq (alu_op2_sel_lq),
.alu_sel_op2_neg (alu_sel_op2_neg),
.alu_sel_op2_high (alu_sel_op2_high),
.alu_core_R (alu_core_R),
.alu_core_V (alu_core_V),
.alu_core_S (alu_core_S)
);
alu_flags alu_flags_(
.ctl_flags_oe (ctl_flags_oe),
.ctl_flags_bus (ctl_flags_bus),
.ctl_flags_alu (ctl_flags_alu),
.alu_sf_out (alu_sf_out),
.alu_yf_out (alu_yf_out),
.alu_xf_out (alu_xf_out),
.ctl_flags_nf_set (ctl_flags_nf_set),
.alu_zero (alu_zero),
.shift_cf_out (shift_cf_out),
.alu_core_cf_out (alu_core_cf_out),
.daa_cf_out (daa_cf_out),
.ctl_flags_cf_set (ctl_flags_cf_set),
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
.pf_sel (pf_sel),
.ctl_flags_cf_we (ctl_flags_cf_we),
.ctl_flags_sz_we (ctl_flags_sz_we),
.ctl_flags_xy_we (ctl_flags_xy_we),
.ctl_flags_hf_we (ctl_flags_hf_we),
.ctl_flags_pf_we (ctl_flags_pf_we),
.ctl_flags_nf_we (ctl_flags_nf_we),
.ctl_flags_cf2_we (ctl_flags_cf2_we),
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
.ctl_flags_hf2_we (ctl_flags_hf2_we),
.ctl_flags_nf_clr (ctl_flags_nf_clr),
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
.clk (clk),
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
.nhold_clk_wait (nhold_clk_wait),
.flags_sf (flags_sf),
.flags_zf (flags_zf),
.flags_hf (flags_hf),
.flags_pf (flags_pf),
.flags_cf (flags_cf),
.flags_nf (flags_nf),
.flags_cf_latch (flags_cf_latch),
.flags_hf2 (flags_hf2),
.db (db1[7:0])
);
alu alu_(
.alu_core_R (alu_core_R),
.alu_core_V (alu_core_V),
.alu_core_S (alu_core_S),
.alu_bs_oe (alu_bs_oe),
.alu_parity_in (alu_parity_in),
.alu_oe (alu_oe),
.alu_shift_oe (alu_shift_oe),
.alu_core_cf_in (alu_core_cf_in),
.alu_op2_oe (alu_op2_oe),
.alu_op1_oe (alu_op1_oe),
.alu_res_oe (alu_res_oe),
.alu_op1_sel_low (alu_op1_sel_low),
.alu_op1_sel_zero (alu_op1_sel_zero),
.alu_op1_sel_bus (alu_op1_sel_bus),
.alu_op2_sel_zero (alu_op2_sel_zero),
.alu_op2_sel_bus (alu_op2_sel_bus),
.alu_op2_sel_lq (alu_op2_sel_lq),
.alu_op_low (alu_op_low),
.alu_shift_in (alu_shift_in),
.alu_sel_op2_neg (alu_sel_op2_neg),
.alu_sel_op2_high (alu_sel_op2_high),
.alu_shift_left (alu_shift_left),
.alu_shift_right (alu_shift_right),
.clk (clk),
.bsel (db0[5:3]),
.alu_zero (alu_zero),
.alu_parity_out (alu_parity_out),
.alu_high_eq_9 (alu_high_eq_9),
.alu_high_gt_9 (alu_high_gt_9),
.alu_low_gt_9 (alu_low_gt_9),
.alu_shift_db0 (alu_shift_db0),
.alu_shift_db7 (alu_shift_db7),
.alu_core_cf_out (alu_core_cf_out),
.alu_sf_out (alu_sf_out),
.alu_yf_out (alu_yf_out),
.alu_xf_out (alu_xf_out),
.alu_vf_out (alu_vf_out),
.db (db2[7:0]),
.test_db_high (test_db_high),
.test_db_low (test_db_low)
);
reg_file reg_file_(
.reg_sel_sys_lo (reg_sel_sys_lo),
.reg_sel_gp_lo (reg_sel_gp_lo),
.reg_sel_sys_hi (reg_sel_sys_hi),
.reg_sel_gp_hi (reg_sel_gp_hi),
.reg_sel_ir (reg_sel_ir),
.reg_sel_pc (reg_sel_pc),
.ctl_sw_4u (ctl_sw_4u),
.reg_sel_wz (reg_sel_wz),
.reg_sel_sp (reg_sel_sp),
.reg_sel_iy (reg_sel_iy),
.reg_sel_ix (reg_sel_ix),
.reg_sel_hl2 (reg_sel_hl2),
.reg_sel_hl (reg_sel_hl),
.reg_sel_de2 (reg_sel_de2),
.reg_sel_de (reg_sel_de),
.reg_sel_bc2 (reg_sel_bc2),
.reg_sel_bc (reg_sel_bc),
.reg_sel_af2 (reg_sel_af2),
.reg_sel_af (reg_sel_af),
.reg_gp_we (reg_gp_we),
.reg_sys_we_lo (reg_sys_we_lo),
.reg_sys_we_hi (reg_sys_we_hi),
.ctl_reg_in_hi (ctl_reg_in_hi),
.ctl_reg_in_lo (ctl_reg_in_lo),
.ctl_reg_out_lo (ctl_reg_out_lo),
.ctl_reg_out_hi (ctl_reg_out_hi),
.clk (clk),
.reg_sw_4d_lo (reg_sw_4d_lo),
.reg_sw_4d_hi (reg_sw_4d_hi),
.db_hi_as (db_hi_as[7:0]),
.db_hi_ds (db2[7:0]),
.db_lo_as (db_lo_as[7:0]),
.db_lo_ds (db1[7:0])
);
reg_control reg_control_(
.ctl_reg_exx (ctl_reg_exx),
.ctl_reg_ex_af (ctl_reg_ex_af),
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
.ctl_reg_use_sp (ctl_reg_use_sp),
.nreset (nreset),
.ctl_reg_sel_pc (ctl_reg_sel_pc),
.ctl_reg_sel_ir (ctl_reg_sel_ir),
.ctl_reg_sel_wz (ctl_reg_sel_wz),
.ctl_reg_gp_we (ctl_reg_gp_we),
.ctl_reg_not_pc (ctl_reg_not_pc),
.use_ixiy (use_ixiy),
.use_ix (use_ix),
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
.ctl_reg_sys_we (ctl_reg_sys_we),
.clk (clk),
.ctl_sw_4d (ctl_sw_4d),
.nhold_clk_wait (nhold_clk_wait),
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
.ctl_reg_gp_sel (ctl_reg_gp_sel),
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
.reg_sel_bc (reg_sel_bc),
.reg_sel_bc2 (reg_sel_bc2),
.reg_sel_ix (reg_sel_ix),
.reg_sel_iy (reg_sel_iy),
.reg_sel_de (reg_sel_de),
.reg_sel_hl (reg_sel_hl),
.reg_sel_de2 (reg_sel_de2),
.reg_sel_hl2 (reg_sel_hl2),
.reg_sel_af (reg_sel_af),
.reg_sel_af2 (reg_sel_af2),
.reg_sel_wz (reg_sel_wz),
.reg_sel_pc (reg_sel_pc),
.reg_sel_ir (reg_sel_ir),
.reg_sel_sp (reg_sel_sp),
.reg_sel_gp_hi (reg_sel_gp_hi),
.reg_sel_gp_lo (reg_sel_gp_lo),
.reg_sel_sys_lo (reg_sel_sys_lo),
.reg_sel_sys_hi (reg_sel_sys_hi),
.reg_gp_we (reg_gp_we),
.reg_sys_we_lo (reg_sys_we_lo),
.reg_sys_we_hi (reg_sys_we_hi),
.reg_sw_4d_lo (reg_sw_4d_lo),
.reg_sw_4d_hi (reg_sw_4d_hi)
);
address_latch address_latch_(
.ctl_inc_cy (ctl_inc_cy),
.ctl_inc_dec (ctl_inc_dec),
.ctl_al_we (ctl_al_we),
.ctl_inc_limit6 (ctl_inc_limit6),
.ctl_bus_inc_oe (ctl_bus_inc_oe),
.clk (clk),
.ctl_apin_mux (ctl_apin_mux),
.ctl_apin_mux2 (ctl_apin_mux2),
.clrpc (clrpc),
.nreset (nreset),
.address_is_1 (address_is_1),
.abus ({db_hi_as[7:0], db_lo_as[7:0]}),
.address (address)
);
bus_control bus_control_(
.ctl_bus_ff_oe (ctl_bus_ff_oe),
.ctl_bus_zero_oe (ctl_bus_zero_oe),
.db (db0[7:0])
);
bus_switch bus_switch_(
.ctl_sw_1u (ctl_sw_1u),
.ctl_sw_1d (ctl_sw_1d),
.ctl_sw_2u (ctl_sw_2u),
.ctl_sw_2d (ctl_sw_2d),
.ctl_sw_mask543_en (ctl_sw_mask543_en),
.bus_sw_1u (bus_sw_1u),
.bus_sw_1d (bus_sw_1d),
.bus_sw_2u (bus_sw_2u),
.bus_sw_2d (bus_sw_2d),
.bus_sw_mask543_en (bus_sw_mask543_en)
);

99
FPGA/SW700/v1.3/softT80/AZ80/data_pins.v Normal file
View File

@@ -0,0 +1,99 @@
//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Thu Nov 06 23:28:26 2014"
module data_pins(
bus_db_pin_oe,
bus_db_pin_re,
ctl_bus_db_we,
clk,
ctl_bus_db_oe,
D,
db
);
input wire bus_db_pin_oe;
input wire bus_db_pin_re;
input wire ctl_bus_db_we;
input wire clk;
input wire ctl_bus_db_oe;
inout wire [7:0] D;
inout wire [7:0] db;
reg [7:0] dout;
wire [7:0] SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire [7:0] SYNTHESIZED_WIRE_3;
wire [7:0] SYNTHESIZED_WIRE_4;
always@(posedge SYNTHESIZED_WIRE_1)
begin
if (SYNTHESIZED_WIRE_2)
begin
dout[7:0] <= SYNTHESIZED_WIRE_0[7:0];
end
end
assign SYNTHESIZED_WIRE_4 = {ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we} & db;
assign SYNTHESIZED_WIRE_3 = {bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re} & D;
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re;
assign db[7] = ctl_bus_db_oe ? dout[7] : 1'bz;
assign db[6] = ctl_bus_db_oe ? dout[6] : 1'bz;
assign db[5] = ctl_bus_db_oe ? dout[5] : 1'bz;
assign db[4] = ctl_bus_db_oe ? dout[4] : 1'bz;
assign db[3] = ctl_bus_db_oe ? dout[3] : 1'bz;
assign db[2] = ctl_bus_db_oe ? dout[2] : 1'bz;
assign db[1] = ctl_bus_db_oe ? dout[1] : 1'bz;
assign db[0] = ctl_bus_db_oe ? dout[0] : 1'bz;
assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz;
assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz;
assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz;
assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz;
assign D[3] = bus_db_pin_oe ? dout[3] : 1'bz;
assign D[2] = bus_db_pin_oe ? dout[2] : 1'bz;
assign D[1] = bus_db_pin_oe ? dout[1] : 1'bz;
assign D[0] = bus_db_pin_oe ? dout[0] : 1'bz;
assign SYNTHESIZED_WIRE_1 = ~clk;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:33:19 2014"
module data_switch(
sw_up_en,
sw_down_en,
db_down,
db_up
);
input wire sw_up_en;
input wire sw_down_en;
inout wire [7:0] db_down;
inout wire [7:0] db_up;
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz;
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz;
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz;
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz;
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz;
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz;
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz;
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz;
assign db_down[7] = sw_down_en ? db_up[7] : 1'bz;
assign db_down[6] = sw_down_en ? db_up[6] : 1'bz;
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz;
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz;
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz;
assign db_down[2] = sw_down_en ? db_up[2] : 1'bz;
assign db_down[1] = sw_down_en ? db_up[1] : 1'bz;
assign db_down[0] = sw_down_en ? db_up[0] : 1'bz;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:32:03 2014"
module data_switch_mask(
sw_up_en,
sw_down_en,
sw_mask543_en,
db_down,
db_up
);
input wire sw_up_en;
input wire sw_down_en;
input wire sw_mask543_en;
inout wire [7:0] db_down;
inout wire [7:0] db_up;
wire SYNTHESIZED_WIRE_4;
wire [1:0] SYNTHESIZED_WIRE_1;
wire [2:0] SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_4 = ~sw_mask543_en;
assign SYNTHESIZED_WIRE_1 = db_up[7:6] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};
assign db_down[7] = sw_down_en ? SYNTHESIZED_WIRE_1[1] : 1'bz;
assign db_down[6] = sw_down_en ? SYNTHESIZED_WIRE_1[0] : 1'bz;
assign db_down[2] = sw_down_en ? SYNTHESIZED_WIRE_2[2] : 1'bz;
assign db_down[1] = sw_down_en ? SYNTHESIZED_WIRE_2[1] : 1'bz;
assign db_down[0] = sw_down_en ? SYNTHESIZED_WIRE_2[0] : 1'bz;
assign SYNTHESIZED_WIRE_2 = db_up[2:0] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz;
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz;
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz;
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz;
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz;
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz;
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz;
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz;
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz;
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz;
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:55:35 2016"
module decode_state(
ctl_state_iy_set,
ctl_state_ixiy_clr,
ctl_state_ixiy_we,
ctl_state_halt_set,
ctl_state_tbl_ed_set,
ctl_state_tbl_cb_set,
ctl_state_alu,
clk,
address_is_1,
ctl_repeat_we,
in_intr,
in_nmi,
nreset,
ctl_state_tbl_we,
nhold_clk_wait,
in_halt,
table_cb,
table_ed,
table_xx,
use_ix,
use_ixiy,
in_alu,
repeat_en
);
input wire ctl_state_iy_set;
input wire ctl_state_ixiy_clr;
input wire ctl_state_ixiy_we;
input wire ctl_state_halt_set;
input wire ctl_state_tbl_ed_set;
input wire ctl_state_tbl_cb_set;
input wire ctl_state_alu;
input wire clk;
input wire address_is_1;
input wire ctl_repeat_we;
input wire in_intr;
input wire in_nmi;
input wire nreset;
input wire ctl_state_tbl_we;
input wire nhold_clk_wait;
output reg in_halt;
output wire table_cb;
output wire table_ed;
output wire table_xx;
output wire use_ix;
output wire use_ixiy;
output wire in_alu;
output wire repeat_en;
reg DFFE_instNonRep;
reg DFFE_instIY1;
reg DFFE_inst4;
reg DFFE_instED;
reg DFFE_instCB;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_3;
assign in_alu = ctl_state_alu;
assign table_cb = DFFE_instCB;
assign table_ed = DFFE_instED;
assign use_ix = DFFE_inst4;
assign repeat_en = ~DFFE_instNonRep;
assign use_ixiy = DFFE_instIY1 | DFFE_inst4;
assign table_xx = ~(DFFE_instED | DFFE_instCB);
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_inst4 <= 0;
end
else
if (ctl_state_ixiy_we)
begin
DFFE_inst4 <= SYNTHESIZED_WIRE_0;
end
end
assign SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
assign SYNTHESIZED_WIRE_4 = ctl_state_tbl_we & nhold_clk_wait;
assign SYNTHESIZED_WIRE_3 = in_nmi | in_intr;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instCB <= 0;
end
else
if (SYNTHESIZED_WIRE_4)
begin
DFFE_instCB <= ctl_state_tbl_cb_set;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instED <= 0;
end
else
if (SYNTHESIZED_WIRE_4)
begin
DFFE_instED <= ctl_state_tbl_ed_set;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
in_halt <= 0;
end
else
begin
in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instIY1 <= 0;
end
else
if (ctl_state_ixiy_we)
begin
DFFE_instIY1 <= ctl_state_iy_set;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_instNonRep <= 0;
end
else
if (ctl_repeat_we)
begin
DFFE_instNonRep <= address_is_1;
end
end
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Automatically generated by genref.py
// Module: control/decode_state.v
output reg ctl_state_iy_set,
output reg ctl_state_ixiy_clr,
output reg ctl_state_ixiy_we,
output reg ctl_state_halt_set,
output reg ctl_state_tbl_ed_set,
output reg ctl_state_tbl_cb_set,
output reg ctl_state_alu,
output reg ctl_repeat_we,
output reg ctl_state_tbl_we,
// Module: control/interrupts.v
output reg ctl_iff1_iff2,
output reg ctl_iffx_we,
output reg ctl_iffx_bit,
output reg ctl_im_we,
output reg ctl_no_ints,
// Module: control/ir.v
output reg ctl_ir_we,
// Module: control/memory_ifc.v
output reg ctl_mRead,
output reg ctl_mWrite,
output reg ctl_iorw,
// Module: alu/alu_control.v
output reg ctl_shift_en,
output reg ctl_daa_oe,
output reg ctl_alu_op_low,
output reg ctl_cond_short,
output reg ctl_alu_core_hf,
output reg ctl_eval_cond,
output reg ctl_66_oe,
output reg [1:0] ctl_pf_sel,
// Module: alu/alu_select.v
output reg ctl_alu_oe,
output reg ctl_alu_shift_oe,
output reg ctl_alu_op2_oe,
output reg ctl_alu_res_oe,
output reg ctl_alu_op1_oe,
output reg ctl_alu_bs_oe,
output reg ctl_alu_op1_sel_bus,
output reg ctl_alu_op1_sel_low,
output reg ctl_alu_op1_sel_zero,
output reg ctl_alu_op2_sel_zero,
output reg ctl_alu_op2_sel_bus,
output reg ctl_alu_op2_sel_lq,
output reg ctl_alu_sel_op2_neg,
output reg ctl_alu_sel_op2_high,
output reg ctl_alu_core_R,
output reg ctl_alu_core_V,
output reg ctl_alu_core_S,
// Module: alu/alu_flags.v
output reg ctl_flags_oe,
output reg ctl_flags_bus,
output reg ctl_flags_alu,
output reg ctl_flags_nf_set,
output reg ctl_flags_cf_set,
output reg ctl_flags_cf_cpl,
output reg ctl_flags_cf_we,
output reg ctl_flags_sz_we,
output reg ctl_flags_xy_we,
output reg ctl_flags_hf_we,
output reg ctl_flags_pf_we,
output reg ctl_flags_nf_we,
output reg ctl_flags_cf2_we,
output reg ctl_flags_hf_cpl,
output reg ctl_flags_use_cf2,
output reg ctl_flags_hf2_we,
output reg ctl_flags_nf_clr,
output reg ctl_alu_zero_16bit,
output reg ctl_flags_cf2_sel_shift,
output reg ctl_flags_cf2_sel_daa,
// Module: registers/reg_file.v
output reg ctl_sw_4u,
output reg ctl_reg_in_hi,
output reg ctl_reg_in_lo,
output reg ctl_reg_out_lo,
output reg ctl_reg_out_hi,
// Module: registers/reg_control.v
output reg ctl_reg_exx,
output reg ctl_reg_ex_af,
output reg ctl_reg_ex_de_hl,
output reg ctl_reg_use_sp,
output reg ctl_reg_sel_pc,
output reg ctl_reg_sel_ir,
output reg ctl_reg_sel_wz,
output reg ctl_reg_gp_we,
output reg ctl_reg_not_pc,
output reg ctl_reg_sys_we_lo,
output reg ctl_reg_sys_we_hi,
output reg ctl_reg_sys_we,
output reg ctl_sw_4d,
output reg [1:0] ctl_reg_gp_hilo,
output reg [1:0] ctl_reg_gp_sel,
output reg [1:0] ctl_reg_sys_hilo,
// Module: bus/address_latch.v
output reg ctl_inc_cy,
output reg ctl_inc_dec,
output reg ctl_al_we,
output reg ctl_inc_limit6,
output reg ctl_bus_inc_oe,
output reg ctl_apin_mux,
output reg ctl_apin_mux2,
// Module: bus/bus_control.v
output reg ctl_bus_ff_oe,
output reg ctl_bus_zero_oe,
// Module: bus/bus_switch.v
output reg ctl_sw_1u,
output reg ctl_sw_1d,
output reg ctl_sw_2u,
output reg ctl_sw_2d,
output reg ctl_sw_mask543_en,
// Module: bus/data_pins.v
output reg ctl_bus_db_we,
output reg ctl_bus_db_oe,

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Automatically generated by genref.py
// Module: control/decode_state.v
ctl_state_iy_set = 0;
ctl_state_ixiy_clr = 0;
ctl_state_ixiy_we = 0;
ctl_state_halt_set = 0;
ctl_state_tbl_ed_set = 0;
ctl_state_tbl_cb_set = 0;
ctl_state_alu = 0;
ctl_repeat_we = 0;
ctl_state_tbl_we = 0;
// Module: control/interrupts.v
ctl_iff1_iff2 = 0;
ctl_iffx_we = 0;
ctl_iffx_bit = 0;
ctl_im_we = 0;
ctl_no_ints = 0;
// Module: control/ir.v
ctl_ir_we = 0;
// Module: control/memory_ifc.v
ctl_mRead = 0;
ctl_mWrite = 0;
ctl_iorw = 0;
// Module: alu/alu_control.v
ctl_shift_en = 0;
ctl_daa_oe = 0;
ctl_alu_op_low = 0;
ctl_cond_short = 0;
ctl_alu_core_hf = 0;
ctl_eval_cond = 0;
ctl_66_oe = 0;
ctl_pf_sel = 0;
// Module: alu/alu_select.v
ctl_alu_oe = 0;
ctl_alu_shift_oe = 0;
ctl_alu_op2_oe = 0;
ctl_alu_res_oe = 0;
ctl_alu_op1_oe = 0;
ctl_alu_bs_oe = 0;
ctl_alu_op1_sel_bus = 0;
ctl_alu_op1_sel_low = 0;
ctl_alu_op1_sel_zero = 0;
ctl_alu_op2_sel_zero = 0;
ctl_alu_op2_sel_bus = 0;
ctl_alu_op2_sel_lq = 0;
ctl_alu_sel_op2_neg = 0;
ctl_alu_sel_op2_high = 0;
ctl_alu_core_R = 0;
ctl_alu_core_V = 0;
ctl_alu_core_S = 0;
// Module: alu/alu_flags.v
ctl_flags_oe = 0;
ctl_flags_bus = 0;
ctl_flags_alu = 0;
ctl_flags_nf_set = 0;
ctl_flags_cf_set = 0;
ctl_flags_cf_cpl = 0;
ctl_flags_cf_we = 0;
ctl_flags_sz_we = 0;
ctl_flags_xy_we = 0;
ctl_flags_hf_we = 0;
ctl_flags_pf_we = 0;
ctl_flags_nf_we = 0;
ctl_flags_cf2_we = 0;
ctl_flags_hf_cpl = 0;
ctl_flags_use_cf2 = 0;
ctl_flags_hf2_we = 0;
ctl_flags_nf_clr = 0;
ctl_alu_zero_16bit = 0;
ctl_flags_cf2_sel_shift = 0;
ctl_flags_cf2_sel_daa = 0;
// Module: registers/reg_file.v
ctl_sw_4u = 0;
ctl_reg_in_hi = 0;
ctl_reg_in_lo = 0;
ctl_reg_out_lo = 0;
ctl_reg_out_hi = 0;
// Module: registers/reg_control.v
ctl_reg_exx = 0;
ctl_reg_ex_af = 0;
ctl_reg_ex_de_hl = 0;
ctl_reg_use_sp = 0;
ctl_reg_sel_pc = 0;
ctl_reg_sel_ir = 0;
ctl_reg_sel_wz = 0;
ctl_reg_gp_we = 0;
ctl_reg_not_pc = 0;
ctl_reg_sys_we_lo = 0;
ctl_reg_sys_we_hi = 0;
ctl_reg_sys_we = 0;
ctl_sw_4d = 0;
ctl_reg_gp_hilo = 0;
ctl_reg_gp_sel = 0;
ctl_reg_sys_hilo = 0;
// Module: bus/address_latch.v
ctl_inc_cy = 0;
ctl_inc_dec = 0;
ctl_al_we = 0;
ctl_inc_limit6 = 0;
ctl_bus_inc_oe = 0;
ctl_apin_mux = 0;
ctl_apin_mux2 = 0;
// Module: bus/bus_control.v
ctl_bus_ff_oe = 0;
ctl_bus_zero_oe = 0;
// Module: bus/bus_switch.v
ctl_sw_1u = 0;
ctl_sw_1d = 0;
ctl_sw_2u = 0;
ctl_sw_2d = 0;
ctl_sw_mask543_en = 0;
// Module: bus/data_pins.v
ctl_bus_db_we = 0;
ctl_bus_db_oe = 0;

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
//=============================================================================
// This module implements the instruction execute state logic.
//
// Copyright (C) 2014-2016 Goran Devic
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//=============================================================================
// Using a compiled format will include files generated by "gencompile.py" script
// These files are a processed version of "exec_matrix_compiled.vh"
// You would define this on Xilinx and undefine (comment out) on Altera
`define USE_COMPILED_FORMAT
module execute
(
//----------------------------------------------------------
// Control signals generated by the instruction execution
//----------------------------------------------------------
`include "exec_module.vh"
output reg nextM, // Last M cycle of any instruction
output reg setM1, // Last T clock of any instruction
output reg fFetch, // Function: opcode fetch cycle ("M1")
output reg fMRead, // Function: memory read cycle
output reg fMWrite, // Function: memory write cycle
output reg fIORead, // Function: IO Read cycle
output reg fIOWrite, // Function: IO Write cycle
//----------------------------------------------------------
// Inputs from the instruction decode PLA
//----------------------------------------------------------
input wire [104:0] pla, // Statically decoded instructions
//----------------------------------------------------------
// Inputs from various blocks
//----------------------------------------------------------
input wire in_intr, // Servicing maskable interrupt
input wire in_nmi, // Servicing non-maskable interrupt
input wire in_halt, // Currently in HALT mode
input wire im1, // Interrupt Mode 1
input wire im2, // Interrupt Mode 2
input wire use_ixiy, // Special decode signal
input wire flags_cond_true, // Flags condition is true
input wire repeat_en, // Enable repeat of a block instruction
input wire flags_zf, // ZF to test a condition
input wire flags_nf, // NF to test for subtraction
input wire flags_sf, // SF to test for 8-bit sign of a value
input wire flags_cf, // CF to set HF for CCF
//----------------------------------------------------------
// Machine and clock cycles
//----------------------------------------------------------
input wire M1, // Machine cycle #1
input wire M2, // Machine cycle #2
input wire M3, // Machine cycle #3
input wire M4, // Machine cycle #4
input wire M5, // Machine cycle #5
input wire T1, // T-cycle #1
input wire T2, // T-cycle #2
input wire T3, // T-cycle #3
input wire T4, // T-cycle #4
input wire T5, // T-cycle #5
input wire T6 // T-cycle #6
);
// Detects unknown instructions by signalling the known ones
reg validPLA; // Valid PLA asserts this reg
// Activates a state machine to compute WZ=IX+d; takes 5T cycles
reg ixy_d; // Compute WX=IX+d
// Signals the setting of IX/IY prefix flags; inhibits clearing them
reg setIXIY; // Set IX/IY flag at the next T cycle
// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
reg nonRep; // Non-repeating block instruction
// Suspends incrementing PC through address latch unless in HALT or interrupt mode
reg pc_inc_hold; // Normally 0 unless in one of those modes
//--------------------------------------------------------------
// Define various shortcuts to field naming
//--------------------------------------------------------------
`define GP_REG_BC 2'h0
`define GP_REG_DE 2'h1
`define GP_REG_HL 2'h2
`define GP_REG_AF 2'h3
`define PFSEL_P 2'h0
`define PFSEL_V 2'h1
`define PFSEL_IFF2 2'h2
`define PFSEL_REP 2'h3
//--------------------------------------------------------------
// Make available different bits and sections of the opcode byte
//--------------------------------------------------------------
wire op0 = pla[99];
wire op1 = pla[100];
wire op2 = pla[101];
wire op3 = pla[102];
wire op4 = pla[103];
wire op5 = pla[104];
wire [1:0] op21 = { pla[101], pla[100] };
wire [1:0] op54 = { pla[104], pla[103] };
//--------------------------------------------------------------
// 8-bit register selections needs to swizzle mux for A and F
//--------------------------------------------------------------
wire rsel0 = op0 ^ (op1 & op2);
wire rsel3 = op3 ^ (op4 & op5);
`ifdef USE_COMPILED_FORMAT
`include "temp_wires.vh" // Define all temp wires used with compiled equations
`endif
always @(*) // always_comb
begin
//-----------------------------------------------------------------------------
// Default assignment of all control outputs to 0 to prevent generating latches
//-----------------------------------------------------------------------------
`include "exec_zero.vh" // Initial assignment to all ctl wires to zero
// Reset internal control regs
validPLA = 0; // Will be set by every *valid* PLA entry
nextM = 0; // Will be set to advance to the next M cycle
setM1 = 0; // Will be set on a last M/T cycle of an instruction
// Reset global machine cycle functions
fFetch = M1; // Fetch is aliased to M1
fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
ixy_d = 0;
setIXIY = 0;
nonRep = 0;
pc_inc_hold = 0;
//-------------------------------------------------------------------------
// State-based signal assignment; code generated from Timings spreadsheet
//-------------------------------------------------------------------------
`ifdef USE_COMPILED_FORMAT
`include "exec_matrix_compiled.vh" // Compiled execution equations
`else
`include "exec_matrix.vh" // Execution statements in the original nested-if format
`endif
// Needed by data bus 0 override logic, make only one bus writer active at any time
ctl_bus_db_oe = ctl_bus_db_oe & ~(ctl_bus_zero_oe | ctl_bus_ff_oe);
end
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Automatically generated by genglobals.py
// Module: control/clk_delay.v
wire hold_clk_iorq;
wire hold_clk_wait;
wire iorq_Tw;
wire busack;
wire pin_control_oe;
wire hold_clk_busrq;
wire nhold_clk_wait;
// Module: control/decode_state.v
wire in_halt;
wire table_cb;
wire table_ed;
wire table_xx;
wire use_ix;
wire use_ixiy;
wire in_alu;
wire repeat_en;
// Module: control/exec_module.vh
wire ctl_state_iy_set;
wire ctl_state_ixiy_clr;
wire ctl_state_ixiy_we;
wire ctl_state_halt_set;
wire ctl_state_tbl_ed_set;
wire ctl_state_tbl_cb_set;
wire ctl_state_alu;
wire ctl_repeat_we;
wire ctl_state_tbl_we;
wire ctl_iff1_iff2;
wire ctl_iffx_we;
wire ctl_iffx_bit;
wire ctl_im_we;
wire ctl_no_ints;
wire ctl_ir_we;
wire ctl_mRead;
wire ctl_mWrite;
wire ctl_iorw;
wire ctl_shift_en;
wire ctl_daa_oe;
wire ctl_alu_op_low;
wire ctl_cond_short;
wire ctl_alu_core_hf;
wire ctl_eval_cond;
wire ctl_66_oe;
wire [1:0] ctl_pf_sel;
wire ctl_alu_oe;
wire ctl_alu_shift_oe;
wire ctl_alu_op2_oe;
wire ctl_alu_res_oe;
wire ctl_alu_op1_oe;
wire ctl_alu_bs_oe;
wire ctl_alu_op1_sel_bus;
wire ctl_alu_op1_sel_low;
wire ctl_alu_op1_sel_zero;
wire ctl_alu_op2_sel_zero;
wire ctl_alu_op2_sel_bus;
wire ctl_alu_op2_sel_lq;
wire ctl_alu_sel_op2_neg;
wire ctl_alu_sel_op2_high;
wire ctl_alu_core_R;
wire ctl_alu_core_V;
wire ctl_alu_core_S;
wire ctl_flags_oe;
wire ctl_flags_bus;
wire ctl_flags_alu;
wire ctl_flags_nf_set;
wire ctl_flags_cf_set;
wire ctl_flags_cf_cpl;
wire ctl_flags_cf_we;
wire ctl_flags_sz_we;
wire ctl_flags_xy_we;
wire ctl_flags_hf_we;
wire ctl_flags_pf_we;
wire ctl_flags_nf_we;
wire ctl_flags_cf2_we;
wire ctl_flags_hf_cpl;
wire ctl_flags_use_cf2;
wire ctl_flags_hf2_we;
wire ctl_flags_nf_clr;
wire ctl_alu_zero_16bit;
wire ctl_flags_cf2_sel_shift;
wire ctl_flags_cf2_sel_daa;
wire ctl_sw_4u;
wire ctl_reg_in_hi;
wire ctl_reg_in_lo;
wire ctl_reg_out_lo;
wire ctl_reg_out_hi;
wire ctl_reg_exx;
wire ctl_reg_ex_af;
wire ctl_reg_ex_de_hl;
wire ctl_reg_use_sp;
wire ctl_reg_sel_pc;
wire ctl_reg_sel_ir;
wire ctl_reg_sel_wz;
wire ctl_reg_gp_we;
wire ctl_reg_not_pc;
wire ctl_reg_sys_we_lo;
wire ctl_reg_sys_we_hi;
wire ctl_reg_sys_we;
wire ctl_sw_4d;
wire [1:0] ctl_reg_gp_hilo;
wire [1:0] ctl_reg_gp_sel;
wire [1:0] ctl_reg_sys_hilo;
wire ctl_inc_cy;
wire ctl_inc_dec;
wire ctl_al_we;
wire ctl_inc_limit6;
wire ctl_bus_inc_oe;
wire ctl_apin_mux;
wire ctl_apin_mux2;
wire ctl_bus_ff_oe;
wire ctl_bus_zero_oe;
wire ctl_sw_1u;
wire ctl_sw_1d;
wire ctl_sw_2u;
wire ctl_sw_2d;
wire ctl_sw_mask543_en;
wire ctl_bus_db_we;
wire ctl_bus_db_oe;
// Module: control/execute.v
wire nextM;
wire setM1;
wire fFetch;
wire fMRead;
wire fMWrite;
wire fIORead;
wire fIOWrite;
// Module: control/interrupts.v
wire iff2;
wire im1;
wire im2;
wire in_nmi;
wire in_intr;
// Module: control/ir.v
wire [7:0] opcode;
// Module: control/pin_control.v
wire bus_ab_pin_we;
wire bus_db_pin_oe;
wire bus_db_pin_re;
// Module: control/pla_decode.v
wire [104:0] pla;
// Module: control/resets.v
wire clrpc;
wire nreset;
// Module: control/memory_ifc.v
wire nM1_out;
wire nRFSH_out;
wire nMREQ_out;
wire nRD_out;
wire nWR_out;
wire nIORQ_out;
wire latch_wait;
wire wait_m1;
// Module: control/sequencer.v
wire M1;
wire M2;
wire M3;
wire M4;
wire M5;
wire T1;
wire T2;
wire T3;
wire T4;
wire T5;
wire T6;
wire timings_en;
// Module: alu/alu_control.v
wire alu_shift_in;
wire alu_shift_right;
wire alu_shift_left;
wire shift_cf_out;
wire alu_parity_in;
wire flags_cond_true;
wire daa_cf_out;
wire pf_sel;
wire alu_op_low;
wire alu_core_cf_in;
wire [7:0] db;
// Module: alu/alu_select.v
wire alu_oe;
wire alu_shift_oe;
wire alu_op2_oe;
wire alu_res_oe;
wire alu_op1_oe;
wire alu_bs_oe;
wire alu_op1_sel_bus;
wire alu_op1_sel_low;
wire alu_op1_sel_zero;
wire alu_op2_sel_zero;
wire alu_op2_sel_bus;
wire alu_op2_sel_lq;
wire alu_sel_op2_neg;
wire alu_sel_op2_high;
wire alu_core_R;
wire alu_core_V;
wire alu_core_S;
// Module: alu/alu_flags.v
wire flags_sf;
wire flags_zf;
wire flags_hf;
wire flags_pf;
wire flags_cf;
wire flags_nf;
wire flags_cf_latch;
wire flags_hf2;
// Module: alu/alu.v
wire alu_zero;
wire alu_parity_out;
wire alu_high_eq_9;
wire alu_high_gt_9;
wire alu_low_gt_9;
wire alu_shift_db0;
wire alu_shift_db7;
wire alu_core_cf_out;
wire alu_sf_out;
wire alu_yf_out;
wire alu_xf_out;
wire alu_vf_out;
wire [3:0] test_db_high;
wire [3:0] test_db_low;
// Module: registers/reg_control.v
wire reg_sel_bc;
wire reg_sel_bc2;
wire reg_sel_ix;
wire reg_sel_iy;
wire reg_sel_de;
wire reg_sel_hl;
wire reg_sel_de2;
wire reg_sel_hl2;
wire reg_sel_af;
wire reg_sel_af2;
wire reg_sel_wz;
wire reg_sel_pc;
wire reg_sel_ir;
wire reg_sel_sp;
wire reg_sel_gp_hi;
wire reg_sel_gp_lo;
wire reg_sel_sys_lo;
wire reg_sel_sys_hi;
wire reg_gp_we;
wire reg_sys_we_lo;
wire reg_sys_we_hi;
wire reg_sw_4d_lo;
wire reg_sw_4d_hi;
// Module: bus/address_latch.v
wire address_is_1;
wire [15:0] address;
// Module: bus/address_pins.v
wire [15:0] abus;
// Module: bus/bus_switch.v
wire bus_sw_1u;
wire bus_sw_1d;
wire bus_sw_2u;
wire bus_sw_2d;
wire bus_sw_mask543_en;
// Module: bus/control_pins_n.v
wire nmi;
wire busrq;
wire clk;
wire intr;
wire mwait;
wire reset_in;
wire pin_nM1;
wire pin_nMREQ;
wire pin_nIORQ;
wire pin_nRD;
wire pin_nWR;
wire pin_nRFSH;
wire pin_nHALT;
wire pin_nBUSACK;

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:30:20 2014"
module inc_dec(
carry_in,
limit6,
decrement,
d,
address
);
input wire carry_in;
input wire limit6;
input wire decrement;
input wire [15:0] d;
output wire [15:0] address;
wire [15:0] address_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_40;
wire SYNTHESIZED_WIRE_41;
wire SYNTHESIZED_WIRE_42;
wire SYNTHESIZED_WIRE_43;
wire SYNTHESIZED_WIRE_44;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_45;
wire SYNTHESIZED_WIRE_46;
wire SYNTHESIZED_WIRE_47;
wire SYNTHESIZED_WIRE_48;
wire SYNTHESIZED_WIRE_49;
wire SYNTHESIZED_WIRE_50;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_51;
wire SYNTHESIZED_WIRE_52;
wire SYNTHESIZED_WIRE_53;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_22;
wire SYNTHESIZED_WIRE_25;
wire SYNTHESIZED_WIRE_31;
wire SYNTHESIZED_WIRE_34;
wire SYNTHESIZED_WIRE_35;
wire SYNTHESIZED_WIRE_36;
wire SYNTHESIZED_WIRE_37;
wire SYNTHESIZED_WIRE_38;
wire SYNTHESIZED_WIRE_39;
assign SYNTHESIZED_WIRE_34 = carry_in & SYNTHESIZED_WIRE_40 & SYNTHESIZED_WIRE_41 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44 & SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_45;
assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_46 & SYNTHESIZED_WIRE_47 & SYNTHESIZED_WIRE_48 & SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_16;
inc_dec_2bit b2v_dual_adder_0(
.carry_borrow_in(carry_in),
.d1_in(d[1]),
.d0_in(d[0]),
.dec1_in(SYNTHESIZED_WIRE_40),
.dec0_in(SYNTHESIZED_WIRE_41),
.carry_borrow_out(SYNTHESIZED_WIRE_22),
.d1_out(address_ALTERA_SYNTHESIZED[1]),
.d0_out(address_ALTERA_SYNTHESIZED[0]));
inc_dec_2bit b2v_dual_adder_10(
.carry_borrow_in(SYNTHESIZED_WIRE_51),
.d1_in(d[13]),
.d0_in(d[12]),
.dec1_in(SYNTHESIZED_WIRE_53),
.dec0_in(SYNTHESIZED_WIRE_52),
.carry_borrow_out(SYNTHESIZED_WIRE_37),
.d1_out(address_ALTERA_SYNTHESIZED[13]),
.d0_out(address_ALTERA_SYNTHESIZED[12]));
inc_dec_2bit b2v_dual_adder_2(
.carry_borrow_in(SYNTHESIZED_WIRE_22),
.d1_in(d[3]),
.d0_in(d[2]),
.dec1_in(SYNTHESIZED_WIRE_45),
.dec0_in(SYNTHESIZED_WIRE_42),
.carry_borrow_out(SYNTHESIZED_WIRE_25),
.d1_out(address_ALTERA_SYNTHESIZED[3]),
.d0_out(address_ALTERA_SYNTHESIZED[2]));
inc_dec_2bit b2v_dual_adder_4(
.carry_borrow_in(SYNTHESIZED_WIRE_25),
.d1_in(d[5]),
.d0_in(d[4]),
.dec1_in(SYNTHESIZED_WIRE_43),
.dec0_in(SYNTHESIZED_WIRE_44),
.carry_borrow_out(SYNTHESIZED_WIRE_39),
.d1_out(address_ALTERA_SYNTHESIZED[5]),
.d0_out(address_ALTERA_SYNTHESIZED[4]));
inc_dec_2bit b2v_dual_adder_7(
.carry_borrow_in(SYNTHESIZED_WIRE_47),
.d1_in(d[8]),
.d0_in(d[7]),
.dec1_in(SYNTHESIZED_WIRE_46),
.dec0_in(SYNTHESIZED_WIRE_48),
.carry_borrow_out(SYNTHESIZED_WIRE_31),
.d1_out(address_ALTERA_SYNTHESIZED[8]),
.d0_out(address_ALTERA_SYNTHESIZED[7]));
inc_dec_2bit b2v_dual_adder_9(
.carry_borrow_in(SYNTHESIZED_WIRE_31),
.d1_in(d[10]),
.d0_in(d[9]),
.dec1_in(SYNTHESIZED_WIRE_50),
.dec0_in(SYNTHESIZED_WIRE_49),
.carry_borrow_out(SYNTHESIZED_WIRE_36),
.d1_out(address_ALTERA_SYNTHESIZED[10]),
.d0_out(address_ALTERA_SYNTHESIZED[9]));
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35;
assign SYNTHESIZED_WIRE_35 = ~limit6;
assign SYNTHESIZED_WIRE_41 = d[0] ^ decrement;
assign SYNTHESIZED_WIRE_40 = d[1] ^ decrement;
assign SYNTHESIZED_WIRE_50 = d[10] ^ decrement;
assign SYNTHESIZED_WIRE_12 = d[11] ^ decrement;
assign address_ALTERA_SYNTHESIZED[11] = SYNTHESIZED_WIRE_36 ^ d[11];
assign SYNTHESIZED_WIRE_52 = d[12] ^ decrement;
assign SYNTHESIZED_WIRE_53 = d[13] ^ decrement;
assign SYNTHESIZED_WIRE_16 = d[14] ^ decrement;
assign address_ALTERA_SYNTHESIZED[14] = SYNTHESIZED_WIRE_37 ^ d[14];
assign address_ALTERA_SYNTHESIZED[15] = SYNTHESIZED_WIRE_38 ^ d[15];
assign SYNTHESIZED_WIRE_42 = d[2] ^ decrement;
assign SYNTHESIZED_WIRE_45 = d[3] ^ decrement;
assign SYNTHESIZED_WIRE_44 = d[4] ^ decrement;
assign SYNTHESIZED_WIRE_43 = d[5] ^ decrement;
assign SYNTHESIZED_WIRE_5 = d[6] ^ decrement;
assign address_ALTERA_SYNTHESIZED[6] = SYNTHESIZED_WIRE_39 ^ d[6];
assign SYNTHESIZED_WIRE_48 = d[7] ^ decrement;
assign SYNTHESIZED_WIRE_46 = d[8] ^ decrement;
assign SYNTHESIZED_WIRE_49 = d[9] ^ decrement;
assign address = address_ALTERA_SYNTHESIZED;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:26:57 2014"
module inc_dec_2bit(
carry_borrow_in,
d1_in,
d0_in,
dec1_in,
dec0_in,
carry_borrow_out,
d1_out,
d0_out
);
input wire carry_borrow_in;
input wire d1_in;
input wire d0_in;
input wire dec1_in;
input wire dec0_in;
output wire carry_borrow_out;
output wire d1_out;
output wire d0_out;
wire SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_0 = dec0_in & carry_borrow_in;
assign carry_borrow_out = dec0_in & dec1_in & carry_borrow_in;
assign d1_out = d1_in ^ SYNTHESIZED_WIRE_0;
assign d0_out = carry_borrow_in ^ d0_in;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Feb 13 19:23:03 2016"
module interrupts(
ctl_iff1_iff2,
nmi,
setM1,
intr,
ctl_iffx_we,
ctl_iffx_bit,
ctl_im_we,
clk,
ctl_no_ints,
nreset,
db,
iff2,
im1,
im2,
in_nmi,
in_intr
);
input wire ctl_iff1_iff2;
input wire nmi;
input wire setM1;
input wire intr;
input wire ctl_iffx_we;
input wire ctl_iffx_bit;
input wire ctl_im_we;
input wire clk;
input wire ctl_no_ints;
input wire nreset;
input wire [1:0] db;
output wire iff2;
output reg im1;
output reg im2;
output wire in_nmi;
output wire in_intr;
reg iff1;
wire in_intr_ALTERA_SYNTHESIZED;
reg in_nmi_ALTERA_SYNTHESIZED;
reg int_armed;
reg nmi_armed;
wire test1;
wire SYNTHESIZED_WIRE_0;
reg DFFE_instIFF2;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
reg DFFE_inst44;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_20;
assign iff2 = DFFE_instIFF2;
assign SYNTHESIZED_WIRE_10 = 1;
assign SYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2;
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2;
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset;
assign SYNTHESIZED_WIRE_0 = ~ctl_iff1_iff2;
assign SYNTHESIZED_WIRE_4 = ~db[0];
assign SYNTHESIZED_WIRE_5 = ~in_nmi_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_20 = db[1] & db[0];
assign SYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4;
assign in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_13 = iff1 & intr;
assign test1 = setM1 & SYNTHESIZED_WIRE_8;
always@(posedge nmi or negedge SYNTHESIZED_WIRE_9)
begin
if (!SYNTHESIZED_WIRE_9)
begin
nmi_armed <= 0;
end
else
begin
nmi_armed <= SYNTHESIZED_WIRE_10;
end
end
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
in_nmi_ALTERA_SYNTHESIZED <= 0;
end
else
if (test1)
begin
in_nmi_ALTERA_SYNTHESIZED <= nmi_armed;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_inst44 <= 0;
end
else
if (test1)
begin
DFFE_inst44 <= int_armed;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_12)
begin
if (!SYNTHESIZED_WIRE_12)
begin
int_armed <= 0;
end
else
begin
int_armed <= SYNTHESIZED_WIRE_13;
end
end
assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset;
assign SYNTHESIZED_WIRE_8 = ~ctl_no_ints;
always@(posedge clk or negedge SYNTHESIZED_WIRE_15)
begin
if (!SYNTHESIZED_WIRE_15)
begin
iff1 <= 0;
end
else
if (SYNTHESIZED_WIRE_17)
begin
iff1 <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_21)
begin
if (!SYNTHESIZED_WIRE_21)
begin
DFFE_instIFF2 <= 0;
end
else
if (ctl_iffx_we)
begin
DFFE_instIFF2 <= ctl_iffx_bit;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
im1 <= 0;
end
else
if (ctl_im_we)
begin
im1 <= SYNTHESIZED_WIRE_19;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
im2 <= 0;
end
else
if (ctl_im_we)
begin
im2 <= SYNTHESIZED_WIRE_20;
end
end
assign SYNTHESIZED_WIRE_3 = ~in_intr_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_11 = ~in_intr_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_7 = ~in_nmi_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_14 = ~in_nmi_ALTERA_SYNTHESIZED;
assign in_nmi = in_nmi_ALTERA_SYNTHESIZED;
assign in_intr = in_intr_ALTERA_SYNTHESIZED;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:56:46 2016"
module ir(
ctl_ir_we,
clk,
nreset,
nhold_clk_wait,
db,
opcode
);
input wire ctl_ir_we;
input wire clk;
input wire nreset;
input wire nhold_clk_wait;
input wire [7:0] db;
output reg [7:0] opcode;
wire SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_0 = ctl_ir_we & nhold_clk_wait;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
opcode[7:0] <= 8'b00000000;
end
else
if (SYNTHESIZED_WIRE_0)
begin
opcode[7:0] <= db[7:0];
end
end
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Dec 09 19:14:29 2018"
module memory_ifc(
clk,
nM1_int,
ctl_mRead,
ctl_mWrite,
in_intr,
nreset,
fIORead,
fIOWrite,
setM1,
ctl_iorw,
timings_en,
iorq_Tw,
nhold_clk_wait,
nM1_out,
nRFSH_out,
nMREQ_out,
nRD_out,
nWR_out,
nIORQ_out,
latch_wait,
wait_m1
);
input wire clk;
input wire nM1_int;
input wire ctl_mRead;
input wire ctl_mWrite;
input wire in_intr;
input wire nreset;
input wire fIORead;
input wire fIOWrite;
input wire setM1;
input wire ctl_iorw;
input wire timings_en;
input wire iorq_Tw;
input wire nhold_clk_wait;
output wire nM1_out;
output wire nRFSH_out;
output wire nMREQ_out;
output wire nRD_out;
output wire nWR_out;
output wire nIORQ_out;
output wire latch_wait;
output wire wait_m1;
wire intr_iorq;
wire ioRead;
wire iorq;
wire ioWrite;
wire m1_mreq;
wire mrd_mreq;
wire mwr_mreq;
reg mwr_wr;
wire nMEMRQ_int;
wire nq2;
reg q1;
reg q2;
wire wait_io;
reg wait_iorq;
reg wait_iorqinta;
reg wait_m_ALTERA_SYNTHESIZED1;
reg wait_mrd;
reg wait_mwr;
wire SYNTHESIZED_WIRE_0;
reg DFFE_m1_ff3;
wire SYNTHESIZED_WIRE_1;
reg DFFE_iorq_ff4;
reg SYNTHESIZED_WIRE_15;
reg DFFE_mrd_ff3;
reg DFFE_intr_ff3;
wire SYNTHESIZED_WIRE_2;
reg SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_3;
reg SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
reg DFFE_iorq_ff1;
reg DFFE_m1_ff1;
reg DFFE_mrd_ff1;
reg DFFE_mwr_ff1;
reg DFFE_mreq_ff2;
assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
assign ioRead = iorq & fIORead;
assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
assign m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
assign iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;
assign ioWrite = iorq & fIOWrite;
assign latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
assign nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
assign nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
assign mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
assign nWR_out = ~(ioWrite | mwr_wr);
assign mwr_mreq = mwr_wr | wait_mwr;
assign nIORQ_out = ~(intr_iorq | iorq);
assign wait_io = wait_iorqinta | wait_iorq;
assign intr_iorq = DFFE_intr_ff3 | wait_iorqinta;
assign nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;
assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);
assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_iorqinta <= 0;
end
else
begin
wait_iorqinta <= iorq_Tw;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_intr_ff3 <= 0;
end
else
if (nhold_clk_wait)
begin
DFFE_intr_ff3 <= wait_iorqinta;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_iorq_ff1 <= 0;
end
else
if (timings_en)
begin
DFFE_iorq_ff1 <= ctl_iorw;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_15 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_iorq <= 0;
end
else
if (timings_en)
begin
wait_iorq <= SYNTHESIZED_WIRE_15;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_iorq_ff4 <= 0;
end
else
if (timings_en)
begin
DFFE_iorq_ff4 <= wait_iorq;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_16 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_16 <= nM1_int;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_m1_ff1 <= 1;
end
else
if (timings_en)
begin
DFFE_m1_ff1 <= setM1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_m_ALTERA_SYNTHESIZED1 <= 0;
end
else
if (timings_en)
begin
wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_m1_ff3 <= 0;
end
else
if (timings_en)
begin
DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_mrd_ff1 <= 0;
end
else
if (timings_en)
begin
DFFE_mrd_ff1 <= ctl_mRead;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_mrd <= 0;
end
else
if (timings_en)
begin
wait_mrd <= DFFE_mrd_ff1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_mrd_ff3 <= 0;
end
else
if (timings_en)
begin
DFFE_mrd_ff3 <= wait_mrd;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_17 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
DFFE_mreq_ff2 <= 0;
end
else
if (timings_en)
begin
DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_mwr_ff1 <= 0;
end
else
if (timings_en)
begin
DFFE_mwr_ff1 <= ctl_mWrite;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
wait_mwr <= 0;
end
else
if (timings_en)
begin
wait_mwr <= DFFE_mwr_ff1;
end
end
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
begin
mwr_wr <= 0;
end
else
if (timings_en)
begin
mwr_wr <= wait_mwr;
end
end
assign SYNTHESIZED_WIRE_18 = ~clk;
assign nq2 = ~q2;
assign SYNTHESIZED_WIRE_2 = ~nreset;
assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
q1 <= 0;
end
else
if (timings_en)
begin
q1 <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
q2 <= 0;
end
else
if (timings_en)
begin
q2 <= q1;
end
end
assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 16 21:18:37 2014"
module pin_control(
fFetch,
fMRead,
fMWrite,
fIORead,
fIOWrite,
T1,
T2,
T3,
T4,
bus_ab_pin_we,
bus_db_pin_oe,
bus_db_pin_re
);
input wire fFetch;
input wire fMRead;
input wire fMWrite;
input wire fIORead;
input wire fIOWrite;
input wire T1;
input wire T2;
input wire T3;
input wire T4;
output wire bus_ab_pin_we;
output wire bus_db_pin_oe;
output wire bus_db_pin_re;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
assign SYNTHESIZED_WIRE_9 = fFetch | fMWrite | fMRead | fIORead | fIOWrite | fIOWrite;
assign SYNTHESIZED_WIRE_7 = T3 | T2;
assign bus_db_pin_oe = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_3 = T3 & fIORead;
assign bus_db_pin_re = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
assign bus_ab_pin_we = SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6;
assign SYNTHESIZED_WIRE_8 = T2 | T3 | T4;
assign SYNTHESIZED_WIRE_1 = fMWrite & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_8 & fIOWrite;
assign SYNTHESIZED_WIRE_4 = T2 & fFetch;
assign SYNTHESIZED_WIRE_2 = T2 & fMRead;
assign SYNTHESIZED_WIRE_6 = T3 & fFetch;
assign SYNTHESIZED_WIRE_5 = T1 & SYNTHESIZED_WIRE_9;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
//=====================================================================================
// This file is automatically generated by the z80_pla_checker tool. Do not edit!
//=====================================================================================
module pla_decode
(
input wire [6:0] prefix,
input wire [7:0] opcode,
output wire [104:0] pla
);
assign pla[ 0] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110100) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldx/cpx/inx/outx brk
assign pla[ 1] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11011001) ? 1'b1 : 1'b0; // exx
assign pla[ 2] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101011) ? 1'b1 : 1'b0; // ex de,hl
assign pla[ 3] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11011111) == 15'b0000100_11011101) ? 1'b1 : 1'b0; // IX/IY prefix
assign pla[ 5] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11111001) ? 1'b1 : 1'b0; // ld sp,hl
assign pla[ 6] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101001) ? 1'b1 : 1'b0; // jp hl
assign pla[ 7] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000001) ? 1'b1 : 1'b0; // ld rr,nn
assign pla[ 8] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld (rr),a/a,(rr)
assign pla[ 9] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000011) ? 1'b1 : 1'b0; // inc/dec rr
assign pla[ 10] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11100011) ? 1'b1 : 1'b0; // ex (sp),hl
assign pla[ 11] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100001) ? 1'b1 : 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 12] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 13] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld direction
assign pla[ 15] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01100111) ? 1'b1 : 1'b0; // rrd/rld
assign pla[ 16] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_11000101) ? 1'b1 : 1'b0; // push rr
assign pla[ 17] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000110) ? 1'b1 : 1'b0; // ld r,n
assign pla[ 20] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100011) ? 1'b1 : 1'b0; // outx/otxr
assign pla[ 21] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/inxr
assign pla[ 23] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001011) == 15'b0000100_11000001) ? 1'b1 : 1'b0; // push/pop
assign pla[ 24] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001101) ? 1'b1 : 1'b0; // call nn
assign pla[ 25] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000111) ? 1'b1 : 1'b0; // rlca/rla/rrca/rra
assign pla[ 26] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00010000) ? 1'b1 : 1'b0; // djnz e
assign pla[ 27] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000110) == 15'b0000001_01000000) ? 1'b1 : 1'b0; // in/out r,(c)
assign pla[ 28] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a
assign pla[ 29] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11000011) ? 1'b1 : 1'b0; // jp nn
assign pla[ 30] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00100010) ? 1'b1 : 1'b0; // ld hl,(nn)/(nn),hl
assign pla[ 31] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld rr,(nn)/(nn),rr
assign pla[ 33] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11001111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld direction
assign pla[ 34] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000001) ? 1'b1 : 1'b0; // out (c),r
assign pla[ 35] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001001) ? 1'b1 : 1'b0; // ret
assign pla[ 37] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a/a,(n)
assign pla[ 38] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00110010) ? 1'b1 : 1'b0; // ld (nn),a/a,(nn)
assign pla[ 39] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00001000) ? 1'b1 : 1'b0; // ex af,af'
assign pla[ 40] = (({prefix[6:0], opcode[7:0]} & 15'b0100100_11111111) == 15'b0100100_00110110) ? 1'b1 : 1'b0; // ld (ix+d),n
assign pla[ 42] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000100) ? 1'b1 : 1'b0; // call cc,nn
assign pla[ 43] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000010) ? 1'b1 : 1'b0; // jp cc,nn
assign pla[ 44] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001011) ? 1'b1 : 1'b0; // CB prefix
assign pla[ 45] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000000) ? 1'b1 : 1'b0; // ret cc
assign pla[ 46] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000101) ? 1'b1 : 1'b0; // reti/retn
assign pla[ 47] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00011000) ? 1'b1 : 1'b0; // jr e
assign pla[ 48] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00100000) ? 1'b1 : 1'b0; // jr ss,e
assign pla[ 49] = (({prefix[6:0], opcode[7:0]} & 15'b0100000_11111111) == 15'b0100000_11001011) ? 1'b1 : 1'b0; // CB prefix with IX/IY
assign pla[ 50] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110110) ? 1'b1 : 1'b0; // ld (hl),n
assign pla[ 51] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101101) ? 1'b1 : 1'b0; // ED prefix
assign pla[ 52] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_10000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cp (hl)
assign pla[ 53] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111110) == 15'b0000100_00110100) ? 1'b1 : 1'b0; // inc/dec (hl)
assign pla[ 55] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_00000111) == 15'b0000010_00000110) ? 1'b1 : 1'b0; // Every CB op (hl)
assign pla[ 56] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000111) ? 1'b1 : 1'b0; // rst p
assign pla[ 57] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01000111) ? 1'b1 : 1'b0; // ld i,a/r,a
assign pla[ 58] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11000111) == 15'b0010100_01000110) ? 1'b1 : 1'b0; // ld r,(hl)
assign pla[ 59] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11111000) == 15'b0010100_01110000) ? 1'b1 : 1'b0; // ld (hl),r
assign pla[ 61] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_01000000) ? 1'b1 : 1'b0; // ld r,r'
assign pla[ 64] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,imm
assign pla[ 65] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_10000000) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,r
assign pla[ 66] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000110) == 15'b0000100_00000100) ? 1'b1 : 1'b0; // inc/dec r
assign pla[ 68] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000010) ? 1'b1 : 1'b0; // adc/sbc hl,rr
assign pla[ 69] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00001001) ? 1'b1 : 1'b0; // add hl,rr
assign pla[ 70] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_00000000) ? 1'b1 : 1'b0; // rlc r
assign pla[ 72] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_01000000) ? 1'b1 : 1'b0; // bit b,r
assign pla[ 73] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_10000000) ? 1'b1 : 1'b0; // res b,r
assign pla[ 74] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_11000000) ? 1'b1 : 1'b0; // set b,r
assign pla[ 75] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000101) ? 1'b1 : 1'b0; // dec r
assign pla[ 76] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00111000) ? 1'b1 : 1'b0; // 111 (CP)
assign pla[ 77] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00100111) ? 1'b1 : 1'b0; // daa
assign pla[ 78] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00010000) ? 1'b1 : 1'b0; // 010 (SUB)
assign pla[ 79] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00011000) ? 1'b1 : 1'b0; // 011 (SBC)
assign pla[ 80] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00001000) ? 1'b1 : 1'b0; // 001 (ADC)
assign pla[ 81] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00101111) ? 1'b1 : 1'b0; // cpl
assign pla[ 82] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000100) ? 1'b1 : 1'b0; // neg
assign pla[ 83] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01010111) ? 1'b1 : 1'b0; // ld a,i/a,r
assign pla[ 84] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00000000) ? 1'b1 : 1'b0; // 000 (ADD)
assign pla[ 85] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00100000) ? 1'b1 : 1'b0; // 100 (AND)
assign pla[ 86] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00110000) ? 1'b1 : 1'b0; // 110 (OR)
assign pla[ 88] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00101000) ? 1'b1 : 1'b0; // 101 (XOR)
assign pla[ 89] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00111111) ? 1'b1 : 1'b0; // ccf
assign pla[ 91] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100110) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/outx/inxr/otxr
assign pla[ 92] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110111) ? 1'b1 : 1'b0; // scf
assign pla[ 95] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_01110110) ? 1'b1 : 1'b0; // halt
assign pla[ 96] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000110) ? 1'b1 : 1'b0; // im n
assign pla[ 97] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11110011) ? 1'b1 : 1'b0; // di/ei
assign pla[ 99] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000001) == 15'b0000000_00000001) ? 1'b1 : 1'b0; // opcode[0]
assign pla[100] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000010) == 15'b0000000_00000010) ? 1'b1 : 1'b0; // opcode[1]
assign pla[101] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000100) == 15'b0000000_00000100) ? 1'b1 : 1'b0; // opcode[2]
assign pla[102] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00001000) == 15'b0000000_00001000) ? 1'b1 : 1'b0; // opcode[3]
assign pla[103] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00010000) == 15'b0000000_00010000) ? 1'b1 : 1'b0; // opcode[4]
assign pla[104] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00100000) == 15'b0000000_00100000) ? 1'b1 : 1'b0; // opcode[5]
// Entries not used by our timing matrix
assign pla[ 67] = 1'b0; // in
assign pla[ 62] = 1'b0; // For all CB opcodes
assign pla[ 54] = 1'b0; // Every CB with IX/IY
assign pla[ 22] = 1'b0; // CB prefix w/o IX/IY
assign pla[ 14] = 1'b0; // dec rr
assign pla[ 4] = 1'b0; // ld x,a/a,x
// Duplicate entries
assign pla[ 18] = 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 19] = 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 32] = 1'b0; // ld i,a/a,i/r,a/a,r
assign pla[ 36] = 1'b0; // ld(rr),a/a,(rr)
assign pla[ 41] = 1'b0; // IX/IY
assign pla[ 60] = 1'b0; // rrd/rld
assign pla[ 63] = 1'b0; // ld r,*
assign pla[ 71] = 1'b0; // rlca/rla/rrca/rra
assign pla[ 87] = 1'b0; // ld a,i / ld a,r
assign pla[ 90] = 1'b0; // djnz *
assign pla[ 93] = 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 94] = 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 98] = 1'b0; // out (*),a/in a,(*)
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 09:05:10 2016"
module reg_control(
ctl_reg_exx,
ctl_reg_ex_af,
ctl_reg_ex_de_hl,
ctl_reg_use_sp,
nreset,
ctl_reg_sel_pc,
ctl_reg_sel_ir,
ctl_reg_sel_wz,
ctl_reg_gp_we,
ctl_reg_not_pc,
use_ixiy,
use_ix,
ctl_reg_sys_we_lo,
ctl_reg_sys_we_hi,
ctl_reg_sys_we,
clk,
ctl_sw_4d,
nhold_clk_wait,
ctl_reg_gp_hilo,
ctl_reg_gp_sel,
ctl_reg_sys_hilo,
reg_sel_bc,
reg_sel_bc2,
reg_sel_ix,
reg_sel_iy,
reg_sel_de,
reg_sel_hl,
reg_sel_de2,
reg_sel_hl2,
reg_sel_af,
reg_sel_af2,
reg_sel_wz,
reg_sel_pc,
reg_sel_ir,
reg_sel_sp,
reg_sel_gp_hi,
reg_sel_gp_lo,
reg_sel_sys_lo,
reg_sel_sys_hi,
reg_gp_we,
reg_sys_we_lo,
reg_sys_we_hi,
reg_sw_4d_lo,
reg_sw_4d_hi
);
input wire ctl_reg_exx;
input wire ctl_reg_ex_af;
input wire ctl_reg_ex_de_hl;
input wire ctl_reg_use_sp;
input wire nreset;
input wire ctl_reg_sel_pc;
input wire ctl_reg_sel_ir;
input wire ctl_reg_sel_wz;
input wire ctl_reg_gp_we;
input wire ctl_reg_not_pc;
input wire use_ixiy;
input wire use_ix;
input wire ctl_reg_sys_we_lo;
input wire ctl_reg_sys_we_hi;
input wire ctl_reg_sys_we;
input wire clk;
input wire ctl_sw_4d;
input wire nhold_clk_wait;
input wire [1:0] ctl_reg_gp_hilo;
input wire [1:0] ctl_reg_gp_sel;
input wire [1:0] ctl_reg_sys_hilo;
output wire reg_sel_bc;
output wire reg_sel_bc2;
output wire reg_sel_ix;
output wire reg_sel_iy;
output wire reg_sel_de;
output wire reg_sel_hl;
output wire reg_sel_de2;
output wire reg_sel_hl2;
output wire reg_sel_af;
output wire reg_sel_af2;
output wire reg_sel_wz;
output wire reg_sel_pc;
output wire reg_sel_ir;
output wire reg_sel_sp;
output wire reg_sel_gp_hi;
output wire reg_sel_gp_lo;
output wire reg_sel_sys_lo;
output wire reg_sel_sys_hi;
output wire reg_gp_we;
output wire reg_sys_we_lo;
output wire reg_sys_we_hi;
output wire reg_sw_4d_lo;
output wire reg_sw_4d_hi;
reg bank_af;
reg bank_exx;
reg bank_hl_de1;
reg bank_hl_de2;
wire reg_sys_we_lo_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_52;
wire SYNTHESIZED_WIRE_53;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_54;
wire SYNTHESIZED_WIRE_55;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_56;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_57;
wire SYNTHESIZED_WIRE_58;
wire SYNTHESIZED_WIRE_59;
wire SYNTHESIZED_WIRE_60;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_23;
wire SYNTHESIZED_WIRE_24;
wire SYNTHESIZED_WIRE_25;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;
wire SYNTHESIZED_WIRE_32;
wire SYNTHESIZED_WIRE_61;
wire SYNTHESIZED_WIRE_34;
wire SYNTHESIZED_WIRE_36;
wire SYNTHESIZED_WIRE_37;
wire SYNTHESIZED_WIRE_38;
wire SYNTHESIZED_WIRE_39;
wire SYNTHESIZED_WIRE_40;
wire SYNTHESIZED_WIRE_41;
wire SYNTHESIZED_WIRE_42;
wire SYNTHESIZED_WIRE_43;
wire SYNTHESIZED_WIRE_44;
wire SYNTHESIZED_WIRE_45;
wire SYNTHESIZED_WIRE_46;
wire SYNTHESIZED_WIRE_47;
wire SYNTHESIZED_WIRE_48;
wire SYNTHESIZED_WIRE_49;
wire SYNTHESIZED_WIRE_50;
assign reg_sel_wz = ctl_reg_sel_wz;
assign reg_sel_ir = ctl_reg_sel_ir;
assign reg_sel_gp_hi = ctl_reg_gp_hilo[1];
assign reg_sel_gp_lo = ctl_reg_gp_hilo[0];
assign reg_sel_sys_lo = ctl_reg_sys_hilo[0];
assign reg_sel_sys_hi = ctl_reg_sys_hilo[1];
assign reg_gp_we = ctl_reg_gp_we;
assign reg_sw_4d_lo = ctl_sw_4d;
assign reg_sel_bc = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53;
assign reg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_54;
assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_55 & SYNTHESIZED_WIRE_5;
assign reg_sel_sp = SYNTHESIZED_WIRE_55 & ctl_reg_use_sp;
assign SYNTHESIZED_WIRE_5 = ~ctl_reg_use_sp;
assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
assign SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
assign reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;
assign SYNTHESIZED_WIRE_2 = ~bank_af;
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
assign reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;
assign reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;
assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
assign SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_53 = ~bank_exx;
assign SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
assign SYNTHESIZED_WIRE_60 = ~bank_hl_de1;
assign reg_sys_we_hi = ctl_reg_sys_we | ctl_reg_sys_we_hi;
assign reg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32;
assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_61 & SYNTHESIZED_WIRE_34;
assign SYNTHESIZED_WIRE_32 = ~ctl_reg_not_pc;
assign SYNTHESIZED_WIRE_36 = ~ctl_reg_gp_sel[1];
assign reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we;
assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
assign SYNTHESIZED_WIRE_42 = ~ctl_reg_gp_sel[0];
assign SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;
assign SYNTHESIZED_WIRE_34 = ~use_ixiy;
assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_af <= 0;
end
else
if (nhold_clk_wait)
begin
bank_af <= bank_af ^ ctl_reg_ex_af;
end
end
assign SYNTHESIZED_WIRE_10 = ~use_ix;
assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
assign SYNTHESIZED_WIRE_41 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
assign SYNTHESIZED_WIRE_40 = ~SYNTHESIZED_WIRE_37;
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39;
assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;
assign SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;
assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_hl_de2 <= 0;
end
else
if (nhold_clk_wait)
begin
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
end
end
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45;
assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47;
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_hl_de1 <= 0;
end
else
if (nhold_clk_wait)
begin
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_exx <= 0;
end
else
if (nhold_clk_wait)
begin
bank_exx <= bank_exx ^ ctl_reg_exx;
end
end
assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
endmodule

583
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@@ -0,0 +1,583 @@
//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Mar 08 06:12:46 2016"
module reg_file(
reg_sel_sys_lo,
reg_sel_gp_lo,
reg_sel_sys_hi,
reg_sel_gp_hi,
reg_sel_ir,
reg_sel_pc,
ctl_sw_4u,
reg_sel_wz,
reg_sel_sp,
reg_sel_iy,
reg_sel_ix,
reg_sel_hl2,
reg_sel_hl,
reg_sel_de2,
reg_sel_de,
reg_sel_bc2,
reg_sel_bc,
reg_sel_af2,
reg_sel_af,
reg_gp_we,
reg_sys_we_lo,
reg_sys_we_hi,
ctl_reg_in_hi,
ctl_reg_in_lo,
ctl_reg_out_lo,
ctl_reg_out_hi,
clk,
reg_sw_4d_lo,
reg_sw_4d_hi,
db_hi_as,
db_hi_ds,
db_lo_as,
db_lo_ds
);
input wire reg_sel_sys_lo;
input wire reg_sel_gp_lo;
input wire reg_sel_sys_hi;
input wire reg_sel_gp_hi;
input wire reg_sel_ir;
input wire reg_sel_pc;
input wire ctl_sw_4u;
input wire reg_sel_wz;
input wire reg_sel_sp;
input wire reg_sel_iy;
input wire reg_sel_ix;
input wire reg_sel_hl2;
input wire reg_sel_hl;
input wire reg_sel_de2;
input wire reg_sel_de;
input wire reg_sel_bc2;
input wire reg_sel_bc;
input wire reg_sel_af2;
input wire reg_sel_af;
input wire reg_gp_we;
input wire reg_sys_we_lo;
input wire reg_sys_we_hi;
input wire ctl_reg_in_hi;
input wire ctl_reg_in_lo;
input wire ctl_reg_out_lo;
input wire ctl_reg_out_hi;
input wire clk;
input wire reg_sw_4d_lo;
input wire reg_sw_4d_hi;
inout wire [7:0] db_hi_as;
inout wire [7:0] db_hi_ds;
inout wire [7:0] db_lo_as;
inout wire [7:0] db_lo_ds;
wire [7:0] gdfx_temp0;
wire [7:0] gdfx_temp1;
wire SYNTHESIZED_WIRE_84;
wire SYNTHESIZED_WIRE_85;
wire SYNTHESIZED_WIRE_86;
wire SYNTHESIZED_WIRE_28;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;
wire SYNTHESIZED_WIRE_32;
wire SYNTHESIZED_WIRE_33;
wire SYNTHESIZED_WIRE_34;
wire SYNTHESIZED_WIRE_35;
wire SYNTHESIZED_WIRE_36;
wire SYNTHESIZED_WIRE_37;
wire SYNTHESIZED_WIRE_38;
wire SYNTHESIZED_WIRE_39;
wire SYNTHESIZED_WIRE_40;
wire SYNTHESIZED_WIRE_41;
wire SYNTHESIZED_WIRE_42;
wire SYNTHESIZED_WIRE_43;
wire SYNTHESIZED_WIRE_44;
wire SYNTHESIZED_WIRE_45;
wire SYNTHESIZED_WIRE_46;
wire SYNTHESIZED_WIRE_47;
wire SYNTHESIZED_WIRE_48;
wire SYNTHESIZED_WIRE_49;
wire SYNTHESIZED_WIRE_50;
wire SYNTHESIZED_WIRE_51;
wire SYNTHESIZED_WIRE_52;
wire SYNTHESIZED_WIRE_53;
wire SYNTHESIZED_WIRE_54;
wire SYNTHESIZED_WIRE_55;
wire SYNTHESIZED_WIRE_56;
wire SYNTHESIZED_WIRE_57;
wire SYNTHESIZED_WIRE_58;
wire SYNTHESIZED_WIRE_59;
wire SYNTHESIZED_WIRE_60;
wire SYNTHESIZED_WIRE_61;
wire SYNTHESIZED_WIRE_62;
wire SYNTHESIZED_WIRE_63;
wire SYNTHESIZED_WIRE_64;
wire SYNTHESIZED_WIRE_65;
wire SYNTHESIZED_WIRE_66;
wire SYNTHESIZED_WIRE_67;
wire SYNTHESIZED_WIRE_68;
wire SYNTHESIZED_WIRE_69;
wire SYNTHESIZED_WIRE_70;
wire SYNTHESIZED_WIRE_71;
wire SYNTHESIZED_WIRE_72;
wire SYNTHESIZED_WIRE_73;
wire SYNTHESIZED_WIRE_74;
wire SYNTHESIZED_WIRE_75;
wire SYNTHESIZED_WIRE_76;
wire SYNTHESIZED_WIRE_77;
wire SYNTHESIZED_WIRE_78;
wire SYNTHESIZED_WIRE_79;
wire SYNTHESIZED_WIRE_80;
wire SYNTHESIZED_WIRE_81;
wire SYNTHESIZED_WIRE_82;
wire SYNTHESIZED_WIRE_83;
assign SYNTHESIZED_WIRE_82 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_wz;
assign SYNTHESIZED_WIRE_80 = reg_sel_wz & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
assign SYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_sp;
assign SYNTHESIZED_WIRE_76 = reg_sel_sp & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_84 = ~reg_sys_we_lo;
assign SYNTHESIZED_WIRE_71 = reg_sel_gp_lo & reg_gp_we & reg_sel_iy;
assign SYNTHESIZED_WIRE_85 = ~reg_sys_we_hi;
assign SYNTHESIZED_WIRE_74 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_pc;
assign SYNTHESIZED_WIRE_67 = reg_sel_gp_lo & reg_gp_we & reg_sel_ix;
assign SYNTHESIZED_WIRE_55 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl2;
assign SYNTHESIZED_WIRE_72 = reg_sel_pc & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
assign SYNTHESIZED_WIRE_59 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl;
assign SYNTHESIZED_WIRE_47 = reg_sel_gp_lo & reg_gp_we & reg_sel_de2;
assign SYNTHESIZED_WIRE_51 = reg_sel_gp_lo & reg_gp_we & reg_sel_de;
assign SYNTHESIZED_WIRE_81 = reg_sel_wz & reg_sys_we_hi & reg_sel_sys_hi;
assign SYNTHESIZED_WIRE_86 = ~reg_gp_we;
assign SYNTHESIZED_WIRE_70 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_iy;
assign SYNTHESIZED_WIRE_68 = reg_sel_iy & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_39 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc2;
assign SYNTHESIZED_WIRE_43 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc;
assign SYNTHESIZED_WIRE_31 = reg_sel_gp_lo & reg_gp_we & reg_sel_af2;
assign SYNTHESIZED_WIRE_77 = reg_sel_sp & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_66 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_ix;
assign SYNTHESIZED_WIRE_64 = reg_sel_ix & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_35 = reg_sel_gp_lo & reg_gp_we & reg_sel_af;
assign SYNTHESIZED_WIRE_69 = reg_sel_iy & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_63 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_ir;
assign SYNTHESIZED_WIRE_65 = reg_sel_ix & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_53 = reg_sel_hl2 & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl2;
assign SYNTHESIZED_WIRE_52 = reg_sel_hl2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_57 = reg_sel_hl & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_45 = reg_sel_de2 & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_49 = reg_sel_de & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_37 = reg_sel_bc2 & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl;
assign SYNTHESIZED_WIRE_56 = reg_sel_hl & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_75 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_pc;
assign SYNTHESIZED_WIRE_41 = reg_sel_bc & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_29 = reg_sel_af2 & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_33 = reg_sel_af & reg_gp_we & reg_sel_gp_hi;
assign SYNTHESIZED_WIRE_61 = reg_sel_ir & reg_sys_we_hi & reg_sel_sys_hi;
assign SYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de2;
assign SYNTHESIZED_WIRE_44 = reg_sel_de2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_73 = reg_sel_pc & reg_sys_we_hi & reg_sel_sys_hi;
assign SYNTHESIZED_WIRE_83 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_wz;
assign SYNTHESIZED_WIRE_50 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de;
assign SYNTHESIZED_WIRE_48 = reg_sel_de & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc2;
assign SYNTHESIZED_WIRE_36 = reg_sel_bc2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc;
assign SYNTHESIZED_WIRE_40 = reg_sel_bc & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af2;
assign SYNTHESIZED_WIRE_28 = reg_sel_af2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_62 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_ir;
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af;
assign SYNTHESIZED_WIRE_32 = reg_sel_af & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
assign SYNTHESIZED_WIRE_60 = reg_sel_ir & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
assign SYNTHESIZED_WIRE_79 = reg_sel_gp_lo & reg_gp_we & reg_sel_sp;
reg_latch b2v_latch_af2_hi(
.oe(SYNTHESIZED_WIRE_28),
.we(SYNTHESIZED_WIRE_29),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_af2_lo(
.oe(SYNTHESIZED_WIRE_30),
.we(SYNTHESIZED_WIRE_31),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_af_hi(
.oe(SYNTHESIZED_WIRE_32),
.we(SYNTHESIZED_WIRE_33),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_af_lo(
.oe(SYNTHESIZED_WIRE_34),
.we(SYNTHESIZED_WIRE_35),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_bc2_hi(
.oe(SYNTHESIZED_WIRE_36),
.we(SYNTHESIZED_WIRE_37),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_bc2_lo(
.oe(SYNTHESIZED_WIRE_38),
.we(SYNTHESIZED_WIRE_39),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_bc_hi(
.oe(SYNTHESIZED_WIRE_40),
.we(SYNTHESIZED_WIRE_41),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_bc_lo(
.oe(SYNTHESIZED_WIRE_42),
.we(SYNTHESIZED_WIRE_43),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_de2_hi(
.oe(SYNTHESIZED_WIRE_44),
.we(SYNTHESIZED_WIRE_45),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_de2_lo(
.oe(SYNTHESIZED_WIRE_46),
.we(SYNTHESIZED_WIRE_47),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_de_hi(
.oe(SYNTHESIZED_WIRE_48),
.we(SYNTHESIZED_WIRE_49),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_de_lo(
.oe(SYNTHESIZED_WIRE_50),
.we(SYNTHESIZED_WIRE_51),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_hl2_hi(
.oe(SYNTHESIZED_WIRE_52),
.we(SYNTHESIZED_WIRE_53),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_hl2_lo(
.oe(SYNTHESIZED_WIRE_54),
.we(SYNTHESIZED_WIRE_55),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_hl_hi(
.oe(SYNTHESIZED_WIRE_56),
.we(SYNTHESIZED_WIRE_57),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_hl_lo(
.oe(SYNTHESIZED_WIRE_58),
.we(SYNTHESIZED_WIRE_59),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_ir_hi(
.oe(SYNTHESIZED_WIRE_60),
.we(SYNTHESIZED_WIRE_61),
.clk(clk),
.db(db_hi_as)
);
reg_latch b2v_latch_ir_lo(
.oe(SYNTHESIZED_WIRE_62),
.we(SYNTHESIZED_WIRE_63),
.clk(clk),
.db(db_lo_as)
);
reg_latch b2v_latch_ix_hi(
.oe(SYNTHESIZED_WIRE_64),
.we(SYNTHESIZED_WIRE_65),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_ix_lo(
.oe(SYNTHESIZED_WIRE_66),
.we(SYNTHESIZED_WIRE_67),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_iy_hi(
.oe(SYNTHESIZED_WIRE_68),
.we(SYNTHESIZED_WIRE_69),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_iy_lo(
.oe(SYNTHESIZED_WIRE_70),
.we(SYNTHESIZED_WIRE_71),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_pc_hi(
.oe(SYNTHESIZED_WIRE_72),
.we(SYNTHESIZED_WIRE_73),
.clk(clk),
.db(db_hi_as)
);
reg_latch b2v_latch_pc_lo(
.oe(SYNTHESIZED_WIRE_74),
.we(SYNTHESIZED_WIRE_75),
.clk(clk),
.db(db_lo_as)
);
reg_latch b2v_latch_sp_hi(
.oe(SYNTHESIZED_WIRE_76),
.we(SYNTHESIZED_WIRE_77),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_sp_lo(
.oe(SYNTHESIZED_WIRE_78),
.we(SYNTHESIZED_WIRE_79),
.clk(clk),
.db(gdfx_temp0)
);
reg_latch b2v_latch_wz_hi(
.oe(SYNTHESIZED_WIRE_80),
.we(SYNTHESIZED_WIRE_81),
.clk(clk),
.db(gdfx_temp1)
);
reg_latch b2v_latch_wz_lo(
.oe(SYNTHESIZED_WIRE_82),
.we(SYNTHESIZED_WIRE_83),
.clk(clk),
.db(gdfx_temp0)
);
assign gdfx_temp0[7] = ctl_sw_4u ? db_lo_as[7] : 1'bz;
assign gdfx_temp0[6] = ctl_sw_4u ? db_lo_as[6] : 1'bz;
assign gdfx_temp0[5] = ctl_sw_4u ? db_lo_as[5] : 1'bz;
assign gdfx_temp0[4] = ctl_sw_4u ? db_lo_as[4] : 1'bz;
assign gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz;
assign gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz;
assign gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz;
assign gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz;
assign db_lo_as[7] = reg_sw_4d_lo ? gdfx_temp0[7] : 1'bz;
assign db_lo_as[6] = reg_sw_4d_lo ? gdfx_temp0[6] : 1'bz;
assign db_lo_as[5] = reg_sw_4d_lo ? gdfx_temp0[5] : 1'bz;
assign db_lo_as[4] = reg_sw_4d_lo ? gdfx_temp0[4] : 1'bz;
assign db_lo_as[3] = reg_sw_4d_lo ? gdfx_temp0[3] : 1'bz;
assign db_lo_as[2] = reg_sw_4d_lo ? gdfx_temp0[2] : 1'bz;
assign db_lo_as[1] = reg_sw_4d_lo ? gdfx_temp0[1] : 1'bz;
assign db_lo_as[0] = reg_sw_4d_lo ? gdfx_temp0[0] : 1'bz;
assign gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz;
assign gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz;
assign gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz;
assign gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz;
assign gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz;
assign gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz;
assign gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz;
assign gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz;
assign db_hi_as[7] = reg_sw_4d_hi ? gdfx_temp1[7] : 1'bz;
assign db_hi_as[6] = reg_sw_4d_hi ? gdfx_temp1[6] : 1'bz;
assign db_hi_as[5] = reg_sw_4d_hi ? gdfx_temp1[5] : 1'bz;
assign db_hi_as[4] = reg_sw_4d_hi ? gdfx_temp1[4] : 1'bz;
assign db_hi_as[3] = reg_sw_4d_hi ? gdfx_temp1[3] : 1'bz;
assign db_hi_as[2] = reg_sw_4d_hi ? gdfx_temp1[2] : 1'bz;
assign db_hi_as[1] = reg_sw_4d_hi ? gdfx_temp1[1] : 1'bz;
assign db_hi_as[0] = reg_sw_4d_hi ? gdfx_temp1[0] : 1'bz;
assign db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz;
assign db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz;
assign db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz;
assign db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz;
assign db_lo_ds[3] = ctl_reg_out_lo ? gdfx_temp0[3] : 1'bz;
assign db_lo_ds[2] = ctl_reg_out_lo ? gdfx_temp0[2] : 1'bz;
assign db_lo_ds[1] = ctl_reg_out_lo ? gdfx_temp0[1] : 1'bz;
assign db_lo_ds[0] = ctl_reg_out_lo ? gdfx_temp0[0] : 1'bz;
assign gdfx_temp0[7] = ctl_reg_in_lo ? db_lo_ds[7] : 1'bz;
assign gdfx_temp0[6] = ctl_reg_in_lo ? db_lo_ds[6] : 1'bz;
assign gdfx_temp0[5] = ctl_reg_in_lo ? db_lo_ds[5] : 1'bz;
assign gdfx_temp0[4] = ctl_reg_in_lo ? db_lo_ds[4] : 1'bz;
assign gdfx_temp0[3] = ctl_reg_in_lo ? db_lo_ds[3] : 1'bz;
assign gdfx_temp0[2] = ctl_reg_in_lo ? db_lo_ds[2] : 1'bz;
assign gdfx_temp0[1] = ctl_reg_in_lo ? db_lo_ds[1] : 1'bz;
assign gdfx_temp0[0] = ctl_reg_in_lo ? db_lo_ds[0] : 1'bz;
assign db_hi_ds[7] = ctl_reg_out_hi ? gdfx_temp1[7] : 1'bz;
assign db_hi_ds[6] = ctl_reg_out_hi ? gdfx_temp1[6] : 1'bz;
assign db_hi_ds[5] = ctl_reg_out_hi ? gdfx_temp1[5] : 1'bz;
assign db_hi_ds[4] = ctl_reg_out_hi ? gdfx_temp1[4] : 1'bz;
assign db_hi_ds[3] = ctl_reg_out_hi ? gdfx_temp1[3] : 1'bz;
assign db_hi_ds[2] = ctl_reg_out_hi ? gdfx_temp1[2] : 1'bz;
assign db_hi_ds[1] = ctl_reg_out_hi ? gdfx_temp1[1] : 1'bz;
assign db_hi_ds[0] = ctl_reg_out_hi ? gdfx_temp1[0] : 1'bz;
assign gdfx_temp1[7] = ctl_reg_in_hi ? db_hi_ds[7] : 1'bz;
assign gdfx_temp1[6] = ctl_reg_in_hi ? db_hi_ds[6] : 1'bz;
assign gdfx_temp1[5] = ctl_reg_in_hi ? db_hi_ds[5] : 1'bz;
assign gdfx_temp1[4] = ctl_reg_in_hi ? db_hi_ds[4] : 1'bz;
assign gdfx_temp1[3] = ctl_reg_in_hi ? db_hi_ds[3] : 1'bz;
assign gdfx_temp1[2] = ctl_reg_in_hi ? db_hi_ds[2] : 1'bz;
assign gdfx_temp1[1] = ctl_reg_in_hi ? db_hi_ds[1] : 1'bz;
assign gdfx_temp1[0] = ctl_reg_in_hi ? db_hi_ds[0] : 1'bz;
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Nov 07 10:28:37 2014"
module reg_latch(
we,
oe,
clk,
db
);
input wire we;
input wire oe;
input wire clk;
inout wire [7:0] db;
reg [7:0] latch;
assign db[7] = oe ? latch[7] : 1'bz;
assign db[6] = oe ? latch[6] : 1'bz;
assign db[5] = oe ? latch[5] : 1'bz;
assign db[4] = oe ? latch[4] : 1'bz;
assign db[3] = oe ? latch[3] : 1'bz;
assign db[2] = oe ? latch[2] : 1'bz;
assign db[1] = oe ? latch[1] : 1'bz;
assign db[0] = oe ? latch[0] : 1'bz;
always@(posedge clk)
begin
if (we)
begin
latch[7:0] <= db[7:0];
end
end
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Dec 10 08:57:54 2016"
module resets(
reset_in,
clk,
M1,
T2,
fpga_reset,
nhold_clk_wait,
clrpc,
nreset
);
input wire reset_in;
input wire clk;
input wire M1;
input wire T2;
input wire fpga_reset;
input wire nhold_clk_wait;
output wire clrpc;
output wire nreset;
reg clrpc_int;
wire nclk;
reg x1;
wire x2;
wire x3;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_1;
reg SYNTHESIZED_WIRE_9;
reg DFFE_intr_ff3;
reg SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_3;
reg SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_6;
assign nreset = SYNTHESIZED_WIRE_6;
always@(posedge nclk or negedge SYNTHESIZED_WIRE_8)
begin
if (!SYNTHESIZED_WIRE_8)
begin
x1 <= 1;
end
else
begin
x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;
end
end
assign clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_1 = ~reset_in;
assign x2 = x1 & SYNTHESIZED_WIRE_11;
assign SYNTHESIZED_WIRE_11 = M1 & T2;
assign x3 = x1 & SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_11;
assign nclk = ~clk;
assign SYNTHESIZED_WIRE_8 = ~fpga_reset;
always@(posedge nclk)
begin
if (nhold_clk_wait)
begin
DFFE_intr_ff3 <= SYNTHESIZED_WIRE_9;
end
end
always@(posedge nclk)
begin
if (nhold_clk_wait)
begin
SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;
end
end
always@(posedge nclk)
begin
if (nhold_clk_wait)
begin
SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;
end
end
always@(posedge clk or negedge SYNTHESIZED_WIRE_8)
begin
if (!SYNTHESIZED_WIRE_8)
begin
SYNTHESIZED_WIRE_12 <= 1;
end
else
begin
SYNTHESIZED_WIRE_12 <= x3;
end
end
always@(posedge nclk or negedge SYNTHESIZED_WIRE_6)
begin
if (!SYNTHESIZED_WIRE_6)
begin
clrpc_int <= 0;
end
else
begin
clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;
end
end
endmodule

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//----------------------------------------------------------------------------
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//----------------------------------------------------------------------------
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Feb 13 17:56:57 2016"
module sequencer(
clk,
nextM,
setM1,
nreset,
hold_clk_iorq,
hold_clk_wait,
hold_clk_busrq,
M1,
M2,
M3,
M4,
M5,
T1,
T2,
T3,
T4,
T5,
T6,
timings_en
);
input wire clk;
input wire nextM;
input wire setM1;
input wire nreset;
input wire hold_clk_iorq;
input wire hold_clk_wait;
input wire hold_clk_busrq;
output wire M1;
output wire M2;
output wire M3;
output wire M4;
output reg M5;
output wire T1;
output wire T2;
output wire T3;
output wire T4;
output wire T5;
output reg T6;
output wire timings_en;
wire ena_M;
wire ena_T;
reg DFFE_M4_ff;
wire SYNTHESIZED_WIRE_18;
reg DFFE_T1_ff;
wire SYNTHESIZED_WIRE_19;
reg DFFE_T2_ff;
reg DFFE_T3_ff;
reg DFFE_T4_ff;
reg DFFE_T5_ff;
reg DFFE_M1_ff;
reg DFFE_M2_ff;
reg DFFE_M3_ff;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
assign M1 = DFFE_M1_ff;
assign M2 = DFFE_M2_ff;
assign M3 = DFFE_M3_ff;
assign M4 = DFFE_M4_ff;
assign T1 = DFFE_T1_ff;
assign T2 = DFFE_T2_ff;
assign T3 = DFFE_T3_ff;
assign T4 = DFFE_T4_ff;
assign T5 = DFFE_T5_ff;
assign ena_M = nextM | setM1;
assign SYNTHESIZED_WIRE_12 = DFFE_M4_ff & SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_13 = DFFE_T1_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_14 = DFFE_T2_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_15 = DFFE_T3_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_16 = DFFE_T4_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_17 = DFFE_T5_ff & SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_9 = DFFE_M1_ff & SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_10 = DFFE_M2_ff & SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_11 = DFFE_M3_ff & SYNTHESIZED_WIRE_18;
assign ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq);
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M1_ff <= 1;
end
else
if (ena_M)
begin
DFFE_M1_ff <= setM1;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M2_ff <= 0;
end
else
if (ena_M)
begin
DFFE_M2_ff <= SYNTHESIZED_WIRE_9;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M3_ff <= 0;
end
else
if (ena_M)
begin
DFFE_M3_ff <= SYNTHESIZED_WIRE_10;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_M4_ff <= 0;
end
else
if (ena_M)
begin
DFFE_M4_ff <= SYNTHESIZED_WIRE_11;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
M5 <= 0;
end
else
if (ena_M)
begin
M5 <= SYNTHESIZED_WIRE_12;
end
end
assign SYNTHESIZED_WIRE_19 = ~ena_M;
assign SYNTHESIZED_WIRE_18 = ~setM1;
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T1_ff <= 1;
end
else
if (ena_T)
begin
DFFE_T1_ff <= ena_M;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T2_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T2_ff <= SYNTHESIZED_WIRE_13;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T3_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T3_ff <= SYNTHESIZED_WIRE_14;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T4_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T4_ff <= SYNTHESIZED_WIRE_15;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
DFFE_T5_ff <= 0;
end
else
if (ena_T)
begin
DFFE_T5_ff <= SYNTHESIZED_WIRE_16;
end
end
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
T6 <= 0;
end
else
if (ena_T)
begin
T6 <= SYNTHESIZED_WIRE_17;
end
end
assign timings_en = ena_T;
endmodule

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