195 lines
6.0 KiB
Verilog
195 lines
6.0 KiB
Verilog
//----------------------------------------------------------------------------
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// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//----------------------------------------------------------------------------
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 12:30:20 2014"
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module inc_dec(
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carry_in,
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limit6,
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decrement,
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d,
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address
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);
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input wire carry_in;
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input wire limit6;
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input wire decrement;
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input wire [15:0] d;
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output wire [15:0] address;
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wire [15:0] address_ALTERA_SYNTHESIZED;
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wire SYNTHESIZED_WIRE_40;
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wire SYNTHESIZED_WIRE_41;
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wire SYNTHESIZED_WIRE_42;
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wire SYNTHESIZED_WIRE_43;
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wire SYNTHESIZED_WIRE_44;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_45;
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wire SYNTHESIZED_WIRE_46;
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wire SYNTHESIZED_WIRE_47;
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wire SYNTHESIZED_WIRE_48;
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wire SYNTHESIZED_WIRE_49;
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wire SYNTHESIZED_WIRE_50;
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wire SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_51;
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wire SYNTHESIZED_WIRE_52;
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wire SYNTHESIZED_WIRE_53;
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wire SYNTHESIZED_WIRE_16;
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wire SYNTHESIZED_WIRE_22;
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wire SYNTHESIZED_WIRE_25;
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wire SYNTHESIZED_WIRE_31;
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wire SYNTHESIZED_WIRE_34;
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wire SYNTHESIZED_WIRE_35;
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wire SYNTHESIZED_WIRE_36;
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wire SYNTHESIZED_WIRE_37;
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wire SYNTHESIZED_WIRE_38;
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wire SYNTHESIZED_WIRE_39;
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assign SYNTHESIZED_WIRE_34 = carry_in & SYNTHESIZED_WIRE_40 & SYNTHESIZED_WIRE_41 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44 & SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_45;
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assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_46 & SYNTHESIZED_WIRE_47 & SYNTHESIZED_WIRE_48 & SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_12;
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assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_16;
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inc_dec_2bit b2v_dual_adder_0(
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.carry_borrow_in(carry_in),
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.d1_in(d[1]),
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.d0_in(d[0]),
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.dec1_in(SYNTHESIZED_WIRE_40),
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.dec0_in(SYNTHESIZED_WIRE_41),
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.carry_borrow_out(SYNTHESIZED_WIRE_22),
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.d1_out(address_ALTERA_SYNTHESIZED[1]),
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.d0_out(address_ALTERA_SYNTHESIZED[0]));
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inc_dec_2bit b2v_dual_adder_10(
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.carry_borrow_in(SYNTHESIZED_WIRE_51),
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.d1_in(d[13]),
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.d0_in(d[12]),
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.dec1_in(SYNTHESIZED_WIRE_53),
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.dec0_in(SYNTHESIZED_WIRE_52),
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.carry_borrow_out(SYNTHESIZED_WIRE_37),
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.d1_out(address_ALTERA_SYNTHESIZED[13]),
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.d0_out(address_ALTERA_SYNTHESIZED[12]));
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inc_dec_2bit b2v_dual_adder_2(
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.carry_borrow_in(SYNTHESIZED_WIRE_22),
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.d1_in(d[3]),
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.d0_in(d[2]),
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.dec1_in(SYNTHESIZED_WIRE_45),
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.dec0_in(SYNTHESIZED_WIRE_42),
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.carry_borrow_out(SYNTHESIZED_WIRE_25),
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.d1_out(address_ALTERA_SYNTHESIZED[3]),
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.d0_out(address_ALTERA_SYNTHESIZED[2]));
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inc_dec_2bit b2v_dual_adder_4(
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.carry_borrow_in(SYNTHESIZED_WIRE_25),
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.d1_in(d[5]),
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.d0_in(d[4]),
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.dec1_in(SYNTHESIZED_WIRE_43),
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.dec0_in(SYNTHESIZED_WIRE_44),
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.carry_borrow_out(SYNTHESIZED_WIRE_39),
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.d1_out(address_ALTERA_SYNTHESIZED[5]),
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.d0_out(address_ALTERA_SYNTHESIZED[4]));
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inc_dec_2bit b2v_dual_adder_7(
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.carry_borrow_in(SYNTHESIZED_WIRE_47),
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.d1_in(d[8]),
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.d0_in(d[7]),
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.dec1_in(SYNTHESIZED_WIRE_46),
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.dec0_in(SYNTHESIZED_WIRE_48),
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.carry_borrow_out(SYNTHESIZED_WIRE_31),
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.d1_out(address_ALTERA_SYNTHESIZED[8]),
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.d0_out(address_ALTERA_SYNTHESIZED[7]));
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inc_dec_2bit b2v_dual_adder_9(
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.carry_borrow_in(SYNTHESIZED_WIRE_31),
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.d1_in(d[10]),
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.d0_in(d[9]),
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.dec1_in(SYNTHESIZED_WIRE_50),
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.dec0_in(SYNTHESIZED_WIRE_49),
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.carry_borrow_out(SYNTHESIZED_WIRE_36),
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.d1_out(address_ALTERA_SYNTHESIZED[10]),
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.d0_out(address_ALTERA_SYNTHESIZED[9]));
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assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35;
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assign SYNTHESIZED_WIRE_35 = ~limit6;
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assign SYNTHESIZED_WIRE_41 = d[0] ^ decrement;
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assign SYNTHESIZED_WIRE_40 = d[1] ^ decrement;
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assign SYNTHESIZED_WIRE_50 = d[10] ^ decrement;
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assign SYNTHESIZED_WIRE_12 = d[11] ^ decrement;
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assign address_ALTERA_SYNTHESIZED[11] = SYNTHESIZED_WIRE_36 ^ d[11];
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assign SYNTHESIZED_WIRE_52 = d[12] ^ decrement;
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assign SYNTHESIZED_WIRE_53 = d[13] ^ decrement;
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assign SYNTHESIZED_WIRE_16 = d[14] ^ decrement;
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assign address_ALTERA_SYNTHESIZED[14] = SYNTHESIZED_WIRE_37 ^ d[14];
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assign address_ALTERA_SYNTHESIZED[15] = SYNTHESIZED_WIRE_38 ^ d[15];
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assign SYNTHESIZED_WIRE_42 = d[2] ^ decrement;
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assign SYNTHESIZED_WIRE_45 = d[3] ^ decrement;
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assign SYNTHESIZED_WIRE_44 = d[4] ^ decrement;
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assign SYNTHESIZED_WIRE_43 = d[5] ^ decrement;
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assign SYNTHESIZED_WIRE_5 = d[6] ^ decrement;
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assign address_ALTERA_SYNTHESIZED[6] = SYNTHESIZED_WIRE_39 ^ d[6];
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assign SYNTHESIZED_WIRE_48 = d[7] ^ decrement;
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assign SYNTHESIZED_WIRE_46 = d[8] ^ decrement;
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assign SYNTHESIZED_WIRE_49 = d[9] ^ decrement;
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assign address = address_ALTERA_SYNTHESIZED;
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endmodule
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