tranZPUter SW-700

Website: engineers@work  |  Repository: git.eaw.app/eaw/tranZPUter

---

Automated setup and build (recommended)

The quickest way to a working build is the bundled setup script for your platform. It installs the base tools, installs Java (JRE) for the GLASS Z80 assembler and Docker, builds three reproducible Quartus Docker images, clones this repository --recurse-submodules (initialising the TZFS, zSoft/zOS and zpu submodules), and then offers to run the first build (./build.sh -t all). Quartus is not installed on the host — the CPLD and FPGA builds run inside the Docker images. Each script is self-contained: copy the single file for your platform and run it. The scripts work on Windows, macOS and Linux.

Script	Platform	Notes
setup_tranZPUter.sh	Linux / macOS	Installs base tools + Java (JRE) + Docker, builds the three Quartus images, clones into ~/tranZPUter, offers ./build.sh -t all.
setup_tranZPUter_windows.cmd	Windows 10 / 11	Double-click launcher — sets ASSUME_YES/DIR, runs the .ps1 non-interactively, logs to setup_tranZPUter_log.txt, keeps the window open.
setup_tranZPUter_windows_native.ps1	Windows 10 / 11	winget installs Git for Windows + Docker Desktop, builds the Quartus images, clones into %HOME%\tranZPUter, runs ./build.sh -t all via Git Bash.

Linux / macOS:

chmod +x setup_tranZPUter.sh
./setup_tranZPUter.sh

Windows — double-click setup_tranZPUter_windows.cmd, or from PowerShell:

Set-ExecutionPolicy -Scope Process -ExecutionPolicy Bypass
.\setup_tranZPUter_windows_native.ps1

What it installs

• Base tools for your platform (git, bash/coreutils, curl, etc.).
• Java (JRE) — required to run the GLASS Z80 assembler.
• Docker (Docker Desktop on Windows) — used to run Quartus without installing it on the host.
• Three free Quartus Docker images (Web/Lite Edition, no licence), one per device family, built from docker/QuartusPrime/:

  Image	Quartus	Device family	Used for
  tzpu-quartus:13.0.1	13.0.1	MAX7000AE CPLD	CPLD .pof
  tzpu-quartus:13.1	13.1	Cyclone III (EP3C25)	SW-700 v1.2 FPGA
  tzpu-quartus:17.1	17.1	Cyclone IV (EP4CE75 / EP4CE115)	SW-700 v1.3 / Fusion FPGA

The setup then clones the repository (with submodules) into ~/tranZPUter (Linux/macOS) or %HOME%\tranZPUter (Windows) and offers to run the first build.

Environment overrides

Variable (alias)	Purpose
TZPU_REPO_URL (tranZPUter_REPO_URL)	Repository URL to clone. Default https://git.eaw.app/eaw/tranZPUter.git.
TZPU_DIR (tranZPUter_DIR)	Build in an existing checkout instead of cloning.
TZPU_ASSUME_YES (tranZPUter_ASSUME_YES)=1	Non-interactive; accept all defaults.
TZPU_QUARTUS_CPLD_IMAGE (tranZPUter_CPLD_IMAGE)	Override the CPLD image (default tzpu-quartus:13.0.1).
TZPU_QUARTUS_C3_IMAGE (tranZPUter_FPGA_IMAGE)	Override the Cyclone III image (default tzpu-quartus:13.1).
TZPU_QUARTUS_C4_IMAGE	Override the Cyclone IV image (default tzpu-quartus:17.1).

Output artifacts

All build products are collected under build/output/:

• CPLD programming files — .pof (MAX 7000AE).
• FPGA bitstreams — .sof, plus .jic for the EPCS boot flash so the FPGA reconfigures itself at power-on.
• Software images — zOS (K64F firmware), TZFS, the SA-1510/1Z-013A monitor ROMs and CP/M images.

---

---

The tranZPUter SW-700 is an in-situ upgrade for the Sharp MZ-700 (and, in the current version, the Sharp MZ-2000). It lifts the original Z80 onto the board and, through Z80 bus mastering, adds a Freescale K64F ARM Cortex-M4 I/O processor, a 5V-tolerant MAX 7000A CPLD and an Altera FPGA. Together these let the machine run a faster and/or alternative CPU, far more RAM (enough for 64K CP/M 2.2), a rapid SD-card filing system with the enhanced TZFS monitor, and an upgraded video module — all while keeping the host machine completely original. The name comes from TRANsformable ZPU compuTER; the SW-700 suffix denotes the SoftWare-centric design for the MZ-700.

Board revision matrix

Revision	FPGA	Quartus	Config flash	Notes
v1.2	Cyclone III EP3C25 (25K LE, 76 KB BRAM, 144-pin TQFP)	13.1	EPCS16	First assembled/tested design. Cheaper to produce; maintained on its own git branch.
v1.3	Cyclone IV EP4CE75 / EP4CE115 (75K / 115K LE, 360 / 480 KB BRAM, 484-pin BGA)	17.1	EPCS64	Mainstream design. Larger FPGA → higher-resolution graphics, soft CPUs (T80, ZPU Evolution) and MZ-2000 emulation. Recommended for new builds.
Fusion	Cyclone IV	17.1	EPCS64	FPGA-realised sibling design; shares the v1.3 Cyclone IV tool chain.

The CPLD across all revisions is a 512-macrocell Altera MAX 7000AE (EPM7xxx), built with Quartus II 13.0.1 and chosen for its 5V tolerance, which lets it read/drive the 5V Z80 host bus directly without level-shifting.

Manual build (build.sh)

Once set up, the build is driven by build.sh. It runs the logic tool chains natively when a matching Quartus is found on PATH, otherwise inside the Quartus Docker images above; Java (for GLASS) always runs natively. Run it from the repository root:

./build.sh -t all              # everything (default)
./build.sh -t fpga -V v1.2     # just the v1.2 (Cyclone III) FPGA bitstream
./build.sh -t cpld             # just the CPLD .pof
./build.sh -t software         # zOS + TZFS + monitor ROMs + CP/M
./build.sh -h                  # list all targets and options

Targets and options

Target (-t)	Produces	Tool
cpld	CPLD .pof (MAX7000AE/S)	Quartus 13.0.1
fpga	FPGA .sof + .jic EPCS boot flash	v1.2 → Cyclone III EP3C25 / Quartus 13.1; v1.3 & Fusion → Cyclone IV EP4CE75/EP4CE115 / Quartus 17.1
software	zOS (via the zSoft submodule) + TZFS + SA-1510 monitor ROMs + CP/M	GLASS / Java
all	everything (default)

Option	Meaning	Default
-t	Target: cpld | fpga | software | all	all
-V	Board version: v1.2 | v1.3	v1.3
-M	Machine: MZ80A | MZ700 | MZ2000 | all	all
-D	FPGA device: E115 | E75	E115
-C	FPGA configuration: base | emuMZ | SoftCPU	emuMZ
-m	Method: auto | native | docker	auto

The right Quartus version is auto-selected per device. SoftCPU and base revisions are work in progress. Outputs are collected under build/output/.

---

Hardware

The design lies in Z80 bus mastering — the ability to tri-state the original Z80 and drive the host computer as required. The original Z80 is lifted onto a daughter card and several of its signals rerouted so they can be controlled. Bus mastering is used to transfer data between main memory and the SD card, between the I/O processor and video display buffer (for menu overlays), and to let a soft processor idle the hard Z80 and act as the main CPU, executing from local (K64F/FPGA/512K) memory and only slowing to access host peripherals. The board also intercepts the mainboard video output and routes it through the FPGA video module, where original or enhanced video is selected before being returned to the modulator.

• CPLD (MAX 7000AE, EPM7xxx) — replaces the discrete logic and Flash decoder of the earlier tranZPUter SW. Handles Z80 memory-map decoding, bus control, bi-directional bus control (so a processor inside the FPGA can drive the host), WAIT-state generation, hardware remapping and 5V↔3.3V voltage translation.
• K64F ARM Cortex-M4 — runs zOS, loads the TZFS enhanced monitor, provides the SD drive and assists the alternate MZ-series emulations. A USB console exposes an interactive zOS session for changing CPU frequency, editing/dumping memory, inspecting registers, etc.
• FPGA (Cyclone III on v1.2, Cyclone IV on v1.3 / Fusion) — the video module and soft CPUs (T80, ZPU Evolution). Boots from an EPCS serial configuration device programmed via the Serial Flash Loader (SFL) megafunction over JTAG.

Design versions v1.0/v1.1 were internal and are not published. v1.2 was the first assembled/tested design (used to advance the software and FPGA work). v1.3 is the mainstream design with a more powerful FPGA. v1.2 and v1.3 have fundamental differences in logic and software and are maintained on their own git branches; both are proven, with v1.2 cheaper to produce.

Schematics

Full schematics and PCB artwork for both v1.2 and v1.3 are in the schematics/ and pcb/ directories, grouped by Z80 upgrade, K64F I/O processor, JTAG/oscillator, power supply and video interface. See the web documentation for the annotated walkthroughs:

• tranZPUter SW-700 — Design & Reference
• Technical Guide
• Developer's Guide

---

Software

The firmware spans three components, each built by build.sh -t software:

• zOS (K64F firmware) — a small embedded OS providing SD-card FAT32 initialisation and file I/O, the SVCREQ service-request dispatch, system startup sequencing and an interactive MS-DOS-like console over USB serial. Built from the zSoft submodule with the ARM GCC tool chain. As a soft ZPU Evolution CPU, zOS can also run on the FPGA driving the Sharp MZ keyboard/screen directly, with an ANSI terminal emulator and small apps (tbasic, mbasic, kilo).
• TZFS — the enhanced monitor and filing system. It intercepts the host monitor's command dispatcher transparently (the prompt gains a + TZFS vX.xx suffix), adds rapid SD-card program loading, memory tools and the CP/M / emulation launch commands, while keeping every original monitor command intact. Built from the TZFS submodule and assembled with GLASS (Java).
• Monitor ROMs — the original SA-1510 (MZ-80A) and 1Z-013A (MZ-700) monitor images, plus 80-column and hi-load variants, assembled with GLASS.
• CP/M 2.2 — a 64K build supported by a custom CBIOS that uses the tranZPUter's extra RAM and SD storage (a 512K CP/M v3 port is planned).

Startup runs the host monitor, which calls the TZFS entry point; TZFS then pages in the tranZPUter RAM and brings up the SD drive. Soft-CPU and CP/M memory modes are documented in the Technical Guide.

---

Programming the board / first boot

1. Program the CPLD (build/output/*.pof) via JTAG with a USB-Blaster — persistent (EEPROM), one time per bitstream.
2. Program the FPGA — either JTAG-load the .sof (volatile, lost on power cycle) or write the .jic to the EPCS boot flash via the SFL megafunction (non-volatile — the FPGA reconfigures itself at every power-on). Non-volatile is recommended for permanent installation.
3. Flash the K64F (zOS_xxx.bin) — the K64F presents as a USB mass-storage device (FRDM-K64F bootloader); drag-and-drop the binary and wait for the LED to finish flashing.
4. Insert a FAT32 SD card populated with the pre-built TZFS/CP/M images.
5. Power on. The machine boots to its monitor; the prompt shows + TZFS vX.xx when TZFS has initialised and the SD card is available. Type H for the TZFS command help screen.

Full step-by-step instructions are in the User Manual.

---

Repository layout

Path	Contents
setup_tranZPUter.sh	Linux / macOS automated setup + build script.
setup_tranZPUter_windows.cmd / setup_tranZPUter_windows_native.ps1	Windows setup launcher and native PowerShell script.
build.sh	Top-level build driver (CPLD + FPGA + software; native or Docker).
docker/QuartusPrime/	Dockerfiles for the three Quartus images (Dockerfile.13.0.1, Dockerfile.13.1, Dockerfile.17.1).
CPLD/	CPLD (MAX 7000A) VHDL and Quartus projects — SW700/, plus Fusion/, FusionX/, mz80b/, EPM7160/.
FPGA/SW700/	FPGA VHDL and Quartus projects for v1.2/ and v1.3/.
software/TZFS	TZFS monitor / filing system (submodule).
software/zSoft	zSoft / zOS K64F firmware (submodule).
zpu/	ZPU Evolution soft CPU (submodule).
cpu/	Soft-CPU cores (T80, etc.).
schematics/, pcb/	Board schematics and PCB artwork (v1.2 & v1.3).
SD/	Pre-built SD-card content (TZFS / CP/M).
datasheets/, docs/, devices/	Component datasheets and reference documentation.
build/output/	Collected build artifacts (.pof, .sof, .jic, ROM/TZFS/CP/M images).
TRANZPUTER_SW_700_README.md, TRANZPUTER_SW_README.md	Comprehensive design documents.

Submodules

The setup scripts clone with --recurse-submodules and initialise them for you. For a manual clone:

git clone --recurse-submodules https://git.eaw.app/eaw/tranZPUter.git
# or, in an existing checkout:
git submodule update --init --recursive

Submodule	Path	URL
TZFS	software/TZFS	https://git.eaw.app/eaw/TZFS.git
zSoft (zOS)	software/zSoft	https://git.eaw.app/eaw/zSoft.git
ZPU	zpu	https://git.eaw.app/eaw/ZPU.git

---

Credits

Where any component is based on or derived from a third-party design, the original author's copyright notice is included in the relevant source file. All third-party software is, to the best of knowledge and research, open source and freely usable; if any component is found to carry licensing restrictions it will be removed and a suitable link/config provided instead.

Licenses

This design, hardware and software, is licensed under the GNU General Public License v3.

No commercial use is to be made of this design or any hardware/firmware component without express permission from the author. This condition overrides any rights afforded by the GNU GPL v3 licence.

The source and binary files in this project marked as GPL v3 are free software: you can redistribute them and/or modify them under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

The source files are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.