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Updates for MZ-700/800

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This commit is contained in:
Philip Smart
2021-03-26 22:54:57 +00:00
parent f24d635fb9
commit 939eade4a3
19 changed files with 1332 additions and 471 deletions
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9
.gitignore vendored
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@@ -331,4 +331,11 @@ software/CPM/1M44/DSK
software/CPM/1M44/RAW
software/CPM/CPM_MULTICOMP_contents.txt
software/disks
software/CPM
software/DSK
software/MZ800_IOCS.ref
software/asm/new/
software/asm/savit
software/dz80.ini
software/full.asm
software.bak/

132
CPLD/SW/tranZPUterSW.vhd
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@@ -147,7 +147,7 @@ architecture rtl of cpld512 is
signal MODE_CPLD_MB_VIDEOn : std_logic; -- Mainboard video, 0 = enabled, 1 = disabled.
signal MODE_HOST_DEFAULT : std_logic; -- On cold start, the host acts per original specifications until changed by programming.
signal CPU_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPU Configuration register.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD Configuration register.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPLD Configuration register.
signal CPLD_INFO_DATA : std_logic_vector(7 downto 0); -- CPLD status value.
signal VIDEOMODULE_PRESENT : std_logic; -- Automatic flag which is set if the serializer becomes active.
@@ -158,7 +158,7 @@ architecture rtl of cpld512 is
signal CS_SCK_SYSCLKn : std_logic; -- Select for setting the Mainboard clock as the active Z80 clock.
signal CS_SCK_RDn : std_logic; -- Select to read which clock is active.
signal CS_CPU_CFGn : std_logic; -- Select to set the CPU configuration register.
signal CS_CPU_INFOn : std_logic; -- Select to set the CPU information register.
signal CS_CPU_INFOn : std_logic; -- Select to read the CPU information register.
signal CS_CPLD_CFGn : std_logic; -- Select to set the CPLD configuration register.
signal CS_CPLD_INFOn : std_logic; -- Select to read the CPLD information register.
signal CS_VIDEOn : std_logic; -- Primary select of the FPGA video logic, used to enable control signals in the memory management process.
@@ -211,6 +211,7 @@ architecture rtl of cpld512 is
--signal REQ_WAITn : std_logic;
-- Internal control signals.
signal SYSRESETn : std_logic; -- Internal system reset pulse 1 clock period after reset, used to preset registers.
signal Z80_HI_ADDRi : std_logic_vector(23 downto 16); -- Hi address. These are the upper bank bits allowing 512K of address space. They are directly set by the K64F when accessing RAM or FPGA and set by the FPGA according to memory mode.
signal Z80_RA_ADDRi : std_logic_vector(15 downto 12); -- Row address - RAM is subdivided into 4K blocks which can be remapped as needed. This is required for the MZ80B emulation where memory changes location according to mode.
signal CTL_BUSACKni : std_logic; -- Buffered BUSACK signal to the K64F to indicate it has control of the bus.
@@ -279,9 +280,19 @@ architecture rtl of cpld512 is
end function to_std_logic;
begin
-- CPLD Configuration register.
-- Delayed reset process to set defaults on registers as required.
RESET: process( Z80_CLKi, Z80_RESETn ) begin
if Z80_RESETn = '0' then
SYSRESETn <= '0';
-- First rising edge the internal system reset is cancelled.
elsif( rising_edge(Z80_CLKi) ) then
SYSRESETn <= '1';
end if;
end process;
-- CPLD/CPU Configuration register.
--
-- CPU: (NOT YET IMPLEMENTED)
-- CPU: (NOT YET IMPLEMENTED IN THE traznZPUter)
-- Version 1.3-> of the tranZPUter SW-700 provides the ability to instantiate alternative soft CPU's. This register configures the FPGA to enable a soft/hard CPU and the CPLD
-- is reconfigured to allow a CPU operation on the FPGA side rather than the physical hardware side.
--
@@ -296,6 +307,7 @@ begin
-- All other configurations reserved and default to Hard CPU.
-- [7] - R/W - CPU Reset. When active ('1'), hold the CPU in reset, when inactive, commence the reset completion and CPU run.
--
-- CPLD:
-- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used
-- by host software such as RFS.
--
@@ -321,7 +333,7 @@ begin
--*[7] - R/W - Preserve configuration over reset (=1) or set to default on reset (=0).
-- * = SW700 v1.3 only, not used in other CPLD versions.
--
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPU_CFGn, CS_CPLD_CFGn, CPLD_CFG_DATA, CS_CPLD_INFOn, Z80_DATA )
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, SYSRESETn, CS_CPU_CFGn, CS_CPLD_CFGn, CPLD_CFG_DATA, CS_CPLD_INFOn, Z80_DATA )
begin
if(Z80_RESETn = '0') then
@@ -331,16 +343,26 @@ begin
MODE_640x200 <= '1';
MODE_320x200 <= '0';
-- MODE_HOST_DEFAULT <= '0';
if CPLD_CFG_DATA(7) = '0' then
-- On MZ-800 hardware, reset the mode to MZ800 as it may be in MZ700 mode prior to reset.
if CPLD_HOST_HW = MODE_MZ800 then
CPLD_CFG_DATA <= "10001101"; -- Enable Sharp MZ-800 host setting, mainboard video unused, wait state unused.
else
-- Default to MZ-80A
CPLD_CFG_DATA <= "10000011"; -- Default to Sharp MZ80A
end if;
MODE_HOST_DEFAULT <= '1'; -- Host runs as original until features enabled.
-- if CPLD_CFG_DATA(7) = '0' then
-- -- On MZ-800 hardware, reset the mode to MZ800 as it may be in MZ700 mode prior to reset.
-- if CPLD_HOST_HW = MODE_MZ800 then
-- CPLD_CFG_DATA <= "10001101"; -- Enable Sharp MZ-800 host setting, mainboard video unused, wait state unused.
-- else
-- -- Default to MZ-80A
-- CPLD_CFG_DATA <= "10000011"; -- Default to Sharp MZ80A
-- end if;
-- MODE_HOST_DEFAULT <= '1'; -- Host runs as original until features enabled.
-- end if;
elsif SYSRESETn = '0' and CPLD_CFG_DATA(7) = '0' then
-- On MZ-800 hardware, reset the mode to MZ800 as it may be in MZ700 mode prior to reset.
if CPLD_HOST_HW = MODE_MZ800 then
CPLD_CFG_DATA <= "10001101"; -- Enable Sharp MZ-800 host setting, mainboard video unused, wait state unused.
else
-- Default to MZ-80A
CPLD_CFG_DATA <= "10000011"; -- Default to Sharp MZ80A
end if;
MODE_HOST_DEFAULT <= '1'; -- Host runs as original until features enabled.
elsif(rising_edge(Z80_CLKi)) then
@@ -403,7 +425,7 @@ begin
-- Memory mode latch. This latch stores the current memory mode (or Bank Paging Scheme) according to the running software.
--
MEMORYMODE: process( Z80_CLKi, Z80_RESETn, CS_MEM_CFGn, Z80_IORQn, Z80_WRn, Z80_ADDR, Z80_DATA, CPLD_CFG_DATA, MODE_640x200 )
MEMORYMODE: process( Z80_CLKi, Z80_RESETn, SYSRESETn, CS_MEM_CFGn, Z80_IORQn, Z80_WRn, Z80_ADDR, Z80_DATA, CPLD_CFG_DATA, MODE_640x200 )
variable mz700_LOWER_RAM : std_logic;
variable mz700_UPPER_RAM : std_logic;
variable mz700_INHIBIT : std_logic;
@@ -411,15 +433,15 @@ begin
begin
if(Z80_RESETn = '0') then
-- On power up reset, default to original configuration.
if CPLD_CFG_DATA(7) = '0' then
-- Default to MZ-700/MZ-80A
MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_ORIG, MEM_MODE_LATCH'length));
-- MZ-800 mode
--elsif CPLD_HOST_HW = MODE_MZ800 then
-- MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_MZ800, MEM_MODE_LATCH'length));
end if;
-- -- On power up reset, default to original configuration.
-- if CPLD_CFG_DATA(7) = '0' then
-- -- Default to MZ-700/MZ-80A
-- MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_ORIG, MEM_MODE_LATCH'length));
--
-- -- MZ-800 mode
-- --elsif CPLD_HOST_HW = MODE_MZ800 then
-- -- MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_MZ800, MEM_MODE_LATCH'length));
-- end if;
mz700_LOWER_RAM := '0';
mz700_UPPER_RAM := '0';
mz700_INHIBIT := '0';
@@ -457,6 +479,17 @@ begin
MODE_CPLD_LAST := std_logic_vector(to_unsigned(CPLD_HOST_HW, MODE_CPLD_LAST'length));
-- On power up reset, default to original configuration.
elsif SYSRESETn = '0' and CPLD_CFG_DATA(7) = '0' then
-- Default to MZ-700/MZ-80A
MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_ORIG, MEM_MODE_LATCH'length));
-- MZ-800 mode
--elsif CPLD_HOST_HW = MODE_MZ800 then
-- MEM_MODE_LATCH <= std_logic_vector(to_unsigned(TZMM_MZ800, MEM_MODE_LATCH'length));
-- A direct write to the memory latch stores the required memory mode into the latch.
elsif (CS_MEM_CFGn = '0' and Z80_WRn = '0') then
MEM_MODE_LATCH <= Z80_DATA(4 downto 0);
@@ -745,7 +778,16 @@ begin
-- Check for MZ700 Mode memory changes and adjust current memory mode setting.
--
elsif((CPLD_HOST_HW = MODE_MZ700 or CPLD_HOST_HW = MODE_MZ80A) and MODE_CPLD_MZ700 = '1' and Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 3) = "11100") then
-- MZ700 memory mode switch?
-- 0x0000:0x0FFF 0xD000:0xFFFF
-- 0xE0 = DRAM
-- 0xE1 = DRAM
-- 0xE2 = MONITOR
-- 0xE3 = Memory Mapped I/O
-- 0xE4 = MONITOR Memory Mapped I/O
-- 0xE5 = Inhibit
-- 0xE6 = Return to state prior to 0xE5
case Z80_ADDR(2 downto 0) is
-- 0xE0
when "000" =>
@@ -1248,6 +1290,7 @@ begin
-- uses the rom as a wait detection by toggling the ROM lines according to WAIT, the Z80 at 2MHz hasnt enough ooomph to read WAIT and action it.
-- 8 - Monitor ROM (0000:0FFF) on mainboard, Main RAM (1000:CFFF) in tranZPUter bank 0 and video, memory mapped I/O, User/Floppy ROM on mainboard.
-- NB: Main DRAM will not be refreshed so cannot be used to store data in this mode.
-- 9 - Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
-- 10 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
-- 11 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
-- 12 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
@@ -1595,6 +1638,45 @@ begin
RAM_OEni <= '1';
end if;
-- Set 9 - Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
-- This mode is to allow a program running in tranZPUTer RAM Bank 0 - address E000:FFFF, to access host memory and I/O directly.
when TZMM_HOSTACCESS =>
if CS_VIDEOn = '0' then
CS_VIDEO_MEMn <= Z80_MREQn;
DISABLE_BUSn <= '1';
RAM_CSni <= '1';
RAM_WEni <= '1';
RAM_OEni <= '1';
-- 0000:E7FF are on the host.
elsif( ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) <= X"E7FF") and not std_match(Z80_ADDR(15 downto 1), "11110-111111111")) ) then
Z80_HI_ADDRi <= "00000000";
Z80_RA_ADDRi <= Z80_ADDR(15 downto 12);
DISABLE_BUSn <= '1';
CS_VIDEO_MEMn <= '1';
RAM_CSni <= '1';
RAM_OEni <= '1';
RAM_WEni <= '1';
-- Upper tranZPUter RAM bank 0 address E800:FFFF execute on the tranZPUter.
elsif(unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF") then
Z80_HI_ADDRi <= "00000000";
Z80_RA_ADDRi <= Z80_ADDR(15 downto 12);
DISABLE_BUSn <= '0';
CS_VIDEO_MEMn <= '1';
RAM_CSni <= '0';
RAM_OEni <= Z80_RDn;
RAM_WEni <= Z80_WRn;
else
-- No action, defaults set to work directly on mainboard.
DISABLE_BUSn <= '1';
CS_VIDEO_MEMn <= '1';
RAM_CSni <= '1';
RAM_WEni <= '1';
RAM_OEni <= '1';
end if;
-- Set 10 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
when TZMM_MZ700_0 =>
RAM_CSni <= '0';

1
CPLD/SW/tranZPUterSW_pkg.vhd
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@@ -70,6 +70,7 @@ package tranZPUterSW_pkg is
constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
-- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_COMPAT : integer := 08; -- Compatibility monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
constant TZMM_HOSTACCESS : integer := 09; -- Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.

7
CPLD/SW700/v1.3/build/tranZPUterSW700_constraints.sdc
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@@ -289,6 +289,13 @@ set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2
set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -hold -end 1
set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2
set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1
set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2
set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1
#**************************************************************
# Set Maximum Delay

100
CPLD/SW700/v1.3/tranZPUterSW700.vhd
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@@ -180,7 +180,7 @@ architecture rtl of cpld512 is
signal CS_VIDEO_IOn : std_logic; -- Select to read/write video IO registers according to mode.
signal CS_VIDEO_RDn : std_logic; -- Select to read video memory and video IO registers according to mode.
signal CS_VIDEO_WRn : std_logic; -- Select to write video memory and video IO registers according to mode.
signal MEM_MODE_LATCH : std_logic_vector(4 downto 0); -- Register to store the active memory mode.
signal MEM_MODE_LATCH : std_logic_vector(4 downto 0):=(others => '0'); -- Register to store the active memory mode.
signal MEM_MODE_DATA : std_logic_vector(7 downto 0); -- Scratch signal to form an 8 bit read of the memory mode register.
-- SR (LS279) state symbols.
@@ -219,6 +219,7 @@ architecture rtl of cpld512 is
signal VWAITn : std_logic;
-- Internal control signals.
signal SYSRESETn : std_logic; -- Internal system reset pulse 1 clock period after reset, used to preset registers.
signal VZ80_BUSRQn : std_logic; --
signal VZ80_RFSHn : std_logic; --
signal VZ80_HALTn : std_logic; --
@@ -257,6 +258,16 @@ architecture rtl of cpld512 is
end function to_std_logic;
begin
-- Delayed reset process to set defaults on registers as required.
RESET: process( Z80_CLKi, Z80_RESETn ) begin
if Z80_RESETn = '0' then
SYSRESETn <= '0';
-- First rising edge the internal system reset is cancelled.
elsif( rising_edge(Z80_CLKi) ) then
SYSRESETn <= '1';
end if;
end process;
-- CPLD/CPU Configuration registers.
--
-- CPU:
@@ -300,14 +311,14 @@ begin
-- [7] - R/W - Preserve configuration over reset (=1) or set to default on reset (=0).
-- * = SW v2.2 MZ80A only, not used in other CPLD versions.
--
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPU_CFGn, CS_CPLD_CFGn, CPLD_ADDR, CPLD_DATA_IN, CPLD_CFG_DATA, CPU_CFG_DATA )
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, SYSRESETn, CS_CPU_CFGn, CS_CPLD_CFGn, CPLD_ADDR, CPLD_DATA_IN, CPLD_CFG_DATA, CPU_CFG_DATA )
begin
if(Z80_RESETn = '0') then
MODE_CPLD_SWITCH <= '0';
if CPLD_CFG_DATA(7) = '0' or CPU_CFG_DATA(5 downto 0) = "000000" then
CPLD_CFG_DATA <= "10000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
end if;
elsif SYSRESETn = '0' and (CPLD_CFG_DATA(7) = '0' or CPU_CFG_DATA(5 downto 0) = "000000") then
CPLD_CFG_DATA <= "10000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
elsif(rising_edge(Z80_CLKi)) then
@@ -341,7 +352,7 @@ begin
-- Memory mode latch. This latch stores the current memory mode (or Bank Paging Scheme) according to the running software.
--
MEMORYMODE: process( Z80_CLKi, Z80_RESETn, CS_MEM_CFGn, MODE_CPU_SOFT, VZ80_IORQn, VZ80_MREQn, VZ80_M1n, CTL_BUSACKni, CPLD_IORQn, CPLD_WRn, CPLD_ADDR, CPLD_DATA_IN, CPU_CFG_DATA )
MEMORYMODE: process( Z80_CLKi, Z80_RESETn, SYSRESETn, CS_MEM_CFGn, MODE_CPU_SOFT, VZ80_IORQn, VZ80_MREQn, VZ80_M1n, CTL_BUSACKni, CPLD_IORQn, CPLD_WRn, CPLD_ADDR, CPLD_DATA_IN, CPU_CFG_DATA )
variable mz700_LOWER_RAM : std_logic;
variable mz700_UPPER_RAM : std_logic;
variable mz700_INHIBIT : std_logic;
@@ -350,16 +361,15 @@ begin
if(Z80_RESETn = '0') then
-- Initialise memory mode if running on hard cpu, soft cpu remains on current selection.
MEM_MODE_LATCH <= "00000";
-- If a soft CPU is running, force the reset memory mode to TZMM_TZFS - this is to accommodate the Z80 which runs original software. For alternate processors it is still
-- important they can access the 512K RAM in case they boot out of it but there coding should change the memory mode to one more suited for its requirements.
if MODE_CPU_SOFT = '1' then
MEM_MODE_LATCH(1) <= '1';
end if;
mz700_LOWER_RAM := '0';
mz700_UPPER_RAM := '0';
mz700_INHIBIT := '0';
-- If a soft CPU is running, force the reset memory mode to TZMM_TZFS - this is to accommodate the Z80 which runs original software. For alternate processors it is still
-- important they can access the 512K RAM in case they boot out of it but there coding should change the memory mode to one more suited for its requirements.
elsif SYSRESETn = '0' and MODE_CPU_SOFT = '1' then
MEM_MODE_LATCH(1) <= MODE_CPU_SOFT;
-- Special case for soft CPU's wanting to address the entire 16M address space (currently 512 RAM) or the 64K address space of the mainboard.
-- Using the IORQ, HMREQ and M1 signals out of the FPGA when in FPGA video mode (including soft cpu mode) in various non standard combinations we latch the upper address
-- or the fixed mainboard access modes.
@@ -381,8 +391,8 @@ begin
elsif(Z80_CLKi'event and Z80_CLKi = '1') then
-- Check for MZ700 Mode memory changes and adjust current memory mode setting.
if(MODE_CPLD_MZ700 = '1' and CPLD_IORQn = '0' and CPLD_M1n = '1' and CPLD_ADDR(7 downto 3) = "11100") then
if(MEM_MODE_LATCH /= std_logic_vector(to_unsigned(TZMM_ORIG, 5))and MODE_CPLD_MZ700 = '1' and CPLD_IORQn = '0' and CPLD_M1n = '1' and CPLD_ADDR(7 downto 3) = "11100") then
-- MZ700 memory mode switch?
-- 0x0000:0x0FFF 0xD000:0xFFFF
-- 0xE0 = DRAM
@@ -395,57 +405,59 @@ begin
case CPLD_ADDR(2 downto 0) is
-- 0xE0
when "000" =>
mz700_LOWER_RAM := '1';
mz700_LOWER_RAM := '1';
-- 0xE1
when "001" =>
mz700_UPPER_RAM := '1';
mz700_UPPER_RAM := '1';
-- 0xE2
when "010" =>
mz700_LOWER_RAM := '0';
mz700_LOWER_RAM := '0';
-- 0xE3
when "011" =>
mz700_UPPER_RAM := '0';
mz700_UPPER_RAM := '0';
-- 0xE4
when "100" =>
mz700_LOWER_RAM := '0';
mz700_UPPER_RAM := '0';
mz700_LOWER_RAM := '0';
mz700_UPPER_RAM := '0';
-- 0xE5
when "101" =>
mz700_INHIBIT := '1';
mz700_INHIBIT := '1';
-- 0xE6
when "110" =>
mz700_INHIBIT := '0';
mz700_INHIBIT := '0';
-- 0xE7
when "111" =>
end case;
if(mz700_INHIBIT = '0' and mz700_LOWER_RAM = '0' and mz700_UPPER_RAM = '0') then
MEM_MODE_LATCH(4 downto 0) <= "00010";
MEM_MODE_LATCH(4 downto 0) <= std_logic_vector(to_unsigned(TZMM_TZFS, MEM_MODE_LATCH'length));
elsif(mz700_INHIBIT = '0' and mz700_LOWER_RAM = '1' and mz700_UPPER_RAM = '0') then
MEM_MODE_LATCH(4 downto 0) <= "01010";
MEM_MODE_LATCH(4 downto 0) <= std_logic_vector(to_unsigned(TZMM_MZ700_0, MEM_MODE_LATCH'length));
elsif(mz700_INHIBIT = '0' and mz700_LOWER_RAM = '0' and mz700_UPPER_RAM = '1') then
MEM_MODE_LATCH(4 downto 0) <= "01011";
MEM_MODE_LATCH(4 downto 0) <= std_logic_vector(to_unsigned(TZMM_MZ700_1, MEM_MODE_LATCH'length));
elsif(mz700_INHIBIT = '0' and mz700_LOWER_RAM = '1' and mz700_UPPER_RAM = '1') then
MEM_MODE_LATCH(4 downto 0) <= "01100";
MEM_MODE_LATCH(4 downto 0) <= std_logic_vector(to_unsigned(TZMM_MZ700_2, MEM_MODE_LATCH'length));
elsif(mz700_INHIBIT = '1' and mz700_LOWER_RAM = '0') then
MEM_MODE_LATCH(4 downto 0) <= "01101";
MEM_MODE_LATCH(4 downto 0) <= std_logic_vector(to_unsigned(TZMM_MZ700_3, MEM_MODE_LATCH'length));
elsif(mz700_INHIBIT = '1' and mz700_LOWER_RAM = '1') then
MEM_MODE_LATCH(4 downto 0) <= "01110";
MEM_MODE_LATCH(4 downto 0) <= std_logic_vector(to_unsigned(TZMM_MZ700_4, MEM_MODE_LATCH'length));
else
null;
end if;
-- Unknown event!
else
null;
end if;
@@ -622,6 +634,7 @@ begin
-- uses the rom as a wait detection by toggling the ROM lines according to WAIT, the Z80 at 2MHz hasnt enough ooomph to read WAIT and action it.
-- 8 - Monitor ROM (0000:0FFF) on mainboard, Main RAM (1000:CFFF) in tranZPUter bank 0 and video, memory mapped I/O, User/Floppy ROM on mainboard.
-- NB: Main DRAM will not be refreshed so cannot be used to store data in this mode.
-- 9 - Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
-- 10 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
-- 11 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
-- 12 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
@@ -922,6 +935,37 @@ begin
RAM_WEni <= '1';
RAM_OEni <= '1';
end if;
-- Set 9 - Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
-- This mode is to allow a program running in tranZPUTer RAM Bank 0 - address E000:FFFF, to access host memory and I/O directly.
when TZMM_HOSTACCESS =>
RAM_CSni <= '0';
CS_VIDEO_MEMn <= '1';
CPLD_HI_ADDR <= "00000000";
CPLD_RA_ADDR <= CPLD_ADDR(15 downto 12);
if CS_VIDEOn = '0' then
DISABLE_BUSn <= '0';
RAM_WEni <= '1';
RAM_OEni <= '1';
CS_VIDEO_MEMn <= '0'; --CPLD_MREQn;
-- E800:FFFF are on the tranZPUter RAM bank 0.
elsif( (unsigned(CPLD_ADDR(15 downto 0)) >= X"E800" and unsigned(CPLD_ADDR(15 downto 0)) <= X"FFFF" and not std_match(CPLD_ADDR(15 downto 1), "11110-111111111")) ) then
DISABLE_BUSn <= '0';
RAM_OEni <= CPLD_RDn;
if unsigned(CPLD_ADDR(15 downto 0)) = X"E800" then
RAM_WEni <= '1';
else
RAM_WEni <= CPLD_WRn;
end if;
else
-- 0000:E7FF are on the host, so use default.
DISABLE_BUSn <= '1';
RAM_WEni <= '1';
RAM_OEni <= '1';
end if;
-- Set 10 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
when TZMM_MZ700_0 =>

1
CPLD/SW700/v1.3/tranZPUterSW700_pkg.vhd
View File

@@ -73,6 +73,7 @@ package tranZPUterSW700_pkg is
constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
-- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_COMPAT : integer := 08; -- Compatibility monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
constant TZMM_HOSTACCESS : integer := 09; -- Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.

83
software/asm/include/BASIC_Definitions.asm
View File

@@ -230,8 +230,37 @@ CPUINFO EQU 06DH ; Versi
CPLDCFG EQU 06EH ; Version 2.1 CPLD configuration register.
CPLDSTATUS EQU 06EH ; Version 2.1 CPLD status register.
CPLDINFO EQU 06FH ; Version 2.1 CPLD version information register.
GDCRTC EQU 0CFH ; MZ-800 CRTC control register
GDCMD EQU 0CEH ; MZ-800 CRTC Mode register
GDGRF EQU 0CDH ; MZ-800 read format register
GDGWF EQU 0CCH ; MZ-800 write format register
PALSLCTOFF EQU 0D3H ; set the palette slot Off position to be adjusted.
PALSLCTON EQU 0D4H ; set the palette slot On position to be adjusted.
PALSETRED EQU 0D5H ; set the red palette value according to the PALETTE_PARAM_SEL address.
PALSETGREEN EQU 0D6H ; set the green palette value according to the PALETTE_PARAM_SEL address.
PALSETBLUE EQU 0D7H ; set the blue palette value according to the PALETTE_PARAM_SEL address.
MMIO0 EQU 0E0H ; MZ-700/MZ-800 Memory Management Set 0
MMIO1 EQU 0E1H ; MZ-700/MZ-800 Memory Management Set 1
MMIO2 EQU 0E2H ; MZ-700/MZ-800 Memory Management Set 2
MMIO3 EQU 0E3H ; MZ-700/MZ-800 Memory Management Set 3
MMIO4 EQU 0E4H ; MZ-700/MZ-800 Memory Management Set 4
MMIO5 EQU 0E5H ; MZ-700/MZ-800 Memory Management Set 5
MMIO6 EQU 0E6H ; MZ-700/MZ-800 Memory Management Set 6
MMIO7 EQU 0E7H ; MZ-700/MZ-800 Memory Management Set 7
SYSCTRL EQU 0F0H ; System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
VMBORDER EQU 0F3H ; Select VGA Border colour attributes. Bit 2 = Red, 1 = Green, 0 = Blue.
GRAMMODE EQU 0F4H ; MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
VMPALETTE EQU 0F5H ; Select Palette:
; 0xF5 sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
; Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
; GPU:
GPUPARAM EQU 0F6H ; 0xF6 set parameters. Store parameters in a long word to be used by the graphics command processor.
; The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
GPUCMD EQU 0F7H ; 0xF7 set the graphics processor unit commands.
GPUSTATUS EQU 0F7H ; [7;1] - FSM state, [0] - 1 = busy, 0 = idle
; Bits [5:0] - 0 = Reset parameters.
; 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
;
VMCTRL EQU 0F8H ; Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
VMGRMODE EQU 0F9H ; Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
VMREDMASK EQU 0FAH ; Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
@@ -252,6 +281,28 @@ MODE_MZ80B EQU 6 ; Set t
MODE_MZ2000 EQU 7 ; Set to MZ-2000 mode.
MODE_VIDEO_FPGA EQU 8 ; Bit flag (bit 3) to switch CPLD into using the new FPGA video hardware.
;-----------------------------------------------
; FPGA CPU enhancement control bits.
;-----------------------------------------------
CPUMODE_SET_Z80 EQU 000H ; Set the CPU to the hard Z80.
CPUMODE_SET_T80 EQU 001H ; Set the CPU to the soft T80.
CPUMODE_SET_ZPU_EVO EQU 002H ; Set the CPU to the soft ZPU Evolution.
CPUMODE_SET_AAA EQU 004H ; Place holder for a future soft CPU.
CPUMODE_SET_BBB EQU 008H ; Place holder for a future soft CPU.
CPUMODE_SET_CCC EQU 010H ; Place holder for a future soft CPU.
CPUMODE_SET_DDD EQU 020H ; Place holder for a future soft CPU.
CPUMODE_IS_Z80 EQU 000H ; Status value to indicate if the hard Z80 available.
CPUMODE_IS_T80 EQU 001H ; Status value to indicate if the soft T80 available.
CPUMODE_IS_ZPU_EVO EQU 002H ; Status value to indicate if the soft ZPU Evolution available.
CPUMODE_IS_AAA EQU 004H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_IS_BBB EQU 008H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_IS_CCC EQU 010H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_IS_DDD EQU 020H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_RESET_CPU EQU 080H ; Reset the soft CPU. Active high, when high the CPU is held in RESET, when low the CPU runs.
CPUMODE_IS_SOFT_AVAIL EQU 040H ; Marker to indicate if the underlying FPGA can support soft CPU's.
CPUMODE_IS_SOFT_MASK EQU 0C0H ; Mask to filter out the Soft CPU availability flags.
CPUMODE_IS_CPU_MASK EQU 03FH ; Mask to filter out which soft CPU's are available.
;-----------------------------------------------
; Video Module control bits.
;-----------------------------------------------
@@ -260,13 +311,13 @@ MODE_COLOUR EQU 010H ; Enabl
SYSMODE_MZ80A EQU 000H ; System board mode MZ80A, 2MHz CPU/Bus.
SYSMODE_MZ80B EQU 001H ; System board mode MZ80B, 4MHz CPU/Bus.
SYSMODE_MZ700 EQU 002H ; System board mode MZ700, 3.54MHz CPU/Bus.
VMMODE_MZ80A EQU 000H ; Video mode = MZ80A
VMMODE_MZ700 EQU 001H ; Video mode = MZ700
VMMODE_MZ800 EQU 002H ; Video mode = MZ800
VMMODE_MZ80B EQU 003H ; Video mode = MZ80B
VMMODE_MZ80K EQU 004H ; Video mode = MZ80K
VMMODE_MZ80C EQU 005H ; Video mode = MZ80C
VMMODE_MZ1200 EQU 006H ; Video mode = MZ1200
VMMODE_MZ80K EQU 000H ; Video mode = MZ80K
VMMODE_MZ80C EQU 001H ; Video mode = MZ80C
VMMODE_MZ1200 EQU 002H ; Video mode = MZ1200
VMMODE_MZ80A EQU 003H ; Video mode = MZ80A
VMMODE_MZ700 EQU 004H ; Video mode = MZ700
VMMODE_MZ800 EQU 005H ; Video mode = MZ800
VMMODE_MZ80B EQU 006H ; Video mode = MZ80B
VMMODE_MZ2000 EQU 007H ; Video mode = MZ2000
VMMODE_PCGRAM EQU 020H ; Enable PCG RAM.
VMMODE_VGA_OFF EQU 000H ; Set VGA mode off, external monitor is driven by standard internal signals.
@@ -274,12 +325,22 @@ VMMODE_VGA_640x480 EQU 040H ; Set e
VMMODE_VGA_1024x768 EQU 080H ; Set external monitor to VGA 1024x768 @ 60Hz mode.
VMMODE_VGA_800x600 EQU 0C0H ; Set external monitor to VGA 800x600 @ 60Hz mode.
;-----------------------------------------------
; GPU commands.
;-----------------------------------------------
GPUCLEARVRAM EQU 001H ; Clear the VRAM without updating attributes.
GPUCLEARVRAMCA EQU 002H ; Clear the VRAM/ARAM with given attribute byte,
GPUCLEARVRAMP EQU 003H ; Clear the VRAM/ARAM with parameters.
GPUCLEARGRAM EQU 081H ; Clear the entire Framebuffer.
GPUCLEARGRAMP EQU 082H ; Clear the Framebuffer according to parameters.
GPURESET EQU 0FFH ; Reset the GPU, return to idle state.
;-----------------------------------------------
; tranZPUter SW Memory Management modes
;-----------------------------------------------
TZMM_ENIOWAIT EQU 020H ; Memory management IO Wait State enable - insert a wait state when an IO operation to E0-FF is executed.
TZMM_ORIG EQU 000H ; Original Sharp MZ80A mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063).
TZMM_BOOT EQU 001H + TZMM_ENIOWAIT ; Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
TZMM_BOOT EQU 001H ; Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
TZMM_TZFS EQU 002H + TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
TZMM_TZFS2 EQU 003H + TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
TZMM_TZFS3 EQU 004H + TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
@@ -287,11 +348,17 @@ TZMM_TZFS4 EQU 005H + TZMM_ENIOWAIT ; TZFS
TZMM_CPM EQU 006H + TZMM_ENIOWAIT ; CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_CPM2 EQU 007H + TZMM_ENIOWAIT ; CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
; Special case for 0000:003F (interrupt vectors) which resides in block 4, F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_COMPAT EQU 008H + TZMM_ENIOWAIT ; Original mode but with main DRAM in Bank 0 to allow bootstrapping of programs from other machines such as the MZ700.
TZMM_HOSTACCESS EQU 009H + TZMM_ENIOWAIT ; Mode to allow code running in Bank 0, address E800:FFFF to access host memory. Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
TZMM_MZ700_0 EQU 00AH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
TZMM_MZ700_1 EQU 00BH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_2 EQU 00CH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_3 EQU 00DH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_MZ700_4 EQU 00EH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_MZ800 EQU 00FH + TZMM_ENIOWAIT ; MZ800 Mode - Tracks original hardware mode offering MZ700/MZ800 configurations.
TZMM_FPGA EQU 015H + TZMM_ENIOWAIT ; Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked.
TZMM_TZPUM EQU 016H + TZMM_ENIOWAIT ; Everything in on mainboard, no access to tranZPUter memory.
TZMM_TZPU EQU 017H + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
TZMM_TZPU0 EQU 018H + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
TZMM_TZPU1 EQU 019H + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
TZMM_TZPU2 EQU 01AH + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.

71
software/asm/include/CPM_Definitions.asm
View File

@@ -161,6 +161,7 @@ TAB EQU 009H ;TAB AC
CR EQU 00DH
LF EQU 00AH
FF EQU 00CH
CS EQU 0CH ; Clear screen
DELETE EQU 07FH
BACKS EQU 008H
SOH EQU 1 ; For XModem etc.
@@ -265,9 +266,37 @@ CPUINFO EQU 06DH ; Versi
CPLDCFG EQU 06EH ; Version 2.1 CPLD configuration register.
CPLDSTATUS EQU 06EH ; Version 2.1 CPLD status register.
CPLDINFO EQU 06FH ; Version 2.1 CPLD version information register.
GDCRTC EQU 0CFH ; MZ-800 CRTC control register
GDCMD EQU 0CEH ; MZ-800 CRTC Mode register
GDGRF EQU 0CDH ; MZ-800 read format register
GDGWF EQU 0CCH ; MZ-800 write format register
PALSLCTOFF EQU 0D3H ; set the palette slot Off position to be adjusted.
PALSLCTON EQU 0D4H ; set the palette slot On position to be adjusted.
PALSETRED EQU 0D5H ; set the red palette value according to the PALETTE_PARAM_SEL address.
PALSETGREEN EQU 0D6H ; set the green palette value according to the PALETTE_PARAM_SEL address.
PALSETBLUE EQU 0D7H ; set the blue palette value according to the PALETTE_PARAM_SEL address.
MMIO0 EQU 0E0H ; MZ-700/MZ-800 Memory Management Set 0
MMIO1 EQU 0E1H ; MZ-700/MZ-800 Memory Management Set 1
MMIO2 EQU 0E2H ; MZ-700/MZ-800 Memory Management Set 2
MMIO3 EQU 0E3H ; MZ-700/MZ-800 Memory Management Set 3
MMIO4 EQU 0E4H ; MZ-700/MZ-800 Memory Management Set 4
MMIO5 EQU 0E5H ; MZ-700/MZ-800 Memory Management Set 5
MMIO6 EQU 0E6H ; MZ-700/MZ-800 Memory Management Set 6
MMIO7 EQU 0E7H ; MZ-700/MZ-800 Memory Management Set 7
;SYSCTRL EQU 0F0H ; System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
VMBORDER EQU 0F3H ; Select VGA Border colour attributes. Bit 2 = Red, 1 = Green, 0 = Blue.
;GRAMMODE EQU 0F4H ; MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
;VMPALETTE EQU 0F5H ; Select Palette:
; ; 0xF5 sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
; ; Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
; ; GPU:
;GPUPARAM EQU 0F6H ; 0xF6 set parameters. Store parameters in a long word to be used by the graphics command processor.
; ; The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
;GPUCMD EQU 0F7H ; 0xF7 set the graphics processor unit commands.
;GPUSTATUS EQU 0F7H ; [7;1] - FSM state, [0] - 1 = busy, 0 = idle
; ; Bits [5:0] - 0 = Reset parameters.
; ; 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
; ;
VMCTRL EQU 0F8H ; Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
VMGRMODE EQU 0F9H ; Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
VMREDMASK EQU 0FAH ; Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
@@ -288,6 +317,28 @@ MODE_MZ80B EQU 6 ; Set t
MODE_MZ2000 EQU 7 ; Set to MZ-2000 mode.
MODE_VIDEO_FPGA EQU 8 ; Bit flag (bit 3) to switch CPLD into using the new FPGA video hardware.
;-----------------------------------------------
; FPGA CPU enhancement control bits.
;-----------------------------------------------
CPUMODE_SET_Z80 EQU 000H ; Set the CPU to the hard Z80.
CPUMODE_SET_T80 EQU 001H ; Set the CPU to the soft T80.
CPUMODE_SET_ZPU_EVO EQU 002H ; Set the CPU to the soft ZPU Evolution.
CPUMODE_SET_AAA EQU 004H ; Place holder for a future soft CPU.
CPUMODE_SET_BBB EQU 008H ; Place holder for a future soft CPU.
CPUMODE_SET_CCC EQU 010H ; Place holder for a future soft CPU.
CPUMODE_SET_DDD EQU 020H ; Place holder for a future soft CPU.
CPUMODE_IS_Z80 EQU 000H ; Status value to indicate if the hard Z80 available.
CPUMODE_IS_T80 EQU 001H ; Status value to indicate if the soft T80 available.
CPUMODE_IS_ZPU_EVO EQU 002H ; Status value to indicate if the soft ZPU Evolution available.
CPUMODE_IS_AAA EQU 004H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_IS_BBB EQU 008H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_IS_CCC EQU 010H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_IS_DDD EQU 020H ; Place holder to indicate if a future soft CPU is available.
CPUMODE_RESET_CPU EQU 080H ; Reset the soft CPU. Active high, when high the CPU is held in RESET, when low the CPU runs.
CPUMODE_IS_SOFT_AVAIL EQU 040H ; Marker to indicate if the underlying FPGA can support soft CPU's.
CPUMODE_IS_SOFT_MASK EQU 0C0H ; Mask to filter out the Soft CPU availability flags.
CPUMODE_IS_CPU_MASK EQU 03FH ; Mask to filter out which soft CPU's are available.
;-----------------------------------------------
; Video Module control bits.
;-----------------------------------------------
@@ -310,6 +361,16 @@ VMMODE_VGA_640x480 EQU 040H ; Set e
VMMODE_VGA_1024x768 EQU 080H ; Set external monitor to VGA 1024x768 @ 60Hz mode.
VMMODE_VGA_800x600 EQU 0C0H ; Set external monitor to VGA 800x600 @ 60Hz mode.
;-----------------------------------------------
; GPU commands.
;-----------------------------------------------
GPUCLEARVRAM EQU 001H ; Clear the VRAM without updating attributes.
GPUCLEARVRAMCA EQU 002H ; Clear the VRAM/ARAM with given attribute byte,
GPUCLEARVRAMP EQU 003H ; Clear the VRAM/ARAM with parameters.
GPUCLEARGRAM EQU 081H ; Clear the entire Framebuffer.
GPUCLEARGRAMP EQU 082H ; Clear the Framebuffer according to parameters.
GPURESET EQU 0FFH ; Reset the GPU, return to idle state.
;-----------------------------------------------
; tranZPUter SW Memory Management modes
;-----------------------------------------------
@@ -324,11 +385,16 @@ TZMM_CPM EQU 006H ; TZMM_ENIOWAIT ; CPM m
TZMM_CPM2 EQU 007H ; TZMM_ENIOWAIT ; CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
; Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_COMPAT EQU 008H ; TZMM_ENIOWAIT ; Original mode but with main DRAM in Bank 0 to allow bootstrapping of programs from other machines such as the MZ700.
TZMM_HOSTACCESS EQU 009H ; TZMM_ENIOWAIT ; Mode to allow code running in Bank 0, address E800:FFFF to access host memory. Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
TZMM_MZ700_0 EQU 00AH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
TZMM_MZ700_1 EQU 00BH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_2 EQU 00CH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_3 EQU 00DH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_MZ700_4 EQU 00EH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_MZ800 EQU 00FH ; TZMM_ENIOWAIT ; MZ800 Mode - Tracks original hardware mode offering MZ700/MZ800 configurations.
TZMM_FPGA EQU 015H ; TZMM_ENIOWAIT ; Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked.
TZMM_TZPUM EQU 016H ; TZMM_ENIOWAIT ; Everything in on mainboard, no access to tranZPUter memory.
TZMM_TZPU EQU 017H ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
TZMM_TZPU0 EQU 018H ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
TZMM_TZPU1 EQU 019H ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
TZMM_TZPU2 EQU 01AH ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
@@ -389,8 +455,8 @@ TZSVC_CMD_LOADFILE EQU 08H ; Servi
TZSVC_CMD_SAVEFILE EQU 09H ; Service command to save a file directly from tranZPUter memory.
TZSVC_CMD_ERASEFILE EQU 0aH ; Service command to erase a file on the SD card.
TZSVC_CMD_CHANGEDIR EQU 0bH ; Service command to change the active directory on the SD card.
TZSVC_CMD_LOAD40BIOS EQU 20H ; Service command requesting that the 40 column version of the SA1510 BIOS is loaded.
TZSVC_CMD_LOAD80BIOS EQU 21H ; Service command requesting that the 80 column version of the SA1510 BIOS is loaded.
TZSVC_CMD_LOAD40ABIOS EQU 20H ; Service command requesting that the 40 column version of the SA1510 BIOS is loaded.
TZSVC_CMD_LOAD80ABIOS EQU 21H ; Service command requesting that the 80 column version of the SA1510 BIOS is loaded.
TZSVC_CMD_LOAD700BIOS40 EQU 22H ; Service command requesting that the MZ700 1Z-013A 40 column BIOS is loaded.
TZSVC_CMD_LOAD700BIOS80 EQU 23H ; Service command requesting that the MZ700 1Z-013A 80 column patched BIOS is loaded.
TZSVC_CMD_LOAD80BIPL EQU 24H ; Service command requesting the MZ-80B IPL is loaded.
@@ -403,6 +469,7 @@ TZSVC_CMD_CPU_ALTFREQ EQU 41H ; Servi
TZSVC_CMD_CPU_CHGFREQ EQU 42H ; Service command to set the alternate frequency in hertz.
TZSVC_CMD_CPU_SETZ80 EQU 50H ; Service command to switch to the external Z80 hard cpu.
TZSVC_CMD_CPU_SETT80 EQU 51H ; Service command to switch to the internal T80 soft cpu.
TZSVC_CMD_CPU_SETZPUEVO EQU 52H ; Service command to switch to the internal ZPU Evolution soft cpu.
TZSVC_CMD_EXIT EQU 07FH ; Service command to terminate TZFS and restart the machine in original mode.
TZSVC_STATUS_OK EQU 000H ; Flag to indicate the K64F processing completed successfully.
TZSVC_STATUS_REQUEST EQU 0FEH ; Flag to indicate the Z80 has made a request to the K64F.

10
software/asm/include/TZFS_Definitions.asm
View File

@@ -49,6 +49,7 @@ FDCJMP1 EQU 0F3FEH ; ROM p
FDCJMP2 EQU 0F7FEH ; ROM paged vector 2.
FDCJMP3 EQU 0F7FEH ; ROM paged vector 3.
FDCJMP4 EQU 0F7FEH ; ROM paged vector 4.
PRGBOOTJMP EQU 0CF00H ; Location to load bootstrap for original host program.
;-----------------------------------------------
; Common character definitions.
@@ -60,6 +61,7 @@ TAB EQU 009H ;TAB AC
CR EQU 00DH
LF EQU 00AH
FF EQU 00CH
CS EQU 0CH ; Clear screen
DELETE EQU 07FH
BACKS EQU 008H
SOH EQU 1 ; For XModem etc.
@@ -96,6 +98,7 @@ CTRL_Y EQU 019H
CTRL_Z EQU 01AH
ESC EQU 01BH
CTRL_SLASH EQU 01CH
CTRL_LB EQU 01BH
CTRL_RB EQU 01DH
CTRL_CAPPA EQU 01EH
CTRL_UNDSCR EQU 01FH
@@ -110,6 +113,8 @@ INSERT EQU 0F6H
CLRKEY EQU 0F7H
HOMEKEY EQU 0F8H
BREAKKEY EQU 0FBH
GRAPHKEY EQU 0FCH
ALPHAKEY EQU 0FDH
;-------------------------------------------------------
@@ -330,6 +335,7 @@ TZMM_CPM EQU 006H + TZMM_ENIOWAIT ; CPM m
TZMM_CPM2 EQU 007H + TZMM_ENIOWAIT ; CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
; Special case for 0000:003F (interrupt vectors) which resides in block 4, F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_COMPAT EQU 008H + TZMM_ENIOWAIT ; Original mode but with main DRAM in Bank 0 to allow bootstrapping of programs from other machines such as the MZ700.
TZMM_HOSTACCESS EQU 009H + TZMM_ENIOWAIT ; Mode to allow code running in Bank 0, address E800:FFFF to access host memory. Monitor ROM 0000-0FFF and Main DRAM 0x1000-0xD000, video and memory mapped I/O are on the host machine, User/Floppy ROM E800-FFFF are in tranZPUter memory.
TZMM_MZ700_0 EQU 00AH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
TZMM_MZ700_1 EQU 00BH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_2 EQU 00CH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
@@ -382,7 +388,9 @@ ROMBANK1 EQU 1 ; TZFS
ROMBANK2 EQU 2 ; TZFS Bank 2 -
ROMBANK3 EQU 3 ; TZFS Bank 3 -
OBJCD EQU 001h ; MZF contains a binary object.
OBJCD EQU 001H ; MZF contains a binary object.
BTX1CD EQU 002H ; MZF contains a BASIC program.
BTX2CD EQU 005H ; MZF contains a BASIC program.
TZOBJCD0 EQU 0F8H ; MZF contains a TZFS binary object for page 0.
TZOBJCD1 EQU 0F8H
TZOBJCD2 EQU 0F8H

505
software/asm/tzfs.asm
View File

@@ -110,6 +110,8 @@ BANKTOBANK_:JMPTOBNK
?SETT80: CALLBNK SETT80, TZMM_TZFS4
?SETZ80: CALLBNK SETZ80, TZMM_TZFS4
?SETZPUEVO: CALLBNK SETZPUEVO, TZMM_TZFS4
?TIMERTST: CALLBNK TIMERTST, TZMM_TZFS3
?PTESTX: CALLBNK PTESTX, TZMM_TZFS3
?GETMODEL: CALLBNK GETMODEL, TZMM_TZFS3
?PLTST: CALLBNK PLTST, TZMM_TZFS3
;-----------------------------------------
@@ -350,7 +352,7 @@ CMDTABLE: DB 000H | 000H | 000H | 003H
DW ?MCORX
DB 000H | 000H | 000H | 001H
DB 'P' ; Printer test.
DW PTESTX
DW ?PTESTX
DB 000H | 000H | 000H | 001H
DB 'R' ; Memory test.
DW MEMTEST
@@ -383,7 +385,7 @@ CMDTABLE: DB 000H | 000H | 000H | 003H
DW ?SETT80
DB 000H | 000H | 000H | 001H
DB 'T' ; Timer test.
DW TIMERTST
DW ?TIMERTST
DB 000H | 000H | 000H | 007H
DB "VBORDER" ; Set VGA border colour.
DW ?SETVBORDER
@@ -534,11 +536,6 @@ HEXIYX: EX (SP),IY
HEXIYX2: POP AF ; Waste the intermediate caller address
RET
BOOTMB: LD A, TZMM_BOOT
OUT (MMCFG),A
LD HL,(EXADR)
JP (HL)
; Bring in additional resources.
USE_CMPSTRING: EQU 1
USE_SUBSTRING: EQU 0
@@ -638,7 +635,7 @@ SETMODE40_1:OUT (CPLDCFG),A ;
LD A,(SCRNMODE)
RES 0, A
LD (SCRNMODE),A ; Bit 0 = 0 = 40char mode on reset.
;
IN A,(CPLDINFO) ; Check to see if this is an MZ700, if it is not, setup the correct frequency.
AND 007H
CP MODE_MZ80A
@@ -1005,109 +1002,6 @@ SGX: LD A,(SWRK)
; END OF CMT CONTROLLER FUNCTIONALITY
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; START OF PRINTER CMDLINE TOOLS FUNCTIONALITY
;-------------------------------------------------------------------------------
PTESTX: LD A,(DE)
CP '&' ; plotter test
JR NZ,PTST1X
PTST0X: INC DE
LD A,(DE)
CP 'L' ; 40 in 1 line
JR Z,.LPTX
CP 'S' ; 80 in 1 line
JR Z,..LPTX
CP 'C' ; Pen change
JR Z,PENX
CP 'G' ; Graph mode
JR Z,PLOTX
CP 'T' ; Test
JR Z,PTRNX
;
PTST1X: CALL PMSGX
ST1X2: RET
.LPTX: LD DE,LLPT ; 01-09-09-0B-0D
JR PTST1X
..LPTX: LD DE,SLPT ; 01-09-09-09-0D
JR PTST1X
PTRNX: LD A,004h ; Test pattern
JR LE999
PLOTX: LD A,002h ; Graph mode
LE999: CALL LPRNTX
JR PTST0X
PENX: LD A,01Dh ; 1 change code (text mode)
JR LE999
;
;
; 1 char print to $LPT
;
; in: ACC print data
;
;
LPRNTX: LD C,000h ; RDAX test
LD B,A ; print data store
CALL RDAX
LD A,B
OUT (0FFh),A ; data out
LD A,080h ; RDP high
OUT (0FEh),A
LD C,001h ; RDA test
CALL RDAX
XOR A ; RDP low
OUT (0FEh),A
RET
;
; $LPT msg.
; in: DE data low address
; 0D msg. end
;
PMSGX: PUSH DE
PUSH BC
PUSH AF
PMSGX1: LD A,(DE) ; ACC = data
CALL LPRNTX
LD A,(DE)
INC DE
CP 00Dh ; end ?
JR NZ,PMSGX1
POP AF
POP BC
POP DE
RET
;
; RDA check
;
; BRKEY in to monitor return
; in: C RDA code
;
RDAX: IN A,(0FEh)
AND 00Dh
CP C
RET Z
CALL BRKEY
JR NZ,RDAX
LD SP,ATRB
JR ST1X2
; 40 CHA. IN 1 LINE CODE (DATA)
LLPT: DB 01H ; TEXT MODE
DB 09H
DB 09H
DB 0BH
DB 0DH
; 80 CHA. 1 LINE CODE (DATA)
SLPT: DB 01H ; TEXT MODE
DB 09H
DB 09H
DB 09H
DB 0DH
;-------------------------------------------------------------------------------
; END OF PRINTER CMDLINE TOOLS FUNCTIONALITY
;-------------------------------------------------------------------------------
; The FDC controller uses it's busy/wait signal as a ROM address line input, this
; causes a jump in the code dependent on the signal status. It gets around the 2MHz
; Z80 not being quick enough to process the signal by polling.
@@ -1252,220 +1146,6 @@ L0324: CALL DLY12
; END OF MEMORY TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; START OF TIMER TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
; Test the 8253 Timer, configure it as per the monitor and display the read back values.
TIMERTST: CALL NL
LD DE,MSG_TIMERTST
CALL MSG
CALL NL
LD DE,MSG_TIMERVAL
CALL MSG
LD A,01h
LD DE,8000h
CALL TIMERTST1
NDE: JP NDE
JP ST1X
TIMERTST1: DI
PUSH BC
PUSH DE
PUSH HL
LD (AMPM),A
LD A,0F0H
LD (TIMFG),A
ABCD: LD HL,0A8C0H
XOR A
SBC HL,DE
PUSH HL
INC HL
EX DE,HL
LD HL,CONTF ; Control Register
LD (HL),0B0H ; 10110000 Control Counter 2 10, Write 2 bytes 11, 000 Interrupt on Terminal Count, 0 16 bit binary
LD (HL),074H ; 01110100 Control Counter 1 01, Write 2 bytes 11, 010 Rate Generator, 0 16 bit binary
LD (HL),030H ; 00110100 Control Counter 1 01, Write 2 bytes 11, 010 interrupt on Terminal Count, 0 16 bit binary
LD HL,CONT2 ; Counter 2
LD (HL),E
LD (HL),D
LD HL,CONT1 ; Counter 1
LD (HL),00AH
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD (HL),00CH
LD (HL),0C0H
; LD HL,CONT2 ; Counter 2
; LD C,(HL)
; LD A,(HL)
; CP D
; JP NZ,L0323H
; LD A,C
; CP E
; JP Z,CDEF
;
L0323H: PUSH AF
PUSH BC
PUSH DE
PUSH HL
;
LD HL,CONTF ; Control Register
LD (HL),080H
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
;CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),040H
LD HL,CONT1 ; Counter 1
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
;CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
;CALL DLY1S
;
LD A,0C4h ; Move cursor left.
LD E,0Eh ; 4 times.
L0330: CALL DPCT
DEC E
JR NZ,L0330
;
; LD C,20
;L0324: CALL DLY12
; DEC C
; JR NZ,L0324
;
POP HL
POP DE
POP BC
POP AF
;
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CP D
JP NZ,L0323H
LD A,C
CP E
JP NZ,L0323H
;
;
PUSH AF
PUSH BC
PUSH DE
PUSH HL
CALL NL
CALL NL
CALL NL
LD DE,MSG_TIMERVAL2
CALL MSG
POP HL
POP DE
POP BC
POP AF
;
CDEF: POP DE
LD HL,CONT1
LD (HL),00CH
LD (HL),07BH
INC HL
L0336H: PUSH AF
PUSH BC
PUSH DE
PUSH HL
;
LD HL,CONTF ; Control Register
LD (HL),080H
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),040H
LD HL,CONT1 ; Counter 1
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL DLY1S
;
LD A,0C4h ; Move cursor left.
LD E,0Eh ; 4 times.
L0340: CALL DPCT
DEC E
JR NZ,L0340
;
POP HL
POP DE
POP BC
POP AF
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CP D
JR NZ,L0336H
LD A,C
CP E
JR NZ,L0336H
CALL NL
LD DE,MSG_TIMERVAL3
CALL MSG
POP HL
POP DE
POP BC
EI
RET
;-------------------------------------------------------------------------------
; END OF TIMER TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
; Method to print out an SDC directory entry name along with an incremental file number. The file number can be
@@ -1473,10 +1153,12 @@ L0340: CALL DPCT
;
; Input: HL = Address of filename.
; D = File number.
; A = File type.
;
PRTDIR: PUSH BC
PUSH DE
PUSH HL
LD C,A ; Preserve the file type.
;
LD A,(SCRNMODE)
BIT 0, A
@@ -1501,12 +1183,24 @@ PRTNOWAIT: LD A,E
;
LD A, D ; Print out file number and increment.
CALL PRTHX
LD A, '.'
CALL PRNT
LD A,C
CP OBJCD
LD A, '.' ; File type is MACHINE CODE program.
JR Z,PRTDIR0A
LD A,C
CP BTX1CD
LD A,'-' ; File type is BASIC.
JR Z,PRTDIR0A
LD A,C
CP BTX2CD
LD A,'_' ; File type is BASIC.
JR Z,PRTDIR0A
LD A,'+'
PRTDIR0A: CALL PRNT
POP DE
PUSH DE ; Get pointer to the file name and print.
CALL ?PRTFN ; Print out the filename.
CALL ?PRTFN ; Print out the filename.
;
LD HL, (DSPXY)
;
@@ -1707,8 +1401,8 @@ LOADSD2A: CALL ?GETMODEL ; Get m
LD (TMPCNT),A
CP 008H ; Original mainboard memory is target?
LD A,000H ; tranZPUter.
JR NZ,LOADSD2B
INC A ; Mainboard.
JR C,LOADSD2B ; MZ-80K .. MZ-2000 modes on tranZPUter.
INC A ; Mainboard mode.
LOADSD2B: LD (TZSVC_MEM_TARGET), A
POP HL
LD A,(TZSVC_FILE_NO) ; Test to see if a file number was found, if one wasnt then a filename was given, so copy.
@@ -1740,70 +1434,149 @@ LOADSD4A: LD DE,MSGNOTFND
LOADSD14: LD A,(SDAUTOEXEC) ; Autoexecute turned off?
CP 0FFh
JP Z,LOADSD15 ; Go back to monitor if it has been, else execute.
LD A,(ATRB)
JP Z,LOADSD15 ; Go back to monitor if it has been turned off, else execute.
;
LD A,(TZSVCSECTOR+TZFS_ATRB) ; Fetch the CMT data from the service sector.
LD HL,(TZSVCSECTOR+TZFS_EXADR) ; Save the execution address as it may not be in scope later on.
LD DE,(TZSVCSECTOR+TZFS_DTADR) ; Save the data address, used to check if it was a low memory load.
;
CP OBJCD ; Standard binary file?
JR Z,LOADSD14A
CP TZOBJCD0 ; TZFS binary file for a particular bank?
JR C,LOADSD17
LOADSD14A: IN A,(CPLDINFO) ; Check hardware, if not MZ800 skip memory reconfig.
LOADSD14A: LD A,(TZSVC_MEM_TARGET) ; Are we loading/executing in original host memory?
OR A
JR NZ,ORIPRGBOOT ; Yes, then need special bootstrap.
;
IN A,(CPLDINFO) ; Check hardware, if not MZ700/MZ800 skip memory reconfig.
AND 07H
CP MODE_MZ700
JR Z, LOADSD14B ; 700 mode we just check if the lower bank needs paging in.
CP MODE_MZ800
JR NZ, LOADSD14C
;
LD A,TZMM_MZ800 ; Return to MZ800 memory mode.
OUT (MMCFG),A
OUT (MMIO4),A ; Reset to known state.
IN A,(MMIO1) ; Remove CGROM.
;
LD HL,DTADR ; Load address 0? If so, page out monitor ROM.
XOR A
OR (HL)
INC HL
OR (HL)
JR NZ, LOADSD14B
OUT (MMIO0), A
;
LOADSD14B: LD A,(TMPCNT) ; Get hardware model the loaded program should execute under.
CP MODE_MZ700
JR Z,LOADSD14C
CP MODE_MZ800 ; Only interested in the MZ-800 at the moment, K to 700 models dont need special settings.
; DE = Load Address
LOADSD14B: LD A,010H ; Load address below 1000H? If so, page out monitor ROM.
CP D
JR C,LOADSD14C
JR NZ,LOADSD14C
OUT (MMIO0),A ; Bring in RAM to lower bank.
OUT (MMIO0), A ; Program loaded below 1000H so page in memory.
;
XOR A
LOADSD14C: LD A,(TMPCNT) ; Get hardware model the loaded program should execute under.
CP MODE_MZ800 ; Only interested in the MZ-800 at the moment, K to 700 models dont need special settings.
JR Z,LOADSD14D
JR LOADSD14E
;
LOADSD14D: XOR A
OUT (GDCMD),A ; Set MZ 800 mode
CALL ?PLTST ; Set the palette.
;
LOADSD14C: LD HL,(EXADR)
LD A,(TZSVC_MEM_TARGET)
OR A
JP NZ,BOOTMB
; HL = Execution address.
LOADSD14E: XOR A
JP (HL) ; Execution address.
LOADSD15: LD DE,MSGCMTDATA ; Indicate where the program was loaded and the execution address.
LD HL,(DTADR)
LD HL,(TZSVCSECTOR+TZFS_DTADR)
PUSH HL
LD HL,(EXADR)
LD HL,(TZSVCSECTOR+TZFS_EXADR)
PUSH HL
LD BC,(SIZE)
LD BC,(TZSVCSECTOR+TZFS_SIZE)
LOADSD16: CALL ?PRINTMSG ; Print out the filename.
POP BC
POP BC ; Remove parameters off stack.
LOADSDX: LD A,0 ; Non error exit.
LOADSDX1: LD (RESULT),A
;
LOADSDX2: LD (RESULT),A
RET
;
LOADSD17: LD DE,MSGNOTBIN
CALL ?PRINTMSG ; Print out the filename.
JR LOADSD16
LD A,1
JR LOADSDX2
LOADSDERR: LD DE,MSGSDRERR
LD BC,(TMPCNT)
CALL ?PRINTMSG ; Print out the filename.
LD A,2
JR LOADSDX1
; Code to bootstrap a program residing in the host memory.
; It is assumed, running in TZFS, that the memory map is of TZFS and actions taken accordingly.
ORIPRGBOOT: LD A,(TMPCNT) ; Get requested mode before it goes out of scope and store.
LD C,A
;
LD A,TZMM_HOSTACCESS ; Page in host memory so we can read the execution address and run the program.
OUT (MMCFG),A
EXX ; Execution and load address are stored in HL/DE from the tape header.
LD DE,PRGBOOTJMP ; Move the relocatable code into the safe area, in this case the upper attribute RAM.
LD HL,ORIBOOTREL
LD BC,ORIBOOTRELEND - ORIBOOTREL
LDIR
EXX
JP PRGBOOTJMP
; Relocatable code which operates in a safe area within original host memory. This code then switches memory mode
; and executes the stored code.
ORIBOOTREL: LD SP,PRGBOOTJMP + (ORIBOOTRELEND - ORIBOOTREL) ; Relative as this code block is moved.
;
LD A,TZMM_ORIG ; Switch to original host mode.
OUT (MMCFG),A
OUT (MMIO4),A
; Determine if this program is loaded below 1200h? We cant initialise monitor variables for this case ; as it may corrupt the program.
LD A,D
CP 011H
JR C,ORIBOOT1 ; Some programs load data in the tape header or scratch area so need to work on 1000H or below.
;
PUSH HL ; The loaded program may call or reference monitor api procedures and the monitor scratch area
LD HL,SWPW ; state will be unknown, we therefore need to zero it to ensure correct loaded program execution.
LD B,BUFER - SWPW
XOR A
ORIBOOT0: LD (HL), A
INC HL
DJNZ ORIBOOT0
LD A,004H
LD (TEMPW),A ; Set the sound tempo to default.
;
LD A,24 ; Set the display coordinates to end of screen to not corrupt existing data.
LD (DSPXY+1),A
POP HL
;
ORIBOOT1: IN A,(CPLDINFO) ; Check hardware, if not MZ700/MZ800 skip memory reconfig.
AND 07H
CP MODE_MZ700
JR Z, ORIBOOT3 ; 700 mode we just check if the lower bank needs paging in.
CP MODE_MZ800
JR NZ, ORIBOOT4
;
ORIBOOT2: LD A,C ; Check user requested mode, original or alternative (ie. MZ-700 mode on an MZ-800).
CP 09H
JR Z,ORIBOOT3
;
XOR A ; Set the graphics display gatearray command register to enable 800 mode.
OUT (GDCMD),A
;OUT (MMIO4),A
; Set the MZ-800 palette.
PUSH HL
LD BC,05F0H ; C=port (Pallet Write), B=count
LD HL,PRGBOOTJMP + (ORIPLTDT - ORIBOOTREL) ; Data
OTIR
XOR A
LD BC,06CFH ; Border Black
OUT (C),A ; Send to port.
POP HL
;
ORIBOOT3: LD A,D ; Load address below 1000H? If so, page out monitor ROM.
CP 011H
JR NC, ORIBOOT4
OUT (MMIO0), A ; Page in lower DRAM as the program executes from below 0x1000.
;
ORIBOOT4: JP (HL) ; Execute program.
; Initialization table for Palette
;
ORIPLTDT: DB 0,10H,20H,30H,40H
; Temporary stack.
DS 32
ORISTACK EQU $
;
ORIBOOTRELEND:
; The FDC controller uses it's busy/wait signal as a ROM address line input, this
; causes a jump in the code dependent on the signal status. It gets around the 2MHz

362
software/asm/tzfs_bank3.asm
View File

@@ -72,38 +72,42 @@ SKIPCOM2: LD A,(DE) ; Comma
; 7 = MZ-700
; 8 = MZ-800
; 2 = MZ-2000
; O = Original memory load.
; O = Original memory load, original machine configuration, ie. MZ-800 as an MZ-800..
; o = Original memory load, alternative mode, ie. MZ-700 on MZ-800 host..
; Outputs:
; C = Binary model number 0..7
; Z = Model code valid.
; NZ = Invalid code.
CHECKMODEL: LD C,MODE_MZ80K
CP 'K'
RET Z
CP 'K' ; MZ-80K
RET Z ; 0
INC C
CP 'C'
RET Z
CP 'C' ; MZ-80C
RET Z ; 1
INC C
CP '1'
RET Z
CP '1' ; MZ-1200
RET Z ; 2
INC C
CP 'A'
RET Z
CP 'A' ; MZ-80A
RET Z ; 3
INC C
CP '7'
RET Z
CP '7' ; MZ-700
RET Z ; 4
INC C
CP '8'
RET Z
CP '8' ; MZ-800
RET Z ; 5
INC C
CP 'B'
RET Z
CP 'B' ; MZ-80B
RET Z ; 6
INC C
CP '2'
RET Z
CP '2' ; MZ-2000
RET Z ; 7
INC C
CP 'O'
RET
CP 'O' ; Original host, ie. MZ-800 as an MZ-800
RET Z ; 8
INC C
CP 'S' ; Original host, alternative mode, ie. MZ-700 mode on MZ-800 host.
RET ; 9?
; Get optional machine model code. Format is: CMD<param>[,][machine model code]
; Outputs:
@@ -116,7 +120,7 @@ GETMODEL: CALL SKIPCOMMA
JR NZ,READMODEL
RET
READMODEL: IN A,(CPLDINFO) ; Get the model number from the underlying hardware.
AND 00FH ; Mask in the relevant bits, A = Model number.
AND 007H ; Mask in the relevant bits, A = Model number.
RET
;
@@ -310,6 +314,324 @@ CLEAR1: LD A,D
; END OF ADDITIONAL TZFS COMMAND METHODS
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; START OF TIMER TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
; Test the 8253 Timer, configure it as per the monitor and display the read back values.
TIMERTST: CALL NL
LD DE,MSG_TIMERTST
CALL MSG
CALL NL
LD DE,MSG_TIMERVAL
CALL MSG
LD A,01h
LD DE,8000h
CALL TIMERTST1
NDE: JP NDE
JP ST1X
TIMERTST1: DI
PUSH BC
PUSH DE
PUSH HL
LD (AMPM),A
LD A,0F0H
LD (TIMFG),A
ABCD: LD HL,0A8C0H
XOR A
SBC HL,DE
PUSH HL
INC HL
EX DE,HL
LD HL,CONTF ; Control Register
LD (HL),0B0H ; 10110000 Control Counter 2 10, Write 2 bytes 11, 000 Interrupt on Terminal Count, 0 16 bit binary
LD (HL),074H ; 01110100 Control Counter 1 01, Write 2 bytes 11, 010 Rate Generator, 0 16 bit binary
LD (HL),030H ; 00110100 Control Counter 1 01, Write 2 bytes 11, 010 interrupt on Terminal Count, 0 16 bit binary
LD HL,CONT2 ; Counter 2
LD (HL),E
LD (HL),D
LD HL,CONT1 ; Counter 1
LD (HL),00AH
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD (HL),00CH
LD (HL),0C0H
; LD HL,CONT2 ; Counter 2
; LD C,(HL)
; LD A,(HL)
; CP D
; JP NZ,L0323H
; LD A,C
; CP E
; JP Z,CDEF
;
L0323H: PUSH AF
PUSH BC
PUSH DE
PUSH HL
;
LD HL,CONTF ; Control Register
LD (HL),080H
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
;CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),040H
LD HL,CONT1 ; Counter 1
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
;CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
;CALL DLY1S
;
LD A,0C4h ; Move cursor left.
LD E,0Eh ; 4 times.
L0330: CALL DPCT
DEC E
JR NZ,L0330
;
; LD C,20
;L0324: CALL DLY12
; DEC C
; JR NZ,L0324
;
POP HL
POP DE
POP BC
POP AF
;
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CP D
JP NZ,L0323H
LD A,C
CP E
JP NZ,L0323H
;
;
PUSH AF
PUSH BC
PUSH DE
PUSH HL
CALL NL
CALL NL
CALL NL
LD DE,MSG_TIMERVAL2
CALL MSG
POP HL
POP DE
POP BC
POP AF
;
CDEF: POP DE
LD HL,CONT1
LD (HL),00CH
LD (HL),07BH
INC HL
L0336H: PUSH AF
PUSH BC
PUSH DE
PUSH HL
;
LD HL,CONTF ; Control Register
LD (HL),080H
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),040H
LD HL,CONT1 ; Counter 1
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL DLY1S
;
LD A,0C4h ; Move cursor left.
LD E,0Eh ; 4 times.
L0340: CALL DPCT
DEC E
JR NZ,L0340
;
POP HL
POP DE
POP BC
POP AF
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CP D
JR NZ,L0336H
LD A,C
CP E
JR NZ,L0336H
CALL NL
LD DE,MSG_TIMERVAL3
CALL MSG
POP HL
POP DE
POP BC
EI
RET
;-------------------------------------------------------------------------------
; END OF TIMER TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; START OF PRINTER CMDLINE TOOLS FUNCTIONALITY
;-------------------------------------------------------------------------------
PTESTX: LD A,(DE)
CP '&' ; plotter test
JR NZ,PTST1X
PTST0X: INC DE
LD A,(DE)
CP 'L' ; 40 in 1 line
JR Z,.LPTX
CP 'S' ; 80 in 1 line
JR Z,..LPTX
CP 'C' ; Pen change
JR Z,PENX
CP 'G' ; Graph mode
JR Z,PLOTX
CP 'T' ; Test
JR Z,PTRNX
;
PTST1X: CALL PMSGX
ST1X2: RET
.LPTX: LD DE,LLPT ; 01-09-09-0B-0D
JR PTST1X
..LPTX: LD DE,SLPT ; 01-09-09-09-0D
JR PTST1X
PTRNX: LD A,004h ; Test pattern
JR LE999
PLOTX: LD A,002h ; Graph mode
LE999: CALL LPRNTX
JR PTST0X
PENX: LD A,01Dh ; 1 change code (text mode)
JR LE999
;
;
; 1 char print to $LPT
;
; in: ACC print data
;
;
LPRNTX: LD C,000h ; RDAX test
LD B,A ; print data store
CALL RDAX
LD A,B
OUT (0FFh),A ; data out
LD A,080h ; RDP high
OUT (0FEh),A
LD C,001h ; RDA test
CALL RDAX
XOR A ; RDP low
OUT (0FEh),A
RET
;
; $LPT msg.
; in: DE data low address
; 0D msg. end
;
PMSGX: PUSH DE
PUSH BC
PUSH AF
PMSGX1: LD A,(DE) ; ACC = data
CALL LPRNTX
LD A,(DE)
INC DE
CP 00Dh ; end ?
JR NZ,PMSGX1
POP AF
POP BC
POP DE
RET
;
; RDA check
;
; BRKEY in to monitor return
; in: C RDA code
;
RDAX: IN A,(0FEh)
AND 00Dh
CP C
RET Z
CALL BRKEY
JR NZ,RDAX
LD SP,ATRB
JR ST1X2
; 40 CHA. IN 1 LINE CODE (DATA)
LLPT: DB 01H ; TEXT MODE
DB 09H
DB 09H
DB 0BH
DB 0DH
; 80 CHA. 1 LINE CODE (DATA)
SLPT: DB 01H ; TEXT MODE
DB 09H
DB 09H
DB 09H
DB 0DH
;-------------------------------------------------------------------------------
; END OF PRINTER CMDLINE TOOLS FUNCTIONALITY
;-------------------------------------------------------------------------------
; The FDC controller uses it's busy/wait signal as a ROM address line input, this
; causes a jump in the code dependent on the signal status. It gets around the 2MHz Z80 not being quick

BIN
software/roms/tzfs.rom
View File

Binary file not shown.

2
software/tools/assemble_cpm.sh
View File

@@ -1,4 +1,4 @@
#!/bin/bash
#!/bin/bash -x
#########################################################################################################
##
## Name: assemble_cpm.sh

2
software/tools/assemble_roms.sh
View File

@@ -35,7 +35,7 @@ JARDIR=${ROOTDIR}/software/tools
ASM=glass-0.5.jar
BUILDROMLIST="MZ800_1Z_013B MZ800_9Z_504M MZ800_IOCS MZ80AFI monitor_SA1510 monitor_80c_SA1510 monitor_1Z-013A monitor_80c_1Z-013A monitor_1Z-013A-KM monitor_80c_1Z-013A-KM MZ80B_IPL"
#BUILDMZFLIST="hi-ramcheck sharpmz-test"
BUILDMZFLIST="BASIC sharpmz-test"
BUILDMZFLIST="5Z009-1B BASIC sharpmz-test"
ASMDIR=${ROOTDIR}/software/asm
ASMTMPDIR=${ROOTDIR}/software/tmp
INCDIR=${ROOTDIR}/software/asm/include

9
software/tools/copytosd.sh
View File

@@ -12,7 +12,7 @@
# OPTIONS
# -D<root path> = Absolute path to root of tranZPUter project dir.
# -M<mediapath> = Path to mounted SD card.
# -t<targethost>= Target host, MZ-80A, MZ-700, MZ-800, MZ-2000
# -t<targethost>= Target host, MZ-80K, MZ-80A, MZ-700, MZ-800, MZ-1500, MZ-2000
# -d = Debug mode.
# -x = Shell trace mode.
# -h = This help screen.
@@ -161,7 +161,7 @@ if [ $# -gt 0 ]; then
case $opt in
d) DEBUGMODE=1;;
D) rootdir=${OPTARG};;
m) media=${OPTARG};;
M) media=${OPTARG};;
t) target=${OPTARG};;
x) set -x; TRACEMODE=1;;
h) Usage;;
@@ -176,7 +176,7 @@ if [ ! -d "${rootdir}/${softwaredir}" ]; then
Fatal "-D < root path > is invalid, this should be the directory where the tranZPUter project directory is located."
fi
if [ ! -d "${rootdir}/${softwaredir}/MZF/${target}" ]; then
Fatal "-t < target host> is invalid, this should be one of: MZ-80A, MZ-700, MZ-800, MZ-2000"
Fatal "-t < target host> is invalid, this should be one of: MZ-80K, MZ-80A, MZ-700, MZ-800, MZ-1500, MZ-2000"
fi
if [ ! -d "${media}" ]; then
Fatal "-m < root path > is invalid, this should be the directory where the tranZPUter project directory is located."
@@ -209,7 +209,8 @@ cp ${rootdir}/${softwaredir}/roms/MZ800_* $media/TZFS/;
cp ${rootdir}/${softwaredir}/roms/cpm22.bin $media/CPM/;
cp ${rootdir}/${softwaredir}/CPM/SDC16M/RAW/* $media/CPM/;
cp ${rootdir}/${softwaredir}/MZF/Common/* $media/MZF/;
cp ${rootdir}/${softwaredir}/MZF/MZ-800/* $media/MZF/;
cp ${rootdir}/${softwaredir}/MZF/${target}/* $media/MZF/;
cp ${rootdir}/${softwaredir}/MZF/MZ-80K/* $media/MZF/;
cp ${rootdir}/${softwaredir}/BAS/* $media/BAS/;
cp ${rootdir}/${softwaredir}/CAS/* $media/CAS/

BIN
software/tools/dz80
View File

Binary file not shown.

2
software/tools/make_cpmdisks.sh
View File

@@ -34,7 +34,7 @@
# These two variables configure which CPM images and disks to build. If only 1 CPM_RFS ROM Drive is needed,
# remove it fro the lists.
BUILDCPMLIST="cpm22"
#BUILDCPMLIST="cpm22"
#SOURCEDIRS="CPM_RFS_[1] CPM[0-9][0-9]_* CPM_MC_5 CPM_MC_C? CPM_MC_D? CPM_MC_E? CPM_MC_F? CPM[0-9][0-9]_MZ800*"
SOURCEDIRS="CPM_RFS_[1-2] CPM[0-9][0-9]_* CPM_MC_5 CPM_MC_C? CPM_MC_D? CPM_MC_E? CPM_MC_F? CPM[0-9][0-9]_MZ800*"

507
software/tools/mzftool.pl
View File

@@ -10,9 +10,12 @@
## Also useful to add headers to homegrow machine code programs.
##
## Credits:
## Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
## Copyright: (c) 2018-2021 Philip Smart <philip.smart@net2net.org>
##
## History: August 2018 - Initial script written.
## March 2021 - Updated to fix MZF header files. Some programs have encoded ASCII
## into the header along with other strange characters, these need to
## be in Sharp ASCII format.
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
@@ -32,8 +35,8 @@
# Title and Versioning.
#
$TITLE = "MZF Tool";
$VERSION = "0.1";
$VERSIONDATE = "25.09.2018";
$VERSION = "0.2";
$VERSIONDATE = "23.03.2021";
# Global Modules.
#
@@ -82,6 +85,407 @@ $errorMailSubject = "MZF Tool Errors...";
$PERL = "perl";
$PERLFLAGS = "";
# ASCII to Sharp Display Code mapping table.
@ASCIIToSharpCode = (
0xCC, # NUL '\0' (null character)
0xE0, # SOH (start of heading)
0xF2, # STX (start of text)
0xF3, # ETX (end of text)
0xCE, # EOT (end of transmission)
0xCF, # ENQ (enquiry)
0xF6, # ACK (acknowledge)
0xF7, # BEL '\a' (bell)
0xF8, # BS '\b' (backspace)
0xF9, # HT '\t' (horizontal tab)
0xFA, # LF '\n' (new line)
0xFB, # VT '\v' (vertical tab)
0xFC, # FF '\f' (form feed)
0xFD, # CR '\r' (carriage ret)
0xFE, # SO (shift out)
0xFF, # SI (shift in)
0xE1, # DLE (data link escape)
0xC1, # DC1 (device control 1)
0xC2, # DC2 (device control 2)
0xC3, # DC3 (device control 3)
0xC4, # DC4 (device control 4)
0xC5, # NAK (negative ack.)
0xC6, # SYN (synchronous idle)
0xE2, # ETB (end of trans. blk)
0xE3, # CAN (cancel)
0xE4, # EM (end of medium)
0xE5, # SUB (substitute)
0xE6, # ESC (escape)
0xEB, # FS (file separator)
0xEE, # GS (group separator)
0xEF, # RS (record separator)
0xF4, # US (unit separator)
0x00, # SPACE
0x61, # !
0x62, # "
0x63, # #
0x64, # $
0x65, # %
0x66, # &
0x67, # '
0x68, # (
0x69, # )
0x6B, # *
0x6A, # +
0x2F, # ,
0x2A, # -
0x2E, # .
0x2D, # /
0x20, # 0
0x21, # 1
0x22, # 2
0x23, # 3
0x24, # 4
0x25, # 5
0x26, # 6
0x27, # 7
0x28, # 8
0x29, # 9
0x4F, # :
0x2C, # ;
0x51, # <
0x2B, # =
0x57, # >
0x49, # ?
0x55, # @
0x01, # A
0x02, # B
0x03, # C
0x04, # D
0x05, # E
0x06, # F
0x07, # G
0x08, # H
0x09, # I
0x0A, # J
0x0B, # K
0x0C, # L
0x0D, # M
0x0E, # N
0x0F, # O
0x10, # P
0x11, # Q
0x12, # R
0x13, # S
0x14, # T
0x15, # U
0x16, # V
0x17, # W
0x18, # X
0x19, # Y
0x1A, # Z
0x52, # [
0x59, # \ '\\'
0x54, # ]
0xBE, # ^
0x3C, # _
0xC7, # `
0x81, # a
0x82, # b
0x83, # c
0x84, # d
0x85, # e
0x86, # f
0x87, # g
0x88, # h
0x89, # i
0x8A, # j
0x8B, # k
0x8C, # l
0x8D, # m
0x8E, # n
0x8F, # o
0x90, # p
0x91, # q
0x92, # r
0x93, # s
0x94, # t
0x95, # u
0x96, # v
0x97, # w
0x98, # x
0x99, # y
0x9A, # z
0xBC, # {
0x80, # |
0x40, # }
0xA5, # ~
0xC0 # DEL
);
# Sharp Display Code to ASCII mapping tables.
#
@SharpCodeToASCII = (
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0x0F
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0x1F
0x20,
0x21,
0x22,
0x23,
0x24,
0x25,
0x26,
0x27,
0x28,
0x29,
0x2A,
0x2B,
0x2C,
0x2D,
0x2E,
0x2F, # 0x2F
0x30,
0x31,
0x32,
0x33,
0x34,
0x35,
0x36,
0x37,
0x38,
0x39,
0x3A,
0x3B,
0x3C,
0x3D,
0x3E,
0x3F, # 0x3F
0x40,
0x41,
0x42,
0x43,
0x44,
0x45,
0x46,
0x47,
0x48,
0x49,
0x4A,
0x4B,
0x4C,
0x4D,
0x4E,
0x4F, # 0x4F
0x50,
0x51,
0x52,
0x53,
0x54,
0x55,
0x56,
0x57,
0x58,
0x59,
0x5A,
0x5B,
0x5C,
0x5D,
0x5E,
0x5F, # 0x5F
0x20, # 0x60
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0x6F
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0x7F
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0x8F
0x20,
0x20,
0x65,
0x20,
0x20,
0x20,
0x74,
0x67,
0x68,
0x20,
0x62,
0x78,
0x64,
0x72,
0x70,
0x63, # 0x9F
0x71,
0x61,
0x7A,
0x77,
0x73,
0x75,
0x69,
0x20,
0x4F, # O with umlaut
0x6B,
0x66,
0x76,
0x20,
0x75, # u with umlaut
0x42, # Strasse S
0x6A, # 0XAF
0x6E,
0x20,
0x55, # U with umlaut
0x6D,
0x20,
0x20,
0x20,
0x6F,
0x6C,
0x41, # A with umlaut
0x6F, # o with umlaut
0x61, # a with umlaut
0x20,
0x79,
0x20,
0x20, # 0xBF
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0XCF
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0XDF
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20, # 0XEF
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20 # 0XFF
);
##################################################################################
# GENERIC SUB-ROUTINES
@@ -428,10 +832,10 @@ sub argOptions
print STDOUT "Usage: $PROGNAME <commands> [<options>] \n";
print STDOUT " commands= --help |\n";
print STDOUT " --verbose |\n";
print STDOUT " --command=<IDENT|ADDHEADER|DELHEADER> |\n";
print STDOUT " --mzffile=<file> {IDENT|ADDHEADER|DELHEADER} |\n";
print STDOUT " --command=<IDENT|ADDHEADER|DELHEADER|FIXHEADER> |\n";
print STDOUT " --mzffile=<file> {IDENT|ADDHEADER|DELHEADER|FIXHEADER}|\n";
print STDOUT " --srcfile=<file> {ADDHEADER} |\n";
print STDOUT " --dstfile=<file> {DELHEADER} |\n";
print STDOUT " --dstfile=<file> {DELHEADER|FIXHEADER} |\n";
print STDOUT " --filename=<name of tape file> (ADDHEADER} |\n";
print STDOUT " --loadaddr=<addr tape should load @> (ADDHEADER} |\n";
print STDOUT " --execaddr=<auto exec addr> (ADDHEADER} |\n";
@@ -447,6 +851,22 @@ sub argOptions
exit( $exitCode );
}
# Method to map an ASCII standard character, as a value, into a Sharp ASCII value.
#
sub getSharpASCIICode
{
local($matchChar) = @_;
$matchcnt = 0;
foreach (@SharpCodeToASCII)
{
if($matchChar eq $_)
{
return($matchcnt);
}
$matchcnt = $matchcnt + 1;
}
return(0xF0);
}
##################################################################################
# END OF GENERIC SUB-ROUTINES
@@ -487,7 +907,7 @@ $comment = "";
GetOptions( "debug=n" => \$debugMode, # Debug Mode?
"verbose" => \$verbose, # Show details?
"mzffile=s" => \$mzfFile, # MZF file.
"dstfile=s" => \$dstFile, # Destination file (for header removal).
"dstfile=s" => \$dstFile, # Destination file (for header removal or MZF file with updated header).
"srcfile=s" => \$srcFile, # Source file (for header adding).
"filename=s" => \$fileName, # Filename to insert into header.
"loadaddr=s" => \$s_loadAddr, # Tape load address.
@@ -522,7 +942,7 @@ if($s_tapeType ne "")
# Verify command.
#
if($command eq "IDENT" || $command eq "ADDHEADER" || $command eq "DELHEADER")
if($command eq "IDENT" || $command eq "ADDHEADER" || $command eq "DELHEADER" || $command eq "FIXHEADER")
{
1;
}
@@ -536,10 +956,14 @@ if($command eq "ADDHEADER" && ($fileName eq "" || !defined($loadAddr) || !define
{
argOptions(3, "ADDHEADER command requires the following parameters to be provided: --filename, --loadaddr, --execaddr, --tapetype\n",$ERR_BADARGUMENTS);
}
if($command eq "FIXHEADER" && $dstFile eq "")
{
argOptions(3, "FIXHEADER command requires the following parameter to be provided: --dstfile\n",$ERR_BADARGUMENTS);
}
# For ident or delete header commands, we need to open and read the mzf file.
#
if(($command eq "IDENT" || $command eq "DELHEADER") && defined($mzfFile) && $mzfFile ne "")
if(($command eq "IDENT" || $command eq "DELHEADER" || $command eq "FIXHEADER") && defined($mzfFile) && $mzfFile ne "")
{
# If defined, can we open it?
#
@@ -562,8 +986,10 @@ if(($command eq "IDENT" || $command eq "DELHEADER") && defined($mzfFile) && $mzf
# Once the MZF is in memory, analyse the details and output.
#
$mzf_header = pack('a'x128, @MZF);
($mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr, $mzf_comment) = unpack 'c1 a17 v4 v4 v4 a104', $mzf_header;
$mzf_header = pack('a'x24, @MZF);
($mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr) = unpack 'c1 a17 v4 v4 v4 a104', $mzf_header;
# Comment is unpacked seperately as there appears to be a perl bug where the first char becomes 0 when unpacking in the above list.
$mzf_comment = pack('a'x104, @MZF[24..128]);
$mzf_filename =~ s/\r|\n//g;
# Output detail if requested.
@@ -578,14 +1004,50 @@ if(($command eq "IDENT" || $command eq "DELHEADER") && defined($mzfFile) && $mzf
printf STDOUT "Comment : %s\n", $mzf_comment;
}
# For the DELHEADER command, a destination needs to be provided and opened.
if($command eq "DELHEADER" && defined($dstFile) && $dstFile ne "")
# For the DELHEADER/FIXHEADER command, a destination needs to be provided and opened.
if(($command eq "DELHEADER" || $command eq "FIXHEADER") && defined($dstFile) && $dstFile ne "")
{
if( ! open(DSTFILE, ">".$dstFile) )
{
argOptions(1, "Cannot open the destination file: $dstFile.\n",$ERR_BADFILENAME);
}
}
# For the FIXHEADER, look at the filename and correct if it doesnt use Sharp ASCII.
#
if($command eq "FIXHEADER")
{
# Remove start and trailing space.
$mzf_filename = trim($mzf_filename);
# Go through the string and convert the stored filename to Sharp format.
$new_mzf_filename = "";
for $idx (0..length($mzf_filename)-1)
{
$hdrChar = substr($mzf_filename, $idx, 1);
$mapIdx = ord($hdrChar);
if($hdrChar =~ m/[^a-z]/)
{
$new_mzf_filename = $new_mzf_filename . pack("C1", $mapIdx);
} else
{
$new_mzf_filename = $new_mzf_filename . pack("C1", getSharpASCIICode($mapIdx));
}
}
# Remove start and trailing space.
$new_mzf_filename = trim($new_mzf_filename);
# Pad to length of filename field with NULL bytes.
for $idx (length($new_mzf_filename)..17-1)
{
$new_mzf_filename = $new_mzf_filename . pack("C1", 0x00);
}
# Repack the header with the updated filename.
$new_mzf_header = pack('c1 a17 v v v', $mzf_type, $new_mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr);
$new_mzf_header .= pack('a104', $mzf_comment) ;
}
}
elsif($command eq "ADDHEADER" && defined($mzfFile) && $mzfFile ne "")
{
@@ -660,6 +1122,25 @@ elsif($command eq "DELHEADER")
foreach my $byte (@MZF) { if($cnt++ >= 128) { print DSTFILE $byte; } }
close DSTFILE;
}
elsif($command eq "FIXHEADER")
{
# Can we create the destination file, ie. the file containing the MZF program with a corrected header?
#
if( ! open(DSTFILE, ">".$dstFile) )
{
argOptions(1, "Cannot open the destination file: $dstFile.\n",$ERR_BADFILENAME);
}
# Strip off the old header.
splice(@MZF, 0, 128);
# Now add the new header and source data into the destination file.
print DSTFILE $new_mzf_header;
foreach my $byte (@MZF) { print DSTFILE $byte; }
# All done.
close DSTFILE;
}
# Exit code is the type of MZF file.
exit $mzf_type;

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