584 lines
16 KiB
Verilog
584 lines
16 KiB
Verilog
//----------------------------------------------------------------------------
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// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//----------------------------------------------------------------------------
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Tue Mar 08 06:12:46 2016"
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module reg_file(
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reg_sel_sys_lo,
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reg_sel_gp_lo,
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reg_sel_sys_hi,
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reg_sel_gp_hi,
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reg_sel_ir,
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reg_sel_pc,
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ctl_sw_4u,
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reg_sel_wz,
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reg_sel_sp,
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reg_sel_iy,
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reg_sel_ix,
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reg_sel_hl2,
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reg_sel_hl,
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reg_sel_de2,
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reg_sel_de,
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reg_sel_bc2,
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reg_sel_bc,
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reg_sel_af2,
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reg_sel_af,
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reg_gp_we,
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reg_sys_we_lo,
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reg_sys_we_hi,
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ctl_reg_in_hi,
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ctl_reg_in_lo,
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ctl_reg_out_lo,
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ctl_reg_out_hi,
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clk,
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reg_sw_4d_lo,
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reg_sw_4d_hi,
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db_hi_as,
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db_hi_ds,
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db_lo_as,
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db_lo_ds
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);
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input wire reg_sel_sys_lo;
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input wire reg_sel_gp_lo;
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input wire reg_sel_sys_hi;
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input wire reg_sel_gp_hi;
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input wire reg_sel_ir;
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input wire reg_sel_pc;
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input wire ctl_sw_4u;
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input wire reg_sel_wz;
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input wire reg_sel_sp;
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input wire reg_sel_iy;
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input wire reg_sel_ix;
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input wire reg_sel_hl2;
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input wire reg_sel_hl;
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input wire reg_sel_de2;
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input wire reg_sel_de;
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input wire reg_sel_bc2;
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input wire reg_sel_bc;
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input wire reg_sel_af2;
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input wire reg_sel_af;
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input wire reg_gp_we;
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input wire reg_sys_we_lo;
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input wire reg_sys_we_hi;
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input wire ctl_reg_in_hi;
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input wire ctl_reg_in_lo;
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input wire ctl_reg_out_lo;
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input wire ctl_reg_out_hi;
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input wire clk;
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input wire reg_sw_4d_lo;
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input wire reg_sw_4d_hi;
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inout wire [7:0] db_hi_as;
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inout wire [7:0] db_hi_ds;
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inout wire [7:0] db_lo_as;
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inout wire [7:0] db_lo_ds;
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wire [7:0] gdfx_temp0;
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wire [7:0] gdfx_temp1;
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wire SYNTHESIZED_WIRE_84;
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wire SYNTHESIZED_WIRE_85;
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wire SYNTHESIZED_WIRE_86;
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wire SYNTHESIZED_WIRE_28;
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wire SYNTHESIZED_WIRE_29;
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wire SYNTHESIZED_WIRE_30;
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wire SYNTHESIZED_WIRE_31;
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wire SYNTHESIZED_WIRE_32;
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wire SYNTHESIZED_WIRE_33;
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wire SYNTHESIZED_WIRE_34;
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wire SYNTHESIZED_WIRE_35;
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wire SYNTHESIZED_WIRE_36;
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wire SYNTHESIZED_WIRE_37;
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wire SYNTHESIZED_WIRE_38;
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wire SYNTHESIZED_WIRE_39;
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wire SYNTHESIZED_WIRE_40;
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wire SYNTHESIZED_WIRE_41;
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wire SYNTHESIZED_WIRE_42;
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wire SYNTHESIZED_WIRE_43;
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wire SYNTHESIZED_WIRE_44;
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wire SYNTHESIZED_WIRE_45;
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wire SYNTHESIZED_WIRE_46;
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wire SYNTHESIZED_WIRE_47;
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wire SYNTHESIZED_WIRE_48;
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wire SYNTHESIZED_WIRE_49;
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wire SYNTHESIZED_WIRE_50;
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wire SYNTHESIZED_WIRE_51;
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wire SYNTHESIZED_WIRE_52;
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wire SYNTHESIZED_WIRE_53;
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wire SYNTHESIZED_WIRE_54;
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wire SYNTHESIZED_WIRE_55;
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wire SYNTHESIZED_WIRE_56;
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wire SYNTHESIZED_WIRE_57;
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wire SYNTHESIZED_WIRE_58;
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wire SYNTHESIZED_WIRE_59;
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wire SYNTHESIZED_WIRE_60;
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wire SYNTHESIZED_WIRE_61;
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wire SYNTHESIZED_WIRE_62;
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wire SYNTHESIZED_WIRE_63;
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wire SYNTHESIZED_WIRE_64;
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wire SYNTHESIZED_WIRE_65;
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wire SYNTHESIZED_WIRE_66;
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wire SYNTHESIZED_WIRE_67;
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wire SYNTHESIZED_WIRE_68;
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wire SYNTHESIZED_WIRE_69;
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wire SYNTHESIZED_WIRE_70;
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wire SYNTHESIZED_WIRE_71;
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wire SYNTHESIZED_WIRE_72;
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wire SYNTHESIZED_WIRE_73;
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wire SYNTHESIZED_WIRE_74;
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wire SYNTHESIZED_WIRE_75;
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wire SYNTHESIZED_WIRE_76;
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wire SYNTHESIZED_WIRE_77;
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wire SYNTHESIZED_WIRE_78;
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wire SYNTHESIZED_WIRE_79;
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wire SYNTHESIZED_WIRE_80;
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wire SYNTHESIZED_WIRE_81;
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wire SYNTHESIZED_WIRE_82;
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wire SYNTHESIZED_WIRE_83;
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assign SYNTHESIZED_WIRE_82 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_wz;
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assign SYNTHESIZED_WIRE_80 = reg_sel_wz & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
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assign SYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_sp;
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assign SYNTHESIZED_WIRE_76 = reg_sel_sp & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_84 = ~reg_sys_we_lo;
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assign SYNTHESIZED_WIRE_71 = reg_sel_gp_lo & reg_gp_we & reg_sel_iy;
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assign SYNTHESIZED_WIRE_85 = ~reg_sys_we_hi;
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assign SYNTHESIZED_WIRE_74 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_pc;
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assign SYNTHESIZED_WIRE_67 = reg_sel_gp_lo & reg_gp_we & reg_sel_ix;
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assign SYNTHESIZED_WIRE_55 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl2;
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assign SYNTHESIZED_WIRE_72 = reg_sel_pc & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
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assign SYNTHESIZED_WIRE_59 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl;
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assign SYNTHESIZED_WIRE_47 = reg_sel_gp_lo & reg_gp_we & reg_sel_de2;
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assign SYNTHESIZED_WIRE_51 = reg_sel_gp_lo & reg_gp_we & reg_sel_de;
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assign SYNTHESIZED_WIRE_81 = reg_sel_wz & reg_sys_we_hi & reg_sel_sys_hi;
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assign SYNTHESIZED_WIRE_86 = ~reg_gp_we;
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assign SYNTHESIZED_WIRE_70 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_iy;
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assign SYNTHESIZED_WIRE_68 = reg_sel_iy & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_39 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc2;
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assign SYNTHESIZED_WIRE_43 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc;
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assign SYNTHESIZED_WIRE_31 = reg_sel_gp_lo & reg_gp_we & reg_sel_af2;
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assign SYNTHESIZED_WIRE_77 = reg_sel_sp & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_66 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_ix;
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assign SYNTHESIZED_WIRE_64 = reg_sel_ix & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_35 = reg_sel_gp_lo & reg_gp_we & reg_sel_af;
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assign SYNTHESIZED_WIRE_69 = reg_sel_iy & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_63 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_ir;
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assign SYNTHESIZED_WIRE_65 = reg_sel_ix & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_53 = reg_sel_hl2 & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl2;
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assign SYNTHESIZED_WIRE_52 = reg_sel_hl2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_57 = reg_sel_hl & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_45 = reg_sel_de2 & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_49 = reg_sel_de & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_37 = reg_sel_bc2 & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl;
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assign SYNTHESIZED_WIRE_56 = reg_sel_hl & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_75 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_pc;
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assign SYNTHESIZED_WIRE_41 = reg_sel_bc & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_29 = reg_sel_af2 & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_33 = reg_sel_af & reg_gp_we & reg_sel_gp_hi;
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assign SYNTHESIZED_WIRE_61 = reg_sel_ir & reg_sys_we_hi & reg_sel_sys_hi;
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assign SYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de2;
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assign SYNTHESIZED_WIRE_44 = reg_sel_de2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_73 = reg_sel_pc & reg_sys_we_hi & reg_sel_sys_hi;
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assign SYNTHESIZED_WIRE_83 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_wz;
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assign SYNTHESIZED_WIRE_50 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de;
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assign SYNTHESIZED_WIRE_48 = reg_sel_de & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc2;
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assign SYNTHESIZED_WIRE_36 = reg_sel_bc2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc;
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assign SYNTHESIZED_WIRE_40 = reg_sel_bc & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af2;
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assign SYNTHESIZED_WIRE_28 = reg_sel_af2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_62 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_ir;
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assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af;
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assign SYNTHESIZED_WIRE_32 = reg_sel_af & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
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assign SYNTHESIZED_WIRE_60 = reg_sel_ir & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
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assign SYNTHESIZED_WIRE_79 = reg_sel_gp_lo & reg_gp_we & reg_sel_sp;
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reg_latch b2v_latch_af2_hi(
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.oe(SYNTHESIZED_WIRE_28),
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.we(SYNTHESIZED_WIRE_29),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_af2_lo(
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.oe(SYNTHESIZED_WIRE_30),
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.we(SYNTHESIZED_WIRE_31),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_af_hi(
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.oe(SYNTHESIZED_WIRE_32),
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.we(SYNTHESIZED_WIRE_33),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_af_lo(
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.oe(SYNTHESIZED_WIRE_34),
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.we(SYNTHESIZED_WIRE_35),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_bc2_hi(
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.oe(SYNTHESIZED_WIRE_36),
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.we(SYNTHESIZED_WIRE_37),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_bc2_lo(
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.oe(SYNTHESIZED_WIRE_38),
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.we(SYNTHESIZED_WIRE_39),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_bc_hi(
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.oe(SYNTHESIZED_WIRE_40),
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.we(SYNTHESIZED_WIRE_41),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_bc_lo(
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.oe(SYNTHESIZED_WIRE_42),
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.we(SYNTHESIZED_WIRE_43),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_de2_hi(
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.oe(SYNTHESIZED_WIRE_44),
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.we(SYNTHESIZED_WIRE_45),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_de2_lo(
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.oe(SYNTHESIZED_WIRE_46),
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.we(SYNTHESIZED_WIRE_47),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_de_hi(
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.oe(SYNTHESIZED_WIRE_48),
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.we(SYNTHESIZED_WIRE_49),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_de_lo(
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.oe(SYNTHESIZED_WIRE_50),
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.we(SYNTHESIZED_WIRE_51),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_hl2_hi(
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.oe(SYNTHESIZED_WIRE_52),
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.we(SYNTHESIZED_WIRE_53),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_hl2_lo(
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.oe(SYNTHESIZED_WIRE_54),
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.we(SYNTHESIZED_WIRE_55),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_hl_hi(
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.oe(SYNTHESIZED_WIRE_56),
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.we(SYNTHESIZED_WIRE_57),
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.clk(clk),
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.db(gdfx_temp1)
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);
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reg_latch b2v_latch_hl_lo(
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.oe(SYNTHESIZED_WIRE_58),
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.we(SYNTHESIZED_WIRE_59),
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.clk(clk),
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.db(gdfx_temp0)
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);
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reg_latch b2v_latch_ir_hi(
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.oe(SYNTHESIZED_WIRE_60),
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.we(SYNTHESIZED_WIRE_61),
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.clk(clk),
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.db(db_hi_as)
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);
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reg_latch b2v_latch_ir_lo(
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.oe(SYNTHESIZED_WIRE_62),
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.we(SYNTHESIZED_WIRE_63),
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.clk(clk),
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.db(db_lo_as)
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);
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reg_latch b2v_latch_ix_hi(
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.oe(SYNTHESIZED_WIRE_64),
|
|
.we(SYNTHESIZED_WIRE_65),
|
|
.clk(clk),
|
|
.db(gdfx_temp1)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_ix_lo(
|
|
.oe(SYNTHESIZED_WIRE_66),
|
|
.we(SYNTHESIZED_WIRE_67),
|
|
.clk(clk),
|
|
.db(gdfx_temp0)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_iy_hi(
|
|
.oe(SYNTHESIZED_WIRE_68),
|
|
.we(SYNTHESIZED_WIRE_69),
|
|
.clk(clk),
|
|
.db(gdfx_temp1)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_iy_lo(
|
|
.oe(SYNTHESIZED_WIRE_70),
|
|
.we(SYNTHESIZED_WIRE_71),
|
|
.clk(clk),
|
|
.db(gdfx_temp0)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_pc_hi(
|
|
.oe(SYNTHESIZED_WIRE_72),
|
|
.we(SYNTHESIZED_WIRE_73),
|
|
.clk(clk),
|
|
.db(db_hi_as)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_pc_lo(
|
|
.oe(SYNTHESIZED_WIRE_74),
|
|
.we(SYNTHESIZED_WIRE_75),
|
|
.clk(clk),
|
|
.db(db_lo_as)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_sp_hi(
|
|
.oe(SYNTHESIZED_WIRE_76),
|
|
.we(SYNTHESIZED_WIRE_77),
|
|
.clk(clk),
|
|
.db(gdfx_temp1)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_sp_lo(
|
|
.oe(SYNTHESIZED_WIRE_78),
|
|
.we(SYNTHESIZED_WIRE_79),
|
|
.clk(clk),
|
|
.db(gdfx_temp0)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_wz_hi(
|
|
.oe(SYNTHESIZED_WIRE_80),
|
|
.we(SYNTHESIZED_WIRE_81),
|
|
.clk(clk),
|
|
.db(gdfx_temp1)
|
|
);
|
|
|
|
|
|
reg_latch b2v_latch_wz_lo(
|
|
.oe(SYNTHESIZED_WIRE_82),
|
|
.we(SYNTHESIZED_WIRE_83),
|
|
.clk(clk),
|
|
.db(gdfx_temp0)
|
|
);
|
|
|
|
assign gdfx_temp0[7] = ctl_sw_4u ? db_lo_as[7] : 1'bz;
|
|
assign gdfx_temp0[6] = ctl_sw_4u ? db_lo_as[6] : 1'bz;
|
|
assign gdfx_temp0[5] = ctl_sw_4u ? db_lo_as[5] : 1'bz;
|
|
assign gdfx_temp0[4] = ctl_sw_4u ? db_lo_as[4] : 1'bz;
|
|
assign gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz;
|
|
assign gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz;
|
|
assign gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz;
|
|
assign gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz;
|
|
|
|
assign db_lo_as[7] = reg_sw_4d_lo ? gdfx_temp0[7] : 1'bz;
|
|
assign db_lo_as[6] = reg_sw_4d_lo ? gdfx_temp0[6] : 1'bz;
|
|
assign db_lo_as[5] = reg_sw_4d_lo ? gdfx_temp0[5] : 1'bz;
|
|
assign db_lo_as[4] = reg_sw_4d_lo ? gdfx_temp0[4] : 1'bz;
|
|
assign db_lo_as[3] = reg_sw_4d_lo ? gdfx_temp0[3] : 1'bz;
|
|
assign db_lo_as[2] = reg_sw_4d_lo ? gdfx_temp0[2] : 1'bz;
|
|
assign db_lo_as[1] = reg_sw_4d_lo ? gdfx_temp0[1] : 1'bz;
|
|
assign db_lo_as[0] = reg_sw_4d_lo ? gdfx_temp0[0] : 1'bz;
|
|
|
|
assign gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz;
|
|
assign gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz;
|
|
assign gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz;
|
|
assign gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz;
|
|
assign gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz;
|
|
assign gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz;
|
|
assign gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz;
|
|
assign gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz;
|
|
|
|
assign db_hi_as[7] = reg_sw_4d_hi ? gdfx_temp1[7] : 1'bz;
|
|
assign db_hi_as[6] = reg_sw_4d_hi ? gdfx_temp1[6] : 1'bz;
|
|
assign db_hi_as[5] = reg_sw_4d_hi ? gdfx_temp1[5] : 1'bz;
|
|
assign db_hi_as[4] = reg_sw_4d_hi ? gdfx_temp1[4] : 1'bz;
|
|
assign db_hi_as[3] = reg_sw_4d_hi ? gdfx_temp1[3] : 1'bz;
|
|
assign db_hi_as[2] = reg_sw_4d_hi ? gdfx_temp1[2] : 1'bz;
|
|
assign db_hi_as[1] = reg_sw_4d_hi ? gdfx_temp1[1] : 1'bz;
|
|
assign db_hi_as[0] = reg_sw_4d_hi ? gdfx_temp1[0] : 1'bz;
|
|
|
|
assign db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz;
|
|
assign db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz;
|
|
assign db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz;
|
|
assign db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz;
|
|
assign db_lo_ds[3] = ctl_reg_out_lo ? gdfx_temp0[3] : 1'bz;
|
|
assign db_lo_ds[2] = ctl_reg_out_lo ? gdfx_temp0[2] : 1'bz;
|
|
assign db_lo_ds[1] = ctl_reg_out_lo ? gdfx_temp0[1] : 1'bz;
|
|
assign db_lo_ds[0] = ctl_reg_out_lo ? gdfx_temp0[0] : 1'bz;
|
|
|
|
assign gdfx_temp0[7] = ctl_reg_in_lo ? db_lo_ds[7] : 1'bz;
|
|
assign gdfx_temp0[6] = ctl_reg_in_lo ? db_lo_ds[6] : 1'bz;
|
|
assign gdfx_temp0[5] = ctl_reg_in_lo ? db_lo_ds[5] : 1'bz;
|
|
assign gdfx_temp0[4] = ctl_reg_in_lo ? db_lo_ds[4] : 1'bz;
|
|
assign gdfx_temp0[3] = ctl_reg_in_lo ? db_lo_ds[3] : 1'bz;
|
|
assign gdfx_temp0[2] = ctl_reg_in_lo ? db_lo_ds[2] : 1'bz;
|
|
assign gdfx_temp0[1] = ctl_reg_in_lo ? db_lo_ds[1] : 1'bz;
|
|
assign gdfx_temp0[0] = ctl_reg_in_lo ? db_lo_ds[0] : 1'bz;
|
|
|
|
assign db_hi_ds[7] = ctl_reg_out_hi ? gdfx_temp1[7] : 1'bz;
|
|
assign db_hi_ds[6] = ctl_reg_out_hi ? gdfx_temp1[6] : 1'bz;
|
|
assign db_hi_ds[5] = ctl_reg_out_hi ? gdfx_temp1[5] : 1'bz;
|
|
assign db_hi_ds[4] = ctl_reg_out_hi ? gdfx_temp1[4] : 1'bz;
|
|
assign db_hi_ds[3] = ctl_reg_out_hi ? gdfx_temp1[3] : 1'bz;
|
|
assign db_hi_ds[2] = ctl_reg_out_hi ? gdfx_temp1[2] : 1'bz;
|
|
assign db_hi_ds[1] = ctl_reg_out_hi ? gdfx_temp1[1] : 1'bz;
|
|
assign db_hi_ds[0] = ctl_reg_out_hi ? gdfx_temp1[0] : 1'bz;
|
|
|
|
assign gdfx_temp1[7] = ctl_reg_in_hi ? db_hi_ds[7] : 1'bz;
|
|
assign gdfx_temp1[6] = ctl_reg_in_hi ? db_hi_ds[6] : 1'bz;
|
|
assign gdfx_temp1[5] = ctl_reg_in_hi ? db_hi_ds[5] : 1'bz;
|
|
assign gdfx_temp1[4] = ctl_reg_in_hi ? db_hi_ds[4] : 1'bz;
|
|
assign gdfx_temp1[3] = ctl_reg_in_hi ? db_hi_ds[3] : 1'bz;
|
|
assign gdfx_temp1[2] = ctl_reg_in_hi ? db_hi_ds[2] : 1'bz;
|
|
assign gdfx_temp1[1] = ctl_reg_in_hi ? db_hi_ds[1] : 1'bz;
|
|
assign gdfx_temp1[0] = ctl_reg_in_hi ? db_hi_ds[0] : 1'bz;
|
|
|
|
|
|
endmodule
|