Files
tranZPUter/FPGA/SW700/v1.3/PLL/Video_Clock_II.qip
2021-02-06 11:31:15 +00:00

8 lines
546 B
Plaintext

set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_II.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II.ppf"]