444 lines
7.8 KiB
Verilog
444 lines
7.8 KiB
Verilog
//----------------------------------------------------------------------------
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// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//----------------------------------------------------------------------------
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sun Dec 09 19:14:29 2018"
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module memory_ifc(
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clk,
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nM1_int,
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ctl_mRead,
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ctl_mWrite,
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in_intr,
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nreset,
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fIORead,
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fIOWrite,
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setM1,
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ctl_iorw,
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timings_en,
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iorq_Tw,
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nhold_clk_wait,
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nM1_out,
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nRFSH_out,
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nMREQ_out,
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nRD_out,
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nWR_out,
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nIORQ_out,
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latch_wait,
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wait_m1
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);
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input wire clk;
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input wire nM1_int;
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input wire ctl_mRead;
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input wire ctl_mWrite;
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input wire in_intr;
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input wire nreset;
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input wire fIORead;
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input wire fIOWrite;
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input wire setM1;
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input wire ctl_iorw;
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input wire timings_en;
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input wire iorq_Tw;
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input wire nhold_clk_wait;
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output wire nM1_out;
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output wire nRFSH_out;
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output wire nMREQ_out;
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output wire nRD_out;
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output wire nWR_out;
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output wire nIORQ_out;
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output wire latch_wait;
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output wire wait_m1;
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wire intr_iorq;
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wire ioRead;
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wire iorq;
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wire ioWrite;
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wire m1_mreq;
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wire mrd_mreq;
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wire mwr_mreq;
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reg mwr_wr;
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wire nMEMRQ_int;
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wire nq2;
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reg q1;
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reg q2;
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wire wait_io;
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reg wait_iorq;
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reg wait_iorqinta;
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reg wait_m_ALTERA_SYNTHESIZED1;
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reg wait_mrd;
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reg wait_mwr;
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wire SYNTHESIZED_WIRE_0;
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reg DFFE_m1_ff3;
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wire SYNTHESIZED_WIRE_1;
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reg DFFE_iorq_ff4;
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reg SYNTHESIZED_WIRE_15;
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reg DFFE_mrd_ff3;
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reg DFFE_intr_ff3;
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wire SYNTHESIZED_WIRE_2;
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reg SYNTHESIZED_WIRE_16;
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wire SYNTHESIZED_WIRE_3;
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reg SYNTHESIZED_WIRE_17;
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wire SYNTHESIZED_WIRE_18;
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reg DFFE_iorq_ff1;
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reg DFFE_m1_ff1;
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reg DFFE_mrd_ff1;
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reg DFFE_mwr_ff1;
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reg DFFE_mreq_ff2;
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assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
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assign ioRead = iorq & fIORead;
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assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
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assign m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
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assign iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;
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assign ioWrite = iorq & fIOWrite;
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assign latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
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assign nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
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assign nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
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assign mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
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assign nWR_out = ~(ioWrite | mwr_wr);
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assign mwr_mreq = mwr_wr | wait_mwr;
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assign nIORQ_out = ~(intr_iorq | iorq);
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assign wait_io = wait_iorqinta | wait_iorq;
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assign intr_iorq = DFFE_intr_ff3 | wait_iorqinta;
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assign nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;
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assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);
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assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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wait_iorqinta <= 0;
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end
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else
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begin
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wait_iorqinta <= iorq_Tw;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_intr_ff3 <= 0;
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end
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else
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if (nhold_clk_wait)
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begin
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DFFE_intr_ff3 <= wait_iorqinta;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_iorq_ff1 <= 0;
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end
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else
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if (timings_en)
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begin
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DFFE_iorq_ff1 <= ctl_iorw;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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SYNTHESIZED_WIRE_15 <= 0;
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end
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else
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if (timings_en)
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begin
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SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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wait_iorq <= 0;
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end
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else
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if (timings_en)
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begin
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wait_iorq <= SYNTHESIZED_WIRE_15;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_iorq_ff4 <= 0;
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end
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else
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if (timings_en)
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begin
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DFFE_iorq_ff4 <= wait_iorq;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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SYNTHESIZED_WIRE_16 <= 0;
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end
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else
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if (timings_en)
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begin
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SYNTHESIZED_WIRE_16 <= nM1_int;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_m1_ff1 <= 1;
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end
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else
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if (timings_en)
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begin
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DFFE_m1_ff1 <= setM1;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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wait_m_ALTERA_SYNTHESIZED1 <= 0;
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end
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else
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if (timings_en)
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begin
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wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_m1_ff3 <= 0;
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end
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else
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if (timings_en)
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begin
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DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_mrd_ff1 <= 0;
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end
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else
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if (timings_en)
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begin
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DFFE_mrd_ff1 <= ctl_mRead;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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wait_mrd <= 0;
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end
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else
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if (timings_en)
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begin
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wait_mrd <= DFFE_mrd_ff1;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_mrd_ff3 <= 0;
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end
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else
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if (timings_en)
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begin
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DFFE_mrd_ff3 <= wait_mrd;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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SYNTHESIZED_WIRE_17 <= 0;
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end
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else
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if (timings_en)
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begin
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SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_mreq_ff2 <= 0;
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end
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else
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if (timings_en)
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begin
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DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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DFFE_mwr_ff1 <= 0;
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end
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else
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if (timings_en)
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begin
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DFFE_mwr_ff1 <= ctl_mWrite;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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wait_mwr <= 0;
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end
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else
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if (timings_en)
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begin
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wait_mwr <= DFFE_mwr_ff1;
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end
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end
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always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
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begin
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if (!nreset)
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begin
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mwr_wr <= 0;
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end
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else
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if (timings_en)
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begin
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mwr_wr <= wait_mwr;
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end
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end
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assign SYNTHESIZED_WIRE_18 = ~clk;
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assign nq2 = ~q2;
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assign SYNTHESIZED_WIRE_2 = ~nreset;
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assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2;
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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q1 <= 0;
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end
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else
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if (timings_en)
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begin
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q1 <= SYNTHESIZED_WIRE_16;
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end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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q2 <= 0;
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end
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else
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if (timings_en)
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begin
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q2 <= q1;
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end
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end
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assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
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endmodule
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