eaw/tranZPUter
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Split for v1.2 and v1.3 developments

Browse Source
This commit is contained in:
Philip Smart
2020-12-12 00:20:07 +00:00
parent f9271f3bba
commit 290ae9aadd
128 changed files with 151362 additions and 574 deletions
Download Patch File Download Diff File Expand all files Collapse all files

107
.gitignore vendored
View File

@@ -138,37 +138,80 @@ CPLD/SW/tranZPUterSW.sav2
CPLD/SW/tranZPUterSW.vhd.clk
CPLD/SW/tranZPUterSW.vhd.presweep
CPLD/SW/tranZPUterSW.vhd.sav3
CPLD/SW700/build/db/
CPLD/SW700/build/incremental_db/
CPLD/SW700/build/output_files/
CPLD/SW700/build/simulation/
CPLD/SW700/build/tranZPUterSW_constraints.sdc.clk
CPLD/SW700/tranZPUterSW.sav2
CPLD/SW700/tranZPUterSW.vhd.clk
CPLD/SW700/tranZPUterSW.vhd.presweep
FPGA/SW700/VideoController.vhd.inpro
FPGA/SW700/VideoController.vhd.orig
FPGA/SW700/VideoController_Toplevel.vhd.orig
FPGA/SW700/VideoController_pkg.vhd.orig
FPGA/SW700/build/.qsys_edit/
FPGA/SW700/build/PLLJ_PLLSPE_INFO.txt
FPGA/SW700/build/VideoController.qsf.orig
FPGA/SW700/build/VideoController_constraints.sdc.orig
FPGA/SW700/build/Video_Clock_III.cmp
FPGA/SW700/build/Video_Clock_III.ppf
FPGA/SW700/build/Video_Clock_III.qip
FPGA/SW700/build/Video_Clock_III.vhd
FPGA/SW700/build/Video_Clock_III_inst.vhd
FPGA/SW700/build/abc.qip
FPGA/SW700/build/core
FPGA/SW700/build/db/
FPGA/SW700/build/greybox_tmp/
FPGA/SW700/build/incremental_db/
FPGA/SW700/build/output_files/VideoController700.2
FPGA/SW700/build/output_files/VideoController700.cdf
FPGA/SW700/build/simulation/
FPGA/SW700/devices/
FPGA/SW700/functions.vhd
FPGA/SW700/vidsav
CPLD/SW700/v1.2/build/db/
CPLD/SW700/v1.2/build/incremental_db/
CPLD/SW700/v1.2/build/output_files/
CPLD/SW700/v1.2/build/simulation/
CPLD/SW700/v1.2/build/tranZPUterSW_constraints.sdc.clk
CPLD/SW700/v1.2/tranZPUterSW.sav2
CPLD/SW700/v1.2/tranZPUterSW.vhd.clk
CPLD/SW700/v1.2/tranZPUterSW.vhd.presweep
FPGA/SW700/v1.2/VideoController.vhd.inpro
FPGA/SW700/v1.2/VideoController.vhd.orig
FPGA/SW700/v1.2/VideoController_Toplevel.vhd.orig
FPGA/SW700/v1.2/VideoController_pkg.vhd.orig
FPGA/SW700/v1.2/build/.qsys_edit/
FPGA/SW700/v1.2/build/PLLJ_PLLSPE_INFO.txt
FPGA/SW700/v1.2/build/VideoController.qsf.orig
FPGA/SW700/v1.2/build/VideoController_constraints.sdc.orig
FPGA/SW700/v1.2/build/abc.qip
FPGA/SW700/v1.2/build/core
FPGA/SW700/v1.2/build/db/
FPGA/SW700/v1.2/build/greybox_tmp/
FPGA/SW700/v1.2/build/incremental_db/
FPGA/SW700/v1.2/build/output_files/VideoController700.2
FPGA/SW700/v1.2/build/output_files/VideoController700.cdf
FPGA/SW700/v1.2/build/simulation/
FPGA/SW700/v1.2/devices/
FPGA/SW700/v1.2/functions.vhd
FPGA/SW700/v1.2/vidsav
CPLD/SW700/v1.3/build/db/
CPLD/SW700/v1.3/build/incremental_db/
CPLD/SW700/v1.3/build/output_files/
CPLD/SW700/v1.3/build/simulation/
CPLD/SW700/v1.3/build/tranZPUterSW_constraints.sdc.clk
CPLD/SW700/v1.3/tranZPUterSW.sav2
CPLD/SW700/v1.3/tranZPUterSW.vhd.clk
CPLD/SW700/v1.3/tranZPUterSW.vhd.presweep
FPGA/SW700/v1.3/VideoController.vhd.inpro
FPGA/SW700/v1.3/VideoController.vhd.orig
FPGA/SW700/v1.3/VideoController_Toplevel.vhd.orig
FPGA/SW700/v1.3/VideoController_pkg.vhd.orig
FPGA/SW700/v1.3/build/.qsys_edit/
FPGA/SW700/v1.3/build/PLLJ_PLLSPE_INFO.txt
FPGA/SW700/v1.3/build/VideoController.qsf.orig
FPGA/SW700/v1.3/build/VideoController_constraints.sdc.orig
FPGA/SW700/v1.3/build/abc.qip
FPGA/SW700/v1.3/build/core
FPGA/SW700/v1.3/build/db/
FPGA/SW700/v1.3/build/greybox_tmp/
FPGA/SW700/v1.3/build/incremental_db/
FPGA/SW700/v1.3/build/output_files/VideoController700.2
FPGA/SW700/v1.3/build/output_files/VideoController700.cdf
FPGA/SW700/v1.3/build/simulation/
FPGA/SW700/v1.3/devices/
FPGA/SW700/v1.3/functions.vhd
FPGA/SW700/v1.3/vidsav
tools/Mars4_5.jar
docker/QuartusPrime/Dockerfile.13.0.1.old
docker/QuartusPrime/Quartus-web-13.0.1.232-linux.tar
docker/QuartusPrime/files/13.0/
docker/QuartusPrime/files/13.1/
docker/QuartusPrime/files/17.1/
docker/QuartusPrime/local/
docker/QuartusPrime/quartus_docker.sh
FPGA/SW700/v1.2/build/VideoController700.pti_db_list.ddb
FPGA/SW700/v1.2/build/VideoController700.tis_db_list.ddb
FPGA/SW700/v1.2/build/output_files/greybox_tmp/
FPGA/SW700/v1.2/build/x
FPGA/SW700/v1.3/build/VideoController700.pti_db_list.ddb
FPGA/SW700/v1.3/build/VideoController700.tis_db_list.ddb
FPGA/SW700/v1.3/build/coreMZ.qsf.bak
FPGA/SW700/v1.3/build/x
software/mif/monitor_SA1510.mif.bak
software/mif/monitor_SA1510.mif.tst
FPGA/SW700/v1.2/build/output_files/
FPGA/SW700/v1.3/XX
FPGA/SW700/v1.3/build/output_files/
FPGA/SW700/v1.3/devices.old/

0
CPLD/SW700/build/tranZPUterSW700.qpf → CPLD/SW700/v1.2/build/tranZPUterSW700.qpf
View File

0
CPLD/SW700/build/tranZPUterSW700.qsf → CPLD/SW700/v1.2/build/tranZPUterSW700.qsf
View File

0
CPLD/SW700/build/tranZPUterSW700_constraints.sdc → CPLD/SW700/v1.2/build/tranZPUterSW700_constraints.sdc
View File

0
CPLD/SW700/tranZPUterSW700.vhd → CPLD/SW700/v1.2/tranZPUterSW700.vhd
View File

0
CPLD/SW700/tranZPUterSW700_Toplevel.vhd → CPLD/SW700/v1.2/tranZPUterSW700_Toplevel.vhd
View File

0
CPLD/SW700/tranZPUterSW700_pkg.vhd → CPLD/SW700/v1.2/tranZPUterSW700_pkg.vhd
View File

30
CPLD/SW700/v1.3/build/tranZPUterSW700.qpf Normal file
View File

@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "16:29:32 June 24, 2020"
# Revisions
PROJECT_REVISION = "tranZPUterSW700"

218
CPLD/SW700/v1.3/build/tranZPUterSW700.qsf Normal file
View File

@@ -0,0 +1,218 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# tranZPUterSW700_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000AE
set_global_assignment -name DEVICE "EPM7512AETC144-10"
set_global_assignment -name TOP_LEVEL_ENTITY tranZPUterSW700
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
# Z80 Address Bus
# ===============
set_location_assignment PIN_107 -to Z80_HI_ADDR[18]
set_location_assignment PIN_102 -to Z80_HI_ADDR[17]
set_location_assignment PIN_108 -to Z80_HI_ADDR[16]
set_location_assignment PIN_109 -to Z80_RA_ADDR[15]
set_location_assignment PIN_110 -to Z80_RA_ADDR[14]
set_location_assignment PIN_111 -to Z80_RA_ADDR[13]
set_location_assignment PIN_112 -to Z80_RA_ADDR[12]
set_location_assignment PIN_106 -to Z80_ADDR[15]
set_location_assignment PIN_103 -to Z80_ADDR[14]
set_location_assignment PIN_98 -to Z80_ADDR[13]
set_location_assignment PIN_101 -to Z80_ADDR[12]
set_location_assignment PIN_91 -to Z80_ADDR[11]
set_location_assignment PIN_86 -to Z80_ADDR[10]
set_location_assignment PIN_93 -to Z80_ADDR[9]
set_location_assignment PIN_96 -to Z80_ADDR[8]
set_location_assignment PIN_99 -to Z80_ADDR[7]
set_location_assignment PIN_97 -to Z80_ADDR[6]
set_location_assignment PIN_94 -to Z80_ADDR[5]
set_location_assignment PIN_92 -to Z80_ADDR[4]
set_location_assignment PIN_90 -to Z80_ADDR[3]
set_location_assignment PIN_87 -to Z80_ADDR[2]
set_location_assignment PIN_84 -to Z80_ADDR[1]
set_location_assignment PIN_82 -to Z80_ADDR[0]
# Z80 Data Bus
# ============
set_location_assignment PIN_80 -to Z80_DATA[0]
set_location_assignment PIN_78 -to Z80_DATA[1]
set_location_assignment PIN_75 -to Z80_DATA[2]
set_location_assignment PIN_72 -to Z80_DATA[3]
set_location_assignment PIN_74 -to Z80_DATA[4]
set_location_assignment PIN_77 -to Z80_DATA[5]
set_location_assignment PIN_79 -to Z80_DATA[6]
set_location_assignment PIN_81 -to Z80_DATA[7]
# FPGA extension address and control.
# ===================================
set_location_assignment PIN_122 -to VZ80_ADDR[15]
set_location_assignment PIN_131 -to VZ80_ADDR[14]
set_location_assignment PIN_132 -to VZ80_ADDR[13]
set_location_assignment PIN_133 -to VZ80_ADDR[12]
set_location_assignment PIN_134 -to VZ80_ADDR[11]
set_location_assignment PIN_136 -to VZ80_ADDR[10]
set_location_assignment PIN_137 -to VZ80_ADDR[9]
set_location_assignment PIN_138 -to VZ80_ADDR[8]
set_location_assignment PIN_139 -to VZ80_ADDR[7]
set_location_assignment PIN_140 -to VZ80_ADDR[6]
set_location_assignment PIN_141 -to VZ80_ADDR[5]
set_location_assignment PIN_142 -to VZ80_ADDR[4]
set_location_assignment PIN_143 -to VZ80_ADDR[3]
set_location_assignment PIN_1 -to VZ80_ADDR[2]
set_location_assignment PIN_2 -to VZ80_ADDR[1]
set_location_assignment PIN_5 -to VZ80_ADDR[0]
set_location_assignment PIN_113 -to VZ80_DATA[7]
set_location_assignment PIN_114 -to VZ80_DATA[6]
set_location_assignment PIN_116 -to VZ80_DATA[5]
set_location_assignment PIN_117 -to VZ80_DATA[4]
set_location_assignment PIN_118 -to VZ80_DATA[3]
set_location_assignment PIN_119 -to VZ80_DATA[2]
set_location_assignment PIN_120 -to VZ80_DATA[1]
set_location_assignment PIN_121 -to VZ80_DATA[0]
set_location_assignment PIN_6 -to VIDEO_RDn
set_location_assignment PIN_7 -to VIDEO_WRn
set_location_assignment PIN_8 -to VZ80_IORQn
set_location_assignment PIN_9 -to VZ80_CLK
set_location_assignment PIN_11 -to VZ80_M1n
set_location_assignment PIN_21 -to VZ80_BUSACKn
set_location_assignment PIN_22 -to VZ80_WRn
set_location_assignment PIN_23 -to VZ80_RDn
set_location_assignment PIN_26 -to VZ80_MREQn
#set_location_assignment PIN_25 -to NOT CONNECTED - PIN D1
# FPGA Video and Control signals.
# ===============================
set_location_assignment PIN_10 -to VWAITn_V_CSYNC
set_location_assignment PIN_12 -to VZ80_RFSHn_V_HSYNC
set_location_assignment PIN_14 -to VZ80_HALTn_V_VSYNC
set_location_assignment PIN_15 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_16 -to VZ80_WAITn_V_B
set_location_assignment PIN_18 -to VZ80_INTn_V_R
set_location_assignment PIN_19 -to VZ80_NMIn_V_COLR
# RAM control
# ===========
set_location_assignment PIN_83 -to RAM_CSn
set_location_assignment PIN_88 -to RAM_OEn
set_location_assignment PIN_100 -to RAM_WEn
# K64F Interrupt requests
# =======================
set_location_assignment PIN_60 -to SVCREQn
# K64F control
# ============
set_location_assignment PIN_37 -to CTL_WAITn
set_location_assignment PIN_39 -to CTL_RFSHn
set_location_assignment PIN_65 -to CTL_BUSACKn
set_location_assignment PIN_53 -to CTL_HALTn
set_location_assignment PIN_128 -to CTLCLK
set_location_assignment PIN_47 -to CTL_M1n
set_location_assignment PIN_54 -to CTL_MBSEL
set_location_assignment PIN_55 -to CTL_BUSRQn
set_location_assignment PIN_41 -to Z80_MEM[4]
set_location_assignment PIN_42 -to Z80_MEM[3]
set_location_assignment PIN_43 -to Z80_MEM[2]
set_location_assignment PIN_44 -to Z80_MEM[1]
set_location_assignment PIN_45 -to Z80_MEM[0]
# Z80 Control signals.
# ====================
set_location_assignment PIN_70 -to Z80_MREQn
set_location_assignment PIN_71 -to Z80_IORQn
set_location_assignment PIN_69 -to Z80_RDn
set_location_assignment PIN_67 -to Z80_WRn
set_location_assignment PIN_38 -to Z80_RFSHn
set_location_assignment PIN_40 -to Z80_M1n
set_location_assignment PIN_61 -to Z80_WAITn
set_location_assignment PIN_68 -to Z80_HALTn
set_location_assignment PIN_63 -to Z80_BUSACKn
set_location_assignment PIN_56 -to Z80_BUSRQn
set_location_assignment PIN_62 -to Z80_INTn
set_location_assignment PIN_66 -to Z80_NMIn
set_location_assignment PIN_36 -to Z80_CLK
set_location_assignment PIN_127 -to Z80_RESETn
# Mainboard control signals.
# ==========================
set_location_assignment PIN_125 -to SYSCLK
set_location_assignment PIN_48 -to SYS_WAITn
set_location_assignment PIN_46 -to SYS_BUSRQn
set_location_assignment PIN_49 -to SYS_BUSACKn
# Mainboard Video signals.
# ========================
set_location_assignment PIN_35 -to CSYNC_IN
set_location_assignment PIN_32 -to HSYNC_IN
set_location_assignment PIN_31 -to VSYNC_IN
set_location_assignment PIN_30 -to G_IN
set_location_assignment PIN_29 -to B_IN
set_location_assignment PIN_28 -to R_IN
set_location_assignment PIN_27 -to COLR_IN
set_global_assignment -name VHDL_FILE ../tranZPUterSW700_Toplevel.vhd
set_global_assignment -name VHDL_FILE ../tranZPUterSW700_pkg.vhd
set_global_assignment -name VHDL_FILE ../tranZPUterSW700.vhd
set_global_assignment -name SDC_FILE tranZPUterSW700_constraints.sdc
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF
set_global_assignment -name AUTO_LCELL_INSERTION ON

293
CPLD/SW700/v1.3/build/tranZPUterSW700_constraints.sdc Normal file
View File

@@ -0,0 +1,293 @@
## Generated SDC file "tranZPUterSW700.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
## DATE "Fri Jun 26 22:10:05 2020"
##
## DEVICE "EPM7160STC100-10"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
# Standard mainboard clock. If using tranZPUter on a different host then set to the host frequency.
create_clock -name {SYSCLK} -period 282.486 -waveform { 0.000 141.243 } [get_ports { SYSCLK }]
# For K64F
create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [ get_ports { CTLCLK }]
# For basic board with oscillator.
#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }]
#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ]
##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSELn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HI_ADDR[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_ADDR[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {R_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {G_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {B_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {COLR_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CSYNC_IN}]
#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {HSYNC_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VSYNC_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_DATA[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RFSHn_V_HSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_HALTn_V_VSYNC}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_DATA[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_CLK}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_RDn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_WRn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_INTn_V_R}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSRQn_V_G}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WAITn_V_B}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_NMIn_V_COLR}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RFSHn_V_HSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_HALTn_V_VSYNC}]
# For K64F
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}]
# For basic board with oscillator.
#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}]
#**************************************************************
# Set Max Delay
#**************************************************************
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 30.000
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 30.000
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 30.000
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 30.000
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 30.000
set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 30.000
set_max_delay -from [get_ports {VZ80_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000
set_max_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 30.000
set_max_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 30.000
set_max_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 30.000
set_max_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 30.000
set_max_delay -from [get_ports {VZ80_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 30.000
set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 30.000
set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 30.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000
set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 40.000
#**************************************************************
# Set Max Delay
#**************************************************************
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 1.000
set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 1.000
set_min_delay -from [get_ports {VZ80_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 1.000
set_min_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 1.000
set_min_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 1.000
set_min_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 1.000
set_min_delay -from [get_ports {VZ80_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 1.000
set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 1.000
set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 1.000
set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 1.000
set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 1.000
set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 1.000
set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 1.000
set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000
set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
# For K64F
set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}]
set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
# For basic board with oscillator.
#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}]
#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}]
#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}]
#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
# For both configurations.
#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

1551
CPLD/SW700/v1.3/tranZPUterSW700.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

211
CPLD/SW700/v1.3/tranZPUterSW700_Toplevel.vhd Normal file
View File

@@ -0,0 +1,211 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: tranZPUterSW700_Toplevel.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: tranZPUter SW CPLD Top Level module.
--
-- This module contains the basic pin definition of the CPLD<->logic needed in the project.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Oct 2020 - Cut taken from the tranZPUterSW 2.1 to be used for the tranZPUter SW 700
-- as there are a lot of pin and logic differences. The tranZPUter SW is still
-- under development so didnt make sense to share the same files and make
-- them conditional.
-- Nov 2020 - Version 1.3 board needs major changes as the FPGA is now capable of
-- supporting soft CPU's, an original target of the tranZPUter project.
-- The keyboard mapping has been removed as more complex signal switching is
-- needed and this logic will be placed in the FPGA. The CPLD still remains
-- the central memory management for both hard and soft CPU's.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tranZPUterSW700_pkg.all;
library altera;
use altera.altera_syn_attributes.all;
entity tranZPUterSW700 is
port (
-- Z80 Address and Data.
Z80_HI_ADDR : inout std_logic_vector(18 downto 16); -- Hi address. These are the upper bank bits allowing 512K of address space. They are directly set by the K64F when accessing RAM or FPGA and set by the FPGA according to memory mode.
Z80_RA_ADDR : out std_logic_vector(15 downto 12); -- Row address - RAM is subdivided into 4K blocks which can be remapped as needed. This is required for the MZ80B emulation where memory changes location according to mode.
Z80_ADDR : inout std_logic_vector(15 downto 0);
Z80_DATA : inout std_logic_vector(7 downto 0);
-- Z80 Control signals.
Z80_BUSRQn : out std_logic;
Z80_BUSACKn : in std_logic;
Z80_INTn : in std_logic;
Z80_IORQn : inout std_logic;
Z80_MREQn : inout std_logic;
Z80_NMIn : in std_logic;
Z80_RDn : inout std_logic;
Z80_WRn : inout std_logic;
Z80_RESETn : in std_logic;
Z80_HALTn : inout std_logic;
Z80_WAITn : inout std_logic;
Z80_M1n : inout std_logic;
Z80_RFSHn : inout std_logic;
Z80_CLK : out std_logic;
-- K64F control signals.
CTL_MBSEL : in std_logic; -- Select mainboard, 1 = mainboard, 0 = tranzputer bus.
CTL_BUSRQn : in std_logic;
CTL_BUSACKn : out std_logic; -- Combined BUSACK signal to the K64F
CTL_HALTn : out std_logic;
CTL_M1n : out std_logic;
CTL_RFSHn : out std_logic;
CTL_WAITn : in std_logic;
SVCREQn : out std_logic;
Z80_MEM : out std_logic_vector(4 downto 0);
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
SYS_BUSACKn : out std_logic;
SYS_BUSRQn : in std_logic;
SYS_WAITn : in std_logic;
-- RAM control.
RAM_CSn : out std_logic;
RAM_OEn : out std_logic;
RAM_WEn : out std_logic;
-- FPGA address, data and control signals.
VZ80_ADDR : inout std_logic_vector(15 downto 0);
VZ80_DATA : inout std_logic_vector(7 downto 0);
VZ80_MREQn : inout std_logic;
VZ80_IORQn : inout std_logic;
VZ80_RDn : inout std_logic;
VZ80_WRn : inout std_logic;
VZ80_M1n : inout std_logic;
VZ80_BUSACKn : in std_logic;
VZ80_CLK : out std_logic;
VIDEO_RDn : out std_logic;
VIDEO_WRn : out std_logic;
-- FPGA control signals muxed with Graphics signals from the mainboard.
VWAITn_V_CSYNC : inout std_logic; -- Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_RFSHn_V_HSYNC : inout std_logic; -- Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_HALTn_V_VSYNC : inout std_logic; -- Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VZ80_BUSRQn_V_G : out std_logic; -- Voltage translated Z80 BUSRQ / Mainboard Video Green signal.
VZ80_WAITn_V_B : out std_logic; -- Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_INTn_V_R : out std_logic; -- Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_NMIn_V_COLR : out std_logic; -- Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
CSYNC_IN : in std_logic; -- Mainboard Video Composite Sync.
HSYNC_IN : in std_logic; -- Mainboard Video Horizontal Sync.
VSYNC_IN : in std_logic; -- Mainboard Video Vertical Sync.
G_IN : in std_logic; -- Mainboard Video Green signal.
B_IN : in std_logic; -- Mainboard Video Blue signal.
R_IN : in std_logic; -- Mainboard Video Red signal.
COLR_IN : in std_logic; -- Mainboard Video Colour Modulation Frequency.
-- Clocks, system and K64F generated.
SYSCLK : in std_logic;
CTLCLK : in std_logic
);
END entity;
architecture rtl of tranZPUterSW700 is
begin
cpldl512Toplevel : entity work.cpld512
--generic map
--(
--)
port map
(
Z80_HI_ADDR => Z80_HI_ADDR,
Z80_RA_ADDR => Z80_RA_ADDR,
Z80_ADDR => Z80_ADDR,
Z80_DATA => Z80_DATA,
-- Z80 Control signals.
Z80_BUSRQn => Z80_BUSRQn,
Z80_BUSACKn => Z80_BUSACKn,
Z80_INTn => Z80_INTn,
Z80_IORQn => Z80_IORQn,
Z80_MREQn => Z80_MREQn,
Z80_NMIn => Z80_NMIn,
Z80_RDn => Z80_RDn,
Z80_WRn => Z80_WRn,
Z80_RESETn => Z80_RESETn,
Z80_HALTn => Z80_HALTn,
Z80_WAITn => Z80_WAITn,
Z80_M1n => Z80_M1n,
Z80_RFSHn => Z80_RFSHn,
Z80_CLK => Z80_CLK,
-- K64F control signals.
CTL_MBSEL => CTL_MBSEL,
CTL_BUSRQn => CTL_BUSRQn,
CTL_BUSACKn => CTL_BUSACKn,
CTL_HALTn => CTL_HALTn,
CTL_M1n => CTL_M1n,
CTL_RFSHn => CTL_RFSHn,
CTL_WAITn => CTL_WAITn,
SVCREQn => SVCREQn,
Z80_MEM => Z80_MEM,
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
SYS_BUSACKn => SYS_BUSACKn,
SYS_BUSRQn => SYS_BUSRQn,
SYS_WAITn => SYS_WAITn,
-- RAM control.
RAM_CSn => RAM_CSn,
RAM_OEn => RAM_OEn,
RAM_WEn => RAM_WEn,
-- FPGA address, data and control signals.
VZ80_ADDR => VZ80_ADDR,
VZ80_DATA => VZ80_DATA,
VZ80_MREQn => VZ80_MREQn,
VZ80_IORQn => VZ80_IORQn,
VZ80_RDn => VZ80_RDn,
VZ80_WRn => VZ80_WRn,
VZ80_M1n => VZ80_M1n,
VZ80_BUSACKn => VZ80_BUSACKn,
VZ80_CLK => VZ80_CLK,
VIDEO_RDn => VIDEO_RDn,
VIDEO_WRn => VIDEO_WRn,
-- FPGA control signals muxed with Graphics signals from the mainboard.
VWAITn_V_CSYNC => VWAITn_V_CSYNC, -- Wait signal from asserted when Video RAM is busy / Mainboard Video Composite Sync.
VZ80_RFSHn_V_HSYNC => VZ80_RFSHn_V_HSYNC, -- Voltage translated Z80 RFSH / Mainboard Video Horizontal Sync.
VZ80_HALTn_V_VSYNC => VZ80_HALTn_V_VSYNC, -- Voltage translated Z80 HALT / Mainboard Video Vertical Sync.
VZ80_BUSRQn_V_G => VZ80_BUSRQn_V_G, -- Voltage translated Z80 BUSRQ / Mainboard Video Green signal.
VZ80_WAITn_V_B => VZ80_WAITn_V_B, -- Voltage translated Z80 WAIT / Mainboard Video Blue signal.
VZ80_INTn_V_R => VZ80_INTn_V_R, -- Voltage translated Z80 INT / Mainboard Video Red signal.
VZ80_NMIn_V_COLR => VZ80_NMIn_V_COLR, -- Voltage translated Z80 NMI / Mainboard Video Colour Modulation Frequency.
CSYNC_IN => CSYNC_IN, -- Mainboard Video Composite Sync.
HSYNC_IN => HSYNC_IN, -- Mainboard Video Horizontal Sync.
VSYNC_IN => VSYNC_IN, -- Mainboard Video Vertical Sync.
G_IN => G_IN, -- Mainboard Video Green signal.
B_IN => B_IN, -- Mainboard Video Blue signal.
R_IN => R_IN, -- Mainboard Video Red signal.
COLR_IN => COLR_IN, -- Mainboard Video Colour Modulation Frequency.
-- Clocks, system and K64F generated.
SYSCLK => SYSCLK,
CTLCLK => CTLCLK
);
end architecture;

216
CPLD/SW700/v1.3/tranZPUterSW700_pkg.vhd Normal file
View File

@@ -0,0 +1,216 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: tranZPUterSW700_pkg.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: tranZPUter SW CPLD configuration file.
--
-- This module contains parameters for the CPLD in v1.2 of the tranZPUterSW 700 project.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Oct 2020 - Cut taken from the tranZPUterSW 2.1 to be used for the tranZPUter SW 700
-- as there are a lot of pin and logic differences. The tranZPUter SW is still
-- under development so didnt make sense to share the same files and make
-- them conditional.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package tranZPUterSW700_pkg is
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Target hardware modes.
constant MODE_MZ80K : integer := 0;
constant MODE_MZ80C : integer := 1;
constant MODE_MZ1200 : integer := 2;
constant MODE_MZ80A : integer := 3;
constant MODE_MZ700 : integer := 4;
constant MODE_MZ800 : integer := 5;
constant MODE_MZ80B : integer := 6;
constant MODE_MZ2000 : integer := 7;
-- Memory management modes.
constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063).
constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3.
constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
-- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_COMPAT : integer := 08; -- Compatibility monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_FPGA : integer := 21; -- Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked.
constant TZMM_TZPUM : integer := 22; -- Everything in on mainboard, no access to tranZPUter memory.
constant TZMM_TZPU : integer := 23; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected.
constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected.
constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected.
constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Target hardware.
constant CPLD_HOST_HW : integer := MODE_MZ700;
-- Target video hardware.
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
--
constant USE_K64F_CTL_CLOCK : integer := 1;
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
-- Function to reverse the order of the bits in a standard logic vector.
-- ie. 1010 becomes 0101
function reverse_vector(slv:std_logic_vector) return std_logic_vector;
-- Function to convert an integer (0 or 1) into std_logic.
--
function to_std_logic(i : in integer) return std_logic;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural;
------------------------------------------------------------
-- Records
------------------------------------------------------------
------------------------------------------------------------
-- Components
------------------------------------------------------------
end tranZPUterSW700_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body tranZPUterSW700_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then
return 0;
end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer is
variable ticks : real;
variable fracTicks : real;
begin
ticks := (Real(period) * Real(clock)) / 1000000000.0;
fracTicks := ticks - CEIL(ticks);
if fracTicks > 0.0001 then
return Integer(CEIL(ticks + 1.0));
else
return Integer(CEIL(ticks));
end if;
end function;
function reverse_vector(slv:std_logic_vector) return std_logic_vector is
variable target : std_logic_vector(slv'high downto slv'low);
begin
for idx in slv'high downto slv'low loop
target(idx) := slv(slv'low + (slv'high-idx));
end loop;
return target;
end reverse_vector;
function to_std_logic(i : in integer) return std_logic is
begin
if i = 0 then
return '0';
end if;
return '1';
end function;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
end package body;

198
FPGA/SW700/build/VideoController700_constraints.sdc
View File

@@ -1,198 +0,0 @@
## Generated SDC file "VideoController700_constraints.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {VZ80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {VZ80_CLK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
#create_generated_clock -name {vcpll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {vcpll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLOCK_50} [get_pins {vcpll|altpll_component|auto_generated|pll1|clk[0]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_CSYNC}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_CVIDEO}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_HSYNCn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_VSYNCn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_COLR}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_G}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_B}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V_R}]
# Required for the Serial Flash Loader.
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tck}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tms}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[3]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[3]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[3]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {HSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {COLR_OUT}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC_OUT}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC_OUTn}]
# Required for the Serial Flash Loader.
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {VCPLL3|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL3|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {VCPLL3|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

BIN
FPGA/SW700/build/output_files/VideoController700.jic
View File

Binary file not shown.

239
FPGA/SW700/VideoController700.vhd → FPGA/SW700/v1.2/VideoController700.vhd
View File

@@ -138,7 +138,7 @@ architecture rtl of VideoController is
-- H_DSP_START, H_DSP_END, H_DSP_WND_START, H_DSP_WND_END, V_DSP_START, V_DSP_END, V_DSP_WND_START, V_DSP_WND_END, H_LINE_END, V_LINE_END, MAX_COLUMNS, H_SYNC_START, H_SYNC_END, V_SYNC_START, V_SYNC_END, H_POLARITY, V_POLARITY, H_PX, V_PX
( 0, 320, 0, 320, 0, 200, 0, 200, 511, 259, 40, 320 + 43, 320 + 43 + 45, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 0 MZ80K/C/1200/A machines have a monochrome 60Hz display with scan of 512 x 260 for a 320x200 viewable area.
( 0, 640, 0, 640, 0, 200, 0, 200, 1023, 259, 80, 640 + 106, 640 + 106 + 90, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 1 MZ80K/C/1200/A machines with an adapted monochrome 60Hz display with scan of 1024 x 260 for a 640x200 viewable area.
--( 0, 320, 0, 320, 0, 200, 0, 200, 567, 311, 40, 320 + 80, 320 + 80 + 40, 200 + 50, 200 + 50 + 3, 0, 0, 0, 0), -- 2 MZ80K/C/1200/A machines with MZ700 style colour @ 50Hz display with scan of 568 x 312 for a 320x200 viewable area.
--( 0, 320, 0, 320, 0, 200, 0, 200, 567, 311, 40, 320 + 80, 320 + 80 + 40, 200 + 50, 200 + 50 + 3, 0, 0, 0, 0), -- 2 MZ80K/C/1200/A machines with MZ700 style colour @ 50Hz display with scan of 568 x 312 for a 320x200 viewable area.
--( 0, 640, 0, 640, 0, 200, 0, 200, 1135, 311, 80, 640 + 160, 640 + 160 + 80, 200 + 50, 200 + 50 + 3, 0, 0, 0, 0), -- 3 MZ80K/C/1200/A machines with MZ700 style colour @ 50Hz display with scan of 1136 x 312 for a 640x200 viewable area.
( 0, 320, 0, 320, 0, 200, 0, 200, 567, 259, 40, 320 + 80, 320 + 80 + 40, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 2 MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display with scan of 512 x 260 for a 320x200 viewable area.
( 0, 640, 0, 640, 0, 200, 0, 200, 1135, 259, 80, 640 + 160, 640 + 160 + 80, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 3 MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display with scan of 1024 x 260 for a 640x200 viewable area.
@@ -245,6 +245,10 @@ architecture rtl of VideoController is
signal MODE_CPLD_SWITCH : std_logic := '1'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the machine mode has changed. Flag is active for 1 clock cycle.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD Configuration register.
signal DSP_PARAM_SEL : std_logic_vector(3 downto 0); -- Display parameter selection register.
signal DSP_PARAM_DATA : unsigned(7 downto 0); -- Video parameter update data.
signal DSP_PARAM_UPD : std_logic; -- Flag to indicate parameter update data is available.
signal DSP_PARAM_ADDR : std_logic; -- Video parameter address to update.
signal DSP_PARAM_CLR : std_logic; -- Flag to indicate parameter update data processed and can be cleared.
signal PALETTE_PARAM_SEL : std_logic_vector(8 downto 0); -- Palette parameter selection register.
signal PALETTE_DO_R : std_logic_vector(4 downto 0); -- Read Red palette output.
signal PALETTE_DO_G : std_logic_vector(4 downto 0); -- Read Green palette output.
@@ -313,6 +317,7 @@ architecture rtl of VideoController is
signal GPU_COMMAND : std_logic_vector(7 downto 0); -- GPU command register.
signal GPU_STATUS : std_logic_vector(7 downto 0); -- GPU Status register.
signal GPU_STATE : GPUStateType; -- GPU FSM State.
signal GPU_START_ADDR : std_logic_vector(13 downto 0); -- Address being worked on by the GPU.
signal Z80_MA : std_logic_vector(11 downto 0); -- CPU Address Masked according to machine model.
signal CS_INVERTn : std_logic; -- Chip Select to enable Inverse mode.
signal CS_SCROLLn : std_logic; -- Chip Select to perform a hardware scroll.
@@ -452,11 +457,12 @@ begin
width_a => 5,
widthad_b => 9,
width_b => 5,
outdata_reg_b => "UNREGISTERED"
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1"
)
PORT MAP (
-- Port A used for CPU access.
clock_a => VID_CLK,
clock_a => SYS_CLK,
clocken_a => '1',
address_a => PALETTE_PARAM_SEL,
data_a => VDATA(4 downto 0),
@@ -478,11 +484,12 @@ begin
width_a => 5,
widthad_b => 9,
width_b => 5,
outdata_reg_b => "UNREGISTERED"
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1"
)
PORT MAP (
-- Port A used for CPU access.
clock_a => VID_CLK,
clock_a => SYS_CLK,
clocken_a => '1',
address_a => PALETTE_PARAM_SEL,
data_a => VDATA(4 downto 0),
@@ -504,11 +511,12 @@ begin
width_a => 5,
widthad_b => 9,
width_b => 5,
outdata_reg_b => "UNREGISTERED"
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1"
)
PORT MAP (
-- Port A used for CPU access.
clock_a => VID_CLK,
clock_a => SYS_CLK,
clocken_a => '1',
address_a => PALETTE_PARAM_SEL,
data_a => VDATA(4 downto 0),
@@ -535,11 +543,12 @@ begin
width_a => 8,
widthad_b => 11,
width_b => 16,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED"
)
PORT MAP (
-- Port A used for CPU access.
clock_a => not SYS_CLK,
clock_a => SYS_CLK,
clocken_a => '1',
address_a => VRAM_ADDR(10 downto 0) & VRAM_ADDR(11),
data_a => VRAM_DI,
@@ -565,6 +574,7 @@ begin
width_a => 8,
widthad_b => 14,
width_b => 8,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED"
)
PORT MAP (
@@ -595,6 +605,7 @@ begin
width_a => 8,
widthad_b => 14,
width_b => 8,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED"
)
PORT MAP (
@@ -626,6 +637,7 @@ begin
width_a => 8,
widthad_b => 14,
width_b => 8,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED"
)
PORT MAP (
@@ -655,7 +667,9 @@ begin
widthad_a => 12,
width_a => 8,
widthad_b => 12,
width_b => 8
width_b => 8,
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED"
)
PORT MAP (
clock_a => SYS_CLK,
@@ -682,10 +696,11 @@ begin
widthad_a => 12,
width_a => 8,
widthad_b => 12,
width_b => 8
width_b => 8,
outdata_reg_a => "UNREGISTERED"
)
PORT MAP (
clock_a => VID_CLK,
clock_a => SYS_CLK,
clocken_a => '1',
address_a => CG_ADDR(11 downto 0),
data_a => CGRAM_DI,
@@ -1225,6 +1240,7 @@ begin
VIDEOMODE <= 0;
VIDEOMODE_RESET_TIMER <= (others => '1');
VIDCLK_DIV <= '0';
DSP_PARAM_CLR <= '0';
elsif rising_edge(VID_CLK) then
@@ -1299,91 +1315,93 @@ begin
--
elsif VIDCLK_DIV = '1' then
-- Parameter update handshake. Clear the flag when the Z80 domain has cleared its flag.
if DSP_PARAM_CLR = '1' and DSP_PARAM_UPD = '0' then
DSP_PARAM_CLR <= '0';
end if;
-- Ability to adjust the video parameter registers to tune or override the default values from the lookup table. This can be useful in debugging,
-- adjusting to a new monitor etc.
--
if CS_IO_DXXn = '0' and VZ80_WRn = '0' then
-- The actual data is captured in the Z80 clock domain and passed/synchronised to this multi-clock domain via internal hand shaked registers.
--
if DSP_PARAM_UPD = '1' and DSP_PARAM_CLR = '0' then
case VADDR(3 downto 0) is
-- 0xD0 - Set the parameter number to update.
when "0000" =>
DSP_PARAM_SEL <= VDATA(3 downto 0);
-- 0xD1 - Update the lower selected parameter byte.
when "0001" =>
if DSP_PARAM_ADDR = '0' then
case DSP_PARAM_SEL is
when "0000" =>
H_DSP_START(7 downto 0) <= unsigned(VDATA);
H_DSP_START(7 downto 0) <= DSP_PARAM_DATA;
when "0001" =>
H_DSP_END(7 downto 0) <= unsigned(VDATA);
H_DSP_END(7 downto 0) <= DSP_PARAM_DATA;
when "0010" =>
H_DSP_WND_START(7 downto 0) <= unsigned(VDATA);
H_DSP_WND_START(7 downto 0) <= DSP_PARAM_DATA;
when "0011" =>
H_DSP_WND_END(7 downto 0) <= unsigned(VDATA);
H_DSP_WND_END(7 downto 0) <= DSP_PARAM_DATA;
when "0100" =>
V_DSP_START(7 downto 0) <= unsigned(VDATA);
V_DSP_START(7 downto 0) <= DSP_PARAM_DATA;
when "0101" =>
V_DSP_END(7 downto 0) <= unsigned(VDATA);
V_DSP_END(7 downto 0) <= DSP_PARAM_DATA;
when "0110" =>
V_DSP_WND_START(7 downto 0) <= unsigned(VDATA);
V_DSP_WND_START(7 downto 0) <= DSP_PARAM_DATA;
when "0111" =>
V_DSP_WND_END(7 downto 0) <= unsigned(VDATA);
V_DSP_WND_END(7 downto 0) <= DSP_PARAM_DATA;
when "1000" =>
H_LINE_END(7 downto 0) <= unsigned(VDATA);
H_LINE_END(7 downto 0) <= DSP_PARAM_DATA;
when "1001" =>
V_LINE_END(7 downto 0) <= unsigned(VDATA);
V_LINE_END(7 downto 0) <= DSP_PARAM_DATA;
when "1010" =>
MAX_COLUMN(7 downto 0) <= unsigned(VDATA);
MAX_COLUMN(7 downto 0) <= DSP_PARAM_DATA;
when "1011" =>
H_SYNC_START(7 downto 0) <= unsigned(VDATA);
H_SYNC_START(7 downto 0) <= DSP_PARAM_DATA;
when "1100" =>
H_SYNC_END(7 downto 0) <= unsigned(VDATA);
H_SYNC_END(7 downto 0) <= DSP_PARAM_DATA;
when "1101" =>
V_SYNC_START(7 downto 0) <= unsigned(VDATA);
V_SYNC_START(7 downto 0) <= DSP_PARAM_DATA;
when "1110" =>
V_SYNC_END(7 downto 0) <= unsigned(VDATA);
V_SYNC_END(7 downto 0) <= DSP_PARAM_DATA;
when "1111" =>
H_PX(7 downto 0) <= unsigned(VDATA);
H_PX(7 downto 0) <= DSP_PARAM_DATA;
end case;
else
-- 0xD2 - Update the upper selected parameter byte.
when "0010" =>
case DSP_PARAM_SEL is
when "0000" =>
H_DSP_START(15 downto 8) <= unsigned(VDATA);
H_DSP_START(15 downto 8) <= DSP_PARAM_DATA;
when "0001" =>
H_DSP_END(15 downto 8) <= unsigned(VDATA);
H_DSP_END(15 downto 8) <= DSP_PARAM_DATA;
when "0010" =>
H_DSP_WND_START(15 downto 8) <= unsigned(VDATA);
H_DSP_WND_START(15 downto 8) <= DSP_PARAM_DATA;
when "0011" =>
H_DSP_WND_END(15 downto 8) <= unsigned(VDATA);
H_DSP_WND_END(15 downto 8) <= DSP_PARAM_DATA;
when "0100" =>
V_DSP_START(15 downto 8) <= unsigned(VDATA);
V_DSP_START(15 downto 8) <= DSP_PARAM_DATA;
when "0101" =>
V_DSP_END(15 downto 8) <= unsigned(VDATA);
V_DSP_END(15 downto 8) <= DSP_PARAM_DATA;
when "0110" =>
V_DSP_WND_START(15 downto 8) <= unsigned(VDATA);
V_DSP_WND_START(15 downto 8) <= DSP_PARAM_DATA;
when "0111" =>
V_DSP_WND_END(15 downto 8) <= unsigned(VDATA);
V_DSP_WND_END(15 downto 8) <= DSP_PARAM_DATA;
when "1000" =>
H_LINE_END(15 downto 8) <= unsigned(VDATA);
H_LINE_END(15 downto 8) <= DSP_PARAM_DATA;
when "1001" =>
V_LINE_END(15 downto 8) <= unsigned(VDATA);
V_LINE_END(15 downto 8) <= DSP_PARAM_DATA;
when "1010" =>
when "1011" =>
H_SYNC_START(15 downto 8) <= unsigned(VDATA);
H_SYNC_START(15 downto 8) <= DSP_PARAM_DATA;
when "1100" =>
H_SYNC_END(15 downto 8) <= unsigned(VDATA);
H_SYNC_END(15 downto 8) <= DSP_PARAM_DATA;
when "1101" =>
V_SYNC_START(15 downto 8) <= unsigned(VDATA);
V_SYNC_START(15 downto 8) <= DSP_PARAM_DATA;
when "1110" =>
V_SYNC_END(15 downto 8) <= unsigned(VDATA);
V_SYNC_END(15 downto 8) <= DSP_PARAM_DATA;
when "1111" =>
V_PX(7 downto 0) <= unsigned(VDATA);
V_PX(7 downto 0) <= DSP_PARAM_DATA;
end case;
when others =>
end case;
end if;
-- Flag the data has been registered.
DSP_PARAM_CLR <= '1';
end if;
-- Activate/deactivate signals according to pixel position.
@@ -1511,8 +1529,7 @@ begin
-- 0x82 = Parameterised Clear framebuffer screen. Parameters: start x [87:72], start y [71:56], end x [55:40], end y [39:24], R Filter [23:16], G Filter [15:8], B Filter [7:0] - R/G/B Filters are 8 pixel wide.
-- Other commands.
-- 0xFF = Immediate GPU reset, cancel current command and return to idle.
GPU: process( VRESETn, IF_CLK, SYS_CLK )
variable GPU_START_ADDR : std_logic_vector(13 downto 0); -- Current start address being worked on by the GPU.
GPU: process( VRESETn, SYS_CLK )
variable GPU_START_X : integer range 0 to 640; -- X starting location.
variable GPU_START_Y : integer range 0 to 200; -- Y starting location.
variable GPU_END_X : integer range 0 to 640; -- X ending location.
@@ -1639,7 +1656,7 @@ begin
GPU_STATE <= GPU_FB_Clear_Start;
when GPU_FB_Clear_Start =>
GPU_START_ADDR := std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14));
GPU_START_ADDR <= std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14));
GRAM_GPU_ADDR <= std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14));
GRAM_GPU_DI_R <= GPU_FILTER_R;
GRAM_GPU_DI_G <= GPU_FILTER_G;
@@ -1666,7 +1683,7 @@ begin
GPU_STATE <= GPU_FB_Clear_3;
else
GRAM_GPU_ADDR <= GPU_START_ADDR + 80;
GPU_START_ADDR:= GPU_START_ADDR + 80;
GPU_START_ADDR<= GPU_START_ADDR + 80;
GPU_VAR_Y := GPU_VAR_Y + 1;
GPU_STATE <= GPU_FB_Clear_1;
end if;
@@ -1741,10 +1758,10 @@ begin
when GPU_VRAM_Clear_Start =>
-- For modes with hardware scroll, add in the current offset so the visible part of the display is updated.
if MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ700 = '1' then
GPU_START_ADDR:= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14)) + (OFFSET_ADDR & "000");
GPU_START_ADDR<= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14)) + (OFFSET_ADDR & "000");
VRAM_GPU_ADDR <= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 13)) + (OFFSET_ADDR & "000");
else
GPU_START_ADDR:= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14));
GPU_START_ADDR<= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14));
VRAM_GPU_ADDR <= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 13));
end if;
GPU_VAR_Y := GPU_START_Y;
@@ -1783,10 +1800,10 @@ begin
-- Alternate between character ram and attribute ram, they differ by 0x800 bytes, ie; 0xD000:D7FF and 0xD800:0xDFFF
if VRAM_GPU_ADDR < X"800" then
VRAM_GPU_ADDR <= GPU_START_ADDR(12 downto 0) + X"800";
GPU_START_ADDR := GPU_START_ADDR + X"800";
GPU_START_ADDR <= GPU_START_ADDR + X"800";
else
VRAM_GPU_ADDR <= GPU_START_ADDR(12 downto 0) - X"800" + GPU_COLUMNS;
GPU_START_ADDR := GPU_START_ADDR - X"800" + GPU_COLUMNS;
GPU_START_ADDR <= GPU_START_ADDR - X"800" + GPU_COLUMNS;
GPU_VAR_Y := GPU_VAR_Y + 1;
-- If we have filled to the set line, exit.
@@ -1893,6 +1910,7 @@ begin
CGRAM_WEn <= '1';
GPU_PARAMS <= (others => '0');
GPU_COMMAND <= (others => '0');
DSP_PARAM_UPD <= '0';
elsif rising_edge(IF_CLK) then
@@ -2270,13 +2288,44 @@ begin
-- Set the mode switch event flag if the mode changes.
if CPLD_CFG_DATA(2 downto 0) /= VDATA(2 downto 0) then
MODE_CPLD_SWITCH <= '1';
MODE_CPLD_SWITCH <= '1';
end if;
-- Store the new value into the register, used for read operations.
CPLD_CFG_DATA <= VDATA;
CPLD_CFG_DATA <= VDATA;
else
MODE_CPLD_SWITCH <= '0';
MODE_CPLD_SWITCH <= '0';
end if;
-- Clear the parameter update flag if it has been actioned and the handshake has been set.
if DSP_PARAM_UPD = '1' and DSP_PARAM_CLR = '1' then
DSP_PARAM_UPD <= '0';
end if;
-- Ability to adjust the video parameter registers to tune or override the default values from the lookup table. This can be useful in debugging,
-- adjusting to a new monitor etc.
--
if CS_IO_DXXn = '0' and VZ80_WRn = '0' then
case VADDR(3 downto 0) is
-- 0xD0 - Set the parameter number to update.
when "0000" =>
DSP_PARAM_SEL <= VDATA(3 downto 0);
-- 0xD1 - Update the lower selected parameter byte.
when "0001" =>
DSP_PARAM_DATA <= unsigned(VDATA);
DSP_PARAM_ADDR <= '0';
DSP_PARAM_UPD <= '1';
-- 0xD2 - Update the upper selected parameter byte.
when "0010" =>
DSP_PARAM_DATA <= unsigned(VDATA);
DSP_PARAM_ADDR <= '1';
DSP_PARAM_UPD <= '1';
when others =>
end case;
end if;
end if;
@@ -2688,32 +2737,42 @@ begin
-- Process to output signals on clock edges, to clean them up as needed.
--
process(SYS_CLK)
begin
if rising_edge(SYS_CLK) then
if MODE_CPLD_MB_VIDEOn = '1' then
if H_POLARITY(0) = '0' then
HSYNC_OUTn <= H_SYNCni;
else
HSYNC_OUTn <= not H_SYNCni;
end if;
if V_POLARITY(0) = '0' then
VSYNC_OUTn <= V_SYNCni;
else
VSYNC_OUTn <= not V_SYNCni;
end if;
elsif MODE_CPLD_MB_VIDEOn = '0' then
HSYNC_OUTn <= V_HSYNCn; -- Horizontal sync (negative) from mainboard.
VSYNC_OUTn <= V_VSYNCn; -- Vertical sync (negative) from mainboard.
end if;
end if;
end process;
-- -- Process to output signals on clock edges, to clean them up as needed.
-- --
-- process(VID_CLK)
-- begin
-- if rising_edge(VID_CLK) then
-- if MODE_CPLD_MB_VIDEOn = '1' then
--
-- if H_POLARITY(0) = '0' then
-- HSYNC_OUTn <= H_SYNCni;
-- else
-- HSYNC_OUTn <= not H_SYNCni;
-- end if;
--
-- if V_POLARITY(0) = '0' then
-- VSYNC_OUTn <= V_SYNCni;
-- else
-- VSYNC_OUTn <= not V_SYNCni;
-- end if;
--
-- elsif MODE_CPLD_MB_VIDEOn = '0' then
-- HSYNC_OUTn <= V_HSYNCn; -- Horizontal sync (negative) from mainboard.
-- VSYNC_OUTn <= V_VSYNCn; -- Vertical sync (negative) from mainboard.
-- end if;
-- end if;
-- end process;
HSYNC_OUTn <= V_HSYNCn when MODE_CPLD_MB_VIDEOn = '0'
else
H_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and H_POLARITY(0) = '0'
else
not H_SYNCni; -- Horizontal sync (negative) from mainboard.
VSYNC_OUTn <= V_VSYNCn when MODE_CPLD_MB_VIDEOn = '0'
else
V_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and V_POLARITY(0) = '0'
else
not V_SYNCni; -- Vertical sync (negative) from mainboard.
-- Set the mainboard video state, 0 = enabled, 1 = disabled.
MODE_CPLD_MB_VIDEOn <= CPLD_CFG_DATA(3);

2
FPGA/SW700/VideoController700_Toplevel.vhd → FPGA/SW700/v1.2/VideoController700_Toplevel.vhd
View File

@@ -120,7 +120,7 @@ begin
VCPLL2 : entity work.Video_Clock_II
port map
(
inclk0 => SYS_CLK,
inclk0 => CLOCK_50,
areset => '0',
c0 => VIDCLK_65MHZ,
c1 => VIDCLK_25_175MHZ,

0
FPGA/SW700/VideoController700_pkg.vhd → FPGA/SW700/v1.2/VideoController700_pkg.vhd
View File

0
FPGA/SW700/build/SFL.cmp → FPGA/SW700/v1.2/build/SFL.cmp
View File

0
FPGA/SW700/build/SFL.qip → FPGA/SW700/v1.2/build/SFL.qip
View File

0
FPGA/SW700/build/SFL.vhd → FPGA/SW700/v1.2/build/SFL.vhd
View File

0
FPGA/SW700/build/SFL_inst.vhd → FPGA/SW700/v1.2/build/SFL_inst.vhd
View File

0
FPGA/SW700/build/VideoController700.qpf → FPGA/SW700/v1.2/build/VideoController700.qpf
View File

0
FPGA/SW700/build/VideoController700.qsf → FPGA/SW700/v1.2/build/VideoController700.qsf
View File

269
FPGA/SW700/v1.2/build/VideoController700_constraints.sdc Normal file
View File

@@ -0,0 +1,269 @@
## Generated SDC file "VideoController700_constraints.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {VZ80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {VZ80_CLK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
create_generated_clock -name {SYS_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_8MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_16MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
create_generated_clock -name {VIDCLK_40MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
create_generated_clock -name {VIDCLK_65MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 5 -phase 0.00 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_25_175MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 91 -divide_by 90 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_8_86719MHZ} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 324 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_17_7344MHZ} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 162 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[1]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
set_input_delay -add_delay -clock [get_clocks {VZ80_CLK}] 1.000 [get_ports {VZ80_CLK}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[0]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[1]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[2]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[3]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[4]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[5]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[6]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[7]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {V_HSYNCn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {V_VSYNCn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {V_COLR}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {V_G}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {V_B}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {V_R}]
# Required for the Serial Flash Loader.
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tck}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tms}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[4]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[5]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[6]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[7]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VWAITn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {HSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {COLR_OUT}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC_OUT}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC_OUTn}]
# Required for the Serial Flash Loader.
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
# There is no relationship between the different video frequencies, only one is used at a time and they are switched through synchronised D-Type flip flops.
set_false_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
# Z80 clock has no relationship to the video frequencies, it is used only for latching data asynchronous to the FPGA clocks.
set_false_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# The system clock has no real relationship with the video frequencies, rendering and display. The only place they meet is in the dual port BRAM.
set_false_path -from [get_clocks {SYS_CLK}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# Clock 50MHZ, the input oscillator is only used for the PLL input and as I/O input/output latch which is detached from the video block
set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# The Z80 data, address and control lines do not go to the video block (except the parameter update which is not critical) so set it as a false path so as not to consider.
set_false_path -from [get_ports {VDATA[*]}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
set_false_path -from [get_ports {VADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
set_false_path -from [get_ports {VZ80_WRn VZ80_RDn VZ80_IORQn}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -setup -start 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VZ80_CLK}] -hold -start 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VZ80_CLK}] -setup -start 2
set_multicycle_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {SYS_CLK}] -hold -start 2
set_multicycle_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {SYS_CLK}] -setup -start 3
# GPU control and run variables have at least 1 clock between them being setup and used.
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -hold -start 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

0
FPGA/SW700/build/Video_Clock.cmp → FPGA/SW700/v1.2/build/Video_Clock.cmp
View File

0
FPGA/SW700/build/Video_Clock.ppf → FPGA/SW700/v1.2/build/Video_Clock.ppf
View File

0
FPGA/SW700/build/Video_Clock.qip → FPGA/SW700/v1.2/build/Video_Clock.qip
View File

0
FPGA/SW700/build/Video_Clock.vhd → FPGA/SW700/v1.2/build/Video_Clock.vhd
View File

0
FPGA/SW700/build/Video_Clock_II.cmp → FPGA/SW700/v1.2/build/Video_Clock_II.cmp
View File

0
FPGA/SW700/build/Video_Clock_II.ppf → FPGA/SW700/v1.2/build/Video_Clock_II.ppf
View File

0
FPGA/SW700/build/Video_Clock_II.qip → FPGA/SW700/v1.2/build/Video_Clock_II.qip
View File

22
FPGA/SW700/build/Video_Clock_II.vhd → FPGA/SW700/v1.2/build/Video_Clock_II.vhd
View File

@@ -147,15 +147,15 @@ BEGIN
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "LOW",
clk0_divide_by => 12,
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 13,
clk0_phase_shift => "0",
clk1_divide_by => 240,
clk1_divide_by => 5000,
clk1_duty_cycle => 50,
clk1_multiply_by => 101,
clk1_multiply_by => 5051,
clk1_phase_shift => "0",
inclk0_input_frequency => 8333,
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_II",
lpm_type => "altpll",
@@ -240,7 +240,7 @@ END SYN;
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "130.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.509998"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -248,7 +248,7 @@ END SYN;
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "120.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
@@ -269,7 +269,7 @@ END SYN;
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "130.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.51000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
@@ -315,15 +315,15 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "240"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5000"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "101"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5051"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8333"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"

25
FPGA/SW700/v1.2/build/Video_Clock_III.cmp Normal file
View File

@@ -0,0 +1,25 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Video_Clock_III
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

12
FPGA/SW700/v1.2/build/Video_Clock_III.ppf Normal file
View File

@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="Video_Clock_III" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

6
FPGA/SW700/v1.2/build/Video_Clock_III.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_III.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III.ppf"]

397
FPGA/SW700/v1.2/build/Video_Clock_III.vhd Normal file
View File

@@ -0,0 +1,397 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Video_Clock_III.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Video_Clock_III IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Video_Clock_III;
ARCHITECTURE SYN OF video_clock_iii IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "LOW",
clk0_divide_by => 15625,
clk0_duty_cycle => 50,
clk0_multiply_by => 5542,
clk0_phase_shift => "0",
clk1_divide_by => 15625,
clk1_duty_cycle => 50,
clk1_multiply_by => 11084,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_III",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "17.734400"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "35.468800"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "17.73440000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "35.46880000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Video_Clock_II.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15625"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5542"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11084"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

7
FPGA/SW700/v1.2/build/Video_Clock_III_inst.vhd Normal file
View File

@@ -0,0 +1,7 @@
Video_Clock_III_inst : Video_Clock_III PORT MAP (
areset => areset_sig,
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
locked => locked_sig
);

0
FPGA/SW700/build/Video_Clock_II_inst.vhd → FPGA/SW700/v1.2/build/Video_Clock_II_inst.vhd
View File

0
FPGA/SW700/build/Video_Clock_inst.vhd → FPGA/SW700/v1.2/build/Video_Clock_inst.vhd
View File

0
FPGA/SW700/build/vbuffer.cmp → FPGA/SW700/v1.2/build/vbuffer.cmp
View File

0
FPGA/SW700/build/vbuffer.qip → FPGA/SW700/v1.2/build/vbuffer.qip
View File

0
FPGA/SW700/build/vbuffer.vhd → FPGA/SW700/v1.2/build/vbuffer.vhd
View File

0
FPGA/SW700/build/vbuffer_inst.vhd → FPGA/SW700/v1.2/build/vbuffer_inst.vhd
View File

1094
FPGA/SW700/v1.3/T80/T80.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

194
FPGA/SW700/v1.3/T80/T8080se.vhd Normal file
View File

@@ -0,0 +1,194 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

371
FPGA/SW700/v1.3/T80/T80_ALU.vhd Normal file
View File

@@ -0,0 +1,371 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

2029
FPGA/SW700/v1.3/T80/T80_MCode.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

220
FPGA/SW700/v1.3/T80/T80_Pack.vhd Normal file
View File

@@ -0,0 +1,220 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

114
FPGA/SW700/v1.3/T80/T80_Reg.vhd Normal file
View File

@@ -0,0 +1,114 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

176
FPGA/SW700/v1.3/T80/T80_RegX.vhd Normal file
View File

@@ -0,0 +1,176 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;

265
FPGA/SW700/v1.3/T80/T80a.vhd Normal file
View File

@@ -0,0 +1,265 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLK_EN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
BUSAK_n <= '0' when RESET_n = '0' else BUSAK_n_i;
MREQ_n <= '1' when RESET_n = '0' else MREQ_n_i; -- when BUSAK_n_i = '1' else 'Z';
IORQ_n <= '1' when RESET_n = '0' else IORQ_n_i; -- when BUSAK_n_i = '1' else 'Z';
RD_n <= '1' when RESET_n = '0' else RD_n_i; -- when BUSAK_n_i = '1' else 'Z';
WR_n <= '1' when RESET_n = '0' else WR_n_i; -- when BUSAK_n_i = '1' else 'Z';
RFSH_n <= '1' when RESET_n = '0' else RFSH_n_i; -- when BUSAK_n_i = '1' else 'Z';
A <= (others => '0') when RESET_n = '0' else A_i; -- when BUSAK_n_i = '1' else (others => 'Z');
DOUT <= (others => '0') when RESET_n = '0' else DO;
--D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLK_EN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => DIN,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(DIN);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

192
FPGA/SW700/v1.3/T80/T80se.vhd Normal file
View File

@@ -0,0 +1,192 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

179
FPGA/SW700/v1.3/T80/T80sed.vhd Normal file
View File

@@ -0,0 +1,179 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

2822
FPGA/SW700/v1.3/VideoController.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

1
FPGA/SW700/v1.3/ZPU/zpu_core_evo.vhd Symbolic link
View File

@@ -0,0 +1 @@
../../../../cpu/zpu_core_evo.vhd

1
FPGA/SW700/v1.3/ZPU/zpu_core_evo_L2.vhd Symbolic link
View File

@@ -0,0 +1 @@
../../../../cpu/zpu_core_evo_L2.vhd

358
FPGA/SW700/v1.3/ZPU/zpu_pkg.vhd Normal file
View File

@@ -0,0 +1,358 @@
-- ZPU
--
-- Copyright 2004-2008 oharboe - <20>yvind Harboe - oyvind.harboe@zylin.com
-- Copyright 2018-2019 psmart - Philip Smart
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package zpu_pkg is
-- Necessary functions for type conversion.
--
function bool_to_integer(level : boolean) return integer;
-- Evo specific options.
--
constant EVO_USE_INSN_BUS : boolean := true; -- Use a seperate instruction bus to connect to the BRAM memory. All other operations go over the normal bus.
constant EVO_USE_HW_BYTE_WRITE : boolean := true; -- Implement hardware writing of bytes, reads are always 32bit and aligned.
constant EVO_USE_HW_WORD_WRITE : boolean := true; -- Implement hardware writing of 16bit words, reads are always 32bit and aligned.
constant EVO_USE_WB_BUS : boolean := false; -- Implement the wishbone interface in addition to the standard direct interface. NB: Change WB_ACTIVE to 1 above if enabling.
-- Debug options.
--
constant DEBUG_CPU : boolean := false; -- Enable CPU debugging output.
constant DEBUG_LEVEL : integer := 0; -- Level of debugging output. 0 = Basic, such as Breakpoint, 1 =+ Executing Instructions, 2 =+ L1 Cache contents, 3 =+ L2 Cache contents, 4 =+ Memory contents, 5=+ 4Everything else.
constant DEBUG_MAX_TX_FIFO_BITS : integer := 10; -- Size of UART TX Fifo for debug output.
constant DEBUG_MAX_FIFO_BITS : integer := 2; -- Size of debug output data records fifo.
constant DEBUG_TX_BAUD_RATE : integer := 115200; --230400; -- Baud rate for the debug transmitter.
-- Constants common to all ZPU models source code.
constant Generate_Trace : boolean := false; -- generate trace output or not.
constant wordPower : integer := 5; -- The number of bits in a word, defined as 2^wordPower).
constant DontCareValue : std_logic := 'X'; -- during simulation, set this to '0' to get matching trace.txt
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
constant WB_ACTIVE : integer := bool_to_integer(EVO_USE_WB_BUS); -- Set to 1 if the wishbone interface is active to divide the address space in two, lower = direct access, upper = wishbone.
constant maxAddrBit : integer := 24 + WB_ACTIVE; -- Maximum address limit in bits.
constant maxAddrSize : integer := (2**maxAddrBit); -- Maximum address space size in bytes.
constant maxIOBit : integer := maxAddrBit - WB_ACTIVE - 4; -- Upper bit (to define range) of IO space in top section of address space.
constant ioBit : integer := maxAddrBit - 1; -- Non-EVO: MSB is used to differentiate IO and memory.
constant ADDR_32BIT_SIZE : integer := maxAddrBit - minAddrBit; -- Bits in the address bus relevant for 32bit access.
constant WB_SELECT_BIT : integer := maxAddrBit - 1; -- Bit which divides the wishbone interface from normal memory space.
-- Ranges used throughout the SOC/ZPU source.
subtype ADDR_BIT_RANGE is natural range maxAddrBit-1 downto 0; -- Full address range - 1 byte aligned
subtype ADDR_16BIT_RANGE is natural range maxAddrBit-1 downto 1; -- Full address range - 2 bytes (16bit) aligned
subtype ADDR_32BIT_RANGE is natural range maxAddrBit-1 downto minAddrBit; -- Full address range - 4 bytes (32bit) aligned
subtype ADDR_64BIT_RANGE is natural range maxAddrBit-1 downto minAddrBit+1; -- Full address range - 8 bytes (64bit) aligned
subtype ADDR_IOBIT_RANGE is natural range ioBit downto minAddrBit; -- Non-EVO: IO range.
subtype WORD_32BIT_RANGE is natural range wordSize-1 downto 0; -- Number of bits in a word (normally 32 for this CPU).
subtype WORD_16BIT_RANGE is natural range (wordSize/2)-1 downto 0; -- Number of bits in a half-word (normally 16 for this CPU).
subtype WORD_UPPER_16BIT_RANGE is natural range (wordSize/2)-1 downto wordSize/4; -- Number of bits in a half-word (normally 16 for this CPU).
subtype WORD_LOWER_16BIT_RANGE is natural range (wordSize/4)-1 downto 0; -- Number of bits in a half-word (normally 16 for this CPU).
subtype WORD_8BIT_RANGE is natural range (wordSize/4)-1 downto 0; -- Number of bits in a byte (normally 8 for this CPU).
subtype WORD_4BYTE_RANGE is natural range wordBytes-1 downto 0; -- Bits needed to represent wordSize in bytes (normally 4 for 32bits).
subtype BYTE_RANGE is natural range 7 downto 0; -- Number of bits in a byte.
------------------------------------------------------------
-- components
------------------------------------------------------------
component zpu_core_evo is
generic (
-- Optional hardware features to be implemented.
IMPL_HW_BYTE_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 8 bits-write 32bits.
IMPL_HW_WORD_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits.
IMPL_OPTIMIZE_IM : boolean := true; -- If the instruction cache is enabled, optimise Im instructions to gain speed.
IMPL_USE_INSN_BUS : boolean := true; -- Use a seperate bus to read instruction memory, normally implemented in BRAM.
IMPL_USE_WB_BUS : boolean := true; -- Use the wishbone interface in addition to direct access bus.
-- Optional instructions to be implemented in hardware:
IMPL_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT).
IMPL_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right.
IMPL_CALL : boolean := true; -- Call to direct address.
IMPL_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter).
IMPL_DIV : boolean := true; -- 32bit signed division.
IMPL_EQ : boolean := true; -- Equality test.
IMPL_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set.
IMPL_FIADD32 : boolean := true; -- Fixed point Q17.15 addition.
IMPL_FIDIV32 : boolean := true; -- Fixed point Q17.15 division.
IMPL_FIMULT32 : boolean := true; -- Fixed point Q17.15 multiplication.
IMPL_LOADB : boolean := true; -- Load single byte from memory.
IMPL_LOADH : boolean := true; -- Load half word (16bit) from memory.
IMPL_LSHIFTRIGHT : boolean := true; -- Logical shift right.
IMPL_MOD : boolean := true; -- 32bit modulo (remainder after division).
IMPL_MULT : boolean := true; -- 32bit signed multiplication.
IMPL_NEG : boolean := true; -- Negate value in TOS.
IMPL_NEQ : boolean := true; -- Not equal test.
IMPL_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer.
IMPL_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack.
IMPL_STOREB : boolean := true; -- Store/Write a single byte to memory/IO.
IMPL_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO.
IMPL_SUB : boolean := true; -- 32bit signed subtract.
IMPL_XOR : boolean := true; -- Exclusive or of value in TOS.
-- Size/Control parameters for the optional hardware.
MAX_INSNRAM_SIZE : integer := 32768; -- Maximum size of the optional Instruction BRAM on the INSN Bus.
MAX_L1CACHE_BITS : integer := 4; -- Maximum size in bytes of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
MAX_L2CACHE_BITS : integer := 12; -- Maximum size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
MAX_MXCACHE_BITS : integer := 4; -- Maximum size of the memory transaction cache governed by the number of bits.
RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU.
START_ADDR_MEM : integer := 0; -- Start address of program memory.
STACK_ADDR : integer := 0; -- Initial stack address on CPU start.
CLK_FREQ : integer := 100000000 -- Frequency of the input clock.
);
port (
CLK : in std_logic;
RESET : in std_logic;
ENABLE : in std_logic;
--
MEM_BUSY : in std_logic;
MEM_DATA_IN : in std_logic_vector(WORD_32BIT_RANGE);
MEM_DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE);
MEM_ADDR : out std_logic_vector(ADDR_BIT_RANGE);
MEM_WRITE_ENABLE : out std_logic;
MEM_READ_ENABLE : out std_logic;
MEM_WRITE_BYTE : out std_logic;
MEM_WRITE_HWORD : out std_logic;
-- Instruction memory path
MEM_BUSY_INSN : in std_logic;
MEM_DATA_IN_INSN : in std_logic_vector(WORD_32BIT_RANGE);
MEM_ADDR_INSN : out std_logic_vector(ADDR_BIT_RANGE);
MEM_READ_ENABLE_INSN : out std_logic;
-- Master Wishbone Memory/IO bus interface.
WB_CLK_I : in std_logic;
WB_RST_I : in std_logic;
WB_ACK_I : in std_logic;
WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE);
WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE);
WB_ADR_O : out std_logic_vector(ADDR_BIT_RANGE);
WB_CYC_O : out std_logic;
WB_STB_O : out std_logic;
WB_CTI_O : out std_logic_vector(2 downto 0);
WB_WE_O : out std_logic;
WB_SEL_O : out std_logic_vector(WORD_4BYTE_RANGE);
WB_HALT_I : in std_logic;
WB_ERR_I : in std_logic;
WB_INTA_I : in std_logic;
-- Set to one to jump to interrupt vector
-- The ZPU will communicate with the hardware that caused the
-- interrupt via memory mapped IO or the interrupt flag can
-- be cleared automatically
INT_REQ : in std_logic;
INT_ACK : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine.
INT_DONE : out std_logic; -- Interrupt service routine completed/done.
-- Break and debug signals.
BREAK : out std_logic; -- A break instruction encountered.
CONTINUE : in std_logic; -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction.
DEBUG_TXD : out std_logic -- Debug serial output.
);
end component zpu_core_evo;
component dpram
generic (
init_file : string;
widthad_a : natural;
width_a : natural;
widthad_b : natural;
width_b : natural;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
port (
clock_a : in std_logic := '1';
clocken_a : in std_logic := '1';
address_a : in std_logic_vector (widthad_a-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0);
wren_a : in std_logic := '0';
q_a : out std_logic_vector (width_a-1 downto 0);
clock_b : in std_logic;
clocken_b : in std_logic := '1';
address_b : in std_logic_vector (widthad_b-1 downto 0);
data_b : in std_logic_vector (width_b-1 downto 0);
wren_b : in std_logic := '0';
q_b : out std_logic_vector (width_b-1 downto 0)
);
end component;
------------------------------------------------------------
-- constants
------------------------------------------------------------
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
--
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
--
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
--
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
--
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_Extend : std_logic_vector(3 downto 0) := "1111";
--
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
--
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
--
constant OpCode_NA5 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
--
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
--
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
--
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
--
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
--
constant OpCode_Div : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(53, 6));
constant OpCode_Mod : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(54, 6));
--
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
--
constant OpCode_FiAdd32 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(58, 6));
constant OpCode_FiDiv32 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(59, 6));
constant OpCode_FiMult32 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(60, 6));
--
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_NA6 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
--
-- Extension instructions.
constant Opcode_Ex_ESR : std_logic_vector(7 downto 0) := "00000000";
constant Opcode_Ex_LDIR : std_logic_vector(7 downto 3) := "00001";
constant Opcode_Ex_Fill : std_logic_vector(7 downto 3) := "00010";
--
constant OpCode_Size : integer := 8;
--
------------------------------------------------------------
-- records
------------------------------------------------------------
-- Debug structure, currently only for the trace module
type zpu_dbgo_t is record
b_inst : std_logic;
opcode : unsigned(OpCode_Size-1 downto 0);
pc : unsigned(31 downto 0);
sp : unsigned(31 downto 0);
stk_a : unsigned(31 downto 0);
stk_b : unsigned(31 downto 0);
end record;
type zpu_dbg_t is record
FMT_DATA_PRTMODE : std_logic_vector(1 downto 0);
FMT_PRE_SPACE : std_logic;
FMT_POST_SPACE : std_logic;
FMT_PRE_CR : std_logic;
FMT_POST_CRLF : std_logic;
FMT_SPLIT_DATA : std_logic_vector(1 downto 0);
DATA_BYTECNT : std_logic_vector(2 downto 0);
DATA2_BYTECNT : std_logic_vector(2 downto 0);
DATA3_BYTECNT : std_logic_vector(2 downto 0);
DATA4_BYTECNT : std_logic_vector(2 downto 0);
WRITE_DATA : std_logic;
WRITE_DATA2 : std_logic;
WRITE_DATA3 : std_logic;
WRITE_DATA4 : std_logic;
WRITE_OPCODE : std_logic;
WRITE_DECODED_OPCODE : std_logic;
WRITE_PC : std_logic;
WRITE_SP : std_logic;
WRITE_STACK_TOS : std_logic;
WRITE_STACK_NOS : std_logic;
DATA : std_logic_vector(63 downto 0);
DATA2 : std_logic_vector(63 downto 0);
DATA3 : std_logic_vector(63 downto 0);
DATA4 : std_logic_vector(63 downto 0);
OPCODE : std_logic_vector(OpCode_Size-1 downto 0);
DECODED_OPCODE : std_logic_vector(5 downto 0);
PC : std_logic_vector(ADDR_BIT_RANGE);
SP : std_logic_vector(ADDR_32BIT_RANGE);
STACK_TOS : std_logic_vector(WORD_32BIT_RANGE);
STACK_NOS : std_logic_vector(WORD_32BIT_RANGE);
end record;
constant ZPU_DBG_T_INIT : zpu_dbg_t := ("00", '0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
constant ZPU_DBG_T_DONTCARE : zpu_dbg_t := ((others => DontCareValue), DontCareValue, DontCareValue, DontCareValue, DontCareValue, (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue));
end zpu_pkg;
package body zpu_pkg is
-- Helper to convert Boolean to integer.
--
function bool_to_integer(level : boolean) return integer is
begin
if level then
return(1);
else
return(0);
end if;
end function;
end package body zpu_pkg;

1
FPGA/SW700/v1.3/ZPU/zpu_uart_debug.vhd Symbolic link
View File

@@ -0,0 +1 @@
../../../../cpu/zpu_uart_debug.vhd

21
FPGA/SW700/v1.3/build/SFL.cmp Normal file
View File

@@ -0,0 +1,21 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component SFL
PORT
(
noe_in : IN STD_LOGIC
);
end component;

5
FPGA/SW700/v1.3/build/SFL.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "Serial Flash Loader"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "SFL.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL.cmp"]

102
FPGA/SW700/v1.3/build/SFL.vhd Normal file
View File

@@ -0,0 +1,102 @@
-- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: SFL.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY SFL IS
PORT
(
noe_in : IN STD_LOGIC
);
END SFL;
ARCHITECTURE SYN OF sfl IS
COMPONENT altserial_flash_loader
GENERIC (
enable_quad_spi_support : NATURAL;
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_quad_spi_support => 0,
enable_shared_access => "OFF",
enhanced_mode => 1,
intended_device_family => "Cyclone IV E",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

21
FPGA/SW700/v1.3/build/SFL_IV.cmp Normal file
View File

@@ -0,0 +1,21 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component SFL_IV
PORT
(
noe_in : IN STD_LOGIC
);
end component;

5
FPGA/SW700/v1.3/build/SFL_IV.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "Serial Flash Loader"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "SFL_IV.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL_IV_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL_IV.cmp"]

102
FPGA/SW700/v1.3/build/SFL_IV.vhd Normal file
View File

@@ -0,0 +1,102 @@
-- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: SFL_IV.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY SFL_IV IS
PORT
(
noe_in : IN STD_LOGIC
);
END SFL_IV;
ARCHITECTURE SYN OF sfl_iv IS
COMPONENT altserial_flash_loader
GENERIC (
enable_quad_spi_support : NATURAL;
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_quad_spi_support => 0,
enable_shared_access => "OFF",
enhanced_mode => 1,
intended_device_family => "Cyclone IV E",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_IV_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

3
FPGA/SW700/v1.3/build/SFL_IV_inst.vhd Normal file
View File

@@ -0,0 +1,3 @@
SFL_IV_inst : SFL_IV PORT MAP (
noe_in => noe_in_sig
);

3
FPGA/SW700/v1.3/build/SFL_inst.vhd Normal file
View File

@@ -0,0 +1,3 @@
SFL_inst : SFL PORT MAP (
noe_in => noe_in_sig
);

27
FPGA/SW700/v1.3/build/Video_Clock.cmp Normal file
View File

@@ -0,0 +1,27 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Video_Clock
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

14
FPGA/SW700/v1.3/build/Video_Clock.ppf Normal file
View File

@@ -0,0 +1,14 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="Video_Clock" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="c3" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

6
FPGA/SW700/v1.3/build/Video_Clock.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock.ppf"]

458
FPGA/SW700/v1.3/build/Video_Clock.vhd Normal file
View File

@@ -0,0 +1,458 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Video_Clock.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Video_Clock IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Video_Clock;
ARCHITECTURE SYN OF video_clock IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "LOW",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 12,
clk0_phase_shift => "0",
clk1_divide_by => 25,
clk1_duty_cycle => 50,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
clk2_divide_by => 25,
clk2_duty_cycle => 50,
clk2_multiply_by => 16,
clk2_phase_shift => "0",
clk3_divide_by => 5,
clk3_duty_cycle => 50,
clk3_multiply_by => 8,
clk3_phase_shift => "0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "120.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "32.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "80.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "16.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "32.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "80.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_Video.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

25
FPGA/SW700/v1.3/build/Video_Clock_II.cmp Normal file
View File

@@ -0,0 +1,25 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Video_Clock_II
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

12
FPGA/SW700/v1.3/build/Video_Clock_II.ppf Normal file
View File

@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="Video_Clock_II" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

6
FPGA/SW700/v1.3/build/Video_Clock_II.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_II.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II.ppf"]

394
FPGA/SW700/v1.3/build/Video_Clock_II.vhd Normal file
View File

@@ -0,0 +1,394 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Video_Clock_II.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Video_Clock_II IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Video_Clock_II;
ARCHITECTURE SYN OF video_clock_ii IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "LOW",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 13,
clk0_phase_shift => "0",
clk1_divide_by => 5000,
clk1_duty_cycle => 50,
clk1_multiply_by => 5051,
clk1_phase_shift => "0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_II",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "130.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.509998"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "130.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.51000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Video_Clock_II.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5000"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5051"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

25
FPGA/SW700/v1.3/build/Video_Clock_III.cmp Normal file
View File

@@ -0,0 +1,25 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Video_Clock_III
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

12
FPGA/SW700/v1.3/build/Video_Clock_III.ppf Normal file
View File

@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="Video_Clock_III" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

6
FPGA/SW700/v1.3/build/Video_Clock_III.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_III.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III.ppf"]

397
FPGA/SW700/v1.3/build/Video_Clock_III.vhd Normal file
View File

@@ -0,0 +1,397 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Video_Clock_III.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Video_Clock_III IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Video_Clock_III;
ARCHITECTURE SYN OF video_clock_iii IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "LOW",
clk0_divide_by => 15625,
clk0_duty_cycle => 50,
clk0_multiply_by => 5542,
clk0_phase_shift => "0",
clk1_divide_by => 15625,
clk1_duty_cycle => 50,
clk1_multiply_by => 11084,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_III",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "17.734400"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "35.468800"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "17.73440000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "35.46880000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Video_Clock_II.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15625"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5542"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11084"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

7
FPGA/SW700/v1.3/build/Video_Clock_III_inst.vhd Normal file
View File

@@ -0,0 +1,7 @@
Video_Clock_III_inst : Video_Clock_III PORT MAP (
areset => areset_sig,
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
locked => locked_sig
);

7
FPGA/SW700/v1.3/build/Video_Clock_II_inst.vhd Normal file
View File

@@ -0,0 +1,7 @@
Video_Clock_II_inst : Video_Clock_II PORT MAP (
areset => areset_sig,
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
locked => locked_sig
);

9
FPGA/SW700/v1.3/build/Video_Clock_inst.vhd Normal file
View File

@@ -0,0 +1,9 @@
Video_Clock_inst : Video_Clock PORT MAP (
areset => areset_sig,
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
c2 => c2_sig,
c3 => c3_sig,
locked => locked_sig
);

30
FPGA/SW700/v1.3/build/coreMZ.qpf Normal file
View File

@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "16:29:32 June 24, 2020"
# Revisions
PROJECT_REVISION = "coreMZ"

312
FPGA/SW700/v1.3/build/coreMZ.qsf Normal file
View File

@@ -0,0 +1,312 @@
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# coreMZ_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
#set_global_assignment -name DEVICE EP4CE115F23I7
set_global_assignment -name DEVICE EP4CE75F23I7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY coreMZ
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
# Clocks.
# =======
set_location_assignment PIN_T21 -to CLOCK_50
set_location_assignment PIN_T22 -to CLOCK_50_2
set_location_assignment PIN_T2 -to CTLCLK
set_location_assignment PIN_T1 -to SYSCLK
set_location_assignment PIN_U1 -to VZ80_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CTL_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SYS_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_CLK
# Video Interface/Soft CPU Address Bus
# ====================================
set_location_assignment PIN_AB10 -to VZ80_ADDR[15]
set_location_assignment PIN_AA10 -to VZ80_ADDR[14]
set_location_assignment PIN_AB9 -to VZ80_ADDR[13]
set_location_assignment PIN_AA9 -to VZ80_ADDR[12]
set_location_assignment PIN_AB8 -to VZ80_ADDR[11]
set_location_assignment PIN_AA8 -to VZ80_ADDR[10]
set_location_assignment PIN_AB7 -to VZ80_ADDR[9]
set_location_assignment PIN_AA7 -to VZ80_ADDR[8]
set_location_assignment PIN_AB6 -to VZ80_ADDR[7]
set_location_assignment PIN_AA6 -to VZ80_ADDR[6]
set_location_assignment PIN_AB5 -to VZ80_ADDR[5]
set_location_assignment PIN_AA5 -to VZ80_ADDR[4]
set_location_assignment PIN_AA4 -to VZ80_ADDR[3]
set_location_assignment PIN_AA1 -to VZ80_ADDR[2]
set_location_assignment PIN_Y2 -to VZ80_ADDR[1]
set_location_assignment PIN_Y1 -to VZ80_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[0]
# Video/Soft CPU Data Bus
# =======================
set_location_assignment PIN_AB16 -to VZ80_DATA[7]
set_location_assignment PIN_AA16 -to VZ80_DATA[6]
set_location_assignment PIN_AB15 -to VZ80_DATA[5]
set_location_assignment PIN_AA15 -to VZ80_DATA[4]
set_location_assignment PIN_AB14 -to VZ80_DATA[3]
set_location_assignment PIN_AA14 -to VZ80_DATA[2]
set_location_assignment PIN_AB13 -to VZ80_DATA[1]
set_location_assignment PIN_AA13 -to VZ80_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[0]
# Video/Soft CPU control signals.
# ===============================
set_location_assignment PIN_W1 -to VIDEO_RDn
set_location_assignment PIN_V1 -to VIDEO_WRn
set_location_assignment PIN_V2 -to VZ80_IORQn
set_location_assignment PIN_C1 -to VZ80_MREQn
set_location_assignment PIN_R2 -to VZ80_M1n
set_location_assignment PIN_F1 -to VZ80_RDn
set_location_assignment PIN_H1 -to VZ80_WRn
set_location_assignment PIN_J1 -to VZ80_BUSACKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_MREQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_M1n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSACKn
# Composite video multiplexed with Soft CPU input signals.
# ========================================================
set_location_assignment PIN_R1 -to VWAITn_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_HALTn_V_VSYNCn
set_location_assignment PIN_N1 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_N2 -to VZ80_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_HALTn_V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSRn_V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_NMIn_V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
set_location_assignment PIN_A20 -to COLR_OUT
set_location_assignment PIN_A14 -to CSYNC_OUTn
set_location_assignment PIN_A13 -to CSYNC_OUT
set_location_assignment PIN_A9 -to VSYNC_OUTn
set_location_assignment PIN_A10 -to HSYNC_OUTn
set_location_assignment PIN_H22 -to VGA_R[0]
set_location_assignment PIN_J22 -to VGA_R[1]
set_location_assignment PIN_K22 -to VGA_R[2]
set_location_assignment PIN_L22 -to VGA_R[3]
set_location_assignment PIN_M22 -to VGA_R_COMPOSITE
set_location_assignment PIN_A15 -to VGA_G[0]
set_location_assignment PIN_A16 -to VGA_G[1]
set_location_assignment PIN_A17 -to VGA_G[2]
set_location_assignment PIN_A18 -to VGA_G[3]
set_location_assignment PIN_A19 -to VGA_G_COMPOSITE
set_location_assignment PIN_B22 -to VGA_B[0]
set_location_assignment PIN_C22 -to VGA_B[1]
set_location_assignment PIN_D22 -to VGA_B[2]
set_location_assignment PIN_E22 -to VGA_B[3]
set_location_assignment PIN_F22 -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to COLR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
# Files in project.
# =================
set_global_assignment -name VHDL_FILE ../coreMZ.vhd
#set_global_assignment -name QIP_FILE Clock_50to100.qip
set_global_assignment -name QIP_FILE SFL_IV.qip
set_global_assignment -name QIP_FILE Video_Clock.qip
set_global_assignment -name QIP_FILE Video_Clock_II.qip
set_global_assignment -name QIP_FILE Video_Clock_III.qip
set_global_assignment -name VHDL_FILE ../coreMZ_pkg.vhd
set_global_assignment -name VHDL_FILE ../VideoController.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
set_global_assignment -name SDC_FILE coreMZ_constraints.sdc
# Latest T80 CPU
# ==============
set_global_assignment -name VHDL_FILE ../softT80.vhd
set_global_assignment -name VHDL_FILE ../T80/T80.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE ../T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE ../T80/T80a.vhd
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name VHDL_FILE ../softZPU.vhd
set_global_assignment -name VHDL_FILE ../softZPU_pkg.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_core_evo.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_core_evo_L2.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_uart_debug.vhd
set_global_assignment -name VHDL_FILE ../ZPU/zpu_pkg.vhd
#set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/TZSW_DualPortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/TZSW_SinglePortBRAM.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

281
FPGA/SW700/v1.3/build/coreMZ_constraints.sdc Normal file
View File

@@ -0,0 +1,281 @@
## Generated SDC file "VideoController700_constraints.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {VZ80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {VZ80_CLK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
create_generated_clock -name {SYS_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_8MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_16MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
create_generated_clock -name {VIDCLK_40MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
create_generated_clock -name {VIDCLK_65MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 5 -phase 0.00 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_25_175MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 91 -divide_by 90 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {VIDCLK_8_86719MHZ} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 324 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {VIDCLK_17_7344MHZ} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 162 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[1]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
set_input_delay -add_delay -clock [get_clocks {VZ80_CLK}] 1.000 [get_ports {VZ80_CLK}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VIDEO_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VIDEO_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_M1n}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_ADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[0]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[1]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[2]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[3]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[4]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[5]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[6]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[7]}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VWAITn_V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_RFSHn_V_HSYNCn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_HALTn_V_VSYNCn}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_BUSRQn_V_G}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_WAITn_V_B}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_INTn_V_R}]
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VZ80_NMIn_V_COLR}]
# Required for the Serial Flash Loader.
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tck}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tms}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[4]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[5]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[6]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_DATA[7]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_WRn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RDn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_IORQn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_M1n}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VWAITn_V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RFSHn_V_HSYNCn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_HALTn_V_VSYNCn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[0]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[1]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[2]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[3]}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {HSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {COLR_OUT}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC_OUT}]
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC_OUTn}]
# Required for the Serial Flash Loader.
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
# There is no relationship between the different video frequencies, only one is used at a time and they are switched through synchronised D-Type flip flops.
set_false_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
set_false_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VZ80_CLK}]
# Z80 clock has no relationship to the video frequencies, it is used only for latching data asynchronous to the FPGA clocks.
set_false_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# The system clock has no real relationship with the video frequencies, rendering and display. The only place they meet is in the dual port BRAM.
set_false_path -from [get_clocks {SYS_CLK}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# Clock 50MHZ, the input oscillator is only used for the PLL input and as I/O input/output latch which is detached from the video block
set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
# The Z80 data, address and control lines do not go to the video block (except the parameter update which is not critical) so set it as a false path so as not to consider.
set_false_path -from [get_ports {VZ80_DATA[*]}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
set_false_path -from [get_ports {VZ80_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}]
set_false_path -from [get_ports {VZ80_WRn VZ80_RDn VZ80_IORQn}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|DSP_PARAM_SEL[*]}] -to [get_ports {VZ80_DATA[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|DSP_PARAM_SEL[*]}] -to [get_ports {VZ80_DATA[*]}] -setup -start 2
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VZ80_CLK}] -hold -start 1
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {VZ80_CLK}] -setup -start 2
set_multicycle_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {SYS_CLK}] -hold -start 2
set_multicycle_path -from [get_clocks {VZ80_CLK}] -to [get_clocks {SYS_CLK}] -setup -start 3
# GPU control and run variables have at least 1 clock between them being setup and used.
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -setup -start 2
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|GRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|\GPU:GPU_VAR_Y[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_STATE.*}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|GPU_START_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcCoreVideo|VRAM_GPU_ADDR[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_MAPPED_DATA[*]}] -hold -start 1
set_multicycle_path -from [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcCoreVideo|XFER_DST_ADDR[*]}] -hold -start 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

29
FPGA/SW700/v1.3/build/vbuffer.cmp Normal file
View File

@@ -0,0 +1,29 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component vbuffer
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
end component;

5
FPGA/SW700/v1.3/build/vbuffer.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "vbuffer.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vbuffer_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vbuffer.cmp"]

204
FPGA/SW700/v1.3/build/vbuffer.vhd Normal file
View File

@@ -0,0 +1,204 @@
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: vbuffer.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY vbuffer IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END vbuffer;
ARCHITECTURE SYN OF vbuffer IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(7 DOWNTO 0);
rdempty <= sub_wire2;
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 8192,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 13,
overflow_checking => "OFF",
rdsync_delaypipe => 3,
read_aclr_synch => "OFF",
underflow_checking => "OFF",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 3
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "4096"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

11
FPGA/SW700/v1.3/build/vbuffer_inst.vhd Normal file
View File

@@ -0,0 +1,11 @@
vbuffer_inst : vbuffer PORT MAP (
aclr => aclr_sig,
data => data_sig,
rdclk => rdclk_sig,
rdreq => rdreq_sig,
wrclk => wrclk_sig,
wrreq => wrreq_sig,
q => q_sig,
rdempty => rdempty_sig,
wrfull => wrfull_sig
);

709
FPGA/SW700/v1.3/coreMZ.vhd Normal file
View File

@@ -0,0 +1,709 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: coreMZ.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ Series FPGA core.
--
-- This module provides a Sharp MZ series computer with Video and Soft CPU enhancements.
-- Initially written for the Sharp MZ-700 on the SW700 v1.3 board and will be migrated
-- to the pure FPGA tranZPUter v2.1 baord.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Oct 2020 - Split off from the Sharp MZ80A Video Module, the Video Module for the
-- Sharp MZ700 has the same roots but different control functionality. The
-- MZ700 version resides within the tranZPUter memory and not the mainboard
-- allowing for generally easier control. The MZ80A and MZ700 graphics logic
-- should be pretty much identical.
-- Nov 2020 - Split off from v1.2 VideoController700 module. With the advent of v1.3
-- with it's much larger FPGA, it is now possible to add Soft CPU's in
-- addition to the Video Controller logic. This required a restructuring
-- of the VHDL to seperate the Video from the Soft CPUs.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.coreMZ_pkg.all;
--use work.zpu_pkg.all;
use altera.altera_syn_attributes.all;
entity coreMZ is
port (
-- Primary and video clocks.
CLOCK_50 : in std_logic; -- 50MHz base clock for video timing and gate clocking.
CTLCLK : in std_logic; -- tranZPUter external clock (for overclocking).
SYSCLK : in std_logic; -- Mainboard system clock.
VZ80_CLK : in std_logic; -- Z80 clock combining SYSCLK and CTLCLK.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Address Bus
VZ80_ADDR : inout std_logic_vector(15 downto 0); -- Z80 Address bus.
-- Data Bus
VZ80_DATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus.
-- Control signals.
VZ80_MREQn : inout std_logic; -- Z80 MREQ Out from Soft CPU.
VZ80_IORQn : inout std_logic; -- Z80 IORQ In from Hard Z80/Out from Soft CPU.
VZ80_RDn : inout std_logic; -- Z80 RDn In from Hard Z80/Out from Soft CPU.
VZ80_WRn : inout std_logic; -- Z80 WRn In from Hard Z80/Out from Soft CPU.
VZ80_M1n : inout std_logic; -- Z80 M1 Out from Soft CPU.
VZ80_BUSACKn : out std_logic; -- Z80 BUSACK Out from Soft CPU.
VIDEO_RDn : in std_logic; -- Decoded Video Controller Read from CPLD memory manager.
VIDEO_WRn : in std_logic; -- Decoded Video Controller Write from CPLD memory manager.
-- VGA & Composite output signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
VGA_G : out std_logic_vector(3 downto 0); -- 16 level Green output.
VGA_B : out std_logic_vector(3 downto 0); -- 16 level Blue output.
VGA_R_COMPOSITE : inout std_logic; -- RGB Red override for composite output.
VGA_G_COMPOSITE : inout std_logic; -- RGB Green override for composite output.
VGA_B_COMPOSITE : inout std_logic; -- RGB Blue override for composite output.
HSYNC_OUTn : out std_logic; -- Horizontal sync.
VSYNC_OUTn : out std_logic; -- Vertical sync.
COLR_OUT : out std_logic; -- Composite and RF base frequency.
CSYNC_OUTn : out std_logic; -- Composite sync (negative).
CSYNC_OUT : out std_logic; -- Composite sync (positive).
-- RGB & Composite input signals.
VWAITn_V_CSYNC : inout std_logic; -- Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
VZ80_RFSHn_V_HSYNCn : inout std_logic; -- Soft CPU RFSH out / Horizontal sync (negative) from mainboard.
VZ80_HALTn_V_VSYNCn : inout std_logic; -- Soft CPU HALT out / Video memory selected / Vertical sync (negative) from mainboard.
VZ80_NMIn_V_COLR : in std_logic; -- Soft CPU NMIn in / Composite and RF base frequency from mainboard.
VZ80_BUSRQn_V_G : in std_logic; -- Soft CPU BUSRQn in / Digital Green (on/off) from mainboard.
VZ80_WAITn_V_B : in std_logic; -- Soft CPU WAITn in / Digital Blue (on/off) from mainboard.
VZ80_INTn_V_R : in std_logic -- Soft CPU INTn in / Digital Red (on/off) from mainboard.
);
END entity;
architecture rtl of coreMZ is
signal SYS_CLK : std_logic;
signal VIDCLK_8MHZ : std_logic;
signal VIDCLK_16MHZ : std_logic;
signal VIDCLK_25_175MHZ : std_logic;
signal VIDCLK_40MHZ : std_logic;
signal VIDCLK_65MHZ : std_logic;
signal VIDCLK_8_86719MHZ : std_logic;
signal VIDCLK_17_7344MHZ : std_logic;
signal PLL_LOCKED : std_logic;
signal PLL_LOCKED2 : std_logic;
signal PLL_LOCKED3 : std_logic;
signal RESETn : std_logic := '0';
signal RESET_COUNTER : unsigned(3 downto 0) := (others => '1');
signal MODE_CPLD_VIDEO_WAIT : std_logic; -- FPGA video display period wait flag, 1 = enabled, 0 = disabled.
signal CPU_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPU Configuration register.
signal CPU_INFO_DATA : std_logic_vector(7 downto 0); -- CPU configuration information register.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD configuration register.
signal MODE_CPLD_SWITCH : std_logic := '1'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the machine mode has changed. Flag is active for 1 clock cycle.
signal MODE_CPU_CHANGED : std_logic; -- Flag to indicate the CPU has been changed.
signal MODE_CPU_SOFT : std_logic; -- Control signal to enable the Soft CPU and support logic.
signal MODE_CPLD_MB_VIDEOn : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the mainboard video logic is enabled, disabling or blending with the FPGA graphics.
signal CS_IO_6XXn : std_logic; -- Chip select for CPLD configuration registers.
signal CS_CPU_CFGn : std_logic; -- Select to set the CPU configuration register.
signal CS_CPU_INFOn : std_logic; -- Select to read the CPU information register.
signal CS_CPLD_CFGn : std_logic; -- Chip Select to write to the CPLD configuration register at 0x6E.
-- T80
--
signal T80_MREQn : std_logic;
signal T80_BUSRQn : std_logic;
signal T80_IORQn : std_logic;
signal T80_WRn : std_logic;
signal T80_RDn : std_logic;
signal T80_WAITn : std_logic;
signal T80_M1n : std_logic;
signal T80_RFSHn : std_logic;
signal T80_ADDR : std_logic_vector(15 downto 0);
signal T80_INTn : std_logic;
signal T80_DATA_IN : std_logic_vector(7 downto 0);
signal T80_DATA_OUT : std_logic_vector(7 downto 0);
signal T80_BUSACKn : std_logic;
signal T80_NMIn : std_logic;
signal T80_HALTn : std_logic;
-- ZPU
signal ZPU_MREQn : std_logic;
signal ZPU_BUSRQn : std_logic;
signal ZPU_IORQn : std_logic;
signal ZPU_WRn : std_logic;
signal ZPU_RDn : std_logic;
signal ZPU_WAITn : std_logic;
signal ZPU_M1n : std_logic;
signal ZPU_RFSHn : std_logic;
signal ZPU_VIDEO_WRn : std_logic;
signal ZPU_VIDEO_RDn : std_logic;
signal ZPU_ADDR : std_logic_vector(15 downto 0);
signal ZPU_VIDEO_ADDR : std_logic_vector(2 downto 0);
signal ZPU_INTn : std_logic;
signal ZPU_DATA_IN : std_logic_vector(7 downto 0);
signal ZPU_DATA_OUT : std_logic_vector(7 downto 0);
signal ZPU_BUSACKn : std_logic;
signal ZPU_NMIn : std_logic;
signal ZPU_HALTn : std_logic;
-- Internal core signals, muxed or demuxed physical connections.
--
signal CORE_MREQn : std_logic; --
signal CORE_IORQn : std_logic; --
signal CORE_RDn : std_logic; --
signal CORE_WRn : std_logic; --
signal CORE_M1n : std_logic; --
signal CORE_RFSHn : std_logic; --
signal CORE_HALTn : std_logic; --
signal CORE_RESETn : std_logic;
signal CORE_VIDEO_WRn : std_logic; -- FPGA video write. Normally from the CPLD memory manager but overriden by soft CPU's such as the ZPU.
signal CORE_VIDEO_RDn : std_logic; -- FPGA video read. Normally from the CPLD memory manager but overriden by soft CPU's such as the ZPU.
signal CORE_ADDR : std_logic_vector(15 downto 0); --
signal CORE_VIDEO_ADDR : std_logic_vector(2 downto 0); --
signal CORE_DATA_OUT : std_logic_vector(7 downto 0); --
signal CORE_DATA_IN : std_logic_vector(7 downto 0); --
signal CORE_V_HSYNCn : std_logic; --
signal CORE_V_VSYNCn : std_logic; --
signal CORE_V_COLR : std_logic; --
signal CORE_V_R : std_logic; --
signal CORE_V_G : std_logic; --
signal CORE_V_B : std_logic; --
begin
-- Instantiate a PLL to generate the system clock and base video clocks.
--
VCPLL1 : entity work.Video_Clock
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => SYS_CLK,
c1 => VIDCLK_8MHZ,
c2 => VIDCLK_16MHZ,
c3 => VIDCLK_40MHZ,
locked => PLL_LOCKED
);
-- Instantiate a 2nd PLL to generate additional video clocks for VGA and Sharp MZ700 modes.
VCPLL2 : entity work.Video_Clock_II
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => VIDCLK_65MHZ,
c1 => VIDCLK_25_175MHZ,
locked => PLL_LOCKED2
);
-- Instantiate a 3rd PLL to generate clock for pseudo monochrome generation on internal monitor.
VCPLL3 : entity work.Video_Clock_III
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => VIDCLK_8_86719MHZ,
c1 => VIDCLK_17_7344MHZ,
locked => PLL_LOCKED3
);
-- Add the Serial Flash Loader megafunction to enable in-situ programming of the EPCS16 configuration memory.
--
SFL : entity work.sfl_iv
port map
(
noe_in => '0'
);
-- Process to reset the FPGA based on the external RESET trigger, PLL's being locked
-- and a counter to set minimum width.
--
FPGARESET: process(CLOCK_50, PLL_LOCKED, PLL_LOCKED2, PLL_LOCKED3)
begin
if PLL_LOCKED = '0' or PLL_LOCKED2 = '0' or PLL_LOCKED3 = '0' then
RESET_COUNTER <= (others => '1');
RESETn <= '0';
elsif PLL_LOCKED = '1' and PLL_LOCKED2 = '1' and PLL_LOCKED3 = '1' then
if rising_edge(CLOCK_50) then
if RESET_COUNTER /= 0 then
RESET_COUNTER <= RESET_COUNTER - 1;
elsif VIDEO_WRn = '0' and VIDEO_RDn = '0' then
RESETn <= '0';
elsif VIDEO_WRn = '1' or VIDEO_RDn = '1' then
RESETn <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------
-- Video Controller
------------------------------------------------------------------------------------
vcCoreVideo : entity work.VideoController
--generic map
--(
--)
port map
(
-- Primary and video clocks.
SYS_CLK => SYS_CLK, -- 120MHz main FPGA clock.
VZ80_CLK => VZ80_CLK, -- Z80 runtime clock (product of SYSCLK and CTLCLK - variable frequency).
VIDCLK_8MHZ => VIDCLK_8MHZ, -- 2x 8MHz base clock for video timing and gate clocking.
VIDCLK_16MHZ => VIDCLK_16MHZ, -- 2x 16MHz base clock for video timing and gate clocking.
VIDCLK_65MHZ => VIDCLK_65MHZ, -- 2x 65MHz base clock for video timing and gate clocking.
VIDCLK_25_175MHZ => VIDCLK_25_175MHZ, -- 2x 25.175MHz base clock for video timing and gate clocking.
VIDCLK_40MHZ => VIDCLK_40MHZ, -- 2x 40MHz base clock for video timing and gate clocking.
VIDCLK_8_86719MHZ => VIDCLK_8_86719MHZ, -- 2x original MZ700 video clock.
VIDCLK_17_7344MHZ => VIDCLK_17_7344MHZ, -- 2x original MZ700 colour modulator clock.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Address Bus
VIDEO_ADDR => CORE_ADDR, -- Z80 Address bus.
-- Direct addressing Bus. Normally this is set to 0 during standard Sharp MZ operation, when > 0 then direct addressing of the various video
-- memory's is required.
-- 000 - Normal
-- 001 - Video RAM..
-- 010 - Attribute RAM.
-- 011 - Character Generator RAM
-- 100 - Red framebuffer.
-- 101 - Blue framebuffer.
-- 110 - Green framebuffer.
VIDEO_HI_ADDR => CORE_VIDEO_ADDR, -- Direct Addressing bus.
-- Data Bus
VIDEO_DATA_IN => CORE_DATA_IN, -- Z80 Data bus from CPU into video module.
VIDEO_DATA_OUT => CORE_DATA_OUT, -- Z80 Data bus from video module to CPU.
-- Control signals.
VIDEO_IORQn => CORE_IORQn, -- IORQ signal, active low. When high, request is to memory.
VIDEO_RDn => CORE_VIDEO_RDn, -- Decoded Video Controller Read from CPLD memory manager.
VIDEO_WRn => CORE_VIDEO_WRn, -- Decoded Video Controller Write from CPLD memory manager.
-- VGA & Composite output signals.
VGA_R => VGA_R, -- 16 level Red output.
VGA_G => VGA_G, -- 16 level Green output.
VGA_B => VGA_B, -- 16 level Blue output.
VGA_R_COMPOSITE => VGA_R_COMPOSITE, -- RGB Red override for composite output.
VGA_G_COMPOSITE => VGA_G_COMPOSITE, -- RGB Green override for composite output.
VGA_B_COMPOSITE => VGA_B_COMPOSITE, -- RGB Blue override for composite output.
HSYNC_OUTn => HSYNC_OUTn, -- Horizontal sync.
VSYNC_OUTn => VSYNC_OUTn, -- Vertical sync.
COLR_OUT => COLR_OUT, -- Composite and RF base frequency.
CSYNC_OUTn => CSYNC_OUTn, -- Composite sync (negative).
CSYNC_OUT => CSYNC_OUT, -- Composite sync (positive).
-- RGB & Composite input signals.
VWAITn_V_CSYNC => VWAITn_V_CSYNC, -- Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
V_HSYNCn => CORE_V_HSYNCn, -- Horizontal sync (negative) from mainboard.
V_VSYNCn => CORE_V_VSYNCn, -- Vertical sync (negative) from mainboard.
V_COLR => CORE_V_COLR, -- Soft CPU NMIn / Composite and RF base frequency from mainboard.
V_G => CORE_V_G, -- Soft CPU BUSRQn / Digital Green (on/off) from mainboard.
V_B => CORE_V_B, -- Soft CPU WAITn / Digital Blue (on/off) from mainboard.
V_R => CORE_V_R, -- Soft CPU INTn / Digital Red (on/off) from mainboard.
-- Reset.
VRESETn => CORE_RESETn, -- Internal reset.
-- Configuration.
CPLD_CFG_DATA => CPLD_CFG_DATA, -- CPLD internal settings register.
MB_VIDEO_ENABLEn => MODE_CPLD_MB_VIDEOn -- Mainboard video enabled (=0) or FPGA advanced video (=1).
);
------------------------------------------------------------------------------------
-- T80 CPU
------------------------------------------------------------------------------------
CPU0 : entity work.softT80
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
SYS_CLK => SYS_CLK, -- System logic clock ~120MHz
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => CPU_CFG_DATA(7), -- Software controlled reset.
SW_ENABLE => MODE_CPU_SOFT, -- Software controlled CPU enable.
CPU_CHANGED => MODE_CPU_CHANGED, -- Flag to indicate when software selects a different CPU.
-- Core Sharp MZ signals.
T80_WAITn => T80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
T80_INTn => T80_INTn, -- INTn signal for maskable interrupts.
T80_NMIn => T80_NMIn, -- NMIn non maskable interrupt input.
T80_BUSRQn => T80_BUSRQn, -- BUSRQn signal to request CPU go into tristate and relinquish bus.
T80_M1n => T80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
T80_MREQn => T80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
T80_IORQn => T80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
T80_RDn => T80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
T80_WRn => T80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
T80_RFSHn => T80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
T80_HALTn => T80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
T80_BUSACKn => T80_BUSACKn, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
T80_ADDR => T80_ADDR, -- 16 bit address lines.
T80_DATA_IN => T80_DATA_IN, -- 8 bit data bus in.
T80_DATA_OUT => T80_DATA_OUT -- 8 bit data bus out.
);
------------------------------------------------------------------------------------
-- ZPU Evolution CPU
------------------------------------------------------------------------------------
CPU1 : entity work.softZPU
generic map (
SYSCLK_FREQUENCY => 50000000 -- Speed of clock used for the ZPU.
)
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
SYS_CLK => SYS_CLK, -- System logic clock ~120MHz
ZPU_CLK => CLOCK_50, -- ZPU clock.
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => CPU_CFG_DATA(7), -- Software controlled reset.
SW_ENABLE => MODE_CPU_SOFT, -- Software controlled CPU enable.
CPU_CHANGED => MODE_CPU_CHANGED, -- Flag to indicate when software selects a different CPU.
VIDEO_WRn => ZPU_VIDEO_WRn, -- Direct video write from ZPU, bypass CPLD memory manager.
VIDEO_RDn => ZPU_VIDEO_RDn, -- Direct video read from ZPU, bypass CPLD memory manager.
VIDEO_DIRECT_ADDR => ZPU_VIDEO_ADDR, -- Direct addressing of video memory (bypassing register configuration needed by Sharp MZ host to maintain compatibility or address space restrictions).
-- Core Sharp MZ signals.
ZPU_WAITn => ZPU_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
ZPU_INTn => ZPU_INTn, -- INTn signal for maskable interrupts.
ZPU_NMIn => ZPU_NMIn, -- NMIn non maskable interrupt input.
ZPU_BUSRQn => ZPU_BUSRQn, -- BUSRQn signal to request CPU go into tristate and relinquish bus.
ZPU_M1n => ZPU_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
ZPU_MREQn => ZPU_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
ZPU_IORQn => ZPU_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
ZPU_RDn => ZPU_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
ZPU_WRn => ZPU_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
ZPU_RFSHn => ZPU_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
ZPU_HALTn => ZPU_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
ZPU_BUSACKn => ZPU_BUSACKn, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
ZPU_ADDR => ZPU_ADDR, -- 16 bit address lines.
ZPU_DATA_IN => ZPU_DATA_IN, -- 8 bit data bus in.
ZPU_DATA_OUT => ZPU_DATA_OUT -- 8 bit data bus out.
);
------------------------------------------------------------------------------------
-- Core Logic
------------------------------------------------------------------------------------
-- Common Control Registers
--
--
CTRLREGISTERS: process( RESETn, VZ80_CLK, CS_CPU_CFGn, CS_CPLD_CFGn, VZ80_WRn, VZ80_RDn )
variable CPU_CHANGED : unsigned(3 downto 0); -- Flag to indicate the CPU has been changed.
begin
-- Ensure default values at reset.
if RESETn='0' then
MODE_CPLD_SWITCH <= '0';
CPLD_CFG_DATA <= "00000100";
CPU_CFG_DATA(7 downto 6) <= "00"; -- Dont reset soft CPU selection flag on a reset.
CPU_CHANGED := (others => '0');
elsif rising_edge(VZ80_CLK) then
-- CPLD/CPU Configuration registers.
--
-- CPU:
-- Version 1.3-> of the tranZPUter SW-700 provides the ability to instantiate alternative soft CPU's. This register configures the FPGA to enable a soft/hard CPU and the CPLD
-- is reconfigured to allow a CPU operation on the FPGA side rather than the physical hardware side.
--
-- [5:0] - R/W - CPU selection.
-- 000000 = Hard CPU
-- 000001 = T80 CPU
-- 000010 = ZPU Evolution
-- 000100 = Future CPU AAA
-- 001000 = Future CPU AAA
-- 010000 = Future CPU AAA
-- 100000 = Future CPU AAA
-- All other configurations reserved and default to Hard CPU.
-- [7] - R/W - CPU Reset. When active ('1'), hold the CPU in reset, when inactive, commence the reset completion and CPU run.
--
-- CPLD:
-- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used
-- by host software such as RFS.
--
-- [2:0] - R/W - Mode/emulated machine.
-- 000 = MZ-80K
-- 001 = MZ-80C
-- 010 = MZ-1200
-- 011 = MZ-80A
-- 100 = MZ-700
-- 101 = MZ-800
-- 110 = MZ-80B
-- 111 = MZ-2000
-- [3] - R/W - Mainboard Video - 0 = Enable, 1 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions
-- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality.
-- [4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
-- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there
-- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator.
--
if(CS_CPU_CFGn = '0' and VZ80_WRn = '0') then
-- Store the new value into the register, used for read operations.
CPU_CFG_DATA <= VZ80_DATA;
-- Check to ensure only one CPU selected, if more than one default to hard CPU. Also check to ensure only instantiated CPU's selected, otherwise default to hard CPU.
--
if (unsigned(VZ80_DATA(5 downto 0)) and (unsigned(VZ80_DATA(5 downto 0))-1)) /= 0 or (VZ80_DATA(5 downto 2) and "1111") /= "0000" then
CPU_CFG_DATA(5 downto 0) <= (others => '0');
end if;
-- If the CPU bit has changed, raise the flag to force a reset.
CPU_CHANGED(0) := '1';
elsif(CS_CPLD_CFGn = '0' and VZ80_WRn = '0') then
-- Set the mode switch event flag if the mode changes.
if CPLD_CFG_DATA(2 downto 0) /= VZ80_DATA(2 downto 0) then
MODE_CPLD_SWITCH <= '1';
end if;
-- Store the new value into the register, used for read operations.
CPLD_CFG_DATA <= VZ80_DATA;
else
MODE_CPLD_SWITCH <= '0';
CPU_CHANGED := CPU_CHANGED(2 downto 0) & '0';
end if;
end if;
-- Flag to indicate when a soft CPU has been changed.
if CPU_CHANGED /= 0 then
MODE_CPU_CHANGED <= '1';
else
MODE_CPU_CHANGED <= '0';
end if;
end process;
-- CPU information register.
-- [5:0] - R/O - CPU Availability.
-- 000000 = Hard CPU
-- 000001 = T80 CPU
-- 000010 = ZPU Evolution
-- 000100 = Future CPU AAA
-- 001000 = Future CPU AAA
-- 010000 = Future CPU AAA
-- 100000 = Future CPU AAA
-- [7:6] - R/O - Soft CPU capable, 01 = capable, /01 = not capable (value to cater for non-FPGA reads which return 11 or 00).
--
CPU_INFO_DATA <= "01" & "000011";
-- CPLD configuration register range.
CS_IO_6XXn <= '0' when CORE_IORQn = '0' and CORE_ADDR(7 downto 4) = "0110"
else '1';
-- CPU configuration register range within the FPGA. These registers select and control the soft/hard CPU and parameters.
CS_CPU_CFGn <= '0' when CS_IO_6XXn = '0' and CORE_ADDR(3 downto 0) = "1100" -- IO 6C
else '1';
CS_CPU_INFOn <= '0' when CS_IO_6XXn = '0' and CORE_ADDR(3 downto 0) = "1101" -- IO 6D
else '1';
-- CPLD mirrored logic. Registers on the CPLD which need to be known by the FPGA are duplicated within the FPGA.
CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and CORE_ADDR(3 downto 0) = "1110" -- IO 6E - CPLD configuration register.
else '1';
-- Set the mainboard video state, 0 = enabled, 1 = disabled. Signal set to enabled if the soft cpu is enabled.
MODE_CPLD_MB_VIDEOn <= '1' when CPLD_CFG_DATA(3) = '1' or CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Flag to indicate Soft CPU is running,
MODE_CPU_SOFT <= '1' when CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Mux the main Z80 control signals for internal use, either use the hard Z80 on the tranZPUter or the soft CPU in the FPGA.
--
CORE_MREQn <= VZ80_MREQn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
T80_MREQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_MREQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else '1';
CORE_IORQn <= VZ80_IORQn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
T80_IORQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_IORQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else '1';
CORE_RDn <= VZ80_RDn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
T80_RDn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_RDn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else '1';
CORE_WRn <= VZ80_WRn when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
T80_WRn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_WRn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else '1';
CORE_M1n <= VZ80_M1n when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
T80_M1n when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_M1n when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else '1';
CORE_RFSHn <= VZ80_RFSHn_V_HSYNCn when MODE_CPU_SOFT = '1' or MODE_CPLD_MB_VIDEOn = '1'
else
T80_RFSHn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_RFSHn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else '1';
CORE_HALTn <= VZ80_HALTn_V_VSYNCn when MODE_CPU_SOFT = '1' or MODE_CPLD_MB_VIDEOn = '1'
else
T80_HALTn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_HALTn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else '1';
CORE_VIDEO_WRn <= ZPU_VIDEO_WRn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else
VIDEO_WRn;
CORE_VIDEO_RDn <= ZPU_VIDEO_RDn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else
VIDEO_RDn;
-- Address lines driven according to the CPU being used. Hard CPU = address via CPLD, Soft CPU = address direct.
CORE_ADDR <= VZ80_ADDR when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
T80_ADDR when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_ADDR when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else (others => '0');
-- Direct addressing of video memory devices for soft CPU's.
CORE_VIDEO_ADDR <= (others => '0') when CPU_CFG_DATA(1) = '0' or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
ZPU_VIDEO_ADDR;
-- Data into the core, generally the Video Controller, comes from the CPLD (hard CPU or mainboard) if the soft CPU is disabled else from the soft CPU.
CORE_DATA_IN <= VZ80_DATA when MODE_CPU_SOFT = '0' or (CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '0') or (CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '0')
else
T80_DATA_OUT when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_DATA_OUT when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else (others => '0');
-- tranZPUter, hard CPU or mainboard data input. Read directly from the Video Controller if selected, else the data being output from the soft CPU if enabled otherwise
-- tri-state as data is coming from the CPLD.
VZ80_DATA <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and VZ80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and VZ80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when VIDEO_RDn = '0'
else
T80_DATA_OUT when CPU_CFG_DATA(0) = '1' and T80_WRn = '0' and T80_BUSACKn = '1'
else
ZPU_DATA_OUT when CPU_CFG_DATA(1) = '1' and ZPU_WRn = '0' and ZPU_BUSACKn = '1'
else
ZPU_DATA_OUT when CPU_CFG_DATA(1) = '1' and ZPU_MREQn = '0' and ZPU_IORQn = '0' and ZPU_BUSACKn = '1'
else (others => 'Z');
-- Soft CPU data input. Read directly from the Video Controller if selected, at all other times read from the CPLD which in turn reads from the tranZPUter or mainboard.
T80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when VIDEO_RDn = '0'
else
VZ80_DATA when CPU_CFG_DATA(0) = '1' and T80_RDn = '0'
else (others => '0');
ZPU_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and ZPU_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and ZPU_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT when VIDEO_RDn = '0'
else
VZ80_DATA when CPU_CFG_DATA(1) = '1' and ZPU_RDn = '0'
else (others => '0');
-- Direct routed signals to the T80 when not using mainboard video.
T80_INTn <= VZ80_INTn_V_R when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_NMIn <= VZ80_NMIn_V_COLR when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_BUSRQn <= VZ80_BUSRQn_V_G when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_WAITn <= VZ80_WAITn_V_B when CPU_CFG_DATA(0) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
-- Direct routed signals to the ZPU when not using mainboard video.
ZPU_INTn <= VZ80_INTn_V_R when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
ZPU_NMIn <= VZ80_NMIn_V_COLR when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
ZPU_BUSRQn <= VZ80_BUSRQn_V_G when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
ZPU_WAITn <= VZ80_WAITn_V_B when CPU_CFG_DATA(1) = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
-- Internal reset dependent on external reset or a change of the SOFT CPU.
CORE_RESETn <= '0' when RESETn = '0'
else '1';
-- Tri-state controls. If the hard Z80 is being used then tri-state output signals.
VZ80_MREQn <= T80_MREQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_MREQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else 'Z';
VZ80_IORQn <= T80_IORQn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_IORQn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else 'Z';
VZ80_RDn <= T80_RDn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_RDn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else 'Z';
VZ80_WRn <= T80_WRn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_WRn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else 'Z';
VZ80_M1n <= T80_M1n when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_M1n when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else 'Z';
VZ80_RFSHn_V_HSYNCn <= T80_RFSHn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_RFSHn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else 'Z';
VZ80_HALTn_V_VSYNCn <= T80_HALTn when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_HALTn when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else 'Z';
VZ80_ADDR <= T80_ADDR when CPU_CFG_DATA(0) = '1' and T80_BUSACKn = '1'
else
ZPU_ADDR when CPU_CFG_DATA(1) = '1' and ZPU_BUSACKn = '1'
else (others => 'Z');
VZ80_BUSACKn <= T80_BUSACKn when CPU_CFG_DATA(0) = '1'
else
ZPU_BUSACKn when CPU_CFG_DATA(1) = '1'
else '1';
-- Demux the mainboard video signals, these are used when the FPGA video is disabled and the Soft CPU is disabled.
CORE_V_HSYNCn <= VZ80_RFSHn_V_HSYNCn when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_VSYNCn <= VZ80_HALTn_V_VSYNCn when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_COLR <= VZ80_NMIn_V_COLR when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_R <= VZ80_INTn_V_R when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_G <= VZ80_BUSRQn_V_G when MODE_CPLD_MB_VIDEOn = '0'
else '1';
CORE_V_B <= VZ80_WAITn_V_B when MODE_CPLD_MB_VIDEOn = '0'
else '1';
end architecture;

188
FPGA/SW700/v1.3/coreMZ_pkg.vhd Normal file
View File

@@ -0,0 +1,188 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: VideoController700_pkg.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ700 Video Module v1.0 FPGA configuration file.
--
-- This module contains parameters for the Sharp MZ700 Video Module found on the
-- tranZPUter700 card.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Oct 2020 - Split off from the Sharp MZ80A Video Module, the Video Module for the
-- Sharp MZ700 has the same roots but different control functionality. The
-- MZ700 version resides within the tranZPUter memory and not the mainboard
-- allowing for generally easier control. The MZ80A and MZ700 graphics logic
-- should be pretty much identical.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package coreMZ_pkg is
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Target hardware modes.
constant MODE_MZ80K : integer := 0;
constant MODE_MZ80C : integer := 1;
constant MODE_MZ1200 : integer := 2;
constant MODE_MZ80A : integer := 3;
constant MODE_MZ700 : integer := 4;
constant MODE_MZ800 : integer := 5;
constant MODE_MZ80B : integer := 6;
constant MODE_MZ2000 : integer := 7;
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Target hardware.
constant CPLD_HOST_HW : integer := MODE_MZ700;
-- Target video hardware.
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
-- Version of hdl.
constant CPLD_VERSION : integer := 2;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
--
constant USE_K64F_CTL_CLOCK : integer := 1;
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
-- Function to reverse the order of the bits in a standard logic vector.
-- ie. 1010 becomes 0101
function reverse_vector(slv:std_logic_vector) return std_logic_vector;
-- Function to convert an integer (0 or 1) into std_logic.
--
function to_std_logic(i : in integer) return std_logic;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural;
------------------------------------------------------------
-- Records
------------------------------------------------------------
------------------------------------------------------------
-- Components
------------------------------------------------------------
end coreMZ_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body coreMZ_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then
return 0;
end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer is
variable ticks : real;
variable fracTicks : real;
begin
ticks := (Real(period) * Real(clock)) / 1000000000.0;
fracTicks := ticks - CEIL(ticks);
if fracTicks > 0.0001 then
return Integer(CEIL(ticks + 1.0));
else
return Integer(CEIL(ticks));
end if;
end function;
function reverse_vector(slv:std_logic_vector) return std_logic_vector is
variable target : std_logic_vector(slv'high downto slv'low);
begin
for idx in slv'high downto slv'low loop
target(idx) := slv(slv'low + (slv'high-idx));
end loop;
return target;
end reverse_vector;
function to_std_logic(i : in integer) return std_logic is
begin
if i = 0 then
return '0';
end if;
return '1';
end function;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
end package body;

1
FPGA/SW700/v1.3/devices Symbolic link
View File

@@ -0,0 +1 @@
../../../devices

194
FPGA/SW700/v1.3/softT80.vhd Normal file
View File

@@ -0,0 +1,194 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: softT80.vhd
-- Created: December 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ Series FPGA soft cpu module - T80.
--
-- This module provides a soft CPU to the Sharp MZ Core running on a Sharp MZ-700 with
-- the tranZPUter SW-700 v1.3-> board and will be migrated to the pure FPGA tranZPUter
-- v2.2 board in due course.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: Dec 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library altera;
library altera_mf;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.coreMZ_pkg.all;
use altera.altera_syn_attributes.all;
use altera_mf.all;
entity softT80 is
--generic (
--);
Port (
-- System signals and clocks.
SYS_RESETn : in std_logic; -- System reset.
SYS_CLK : in std_logic; -- System logic clock ~120MHz
Z80_CLK : in std_logic; -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET : in std_logic; -- Software controlled reset.
SW_ENABLE : in std_logic; -- Software controlled CPU enable.
CPU_CHANGED : in std_logic; -- Flag to indicate when software selects a different CPU.
-- Core Sharp MZ signals.
T80_WAITn : in std_logic; -- WAITn signal into the CPU to prolong a memory cycle.
T80_INTn : in std_logic; -- INTn signal for maskable interrupts.
T80_NMIn : in std_logic; -- NMIn non maskable interrupt input.
T80_BUSRQn : in std_logic; -- BUSRQn signal to request CPU go into tristate and relinquish bus.
T80_M1n : out std_logic; -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
T80_MREQn : out std_logic; -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
T80_IORQn : out std_logic; -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
T80_RDn : out std_logic; -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
T80_WRn : out std_logic; -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
T80_RFSHn : out std_logic; -- RFSHn signal to indicate dynamic memory refresh can take place.
T80_HALTn : out std_logic; -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
T80_BUSACKn : out std_logic; -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
T80_ADDR : out std_logic_vector(15 downto 0); -- 16 bit address lines.
T80_DATA_IN : in std_logic_vector(7 downto 0); -- 8 bit data bus in.
T80_DATA_OUT : out std_logic_vector(7 downto 0) -- 8 bit data bus out.
);
END entity;
architecture rtl of softT80 is
-- T80
--
signal T80_RESETn : std_logic;
signal T80_CLK : std_logic;
signal T80_CLKEN : std_logic;
signal T80_BUSACKni : std_logic;
component T80a
generic (
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
Port (
RESET_n : in std_logic;
CLK_n : in std_logic; -- NB. Clock is high active.
CLK_EN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0)
);
end component;
begin
-- Process to clean up the Z80 clock originating from the CPLD to drive the T80.
--
process(SYS_RESETn, SYS_CLK, Z80_CLK)
begin
if SYS_RESETn = '0' then
T80_CLK <= '0';
elsif rising_edge(SYS_CLK) then
if Z80_CLK = '0' then
T80_CLK <= '0';
elsif Z80_CLK = '1' then
T80_CLK <= '1';
end if;
end if;
end process;
-- Process to reliably reset the T80. The T80 is disabled whilst in hard CPU mode, once switched to soft CPU, the reset is
-- activated and held low whilst the CPLD changes its state, the clock is then enabled so that the synchronous reset is latched
-- and then the reset is deactivated.
process(SYS_RESETn, T80_CLK)
variable T80_RESET_COUNTER: unsigned(3 downto 0) := (others => '1');
begin
if SYS_RESETn = '0' then
T80_RESET_COUNTER := (others => '1');
T80_RESETn <= '0';
T80_CLKEN <= '0';
elsif rising_edge(T80_CLK) then
if CPU_CHANGED = '1' or SW_RESET = '1' then
T80_RESET_COUNTER := (others => '1');
T80_RESETn <= '0';
T80_CLKEN <= '0';
end if;
if T80_RESET_COUNTER = 5 and SW_ENABLE = '1' then
T80_CLKEN <= '1';
elsif T80_RESET_COUNTER = 0 then
T80_RESETn <= '1';
end if;
if T80_BUSRQn = '1' and T80_RESET_COUNTER /= 0 then
T80_RESET_COUNTER := T80_RESET_COUNTER - 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------
-- T80 CPU
------------------------------------------------------------------------------------
CPU0 : T80a
generic map (
Mode => 0, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait => 1 --
)
port map (
RESET_n => T80_RESETn, -- Reset signal.
CLK_n => T80_CLK, -- T80a clock, sane as the hardware clock but synchronised to the system clock.
CLK_EN => T80_CLKEN, -- Only clock the T80 when enabled.
WAIT_n => T80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
INT_n => T80_INTn, -- INTn signal for maskable interrupts.
NMI_n => T80_NMIn, -- NMIn non maskable interrupt input.
BUSRQ_n => T80_BUSRQn, -- BUSRQn signal to request CPU go into tristate and relinquish bus.
M1_n => T80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
MREQ_n => T80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
IORQ_n => T80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
RD_n => T80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
WR_n => T80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
RFSH_n => T80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
HALT_n => T80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
BUSAK_n => T80_BUSACKni, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
A => T80_ADDR, -- 16 bit address lines.
DIN => T80_DATA_IN, -- 8 bit data bus in.
DOUT => T80_DATA_OUT -- 8 bit data bus out.
);
-- Combine RESET into BUSACK signal.
T80_BUSACKn <= '0' when T80_RESETn = '0'
else
T80_BUSACKni when T80_RESETn = '1'
else '1';
end architecture;

1463
FPGA/SW700/v1.3/softZPU.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

280
FPGA/SW700/v1.3/softZPU_pkg.vhd Normal file
View File

@@ -0,0 +1,280 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: softZPU.vhd
-- Created: December 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ Series FPGA soft cpu module - ZPU.
--
-- This module provides a soft CPU to the Sharp MZ Core running on a Sharp MZ-700 with
-- the tranZPUter SW-700 v1.3-> board and will be migrated to the pure FPGA tranZPUter
-- v2.2 board in due course.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: Dec 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library altera;
library altera_mf;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.coreMZ_pkg.all;
use work.zpu_pkg.all;
use altera.altera_syn_attributes.all;
use altera_mf.all;
package softZPU_pkg is
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Target board declaration.
--
constant BOARD_E115 : boolean := false; -- E115 FPGA Board
constant BOARD_QMV : boolean := false; -- QMTECH Cyclone V FPGA Board
constant BOARD_DE0 : boolean := false; -- DE0-Nano FPGA Board
constant BOARD_DE10 : boolean := false; -- DE10-Nano FPGA Board
constant BOARD_CYC1000 : boolean := false; -- Trenz CYC1000 FPGA Board
constant BOARD_TRANZPUTER_SW700 : boolean := true; -- tranZPUter SW-700 v1.3 Board.
-- Frequencies for the various boards.
--
constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board
constant SYSCLK_QMV_FREQ : integer := 100000000; -- QMTECH Cyclone V FPGA Board
constant SYSCLK_DE0_FREQ : integer := 100000000; -- DE0-Nano FPGA Board
constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board
constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board
constant SYSCLK_TRANZPUTER_SW_FREQ: integer := 50000000; -- tranZPUter SW-700 v1.3-> board frequency.
-- ID for the various ZPU models. The format is 2 bytes, MSB=<Model>, LSB=<Revision>
constant ZPU_ID_SMALL : integer := 16#0101#; -- ID for the ZPU Small in this package.
constant ZPU_ID_MEDIUM : integer := 16#0201#; -- ID for the ZPU Medium in this package.
constant ZPU_ID_FLEX : integer := 16#0301#; -- ID for the ZPU Flex in this package.
constant ZPU_ID_EVO : integer := 16#0401#; -- ID for the ZPU Evo in this package.
constant ZPU_ID_EVO_MINIMAL : integer := 16#0501#; -- ID for the ZPU Evo Minimal in this package.
-- EVO CPU specific configuration.
constant MAX_EVO_L1CACHE_BITS : integer := 4; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
constant MAX_EVO_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
constant MAX_EVO_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits.
-- Settings for various IO devices.
--
constant SYSTEM_FREQUENCY : integer := 100000000; -- Default system clock frequency if not overriden in top level.
-- Constants.
--
constant maxZ80BusBit : integer := maxAddrBit - WB_ACTIVE - 4; -- Upper bit (to define range) of the Z80 Bus space in top section of address space.
-- SoC specific options.
--
constant SOC_IMPL_Z80BUS : boolean := true; -- Implement a ZPU<->Z80 Bus interface.
constant SOC_IMPL_TIMER1 : boolean := true; -- Implement Timer 1, an array of prescaled downcounter with enable.
constant SOC_TIMER1_COUNTERS : integer := 0; -- Number of downcounters in Timer 1. Value is a 2^ array of counters, so 0 = 1 counter.
constant SOC_IMPL_INTRCTL : boolean := true; -- Implement the prioritised interrupt controller.
constant SOC_INTR_MAX : integer := 16; -- Maximum number of interrupt inputs.
constant SOC_IMPL_SOCCFG : boolean := true; -- Implement the SoC Configuration information registers.
-- Main Boot BRAM on sysbus, contains startup firmware.
constant SOC_IMPL_BRAM : boolean := true; -- Implement BRAM for the BIOS and initial Stack.
constant SOC_IMPL_INSN_BRAM : boolean := EVO_USE_INSN_BUS; -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory.
constant SOC_MAX_ADDR_BRAM_BIT : integer := 16; -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same.
constant SOC_ADDR_BRAM_START : integer := 0; -- Start address of BRAM.
constant SOC_ADDR_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT); -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
-- Secondary block of sysbus RAM, typically implemented in BRAM.
constant SOC_IMPL_RAM : boolean := true; -- Implement RAM using BRAM, typically for Application programs seperate to BIOS.
constant SOC_MAX_ADDR_RAM_BIT : integer := 16; -- Max address bit of the System RAM.
constant SOC_ADDR_RAM_START : integer := 131072; -- Start address of RAM.
constant SOC_ADDR_RAM_END : integer := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
-- Instruction BRAM on sysbus, typically as a 2nd port on the main Boot BRAM (ie. dualport).
constant SOC_MAX_ADDR_INSN_BRAM_BIT: integer := SOC_MAX_ADDR_BRAM_BIT; -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words.
constant SOC_ADDR_INSN_BRAM_START : integer := 0; -- Start address of dedicated instrution BRAM.
constant SOC_ADDR_INSN_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_INSN_BRAM_BIT); -- End address of dedicated instruction BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
-- CPU specific settings.
-- Define the address which is first executed upon reset, stack address, Sysbus I/O Region, Wishbone I/O Region.
constant SOC_RESET_ADDR_CPU : integer := SOC_ADDR_BRAM_START; -- Initial address to start execution from after reset.
constant SOC_START_ADDR_MEM : integer := SOC_ADDR_BRAM_START; -- Start location of program memory (BRAM/ROM/RAM).
constant SOC_STACK_ADDR : integer := SOC_ADDR_BRAM_END - 8; -- Stack start address (BRAM/RAM).
constant SOC_ADDR_IO_START : integer := (2**(maxAddrBit-WB_ACTIVE)) - (2**maxIOBit); -- Start address of the Evo Direct Memory Mapped IO region.
constant SOC_ADDR_IO_END : integer := (2**(maxAddrBit-WB_ACTIVE)) - 1; -- End address of the Evo Direct Memory Mapped IO region.
constant SOC_ADDR_Z80BUS_START : integer := SOC_ADDR_IO_START - (2**maxZ80BusBit); -- Start address of the Evo Direct Memory Mapped Z80 Bus region.
constant SOC_ADDR_Z80BUS_END : integer := SOC_ADDR_IO_END - 1; -- End address of the Evo Direct Memory Mapped Z80 Bus region.
-- ZPU Evo configuration
--
-- Optional Evo CPU hardware features to be implemented.
constant IMPL_EVO_OPTIMIZE_IM : boolean := true; -- If the instruction cache is enabled, optimise Im instructions to gain speed.
-- Optional Evo CPU instructions to be implemented in hardware:
constant IMPL_EVO_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT).
constant IMPL_EVO_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right.
constant IMPL_EVO_CALL : boolean := true; -- Call to direct address.
constant IMPL_EVO_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter).
constant IMPL_EVO_DIV : boolean := true; -- 32bit signed division.
constant IMPL_EVO_EQ : boolean := true; -- Equality test.
constant IMPL_EVO_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set.
constant IMPL_EVO_FIADD32 : boolean := false; -- Fixed point Q17.15 addition.
constant IMPL_EVO_FIDIV32 : boolean := false; -- Fixed point Q17.15 division.
constant IMPL_EVO_FIMULT32 : boolean := false; -- Fixed point Q17.15 multiplication.
constant IMPL_EVO_LOADB : boolean := true; -- Load single byte from memory.
constant IMPL_EVO_LOADH : boolean := true; -- Load half word (16bit) from memory.
constant IMPL_EVO_LSHIFTRIGHT : boolean := true; -- Logical shift right.
constant IMPL_EVO_MOD : boolean := true; -- 32bit modulo (remainder after division).
constant IMPL_EVO_MULT : boolean := true; -- 32bit signed multiplication.
constant IMPL_EVO_NEG : boolean := true; -- Negate value in TOS.
constant IMPL_EVO_NEQ : boolean := true; -- Not equal test.
constant IMPL_EVO_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer.
constant IMPL_EVO_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack.
constant IMPL_EVO_STOREB : boolean := true; -- Store/Write a single byte to memory/IO.
constant IMPL_EVO_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO.
constant IMPL_EVO_SUB : boolean := true; -- 32bit signed subtract.
constant IMPL_EVO_XOR : boolean := true; -- Exclusive or of value in TOS.
-- Ranges used throughout the SOC source.
subtype ADDR_BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0; -- Address range of the onboard B(lock)RAM - 1 byte aligned
subtype ADDR_16BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 1; -- Address range of the onboard B(lock)RAM - 2 bytes aligned
subtype ADDR_32BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto minAddrBit; -- Address range of the onboard B(lock)RAM - 4 bytes aligned
subtype ADDR_BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
subtype ADDR_16BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
subtype ADDR_32BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
-- subtype ADDR_DECODE_BRAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_BRAM_BIT; -- Decode range for selection of the BRAM within the address space.
-- subtype ADDR_DECODE_RAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_RAM_BIT; -- Decode range for selection of the RAM within the address space.
subtype IO_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
subtype Z80BUS_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxZ80BusBit; -- Upper bits in memory defining the a block within the address space for the Z80 Bus.
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
------------------------------------------------------------
-- Records
------------------------------------------------------------
------------------------------------------------------------
-- Components
------------------------------------------------------------
component dualport_ram is
port (
clk : in std_logic;
memAWriteEnable : in std_logic;
memAAddr : in std_logic_vector(ADDR_32BIT_RANGE);
memAWrite : in std_logic_vector(WORD_32BIT_RANGE);
memARead : out std_logic_vector(WORD_32BIT_RANGE);
memBWriteEnable : in std_logic;
memBAddr : in std_logic_vector(ADDR_32BIT_RANGE);
memBWrite : in std_logic_vector(WORD_32BIT_RANGE);
memBRead : out std_logic_vector(WORD_32BIT_RANGE)
);
end component;
component dpram
generic (
init_file : string;
widthad_a : natural;
width_a : natural;
widthad_b : natural;
width_b : natural;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
port (
clock_a : in std_logic := '1';
clocken_a : in std_logic := '1';
address_a : in std_logic_vector (widthad_a-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0);
wren_a : in std_logic := '0';
q_a : out std_logic_vector (width_a-1 downto 0);
clock_b : in std_logic;
clocken_b : in std_logic := '1';
address_b : in std_logic_vector (widthad_b-1 downto 0);
data_b : in std_logic_vector (width_b-1 downto 0);
wren_b : in std_logic := '0';
q_b : out std_logic_vector (width_b-1 downto 0)
);
end component;
end softZPU_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body softZPU_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then
return 0;
end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer is
variable ticks : real;
variable fracTicks : real;
begin
ticks := (Real(period) * Real(clock)) / 1000000000.0;
fracTicks := ticks - CEIL(ticks);
if fracTicks > 0.0001 then
return Integer(CEIL(ticks + 1.0));
else
return Integer(CEIL(ticks));
end if;
end function;
end package body;

2
cpu/zpu_core_evo_L2.vhd
View File

@@ -38,7 +38,7 @@ library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.zpu_pkg.all;
use work.zpu_soc_pkg.all;
--use work.zpu_soc_pkg.all;
entity evo_L2cache is
generic

43862
devices/sysbus/BRAM/TZSW_DualPortBRAM.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

44086
devices/sysbus/BRAM/TZSW_DualPortBootBRAM.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

161
devices/sysbus/BRAM/TZSW_SinglePortBRAM.vhd Normal file
View File

@@ -0,0 +1,161 @@
-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation.
--
-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation.
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
library pkgs;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.zpu_pkg.all;
use work.softZPU_pkg.all;
entity SinglePortBRAM is
generic
(
addrbits : integer := 16
);
port
(
clk : in std_logic;
memAAddr : in std_logic_vector(addrbits-1 downto 0);
memAWriteEnable : in std_logic;
memAWriteByte : in std_logic;
memAWriteHalfWord : in std_logic;
memAWrite : in std_logic_vector(WORD_32BIT_RANGE);
memARead : out std_logic_vector(WORD_32BIT_RANGE)
);
end SinglePortBRAM;
architecture arch of SinglePortBRAM is
type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0);
shared variable RAM0 : ramArray :=
(
others => X"00"
);
shared variable RAM1 : ramArray :=
(
others => X"00"
);
shared variable RAM2 : ramArray :=
(
others => X"00"
);
shared variable RAM3 : ramArray :=
(
others => X"00"
);
signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written.
signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written.
signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written.
signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written.
signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word.
signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word.
signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word.
signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word.
begin
RAM0_DATA <= memAWrite(7 downto 0);
RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1'
else
memAWrite(7 downto 0);
RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0')
else
memAWrite(7 downto 0);
RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0')
else
memAWrite(15 downto 8) when memAWriteHalfWord = '1'
else
memAWrite(7 downto 0);
RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1'))
else '0';
RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1'))
else '0';
RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0'))
else '0';
RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0'))
else '0';
-- RAM Byte 0 - Port A - bits 7 to 0
process(clk)
begin
if rising_edge(clk) then
if RAM0_WREN = '1' then
RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA;
else
memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2))));
end if;
end if;
end process;
-- RAM Byte 1 - Port A - bits 15 to 8
process(clk)
begin
if rising_edge(clk) then
if RAM1_WREN = '1' then
RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA;
else
memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2))));
end if;
end if;
end process;
-- RAM Byte 2 - Port A - bits 23 to 16
process(clk)
begin
if rising_edge(clk) then
if RAM2_WREN = '1' then
RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA;
else
memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2))));
end if;
end if;
end process;
-- RAM Byte 3 - Port A - bits 31 to 24
process(clk)
begin
if rising_edge(clk) then
if RAM3_WREN = '1' then
RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA;
else
memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2))));
end if;
end if;
end process;
end arch;

44028
devices/sysbus/BRAM/TZSW_SinglePortBootBRAM.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

Some files were not shown because too many files have changed in this diff Show More