sorgelig aab20e1d5c Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

..

avalon_mem.v

Eliminate interconnect between dma and cpu.

2020-08-07 14:35:47 +08:00

icache.v

Instruction Fetch path improved:

2020-08-04 20:08:12 +02:00

link_dcacheread.v

Revert "timing optimization: adjusted TLB to work without link_dcacheread/write"

2020-07-24 18:37:03 +02:00

link_dcachewrite.v

Revert "timing optimization: adjusted TLB to work without link_dcacheread/write"

2020-07-24 18:37:03 +02:00

memory_read.v

bypass aligned reads directly into CPU

2020-08-01 12:02:30 +02:00

memory_write.v

removed level 1 cache, redone level 2 cache reset, modified files to fulfill verilog standard

2020-07-06 17:29:17 +02:00

memory.v

Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

prefetch_control.v

revert: prefetch TLB request removal

2020-08-06 15:28:39 +02:00

prefetch_fifo.v

Instruction Fetch path improved:

2020-08-04 20:08:12 +02:00

prefetch.v

revert 64bit prefetch because of regression

2020-07-25 09:56:52 +02:00

tlb_memtype.v

Initial port.

2017-08-03 21:35:47 +08:00

tlb_regs.v

Some refactoring and optimizations.

2018-04-23 23:52:21 +08:00

tlb.v

timing optimization: removed not needed multiplexers in TLB and not required signal in CPU

2020-08-02 16:55:35 +02:00