sorgelig aab20e1d5c Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

..

autogen

Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

commands

Some refactoring and optimizations.

2018-04-23 23:52:21 +08:00

memory

Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

pipeline

Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

ao486.qip

Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

ao486.v

Remove redundatnt avalon_io layer.

2020-08-10 19:42:22 +08:00

defines.v

Initial port.

2017-08-03 21:35:47 +08:00

exception.v

removed level 1 cache, redone level 2 cache reset, modified files to fulfill verilog standard

2020-07-06 17:29:17 +02:00

global_regs.v

Some refactoring and optimizations.

2018-04-23 23:52:21 +08:00

startup_default.v

Connect CPU and DMA directly to cache controller. Refactoring in bus names to reflect actual functions.

2020-07-10 02:02:11 +08:00