mirror of
https://github.com/MiSTer-devel/ao486_MiSTer.git
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538 lines
20 KiB
Verilog
538 lines
20 KiB
Verilog
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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//PARSED_COMMENTS: this file contains parsed script comments
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module exception(
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input clk,
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input rst_n,
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//exception indicators
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input dec_gp_fault,
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input dec_ud_fault,
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input dec_pf_fault,
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input rd_seg_gp_fault,
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input rd_descriptor_gp_fault,
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input rd_seg_ss_fault,
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input rd_io_allow_fault,
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input rd_ss_esp_from_tss_fault,
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input exe_div_exception,
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input exe_trigger_gp_fault,
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input exe_trigger_ts_fault,
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input exe_trigger_ss_fault,
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input exe_trigger_np_fault,
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input exe_trigger_nm_fault,
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input exe_trigger_db_fault,
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input exe_trigger_pf_fault,
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input exe_bound_fault,
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input exe_load_seg_gp_fault,
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input exe_load_seg_ss_fault,
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input exe_load_seg_np_fault,
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input wr_debug_init,
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input wr_new_push_ss_fault,
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input wr_string_es_fault,
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input wr_push_ss_fault,
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//from memory
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input read_ac_fault,
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input read_page_fault,
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input write_ac_fault,
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input write_page_fault,
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input [15:0] tlb_code_pf_error_code,
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input [15:0] tlb_check_pf_error_code,
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input [15:0] tlb_write_pf_error_code,
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input [15:0] tlb_read_pf_error_code,
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//wr_int
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input wr_int,
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input wr_int_soft_int,
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input wr_int_soft_int_ib,
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input [7:0] wr_int_vector,
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input wr_exception_external_set,
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input wr_exception_finished,
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//eip
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input [31:0] eip,
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input [31:0] dec_eip,
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input [31:0] rd_eip,
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input [31:0] exe_eip,
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input [31:0] wr_eip,
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input [3:0] rd_consumed,
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input [3:0] exe_consumed,
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input [3:0] wr_consumed,
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//pipeline
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input rd_dec_is_front,
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input rd_is_front,
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input exe_is_front,
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input wr_is_front,
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//interrupt
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input [7:0] interrupt_vector,
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output reg interrupt_done,
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//input
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input wr_interrupt_possible,
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input wr_string_in_progress_final,
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input wr_is_esp_speculative,
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input real_mode,
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input [15:0] rd_error_code,
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input [15:0] exe_error_code,
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input [15:0] wr_error_code,
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//output
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output exc_dec_reset,
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output exc_micro_reset,
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output exc_rd_reset,
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output exc_exe_reset,
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output exc_wr_reset,
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output exc_restore_esp,
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output exc_set_rflag,
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output exc_debug_start,
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output exc_init,
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output reg exc_load,
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output reg [31:0] exc_eip,
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output [7:0] exc_vector,
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output reg [15:0] exc_error_code,
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output reg exc_push_error,
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output reg exc_soft_int,
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output reg exc_soft_int_ib,
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output exc_pf_read,
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output exc_pf_write,
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output exc_pf_code,
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output exc_pf_check
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);
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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wire exception_init;
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wire exception_start;
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wire active_dec;
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wire active_rd;
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wire active_exe;
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wire active_wr;
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wire [31:0] exception_eip_from_wr;
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//------------------------------------------------------------------------------
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reg external;
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reg [1:0] count;
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reg [1:0] last_type;
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reg [31:0] trap_eip;
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reg shutdown;
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reg interrupt_load;
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reg interrupt_string_in_progress;
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reg [8:0] exc_vector_full;
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//------------------------------------------------------------------------------
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wire [7:0] vector;
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wire [15:0] error_code;
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wire push_error;
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wire class_trap;
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wire class_abort;
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wire [1:0] exception_type;
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wire shutdown_start;
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wire [8:0] exc_vector_full_to_reg;
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wire [15:0] exc_error_code_to_reg;
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wire exc_push_error_to_reg;
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wire exc_soft_int_ib_to_reg;
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wire exc_soft_int_to_reg;
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wire external_to_reg;
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wire [1:0] count_to_reg;
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wire [1:0] last_type_to_reg;
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wire [31:0] exc_eip_to_reg;
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wire shutdown_to_reg;
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//------------------------------------------------------------------------------
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assign exc_vector = exc_vector_full[7:0];
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//------------------------------------------------------------------------------
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assign exception_init = exc_vector_full[8];
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assign exc_init = exception_init || wr_interrupt_possible || interrupt_done || wr_debug_init;
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assign active_dec = (dec_gp_fault || dec_ud_fault || dec_pf_fault) &&
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rd_dec_is_front && ~(exc_init);
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assign active_rd = (rd_seg_gp_fault || rd_descriptor_gp_fault || rd_seg_ss_fault || rd_io_allow_fault ||
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rd_ss_esp_from_tss_fault || read_ac_fault || read_page_fault) &&
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rd_is_front && ~(exc_init);
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assign active_exe = (exe_div_exception || exe_trigger_gp_fault || exe_trigger_ts_fault || exe_trigger_ss_fault ||
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exe_trigger_np_fault || exe_trigger_nm_fault || exe_trigger_db_fault || exe_trigger_pf_fault ||
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exe_bound_fault || exe_load_seg_gp_fault || exe_load_seg_ss_fault || exe_load_seg_np_fault) &&
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exe_is_front && ~(exc_init);
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assign active_wr = (wr_new_push_ss_fault || wr_string_es_fault || wr_push_ss_fault || write_ac_fault ||
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write_page_fault || wr_int) &&
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wr_is_front && ~(exc_init);
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assign exc_pf_read = active_rd && read_page_fault;
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assign exc_pf_write= active_wr && write_page_fault;
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assign exc_pf_code = active_dec && dec_pf_fault;
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assign exc_pf_check= active_exe && exe_trigger_pf_fault;
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//------------------------------------------------------------------------------
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always @(posedge clk) begin
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if(rst_n == 1'b0) exc_vector_full <= 9'd0;
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else if(active_wr && wr_new_push_ss_fault) exc_vector_full <= { 1'b1, `EXCEPTION_SS };
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else if(active_wr && wr_string_es_fault) exc_vector_full <= { 1'b1, `EXCEPTION_GP };
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else if(active_wr && wr_push_ss_fault) exc_vector_full <= { 1'b1, `EXCEPTION_SS };
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else if(active_wr && write_ac_fault) exc_vector_full <= { 1'b1, `EXCEPTION_AC };
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else if(active_wr && write_page_fault) exc_vector_full <= { 1'b1, `EXCEPTION_PF };
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else if(active_wr && wr_int) exc_vector_full <= { 1'b0, wr_int_vector };
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else if(active_exe && exe_div_exception) exc_vector_full <= { 1'b1, `EXCEPTION_DE };
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else if(active_exe && exe_trigger_gp_fault) exc_vector_full <= { 1'b1, `EXCEPTION_GP };
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else if(active_exe && exe_trigger_ts_fault) exc_vector_full <= { 1'b1, `EXCEPTION_TS };
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else if(active_exe && exe_trigger_ss_fault) exc_vector_full <= { 1'b1, `EXCEPTION_SS };
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else if(active_exe && exe_trigger_np_fault) exc_vector_full <= { 1'b1, `EXCEPTION_NP };
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else if(active_exe && exe_trigger_nm_fault) exc_vector_full <= { 1'b1, `EXCEPTION_NM };
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else if(active_exe && exe_trigger_db_fault) exc_vector_full <= { 1'b1, `EXCEPTION_DB };
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else if(active_exe && exe_trigger_pf_fault) exc_vector_full <= { 1'b1, `EXCEPTION_PF };
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else if(active_exe && exe_bound_fault) exc_vector_full <= { 1'b1, `EXCEPTION_BR };
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else if(active_exe && exe_load_seg_gp_fault) exc_vector_full <= { 1'b1, `EXCEPTION_GP };
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else if(active_exe && exe_load_seg_ss_fault) exc_vector_full <= { 1'b1, `EXCEPTION_SS };
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else if(active_exe && exe_load_seg_np_fault) exc_vector_full <= { 1'b1, `EXCEPTION_NP };
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else if(active_rd && rd_seg_gp_fault) exc_vector_full <= { 1'b1, `EXCEPTION_GP };
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else if(active_rd && rd_descriptor_gp_fault) exc_vector_full <= { 1'b1, `EXCEPTION_GP };
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else if(active_rd && rd_seg_ss_fault) exc_vector_full <= { 1'b1, `EXCEPTION_SS };
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else if(active_rd && rd_io_allow_fault) exc_vector_full <= { 1'b1, `EXCEPTION_GP };
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else if(active_rd && rd_ss_esp_from_tss_fault) exc_vector_full <= { 1'b1, `EXCEPTION_TS };
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else if(active_rd && read_ac_fault) exc_vector_full <= { 1'b1, `EXCEPTION_AC };
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else if(active_rd && read_page_fault) exc_vector_full <= { 1'b1, `EXCEPTION_PF };
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else if(active_dec && dec_gp_fault) exc_vector_full <= { 1'b1, `EXCEPTION_GP };
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else if(active_dec && dec_ud_fault) exc_vector_full <= { 1'b1, `EXCEPTION_UD };
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else if(active_dec && dec_pf_fault) exc_vector_full <= { 1'b1, `EXCEPTION_PF };
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else exc_vector_full <= exc_vector_full_to_reg; //set if(exception_init || wr_debug_init || interrupt_done)
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) exc_error_code <= 16'd0;
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else if(active_wr && write_ac_fault) exc_error_code <= 16'd0;
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else if(active_wr && write_page_fault) exc_error_code <= tlb_write_pf_error_code;
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else if(active_wr) exc_error_code <= wr_error_code;
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else if(active_exe && exe_trigger_pf_fault) exc_error_code <= tlb_check_pf_error_code;
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else if(active_exe) exc_error_code <= exe_error_code;
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else if(active_rd && read_ac_fault) exc_error_code <= 16'd0;
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else if(active_rd && read_page_fault) exc_error_code <= tlb_read_pf_error_code;
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else if(active_rd) exc_error_code <= rd_error_code;
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else if(active_dec && dec_pf_fault) exc_error_code <= tlb_code_pf_error_code;
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else if(active_dec) exc_error_code <= 16'd0;
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else exc_error_code <= exc_error_code_to_reg; //set if(exception_init || wr_debug_init || interrupt_done)
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) exc_push_error <= `FALSE;
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else if(active_wr && wr_int) exc_push_error <= `FALSE;
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else exc_push_error <= exc_push_error_to_reg;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) exc_soft_int <= `FALSE;
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else if(active_wr && wr_int) exc_soft_int <= wr_int_soft_int;
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else exc_soft_int <= exc_soft_int_to_reg;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) exc_soft_int_ib <= `FALSE;
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else if(active_wr && wr_int) exc_soft_int_ib <= wr_int_soft_int_ib;
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else exc_soft_int_ib <= exc_soft_int_ib_to_reg;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) exc_load <= `FALSE;
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else exc_load <= exception_start || interrupt_done;
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end
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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always @(posedge clk) begin
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if(rst_n == 1'b0) external <= 1'b0;
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else if(wr_exception_external_set) external <= `TRUE;
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else if(wr_exception_finished) external <= `FALSE;
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else external <= external_to_reg;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) count <= 2'b0;
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else if(wr_exception_finished) count <= 2'd0;
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else count <= count_to_reg;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) last_type <= 2'b0;
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else last_type <= last_type_to_reg;
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end
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assign exception_eip_from_wr = wr_eip - { 28'd0, wr_consumed };
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always @(posedge clk) begin
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if(rst_n == 1'b0) exc_eip <= 32'd0;
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else if(active_wr) exc_eip <= exception_eip_from_wr;
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else if(active_exe) exc_eip <= exe_eip - { 28'd0, exe_consumed };
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else if(active_rd) exc_eip <= rd_eip - { 28'd0, rd_consumed };
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else if(active_dec) exc_eip <= eip;
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else exc_eip <= exc_eip_to_reg;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) trap_eip <= 32'd0;
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else if(active_wr) trap_eip <= wr_eip;
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else if(active_exe) trap_eip <= exe_eip;
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else if(active_rd) trap_eip <= rd_eip;
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else if(active_dec) trap_eip <= dec_eip;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) shutdown <= `FALSE;
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else shutdown <= shutdown_to_reg;
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end
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//------------------------------------------------------------------------------
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assign vector = (wr_debug_init)? `EXCEPTION_DB : exc_vector_full[7:0];
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assign error_code =
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(real_mode)? 16'd0 :
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(vector != `EXCEPTION_PF && vector != `EXCEPTION_DF)? { exc_error_code[15:1], external } :
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exc_error_code;
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assign push_error =
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~(real_mode) && (
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(vector == `EXCEPTION_DF) || (vector == `EXCEPTION_TS) || (vector == `EXCEPTION_NP) ||
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(vector == `EXCEPTION_SS) || (vector == `EXCEPTION_GP) || (vector == `EXCEPTION_PF) ||
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(vector == `EXCEPTION_AC));
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assign class_trap = (vector == `EXCEPTION_BP) || (vector == `EXCEPTION_OF);
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assign class_abort = (vector == `EXCEPTION_MC);
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`define EXCEPTION_TYPE_BENIGN 2'd0
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`define EXCEPTION_TYPE_CONTRIBUTORY 2'd1
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`define EXCEPTION_TYPE_PAGE_FAULT 2'd2
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`define EXCEPTION_TYPE_DOUBLE_FAULT 2'd3
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assign exception_type =
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(vector == `EXCEPTION_DE) || (vector >= `EXCEPTION_TS && vector <= `EXCEPTION_GP)? `EXCEPTION_TYPE_CONTRIBUTORY :
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(vector == `EXCEPTION_DF)? `EXCEPTION_TYPE_DOUBLE_FAULT :
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(vector == `EXCEPTION_PF)? `EXCEPTION_TYPE_PAGE_FAULT :
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`EXCEPTION_TYPE_BENIGN;
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assign shutdown_start = count > 2'd2 || (count > 2'd0 && last_type == `EXCEPTION_TYPE_DOUBLE_FAULT);
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//------------------------------------------------------------------------------
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// interrupt_vector[7:0], interrupt_done;
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always @(posedge clk) begin
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if(rst_n == 1'b0) interrupt_done <= `FALSE;
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else if(wr_interrupt_possible) interrupt_done <= `TRUE;
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else interrupt_done <= `FALSE;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) interrupt_load <= `FALSE;
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else interrupt_load <= interrupt_done;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) interrupt_string_in_progress <= `FALSE;
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else if(wr_interrupt_possible && wr_string_in_progress_final) interrupt_string_in_progress <= `TRUE;
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else if(wr_interrupt_possible) interrupt_string_in_progress <= `FALSE;
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end
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assign exc_debug_start = exc_load && vector == `EXCEPTION_DB && interrupt_load == `FALSE;
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/*******************************************************************************SCRIPT
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NO_ALWAYS_BLOCK(exc_eip);
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NO_ALWAYS_BLOCK(exc_error_code);
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NO_ALWAYS_BLOCK(exc_push_error);
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NO_ALWAYS_BLOCK(exc_soft_int);
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NO_ALWAYS_BLOCK(exc_soft_int_ib);
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NO_ALWAYS_BLOCK(exc_vector_full);
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NO_ALWAYS_BLOCK(shutdown);
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NO_ALWAYS_BLOCK(last_type);
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NO_ALWAYS_BLOCK(count);
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NO_ALWAYS_BLOCK(external);
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*/
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/*******************************************************************************SCRIPT
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IF(exception_init || wr_debug_init);
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//NOTE: exe_reset must in same cycle as exception_init (wr waits one cycle for wr_one_cycle_wait)
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SET(exc_dec_reset);
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SET(exc_micro_reset);
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SET(exc_rd_reset);
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SET(exc_exe_reset);
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SET(exc_wr_reset);
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IF(~(class_trap) && ~(class_abort));
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IF(wr_is_esp_speculative); SET(exc_restore_esp); ENDIF();
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// eip in exc_eip
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IF(vector != `EXCEPTION_DB); SET(exc_set_rflag); ENDIF();
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ELSE();
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// trap
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//esp no change needed
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SAVE(exc_eip, trap_eip);
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ENDIF();
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IF(vector == `EXCEPTION_DB);
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IF(wr_debug_init && ~(wr_string_in_progress_final)); SAVE(exc_eip, wr_eip); ENDIF();
|
|
IF(wr_debug_init && wr_string_in_progress_final); SAVE(exc_eip, exception_eip_from_wr); ENDIF();
|
|
// if not wr_debug_init -- eip already in exc_eip
|
|
ENDIF();
|
|
|
|
SAVE(external, `TRUE);
|
|
|
|
IF(shutdown_start == `FALSE && count > 2'd0 && exception_type != `EXCEPTION_TYPE_DOUBLE_FAULT && (
|
|
(last_type == `EXCEPTION_TYPE_CONTRIBUTORY && exception_type == `EXCEPTION_TYPE_CONTRIBUTORY) ||
|
|
(last_type == `EXCEPTION_TYPE_PAGE_FAULT && exception_type == `EXCEPTION_TYPE_CONTRIBUTORY) ||
|
|
(last_type == `EXCEPTION_TYPE_PAGE_FAULT && exception_type == `EXCEPTION_TYPE_PAGE_FAULT)));
|
|
|
|
SAVE(exc_vector_full, { 1'b1, `EXCEPTION_DF });
|
|
SAVE(exc_error_code, 16'd0);
|
|
ELSE();
|
|
|
|
IF(shutdown_start == `FALSE);
|
|
SAVE(last_type, exception_type);
|
|
SAVE(count, count + 2'd1);
|
|
|
|
SAVE(exc_push_error, push_error);
|
|
SAVE(exc_error_code, error_code);
|
|
|
|
SAVE(exc_soft_int, `FALSE);
|
|
SAVE(exc_soft_int_ib, `FALSE);
|
|
|
|
// finish this state
|
|
SAVE(exc_vector_full, { 1'b0, vector });
|
|
|
|
SET(exception_start);
|
|
ENDIF();
|
|
ENDIF();
|
|
|
|
IF(shutdown_start);
|
|
// finish this state
|
|
SAVE(exc_vector_full, { 1'b0, vector });
|
|
|
|
SAVE(shutdown, `TRUE);
|
|
ENDIF();
|
|
|
|
ENDIF();
|
|
|
|
*/
|
|
|
|
/*******************************************************************************SCRIPT
|
|
|
|
IF(shutdown);
|
|
|
|
// keep pipeline reset
|
|
SET(exc_dec_reset);
|
|
SET(exc_micro_reset);
|
|
SET(exc_rd_reset);
|
|
SET(exc_exe_reset);
|
|
SET(exc_wr_reset);
|
|
ENDIF();
|
|
|
|
*/
|
|
|
|
/*******************************************************************************SCRIPT
|
|
|
|
IF(interrupt_done);
|
|
|
|
SAVE(external, `TRUE);
|
|
|
|
SAVE(exc_vector_full, { 1'b0, interrupt_vector });
|
|
|
|
SAVE(exc_push_error, `FALSE);
|
|
SAVE(exc_error_code, 16'd0);
|
|
|
|
SAVE(exc_eip, (interrupt_string_in_progress)? exception_eip_from_wr : wr_eip);
|
|
|
|
SAVE(exc_soft_int, `FALSE);
|
|
SAVE(exc_soft_int_ib, `FALSE);
|
|
|
|
SET(exc_dec_reset);
|
|
SET(exc_micro_reset);
|
|
SET(exc_rd_reset);
|
|
SET(exc_exe_reset);
|
|
SET(exc_wr_reset);
|
|
ENDIF();
|
|
|
|
*/
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
`include "autogen/exception.v"
|
|
|
|
|
|
endmodule
|