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https://github.com/MiSTer-devel/ao486_MiSTer.git
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220 lines
7.6 KiB
Verilog
220 lines
7.6 KiB
Verilog
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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//PARSED_COMMENTS: this file contains parsed script comments
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module memory_read(
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// global
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input clk,
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input rst_n,
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// read step
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input rd_reset,
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//RESP:
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input read_do,
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output read_done,
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output reg read_page_fault,
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output reg read_ac_fault,
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input [1:0] read_cpl,
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input [31:0] read_address,
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input [3:0] read_length,
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input read_lock,
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input read_rmw,
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output [63:0] read_data,
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//END
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//REQ:
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output tlbread_do,
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input tlbread_done,
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input tlbread_page_fault,
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input tlbread_ac_fault,
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input tlbread_retry,
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output [1:0] tlbread_cpl,
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output [31:0] tlbread_address,
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output [3:0] tlbread_length,
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output [3:0] tlbread_length_full,
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output tlbread_lock,
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output tlbread_rmw,
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input [63:0] tlbread_data
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//END
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);
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//------------------------------------------------------------------------------
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reg [1:0] state;
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reg [55:0] buffer;
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reg [3:0] length_2_reg;
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reg [31:0] address_2_reg;
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reg reset_waiting;
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reg read_done_next;
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reg [63:0] read_data_next;
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//------------------------------------------------------------------------------
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wire [63:0] merged;
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wire [4:0] left_in_line;
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wire [3:0] length_1;
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wire [3:0] length_2;
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wire [31:0] address_2;
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//------------------------------------------------------------------------------
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localparam [1:0] STATE_IDLE = 2'd0;
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localparam [1:0] STATE_WAIT = 2'd1;
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localparam [1:0] STATE_FIRST = 2'd2;
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localparam [1:0] STATE_SECOND = 2'd3;
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//------------------------------------------------------------------------------
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assign left_in_line = 5'd16 - { 1'b0, read_address[3:0] };
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assign length_1 = (left_in_line >= { 1'd0, read_length })? read_length : left_in_line[3:0];
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assign length_2 = read_length - length_1;
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assign address_2 = { read_address[31:4], 4'd0 } + 32'd16;
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assign tlbread_cpl = read_cpl;
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assign tlbread_length_full = read_length;
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assign tlbread_lock = read_lock;
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assign tlbread_rmw = read_rmw;
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//------------------------------------------------------------------------------
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reg [3:0] length_1_save;
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always @(posedge clk) length_1_save <= length_1;
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assign merged =
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(length_1_save == 4'd1)? { tlbread_data[55:0], buffer[7:0] } :
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(length_1_save == 4'd2)? { tlbread_data[47:0], buffer[15:0] } :
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(length_1_save == 4'd3)? { tlbread_data[39:0], buffer[23:0] } :
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(length_1_save == 4'd4)? { tlbread_data[31:0], buffer[31:0] } :
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(length_1_save == 4'd5)? { tlbread_data[23:0], buffer[39:0] } :
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(length_1_save == 4'd6)? { tlbread_data[15:0], buffer[47:0] } :
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{ tlbread_data[7:0], buffer[55:0] };
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//------------------------------------------------------------------------------
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always @(posedge clk) begin
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if(rst_n == 1'b0) reset_waiting <= `FALSE;
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else if(rd_reset && state != STATE_IDLE) reset_waiting <= `TRUE;
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else if(state == STATE_IDLE) reset_waiting <= `FALSE;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) read_page_fault <= `FALSE;
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else if(rd_reset) read_page_fault <= `FALSE;
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else if(tlbread_page_fault && ~(reset_waiting)) read_page_fault <= `TRUE;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) read_ac_fault <= `FALSE;
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else if(rd_reset) read_ac_fault <= `FALSE;
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else if(tlbread_ac_fault && ~(reset_waiting)) read_ac_fault <= `TRUE;
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end
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//------------------------------------------------------------------------------
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assign tlbread_address = (state == STATE_SECOND) ? address_2_reg : read_address;
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assign tlbread_length = (state == STATE_SECOND) ? length_2_reg : length_1;
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assign tlbread_do =
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(state == STATE_IDLE && read_do && ~(read_done_next) && ~(rd_reset) && ~(read_page_fault) && ~(read_ac_fault))? 1'b1 :
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(state == STATE_WAIT)? 1'b1 :
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(state == STATE_FIRST)? 1'b1 :
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(state == STATE_SECOND)? 1'b1 :
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1'b0;
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assign read_done = (state == STATE_WAIT && ~(tlbread_page_fault || tlbread_ac_fault || (tlbread_retry && reset_waiting)) && tlbread_done && ~rd_reset && ~reset_waiting)? 1'b1 : read_done_next;
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assign read_data = (state == STATE_WAIT) ? tlbread_data : read_data_next;
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always @(posedge clk) begin
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if(!rst_n) begin
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state <= STATE_IDLE;
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end
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else begin
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read_done_next <= 1'b0;
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case(state)
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STATE_IDLE:
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begin
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length_2_reg <= length_2;
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address_2_reg <= { address_2[31:4], 4'd0 };
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if(read_do && ~(read_done_next) && ~(rd_reset) && ~(read_page_fault) && ~(read_ac_fault)) begin
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if (length_2 == 4'd0) begin
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state <= STATE_WAIT;
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end else begin
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state <= STATE_FIRST;
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end
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end
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end
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STATE_WAIT:
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if(tlbread_page_fault || tlbread_ac_fault || (tlbread_retry && reset_waiting)) begin
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state <= STATE_IDLE;
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end else if(tlbread_done) begin
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state <= STATE_IDLE;
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read_data_next <= tlbread_data;
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end
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STATE_FIRST:
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begin
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if(tlbread_page_fault || tlbread_ac_fault || (tlbread_retry && reset_waiting)) begin
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state <= STATE_IDLE;
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end else if(tlbread_done) begin
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buffer <= tlbread_data[55:0];
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state <= STATE_SECOND;
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end
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end
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STATE_SECOND:
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begin
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if(tlbread_page_fault || tlbread_ac_fault || tlbread_done || (tlbread_retry && reset_waiting)) begin
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state <= STATE_IDLE;
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end
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if(tlbread_done && rd_reset == `FALSE && reset_waiting == `FALSE) begin
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read_done_next <= 1'b1;
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read_data_next <= merged;
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end
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end
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endcase
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end
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end
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endmodule
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