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https://github.com/MiSTer-devel/ao486_MiSTer.git
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233 lines
7.2 KiB
Verilog
233 lines
7.2 KiB
Verilog
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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//PARSED_COMMENTS: this file contains parsed script comments
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module memory_write(
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input clk,
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input rst_n,
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// write step
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input wr_reset,
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//RESP:
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input write_do,
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output write_done,
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output write_page_fault,
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output write_ac_fault,
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input [1:0] write_cpl,
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input [31:0] write_address,
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input [2:0] write_length,
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input write_lock,
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input write_rmw,
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input [31:0] write_data,
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//END
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//REQ: done at least one cycle later, do has to wait for doing
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output tlbwrite_do,
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input tlbwrite_done,
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input tlbwrite_page_fault,
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input tlbwrite_ac_fault,
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output [1:0] tlbwrite_cpl,
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output [31:0] tlbwrite_address,
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output [2:0] tlbwrite_length,
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output [2:0] tlbwrite_length_full,
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output tlbwrite_lock,
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output tlbwrite_rmw,
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output [31:0] tlbwrite_data
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//END
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);
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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reg [1:0] state;
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reg [23:0] buffer;
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reg [2:0] length_2_reg;
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reg [31:0] address_2_reg;
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reg reset_waiting;
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reg page_fault;
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reg ac_fault;
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//------------------------------------------------------------------------------
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wire [4:0] left_in_line;
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wire [2:0] length_1;
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wire [2:0] length_2;
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wire [31:0] address_2;
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//------------------------------------------------------------------------------
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assign write_page_fault = tlbwrite_page_fault || page_fault;
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assign write_ac_fault = tlbwrite_ac_fault || ac_fault;
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assign left_in_line = 5'd16 - { 1'b0, write_address[3:0] };
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assign length_1 = (left_in_line >= { 2'd0, write_length })? write_length : left_in_line[2:0];
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assign length_2 = write_length - length_1;
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assign address_2 = { write_address[31:4], 4'd0 } + 32'd16;
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assign tlbwrite_cpl = write_cpl;
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assign tlbwrite_length_full = write_length;
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assign tlbwrite_lock = write_lock;
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assign tlbwrite_rmw = write_rmw;
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//------------------------------------------------------------------------------
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localparam [1:0] STATE_IDLE = 2'd0;
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localparam [1:0] STATE_FIRST_WAIT = 2'd1;
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localparam [1:0] STATE_SECOND = 2'd2;
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always @(posedge clk) begin
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if(rst_n == 1'b0) reset_waiting <= `FALSE;
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else if(wr_reset && state != STATE_IDLE) reset_waiting <= `TRUE;
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else if(state == STATE_IDLE) reset_waiting <= `FALSE;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) page_fault <= `FALSE;
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else if(wr_reset) page_fault <= `FALSE;
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else if(tlbwrite_page_fault && ~(reset_waiting)) page_fault <= `TRUE;
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) ac_fault <= `FALSE;
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else if(wr_reset) ac_fault <= `FALSE;
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else if(tlbwrite_ac_fault && ~(reset_waiting)) ac_fault <= `TRUE;
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end
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, address_2[3:0], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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/*
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tlbwrite_cpl -- constant assign from read
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tlbwrite_address -- set
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tlbwrite_length -- set
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tlbwrite_length_full -- constant assign from read
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tlbwrite_lock -- constant assign from read
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tlbwrite_rmw -- constant assign from read
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tlbwrite_data -- set
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*/
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/*******************************************************************************SCRIPT
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IF(state == STATE_IDLE);
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IF(length_1 == 3'd1); SAVE(buffer, write_data[31:8]);
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ELSE_IF(length_1 == 3'd2); SAVE(buffer, { 8'd0, write_data[31:16] });
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ELSE(); SAVE(buffer, { 16'd0, write_data[31:24] });
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ENDIF();
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SAVE(length_2_reg, length_2);
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SAVE(address_2_reg, { address_2[31:4], 4'd0 });
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SET(tlbwrite_address, write_address);
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SET(tlbwrite_length, length_1);
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SET(tlbwrite_data, write_data);
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IF(write_do && ~(wr_reset) && ~(write_page_fault) && ~(write_ac_fault));
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SET(tlbwrite_do);
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SAVE(state, STATE_FIRST_WAIT);
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ENDIF();
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ENDIF();
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*/
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/*******************************************************************************SCRIPT
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IF(state == STATE_FIRST_WAIT);
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SET(tlbwrite_do);
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SET(tlbwrite_address, write_address);
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SET(tlbwrite_length, length_1);
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SET(tlbwrite_data, write_data);
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IF(tlbwrite_page_fault || tlbwrite_ac_fault);
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SAVE(state, STATE_IDLE);
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ELSE_IF(tlbwrite_done && length_2_reg != 3'd0);
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SAVE(state, STATE_SECOND);
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ELSE_IF(tlbwrite_done);
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IF(reset_waiting == `FALSE); SET(write_done); ENDIF(); //does not depend on: wr_reset == `FALSE
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SAVE(state, STATE_IDLE);
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ENDIF();
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ENDIF();
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*/
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/*******************************************************************************SCRIPT
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IF(state == STATE_SECOND);
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SET(tlbwrite_do);
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SET(tlbwrite_address, address_2_reg);
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SET(tlbwrite_length, length_2_reg);
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SET(tlbwrite_data, { 8'd0, buffer });
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IF(tlbwrite_page_fault || tlbwrite_ac_fault || tlbwrite_done);
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SAVE(state, STATE_IDLE);
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ENDIF();
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IF(tlbwrite_done && reset_waiting == `FALSE); //does not depend on: wr_reset == `FALSE
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SET(write_done);
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ENDIF();
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ENDIF();
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*/
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//------------------------------------------------------------------------------
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`include "autogen/memory_write.v"
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endmodule
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