mirror of
https://github.com/MiSTer-devel/ao486_MiSTer.git
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741 lines
27 KiB
Verilog
741 lines
27 KiB
Verilog
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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module memory(
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input clk,
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input rst_n,
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//REQ:
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input read_do,
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output read_done,
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output read_page_fault,
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output read_ac_fault,
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input [1:0] read_cpl,
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input [31:0] read_address,
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input [3:0] read_length,
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input read_lock,
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input read_rmw,
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output [63:0] read_data,
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//END
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//REQ:
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input write_do,
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output write_done,
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output write_page_fault,
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output write_ac_fault,
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input [1:0] write_cpl,
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input [31:0] write_address,
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input [2:0] write_length,
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input write_lock,
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input write_rmw,
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input [31:0] write_data,
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//END
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//REQ:
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input tlbcheck_do,
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output tlbcheck_done,
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output tlbcheck_page_fault,
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input [31:0] tlbcheck_address,
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input tlbcheck_rw,
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//END
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//RESP:
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input tlbflushsingle_do,
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output tlbflushsingle_done,
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input [31:0] tlbflushsingle_address,
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//END
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//RESP:
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input tlbflushall_do,
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//END
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//RESP:
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input invdcode_do,
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output invdcode_done,
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//END
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//RESP:
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input invddata_do,
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output invddata_done,
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//END
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//RESP:
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input wbinvddata_do,
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output wbinvddata_done,
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//END
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// prefetch exported
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input [1:0] prefetch_cpl,
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input [31:0] prefetch_eip,
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input [63:0] cs_cache,
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input cr0_pg,
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input cr0_wp,
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input cr0_am,
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input cr0_cd,
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input cr0_nw,
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input acflag,
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input [31:0] cr3,
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// prefetch_fifo exported
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input prefetchfifo_accept_do,
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output [67:0] prefetchfifo_accept_data,
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output prefetchfifo_accept_empty,
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input pipeline_after_read_empty,
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input pipeline_after_prefetch_empty,
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output [31:0] tlb_code_pf_cr2,
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output [15:0] tlb_code_pf_error_code,
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output [31:0] tlb_check_pf_cr2,
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output [15:0] tlb_check_pf_error_code,
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output [31:0] tlb_write_pf_cr2,
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output [15:0] tlb_write_pf_error_code,
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output [31:0] tlb_read_pf_cr2,
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output [15:0] tlb_read_pf_error_code,
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// reset exported
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input pr_reset,
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input rd_reset,
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input exe_reset,
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input wr_reset,
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// avalon master
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output [31:2] avm_address,
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output [31:0] avm_writedata,
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output [3:0] avm_byteenable,
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output [3:0] avm_burstcount,
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output avm_write,
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output avm_read,
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input avm_waitrequest,
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input avm_readdatavalid,
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input [31:0] avm_readdata,
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input [23:0] dma_address,
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input dma_write,
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input [7:0] dma_writedata,
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input dma_read,
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output [7:0] dma_readdata,
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output dma_readdatavalid,
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output dma_waitrequest
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);
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//------------------------------------------------------------------------------
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wire req_readcode_do;
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wire req_readcode_done;
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wire [31:0] req_readcode_address;
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wire [31:0] req_readcode_partial;
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//------------------------------------------------------------------------------
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wire req_dcacheread_do;
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wire req_dcacheread_done;
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wire [3:0] req_dcacheread_length;
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wire req_dcacheread_cache_disable;
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wire [31:0] req_dcacheread_address;
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wire [63:0] req_dcacheread_data;
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wire resp_dcacheread_do;
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wire resp_dcacheread_done;
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wire [3:0] resp_dcacheread_length;
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wire resp_dcacheread_cache_disable;
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wire [31:0] resp_dcacheread_address;
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wire [63:0] resp_dcacheread_data;
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link_dcacheread link_dcacheread_inst(
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.clk (clk),
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.rst_n (rst_n),
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// dcacheread REQ
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.req_dcacheread_do (req_dcacheread_do), //input
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.req_dcacheread_done (req_dcacheread_done), //output
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.req_dcacheread_length (req_dcacheread_length), //input [3:0]
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.req_dcacheread_cache_disable (req_dcacheread_cache_disable), //input
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.req_dcacheread_address (req_dcacheread_address), //input [31:0]
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.req_dcacheread_data (req_dcacheread_data), //output [63:0]
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// dcacheread RESP
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.resp_dcacheread_do (resp_dcacheread_do), //output
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.resp_dcacheread_done (resp_dcacheread_done), //input
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.resp_dcacheread_length (resp_dcacheread_length), //output [3:0]
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.resp_dcacheread_cache_disable (resp_dcacheread_cache_disable), //output
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.resp_dcacheread_address (resp_dcacheread_address), //output [31:0]
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.resp_dcacheread_data (resp_dcacheread_data) //input [63:0]
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);
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//------------------------------------------------------------------------------
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wire req_dcachewrite_do;
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wire req_dcachewrite_done;
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wire [2:0] req_dcachewrite_length;
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wire req_dcachewrite_cache_disable;
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wire [31:0] req_dcachewrite_address;
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wire req_dcachewrite_write_through;
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wire [31:0] req_dcachewrite_data;
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wire resp_dcachewrite_do;
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wire resp_dcachewrite_done;
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wire [2:0] resp_dcachewrite_length;
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wire resp_dcachewrite_cache_disable;
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wire [31:0] resp_dcachewrite_address;
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wire resp_dcachewrite_write_through;
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wire [31:0] resp_dcachewrite_data;
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link_dcachewrite link_dcachewrite_inst(
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.clk (clk),
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.rst_n (rst_n),
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// dcachewrite REQ
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.req_dcachewrite_do (req_dcachewrite_do), //input
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.req_dcachewrite_done (req_dcachewrite_done), //output
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.req_dcachewrite_length (req_dcachewrite_length), //input [2:0]
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.req_dcachewrite_cache_disable (req_dcachewrite_cache_disable), //input
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.req_dcachewrite_address (req_dcachewrite_address), //input [31:0]
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.req_dcachewrite_write_through (req_dcachewrite_write_through), //input
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.req_dcachewrite_data (req_dcachewrite_data), //input [31:0]
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// dcachewrite RESP
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.resp_dcachewrite_do (resp_dcachewrite_do), //output
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.resp_dcachewrite_done (resp_dcachewrite_done), //input
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.resp_dcachewrite_length (resp_dcachewrite_length), //output [2:0]
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.resp_dcachewrite_cache_disable (resp_dcachewrite_cache_disable), //output
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.resp_dcachewrite_address (resp_dcachewrite_address), //output [31:0]
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.resp_dcachewrite_write_through (resp_dcachewrite_write_through), //output
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.resp_dcachewrite_data (resp_dcachewrite_data) //output [31:0]
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);
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//------------------------------------------------------------------------------
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wire tlbread_do;
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wire tlbread_done;
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wire tlbread_page_fault;
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wire tlbread_ac_fault;
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wire tlbread_retry;
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wire [1:0] tlbread_cpl;
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wire [31:0] tlbread_address;
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wire [3:0] tlbread_length;
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wire [3:0] tlbread_length_full;
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wire tlbread_lock;
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wire tlbread_rmw;
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wire [63:0] tlbread_data;
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//------------------------------------------------------------------------------
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wire tlbwrite_do;
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wire tlbwrite_done;
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wire tlbwrite_page_fault;
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wire tlbwrite_ac_fault;
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wire [1:0] tlbwrite_cpl;
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wire [31:0] tlbwrite_address;
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wire [2:0] tlbwrite_length;
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wire [2:0] tlbwrite_length_full;
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wire tlbwrite_lock;
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wire tlbwrite_rmw;
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wire [31:0] tlbwrite_data;
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//------------------------------------------------------------------------------
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wire icacheread_do;
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wire [31:0] icacheread_address;
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wire [4:0] icacheread_length; // takes into account: page size and cs segment limit
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//------------------------------------------------------------------------------
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wire prefetchfifo_write_do;
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wire [35:0] prefetchfifo_write_data;
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//------------------------------------------------------------------------------
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wire prefetched_do;
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wire [4:0] prefetched_length;
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//------------------------------------------------------------------------------
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wire [31:0] prefetch_address;
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wire [4:0] prefetch_length;
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wire prefetch_su;
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//------------------------------------------------------------------------------
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wire prefetchfifo_signal_limit_do;
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wire prefetchfifo_signal_pf_do;
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wire [4:0] prefetchfifo_used;
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//------------------------------------------------------------------------------
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wire tlbcoderequest_do;
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wire [31:0] tlbcoderequest_address;
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wire tlbcoderequest_su;
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//------------------------------------------------------------------------------
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wire tlbcode_do;
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wire [31:0] tlbcode_linear;
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wire [31:0] tlbcode_physical;
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wire tlbcode_cache_disable;
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//------------------------------------------------------------------------------
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wire [27:2] snoop_addr;
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wire [31:0] snoop_data;
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wire [3:0] snoop_be;
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wire snoop_we;
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//------------------------------------------------------------------------------
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avalon_mem avalon_mem_inst(
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// global
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.clk (clk),
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.rst_n (rst_n),
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//RESP:
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.writeburst_do (resp_dcachewrite_do), //input
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.writeburst_done (resp_dcachewrite_done), //output
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.writeburst_address (resp_dcachewrite_address), //input [31:0]
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.writeburst_length (resp_dcachewrite_length), //input [2:0]
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.writeburst_data_in (resp_dcachewrite_data), //input [31:0]
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//END
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//RESP:
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.readburst_do (resp_dcacheread_do), //input
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.readburst_done (resp_dcacheread_done), //output
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.readburst_address (resp_dcacheread_address), //input [31:0]
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.readburst_length (resp_dcacheread_length), //input [3:0]
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.readburst_data_out (resp_dcacheread_data), //output [63:0]
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//END
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//RESP:
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.readcode_do (req_readcode_do), //input
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.readcode_done (req_readcode_done), //output
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.readcode_address (req_readcode_address), //input [31:0]
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.readcode_partial (req_readcode_partial), //output [31:0]
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//END
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.snoop_addr (snoop_addr),
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.snoop_data (snoop_data),
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.snoop_be (snoop_be),
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.snoop_we (snoop_we),
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// avalon master
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.avm_address (avm_address), //output [31:0]
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.avm_writedata (avm_writedata), //output [31:0]
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.avm_byteenable (avm_byteenable), //output [3:0]
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.avm_burstcount (avm_burstcount), //output [3:0]
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.avm_write (avm_write), //output
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.avm_read (avm_read), //output
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.avm_waitrequest (avm_waitrequest), //input
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.avm_readdatavalid (avm_readdatavalid), //input
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.avm_readdata (avm_readdata), //input [31:0]
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.dma_address (dma_address),
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.dma_write (dma_write),
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.dma_writedata (dma_writedata),
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.dma_read (dma_read),
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.dma_readdata (dma_readdata),
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.dma_readdatavalid (dma_readdatavalid),
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.dma_waitrequest (dma_waitrequest)
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);
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//------------------------------------------------------------------------------
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assign invddata_done = 1'b1;
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assign wbinvddata_done = 1'b1;
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//------------------------------------------------------------------------------
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icache icache_inst(
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.clk (clk),
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.rst_n (rst_n),
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//RESP:
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.pr_reset (pr_reset), //input
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//END
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//RESP:
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.icacheread_do (icacheread_do), //input
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.icacheread_address (icacheread_address), //input [31:0]
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.icacheread_length (icacheread_length), //input [4:0] // takes into account: page size and cs segment limit
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//REQ:
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.readcode_do (req_readcode_do), //output
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.readcode_done (req_readcode_done), //input
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.readcode_address (req_readcode_address), //output [31:0]
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.readcode_partial (req_readcode_partial), //input [31:0]
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//END
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//REQ:
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.prefetchfifo_write_do (prefetchfifo_write_do), //output
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.prefetchfifo_write_data (prefetchfifo_write_data), //output [35:0]
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//END
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//REQ:
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.prefetched_do (prefetched_do), //output
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.prefetched_length (prefetched_length), //output [4:0]
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//END
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.snoop_addr (snoop_addr),
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.snoop_data (snoop_data),
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.snoop_be (snoop_be),
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.snoop_we (snoop_we)
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);
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assign invdcode_done = 1'b1;
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//------------------------------------------------------------------------------
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memory_read memory_read_inst(
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// global
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.clk (clk),
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.rst_n (rst_n),
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// read step
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.rd_reset (rd_reset), //input
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//RESP:
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.read_do (read_do), //input
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.read_done (read_done), //output
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.read_page_fault (read_page_fault), //output
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.read_ac_fault (read_ac_fault), //output
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.read_cpl (read_cpl), //input [1:0]
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.read_address (read_address), //input [31:0]
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.read_length (read_length), //input [3:0]
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.read_lock (read_lock), //input
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.read_rmw (read_rmw), //input
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.read_data (read_data), //output [63:0]
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//END
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//REQ:
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.tlbread_do (tlbread_do), //output
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.tlbread_done (tlbread_done), //input
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.tlbread_page_fault (tlbread_page_fault), //input
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.tlbread_ac_fault (tlbread_ac_fault), //input
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.tlbread_retry (tlbread_retry), //input
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.tlbread_cpl (tlbread_cpl), //output [1:0]
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.tlbread_address (tlbread_address), //output [31:0]
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.tlbread_length (tlbread_length), //output [3:0]
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.tlbread_length_full (tlbread_length_full), //output [3:0]
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.tlbread_lock (tlbread_lock), //output
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.tlbread_rmw (tlbread_rmw), //output
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.tlbread_data (tlbread_data) //input [63:0]
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//END
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);
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//------------------------------------------------------------------------------
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memory_write memory_write_inst(
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.clk (clk),
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.rst_n (rst_n),
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// write step
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.wr_reset (wr_reset), //input
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//RESP:
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.write_do (write_do), //input
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.write_done (write_done), //output
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.write_page_fault (write_page_fault), //output
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.write_ac_fault (write_ac_fault), //output
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.write_cpl (write_cpl), //input [1:0]
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.write_address (write_address), //input [31:0]
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.write_length (write_length), //input [2:0]
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.write_lock (write_lock), //input
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.write_rmw (write_rmw), //input
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.write_data (write_data), //input [31:0]
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//END
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//REQ:
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.tlbwrite_do (tlbwrite_do), //output
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.tlbwrite_done (tlbwrite_done), //input
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.tlbwrite_page_fault (tlbwrite_page_fault), //input
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.tlbwrite_ac_fault (tlbwrite_ac_fault), //input
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.tlbwrite_cpl (tlbwrite_cpl), //output [1:0]
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.tlbwrite_address (tlbwrite_address), //output [31:0]
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.tlbwrite_length (tlbwrite_length), //output [2:0]
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.tlbwrite_length_full (tlbwrite_length_full), //output [2:0]
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|
.tlbwrite_lock (tlbwrite_lock), //output
|
|
.tlbwrite_rmw (tlbwrite_rmw), //output
|
|
.tlbwrite_data (tlbwrite_data) //output [31:0]
|
|
//END
|
|
|
|
);
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
prefetch prefetch_inst(
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.pr_reset (pr_reset), //input
|
|
|
|
// prefetch exported
|
|
.prefetch_cpl (prefetch_cpl), //input [1:0]
|
|
.prefetch_eip (prefetch_eip), //input [31:0]
|
|
.cs_cache (cs_cache), //input [63:0]
|
|
|
|
//to prefetch_control
|
|
.prefetch_address (prefetch_address), //output [31:0]
|
|
.prefetch_length (prefetch_length), //output [4:0]
|
|
.prefetch_su (prefetch_su), //output
|
|
|
|
//RESP:
|
|
.prefetched_do (prefetched_do), //input
|
|
.prefetched_length (prefetched_length), //input [4:0]
|
|
//END
|
|
|
|
//REQ:
|
|
.prefetchfifo_signal_limit_do (prefetchfifo_signal_limit_do) //output
|
|
//END
|
|
);
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
prefetch_fifo prefetch_fifo_inst(
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.pr_reset (pr_reset), //input
|
|
|
|
//RESP:
|
|
.prefetchfifo_signal_limit_do (prefetchfifo_signal_limit_do), //input
|
|
//END
|
|
|
|
//RESP:
|
|
.prefetchfifo_signal_pf_do (prefetchfifo_signal_pf_do), //input
|
|
//END
|
|
|
|
//RESP:
|
|
.prefetchfifo_write_do (prefetchfifo_write_do), //input
|
|
.prefetchfifo_write_data (prefetchfifo_write_data), //input [35:0]
|
|
//END
|
|
|
|
.prefetchfifo_used (prefetchfifo_used), //output [4:0]
|
|
|
|
//RESP:
|
|
.prefetchfifo_accept_do (prefetchfifo_accept_do), //input
|
|
.prefetchfifo_accept_data (prefetchfifo_accept_data), //output [67:0]
|
|
.prefetchfifo_accept_empty (prefetchfifo_accept_empty) //output
|
|
//END
|
|
);
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
|
|
prefetch_control prefetch_control_inst(
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.pr_reset (pr_reset), //input //same as reset to icache
|
|
|
|
//REQ:
|
|
.tlbcoderequest_do (tlbcoderequest_do), //output
|
|
.tlbcoderequest_address (tlbcoderequest_address), //output [31:0]
|
|
.tlbcoderequest_su (tlbcoderequest_su), //output
|
|
//END
|
|
|
|
//RESP:
|
|
.tlbcode_do (tlbcode_do), //input
|
|
.tlbcode_linear (tlbcode_linear), //input [31:0]
|
|
.tlbcode_physical (tlbcode_physical), //input [31:0]
|
|
.tlbcode_cache_disable (tlbcode_cache_disable), //input
|
|
//END
|
|
|
|
//from prefetch
|
|
.prefetch_address (prefetch_address), //input [31:0]
|
|
.prefetch_length (prefetch_length), //input [4:0]
|
|
.prefetch_su (prefetch_su), //input
|
|
|
|
//from prefetchfifo
|
|
.prefetchfifo_used (prefetchfifo_used), //input [4:0]
|
|
|
|
//REQ
|
|
.icacheread_do (icacheread_do), //output
|
|
.icacheread_address (icacheread_address), //output [31:0]
|
|
.icacheread_length (icacheread_length), //output [4:0] // takes into account: page size and cs segment limit
|
|
.icacheread_cache_disable () //output
|
|
//END
|
|
);
|
|
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
tlb tlb_inst(
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.pr_reset (pr_reset), //input
|
|
.rd_reset (rd_reset), //input
|
|
.exe_reset (exe_reset), //input
|
|
.wr_reset (wr_reset), //input
|
|
|
|
// tlb exported
|
|
.cr0_pg (cr0_pg), //input
|
|
.cr0_wp (cr0_wp), //input
|
|
.cr0_am (cr0_am), //input
|
|
.cr0_cd (cr0_cd), //input
|
|
.cr0_nw (cr0_nw), //input
|
|
|
|
.acflag (acflag), //input
|
|
|
|
.cr3 (cr3), //input [31:0]
|
|
|
|
.pipeline_after_read_empty (pipeline_after_read_empty), //input
|
|
.pipeline_after_prefetch_empty (pipeline_after_prefetch_empty), //input
|
|
|
|
.tlb_code_pf_cr2 (tlb_code_pf_cr2), //output [31:0]
|
|
.tlb_code_pf_error_code (tlb_code_pf_error_code), //output [15:0]
|
|
|
|
.tlb_check_pf_cr2 (tlb_check_pf_cr2), //output [31:0]
|
|
.tlb_check_pf_error_code (tlb_check_pf_error_code), //output [15:0]
|
|
|
|
.tlb_write_pf_cr2 (tlb_write_pf_cr2), //output [31:0]
|
|
.tlb_write_pf_error_code (tlb_write_pf_error_code), //output [15:0]
|
|
|
|
.tlb_read_pf_cr2 (tlb_read_pf_cr2), //output [31:0]
|
|
.tlb_read_pf_error_code (tlb_read_pf_error_code), //output [15:0]
|
|
|
|
//RESP:
|
|
.tlbflushsingle_do (tlbflushsingle_do), //input
|
|
.tlbflushsingle_done (tlbflushsingle_done), //output
|
|
|
|
.tlbflushsingle_address (tlbflushsingle_address), //input
|
|
//END
|
|
|
|
//RESP:
|
|
.tlbflushall_do (tlbflushall_do), //input
|
|
//END
|
|
|
|
//RESP:
|
|
.tlbread_do (tlbread_do), //input
|
|
.tlbread_done (tlbread_done), //output
|
|
.tlbread_page_fault (tlbread_page_fault), //output
|
|
.tlbread_ac_fault (tlbread_ac_fault), //output
|
|
.tlbread_retry (tlbread_retry), //output
|
|
|
|
.tlbread_cpl (tlbread_cpl), //input [1:0]
|
|
.tlbread_address (tlbread_address), //input [31:0]
|
|
.tlbread_length (tlbread_length), //input [3:0]
|
|
.tlbread_length_full (tlbread_length_full), //input [3:0]
|
|
.tlbread_lock (tlbread_lock), //input
|
|
.tlbread_rmw (tlbread_rmw), //input
|
|
.tlbread_data (tlbread_data), //output [63:0]
|
|
//END
|
|
|
|
//RESP:
|
|
.tlbwrite_do (tlbwrite_do), //input
|
|
.tlbwrite_done (tlbwrite_done), //output
|
|
.tlbwrite_page_fault (tlbwrite_page_fault), //output
|
|
.tlbwrite_ac_fault (tlbwrite_ac_fault), //output
|
|
|
|
.tlbwrite_cpl (tlbwrite_cpl), //input [1:0]
|
|
.tlbwrite_address (tlbwrite_address), //input [31:0]
|
|
.tlbwrite_length (tlbwrite_length), //input [2:0]
|
|
.tlbwrite_length_full (tlbwrite_length_full), //input [2:0]
|
|
.tlbwrite_lock (tlbwrite_lock), //input
|
|
.tlbwrite_rmw (tlbwrite_rmw), //input
|
|
.tlbwrite_data (tlbwrite_data), //input [31:0]
|
|
//END
|
|
|
|
//RESP:
|
|
.tlbcheck_do (tlbcheck_do), //input
|
|
.tlbcheck_done (tlbcheck_done), //output
|
|
.tlbcheck_page_fault (tlbcheck_page_fault), //output
|
|
|
|
.tlbcheck_address (tlbcheck_address), //input [31:0]
|
|
.tlbcheck_rw (tlbcheck_rw), //input
|
|
//END
|
|
|
|
//REQ:
|
|
.dcacheread_do (req_dcacheread_do),
|
|
.dcacheread_done (req_dcacheread_done),
|
|
|
|
.dcacheread_length (req_dcacheread_length),
|
|
.dcacheread_cache_disable (req_dcacheread_cache_disable),
|
|
.dcacheread_address (req_dcacheread_address),
|
|
.dcacheread_data (req_dcacheread_data),
|
|
//END
|
|
|
|
//REQ:
|
|
.dcachewrite_do (req_dcachewrite_do), //output
|
|
.dcachewrite_done (req_dcachewrite_done), //input
|
|
|
|
.dcachewrite_length (req_dcachewrite_length), //output [2:0]
|
|
.dcachewrite_cache_disable (req_dcachewrite_cache_disable), //output
|
|
.dcachewrite_address (req_dcachewrite_address), //output [31:0]
|
|
.dcachewrite_write_through (req_dcachewrite_write_through), //output
|
|
.dcachewrite_data (req_dcachewrite_data), //output [31:0]
|
|
//END
|
|
|
|
//RESP:
|
|
.tlbcoderequest_do (tlbcoderequest_do), //input
|
|
.tlbcoderequest_address (tlbcoderequest_address), //input [31:0]
|
|
.tlbcoderequest_su (tlbcoderequest_su), //input
|
|
//END
|
|
|
|
//REQ:
|
|
.tlbcode_do (tlbcode_do), //output
|
|
.tlbcode_linear (tlbcode_linear), //output [31:0]
|
|
.tlbcode_physical (tlbcode_physical), //output [31:0]
|
|
.tlbcode_cache_disable (tlbcode_cache_disable), //output
|
|
//END
|
|
|
|
//REQ:
|
|
.prefetchfifo_signal_pf_do (prefetchfifo_signal_pf_do) //output
|
|
//END
|
|
);
|
|
|
|
|
|
|
|
endmodule
|