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108 lines
3.9 KiB
Verilog
108 lines
3.9 KiB
Verilog
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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module prefetch(
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input clk,
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input rst_n,
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input pr_reset,
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input [1:0] prefetch_cpl,
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input [31:0] prefetch_eip,
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input [63:0] cs_cache,
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//to tlb
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output [31:0] prefetch_address,
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output [4:0] prefetch_length,
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output prefetch_su,
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//RESP:
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input prefetched_do,
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input [4:0] prefetched_length,
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//END
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output prefetchfifo_signal_limit_do
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);
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//------------------------------------------------------------------------------
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reg [31:0] linear;
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reg [31:0] limit;
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reg limit_signaled;
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//------------------------------------------------------------------------------
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wire [4:0] length;
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wire [31:0] cs_base;
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wire [31:0] cs_limit;
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assign cs_base = { cs_cache[63:56], cs_cache[39:16] };
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assign cs_limit = cs_cache[`DESC_BIT_G]? { cs_cache[51:48], cs_cache[15:0], 12'hFFF } : { 12'd0, cs_cache[51:48], cs_cache[15:0] };
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//------------------------------------------------------------------------------
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assign prefetch_su = prefetch_cpl == 2'd3; //0=supervisor; 1=user
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assign prefetch_address = linear;
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assign prefetch_length = (limit > 32'd16)? 5'd16 : limit[4:0];
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assign length = (limit < { 27'd0, prefetched_length })? limit[4:0] : prefetched_length;
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assign prefetchfifo_signal_limit_do = limit == 32'd0 && limit_signaled == `FALSE;
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//------------------------------------------------------------------------------
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always @(posedge clk) begin
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if(rst_n == 1'b0) limit <= `STARTUP_PREFETCH_LIMIT;
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else if(pr_reset) limit <= (cs_limit >= prefetch_eip)? cs_limit - prefetch_eip + 32'd1 : 32'd0;
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else if(prefetched_do) limit <= limit - { 27'd0, length };
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) linear <= `STARTUP_PREFETCH_LINEAR;
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else if(pr_reset) linear <= cs_base + prefetch_eip;
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else if(prefetched_do) linear <= linear + { 27'd0, length };
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end
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always @(posedge clk) begin
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if(rst_n == 1'b0) limit_signaled <= `FALSE;
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else if(pr_reset) limit_signaled <= `FALSE;
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else if(prefetchfifo_signal_limit_do) limit_signaled <= `TRUE;
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end
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, cs_cache[54:52], cs_cache[47:40], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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endmodule
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