Updates since v1.0

.gitignore

@@ -52,3 +52,31 @@ nohup.out
 *bak
 *-backups
 *cache*
+CUPL/SFD700.ABS
+CUPL/SFD700.DOC
+CUPL/SFD700.JED
+CUPL/SFD700.JED.1
+CUPL/SFD700.JED.2
+CUPL/SFD700.JED.3
+CUPL/SFD700.JED.4
+CUPL/SFD700.JED.5
+CUPL/SFD700.JED.6
+CUPL/SFD700.JED.7
+CUPL/SFD700.PLD.v1.0
+CUPL/SFD700.bk
+CUPL/SFD700_1.ABS
+CUPL/SFD700_1.DOC
+CUPL/SFD700_2.ABS
+CUPL/SFD700_2.DOC
+CUPL/SFD700_G.JED
+CUPL/test
+CUPL/testabc
+CUPL/testit
+CUPL/x
+CPLD/v1.2/build/db/
+CPLD/v1.2/build/incremental_db/
+CPLD/v1.2/build/output_files/
+CPLD/v1.2/build/simulation/
+CPLD/v1.2/build/x
+CPLD/v1.2/sfd700.vhd.working12082023
+CPLD/v1.2/tzpuFusionX.vhd.old

CPLD/v1.2/build/sfd700.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 14:14:16  November 28, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "14:14:16  July 27, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "sfd700"

CPLD/v1.2/build/sfd700.qsf

@@ -0,0 +1,163 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 16:29:32  June 24, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		tzpuFusionX_MZ700.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY MAX7000S
+set_global_assignment -name DEVICE "EPM7128SLC84-15"
+set_global_assignment -name TOP_LEVEL_ENTITY sfd700
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32  JULY 27, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
+
+
+# Z80 Address Bus
+# ===============
+set_location_assignment PIN_4 -to Z80_ADDR[0]
+set_location_assignment PIN_5 -to Z80_ADDR[1]
+set_location_assignment PIN_6 -to Z80_ADDR[2]
+set_location_assignment PIN_8 -to Z80_ADDR[3]
+set_location_assignment PIN_9 -to Z80_ADDR[4]
+set_location_assignment PIN_10 -to Z80_ADDR[5]
+set_location_assignment PIN_11 -to Z80_ADDR[6]
+set_location_assignment PIN_15 -to Z80_ADDR[7]
+set_location_assignment PIN_16 -to Z80_ADDR[8]
+set_location_assignment PIN_17 -to Z80_ADDR[9]
+set_location_assignment PIN_18 -to Z80_ADDR[10]
+set_location_assignment PIN_20 -to Z80_ADDR[11]
+set_location_assignment PIN_21 -to Z80_ADDR[12]
+set_location_assignment PIN_22 -to Z80_ADDR[13]
+set_location_assignment PIN_24 -to Z80_ADDR[14]
+set_location_assignment PIN_25 -to Z80_ADDR[15]
+
+# Z80 Data Bus
+# ============
+set_location_assignment PIN_27 -to Z80_DATA[0]
+set_location_assignment PIN_28 -to Z80_DATA[1]
+set_location_assignment PIN_29 -to Z80_DATA[2]
+set_location_assignment PIN_30 -to Z80_DATA[3]
+set_location_assignment PIN_31 -to Z80_DATA[4]
+set_location_assignment PIN_33 -to Z80_DATA[5]
+set_location_assignment PIN_34 -to Z80_DATA[6]
+set_location_assignment PIN_35 -to Z80_DATA[7]
+
+# Z80 Control signals.
+# ====================
+set_location_assignment PIN_36 -to Z80_M1n
+set_location_assignment PIN_37 -to Z80_RDn
+set_location_assignment PIN_39 -to Z80_WRn
+set_location_assignment PIN_40 -to Z80_IORQn
+set_location_assignment PIN_41 -to Z80_MREQn
+set_location_assignment PIN_44 -to Z80_INT
+set_location_assignment PIN_45 -to Z80_EXWAITn
+
+# Mode Select
+# ===========
+set_location_assignment PIN_49 -to MODE[0]
+set_location_assignment PIN_48 -to MODE[1]
+set_location_assignment PIN_50 -to MODE[2]
+
+# Inverted Data Bus
+# =================
+set_location_assignment PIN_74 -to ID[0]
+set_location_assignment PIN_73 -to ID[1]
+set_location_assignment PIN_70 -to ID[2]
+set_location_assignment PIN_69 -to ID[3]
+set_location_assignment PIN_68 -to ID[4]
+set_location_assignment PIN_67 -to ID[5]
+set_location_assignment PIN_65 -to ID[6]
+set_location_assignment PIN_64 -to ID[7]
+
+# FDC Control Signals
+# ===================
+set_location_assignment PIN_63 -to FDCn
+set_location_assignment PIN_61 -to INTRQ
+set_location_assignment PIN_60 -to DRQ
+set_location_assignment PIN_58 -to DDENn
+set_location_assignment PIN_57 -to SIDE1
+set_location_assignment PIN_56 -to MOTOR
+set_location_assignment PIN_55 -to DRVSAn
+set_location_assignment PIN_54 -to DRVSBn
+set_location_assignment PIN_52 -to DRVSCn
+set_location_assignment PIN_51 -to DRVSDn
+
+# Memory Control Signals
+# ======================
+set_location_assignment PIN_80 -to ROM_A10
+set_location_assignment PIN_79 -to RAM_A10
+set_location_assignment PIN_77 -to ROM_CSn
+set_location_assignment PIN_76 -to RAM_CSn
+set_location_assignment PIN_75 -to RSV
+
+# Clocks
+# ======
+set_location_assignment PIN_81 -to CLK_FDC
+set_location_assignment PIN_83 -to CLK_16M
+set_location_assignment PIN_2 -to CLK_BUS0
+
+set_global_assignment -name VHDL_FILE ../sfd700_Toplevel.vhd
+set_global_assignment -name VHDL_FILE ../sfd700_pkg.vhd
+set_global_assignment -name VHDL_FILE ../sfd700.vhd
+set_global_assignment -name SDC_FILE sfd700_constraints.sdc
+
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
+set_global_assignment -name AUTO_RESOURCE_SHARING OFF
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF
+
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF
+set_global_assignment -name AUTO_LCELL_INSERTION ON
+
+set_global_assignment -name CDF_FILE output_files/sfd700.cdf
+
+set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15

CPLD/v1.2/build/sfd700_constraints.sdc

@@ -0,0 +1,138 @@
+## Generated SDC file "tzpuFusionX.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
+
+## DATE    "Fri Jun 26 22:10:05 2020"
+
+##
+## DEVICE  "EPM7160STC100-10"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+# Standard mainboard clock. Varies so take 4MHz being maximum.
+#create_clock -name {CLK_BUS0} -period 250.00 -waveform { 0.000 125.000 } [get_ports { CLK_BUS0 }]
+
+# For 16MHz crystal.
+create_clock -name {CLK_16M} -period 62.500 -waveform { 0.000 31.250 }   [ get_ports { CLK_16M }]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_ADDR[*]}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_DATA[*]}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {ID[*]}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_WRn}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_RDn}]
+#set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_M1n}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_MREQn}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_IORQn}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_RESETn}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {MODE[*]}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {INTRQ}]
+set_input_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {DRQ}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_DATA[*]}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {ID[*]}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_INT}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {Z80_EXWAITn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {ROM_A10}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {RAM_A10}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {ROM_CSn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {RAM_CSn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {RSV}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {FDCn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {DDENn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {SIDE1}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {MOTOR}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {DRVSAn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {DRVSBn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {DRVSCn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {DRVSDn}]
+set_output_delay -add_delay  -clock [get_clocks {CLK_16M}]  1.000 [get_ports {CLK_FDC}]
+
+#**************************************************************
+# Set Max Delay
+#**************************************************************
+
+#**************************************************************
+# Set Min Delay
+#**************************************************************
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************

CPLD/v1.2/sfd700.vhd

@@ -0,0 +1,476 @@
+-------------------------------------------------------------------------------------------------------
+--
+-- Name:            sfd700.vhd
+-- Created:         July 2023
+-- Author(s):       Philip Smart
+-- Description:     SFD700 CPLD configuration file.
+--                                                     
+--                  This module contains parameters for the CPLD in the SFD700 Floppy Disk Interface
+--                  project.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-23 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2023 - v1.0 - Initial write.
+
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.sfd700_pkg.all;
+
+entity cpld128 is
+    port (    
+        -- Z80 Address Bus
+        Z80_ADDR                  : in    std_logic_vector(15 downto 0);       -- Host Address Bus.
+                                                                                                             
+        -- Z80 Data Bus                                                                                      
+        Z80_DATA                  : inout std_logic_vector(7 downto 0);        -- Host Data Bus.
+                                                                                                             
+        -- Z80 Control signals.                                                                              
+        Z80_M1n                   : in    std_logic;                           -- Host M1n input.
+        Z80_RDn                   : in    std_logic;                           -- Host RDn input.
+        Z80_WRn                   : in    std_logic;                           -- Host WRn input.
+        Z80_IORQn                 : in    std_logic;                           -- Host IORQn input.
+        Z80_MREQn                 : in    std_logic;                           -- Host MREQn input.
+        Z80_INT                   : out   std_logic;                           -- Host INT output, active high.
+        Z80_EXWAITn               : out   std_logic;                           -- Host external Wait output.
+
+            -- Reset.
+        Z80_RESETn                : in    std_logic;                           -- Host RESET signal.
+
+        -- Inverted Data to FDC and High Address Bits to ROM/RAM.
+        ID                        : inout std_logic_vector(7 downto 0);
+
+        -- ROM/RAM Control Signals.
+        ROM_A10                   : out   std_logic;                           -- Flash ROM A10 line - additional address bit and used for MZ-80A DRQ code selection.
+        RAM_A10                   : out   std_logic;                           -- RAM A10 line - additional address bit.
+        ROM_CSn                   : out   std_logic;                           -- Chip select for Flash ROM.
+        RAM_CSn                   : out   std_logic;                           -- Chip select for Flash RAM.
+        RSV                       : out   std_logic;                           -- Reserved.
+
+        -- Interface Configuration.
+        MODE                      : in    std_logic_vector(2 downto 0);        -- Jumper settings to configure interface behaviour.
+
+        -- Floppy Disk Interface.
+        FDCn                      : out   std_logic;                           -- WD1773 chip select.
+        INTRQ                     : in    std_logic;                           -- WD1773 Interrupt.
+        DRQ                       : in    std_logic;                           -- WD1773 Data Request.
+        DDENn                     : out   std_logic;                           -- WD1773 Double Data Rate Enable.
+        SIDE1                     : out   std_logic;                           -- Side 1 of disk select.
+        MOTOR                     : out   std_logic;                           -- Motor on signal.
+        DRVSAn                    : out   std_logic;                           -- Drive A select.
+        DRVSBn                    : out   std_logic;                           -- Drive B select.
+        DRVSCn                    : out   std_logic;                           -- Drive C select.
+        DRVSDn                    : out   std_logic;                           -- Drive D select.
+
+        -- Clocks.
+        CLK_16M                   : in    std_logic;                           -- 16MHz primary oscillator.
+        CLK_FDC                   : out   std_logic;                           -- 8MHz clock to drive WD1773.
+        CLK_BUS0                  : in    std_logic                            -- Host clock.
+    );
+end entity;
+
+architecture rtl of cpld128 is
+
+    -- CPU Interface internal signals.
+    signal Z80_M1ni               :       std_logic;
+    signal Z80_RDni               :       std_logic;
+    signal Z80_WRni               :       std_logic;
+    signal Z80_IORQni             :       std_logic;
+    signal Z80_MREQni             :       std_logic;
+    signal Z80_INTi               :       std_logic;
+    signal Z80_EXWAITni           :       std_logic;
+
+    -- Internal CPU state control.
+    signal MEM_ADDR               :       std_logic_vector(15 downto 0) := (others => '0');
+
+    -- Select signals.
+    signal MEM_EXXX_SELni         :       std_logic;
+    signal MEM_FXXX_SELni         :       std_logic;
+    signal FDC_SELni              :       std_logic;
+    signal DRIVE_WR_SELni         :       std_logic;
+    signal DDEN_WR_SELni          :       std_logic;
+    signal SIDE_WR_SELni          :       std_logic;
+    signal INTEN_SELni            :       std_logic;
+    signal EXXX_RD_SELni          :       std_logic;
+    signal EXXX_WR_SELni          :       std_logic;
+    signal FXXX_RD_SELni          :       std_logic;
+    signal FXXX_WR_SELni          :       std_logic;
+    signal RAMEN_RD_SELni         :       std_logic;
+    signal RAMEN_WR_SELni         :       std_logic;
+    signal MODE_RD_SELni          :       std_logic;
+    signal ROMINHSET_WR_SELni     :       std_logic;
+    signal ROMINHCLR_WR_SELni     :       std_logic;
+    signal ROMDISSET_WR_SELni     :       std_logic;
+    signal ROMDISCLR_WR_SELni     :       std_logic;
+    signal ROM_SELni              :       std_logic;
+    signal RAM_SELni              :       std_logic;
+
+    -- Registers.
+    signal REG_DRIVEA             :       std_logic;
+    signal REG_DRIVEB             :       std_logic;
+    signal REG_DRIVEC             :       std_logic;
+    signal REG_DRIVED             :       std_logic;
+    signal REG_MOTOR              :       std_logic;
+    signal REG_SIDE               :       std_logic;
+    signal REG_DDEN               :       std_logic;
+    signal REG_INT                :       std_logic;
+    signal REG_EXXX_PAGE          :       std_logic_vector(6 downto 0);
+    signal REG_FXXX_PAGE          :       std_logic_vector(6 downto 0);
+    signal REG_ROMDIS             :       std_logic;
+    signal REG_ROMINH             :       std_logic;
+    signal REG_RAMEN              :       std_logic;
+
+    -- Selected mode of the interface, ie. which machine it will be plugged into.
+    signal IFMODE                 :       integer range 0 to 7 := 0;
+
+    -- Clocks.
+    signal CLK_8Mi                :       std_logic := '0';
+
+    -- Functions.
+    function to_std_logic(L: boolean) return std_logic is
+    begin
+        if L then
+            return('1');
+        else
+            return('0');
+        end if;
+    end function to_std_logic;
+begin
+
+    -- Create FDC Clock based on primary clock.
+    FDCCLK: process( CLK_16M )
+    begin
+        if(rising_edge(CLK_16M)) then
+            CLK_8Mi              <= not CLK_8Mi;
+        end if;
+    end process;
+
+    -- Process to register configuration mode on reset.
+    SETMODE: process( Z80_RESETn, MODE )
+    begin
+        if(Z80_RESETn = '0') then
+            -- Configuration jumpers specify the machine the SFD700 card will be used with.
+            IFMODE               <= to_integer(unsigned(MODE));
+        end if;
+    end process;
+
+    -- Set Floppy Disk Side.
+    -- A write to 0xDD bit D0 = low sets Floppy Disk side 1, high sets side 0.
+    SETSIDE: process( Z80_RESETn, CLK_16M, SIDE_WR_SELni )
+        variable SIDE_SEL_LASTni : std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            REG_SIDE             <= '0';
+            SIDE_SEL_LASTni      := '0';
+
+        elsif(rising_edge(CLK_16M)) then
+            if(SIDE_WR_SELni = '0' and SIDE_SEL_LASTni = '1') then
+                REG_SIDE         <= not Z80_DATA(0);
+            end if;
+            SIDE_SEL_LASTni      := SIDE_WR_SELni;
+        end if;
+    end process;
+
+    -- Set Double Data Rate Enable.
+    -- A write to 0xDE bit D0 = low enables double data rate, high enables single data rate.
+    SETDDEN: process( Z80_RESETn, CLK_16M, DDEN_WR_SELni )
+        variable DDEN_SEL_LASTni : std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            REG_DDEN             <= '1';
+            DDEN_SEL_LASTni      := '0';
+
+        elsif(rising_edge(CLK_16M)) then
+            if(DDEN_WR_SELni = '0' and DDEN_SEL_LASTni = '1') then
+                REG_DDEN         <= not Z80_DATA(0);
+            end if;
+            DDEN_SEL_LASTni      := DDEN_WR_SELni;
+        end if;
+    end process;
+
+    -- Set Drive Number and Motor
+    -- A write to 0xDC, bits D2:0 sets the active drive. Bit 2 high enables the active drive, low disables all drives.
+    -- Bit D7 enables the motor.
+    SETDRIVE: process( Z80_RESETn, CLK_16M, DRIVE_WR_SELni )
+        variable DRIVE_SEL_LASTni: std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            REG_DRIVEA           <= '0';
+            REG_DRIVEB           <= '0';
+            REG_DRIVEC           <= '0';
+            REG_DRIVED           <= '0';
+            REG_MOTOR            <= '0';
+            DRIVE_SEL_LASTni     := '0';
+
+        elsif(rising_edge(CLK_16M)) then
+            if(DRIVE_WR_SELni = '0' and DRIVE_SEL_LASTni = '1') then
+                REG_DRIVEA       <= '0';
+                REG_DRIVEB       <= '0';
+                REG_DRIVEC       <= '0';
+                REG_DRIVED       <= '0';
+                REG_MOTOR        <= Z80_DATA(7);
+                case(to_integer(unsigned(Z80_DATA(2 downto 0)))) is
+                    when 0 =>
+
+                    when 4 =>
+                        REG_DRIVEA <= '1';
+                    when 5 =>
+                        REG_DRIVEB <= '1';
+                    when 6 =>
+                        REG_DRIVEC <= '1';
+                    when 7 =>
+                        REG_DRIVED <= '1';
+
+                    when others =>
+                end case;
+            end if;
+            DRIVE_SEL_LASTni       := DRIVE_WR_SELni;
+        end if;
+    end process;
+
+    -- Set Interrupt Enable
+    -- A write to 0xDF enables WD1773 interrupts, a read from 0xDF disables WD1773 interrupts.
+    SETINT: process( Z80_RESETn, CLK_16M, INTEN_SELni )
+        variable INTEN_SEL_LASTni: std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            REG_INT              <= '0';
+            INTEN_SEL_LASTni     := '0';
+
+        elsif(rising_edge(CLK_16M)) then
+            if(INTEN_SELni = '0' and INTEN_SEL_LASTni = '1') then
+                REG_INT          <= Z80_RDn;
+            end if;
+            INTEN_SEL_LASTni     := INTEN_SELni;
+        end if;
+    end process;
+
+    -- Set FlashROM/RAM EXXX (E300:EFFF) page address. Each bank is 4K but due to the memory mapped I/O, only
+    -- E300:EFFF is useable in RFS.
+    -- A write t0 0x60 copies D6:0 into the EXXX page address register which selects a required 4K page in region E300:EFFF
+    SETEXXXPAGE: process( Z80_RESETn, CLK_16M, IFMODE, EXXX_WR_SELni )
+        variable EXXX_SEL_LASTni : std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            -- Customised UROM containing RFS start bank.
+            REG_EXXX_PAGE        <= "0000010";
+            EXXX_SEL_LASTni      := '0';
+            
+        elsif(rising_edge(CLK_16M)) then
+            if(EXXX_WR_SELni = '0' and EXXX_SEL_LASTni = '1') then
+                REG_EXXX_PAGE    <= Z80_DATA(6 downto 0);
+            end if;
+            EXXX_SEL_LASTni      := EXXX_WR_SELni;
+        end if;
+    end process;
+
+    -- Set FlashROM/RAM FXXX (F000:FFFF) page address.
+    -- A write to 0x61 copies D6:0 into the FXXX page address register which selects a 4K page
+    -- window of ROM/RAM accessible in the FXXX window.
+    SETFXXXPAGE: process( Z80_RESETn, CLK_16M, IFMODE, FXXX_WR_SELni )
+        variable FXXX_SEL_LASTni : std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            -- Initial page is set to 0, which is the MZ-80A AFI ROM. The original ROM is 2K so potential to add additional code in the upper block.
+            REG_FXXX_PAGE        <= (others => '0');
+
+            -- MZ-700, starting at the second 4k page, set banking registers to 4K block which stores the MZ-700 AFI ROM.
+            if(IFMODE = MODE_MZ700) then
+                REG_FXXX_PAGE(1 downto 0) <= "01";
+            end if;
+
+        elsif(rising_edge(CLK_16M)) then
+
+            -- Set 4k F000:FFFF page address.
+            if(FXXX_WR_SELni = '0' and FXXX_SEL_LASTni = '1') then
+                REG_FXXX_PAGE    <= Z80_DATA(6 downto 0);
+            end if;
+
+            -- Edge detection.
+            FXXX_SEL_LASTni      := FXXX_WR_SELni;
+        end if;
+    end process;
+
+    -- Enable FlashROM or RAM.
+    -- A write to 0x62 with D0 = low enables FlashROM, D0 = high enables RAM.
+    SETRAMEN: process( Z80_RESETn, CLK_16M, RAMEN_WR_SELni )
+        variable RAMEN_SEL_LASTni: std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            REG_RAMEN            <= '0';
+
+        elsif(rising_edge(CLK_16M)) then
+            if(RAMEN_WR_SELni = '0' and RAMEN_SEL_LASTni = '1') then
+                REG_RAMEN        <= Z80_DATA(0);
+            end if;
+            RAMEN_SEL_LASTni     := RAMEN_WR_SELni;
+        end if;
+    end process;
+
+    -- MZ-700/MZ-1500 paged memory logic. Detect the memory paging I/O operations and enable/disable access to the onboard FlashROM/RAM.
+    --
+    -- MZ-700 Memory Management Ports                                  
+    --            |0000:0FFF|1000:CFFF|D000:FFFF                      
+    --            ------------------------------                      
+    -- OUT 0xE0 = |DRAM     |         |                               
+    -- OUT 0xE1 = |         |         |DRAM                           
+    -- OUT 0xE2 = |MONITOR  |         |                               
+    -- OUT 0xE3 = |         |         |Memory Mapped I/O              
+    -- OUT 0xE4 = |MONITOR  |DRAM     |Memory Mapped I/O             
+    -- OUT 0xE5 = |         |         |Inhibit                        
+    -- OUT 0xE6 = |         |         |<return>                       
+    --
+    -- A write to 0xE1 enables RAM in the region 0xD000:FFFF so the onboard FlashROM/RAM should be disabled. A write to 0xE3/0xE4 re-enables
+    -- FlashROM/RAM. A write to 0xE5 inhibits all access to region 0xD000:FFFF so the onboard FlashROM/RAM is disabled, write to 0xE6 re-enables it.
+    SETHIMEM: process( Z80_RESETn, CLK_16M, ROMINHSET_WR_SELni, ROMINHCLR_WR_SELni, ROMDISSET_WR_SELni, ROMDISCLR_WR_SELni )
+        variable ROMINHSET_LAST  : std_logic;
+        variable ROMINHCLR_LAST  : std_logic;
+        variable ROMDISSET_LAST  : std_logic;
+        variable ROMDISCLR_LAST  : std_logic;
+    begin
+        if(Z80_RESETn = '0') then
+            REG_ROMINH           <= '0';
+            REG_ROMDIS           <= '0';
+            ROMINHSET_LAST       := '0';
+            ROMINHCLR_LAST       := '0';
+            ROMDISSET_LAST       := '0';
+            ROMDISCLR_LAST       := '0';
+
+        elsif(rising_edge(CLK_16M)) then
+            if(ROMINHSET_WR_SELni = '0' and ROMINHSET_LAST = '1') then
+                REG_ROMINH       <= '1';
+            end if;
+            if(ROMINHCLR_WR_SELni = '0' and ROMINHCLR_LAST = '1') then
+                REG_ROMINH       <= '0';
+            end if;
+            if(ROMDISSET_WR_SELni = '0' and ROMDISSET_LAST = '1') then
+                REG_ROMDIS       <= '1';
+            end if;
+            if(ROMDISCLR_WR_SELni = '0' and ROMDISCLR_LAST = '1') then
+                REG_ROMDIS       <= '0';
+            end if;
+            ROMINHSET_LAST       := ROMINHSET_WR_SELni;
+            ROMINHCLR_LAST       := ROMINHCLR_WR_SELni;
+            ROMDISSET_LAST       := ROMDISSET_WR_SELni;
+            ROMDISCLR_LAST       := ROMDISCLR_WR_SELni;
+        end if;
+    end process;
+
+    -- Memory address select.
+    MEM_EXXX_SELni               <= '0'                                    when Z80_MREQn = '0' and unsigned(Z80_ADDR(15 downto 8)) >= X"E3" and unsigned(Z80_ADDR(15 downto 8)) < X"F0"
+                                    else '1';
+    MEM_FXXX_SELni               <= '0'                                    when Z80_MREQn = '0' and unsigned(Z80_ADDR(15 downto 8)) >= X"F0" and unsigned(Z80_ADDR(15 downto 8)) <= X"FF"
+                                    else '1';
+    ROM_SELni                    <= '0'                                    when (IFMODE = MODE_MZ700  or IFMODE = MODE_MZ1500) and REG_ROMINH = '0' and REG_ROMDIS = '0' and REG_RAMEN = '0' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
+                                    else
+                                    '0'                                    when (IFMODE = MODE_MZ1200 or IFMODE = MODE_MZ80A)                                            and REG_RAMEN = '0' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
+                                    else '1';
+    RAM_SELni                    <= '0'                                    when (IFMODE = MODE_MZ700  or IFMODE = MODE_MZ1500) and REG_ROMINH = '0' and REG_ROMDIS = '0' and REG_RAMEN = '1' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
+                                    else
+                                    '0'                                    when (IFMODE = MODE_MZ1200 or IFMODE = MODE_MZ80A)                                            and REG_RAMEN = '1' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
+                                    else '1';
+
+    -- I/O Port select.
+    FDC_SELni                    <= '0'                                    when Z80_IORQn = '0' and (Z80_WRn = '0' or Z80_RDn = '0') and unsigned(Z80_ADDR(7 downto 0)) >= X"D8" and unsigned(Z80_ADDR(7 downto 0)) < X"DC"
+                                    else '1';
+    DRIVE_WR_SELni               <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"DC"
+                                    else '1';
+    DDEN_WR_SELni                <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"DE"
+                                    else '1';
+    SIDE_WR_SELni                <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"DD"
+                                    else '1';
+    INTEN_SELni                  <= '0'                                    when Z80_IORQn = '0' and (Z80_WRn = '0' or Z80_RDn = '0') and unsigned(Z80_ADDR(7 downto 0)) = X"DF"
+                                    else '1';
+    EXXX_RD_SELni                <= '0'                                    when Z80_IORQn = '0' and Z80_RDn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"60"
+                                    else '1';
+    EXXX_WR_SELni                <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"60"
+                                    else '1';
+    FXXX_RD_SELni                <= '0'                                    when Z80_IORQn = '0' and Z80_RDn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"61"
+                                    else '1';
+    FXXX_WR_SELni                <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"61"
+                                    else '1';
+    RAMEN_RD_SELni               <= '0'                                    when Z80_IORQn = '0' and Z80_RDn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"62"
+                                    else '1';
+    RAMEN_WR_SELni               <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"62"
+                                    else '1';
+    MODE_RD_SELni                <= '0'                                    when Z80_IORQn = '0' and Z80_RDn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"63"
+                                    else '1';
+    ROMINHSET_WR_SELni           <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"E5"
+                                    else '1';
+    ROMINHCLR_WR_SELni           <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"E6"
+                                    else '1';
+    ROMDISSET_WR_SELni           <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and unsigned(Z80_ADDR(7 downto 0)) = X"E1"
+                                    else '1';
+    ROMDISCLR_WR_SELni           <= '0'                                    when Z80_IORQn = '0' and Z80_WRn = '0'                    and (unsigned(Z80_ADDR(7 downto 0)) = X"E3" or unsigned(Z80_ADDR(7 downto 0)) = X"E4")
+                                    else '1';
+
+    -- WD1773 master clock.
+    CLK_FDC                      <= CLK_8Mi;
+
+    -- Data bus control.
+    Z80_DATA                     <= not ID                                 when FDC_SELni = '0'     and Z80_WRn = '1'          -- WD1773
+                                    else
+                                    '0' & REG_EXXX_PAGE                    when EXXX_RD_SELni = '0'                            -- EXXX Register contents.
+                                    else
+                                    '0' & REG_FXXX_PAGE                    when FXXX_RD_SELni = '0'                            -- FXXX Register contents.
+                                    else
+                                    "0000000" & REG_RAMEN                  when RAMEN_RD_SELni = '0'                           -- ROM/RAM Enable register contents.
+                                    else
+                                    "00000" & MODE                         when MODE_RD_SELni = '0'                            -- Configured mode.
+                                    else
+                                    (others => 'Z');
+    -- ID is the inverted data bus, the WD1773 uses inverted data. ID doubles up as the FlashROM/RAM upper address bits when not being used for the WD1773.
+    ID                           <= not Z80_DATA                           when Z80_WRn = '0' and FDC_SELni = '0'
+                                    else
+                                    REG_EXXX_PAGE & Z80_ADDR(11)           when MEM_EXXX_SELni = '0'
+                                    else
+                                    REG_FXXX_PAGE & Z80_ADDR(11)           when MEM_FXXX_SELni = '0'
+                                    else
+                                    (others => 'Z');
+
+    -- Host interrupts and wait processing.
+    Z80_INT                      <= INTRQ                                  when REG_INT = '1'
+                                    else '0';
+    Z80_EXWAITni                 <= '1';
+    Z80_EXWAITn                  <= Z80_EXWAITni;
+
+    -- FlashROM/RAM Address A10 - this is used on the MZ-80A/MZ-1200 as a means of speeding up data retrieval from the WD1773 where DRQ is used as the address bit and dupliate ROM code appears in each 1K segment except the upper bytes, 0x3FE.
+    ROM_A10                      <= '1'                                    when (IFMODE = MODE_MZ1200 or IFMODE = MODE_MZ80A) and DRQ = '1'
+                                    else Z80_ADDR(10);
+    RAM_A10                      <= Z80_ADDR(10);
+
+    -- FlashROM/RAM Chip Select.
+    ROM_CSn                      <= ROM_SELni;
+    RAM_CSn                      <= RAM_SELni;
+
+    -- Floppy Disk Interface Signals.
+    FDCn                         <= FDC_SELni;
+    DRVSAn                       <= not REG_DRIVEA;
+    DRVSBn                       <= not REG_DRIVEB;
+    DRVSCn                       <= not REG_DRIVEC;
+    DRVSDn                       <= not REG_DRIVED;
+    MOTOR                        <= REG_MOTOR;
+    SIDE1                        <= not REG_SIDE;
+    DDENn                        <= not REG_DDEN;
+
+    -- Reserved pins.
+    RSV                          <= '0';
+
+end architecture;

CPLD/v1.2/sfd700_Toplevel.vhd

@@ -0,0 +1,144 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            sfd700_Toplevel.vhd
+-- Created:         July 2023
+-- Author(s):       Philip Smart
+-- Description:     SFD700 CPLD configuration file.
+--                                                     
+--                  This module contains parameters for the CPLD in the SFD700 Floppy Disk Interface
+--                  project.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-23 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2023 - Initial write.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.sfd700_pkg.all;
+library altera;
+use altera.altera_syn_attributes.all;
+
+entity sfd700 is
+    port (
+        -- Z80 Address Bus
+        Z80_ADDR                  : in    std_logic_vector(15 downto 0);       -- Host Address Bus.
+                                                                                                             
+        -- Z80 Data Bus                                                                                      
+        Z80_DATA                  : inout std_logic_vector(7 downto 0);        -- Host Data Bus.
+                                                                                                             
+        -- Z80 Control signals.                                                                              
+        Z80_M1n                   : in    std_logic;                           -- Host M1n input.
+        Z80_RDn                   : in    std_logic;                           -- Host RDn input.
+        Z80_WRn                   : in    std_logic;                           -- Host WRn input.
+        Z80_IORQn                 : in    std_logic;                           -- Host IORQn input.
+        Z80_MREQn                 : in    std_logic;                           -- Host MREQn input.
+        Z80_INT                   : out   std_logic;                           -- Host INT output, active high.
+        Z80_EXWAITn               : out   std_logic;                           -- Host external Wait output.
+
+        -- Reset.
+        Z80_RESETn                : in    std_logic;                           -- Host RESET signal.
+
+        -- Inverted Data to FDC and High Address Bits to ROM/RAM.
+        ID                        : inout std_logic_vector(7 downto 0);
+
+        -- ROM/RAM Control Signals.
+        ROM_A10                   : out   std_logic;                           -- Flash ROM A10 line - additional address bit and used for MZ-80A DRQ code selection.
+        RAM_A10                   : out   std_logic;                           -- RAM A10 line - additional address bit.
+        ROM_CSn                   : out   std_logic;                           -- Chip select for Flash ROM.
+        RAM_CSn                   : out   std_logic;                           -- Chip select for Flash RAM.
+        RSV                       : out   std_logic;                           -- Reserved.
+
+        -- Interface Configuration.
+        MODE                      : in    std_logic_vector(2 downto 0);        -- Jumper settings to configure interface behaviour.
+
+        -- Floppy Disk Interface.
+        FDCn                      : out   std_logic;                           -- WD1773 chip select.
+        INTRQ                     : in    std_logic;                           -- WD1773 Interrupt.
+        DRQ                       : in    std_logic;                           -- WD1773 Data Request.
+        DDENn                     : out   std_logic;                           -- WD1773 Double Data Rate Enable.
+        SIDE1                     : out   std_logic;                           -- Side 1 of disk select.
+        MOTOR                     : out   std_logic;                           -- Motor on signal.
+        DRVSAn                    : out   std_logic;                           -- Drive A select.
+        DRVSBn                    : out   std_logic;                           -- Drive B select.
+        DRVSCn                    : out   std_logic;                           -- Drive C select.
+        DRVSDn                    : out   std_logic;                           -- Drive D select.
+
+        -- Clocks.
+        CLK_16M                   : in    std_logic;                           -- 16MHz primary oscillator.
+        CLK_FDC                   : out   std_logic;                           -- 8MHz clock to drive WD1773.
+        CLK_BUS0                  : in    std_logic                            -- Host clock.
+    );
+END entity;
+
+architecture rtl of sfd700 is
+
+begin
+
+    cpldl128Toplevel : entity work.cpld128
+    port map
+    (    
+        -- Z80 Address Bus
+        Z80_ADDR                  => Z80_ADDR,                                 -- Host Address Bus.
+
+        -- Z80 Data Bus
+        Z80_DATA                  => Z80_DATA,                                 -- Host Data Bus.
+        
+        -- Z80 Control signals.
+        Z80_M1n                   => Z80_M1n,                                  -- Host M1n input.
+        Z80_RDn                   => Z80_RDn,                                  -- Host RDn input.
+        Z80_WRn                   => Z80_WRn,                                  -- Host WRn input.
+        Z80_IORQn                 => Z80_IORQn,                                -- Host IORQn input.
+        Z80_MREQn                 => Z80_MREQn,                                -- Host MREQn input.
+        Z80_INT                   => Z80_INT,                                  -- Host INT output, active high.
+        Z80_EXWAITn               => Z80_EXWAITn,                              -- Host external Wait output.
+
+        -- Reset.
+        Z80_RESETn                => Z80_RESETn,                               -- Host RESET signal.
+
+        -- Inverted Data to FDC and High Address Bits to ROM/RAM.
+        ID                        => ID,                                   
+
+        -- ROM/RAM Control Signals.
+        ROM_A10                   => ROM_A10,                                  -- Flash ROM A10 line - additional address bit and used for MZ-80A DRQ code selection.
+        RAM_A10                   => RAM_A10,                                  -- RAM A10 line - additional address bit.
+        ROM_CSn                   => ROM_CSn,                                  -- Chip select for Flash ROM.
+        RAM_CSn                   => RAM_CSn,                                  -- Chip select for Flash RAM.
+        RSV                       => RSV,                                      -- Reserved.
+
+        -- Interface Configuration.
+        MODE                      => MODE,                                     -- Jumper settings to configure interface behaviour.
+
+        -- Floppy Disk Interface.
+        FDCn                      => FDCn,                                     -- WD1773 chip select.
+        INTRQ                     => INTRQ,                                    -- WD1773 Interrupt.
+        DRQ                       => DRQ,                                      -- WD1773 Data Request.
+        DDENn                     => DDENn,                                    -- WD1773 Double Data Rate Enable.
+        SIDE1                     => SIDE1,                                    -- Side 1 of disk select.
+        MOTOR                     => MOTOR,                                    -- Motor on signal.
+        DRVSAn                    => DRVSAn,                                   -- Drive A select.
+        DRVSBn                    => DRVSBn,                                   -- Drive B select.
+        DRVSCn                    => DRVSCn,                                   -- Drive C select.
+        DRVSDn                    => DRVSDn,                                   -- Drive D select.
+
+        -- Clocks.
+        CLK_16M                   => CLK_16M,                                  -- 16MHz primary oscillator.
+        CLK_FDC                   => CLK_FDC,                                  -- 8MHz clock to drive WD1773.
+        CLK_BUS0                  => CLK_BUS0                                  -- Host clock.
+    );
+
+end architecture;

CPLD/v1.2/sfd700_pkg.vhd

@@ -0,0 +1,174 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            sfd700_pkg.vhd
+-- Created:         July 2023
+-- Author(s):       Philip Smart
+-- Description:     SFD700 CPLD configuration file.
+--                                                     
+--                  This module contains parameters for the CPLD in the SFD700 Floppy Disk Interface
+--                  project.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-23 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         July 2023 - Initial write.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+package sfd700_pkg is
+
+    ------------------------------------------------------------ 
+    -- Constants
+    ------------------------------------------------------------ 
+
+    -- Potential logic state constants.
+    constant YES                      : std_logic := '1';
+    constant NO                       : std_logic := '0';
+    constant HI                       : std_logic := '1';
+    constant LO                       : std_logic := '0';
+    constant ONE                      : std_logic := '1';
+    constant ZERO                     : std_logic := '0';
+    constant HIZ                      : std_logic := 'Z';
+
+    -- Target hardware modes.
+    constant MODE_MZ1200              : integer   := 0;
+    constant MODE_MZ80A               : integer   := 0;
+    constant MODE_MZ700               : integer   := 1;
+    constant MODE_MZ80B               : integer   := 2;
+    constant MODE_MZ800               : integer   := 3;
+    constant MODE_MZ1500              : integer   := 4;
+    constant MODE_MZ2000              : integer   := 5;
+    constant MODE_MZ2200              : integer   := 6;
+
+    ------------------------------------------------------------ 
+    -- Configurable parameters.
+    ------------------------------------------------------------ 
+
+    -- Version of hdl.
+    constant CPLD_VERSION             : integer   := 1;
+
+    ------------------------------------------------------------ 
+    -- Function prototypes
+    ------------------------------------------------------------ 
+    -- Find the maximum of two integers.
+    function IntMax(a : in integer; b : in integer) return integer;
+
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer;
+
+    -- Function to reverse the order of the bits in a standard logic vector.
+    -- ie. 1010 becomes 0101
+    function reverse_vector(slv:std_logic_vector) return std_logic_vector; 
+
+    -- Function to convert an integer (0 or 1) into std_logic.
+    --
+    function to_std_logic(i : in integer) return std_logic;
+
+    -- Function to return the value of a bit as an integer for array indexing etc.
+    function bit_to_integer( s : std_logic ) return natural;    
+
+    ------------------------------------------------------------ 
+    -- Records
+    ------------------------------------------------------------ 
+
+    ------------------------------------------------------------ 
+    -- Components
+    ------------------------------------------------------------
+
+end sfd700_pkg;
+
+------------------------------------------------------------ 
+-- Function definitions.
+------------------------------------------------------------ 
+package body sfd700_pkg is
+    
+    -- Find the maximum of two integers.
+    function IntMax(a : in integer; b : in integer) return integer is
+    begin
+        if a > b then
+            return a;
+        else
+            return b;
+        end if;
+        return a;
+    end function IntMax;
+
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural is
+        variable tmp : positive     := 1;
+        variable log : natural      := 0;
+    begin
+        if arg = 1 then
+            return 0;
+        end if;
+
+        while arg > tmp loop
+            tmp := tmp * 2;
+            log := log + 1;
+        end loop;
+        return log;
+    end function;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer is
+        variable ticks         : real;
+        variable fracTicks     : real;
+    begin
+        ticks         := (Real(period) * Real(clock)) / 1000000000.0;
+        fracTicks     := ticks - CEIL(ticks);
+        if fracTicks > 0.0001 then
+            return Integer(CEIL(ticks + 1.0));
+        else
+            return Integer(CEIL(ticks));
+        end if;
+    end function;
+
+    function reverse_vector(slv:std_logic_vector) return std_logic_vector is 
+       variable target : std_logic_vector(slv'high downto slv'low); 
+    begin 
+      for idx in slv'high downto slv'low loop 
+        target(idx) := slv(slv'low + (slv'high-idx)); 
+      end loop; 
+      return target; 
+    end reverse_vector;
+
+    function to_std_logic(i : in integer) return std_logic is
+    begin
+      if i = 0 then
+        return '0';
+      end if;
+      return '1';
+    end function;
+
+    -- Function to return the value of a bit as an integer for array indexing etc.
+    function bit_to_integer( s : std_logic ) return natural is
+    begin
+        if s = '1' then
+            return 1;
+        else
+            return 0;
+        end if;
+    end function;
+end package body;

CUPL/SFD700.PLD

@@ -1,67 +0,0 @@
-Name     SFD700 ;
-PartNo   GAL26CV12 ;
-Date     24/04/2023 ;
-Revision 01 ;
-Designer Philip Smart ;
-Company  engineers@work ;
-Assembly SFD700 ;
-Location  ;
-Device   g26cv12 ;
-
-/* *************** CONSTANTS ********************** */
-$DEFINE ON  'b'1
-$DEFINE OFF 'b'0
-
-/* *************** INPUT PINS ********************* */
-PIN  1       = A0                                    ; /* Address bus A0                                                  */ 
-PIN  2       = A1                                    ; /*             A1                                                  */ 
-PIN  3       = A2                                    ; /*             A2                                                  */ 
-PIN  4       = A3                                    ; /*             A3                                                  */ 
-PIN  5       = A4                                    ; /*             A4                                                  */ 
-PIN  6       = A5                                    ; /*             A5                                                  */ 
-PIN  8       = A6                                    ; /*             A6                                                  */ 
-PIN  9       = A7                                    ; /*             A7                                                  */ 
-PIN 10       = A12                                   ; /*             A12                                                 */ 
-PIN 11       = A13                                   ; /*             A13                                                 */ 
-PIN 12       = A14                                   ; /*             A14                                                 */ 
-PIN 13       = A15                                   ; /*             A15                                                 */ 
-PIN 14       = !MREQn                                ; /* Z80 MREQ active low                                             */ 
-PIN 15       = !IORQn                                ; /* Z80 IORQ active low                                             */ 
-PIN 16       = !WRn                                  ; /* Z80 WR active low                                               */ 
-PIN 17       = !RDn                                  ; /* Z80 RD active low                                               */ 
-PIN 28       = RESET                                 ; /* System Reset active high                                        */ 
-
-/* *************** OUTPUT PINS ******************** */
-PIN 22       = !BUSENn                               ; /* BUS direction, low = read into Z80, high = write to card.       */ 
-PIN 20       = !IOBUSDIRn                            ; /* I/O BUS direction, low = read into Z80, high = write to FD IC's */ 
-PIN 27       = !FDCn                                 ; /* WD1773 Chip Select active low I/O - Address 0xD8 .. 0xDB        */ 
-PIN 26       = !DRIVEn                               ; /* Disk Drive Select active low - Address 0xDC                     */ 
-PIN 25       = !DDENn                                ; /* Drive Density select active low - Address 0xDE                  */ 
-PIN 24       = !FDCRESETn                            ; /* Peripheral Reset active low                                     */ 
-PIN 23       = !SIDEn                                ; /* Disk Head Select active low - Address 0xDD                      */ 
-PIN 19       = !INTEN                                ; /* Interrupt enable.                                               */
-PIN 18       = !ROMn                                 ; /* ROM Select.                                                     */
-
-/* Decoder equations. */
-FIELD IOADDR = [A7..0]                               ; /* Address lines considered for I/O devices.                       */
-FIELD HIADDR = [A15..12]                             ; /* Address lines considered for ROM device.                        */
-WD1773SELR   = IORQn & RDn & IOADDR:[D8..DB]         ; /* FDC select.                                                     */
-WD1773SELW   = IORQn & WRn & IOADDR:[D8..DB]         ; /* FDC select.                                                     */
-SIDESEL      = IORQn & WRn & IOADDR:[DD..DD]         ; /* Drive side select.                                              */
-DRIVESEL     = IORQn & WRn & IOADDR:[DC..DC]         ; /* Drive number select.                                            */
-DDENSEL      = IORQn & WRn & IOADDR:[DE..DE]         ; /* Drive Double Density select.                                    */
-ROMSEL       = MREQn & RDn & HIADDR:[F000..F7FF]     ; /* Rom Select.                                                     */
-DRAMENSEL    = IORQn & WRn & IOADDR:[E1];
-
-/* Assign output pins based on equations. */
-IOBUSDIRn    = WD1773SELR                            ;
-BUSENn       = ROMSEL # WD1773SELR # WD1773SELW #
-               SIDESEL # DRIVESEL # DDENSEL          ;
-FDCRESETn    = RESET                                 ;
-FDCn         = WD1773SELR # WD1773SELW               ;
-SIDEn        = SIDESEL                               ;
-DRIVEn       = DRIVESEL                              ;
-DDENn        = DDENSEL                               ;
-ROMn         = ROMSEL                                ;
-INTEN.sp     = DRAMENSEL                             ;
-INTEN.ar     = RESET ;

CUPL/SFD700_2.PLD.MZ700

@@ -0,0 +1,48 @@
+Name         SFD700_GAL2 ;
+PartNo       GAL16V8 ;
+Date         22/05/2023 ;
+Revision     01 ;
+Designer     Philip Smart ;
+Company      engineers@work ;
+Assembly     SFD700 ;
+Location      ;
+Device       g16v8 ;
+
+/* *************** CONSTANTS ********************** */
+$DEFINE ON  'b'1
+$DEFINE OFF 'b'0
+
+/* *************** INPUT PINS ********************* */
+PIN  1       = CLK                                   ; /* Registered clock input                                          */ 
+PIN  2       = A10                                   ; /* Address bus A10                                                 */ 
+PIN  3       = A11                                   ; /*             A11                                                 */ 
+PIN  4       = A12                                   ; /*             A12                                                 */ 
+PIN  5       = A13                                   ; /*             A13                                                 */ 
+PIN  6       = A14                                   ; /*             A14                                                 */ 
+PIN  7       = A15                                   ; /*             A15                                                 */ 
+PIN  8       = !MREQn                                ; /* Z80 MREQ active low                                             */ 
+PIN  9       = !RDn                                  ; /* Z80 RD active low                                               */ 
+PIN 12       = MODESEL0                              ; /* Mode selection bit 0                                            */ 
+PIN 13       = MODESEL1                              ; /* Mode selection bit 1                                            */ 
+PIN 14       = ROMINH                                ; /* Rom select inhibit                                              */ 
+PIN 15       = ROMDIS                                ; /* Rom select disable                                              */ 
+PIN 16       = DRQ                                   ; /* FDC Data Request                                                */ 
+
+/* *************** OUTPUT PINS ******************** */
+PIN 17       = ROMA15                                ; /* ROM A15                                                         */ 
+PIN 18       = ROMA10                                ; /* ROM A10                                                         */ 
+PIN 19       = !ROMCSn                               ; /* ROM Chip Select                                                 */ 
+
+/* Decoder equations. */
+FIELD HIADDR = [A15..A12]                            ; /* Address lines considered for ROM device.                        */
+ROMOUTSEL    = MREQn & RDn & HIADDR:[F000..FFFF] & !ROMDIS & !ROMINH ; /* Rom Select.                                     */
+
+/* Assign output pins based on equations. */
+ROMCSn.D       = ROMOUTSEL                             ;
+ROMA15.D       = MODESEL1;
+ROMA10.D       = (MODESEL1 & ROMOUTSEL & !A10) # (!MODESEL1 & ROMOUTSEL & DRQ);
+MODESEL0.OE = OFF;
+MODESEL1.OE = OFF;
+ROMINH.OE   = OFF;
+ROMEN.OE    = OFF;
+DRQ.OE      = OFF;

CUPL/SFD700_2.PLD.MZ80A

@@ -0,0 +1,46 @@
+Name         SFD700_GAL2 ;
+PartNo       GAL16V8 ;
+Date         22/05/2023 ;
+Revision     01 ;
+Designer     Philip Smart ;
+Company      engineers@work ;
+Assembly     SFD700 ;
+Location      ;
+Device       g16v8 ;
+
+/* *************** CONSTANTS ********************** */
+$DEFINE ON  'b'1
+$DEFINE OFF 'b'0
+
+/* *************** INPUT PINS ********************* */
+PIN  1       = CLK                                   ; /* Registered clock input                                          */ 
+PIN  2       = A10                                   ; /* Address bus A10                                                 */ 
+PIN  3       = A11                                   ; /*             A11                                                 */ 
+PIN  4       = A12                                   ; /*             A12                                                 */ 
+PIN  5       = A13                                   ; /*             A13                                                 */ 
+PIN  6       = A14                                   ; /*             A14                                                 */ 
+PIN  7       = A15                                   ; /*             A15                                                 */ 
+PIN  8       = !MREQn                                ; /* Z80 MREQ active low                                             */ 
+PIN  9       = !RDn                                  ; /* Z80 RD active low                                               */ 
+PIN 12       = MODESEL0                              ; /* Mode selection bit 0                                            */ 
+PIN 13       = MODESEL1                              ; /* Mode selection bit 1                                            */ 
+PIN 14       = ROMINH                                ; /* Rom select inhibit                                              */ 
+PIN 15       = ROMDIS                                ; /* Rom select disable                                              */ 
+PIN 16       = DRQ                                   ; /* FDC Data Request                                                */ 
+
+/* *************** OUTPUT PINS ******************** */
+PIN 17       = ROMA15                                ; /* ROM A15                                                         */ 
+PIN 18       = ROMA10                                ; /* ROM A10                                                         */ 
+PIN 19       = !ROMCSn                               ; /* ROM Chip Select                                                 */ 
+
+/* Decoder equations. */
+FIELD HIADDR = [A15..A12]                            ; /* Address lines considered for ROM device.                        */
+ROMOUTSEL    = MREQn & RDn & HIADDR:[F000..FFFF]     ; /* Rom Select.                                     */
+
+/* Assign output pins based on equations. */
+ROMCSn.D     = ROMOUTSEL;
+ROMA15.D     = MODESEL1;
+ROMA10.D     = !DRQ;
+/*DRQ.OE      = OFF; */
+/* ROMA10.OE      = ON; */
+/* ROMA15.OE      = ON; */

EX.BAT

@@ -0,0 +1 @@
+cupl -j -f -a g16v8 count10

kicad/Output/v1.1/SFD700-B_Mask.gbr

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+G04 #@! TF.CreationDate,2023-05-08T12:54:49+01:00*
+G04 #@! TF.ProjectId,SFD700,53464437-3030-42e6-9b69-6361645f7063,rev?*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Soldermask,Bot*
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kicad/Output/v1.1/SFD700-B_Paste.gbr

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kicad/Output/v1.1/SFD700-B_Silkscreen.gbr

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kicad/Output/v1.1/SFD700-Edge_Cuts.gbr

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kicad/Output/v1.1/SFD700-F_Mask.gbr

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kicad/Output/v1.2/SFD700-Edge_Cuts.gbr

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kicad/Output/v1.2/SFD700-F_Paste.gbr

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kicad/Output/v1.2/SFD700-NPTH.drl

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kicad/Output/v1.2/SFD700-PTH.drl

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kicad/v1.0/Custom.kicad_sym

@@ -0,0 +1,256 @@
+(kicad_symbol_lib (version 20220914) (generator kicad_symbol_editor)
+  (symbol "27C32" (in_bom yes) (on_board yes)
+    (property "Reference" "U" (at -7.62 24.13 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "27C32" (at -1.27 -6.35 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "Package_DIP:DIP-24_W15.24mm" (at -1.27 -22.86 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_keywords" "OTP EPROM 64KiBit" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "OTP EPROM 64 KiBit, [Obsolete 2004-01]" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_fp_filters" "DIP*W15.24mm*" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "27C32_1_1"
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+        (stroke (width 0.254) (type default))
+        (fill (type background))
+      )
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+        (number "11" (effects (font (size 1.27 1.27))))
+      )
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+      )
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+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+        (number "24" (effects (font (size 1.27 1.27))))
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+        (stroke (width 0.254) (type default))
+        (fill (type background))
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+      (pin input line (at -12.7 12.7 0) (length 3.81)
+        (name "I1/CLK" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
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+        (number "20" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 7.62 180) (length 3.81)
+        (name "I03" (effects (font (size 1.27 1.27))))
+        (number "21" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 10.16 180) (length 3.81)
+        (name "IO2" (effects (font (size 1.27 1.27))))
+        (number "22" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 12.7 180) (length 3.81)
+        (name "IO1" (effects (font (size 1.27 1.27))))
+        (number "23" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 7.62 0) (length 3.81)
+        (name "I3" (effects (font (size 1.27 1.27))))
+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 5.08 0) (length 3.81)
+        (name "I4" (effects (font (size 1.27 1.27))))
+        (number "4" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 2.54 0) (length 3.81)
+        (name "I5" (effects (font (size 1.27 1.27))))
+        (number "5" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 0 0) (length 3.81)
+        (name "I6" (effects (font (size 1.27 1.27))))
+        (number "6" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 -2.54 0) (length 3.81)
+        (name "I7" (effects (font (size 1.27 1.27))))
+        (number "7" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 -5.08 0) (length 3.81)
+        (name "I8" (effects (font (size 1.27 1.27))))
+        (number "8" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 -7.62 0) (length 3.81)
+        (name "I9" (effects (font (size 1.27 1.27))))
+        (number "9" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+)

kicad/v1.0/Graphic.pretty/Argo.kicad_mod

@@ -0,0 +1,38 @@
+(module LOGO (layer F.Cu)
+  (at 0 0)
+ (fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
+  )
+  (fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
+  )
+  (fp_poly (pts (xy -0.196711 -1.697674) (xy -0.119057 -1.509220) (xy -0.123862 -1.374646) (xy -0.129716 -1.236468) (xy -0.097802 -1.005898) (xy -0.040397 -0.733497) (xy 0.030224 -0.469826) (xy 0.101784 -0.265448)
+     (xy 0.162008 -0.170922) (xy 0.168777 -0.169333) (xy 0.297274 -0.239711) (xy 0.418671 -0.402675) (xy 0.473805 -0.550333) (xy 0.846667 -0.550333) (xy 0.889000 -0.508000) (xy 0.931334 -0.550333)
+     (xy 0.889000 -0.592666) (xy 0.846667 -0.550333) (xy 0.473805 -0.550333) (xy 0.487114 -0.585975) (xy 0.485719 -0.668727) (xy 0.495617 -0.762000) (xy 0.677334 -0.762000) (xy 0.706220 -0.679534)
+     (xy 0.714670 -0.677333) (xy 0.786956 -0.736662) (xy 0.804334 -0.762000) (xy 0.799138 -0.822397) (xy 1.029648 -0.822397) (xy 1.050249 -0.775082) (xy 1.135499 -0.684188) (xy 1.184509 -0.702834)
+     (xy 1.185334 -0.714670) (xy 1.125197 -0.786282) (xy 1.087585 -0.812418) (xy 1.029648 -0.822397) (xy 0.799138 -0.822397) (xy 0.797621 -0.840019) (xy 0.766997 -0.846666) (xy 0.680779 -0.785206)
+     (xy 0.677334 -0.762000) (xy 0.495617 -0.762000) (xy 0.505644 -0.856480) (xy 0.624365 -1.028153) (xy 0.791038 -1.128901) (xy 0.910773 -1.127241) (xy 1.170170 -0.981838) (xy 1.285822 -0.795551)
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+     (xy 0.586867 0.846667) (xy 0.575880 0.909525) (xy 0.641139 1.063944) (xy 0.658515 1.095201) (xy 0.726206 1.266176) (xy 0.733212 1.398144) (xy 0.690360 1.450964) (xy 0.608475 1.384498)
+     (xy 0.588729 1.353962) (xy 0.450158 1.132796) (xy 0.363474 1.033710) (xy 0.297936 1.030982) (xy 0.250149 1.070652) (xy 0.200922 1.175320) (xy 0.246623 1.223107) (xy 0.317233 1.330489)
+     (xy 0.336440 1.480789) (xy 0.300627 1.592584) (xy 0.263738 1.608667) (xy 0.168533 1.544953) (xy 0.050119 1.397000) (xy -0.082394 1.252472) (xy -0.214153 1.185741) (xy -0.301843 1.204755)
+     (xy -0.302145 1.317462) (xy -0.295986 1.333500) (xy -0.227278 1.587595) (xy -0.271288 1.731367) (xy -0.305906 1.750912) (xy -0.399063 1.705438) (xy -0.497227 1.549604) (xy -0.503121 1.535778)
+     (xy -0.611474 1.370919) (xy -0.752758 1.261874) (xy -0.885274 1.222116) (xy -0.967321 1.265117) (xy -0.963085 1.387172) (xy -0.903244 1.650363) (xy -0.936925 1.795537) (xy -1.025706 1.842257)
+     (xy -1.126508 1.813155) (xy -1.192810 1.655719) (xy -1.216266 1.533882) (xy -1.275255 1.302339) (xy -1.374047 1.194145) (xy -1.460560 1.170048) (xy -1.583689 1.124967) (xy -1.647763 1.003995)
+     (xy -1.677737 0.768791) (xy -1.683021 0.485785) (xy -1.663297 0.241036) (xy -1.653231 0.190414) (xy -1.622443 0.112889) (xy -0.310444 0.112889) (xy -0.298822 0.163223) (xy -0.254000 0.169334)
+     (xy -0.184310 0.138355) (xy -0.197555 0.112889) (xy -0.298035 0.102756) (xy -0.310444 0.112889) (xy -1.622443 0.112889) (xy -1.601404 0.059914) (xy -1.499755 0.016846) (xy -1.292184 0.038596)
+     (xy -1.281169 0.040446) (xy -1.009246 0.053143) (xy -0.960053 0.028222) (xy -0.056444 0.028222) (xy -0.044822 0.078557) (xy 0.000000 0.084667) (xy 0.069690 0.053689) (xy 0.056445 0.028222)
+     (xy -0.044035 0.018089) (xy -0.056444 0.028222) (xy -0.960053 0.028222) (xy -0.894251 -0.005113) (xy 0.315397 -0.005113) (xy 0.423832 -0.037049) (xy 0.604454 -0.162045) (xy 0.724868 -0.293695)
+     (xy 0.740159 -0.388329) (xy 0.738268 -0.390389) (xy 0.643174 -0.379791) (xy 0.489029 -0.271038) (xy 0.443859 -0.228343) (xy 0.315472 -0.071602) (xy 0.315397 -0.005113) (xy -0.894251 -0.005113)
+     (xy -0.872412 -0.016176) (xy -0.787661 -0.169333) (xy -0.423333 -0.169333) (xy -0.358904 -0.087127) (xy -0.338666 -0.084666) (xy -0.256460 -0.149096) (xy -0.254000 -0.169333) (xy -0.318429 -0.251540)
+     (xy -0.338666 -0.254000) (xy -0.420873 -0.189571) (xy -0.423333 -0.169333) (xy -0.787661 -0.169333) (xy -0.776919 -0.188745) (xy -0.751219 -0.254000) (xy -0.592666 -0.254000) (xy -0.561688 -0.184310)
+     (xy -0.536222 -0.197555) (xy -0.526089 -0.298035) (xy -0.536222 -0.310444) (xy -0.586556 -0.298822) (xy -0.592666 -0.254000) (xy -0.751219 -0.254000) (xy -0.701200 -0.381000) (xy -0.338666 -0.381000)
+     (xy -0.296333 -0.338666) (xy -0.254000 -0.381000) (xy -0.296333 -0.423333) (xy -0.338666 -0.381000) (xy -0.701200 -0.381000) (xy -0.671894 -0.455408) (xy -0.668608 -0.465666) (xy -0.169333 -0.465666)
+     (xy -0.127000 -0.423333) (xy -0.084666 -0.465666) (xy -0.127000 -0.508000) (xy -0.169333 -0.465666) (xy -0.668608 -0.465666) (xy -0.627916 -0.592666) (xy -0.338666 -0.592666) (xy -0.307688 -0.522976)
+     (xy -0.282222 -0.536222) (xy -0.272089 -0.636702) (xy -0.282222 -0.649111) (xy -0.332556 -0.637489) (xy -0.338666 -0.592666) (xy -0.627916 -0.592666) (xy -0.573639 -0.762062) (xy -0.498454 -1.054600)
+     (xy -0.462643 -1.278920) (xy -0.467437 -1.360244) (xy -0.468878 -1.556926) (xy -0.420620 -1.698403) (xy -0.323859 -1.879202) (xy -0.196711 -1.697674) )(layer F.SilkS) (width  0.010000)
+  )
+  (fp_poly (pts (xy 1.664232 -1.400084) (xy 1.647878 -1.266812) (xy 1.641503 -1.256210) (xy 1.591774 -1.076543) (xy 1.594935 -0.994833) (xy 1.571229 -0.873555) (xy 1.460270 -0.869531) (xy 1.291925 -0.977713)
+     (xy 1.206500 -1.060486) (xy 1.053024 -1.253391) (xy 1.042188 -1.372092) (xy 1.179190 -1.441292) (xy 1.291167 -1.462976) (xy 1.539212 -1.469081) (xy 1.664232 -1.400084) )(layer F.SilkS) (width  0.010000)
+  )
+)

kicad/v1.0/Graphic.pretty/CycloneInside.kicad_mod

@@ -0,0 +1,144 @@
+(module LOGO (layer F.Cu)
+  (at 0 0)
+ (fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
+  )
+  (fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
+  )
+  (fp_poly (pts (xy 20.320000 11.430000) (xy -20.320000 11.430000) (xy -20.320000 2.328333) (xy -7.664854 2.328333) (xy -7.664517 3.169628) (xy -7.663551 3.894108) (xy -7.662009 4.495699) (xy -7.659949 4.968330)
+     (xy -7.657424 5.305929) (xy -7.654491 5.502422) (xy -7.651204 5.551739) (xy -7.647618 5.447805) (xy -7.643790 5.184550) (xy -7.641203 4.925728) (xy -7.635603 4.092708) (xy -7.632362 3.153739)
+     (xy -7.631479 2.166748) (xy -7.632954 1.189663) (xy -7.636787 0.280410) (xy -7.641222 -0.323606) (xy -7.642993 -0.484984) (xy -6.771487 -0.484984) (xy -6.771474 0.052156) (xy -6.770845 1.138488)
+     (xy -6.769531 2.068586) (xy -6.767174 2.855548) (xy -6.763411 3.512474) (xy -6.757881 4.052461) (xy -6.750225 4.488610) (xy -6.740080 4.834018) (xy -6.727087 5.101784) (xy -6.710883 5.305007)
+     (xy -6.691109 5.456786) (xy -6.667403 5.570219) (xy -6.639405 5.658406) (xy -6.615432 5.715726) (xy -6.421061 6.028752) (xy -6.151020 6.320817) (xy -5.855005 6.545727) (xy -5.607614 6.652515)
+     (xy -5.406707 6.700003) (xy -5.291667 6.731721) (xy -5.161919 6.745496) (xy -4.880348 6.754902) (xy -4.464402 6.760113) (xy -3.931530 6.761305) (xy -3.299180 6.758653) (xy -2.584802 6.752332)
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+     (xy -4.773705 -6.698291) (xy -5.197980 -6.686747) (xy -5.489291 -6.673144) (xy -5.628302 -6.657739) (xy -5.990847 -6.483959) (xy -6.324626 -6.193369) (xy -6.578501 -5.837008) (xy -6.669533 -5.618479)
+     (xy -6.692396 -5.494824) (xy -6.711979 -5.281513) (xy -6.728453 -4.969105) (xy -6.741986 -4.548160) (xy -6.752748 -4.009239) (xy -6.760910 -3.342900) (xy -6.766641 -2.539705) (xy -6.770110 -1.590213)
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+     (xy -7.662639 0.357065) (xy -7.663977 1.007253) (xy -7.664718 1.777020) (xy -7.664854 2.328333) (xy -20.320000 2.328333) (xy -20.320000 -7.672903) (xy -6.478304 -7.672903) (xy -6.424897 -7.668404)
+     (xy -6.226186 -7.664571) (xy -5.890181 -7.661533) (xy -5.424891 -7.659422) (xy -4.838327 -7.658366) (xy -4.572000 -7.658269) (xy -3.939245 -7.658866) (xy -3.424567 -7.660572) (xy -3.035974 -7.663255)
+     (xy -2.781477 -7.666786) (xy -2.669085 -7.671035) (xy -2.706808 -7.675872) (xy -2.902657 -7.681165) (xy -3.026834 -7.683378) (xy -3.680906 -7.690679) (xy -4.426929 -7.693658) (xy -5.187575 -7.692314)
+     (xy -5.885516 -7.686648) (xy -6.117167 -7.683378) (xy -6.378397 -7.677938) (xy -6.478304 -7.672903) (xy -20.320000 -7.672903) (xy -20.320000 -11.430000) (xy 20.320000 -11.430000) (xy 20.320000 11.430000) )(layer F.SilkS) (width  0.010000)
+  )
+  (fp_poly (pts (xy 5.372712 -5.975089) (xy 5.593398 -5.843407) (xy 5.723466 -5.723467) (xy 6.011333 -5.435601) (xy 6.011333 -0.507409) (xy 6.010943 0.538103) (xy 6.009560 1.426526) (xy 6.006865 2.170104)
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kicad/v1.0/Graphic.pretty/IntelInside.kicad_mod

@@ -0,0 +1,291 @@
+(module LOGO (layer F.Cu)
+  (at 0 0)
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+  (effects (font (thickness 0.3)))
+  )
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+     (xy -0.073274 -2.935111) (xy -0.045813 -2.921426) )(layer F.SilkS) (width  0.010000)
+  )
+  (fp_poly (pts (xy 3.756222 -4.902438) (xy 3.805510 -4.878984) (xy 3.833175 -4.842154) (xy 3.838222 -4.813052) (xy 3.827101 -4.768900) (xy 3.793000 -4.738217) (xy 3.734814 -4.720245) (xy 3.696582 -4.715805)
+     (xy 3.612445 -4.709719) (xy 3.612445 -4.910667) (xy 3.688153 -4.910667) (xy 3.756222 -4.902438) )(layer F.SilkS) (width  0.010000)
+  )
+)

kicad/v1.0/SFD700.kicad_prl

@@ -0,0 +1,78 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "All Layers",
+    "auto_track_width": true,
+    "hidden_netclasses": [],
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "images": 0.6,
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      8,
+      9,
+      10,
+      11,
+      12,
+      13,
+      15,
+      16,
+      17,
+      18,
+      19,
+      20,
+      21,
+      22,
+      23,
+      24,
+      25,
+      26,
+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36,
+      39,
+      40
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "SFD700.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

kicad/v1.0/SFD700.kicad_pro

@@ -0,0 +1,553 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.049999999999999996,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
+        "silk_line_width": 0.12,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.0
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.024999999999999998,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
+        "min_text_height": 0.7999999999999999,
+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.25,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.5,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 5,
+          "td_on_pad_in_zone": false,
+          "td_onpadsmd": true,
+          "td_onroundshapesonly": false,
+          "td_ontrackend": false,
+          "td_onviapad": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [
+        0.0,
+        0.1524,
+        0.2,
+        0.254,
+        0.381,
+        0.508,
+        0.8128
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        },
+        {
+          "diameter": 0.5,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.5,
+          "drill": 0.35
+        },
+        {
+          "diameter": 0.5,
+          "drill": 0.4
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.5
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
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+        2
+      ],
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+      ],
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+      ],
+      [
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+        0,
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+      ],
+      [
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+      ],
+      [
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+      ],
+      [
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+        1,
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+        1,
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+      ],
+      [
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+        0,
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+      ],
+      [
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+        2,
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+      ],
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+        1,
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+        0,
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+      ],
+      [
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+        1,
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+      ],
+      [
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+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "error",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "simulation_model_issue": "error",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "SFD700.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Power",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.5,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 3
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": [
+      {
+        "netclass": "Power",
+        "pattern": "+5V"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "GNDPWR"
+      }
+    ]
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "SFD700.dsn",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_voltages": false,
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "418bd263-f0a9-42da-88ea-160d6eff482c",
+      ""
+    ]
+  ],
+  "text_variables": {}
+}

kicad/v1.0/SFD700.lib

@@ -0,0 +1,253 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Ext_Bus_MZ800
+#
+DEF Ext_Bus_MZ800 J 0 20 Y Y 1 F N
+F0 "J" 0 1225 50 H V C CNN
+F1 "Ext_Bus_MZ800" 0 -1225 50 H V C CNN
+F2 "" 0 -450 50 H I C CNN
+F3 "" 0 -450 50 H I C CNN
+DRAW
+T 0 -200 1150 31 0 0 0 " Top Side" Normal 0 C C
+T 0 150 1150 31 0 0 0 "Bottom Side" Normal 0 C C
+S -300 -1150 300 1200 0 1 10 f
+X VCC 1 -400 1050 100 R 50 50 1 1 w
+X D6 10 400 650 100 L 50 50 1 1 T
+X AD15 11 -400 550 100 R 50 50 1 1 O
+X D7 12 400 550 100 L 50 50 1 1 T
+X AD14 13 -400 450 100 R 50 50 1 1 O
+X BUS0 14 400 450 100 L 50 50 1 1 O
+X AD13 15 -400 350 100 R 50 50 1 1 O
+X ~M1 16 400 350 100 L 50 50 1 1 O
+X AD12 17 -400 250 100 R 50 50 1 1 O
+X ~WR 18 400 250 100 L 50 50 1 1 O
+X AD11 19 -400 150 100 R 50 50 1 1 O
+X VCC 2 400 1050 100 L 50 50 1 1 W
+X ~RD 20 400 150 100 L 50 50 1 1 O
+X AD10 21 -400 50 100 R 50 50 1 1 O
+X ~IORQ 22 400 50 100 L 50 50 1 1 O
+X AD9 23 -400 -50 100 R 50 50 1 1 O
+X ~MREQ 24 400 -50 100 L 50 50 1 1 O
+X AD8 25 -400 -150 100 R 50 50 1 1 O
+X GND 26 400 -150 100 L 50 50 1 1 w
+X AD7 27 -400 -250 100 R 50 50 1 1 O
+X ~HALT 28 400 -250 100 L 50 50 1 1 I
+X AD6 29 -400 -350 100 R 50 50 1 1 O
+X D2 3 -400 950 100 R 50 50 1 1 T
+X IE1 30 400 -350 100 L 50 50 1 1 I
+X AD5 31 -400 -450 100 R 50 50 1 1 O
+X NC 32 400 -450 100 L 50 50 1 1 P
+X AD4 33 -400 -550 100 R 50 50 1 1 O
+X RESET 34 400 -550 100 L 50 50 1 1 O
+X AD3 35 -400 -650 100 R 50 50 1 1 O
+X ~EXRESET 36 400 -650 100 L 50 50 1 1 I
+X AD2 37 -400 -750 100 R 50 50 1 1 O
+X ~INT 38 400 -750 100 L 50 50 1 1 I
+X AD1 39 -400 -850 100 R 50 50 1 1 O
+X D3 4 400 950 100 L 50 50 1 1 T
+X ~EXWAIT 40 400 -850 100 L 50 50 1 1 I
+X AD0 41 -400 -950 100 R 50 50 1 1 O
+X NC 42 400 -950 100 L 50 50 1 1 P
+X GND 43 -400 -1050 100 R 50 50 1 1 W
+X GND 44 400 -1050 100 L 50 50 1 1 W
+X D1 5 -400 850 100 R 50 50 1 1 T
+X D4 6 400 850 100 L 50 50 1 1 T
+X D0 7 -400 750 100 R 50 50 1 1 T
+X D5 8 400 750 100 L 50 50 1 1 T
+X GND 9 -400 650 100 R 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# PAL12L6
+#
+DEF PAL12L6 U 0 40 Y Y 1 F N
+F0 "U" -350 650 50 H V L CNN
+F1 "PAL12L6" 50 700 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ PDIP*
+$ENDFPLIST
+DRAW
+S -350 600 300 -850 0 1 10 f
+X GND 10 0 -1000 150 U 50 50 0 0 W
+X VCC 20 0 750 150 D 50 50 0 0 W
+X A0 1 -500 500 150 R 50 50 1 1 I
+X ~WR 11 -500 -500 150 R 50 50 1 1 I
+X ~RD 12 -500 -600 150 R 50 50 1 1 I
+X ~BUS 13 450 400 150 L 50 50 1 1 O
+X ~DRIVE 14 450 50 150 L 50 50 1 1 O
+X ~RES 15 450 -350 150 L 50 50 1 1 O
+X ~SIDE 16 450 -600 150 L 50 50 1 1 O
+X ~DDEN 17 450 -150 150 L 50 50 1 1 O
+X ~FDC 18 450 250 150 L 50 50 1 1 O
+X ~IORQ 19 -500 -400 150 R 50 50 1 1 I
+X A1 2 -500 400 150 R 50 50 1 1 I
+X A2 3 -500 300 150 R 50 50 1 1 I
+X A3 4 -500 200 150 R 50 50 1 1 I
+X RESET 5 -500 -750 150 R 50 50 1 1 I
+X A4 6 -500 100 150 R 50 50 1 1 I
+X A5 7 -500 0 150 R 50 50 1 1 I
+X A6 8 -500 -100 150 R 50 50 1 1 I
+X A7 9 -500 -200 150 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Connector_Generic_Conn_02x17_Odd_Even
+#
+DEF Connector_Generic_Conn_02x17_Odd_Even J 0 40 Y N 1 F N
+F0 "J" 50 900 50 H V C CNN
+F1 "Connector_Generic_Conn_02x17_Odd_Even" 50 -900 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_2x??_*
+$ENDFPLIST
+DRAW
+S -50 -795 0 -805 1 1 6 N
+S -50 -695 0 -705 1 1 6 N
+S -50 -595 0 -605 1 1 6 N
+S -50 -495 0 -505 1 1 6 N
+S -50 -395 0 -405 1 1 6 N
+S -50 -295 0 -305 1 1 6 N
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 305 0 295 1 1 6 N
+S -50 405 0 395 1 1 6 N
+S -50 505 0 495 1 1 6 N
+S -50 605 0 595 1 1 6 N
+S -50 705 0 695 1 1 6 N
+S -50 805 0 795 1 1 6 N
+S -50 850 150 -850 1 1 10 f
+S 150 -795 100 -805 1 1 6 N
+S 150 -695 100 -705 1 1 6 N
+S 150 -595 100 -605 1 1 6 N
+S 150 -495 100 -505 1 1 6 N
+S 150 -395 100 -405 1 1 6 N
+S 150 -295 100 -305 1 1 6 N
+S 150 -195 100 -205 1 1 6 N
+S 150 -95 100 -105 1 1 6 N
+S 150 5 100 -5 1 1 6 N
+S 150 105 100 95 1 1 6 N
+S 150 205 100 195 1 1 6 N
+S 150 305 100 295 1 1 6 N
+S 150 405 100 395 1 1 6 N
+S 150 505 100 495 1 1 6 N
+S 150 605 100 595 1 1 6 N
+S 150 705 100 695 1 1 6 N
+S 150 805 100 795 1 1 6 N
+X Pin_1 1 -200 800 150 R 50 50 1 1 P
+X Pin_10 10 300 400 150 L 50 50 1 1 P
+X Pin_11 11 -200 300 150 R 50 50 1 1 P
+X Pin_12 12 300 300 150 L 50 50 1 1 P
+X Pin_13 13 -200 200 150 R 50 50 1 1 P
+X Pin_14 14 300 200 150 L 50 50 1 1 P
+X Pin_15 15 -200 100 150 R 50 50 1 1 P
+X Pin_16 16 300 100 150 L 50 50 1 1 P
+X Pin_17 17 -200 0 150 R 50 50 1 1 P
+X Pin_18 18 300 0 150 L 50 50 1 1 P
+X Pin_19 19 -200 -100 150 R 50 50 1 1 P
+X Pin_2 2 300 800 150 L 50 50 1 1 P
+X Pin_20 20 300 -100 150 L 50 50 1 1 P
+X Pin_21 21 -200 -200 150 R 50 50 1 1 P
+X Pin_22 22 300 -200 150 L 50 50 1 1 P
+X Pin_23 23 -200 -300 150 R 50 50 1 1 P
+X Pin_24 24 300 -300 150 L 50 50 1 1 P
+X Pin_25 25 -200 -400 150 R 50 50 1 1 P
+X Pin_26 26 300 -400 150 L 50 50 1 1 P
+X Pin_27 27 -200 -500 150 R 50 50 1 1 P
+X Pin_28 28 300 -500 150 L 50 50 1 1 P
+X Pin_29 29 -200 -600 150 R 50 50 1 1 P
+X Pin_3 3 -200 700 150 R 50 50 1 1 P
+X Pin_30 30 300 -600 150 L 50 50 1 1 P
+X Pin_31 31 -200 -700 150 R 50 50 1 1 P
+X Pin_32 32 300 -700 150 L 50 50 1 1 P
+X Pin_33 33 -200 -800 150 R 50 50 1 1 P
+X Pin_34 34 300 -800 150 L 50 50 1 1 P
+X Pin_4 4 300 700 150 L 50 50 1 1 P
+X Pin_5 5 -200 600 150 R 50 50 1 1 P
+X Pin_6 6 300 600 150 L 50 50 1 1 P
+X Pin_7 7 -200 500 150 R 50 50 1 1 P
+X Pin_8 8 300 500 150 L 50 50 1 1 P
+X Pin_9 9 -200 400 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# SFD700_PAL12L6
+#
+DEF SFD700_PAL12L6 U 0 40 Y Y 1 F N
+F0 "U" -350 650 50 H V L CNN
+F1 "SFD700_PAL12L6" 50 700 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ PDIP*
+$ENDFPLIST
+DRAW
+S -350 600 300 -850 0 1 10 f
+X GND 10 0 -1000 150 U 50 50 0 0 W
+X VCC 20 0 750 150 D 50 50 0 0 W
+X A0 1 -500 500 150 R 50 50 1 1 I
+X ~WR 11 -500 -500 150 R 50 50 1 1 I
+X ~RD 12 -500 -600 150 R 50 50 1 1 I
+X ~BUS 13 450 400 150 L 50 50 1 1 O
+X ~DRIVE 14 450 50 150 L 50 50 1 1 O
+X ~RES 15 450 -350 150 L 50 50 1 1 O
+X ~SIDE 16 450 -600 150 L 50 50 1 1 O
+X ~DDEN 17 450 -150 150 L 50 50 1 1 O
+X ~FDC 18 450 250 150 L 50 50 1 1 O
+X ~IORQ 19 -500 -400 150 R 50 50 1 1 I
+X A1 2 -500 400 150 R 50 50 1 1 I
+X A2 3 -500 300 150 R 50 50 1 1 I
+X A3 4 -500 200 150 R 50 50 1 1 I
+X RESET 5 -500 -750 150 R 50 50 1 1 I
+X A4 6 -500 100 150 R 50 50 1 1 I
+X A5 7 -500 0 150 R 50 50 1 1 I
+X A6 8 -500 -100 150 R 50 50 1 1 I
+X A7 9 -500 -200 150 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# SFD700_PAL12L6
+#
+DEF SFD700_PAL12L6 U 0 40 Y Y 1 F N
+F0 "U" -350 650 50 H V L CNN
+F1 "SFD700_PAL12L6" 50 700 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ PDIP*
+$ENDFPLIST
+DRAW
+S -350 600 300 -850 0 1 10 f
+X GND 10 0 -1000 150 U 50 50 0 0 W
+X VCC 20 0 750 150 D 50 50 0 0 W
+X A0 1 -500 500 150 R 50 50 1 1 I
+X ~WR 11 -500 -500 150 R 50 50 1 1 I
+X ~RD 12 -500 -600 150 R 50 50 1 1 I
+X ~BUS 13 450 400 150 L 50 50 1 1 O
+X ~DRIVE 14 450 50 150 L 50 50 1 1 O
+X ~RES 15 450 -350 150 L 50 50 1 1 O
+X ~SIDE 16 450 -600 150 L 50 50 1 1 O
+X ~DDEN 17 450 -150 150 L 50 50 1 1 O
+X ~FDC 18 450 250 150 L 50 50 1 1 O
+X ~IORQ 19 -500 -400 150 R 50 50 1 1 I
+X A1 2 -500 400 150 R 50 50 1 1 I
+X A2 3 -500 300 150 R 50 50 1 1 I
+X A3 4 -500 200 150 R 50 50 1 1 I
+X RESET 5 -500 -750 150 R 50 50 1 1 I
+X A4 6 -500 100 150 R 50 50 1 1 I
+X A5 7 -500 0 150 R 50 50 1 1 I
+X A6 8 -500 -100 150 R 50 50 1 1 I
+X A7 9 -500 -200 150 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library

kicad/v1.0/SFD700.pretty/BUS_MZ800.kicad_mod

@@ -0,0 +1,74 @@
+(footprint "BUS_MZ800" (version 20221018) (generator pcbnew)
+  (layer "F.Cu")
+  (descr "MZ-800 Bus Edge Connector")
+  (tags "BUS MZ-800 Edge connector")
+  (property "Sheetfile" "SFD700.kicad_sch")
+  (property "Sheetname" "")
+  (attr exclude_from_pos_files)
+  (fp_text reference "J1" (at -0.6096 -6.8072) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp 11d40477-5a4f-401e-a919-552a643d49a6)
+  )
+  (fp_text value "MZ-700 Bus" (at 6.1468 -6.858) (layer "F.Fab") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp 247e4a6b-c18b-4097-98d6-554243a923ab)
+  )
+  (fp_line (start -28.5496 -6.3484) (end -28.5496 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 78ead7dd-80e4-4c2d-babd-c0f89491ca2d))
+  (fp_line (start -28.5472 6.8984) (end 28.7528 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 0a250ba9-6e50-46a7-89b0-c2bbf365867b))
+  (fp_line (start 28.7528 -6.3484) (end 28.7528 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp e5753d89-c96f-48eb-93e2-e61b76cbfcf0))
+  (fp_line (start -28.57 -6.35) (end -28.57 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp cadc0662-16a6-45e9-a66b-fb7f408a3757))
+  (fp_line (start -28.57 -6.35) (end 28.73 -6.35)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1366ef9d-07fe-45c0-aad0-9e392f8a301a))
+  (fp_line (start -28.57 6.8984) (end 28.73 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 7d77b8b2-53d4-4655-9209-38134c9abd84))
+  (fp_line (start 28.73 -6.35) (end 28.73 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9b55e1d7-0104-4de3-a68a-a724763bc172))
+  (pad "1" connect rect (at 26.67 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 2e6f6a09-226e-4e49-b7a1-ce313eb361b1))
+  (pad "2" connect rect (at 26.67 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp 06ee9e61-cc1c-4d4a-9781-99ae175ba629))
+  (pad "3" connect rect (at 24.13 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp bafeaa15-19e1-4e05-b8a4-c681e39d673e))
+  (pad "4" connect rect (at 24.13 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp c3d69cd7-a265-4a4b-b054-8dcc44e9e546))
+  (pad "5" connect rect (at 21.59 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 9aef013b-81e4-46d1-bccc-2f0efeccc03f))
+  (pad "6" connect rect (at 21.59 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp 59e49614-b286-472a-8730-7d03d13dacb5))
+  (pad "7" connect rect (at 19.05 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 90f6e432-02b0-4a51-8256-7b9711b91893))
+  (pad "8" connect rect (at 19.05 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp a6d6b34a-e691-4723-b9f4-3fcf3bfca64f))
+  (pad "9" connect rect (at 16.51 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 4107ed5d-7170-4635-8790-9102b9096469))
+  (pad "10" connect rect (at 16.51 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp a6f91da5-a204-40c0-8d99-83e8755ba0be))
+  (pad "11" connect rect (at 13.97 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp a9652936-3f83-44cd-bf5c-748201d24450))
+  (pad "12" connect rect (at 13.97 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp 45457aaa-13bd-456a-9c5c-c63acd514ab4))
+  (pad "13" connect rect (at 11.43 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp d4462769-279f-4776-9554-b3269c43f9e4))
+  (pad "14" connect rect (at 11.43 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp dc46410c-447e-4ffe-8947-998fa04bee2f))
+  (pad "15" connect rect (at 8.89 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp b2a85bea-a5e8-467e-84d3-0f5e0c026d18))
+  (pad "16" connect rect (at 8.89 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp 96c3ddbd-fe53-4735-b457-eaef299e685b))
+  (pad "17" connect rect (at 6.35 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 221a9f91-1bb9-4847-8e07-48b60662c9bd))
+  (pad "18" connect rect (at 6.35 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp a236c0a9-fc5a-4647-b7fc-b99fa553e0b1))
+  (pad "19" connect rect (at 3.81 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 518726ff-640c-4877-9297-0dac57391a27))
+  (pad "20" connect rect (at 3.81 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp d651e947-a45a-4bdf-9e31-ce35e055450f))
+  (pad "21" connect rect (at 1.27 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 913563c1-6793-4fe0-b565-706e45256349))
+  (pad "22" connect rect (at 1.27 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp 1199a083-9083-4223-90f6-7d503051f5dc))
+  (pad "23" connect rect (at -1.27 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 80bd0220-77d6-430e-8e8f-172f1a9b688b))
+  (pad "24" connect rect (at -1.27 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp d60fcf6d-5674-4b0f-a6f2-fdd76aaf5404))
+  (pad "25" connect rect (at -3.81 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp c0abebe9-3619-4309-8510-9555710bbc3d))
+  (pad "26" connect rect (at -3.81 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp bbf66b4a-84f6-4857-9903-2869907d785e))
+  (pad "27" connect rect (at -6.35 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp e3248e0e-98ed-44c6-848d-478fcc75504c))
+  (pad "28" connect rect (at -6.35 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp e0e43f28-d167-4d6a-bd1a-0af075171f75))
+  (pad "29" connect rect (at -8.89 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 05703975-e70b-48f9-a926-b16e7e4003c8))
+  (pad "30" connect rect (at -8.89 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp f054b17e-cce8-4851-98b5-c6dd5538df53))
+  (pad "31" connect rect (at -11.43 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 274ee3f9-d53a-446f-89c0-c5f01a5a41f4))
+  (pad "32" connect rect (at -11.43 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp bce71e07-a90a-4226-b4a5-9a5a9ebefe26))
+  (pad "33" connect rect (at -13.97 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp b27eb94e-5863-4b78-8cd2-d83e9d929e47))
+  (pad "34" connect rect (at -13.97 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp b413ae7b-83ac-43a0-b6c7-2cc89fd3c32c))
+  (pad "35" connect rect (at -16.51 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 82b20f67-d5f3-4879-8236-0348c3501d8e))
+  (pad "36" connect rect (at -16.51 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp cda55003-e72b-473c-a638-5ed9c1c18988))
+  (pad "37" connect rect (at -19.05 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp a4dbe873-82cf-45e7-8088-39f910e639aa))
+  (pad "38" connect rect (at -19.05 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp be4aadfa-ae85-4532-a938-f4708636360f))
+  (pad "39" connect rect (at -21.59 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 20dec8ec-ce35-4ebb-a284-e1c653b25820))
+  (pad "40" connect rect (at -21.59 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp d65e63e6-8934-4752-b39a-d51dd1f01f89))
+  (pad "41" connect rect (at -24.13 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp dbecc811-fb06-4c88-9aad-13db2dff27e4))
+  (pad "42" connect rect (at -24.13 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp 821e133b-0bf5-487a-aaaf-004ab812cbb9))
+  (pad "43" connect rect (at -26.67 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 2f662a35-6052-4ae0-9e97-e809faa5ba45))
+  (pad "44" connect rect (at -26.67 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp bff8d273-bf8a-44d3-917a-ee189cbcec9b))
+)

kicad/v1.0/fp-lib-table

@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name "SFD700")(type "KiCad")(uri "${KIPRJMOD}/SFD700.pretty")(options "")(descr ""))
+)

kicad/v1.0/sym-lib-table

@@ -0,0 +1,4 @@
+(sym_lib_table
+  (lib (name "SFD700")(type "KiCad")(uri "${KIPRJMOD}/SFD700.kicad_sym")(options "")(descr ""))
+  (lib (name "Custom")(type "KiCad")(uri "${KIPRJMOD}/Custom.kicad_sym")(options "")(descr ""))
+)

kicad/v1.2/Custom.kicad_sym

@@ -0,0 +1,929 @@
+(kicad_symbol_lib (version 20220914) (generator kicad_symbol_editor)
+  (symbol "27C32" (in_bom yes) (on_board yes)
+    (property "Reference" "U" (at -7.62 24.13 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "27C32" (at -1.27 -6.35 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "Package_DIP:DIP-24_W15.24mm" (at -1.27 -22.86 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_keywords" "OTP EPROM 64KiBit" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "OTP EPROM 64 KiBit, [Obsolete 2004-01]" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_fp_filters" "DIP*W15.24mm*" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "27C32_1_1"
+      (rectangle (start -7.62 22.86) (end 7.62 -17.78)
+        (stroke (width 0.254) (type default))
+        (fill (type background))
+      )
+      (pin input line (at -10.16 2.54 0) (length 2.54)
+        (name "A7" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 10.16 17.78 180) (length 2.54)
+        (name "D1" (effects (font (size 1.27 1.27))))
+        (number "10" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 10.16 15.24 180) (length 2.54)
+        (name "D2" (effects (font (size 1.27 1.27))))
+        (number "11" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 -20.32 90) (length 2.54)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "12" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 10.16 12.7 180) (length 2.54)
+        (name "D3" (effects (font (size 1.27 1.27))))
+        (number "13" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 10.16 10.16 180) (length 2.54)
+        (name "D4" (effects (font (size 1.27 1.27))))
+        (number "14" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 10.16 7.62 180) (length 2.54)
+        (name "D5" (effects (font (size 1.27 1.27))))
+        (number "15" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 10.16 5.08 180) (length 2.54)
+        (name "D6" (effects (font (size 1.27 1.27))))
+        (number "16" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 10.16 2.54 180) (length 2.54)
+        (name "D7" (effects (font (size 1.27 1.27))))
+        (number "17" (effects (font (size 1.27 1.27))))
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+      )
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+      )
+      (pin bidirectional line (at -16.51 25.4 0) (length 5.08)
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+    )
+    (symbol "EPM7128SLC84_2_1"
+      (rectangle (start -12.7 8.89) (end 12.7 -8.89)
+        (stroke (width 0.254) (type default))
+        (fill (type background))
+      )
+      (pin input line (at -17.78 3.81 0) (length 5.08)
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+      )
+      (pin bidirectional line (at 17.78 -3.81 180) (length 5.08)
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+        (number "14" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -17.78 -1.27 0) (length 5.08)
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+        (number "2" (effects (font (size 1.27 1.27))))
+      )
+      (pin bidirectional line (at 17.78 -1.27 180) (length 5.08)
+        (name "IO_23/TMS" (effects (font (size 1.27 1.27))))
+        (number "23" (effects (font (size 1.27 1.27))))
+      )
+      (pin bidirectional line (at 17.78 3.81 180) (length 5.08)
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+        (number "62" (effects (font (size 1.27 1.27))))
+      )
+      (pin bidirectional line (at 17.78 1.27 180) (length 5.08)
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+      )
+      (pin input line (at -17.78 1.27 0) (length 5.08)
+        (name "GCLK1" (effects (font (size 1.27 1.27))))
+        (number "83" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -17.78 -3.81 0) (length 5.08)
+        (name "OE1" (effects (font (size 1.27 1.27))))
+        (number "84" (effects (font (size 1.27 1.27))))
+      )
+    )
+    (symbol "EPM7128SLC84_3_1"
+      (rectangle (start -12.7 16.51) (end 10.16 -13.97)
+        (stroke (width 0.254) (type default))
+        (fill (type background))
+      )
+      (pin power_in line (at 15.24 2.54 180) (length 5.08)
+        (name "VCCIO1" (effects (font (size 1.27 1.27))))
+        (number "13" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 7.62 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "19" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 15.24 0 180) (length 5.08)
+        (name "VCCIO2" (effects (font (size 1.27 1.27))))
+        (number "26" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 15.24 12.7 180) (length 5.08)
+        (name "VCCINT1" (effects (font (size 1.27 1.27))))
+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 5.08 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "32" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 15.24 -2.54 180) (length 5.08)
+        (name "VCCIO3" (effects (font (size 1.27 1.27))))
+        (number "38" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 2.54 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "42" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 15.24 10.16 180) (length 5.08)
+        (name "VCCINT2" (effects (font (size 1.27 1.27))))
+        (number "43" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 0 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "47" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 15.24 -5.08 180) (length 5.08)
+        (name "VCCIO4" (effects (font (size 1.27 1.27))))
+        (number "53" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 -2.54 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "59" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 15.24 -7.62 180) (length 5.08)
+        (name "VCCIO5" (effects (font (size 1.27 1.27))))
+        (number "66" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 10.16 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "7" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 -5.08 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "72" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 15.24 -10.16 180) (length 5.08)
+        (name "VCCIO6" (effects (font (size 1.27 1.27))))
+        (number "78" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at -17.78 -7.62 0) (length 5.08)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "82" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+  (symbol "GAL22V10" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+    (property "Reference" "U" (at -8.89 16.51 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "GAL22V10" (at 1.27 16.51 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_keywords" "GAL PLD 16V8" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "Programmable Logic Array, DIP-20/SOIC-20/PLCC-20" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_fp_filters" "DIP* PDIP* SOIC* SO* PLCC*" (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "GAL22V10_0_0"
+      (pin power_in line (at 0 -17.78 90) (length 3.81)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "12" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 17.78 270) (length 3.81)
+        (name "VCC" (effects (font (size 1.27 1.27))))
+        (number "24" (effects (font (size 1.27 1.27))))
+      )
+    )
+    (symbol "GAL22V10_0_1"
+      (rectangle (start -8.89 13.97) (end 8.89 -13.97)
+        (stroke (width 0.254) (type default))
+        (fill (type background))
+      )
+    )
+    (symbol "GAL22V10_1_1"
+      (pin input line (at -12.7 12.7 0) (length 3.81)
+        (name "I1/CLK" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 -10.16 0) (length 3.81)
+        (name "I10" (effects (font (size 1.27 1.27))))
+        (number "10" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 -12.7 0) (length 3.81)
+        (name "I11" (effects (font (size 1.27 1.27))))
+        (number "11" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 -12.7 180) (length 3.81)
+        (name "IO11" (effects (font (size 1.27 1.27))))
+        (number "13" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 -10.16 180) (length 3.81)
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+        (number "14" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 -7.62 180) (length 3.81)
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+        (number "15" (effects (font (size 1.27 1.27))))
+      )
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+        (number "16" (effects (font (size 1.27 1.27))))
+      )
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+        (number "17" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 0 180) (length 3.81)
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+        (number "18" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 2.54 180) (length 3.81)
+        (name "IO5" (effects (font (size 1.27 1.27))))
+        (number "19" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 10.16 0) (length 3.81)
+        (name "I2" (effects (font (size 1.27 1.27))))
+        (number "2" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 5.08 180) (length 3.81)
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+        (number "20" (effects (font (size 1.27 1.27))))
+      )
+      (pin tri_state line (at 12.7 7.62 180) (length 3.81)
+        (name "I03" (effects (font (size 1.27 1.27))))
+        (number "21" (effects (font (size 1.27 1.27))))
+      )
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+        (number "22" (effects (font (size 1.27 1.27))))
+      )
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+      )
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+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 5.08 0) (length 3.81)
+        (name "I4" (effects (font (size 1.27 1.27))))
+        (number "4" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 2.54 0) (length 3.81)
+        (name "I5" (effects (font (size 1.27 1.27))))
+        (number "5" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 0 0) (length 3.81)
+        (name "I6" (effects (font (size 1.27 1.27))))
+        (number "6" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 -2.54 0) (length 3.81)
+        (name "I7" (effects (font (size 1.27 1.27))))
+        (number "7" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -12.7 -5.08 0) (length 3.81)
+        (name "I8" (effects (font (size 1.27 1.27))))
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+      )
+      (pin input line (at -12.7 -7.62 0) (length 3.81)
+        (name "I9" (effects (font (size 1.27 1.27))))
+        (number "9" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+  (symbol "SST39SF040-Memory_Flash" (in_bom yes) (on_board yes)
+    (property "Reference" "U" (at 2.54 33.02 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "SST39SF040-Memory_Flash" (at 0 -30.48 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 0 7.62 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 0 7.62 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "SST39SF040-Memory_Flash_0_0"
+      (pin power_in line (at 0 -19.05 90) (length 2.9972)
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+        (number "16" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 34.29 270) (length 2.9972)
+        (name "VCC" (effects (font (size 1.27 1.27))))
+        (number "32" (effects (font (size 1.27 1.27))))
+      )
+    )
+    (symbol "SST39SF040-Memory_Flash_0_1"
+      (rectangle (start -7.62 31.75) (end 7.62 -16.51)
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+        (fill (type background))
+      )
+    )
+    (symbol "SST39SF040-Memory_Flash_1_1"
+      (pin input line (at -12.7 -15.24 0) (length 5.08)
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+      )
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+        (number "13" (effects (font (size 1.27 1.27))))
+      )
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+        (number "15" (effects (font (size 1.27 1.27))))
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+        (number "17" (effects (font (size 1.27 1.27))))
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+      )
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+      )
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+      )
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+      )
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+      )
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+      )
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+      )
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+        (number "9" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+)

kicad/v1.2/Graphic.pretty/Argo.kicad_mod

@@ -0,0 +1,38 @@
+(module LOGO (layer F.Cu)
+  (at 0 0)
+ (fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
+  )
+  (fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
+  )
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kicad/v1.2/Graphic.pretty/CycloneInside.kicad_mod

@@ -0,0 +1,144 @@
+(module LOGO (layer F.Cu)
+  (at 0 0)
+ (fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
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+  (fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
+  (effects (font (thickness 0.3)))
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kicad/v1.2/Graphic.pretty/IntelInside.kicad_mod

@@ -0,0 +1,291 @@
+(module LOGO (layer F.Cu)
+  (at 0 0)
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+  (effects (font (thickness 0.3)))
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kicad/v1.2/SFD700.kicad_prl

@@ -0,0 +1,78 @@
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+  "meta": {
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+    "version": 3
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+  "project": {
+    "files": []
+  }
+}

kicad/v1.2/SFD700.kicad_pro

@@ -0,0 +1,561 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.049999999999999996,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
+        "silk_line_width": 0.12,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.254
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "ignore",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "ignore",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.024999999999999998,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
+        "min_text_height": 0.7999999999999999,
+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.25,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.5,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 5,
+          "td_on_pad_in_zone": false,
+          "td_onpadsmd": true,
+          "td_onroundshapesonly": false,
+          "td_ontrackend": false,
+          "td_onviapad": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [
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+        0.1524,
+        0.2,
+        0.254,
+        0.381,
+        0.508,
+        0.8128
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        },
+        {
+          "diameter": 0.5,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.5,
+          "drill": 0.35
+        },
+        {
+          "diameter": 0.5,
+          "drill": 0.4
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.5
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
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+    },
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+    "rule_severities": {
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+      "bus_entry_needed": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "error",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "simulation_model_issue": "error",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
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+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "SFD700.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      },
+      {
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+        "clearance": 0.2,
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+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Power",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.5,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 3
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": [
+      {
+        "netclass": "Power",
+        "pattern": "+5V"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "GNDPWR"
+      }
+    ]
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "SFD700.dsn",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
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+    "drawing": {
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+      "dashed_lines_gap_length_ratio": 3.0,
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+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "",
+    "ngspice": {
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+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_voltages": false,
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
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+    ],
+    [
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+    [
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+      "Logic Sheet"
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+  ],
+  "text_variables": {}
+}

kicad/v1.2/SFD700.kicad_sch

@@ -0,0 +1,362 @@
+(kicad_sch (version 20230121) (generator eeschema)
+
+  (uuid 418bd263-f0a9-42da-88ea-160d6eff482c)
+
+  (paper "A4")
+
+  (title_block
+    (title "SFD-700 Floppy Interface MKII")
+    (date "2023-07-27")
+    (rev "1.2")
+    (comment 1 "and enhanced to operate with the MZ-80A.")
+    (comment 2 "This is a redesign of the K&P card using the SFD-700 & SFD-800 schematics as the base")
+    (comment 3 "with the MZ-80B/MZ-800/MZ-1500/MZ-2000/MZ-2200.")
+    (comment 4 "SFD-700 Floppy Disk Interface card for the Sharp MZ-80A/MZ-700, also compatible")
+  )
+
+  (lib_symbols
+    (symbol "Mechanical:MountingHole_Pad" (pin_numbers hide) (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes)
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+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Value" "MountingHole_Pad" (at 0 4.445 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "~" (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "mounting hole" (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Mounting Hole with connection" (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_fp_filters" "MountingHole*Pad*" (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "MountingHole_Pad_0_1"
+        (circle (center 0 1.27) (radius 1.27)
+          (stroke (width 1.27) (type default))
+          (fill (type none))
+        )
+      )
+      (symbol "MountingHole_Pad_1_1"
+        (pin input line (at 0 -2.54 90) (length 2.54)
+          (name "1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "power:GNDPWR" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+      (property "Reference" "#PWR" (at 0 -5.08 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Value" "GNDPWR" (at 0 -3.302 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (at 0 -1.27 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "" (at 0 -1.27 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "global ground" (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Power symbol creates a global label with name \"GNDPWR\" , global ground" (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "GNDPWR_0_1"
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+          (fill (type none))
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+      )
+      (symbol "GNDPWR_1_1"
+        (pin power_in line (at 0 0 270) (length 0) hide
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+        )
+      )
+    )
+  )
+
+  (junction (at 34.29 43.18) (diameter 0) (color 0 0 0 0)
+    (uuid 33a04eab-6cd0-4366-a1dd-326dc9f6235e)
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+      (effects (font (size 1.27 1.27)) (justify left))
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+    (property "Footprint" "MountingHole:MountingHole_2.7mm_M2.5_Pad" (at 48.26 49.53 0)
+      (effects (font (size 1.27 1.27)) hide)
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+    (property "Datasheet" "~" (at 48.26 49.53 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid bfd3d638-4c21-4e68-b8b5-a838ad40a322))
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+      (project "SFD700"
+        (path "/418bd263-f0a9-42da-88ea-160d6eff482c"
+          (reference "H4") (unit 1)
+        )
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+  )
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+  (symbol (lib_id "power:GNDPWR") (at 34.29 55.88 0) (unit 1)
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+      (effects (font (size 1.27 1.27)) hide)
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+      (effects (font (size 1.27 1.27)) hide)
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+    (pin "1" (uuid d630ea9a-4b21-45bc-998d-53c837f06cb1))
+    (instances
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+  (symbol (lib_id "Mechanical:MountingHole_Pad") (at 34.29 36.83 0) (unit 1)
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+    (property "Value" "Mounting" (at 36.83 36.8373 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "MountingHole:MountingHole_2.7mm_M2.5_Pad" (at 34.29 36.83 0)
+      (effects (font (size 1.27 1.27)) hide)
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+    (property "Datasheet" "~" (at 34.29 36.83 0)
+      (effects (font (size 1.27 1.27)) hide)
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+    (pin "1" (uuid 226fc6c0-6771-4591-949a-e16d914d8acc))
+    (instances
+      (project "SFD700"
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+  (symbol (lib_id "Mechanical:MountingHole_Pad") (at 34.29 49.53 0) (unit 1)
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+    (property "Reference" "H2" (at 36.83 47.6163 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "Mounting" (at 36.83 49.5373 0)
+      (effects (font (size 1.27 1.27)) (justify left))
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+    (pin "1" (uuid 3c3a9f3b-f82a-4dfe-914e-fbb6533f29bb))
+    (instances
+      (project "SFD700"
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+  (symbol (lib_id "Mechanical:MountingHole_Pad") (at 48.26 36.83 0) (unit 1)
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+    (property "Reference" "H3" (at 50.8 34.9163 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "Mounting" (at 50.8 36.8373 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "MountingHole:MountingHole_2.7mm_M2.5_Pad" (at 48.26 36.83 0)
+      (effects (font (size 1.27 1.27)) hide)
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+      (effects (font (size 1.27 1.27)) hide)
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+    (pin "1" (uuid b6183afd-4afa-432c-916a-22778986e285))
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+  )
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+  (sheet (at 81.28 96.52) (size 137.795 60.96) (fields_autoplaced)
+    (stroke (width 0.1524) (type solid))
+    (fill (color 0 0 0 0.0000))
+    (uuid 363ead2c-6df6-40be-a0a2-b05dcc50e412)
+    (property "Sheetname" "Power Decoupling" (at 81.28 95.8084 0)
+      (effects (font (size 1.27 1.27)) (justify left bottom))
+    )
+    (property "Sheetfile" "PowerDecoupling.kicad_sch" (at 81.28 158.0646 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (instances
+      (project "SFD700"
+        (path "/418bd263-f0a9-42da-88ea-160d6eff482c" (page "2"))
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+    )
+  )
+
+  (sheet (at 81.28 24.765) (size 137.795 62.865) (fields_autoplaced)
+    (stroke (width 0.1524) (type solid))
+    (fill (color 0 0 0 0.0000))
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+    (property "Sheetname" "Logic Sheet" (at 81.28 24.0534 0)
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+    (property "Sheetfile" "Logic.kicad_sch" (at 81.28 88.2146 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (instances
+      (project "SFD700"
+        (path "/418bd263-f0a9-42da-88ea-160d6eff482c" (page "3"))
+      )
+    )
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+)

kicad/v1.2/SFD700.lib

@@ -0,0 +1,253 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Ext_Bus_MZ800
+#
+DEF Ext_Bus_MZ800 J 0 20 Y Y 1 F N
+F0 "J" 0 1225 50 H V C CNN
+F1 "Ext_Bus_MZ800" 0 -1225 50 H V C CNN
+F2 "" 0 -450 50 H I C CNN
+F3 "" 0 -450 50 H I C CNN
+DRAW
+T 0 -200 1150 31 0 0 0 " Top Side" Normal 0 C C
+T 0 150 1150 31 0 0 0 "Bottom Side" Normal 0 C C
+S -300 -1150 300 1200 0 1 10 f
+X VCC 1 -400 1050 100 R 50 50 1 1 w
+X D6 10 400 650 100 L 50 50 1 1 T
+X AD15 11 -400 550 100 R 50 50 1 1 O
+X D7 12 400 550 100 L 50 50 1 1 T
+X AD14 13 -400 450 100 R 50 50 1 1 O
+X BUS0 14 400 450 100 L 50 50 1 1 O
+X AD13 15 -400 350 100 R 50 50 1 1 O
+X ~M1 16 400 350 100 L 50 50 1 1 O
+X AD12 17 -400 250 100 R 50 50 1 1 O
+X ~WR 18 400 250 100 L 50 50 1 1 O
+X AD11 19 -400 150 100 R 50 50 1 1 O
+X VCC 2 400 1050 100 L 50 50 1 1 W
+X ~RD 20 400 150 100 L 50 50 1 1 O
+X AD10 21 -400 50 100 R 50 50 1 1 O
+X ~IORQ 22 400 50 100 L 50 50 1 1 O
+X AD9 23 -400 -50 100 R 50 50 1 1 O
+X ~MREQ 24 400 -50 100 L 50 50 1 1 O
+X AD8 25 -400 -150 100 R 50 50 1 1 O
+X GND 26 400 -150 100 L 50 50 1 1 w
+X AD7 27 -400 -250 100 R 50 50 1 1 O
+X ~HALT 28 400 -250 100 L 50 50 1 1 I
+X AD6 29 -400 -350 100 R 50 50 1 1 O
+X D2 3 -400 950 100 R 50 50 1 1 T
+X IE1 30 400 -350 100 L 50 50 1 1 I
+X AD5 31 -400 -450 100 R 50 50 1 1 O
+X NC 32 400 -450 100 L 50 50 1 1 P
+X AD4 33 -400 -550 100 R 50 50 1 1 O
+X RESET 34 400 -550 100 L 50 50 1 1 O
+X AD3 35 -400 -650 100 R 50 50 1 1 O
+X ~EXRESET 36 400 -650 100 L 50 50 1 1 I
+X AD2 37 -400 -750 100 R 50 50 1 1 O
+X ~INT 38 400 -750 100 L 50 50 1 1 I
+X AD1 39 -400 -850 100 R 50 50 1 1 O
+X D3 4 400 950 100 L 50 50 1 1 T
+X ~EXWAIT 40 400 -850 100 L 50 50 1 1 I
+X AD0 41 -400 -950 100 R 50 50 1 1 O
+X NC 42 400 -950 100 L 50 50 1 1 P
+X GND 43 -400 -1050 100 R 50 50 1 1 W
+X GND 44 400 -1050 100 L 50 50 1 1 W
+X D1 5 -400 850 100 R 50 50 1 1 T
+X D4 6 400 850 100 L 50 50 1 1 T
+X D0 7 -400 750 100 R 50 50 1 1 T
+X D5 8 400 750 100 L 50 50 1 1 T
+X GND 9 -400 650 100 R 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# PAL12L6
+#
+DEF PAL12L6 U 0 40 Y Y 1 F N
+F0 "U" -350 650 50 H V L CNN
+F1 "PAL12L6" 50 700 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ PDIP*
+$ENDFPLIST
+DRAW
+S -350 600 300 -850 0 1 10 f
+X GND 10 0 -1000 150 U 50 50 0 0 W
+X VCC 20 0 750 150 D 50 50 0 0 W
+X A0 1 -500 500 150 R 50 50 1 1 I
+X ~WR 11 -500 -500 150 R 50 50 1 1 I
+X ~RD 12 -500 -600 150 R 50 50 1 1 I
+X ~BUS 13 450 400 150 L 50 50 1 1 O
+X ~DRIVE 14 450 50 150 L 50 50 1 1 O
+X ~RES 15 450 -350 150 L 50 50 1 1 O
+X ~SIDE 16 450 -600 150 L 50 50 1 1 O
+X ~DDEN 17 450 -150 150 L 50 50 1 1 O
+X ~FDC 18 450 250 150 L 50 50 1 1 O
+X ~IORQ 19 -500 -400 150 R 50 50 1 1 I
+X A1 2 -500 400 150 R 50 50 1 1 I
+X A2 3 -500 300 150 R 50 50 1 1 I
+X A3 4 -500 200 150 R 50 50 1 1 I
+X RESET 5 -500 -750 150 R 50 50 1 1 I
+X A4 6 -500 100 150 R 50 50 1 1 I
+X A5 7 -500 0 150 R 50 50 1 1 I
+X A6 8 -500 -100 150 R 50 50 1 1 I
+X A7 9 -500 -200 150 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Connector_Generic_Conn_02x17_Odd_Even
+#
+DEF Connector_Generic_Conn_02x17_Odd_Even J 0 40 Y N 1 F N
+F0 "J" 50 900 50 H V C CNN
+F1 "Connector_Generic_Conn_02x17_Odd_Even" 50 -900 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_2x??_*
+$ENDFPLIST
+DRAW
+S -50 -795 0 -805 1 1 6 N
+S -50 -695 0 -705 1 1 6 N
+S -50 -595 0 -605 1 1 6 N
+S -50 -495 0 -505 1 1 6 N
+S -50 -395 0 -405 1 1 6 N
+S -50 -295 0 -305 1 1 6 N
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 305 0 295 1 1 6 N
+S -50 405 0 395 1 1 6 N
+S -50 505 0 495 1 1 6 N
+S -50 605 0 595 1 1 6 N
+S -50 705 0 695 1 1 6 N
+S -50 805 0 795 1 1 6 N
+S -50 850 150 -850 1 1 10 f
+S 150 -795 100 -805 1 1 6 N
+S 150 -695 100 -705 1 1 6 N
+S 150 -595 100 -605 1 1 6 N
+S 150 -495 100 -505 1 1 6 N
+S 150 -395 100 -405 1 1 6 N
+S 150 -295 100 -305 1 1 6 N
+S 150 -195 100 -205 1 1 6 N
+S 150 -95 100 -105 1 1 6 N
+S 150 5 100 -5 1 1 6 N
+S 150 105 100 95 1 1 6 N
+S 150 205 100 195 1 1 6 N
+S 150 305 100 295 1 1 6 N
+S 150 405 100 395 1 1 6 N
+S 150 505 100 495 1 1 6 N
+S 150 605 100 595 1 1 6 N
+S 150 705 100 695 1 1 6 N
+S 150 805 100 795 1 1 6 N
+X Pin_1 1 -200 800 150 R 50 50 1 1 P
+X Pin_10 10 300 400 150 L 50 50 1 1 P
+X Pin_11 11 -200 300 150 R 50 50 1 1 P
+X Pin_12 12 300 300 150 L 50 50 1 1 P
+X Pin_13 13 -200 200 150 R 50 50 1 1 P
+X Pin_14 14 300 200 150 L 50 50 1 1 P
+X Pin_15 15 -200 100 150 R 50 50 1 1 P
+X Pin_16 16 300 100 150 L 50 50 1 1 P
+X Pin_17 17 -200 0 150 R 50 50 1 1 P
+X Pin_18 18 300 0 150 L 50 50 1 1 P
+X Pin_19 19 -200 -100 150 R 50 50 1 1 P
+X Pin_2 2 300 800 150 L 50 50 1 1 P
+X Pin_20 20 300 -100 150 L 50 50 1 1 P
+X Pin_21 21 -200 -200 150 R 50 50 1 1 P
+X Pin_22 22 300 -200 150 L 50 50 1 1 P
+X Pin_23 23 -200 -300 150 R 50 50 1 1 P
+X Pin_24 24 300 -300 150 L 50 50 1 1 P
+X Pin_25 25 -200 -400 150 R 50 50 1 1 P
+X Pin_26 26 300 -400 150 L 50 50 1 1 P
+X Pin_27 27 -200 -500 150 R 50 50 1 1 P
+X Pin_28 28 300 -500 150 L 50 50 1 1 P
+X Pin_29 29 -200 -600 150 R 50 50 1 1 P
+X Pin_3 3 -200 700 150 R 50 50 1 1 P
+X Pin_30 30 300 -600 150 L 50 50 1 1 P
+X Pin_31 31 -200 -700 150 R 50 50 1 1 P
+X Pin_32 32 300 -700 150 L 50 50 1 1 P
+X Pin_33 33 -200 -800 150 R 50 50 1 1 P
+X Pin_34 34 300 -800 150 L 50 50 1 1 P
+X Pin_4 4 300 700 150 L 50 50 1 1 P
+X Pin_5 5 -200 600 150 R 50 50 1 1 P
+X Pin_6 6 300 600 150 L 50 50 1 1 P
+X Pin_7 7 -200 500 150 R 50 50 1 1 P
+X Pin_8 8 300 500 150 L 50 50 1 1 P
+X Pin_9 9 -200 400 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# SFD700_PAL12L6
+#
+DEF SFD700_PAL12L6 U 0 40 Y Y 1 F N
+F0 "U" -350 650 50 H V L CNN
+F1 "SFD700_PAL12L6" 50 700 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ PDIP*
+$ENDFPLIST
+DRAW
+S -350 600 300 -850 0 1 10 f
+X GND 10 0 -1000 150 U 50 50 0 0 W
+X VCC 20 0 750 150 D 50 50 0 0 W
+X A0 1 -500 500 150 R 50 50 1 1 I
+X ~WR 11 -500 -500 150 R 50 50 1 1 I
+X ~RD 12 -500 -600 150 R 50 50 1 1 I
+X ~BUS 13 450 400 150 L 50 50 1 1 O
+X ~DRIVE 14 450 50 150 L 50 50 1 1 O
+X ~RES 15 450 -350 150 L 50 50 1 1 O
+X ~SIDE 16 450 -600 150 L 50 50 1 1 O
+X ~DDEN 17 450 -150 150 L 50 50 1 1 O
+X ~FDC 18 450 250 150 L 50 50 1 1 O
+X ~IORQ 19 -500 -400 150 R 50 50 1 1 I
+X A1 2 -500 400 150 R 50 50 1 1 I
+X A2 3 -500 300 150 R 50 50 1 1 I
+X A3 4 -500 200 150 R 50 50 1 1 I
+X RESET 5 -500 -750 150 R 50 50 1 1 I
+X A4 6 -500 100 150 R 50 50 1 1 I
+X A5 7 -500 0 150 R 50 50 1 1 I
+X A6 8 -500 -100 150 R 50 50 1 1 I
+X A7 9 -500 -200 150 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# SFD700_PAL12L6
+#
+DEF SFD700_PAL12L6 U 0 40 Y Y 1 F N
+F0 "U" -350 650 50 H V L CNN
+F1 "SFD700_PAL12L6" 50 700 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ PDIP*
+$ENDFPLIST
+DRAW
+S -350 600 300 -850 0 1 10 f
+X GND 10 0 -1000 150 U 50 50 0 0 W
+X VCC 20 0 750 150 D 50 50 0 0 W
+X A0 1 -500 500 150 R 50 50 1 1 I
+X ~WR 11 -500 -500 150 R 50 50 1 1 I
+X ~RD 12 -500 -600 150 R 50 50 1 1 I
+X ~BUS 13 450 400 150 L 50 50 1 1 O
+X ~DRIVE 14 450 50 150 L 50 50 1 1 O
+X ~RES 15 450 -350 150 L 50 50 1 1 O
+X ~SIDE 16 450 -600 150 L 50 50 1 1 O
+X ~DDEN 17 450 -150 150 L 50 50 1 1 O
+X ~FDC 18 450 250 150 L 50 50 1 1 O
+X ~IORQ 19 -500 -400 150 R 50 50 1 1 I
+X A1 2 -500 400 150 R 50 50 1 1 I
+X A2 3 -500 300 150 R 50 50 1 1 I
+X A3 4 -500 200 150 R 50 50 1 1 I
+X RESET 5 -500 -750 150 R 50 50 1 1 I
+X A4 6 -500 100 150 R 50 50 1 1 I
+X A5 7 -500 0 150 R 50 50 1 1 I
+X A6 8 -500 -100 150 R 50 50 1 1 I
+X A7 9 -500 -200 150 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library

kicad/v1.2/SFD700.pretty/BUS_MZ800.kicad_mod

@@ -0,0 +1,74 @@
+(footprint "BUS_MZ800" (version 20221018) (generator pcbnew)
+  (layer "F.Cu")
+  (descr "MZ-800 Bus Edge Connector")
+  (tags "BUS MZ-800 Edge connector")
+  (property "Sheetfile" "SFD700.kicad_sch")
+  (property "Sheetname" "")
+  (attr exclude_from_pos_files)
+  (fp_text reference "J1" (at -0.6096 -6.8072) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp 11d40477-5a4f-401e-a919-552a643d49a6)
+  )
+  (fp_text value "MZ-700 Bus" (at 6.1468 -6.858) (layer "F.Fab") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp 247e4a6b-c18b-4097-98d6-554243a923ab)
+  )
+  (fp_line (start -28.5496 -6.3484) (end -28.5496 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 78ead7dd-80e4-4c2d-babd-c0f89491ca2d))
+  (fp_line (start -28.5472 6.8984) (end 28.7528 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 0a250ba9-6e50-46a7-89b0-c2bbf365867b))
+  (fp_line (start 28.7528 -6.3484) (end 28.7528 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp e5753d89-c96f-48eb-93e2-e61b76cbfcf0))
+  (fp_line (start -28.57 -6.35) (end -28.57 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp cadc0662-16a6-45e9-a66b-fb7f408a3757))
+  (fp_line (start -28.57 -6.35) (end 28.73 -6.35)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1366ef9d-07fe-45c0-aad0-9e392f8a301a))
+  (fp_line (start -28.57 6.8984) (end 28.73 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 7d77b8b2-53d4-4655-9209-38134c9abd84))
+  (fp_line (start 28.73 -6.35) (end 28.73 6.8984)
+    (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9b55e1d7-0104-4de3-a68a-a724763bc172))
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+  (pad "42" connect rect (at -24.13 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp 821e133b-0bf5-487a-aaaf-004ab812cbb9))
+  (pad "43" connect rect (at -26.67 0.2032) (size 1.5 13) (layers "F.Cu" "F.Mask") (tstamp 2f662a35-6052-4ae0-9e97-e809faa5ba45))
+  (pad "44" connect rect (at -26.67 0.2032) (size 1.5 13) (layers "B.Cu" "B.Mask") (tstamp bff8d273-bf8a-44d3-917a-ee189cbcec9b))
+)

kicad/v1.2/fp-lib-table

@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name "SFD700")(type "KiCad")(uri "${KIPRJMOD}/SFD700.pretty")(options "")(descr ""))
+)

kicad/v1.2/sym-lib-table

@@ -0,0 +1,4 @@
+(sym_lib_table
+  (lib (name "SFD700")(type "KiCad")(uri "${KIPRJMOD}/SFD700.kicad_sym")(options "")(descr ""))
+  (lib (name "Custom")(type "KiCad")(uri "${KIPRJMOD}/Custom.kicad_sym")(options "")(descr ""))
+)