145 lines
8.8 KiB
VHDL
Vendored
145 lines
8.8 KiB
VHDL
Vendored
---------------------------------------------------------------------------------------------------------
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--
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-- Name: sfd700_Toplevel.vhd
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-- Created: July 2023
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-- Author(s): Philip Smart
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-- Description: SFD700 CPLD configuration file.
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--
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-- This module contains parameters for the CPLD in the SFD700 Floppy Disk Interface
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-- project.
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--
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-- Credits:
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-- Copyright: (c) 2018-23 Philip Smart <philip.smart@net2net.org>
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--
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-- History: July 2023 - Initial write.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.sfd700_pkg.all;
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library altera;
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use altera.altera_syn_attributes.all;
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entity sfd700 is
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port (
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-- Z80 Address Bus
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Z80_ADDR : in std_logic_vector(15 downto 0); -- Host Address Bus.
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-- Z80 Data Bus
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Z80_DATA : inout std_logic_vector(7 downto 0); -- Host Data Bus.
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-- Z80 Control signals.
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Z80_M1n : in std_logic; -- Host M1n input.
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Z80_RDn : in std_logic; -- Host RDn input.
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Z80_WRn : in std_logic; -- Host WRn input.
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Z80_IORQn : in std_logic; -- Host IORQn input.
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Z80_MREQn : in std_logic; -- Host MREQn input.
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Z80_INT : out std_logic; -- Host INT output, active high.
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Z80_EXWAITn : out std_logic; -- Host external Wait output.
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-- Reset.
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Z80_RESETn : in std_logic; -- Host RESET signal.
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-- Inverted Data to FDC and High Address Bits to ROM/RAM.
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ID : inout std_logic_vector(7 downto 0);
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-- ROM/RAM Control Signals.
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ROM_A10 : out std_logic; -- Flash ROM A10 line - additional address bit and used for MZ-80A DRQ code selection.
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RAM_A10 : out std_logic; -- RAM A10 line - additional address bit.
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ROM_CSn : out std_logic; -- Chip select for Flash ROM.
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RAM_CSn : out std_logic; -- Chip select for Flash RAM.
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RSV : out std_logic; -- Reserved.
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-- Interface Configuration.
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MODE : in std_logic_vector(2 downto 0); -- Jumper settings to configure interface behaviour.
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-- Floppy Disk Interface.
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FDCn : out std_logic; -- WD1773 chip select.
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INTRQ : in std_logic; -- WD1773 Interrupt.
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DRQ : in std_logic; -- WD1773 Data Request.
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DDENn : out std_logic; -- WD1773 Double Data Rate Enable.
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SIDE1 : out std_logic; -- Side 1 of disk select.
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MOTOR : out std_logic; -- Motor on signal.
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DRVSAn : out std_logic; -- Drive A select.
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DRVSBn : out std_logic; -- Drive B select.
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DRVSCn : out std_logic; -- Drive C select.
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DRVSDn : out std_logic; -- Drive D select.
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-- Clocks.
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CLK_16M : in std_logic; -- 16MHz primary oscillator.
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CLK_FDC : out std_logic; -- 8MHz clock to drive WD1773.
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CLK_BUS0 : in std_logic -- Host clock.
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);
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END entity;
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architecture rtl of sfd700 is
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begin
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cpldl128Toplevel : entity work.cpld128
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port map
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(
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-- Z80 Address Bus
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Z80_ADDR => Z80_ADDR, -- Host Address Bus.
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-- Z80 Data Bus
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Z80_DATA => Z80_DATA, -- Host Data Bus.
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-- Z80 Control signals.
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Z80_M1n => Z80_M1n, -- Host M1n input.
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Z80_RDn => Z80_RDn, -- Host RDn input.
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Z80_WRn => Z80_WRn, -- Host WRn input.
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Z80_IORQn => Z80_IORQn, -- Host IORQn input.
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Z80_MREQn => Z80_MREQn, -- Host MREQn input.
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Z80_INT => Z80_INT, -- Host INT output, active high.
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Z80_EXWAITn => Z80_EXWAITn, -- Host external Wait output.
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-- Reset.
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Z80_RESETn => Z80_RESETn, -- Host RESET signal.
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-- Inverted Data to FDC and High Address Bits to ROM/RAM.
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ID => ID,
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-- ROM/RAM Control Signals.
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ROM_A10 => ROM_A10, -- Flash ROM A10 line - additional address bit and used for MZ-80A DRQ code selection.
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RAM_A10 => RAM_A10, -- RAM A10 line - additional address bit.
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ROM_CSn => ROM_CSn, -- Chip select for Flash ROM.
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RAM_CSn => RAM_CSn, -- Chip select for Flash RAM.
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RSV => RSV, -- Reserved.
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-- Interface Configuration.
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MODE => MODE, -- Jumper settings to configure interface behaviour.
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-- Floppy Disk Interface.
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FDCn => FDCn, -- WD1773 chip select.
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INTRQ => INTRQ, -- WD1773 Interrupt.
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DRQ => DRQ, -- WD1773 Data Request.
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DDENn => DDENn, -- WD1773 Double Data Rate Enable.
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SIDE1 => SIDE1, -- Side 1 of disk select.
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MOTOR => MOTOR, -- Motor on signal.
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DRVSAn => DRVSAn, -- Drive A select.
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DRVSBn => DRVSBn, -- Drive B select.
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DRVSCn => DRVSCn, -- Drive C select.
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DRVSDn => DRVSDn, -- Drive D select.
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-- Clocks.
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CLK_16M => CLK_16M, -- 16MHz primary oscillator.
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CLK_FDC => CLK_FDC, -- 8MHz clock to drive WD1773.
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CLK_BUS0 => CLK_BUS0 -- Host clock.
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);
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end architecture;
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