164 lines
6.5 KiB
Plaintext
Vendored
164 lines
6.5 KiB
Plaintext
Vendored
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 16:29:32 June 24, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# tzpuFusionX_MZ700.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY MAX7000S
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set_global_assignment -name DEVICE "EPM7128SLC84-15"
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set_global_assignment -name TOP_LEVEL_ENTITY sfd700
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JULY 27, 2023"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
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set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
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set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
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# Z80 Address Bus
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# ===============
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set_location_assignment PIN_4 -to Z80_ADDR[0]
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set_location_assignment PIN_5 -to Z80_ADDR[1]
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set_location_assignment PIN_6 -to Z80_ADDR[2]
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set_location_assignment PIN_8 -to Z80_ADDR[3]
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set_location_assignment PIN_9 -to Z80_ADDR[4]
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set_location_assignment PIN_10 -to Z80_ADDR[5]
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set_location_assignment PIN_11 -to Z80_ADDR[6]
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set_location_assignment PIN_15 -to Z80_ADDR[7]
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set_location_assignment PIN_16 -to Z80_ADDR[8]
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set_location_assignment PIN_17 -to Z80_ADDR[9]
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set_location_assignment PIN_18 -to Z80_ADDR[10]
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set_location_assignment PIN_20 -to Z80_ADDR[11]
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set_location_assignment PIN_21 -to Z80_ADDR[12]
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set_location_assignment PIN_22 -to Z80_ADDR[13]
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set_location_assignment PIN_24 -to Z80_ADDR[14]
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set_location_assignment PIN_25 -to Z80_ADDR[15]
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# Z80 Data Bus
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# ============
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set_location_assignment PIN_27 -to Z80_DATA[0]
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set_location_assignment PIN_28 -to Z80_DATA[1]
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set_location_assignment PIN_29 -to Z80_DATA[2]
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set_location_assignment PIN_30 -to Z80_DATA[3]
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set_location_assignment PIN_31 -to Z80_DATA[4]
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set_location_assignment PIN_33 -to Z80_DATA[5]
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set_location_assignment PIN_34 -to Z80_DATA[6]
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set_location_assignment PIN_35 -to Z80_DATA[7]
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# Z80 Control signals.
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# ====================
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set_location_assignment PIN_36 -to Z80_M1n
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set_location_assignment PIN_37 -to Z80_RDn
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set_location_assignment PIN_39 -to Z80_WRn
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set_location_assignment PIN_40 -to Z80_IORQn
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set_location_assignment PIN_41 -to Z80_MREQn
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set_location_assignment PIN_44 -to Z80_INT
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set_location_assignment PIN_45 -to Z80_EXWAITn
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# Mode Select
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# ===========
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set_location_assignment PIN_49 -to MODE[0]
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set_location_assignment PIN_48 -to MODE[1]
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set_location_assignment PIN_50 -to MODE[2]
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# Inverted Data Bus
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# =================
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set_location_assignment PIN_74 -to ID[0]
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set_location_assignment PIN_73 -to ID[1]
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set_location_assignment PIN_70 -to ID[2]
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set_location_assignment PIN_69 -to ID[3]
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set_location_assignment PIN_68 -to ID[4]
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set_location_assignment PIN_67 -to ID[5]
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set_location_assignment PIN_65 -to ID[6]
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set_location_assignment PIN_64 -to ID[7]
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# FDC Control Signals
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# ===================
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set_location_assignment PIN_63 -to FDCn
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set_location_assignment PIN_61 -to INTRQ
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set_location_assignment PIN_60 -to DRQ
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set_location_assignment PIN_58 -to DDENn
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set_location_assignment PIN_57 -to SIDE1
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set_location_assignment PIN_56 -to MOTOR
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set_location_assignment PIN_55 -to DRVSAn
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set_location_assignment PIN_54 -to DRVSBn
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set_location_assignment PIN_52 -to DRVSCn
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set_location_assignment PIN_51 -to DRVSDn
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# Memory Control Signals
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# ======================
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set_location_assignment PIN_80 -to ROM_A10
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set_location_assignment PIN_79 -to RAM_A10
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set_location_assignment PIN_77 -to ROM_CSn
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set_location_assignment PIN_76 -to RAM_CSn
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set_location_assignment PIN_75 -to RSV
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# Clocks
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# ======
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set_location_assignment PIN_81 -to CLK_FDC
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set_location_assignment PIN_83 -to CLK_16M
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set_location_assignment PIN_2 -to CLK_BUS0
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set_global_assignment -name VHDL_FILE ../sfd700_Toplevel.vhd
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set_global_assignment -name VHDL_FILE ../sfd700_pkg.vhd
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set_global_assignment -name VHDL_FILE ../sfd700.vhd
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set_global_assignment -name SDC_FILE sfd700_constraints.sdc
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name AUTO_RESOURCE_SHARING OFF
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set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
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set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF
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set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF
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set_global_assignment -name AUTO_LCELL_INSERTION ON
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set_global_assignment -name CDF_FILE output_files/sfd700.cdf
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set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
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