139 lines
6.1 KiB
Tcl
Vendored
139 lines
6.1 KiB
Tcl
Vendored
## Generated SDC file "tzpuFusionX.out.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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## DATE "Fri Jun 26 22:10:05 2020"
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##
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## DEVICE "EPM7160STC100-10"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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# Standard mainboard clock. Varies so take 4MHz being maximum.
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#create_clock -name {CLK_BUS0} -period 250.00 -waveform { 0.000 125.000 } [get_ports { CLK_BUS0 }]
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# For 16MHz crystal.
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create_clock -name {CLK_16M} -period 62.500 -waveform { 0.000 31.250 } [ get_ports { CLK_16M }]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_ADDR[*]}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_DATA[*]}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {ID[*]}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_WRn}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_RDn}]
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#set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_M1n}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_MREQn}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_IORQn}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_RESETn}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {MODE[*]}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {INTRQ}]
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set_input_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {DRQ}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_DATA[*]}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {ID[*]}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_INT}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {Z80_EXWAITn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {ROM_A10}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {RAM_A10}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {ROM_CSn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {RAM_CSn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {RSV}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {FDCn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {DDENn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {SIDE1}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {MOTOR}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {DRVSAn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {DRVSBn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {DRVSCn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {DRVSDn}]
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set_output_delay -add_delay -clock [get_clocks {CLK_16M}] 1.000 [get_ports {CLK_FDC}]
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#**************************************************************
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# Set Max Delay
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#**************************************************************
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#**************************************************************
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# Set Min Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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