477 lines
25 KiB
VHDL
Vendored
477 lines
25 KiB
VHDL
Vendored
-------------------------------------------------------------------------------------------------------
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--
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-- Name: sfd700.vhd
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-- Created: July 2023
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-- Author(s): Philip Smart
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-- Description: SFD700 CPLD configuration file.
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--
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-- This module contains parameters for the CPLD in the SFD700 Floppy Disk Interface
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-- project.
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--
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-- Credits:
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-- Copyright: (c) 2018-23 Philip Smart <philip.smart@net2net.org>
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--
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-- History: July 2023 - v1.0 - Initial write.
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library ieee;
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library pkgs;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.sfd700_pkg.all;
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entity cpld128 is
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port (
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-- Z80 Address Bus
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Z80_ADDR : in std_logic_vector(15 downto 0); -- Host Address Bus.
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-- Z80 Data Bus
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Z80_DATA : inout std_logic_vector(7 downto 0); -- Host Data Bus.
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-- Z80 Control signals.
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Z80_M1n : in std_logic; -- Host M1n input.
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Z80_RDn : in std_logic; -- Host RDn input.
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Z80_WRn : in std_logic; -- Host WRn input.
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Z80_IORQn : in std_logic; -- Host IORQn input.
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Z80_MREQn : in std_logic; -- Host MREQn input.
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Z80_INT : out std_logic; -- Host INT output, active high.
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Z80_EXWAITn : out std_logic; -- Host external Wait output.
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-- Reset.
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Z80_RESETn : in std_logic; -- Host RESET signal.
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-- Inverted Data to FDC and High Address Bits to ROM/RAM.
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ID : inout std_logic_vector(7 downto 0);
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-- ROM/RAM Control Signals.
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ROM_A10 : out std_logic; -- Flash ROM A10 line - additional address bit and used for MZ-80A DRQ code selection.
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RAM_A10 : out std_logic; -- RAM A10 line - additional address bit.
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ROM_CSn : out std_logic; -- Chip select for Flash ROM.
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RAM_CSn : out std_logic; -- Chip select for Flash RAM.
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RSV : out std_logic; -- Reserved.
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-- Interface Configuration.
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MODE : in std_logic_vector(2 downto 0); -- Jumper settings to configure interface behaviour.
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-- Floppy Disk Interface.
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FDCn : out std_logic; -- WD1773 chip select.
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INTRQ : in std_logic; -- WD1773 Interrupt.
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DRQ : in std_logic; -- WD1773 Data Request.
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DDENn : out std_logic; -- WD1773 Double Data Rate Enable.
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SIDE1 : out std_logic; -- Side 1 of disk select.
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MOTOR : out std_logic; -- Motor on signal.
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DRVSAn : out std_logic; -- Drive A select.
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DRVSBn : out std_logic; -- Drive B select.
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DRVSCn : out std_logic; -- Drive C select.
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DRVSDn : out std_logic; -- Drive D select.
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-- Clocks.
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CLK_16M : in std_logic; -- 16MHz primary oscillator.
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CLK_FDC : out std_logic; -- 8MHz clock to drive WD1773.
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CLK_BUS0 : in std_logic -- Host clock.
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);
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end entity;
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architecture rtl of cpld128 is
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-- CPU Interface internal signals.
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signal Z80_M1ni : std_logic;
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signal Z80_RDni : std_logic;
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signal Z80_WRni : std_logic;
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signal Z80_IORQni : std_logic;
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signal Z80_MREQni : std_logic;
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signal Z80_INTi : std_logic;
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signal Z80_EXWAITni : std_logic;
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-- Internal CPU state control.
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signal MEM_ADDR : std_logic_vector(15 downto 0) := (others => '0');
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-- Select signals.
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signal MEM_EXXX_SELni : std_logic;
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signal MEM_FXXX_SELni : std_logic;
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signal FDC_SELni : std_logic;
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signal DRIVE_WR_SELni : std_logic;
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signal DDEN_WR_SELni : std_logic;
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signal SIDE_WR_SELni : std_logic;
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signal INTEN_SELni : std_logic;
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signal EXXX_RD_SELni : std_logic;
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signal EXXX_WR_SELni : std_logic;
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signal FXXX_RD_SELni : std_logic;
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signal FXXX_WR_SELni : std_logic;
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signal RAMEN_RD_SELni : std_logic;
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signal RAMEN_WR_SELni : std_logic;
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signal MODE_RD_SELni : std_logic;
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signal ROMINHSET_WR_SELni : std_logic;
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signal ROMINHCLR_WR_SELni : std_logic;
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signal ROMDISSET_WR_SELni : std_logic;
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signal ROMDISCLR_WR_SELni : std_logic;
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signal ROM_SELni : std_logic;
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signal RAM_SELni : std_logic;
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-- Registers.
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signal REG_DRIVEA : std_logic;
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signal REG_DRIVEB : std_logic;
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signal REG_DRIVEC : std_logic;
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signal REG_DRIVED : std_logic;
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signal REG_MOTOR : std_logic;
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signal REG_SIDE : std_logic;
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signal REG_DDEN : std_logic;
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signal REG_INT : std_logic;
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signal REG_EXXX_PAGE : std_logic_vector(6 downto 0);
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signal REG_FXXX_PAGE : std_logic_vector(6 downto 0);
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signal REG_ROMDIS : std_logic;
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signal REG_ROMINH : std_logic;
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signal REG_RAMEN : std_logic;
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-- Selected mode of the interface, ie. which machine it will be plugged into.
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signal IFMODE : integer range 0 to 7 := 0;
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-- Clocks.
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signal CLK_8Mi : std_logic := '0';
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-- Functions.
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function to_std_logic(L: boolean) return std_logic is
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begin
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if L then
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return('1');
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else
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return('0');
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end if;
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end function to_std_logic;
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begin
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-- Create FDC Clock based on primary clock.
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FDCCLK: process( CLK_16M )
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begin
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if(rising_edge(CLK_16M)) then
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CLK_8Mi <= not CLK_8Mi;
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end if;
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end process;
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-- Process to register configuration mode on reset.
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SETMODE: process( Z80_RESETn, MODE )
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begin
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if(Z80_RESETn = '0') then
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-- Configuration jumpers specify the machine the SFD700 card will be used with.
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IFMODE <= to_integer(unsigned(MODE));
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end if;
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end process;
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-- Set Floppy Disk Side.
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-- A write to 0xDD bit D0 = low sets Floppy Disk side 1, high sets side 0.
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SETSIDE: process( Z80_RESETn, CLK_16M, SIDE_WR_SELni )
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variable SIDE_SEL_LASTni : std_logic;
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begin
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if(Z80_RESETn = '0') then
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REG_SIDE <= '0';
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SIDE_SEL_LASTni := '0';
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elsif(rising_edge(CLK_16M)) then
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if(SIDE_WR_SELni = '0' and SIDE_SEL_LASTni = '1') then
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REG_SIDE <= not Z80_DATA(0);
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end if;
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SIDE_SEL_LASTni := SIDE_WR_SELni;
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end if;
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end process;
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-- Set Double Data Rate Enable.
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-- A write to 0xDE bit D0 = low enables double data rate, high enables single data rate.
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SETDDEN: process( Z80_RESETn, CLK_16M, DDEN_WR_SELni )
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variable DDEN_SEL_LASTni : std_logic;
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begin
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if(Z80_RESETn = '0') then
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REG_DDEN <= '1';
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DDEN_SEL_LASTni := '0';
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elsif(rising_edge(CLK_16M)) then
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if(DDEN_WR_SELni = '0' and DDEN_SEL_LASTni = '1') then
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REG_DDEN <= not Z80_DATA(0);
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end if;
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DDEN_SEL_LASTni := DDEN_WR_SELni;
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end if;
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end process;
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-- Set Drive Number and Motor
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-- A write to 0xDC, bits D2:0 sets the active drive. Bit 2 high enables the active drive, low disables all drives.
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-- Bit D7 enables the motor.
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SETDRIVE: process( Z80_RESETn, CLK_16M, DRIVE_WR_SELni )
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variable DRIVE_SEL_LASTni: std_logic;
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begin
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if(Z80_RESETn = '0') then
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REG_DRIVEA <= '0';
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REG_DRIVEB <= '0';
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REG_DRIVEC <= '0';
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REG_DRIVED <= '0';
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REG_MOTOR <= '0';
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DRIVE_SEL_LASTni := '0';
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elsif(rising_edge(CLK_16M)) then
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if(DRIVE_WR_SELni = '0' and DRIVE_SEL_LASTni = '1') then
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REG_DRIVEA <= '0';
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REG_DRIVEB <= '0';
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REG_DRIVEC <= '0';
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REG_DRIVED <= '0';
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REG_MOTOR <= Z80_DATA(7);
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case(to_integer(unsigned(Z80_DATA(2 downto 0)))) is
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when 0 =>
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when 4 =>
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REG_DRIVEA <= '1';
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when 5 =>
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REG_DRIVEB <= '1';
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when 6 =>
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REG_DRIVEC <= '1';
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when 7 =>
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REG_DRIVED <= '1';
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when others =>
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end case;
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end if;
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DRIVE_SEL_LASTni := DRIVE_WR_SELni;
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end if;
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end process;
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-- Set Interrupt Enable
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-- A write to 0xDF enables WD1773 interrupts, a read from 0xDF disables WD1773 interrupts.
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SETINT: process( Z80_RESETn, CLK_16M, INTEN_SELni )
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variable INTEN_SEL_LASTni: std_logic;
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begin
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if(Z80_RESETn = '0') then
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REG_INT <= '0';
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INTEN_SEL_LASTni := '0';
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elsif(rising_edge(CLK_16M)) then
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if(INTEN_SELni = '0' and INTEN_SEL_LASTni = '1') then
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REG_INT <= Z80_RDn;
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end if;
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INTEN_SEL_LASTni := INTEN_SELni;
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end if;
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end process;
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-- Set FlashROM/RAM EXXX (E300:EFFF) page address. Each bank is 4K but due to the memory mapped I/O, only
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-- E300:EFFF is useable in RFS.
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-- A write t0 0x60 copies D6:0 into the EXXX page address register which selects a required 4K page in region E300:EFFF
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SETEXXXPAGE: process( Z80_RESETn, CLK_16M, IFMODE, EXXX_WR_SELni )
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variable EXXX_SEL_LASTni : std_logic;
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begin
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if(Z80_RESETn = '0') then
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-- Customised UROM containing RFS start bank.
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REG_EXXX_PAGE <= "0000010";
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EXXX_SEL_LASTni := '0';
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elsif(rising_edge(CLK_16M)) then
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if(EXXX_WR_SELni = '0' and EXXX_SEL_LASTni = '1') then
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REG_EXXX_PAGE <= Z80_DATA(6 downto 0);
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end if;
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EXXX_SEL_LASTni := EXXX_WR_SELni;
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end if;
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end process;
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-- Set FlashROM/RAM FXXX (F000:FFFF) page address.
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-- A write to 0x61 copies D6:0 into the FXXX page address register which selects a 4K page
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-- window of ROM/RAM accessible in the FXXX window.
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SETFXXXPAGE: process( Z80_RESETn, CLK_16M, IFMODE, FXXX_WR_SELni )
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variable FXXX_SEL_LASTni : std_logic;
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begin
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if(Z80_RESETn = '0') then
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-- Initial page is set to 0, which is the MZ-80A AFI ROM. The original ROM is 2K so potential to add additional code in the upper block.
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REG_FXXX_PAGE <= (others => '0');
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-- MZ-700, starting at the second 4k page, set banking registers to 4K block which stores the MZ-700 AFI ROM.
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if(IFMODE = MODE_MZ700) then
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REG_FXXX_PAGE(1 downto 0) <= "01";
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end if;
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elsif(rising_edge(CLK_16M)) then
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-- Set 4k F000:FFFF page address.
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if(FXXX_WR_SELni = '0' and FXXX_SEL_LASTni = '1') then
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REG_FXXX_PAGE <= Z80_DATA(6 downto 0);
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end if;
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-- Edge detection.
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FXXX_SEL_LASTni := FXXX_WR_SELni;
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end if;
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end process;
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-- Enable FlashROM or RAM.
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-- A write to 0x62 with D0 = low enables FlashROM, D0 = high enables RAM.
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SETRAMEN: process( Z80_RESETn, CLK_16M, RAMEN_WR_SELni )
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variable RAMEN_SEL_LASTni: std_logic;
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begin
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if(Z80_RESETn = '0') then
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REG_RAMEN <= '0';
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elsif(rising_edge(CLK_16M)) then
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if(RAMEN_WR_SELni = '0' and RAMEN_SEL_LASTni = '1') then
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REG_RAMEN <= Z80_DATA(0);
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end if;
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RAMEN_SEL_LASTni := RAMEN_WR_SELni;
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end if;
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end process;
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-- MZ-700/MZ-1500 paged memory logic. Detect the memory paging I/O operations and enable/disable access to the onboard FlashROM/RAM.
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--
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-- MZ-700 Memory Management Ports
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-- |0000:0FFF|1000:CFFF|D000:FFFF
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-- ------------------------------
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-- OUT 0xE0 = |DRAM | |
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-- OUT 0xE1 = | | |DRAM
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-- OUT 0xE2 = |MONITOR | |
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-- OUT 0xE3 = | | |Memory Mapped I/O
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-- OUT 0xE4 = |MONITOR |DRAM |Memory Mapped I/O
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-- OUT 0xE5 = | | |Inhibit
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-- OUT 0xE6 = | | |<return>
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--
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-- A write to 0xE1 enables RAM in the region 0xD000:FFFF so the onboard FlashROM/RAM should be disabled. A write to 0xE3/0xE4 re-enables
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-- FlashROM/RAM. A write to 0xE5 inhibits all access to region 0xD000:FFFF so the onboard FlashROM/RAM is disabled, write to 0xE6 re-enables it.
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SETHIMEM: process( Z80_RESETn, CLK_16M, ROMINHSET_WR_SELni, ROMINHCLR_WR_SELni, ROMDISSET_WR_SELni, ROMDISCLR_WR_SELni )
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variable ROMINHSET_LAST : std_logic;
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variable ROMINHCLR_LAST : std_logic;
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variable ROMDISSET_LAST : std_logic;
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variable ROMDISCLR_LAST : std_logic;
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begin
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if(Z80_RESETn = '0') then
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REG_ROMINH <= '0';
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REG_ROMDIS <= '0';
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ROMINHSET_LAST := '0';
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ROMINHCLR_LAST := '0';
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ROMDISSET_LAST := '0';
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ROMDISCLR_LAST := '0';
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elsif(rising_edge(CLK_16M)) then
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if(ROMINHSET_WR_SELni = '0' and ROMINHSET_LAST = '1') then
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REG_ROMINH <= '1';
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end if;
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if(ROMINHCLR_WR_SELni = '0' and ROMINHCLR_LAST = '1') then
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REG_ROMINH <= '0';
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end if;
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if(ROMDISSET_WR_SELni = '0' and ROMDISSET_LAST = '1') then
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REG_ROMDIS <= '1';
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end if;
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if(ROMDISCLR_WR_SELni = '0' and ROMDISCLR_LAST = '1') then
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REG_ROMDIS <= '0';
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end if;
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ROMINHSET_LAST := ROMINHSET_WR_SELni;
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ROMINHCLR_LAST := ROMINHCLR_WR_SELni;
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ROMDISSET_LAST := ROMDISSET_WR_SELni;
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ROMDISCLR_LAST := ROMDISCLR_WR_SELni;
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end if;
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end process;
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-- Memory address select.
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MEM_EXXX_SELni <= '0' when Z80_MREQn = '0' and unsigned(Z80_ADDR(15 downto 8)) >= X"E3" and unsigned(Z80_ADDR(15 downto 8)) < X"F0"
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else '1';
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MEM_FXXX_SELni <= '0' when Z80_MREQn = '0' and unsigned(Z80_ADDR(15 downto 8)) >= X"F0" and unsigned(Z80_ADDR(15 downto 8)) <= X"FF"
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else '1';
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ROM_SELni <= '0' when (IFMODE = MODE_MZ700 or IFMODE = MODE_MZ1500) and REG_ROMINH = '0' and REG_ROMDIS = '0' and REG_RAMEN = '0' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
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else
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'0' when (IFMODE = MODE_MZ1200 or IFMODE = MODE_MZ80A) and REG_RAMEN = '0' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
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else '1';
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RAM_SELni <= '0' when (IFMODE = MODE_MZ700 or IFMODE = MODE_MZ1500) and REG_ROMINH = '0' and REG_ROMDIS = '0' and REG_RAMEN = '1' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
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else
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'0' when (IFMODE = MODE_MZ1200 or IFMODE = MODE_MZ80A) and REG_RAMEN = '1' and (MEM_EXXX_SELni = '0' or MEM_FXXX_SELni = '0')
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else '1';
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-- I/O Port select.
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FDC_SELni <= '0' when Z80_IORQn = '0' and (Z80_WRn = '0' or Z80_RDn = '0') and unsigned(Z80_ADDR(7 downto 0)) >= X"D8" and unsigned(Z80_ADDR(7 downto 0)) < X"DC"
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else '1';
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DRIVE_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"DC"
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else '1';
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DDEN_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"DE"
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else '1';
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SIDE_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"DD"
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else '1';
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INTEN_SELni <= '0' when Z80_IORQn = '0' and (Z80_WRn = '0' or Z80_RDn = '0') and unsigned(Z80_ADDR(7 downto 0)) = X"DF"
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else '1';
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EXXX_RD_SELni <= '0' when Z80_IORQn = '0' and Z80_RDn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"60"
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else '1';
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EXXX_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"60"
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else '1';
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FXXX_RD_SELni <= '0' when Z80_IORQn = '0' and Z80_RDn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"61"
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else '1';
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FXXX_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"61"
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else '1';
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RAMEN_RD_SELni <= '0' when Z80_IORQn = '0' and Z80_RDn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"62"
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else '1';
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RAMEN_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"62"
|
|
else '1';
|
|
MODE_RD_SELni <= '0' when Z80_IORQn = '0' and Z80_RDn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"63"
|
|
else '1';
|
|
ROMINHSET_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"E5"
|
|
else '1';
|
|
ROMINHCLR_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"E6"
|
|
else '1';
|
|
ROMDISSET_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and unsigned(Z80_ADDR(7 downto 0)) = X"E1"
|
|
else '1';
|
|
ROMDISCLR_WR_SELni <= '0' when Z80_IORQn = '0' and Z80_WRn = '0' and (unsigned(Z80_ADDR(7 downto 0)) = X"E3" or unsigned(Z80_ADDR(7 downto 0)) = X"E4")
|
|
else '1';
|
|
|
|
-- WD1773 master clock.
|
|
CLK_FDC <= CLK_8Mi;
|
|
|
|
-- Data bus control.
|
|
Z80_DATA <= not ID when FDC_SELni = '0' and Z80_WRn = '1' -- WD1773
|
|
else
|
|
'0' & REG_EXXX_PAGE when EXXX_RD_SELni = '0' -- EXXX Register contents.
|
|
else
|
|
'0' & REG_FXXX_PAGE when FXXX_RD_SELni = '0' -- FXXX Register contents.
|
|
else
|
|
"0000000" & REG_RAMEN when RAMEN_RD_SELni = '0' -- ROM/RAM Enable register contents.
|
|
else
|
|
"00000" & MODE when MODE_RD_SELni = '0' -- Configured mode.
|
|
else
|
|
(others => 'Z');
|
|
-- ID is the inverted data bus, the WD1773 uses inverted data. ID doubles up as the FlashROM/RAM upper address bits when not being used for the WD1773.
|
|
ID <= not Z80_DATA when Z80_WRn = '0' and FDC_SELni = '0'
|
|
else
|
|
REG_EXXX_PAGE & Z80_ADDR(11) when MEM_EXXX_SELni = '0'
|
|
else
|
|
REG_FXXX_PAGE & Z80_ADDR(11) when MEM_FXXX_SELni = '0'
|
|
else
|
|
(others => 'Z');
|
|
|
|
-- Host interrupts and wait processing.
|
|
Z80_INT <= INTRQ when REG_INT = '1'
|
|
else '0';
|
|
Z80_EXWAITni <= '1';
|
|
Z80_EXWAITn <= Z80_EXWAITni;
|
|
|
|
-- FlashROM/RAM Address A10 - this is used on the MZ-80A/MZ-1200 as a means of speeding up data retrieval from the WD1773 where DRQ is used as the address bit and dupliate ROM code appears in each 1K segment except the upper bytes, 0x3FE.
|
|
ROM_A10 <= '1' when (IFMODE = MODE_MZ1200 or IFMODE = MODE_MZ80A) and DRQ = '1'
|
|
else Z80_ADDR(10);
|
|
RAM_A10 <= Z80_ADDR(10);
|
|
|
|
-- FlashROM/RAM Chip Select.
|
|
ROM_CSn <= ROM_SELni;
|
|
RAM_CSn <= RAM_SELni;
|
|
|
|
-- Floppy Disk Interface Signals.
|
|
FDCn <= FDC_SELni;
|
|
DRVSAn <= not REG_DRIVEA;
|
|
DRVSBn <= not REG_DRIVEB;
|
|
DRVSCn <= not REG_DRIVEC;
|
|
DRVSDn <= not REG_DRIVED;
|
|
MOTOR <= REG_MOTOR;
|
|
SIDE1 <= not REG_SIDE;
|
|
DDENn <= not REG_DDEN;
|
|
|
|
-- Reserved pins.
|
|
RSV <= '0';
|
|
|
|
end architecture;
|