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birdybro 26247dd359 Update edge detection method from VHDL 87 to VHDL 93 (#131)
Technically, `Clk’event and clk = ‘1’` can result in non-`0` triggers (e.g. `1`, `U`, `H`, `X`, `Z`, `W`, etc...), whereas `rising_edge(clk)` does not.
2022-07-07 16:00:25 +08:00
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2020-05-11 22:12:26 +08:00