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26247dd359
Technically, `Clk’event and clk = ‘1’` can result in non-`0` triggers (e.g. `1`, `U`, `H`, `X`, `Z`, `W`, etc...), whereas `rising_edge(clk)` does not.
160 lines
6.6 KiB
VHDL
160 lines
6.6 KiB
VHDL
--
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-- AttackTable.vhd
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-- Envelope attack shaping table for VM2413
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--
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-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
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-- All rights reserved.
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--
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-- Redistribution and use of this source code or any derivative works, are
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-- permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- 3. Redistributions may not be sold, nor may they be used in a commercial
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-- product or activity without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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--
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-- modified by t.hara
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_signed.all;
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entity attack_table_mul is
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port(
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i0 : in std_logic_vector( 7 downto 0 ); -- 符号無し 8bit (整数部 0bit, 小数部 8bit)
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i1 : in std_logic_vector( 7 downto 0 ); -- 符号付き 8bit (整数部 8bit)
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o : out std_logic_vector( 13 downto 0 ) -- 符号付き14bit (整数部 8bit, 小数部 6bit)
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);
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end attack_table_mul;
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architecture rtl of attack_table_mul is
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signal w_mul : std_logic_vector( 16 downto 0 );
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begin
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w_mul <= ('0' & i0) * i1;
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o <= w_mul( 15 downto 2 ); -- bit16 は bit15 と同じなのでカット。bit1～0 (小数部) は切り捨て。
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end rtl;
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith;
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entity AttackTable is
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port(
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clk : in std_logic;
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clkena : in std_logic;
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addr : in std_logic_vector( 21 downto 0 ); -- 小数部 15bit
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data : out std_logic_vector( 12 downto 0 ) -- 小数部 6bit
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);
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end AttackTable;
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architecture rtl of attacktable is
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component attack_table_mul
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port(
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i0 : in std_logic_vector( 7 downto 0 ); -- 符号無し 8bit (整数部 0bit, 小数部 8bit)
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i1 : in std_logic_vector( 7 downto 0 ); -- 符号付き 8bit (整数部 8bit)
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o : out std_logic_vector( 13 downto 0 ) -- 符号付き 8bit (整数部 8bit, 小数部 6bit)
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);
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end component;
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type ar_adjust_array is array ( 0 to 127 ) of std_logic_vector( 6 downto 0 );
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constant ar_adjust : ar_adjust_array :=(
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"0000000", "0000000", "0000000", "0000000", "0000000", "0000001", "0000001", "0000001",
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"0000001", "0000001", "0000010", "0000010", "0000010", "0000010", "0000011", "0000011",
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"0000011", "0000011", "0000100", "0000100", "0000100", "0000100", "0000100", "0000101",
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"0000101", "0000101", "0000110", "0000110", "0000110", "0000110", "0000111", "0000111",
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"0000111", "0000111", "0001000", "0001000", "0001000", "0001001", "0001001", "0001001",
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"0001001", "0001010", "0001010", "0001010", "0001011", "0001011", "0001011", "0001100",
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"0001100", "0001100", "0001101", "0001101", "0001101", "0001110", "0001110", "0001110",
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"0001111", "0001111", "0001111", "0010000", "0010000", "0010001", "0010001", "0010001",
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"0010010", "0010010", "0010011", "0010011", "0010100", "0010100", "0010101", "0010101",
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"0010101", "0010110", "0010110", "0010111", "0010111", "0011000", "0011000", "0011001",
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"0011010", "0011010", "0011011", "0011011", "0011100", "0011101", "0011101", "0011110",
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"0011110", "0011111", "0100000", "0100001", "0100001", "0100010", "0100011", "0100100",
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"0100100", "0100101", "0100110", "0100111", "0101000", "0101001", "0101010", "0101011",
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"0101100", "0101101", "0101111", "0110000", "0110001", "0110011", "0110100", "0110110",
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"0111000", "0111001", "0111011", "0111101", "1000000", "1000010", "1000101", "1001000",
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"1001011", "1010000", "1010100", "1011010", "1100010", "1101100", "1110101", "1111111"
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);
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signal ff_w : std_logic_vector( 7 downto 0 );
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signal ff_d1 : std_logic_vector( 6 downto 0 );
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signal ff_d2 : std_logic_vector( 6 downto 0 );
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signal w_addr1 : std_logic_vector( 6 downto 0 );
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signal w_addr2 : std_logic_vector( 6 downto 0 );
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signal w_sub : std_logic_vector( 7 downto 0 ); -- 符号付き
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signal w_mul : std_logic_vector( 13 downto 0 ); -- 符号付き
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signal w_inter : std_logic_vector( 13 downto 0 );
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begin
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w_addr1 <= addr( 21 downto 15 );
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w_addr2 <= (others => '1') when( addr( 21 downto 15 ) = "1111111" )else
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w_addr1 + 1;
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process( clk )
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begin
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if rising_edge(clk) then
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if( clkena = '1' )then
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ff_d1 <= ar_adjust( conv_integer( w_addr1 ) );
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ff_d2 <= ar_adjust( conv_integer( w_addr2 ) );
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end if;
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end if;
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end process;
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process( clk )
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begin
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if rising_edge(clk) then
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if( clkena = '1' )then
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ff_w <= addr( 14 downto 7 ); -- データ自体のビット数が 7bit なので 8bit で十分
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end if;
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end if;
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end process;
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-- 補間 (※符号をまたがる場所では 0 になるから ff_sign は気にしない）
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-- o = i1 * (1 - k) + i2 * w = i1 - w * i1 + w * i2 = i1 + w * (i2 - i1)
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w_sub <= ('0' & ff_d2) - ('0' & ff_d1);
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u_attack_table_mul: attack_table_mul
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port map (
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i0 => ff_w,
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i1 => w_sub,
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o => w_mul
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);
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w_inter <= ('0' & ff_d1 & "000000") + w_mul;
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process( clk )
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begin
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if rising_edge(clk) then
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if( clkena = '1' )then
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data <=w_inter( 12 downto 0 ); -- MSB は必ず 0
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end if;
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end if;
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end process;
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end rtl;
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