2 Commits

Author	SHA1	Message	Date
birdybro	26247dd359	Update edge detection method from VHDL 87 to VHDL 93 (#131) ... Technically, `Clk’event and clk = ‘1’` can result in non-`0` triggers (e.g. `1`, `U`, `H`, `X`, `Z`, `W`, etc...), whereas `rising_edge(clk)` does not.	2022-07-07 16:00:25 +08:00
sorgelig	1fd09c9979	Update sys. Re-Organize the sources.	2020-05-11 22:12:26 +08:00