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26247dd359
Technically, `Clk’event and clk = ‘1’` can result in non-`0` triggers (e.g. `1`, `U`, `H`, `X`, `Z`, `W`, etc...), whereas `rising_edge(clk)` does not.
161 lines
6.4 KiB
VHDL
161 lines
6.4 KiB
VHDL
--
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-- Operator.vhd
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--
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-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
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-- All rights reserved.
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--
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-- Redistribution and use of this source code or any derivative works, are
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-- permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- 3. Redistributions may not be sold, nor may they be used in a commercial
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-- product or activity without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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--
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-- modified by t.hara
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.vm2413.all;
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entity Operator is
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port (
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clk : in std_logic;
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reset : in std_logic;
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clkena : in std_logic;
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slot : in SLOT_TYPE;
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stage : in STAGE_TYPE;
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rhythm : in std_logic;
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WF : in WF_TYPE;
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FB : in FB_TYPE;
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noise : in std_logic;
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pgout : in std_logic_vector( 17 downto 0 ); -- 整数部 9bit, 小数部 9bit
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egout : in std_logic_vector( 12 downto 0 );
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faddr : out CH_TYPE;
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fdata : in SIGNED_LI_TYPE;
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opout : out std_logic_vector( 13 downto 0 ) -- 整数部 8bit, 小数部 6bit
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);
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end Operator;
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architecture rtl of Operator is
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component SineTable
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port (
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clk : in std_logic;
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clkena : in std_logic;
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wf : in std_logic;
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addr : in std_logic_vector( 17 downto 0 ); -- 整数部 9bit, 小数部 9bit
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data : out std_logic_vector( 13 downto 0 ) -- 整数部 8bit, 小数部 6bit
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);
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end component;
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signal addr : std_logic_vector( 17 downto 0 );
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signal data : std_logic_vector( 13 downto 0 );
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signal w_is_carrier : std_logic;
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signal w_modula_m : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
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signal w_modula_c : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
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signal w_modula : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
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signal ff_egout : std_logic_vector( 12 downto 0 );
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begin
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-- サイン波（対数表現）--------------------------------------------------
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-- addr 指定した次々サイクルに data が出てくる
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--
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-- stage X 00 X 01 X 10 X 11 X 00
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-- addr X 確定
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-- data X 確定
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-- opout X 確定
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--
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u_sine_table : SineTable
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port map(
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clk => clk,
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clkena => clkena,
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wf => wf,
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addr => addr,
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data => data
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);
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w_is_carrier <= slot(0);
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w_modula_m <= (others => '0') when( fb = "000" )else
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shr( '0' & fdata.value & '0' & "000000000", "111" xor fb );
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w_modula_c <= fdata.value & "00" & "000000000";
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w_modula <= w_modula_c when( w_is_carrier = '1' )else
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w_modula_m;
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process( reset, clk )
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variable opout_buf : std_logic_vector( 13 downto 0 ); -- 整数部 8bit, 小数部 6bit
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begin
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if( reset = '1' )then
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opout <= (others => '0');
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ff_egout <= (others => '0');
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elsif rising_edge(clk) then
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if( clkena = '1' )then
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if( stage = "00" )then
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-- サイン波の参照アドレス（位相）を決定するステージ
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if( rhythm = '1' and ( slot = 14 or slot = 17 ))then -- HH or CYM
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addr <= (not noise) & "01111111" & "000000000";
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elsif( rhythm = '1' and slot = 15 )then -- SD
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addr <= (not pgout(pgout'high)) & "01111111" & "000000000";
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elsif( rhythm = '1' and slot = 16 )then -- TOM
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addr <= pgout;
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else
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if( fdata.sign = '0' )then -- modula は fdata の絶対値をシフトした値だから、ここで符号処理してる
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addr <= pgout + w_modula(pgout'range);
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else
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addr <= pgout - w_modula(pgout'range);
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end if;
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end if;
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elsif( stage = "01" )then
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-- 決定された参照アドレスが u_sine_table へ供給されるステージ
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elsif( stage = "10" )then
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ff_egout <= egout;
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-- フィードバックメモリのアドレスを決めるステージ
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if( slot(0) = '1' )then
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if( conv_integer(slot)/2 = 8 )then
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faddr <= 0;
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else
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faddr <= conv_integer(slot)/2 + 1; -- 次のモジュレータのアドレスなので +1
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end if;
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end if;
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elsif( stage = "11" )then
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-- SineTable からデータが出てくるステージ
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if ( ( '0' & ff_egout ) + ('0'& data(12 downto 0) ) ) < "10000000000000" then
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opout_buf := data(13) & (ff_egout + data(12 downto 0) );
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else
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opout_buf := data(13) & "1111111111111";
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end if;
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opout <= opout_buf;
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-- 決定されたフィードバックメモリアドレスが FeedBackMemory へ供給されるステージ
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end if;
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end if;
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end if;
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end process;
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end rtl;
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