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26247dd359
Technically, `Clk’event and clk = ‘1’` can result in non-`0` triggers (e.g. `1`, `U`, `H`, `X`, `Z`, `W`, etc...), whereas `rising_edge(clk)` does not.
85 lines
2.5 KiB
VHDL
85 lines
2.5 KiB
VHDL
--
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-- PhaseMemory.vhd
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--
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-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
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-- All rights reserved.
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--
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-- Redistribution and use of this source code or any derivative works, are
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-- permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- 3. Redistributions may not be sold, nor may they be used in a commercial
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-- product or activity without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use WORK.VM2413.ALL;
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entity PhaseMemory is
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port (
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clk : in std_logic;
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reset : in std_logic;
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slot : in SLOT_TYPE;
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memwr : in std_logic;
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memout : out PHASE_TYPE;
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memin : in PHASE_TYPE
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);
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end PhaseMemory;
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architecture RTL of PhaseMemory is
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type PHASE_ARRAY_TYPE is array (0 to 18-1) of PHASE_TYPE;
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signal phase_array : PHASE_ARRAY_TYPE;
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attribute ramstyle : string;
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attribute ramstyle of phase_array : signal is "logic";
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begin
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process (clk, reset)
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variable init_slot : integer range 0 to 18;
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begin
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if reset = '1' then
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init_slot := 0;
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elsif rising_edge(clk) then
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if init_slot /= 18 then
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phase_array(init_slot) <= (others=>'0');
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init_slot := init_slot + 1;
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elsif memwr = '1' then
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phase_array(conv_integer(slot)) <= memin;
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end if;
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memout <= phase_array(conv_integer(slot));
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end if;
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end process;
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end RTL; |