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https://github.com/MiSTer-devel/SMS_MiSTer.git
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26247dd359
Technically, `Clk’event and clk = ‘1’` can result in non-`0` triggers (e.g. `1`, `U`, `H`, `X`, `Z`, `W`, etc...), whereas `rising_edge(clk)` does not.
215 lines
9.2 KiB
VHDL
215 lines
9.2 KiB
VHDL
--
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-- SineTable.vhd
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--
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-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
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-- All rights reserved.
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--
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-- Redistribution and use of this source code or any derivative works, are
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-- permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- 3. Redistributions may not be sold, nor may they be used in a commercial
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-- product or activity without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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--
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-- modified by t.hara
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--
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-- ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_signed.all;
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entity interpolate_mul is
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port (
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i0 : in std_logic_vector( 8 downto 0 ); -- 符号無し 9bit (整数部 0bit, 小数部 9bit)
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i1 : in std_logic_vector( 11 downto 0 ); -- 符号付き12bit (整数部 8bit, 小数部 4bit)
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o : out std_logic_vector( 13 downto 0 ) -- 符号付き 7bit (整数部 8bit, 小数部 6bit)
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);
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end interpolate_mul;
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architecture rtl of interpolate_mul is
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signal w_mul : std_logic_vector( 21 downto 0 ); -- 符号付き22bit (整数部 9bit, 小数部13bit)
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begin
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w_mul <= ('0' & i0) * i1;
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o <= w_mul( 20 downto 7 ); -- MSBカットで 21bit, 小数部下位 7bitカット
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end rtl;
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-- ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all; -- conv_integer()
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entity SineTable is
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port (
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clk : in std_logic;
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clkena : in std_logic;
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wf : in std_logic;
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addr : in std_logic_vector( 17 downto 0 ); -- 整数部 9bit, 小数部 9bit
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data : out std_logic_vector( 13 downto 0 ) -- 整数部 8bit, 小数部 6bit
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);
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end SineTable;
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architecture rtl of sinetable is
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component interpolate_mul
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port (
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i0 : in std_logic_vector( 8 downto 0 ); -- 符号無し 9bit (整数部 0bit, 小数部 9bit)
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i1 : in std_logic_vector( 11 downto 0 ); -- 符号付き 8bit (整数部 8bit)
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o : out std_logic_vector( 13 downto 0 ) -- 符号無し 7bit (整数部 8bit)
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);
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end component;
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type sin_type is array (0 to 127) of std_logic_vector( 10 downto 0 ); -- 整数部 7bit, 小数部 4bit
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constant sin_data : sin_type := (
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"11111111111", "11001010000", "10101010001", "10010111100",
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"10001010011", "10000000001", "01110111110", "01110000101",
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"01101010101", "01100101001", "01100000011", "01011100000",
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"01011000000", "01010100011", "01010001000", "01001101111",
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"01001011000", "01001000010", "01000101101", "01000011010",
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"01000000111", "00111110110", "00111100101", "00111010101",
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"00111000110", "00110110111", "00110101001", "00110011100",
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"00110001111", "00110000011", "00101110111", "00101101011",
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"00101100000", "00101010110", "00101001011", "00101000001",
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"00100111000", "00100101110", "00100100101", "00100011100",
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"00100010100", "00100001011", "00100000011", "00011111011",
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"00011110100", "00011101100", "00011100101", "00011011110",
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"00011010111", "00011010001", "00011001010", "00011000100",
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"00010111110", "00010111000", "00010110010", "00010101100",
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"00010100111", "00010100001", "00010011100", "00010010111",
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"00010010010", "00010001101", "00010001000", "00010000011",
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"00001111111", "00001111010", "00001110110", "00001110010",
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"00001101110", "00001101010", "00001100110", "00001100010",
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"00001011110", "00001011010", "00001010111", "00001010011",
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"00001010000", "00001001101", "00001001001", "00001000110",
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"00001000011", "00001000000", "00000111101", "00000111011",
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"00000111000", "00000110101", "00000110011", "00000110000",
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"00000101110", "00000101011", "00000101001", "00000100111",
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"00000100101", "00000100010", "00000100000", "00000011110",
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"00000011101", "00000011011", "00000011001", "00000010111",
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"00000010110", "00000010100", "00000010011", "00000010001",
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"00000010000", "00000001110", "00000001101", "00000001100",
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"00000001011", "00000001010", "00000001001", "00000001000",
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"00000000111", "00000000110", "00000000101", "00000000100",
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"00000000011", "00000000011", "00000000010", "00000000010",
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"00000000001", "00000000001", "00000000000", "00000000000",
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"00000000000", "00000000000", "00000000000", "00000000000"
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);
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signal ff_data0 : std_logic_vector( 10 downto 0 ); -- 符号ナシ整数部 7bit, 小数部 4bit
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signal ff_data1 : std_logic_vector( 10 downto 0 ); -- 符号ナシ整数部 7bit, 小数部 4bit
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signal w_wf : std_logic_vector( 13 downto 0 );
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signal w_xor : std_logic_vector( 6 downto 0 );
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signal w_addr0 : std_logic_vector( 6 downto 0 );
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signal w_addr1 : std_logic_vector( 6 downto 0 );
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signal w_xaddr : std_logic_vector( 6 downto 0 );
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signal ff_sign : std_logic;
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signal ff_wf : std_logic;
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signal ff_weight : std_logic_vector( 8 downto 0 );
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signal w_sub : std_logic_vector( 11 downto 0 ); -- 符号付き整数部 8bit, 小数部 4bit
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signal w_mul : std_logic_vector( 13 downto 0 ); -- 符号付き整数部 8bit, 小数部 6bit
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signal w_inter : std_logic_vector( 13 downto 0 );
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signal ff_data : std_logic_vector( 13 downto 0 );
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begin
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w_xor <= (others => addr(16));
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w_xaddr <= addr( 15 downto 9 ) xor w_xor;
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w_addr0 <= w_xaddr;
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w_addr1 <= "1111111" xor w_xor when(addr( 15 downto 9 ) = "1111111" )else -- 波形が循環する部分の対処
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(addr( 15 downto 9 ) + 1) xor w_xor;
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-- 波形メモリ
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process( clk )
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begin
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if rising_edge(clk) then
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if( clkena = '1' )then
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ff_data0 <= sin_data( conv_integer( w_addr0 ) );
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ff_data1 <= sin_data( conv_integer( w_addr1 ) );
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end if;
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end if;
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end process;
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-- 修飾情報の遅延（波形メモリの読み出し遅延にあわせる）
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process( clk )
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begin
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if rising_edge(clk) then
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if( clkena = '1' )then
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ff_sign <= addr(17);
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ff_wf <= wf and addr(17);
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ff_weight <= addr( 8 downto 0 );
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end if;
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end if;
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end process;
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-- 補間 (※符号をまたがる場所では 0 になるから ff_sign は気にしない）
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-- o = i0 * (1 - k) + i1 * w = i0 - w * i0 + w * i1 = i0 + w * (i1 - i0)
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w_sub <= ('0' & ff_data1) - ('0' & ff_data0);
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u_interpolate_mul: interpolate_mul
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port map (
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i0 => ff_weight,
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i1 => w_sub,
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o => w_mul
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);
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-- 下位 6bit （小数部）を演算精度維持のために残す
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w_inter <= (ff_data0 & "00") + w_mul; -- "00" は桁あわせ
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w_wf <= (others => ff_wf);
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process( clk )
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begin
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if rising_edge(clk) then
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if( clkena = '1' )then
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-- 補間演算の結果をいったん FF に入れて演算遅延を吸収
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ff_data <= (ff_sign & w_inter(12 downto 0)) or w_wf;
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end if;
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end if;
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end process;
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data <= ff_data;
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--------------------------------------------------------------------------
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-- addr X addr入力 X
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-- w_addr0 X 確定 X
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-- w_addr1 X 確定 X
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-- ff_data0 X 確定 X
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-- ff_data1 X 確定 X
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-- ff_sign X 確定 X
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-- ff_wf X 確定 X
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-- ff_weight X 確定 X
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-- w_sub X 確定 X
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-- w_mul X 確定 X
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-- w_inter X 確定 X
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-- w_wf X 確定 X
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-- ff_data X 確定 X
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-- data X 確定 X
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-- Operator
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-- stage X 01 X 10 X 11 X 00 X
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--
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-- Operator は、stage = 01 のときに投入した入力値に基づく出力を得る場合に
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-- stage = 11 で受け取らなければならない。
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--
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-- アドレス指定されてから、それに対応する値が得られるまで 2cycle の遅延
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--
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end rtl;
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