Commit Graph

50 Commits

Author SHA1 Message Date
Bruno Gouveia
df13f72441 SOUND: sweep updates freq register 2018-11-27 23:42:29 +00:00
Bruno Gouveia
e4e2c36cdb SOUND: disable sq1 after sweep neg->pos direction change 2018-11-27 23:42:22 +00:00
Bruno Gouveia
938d8f6dbe SOUND: sq1 sweep unit rewrite, trigger and length quirks implemented 2018-11-27 23:42:13 +00:00
sorgelig
478f4c65b4 Merge pull request #10 from brNX/master
Sound Fixes , Dummy Serial Port and Video Fix
2018-11-25 01:02:34 +08:00
Bruno Gouveia
a96c294082 VIDEO: moved LY=LYC back to h_count == 1 , fixes Final Fantasy Legend 1 and 2 and improves Mario picross 2018-11-24 01:14:48 +00:00
Bruno Gouveia
c16e3882bb SERIAL: dummy implementation to fix alleway (return not connected 0xFF and triggers interrupt) 2018-11-24 01:14:48 +00:00
Bruno Gouveia
3b0fde5122 SOUND: wav index genetor refactored and moved to WAV block 2018-11-24 01:14:45 +00:00
Bruno Duarte Gouveia
477a9a7f1b SOUND: fix noi_lfsr initialized in noi trigger 2018-11-24 01:11:47 +00:00
Bruno Duarte Gouveia
12fb2e29af SOUND: noise len reg behaviour fixed 2018-11-24 01:11:47 +00:00
Bruno Duarte Gouveia
b966666764 SOUND: fixed wav len behaviour 2018-11-24 01:11:47 +00:00
Bruno Duarte Gouveia
8cdaf63628 SOUND: more len register related changes for sq1 and sq2 (passes 02 dmg sound test) 2018-11-24 01:11:47 +00:00
Bruno Duarte Gouveia
45c13fb472 SOUND: swapped sq1 and sq2 length counter to a decrementing counter
SOUND: sq1 and sq2 length counter can be changed anytime and added real hardware behaviour
2018-11-24 01:11:47 +00:00
Bruno Duarte Gouveia
16239ccc65 SOUND: use index to cycle through wavetable instead of rotating values 2018-11-20 23:45:45 +00:00
Bruno Duarte Gouveia
5b222b7e74 SOUND: added NR50 and NR51 to read block
change sq1_vol and sq2_vol when writing to register even if trigger is not active
2018-11-20 00:00:32 +00:00
sorgelig
5a1cd9068a Release 20181118. 2018-11-18 20:49:57 +08:00
sorgelig
c03c67626b Update sys. Add Q13 project. Support for scaler coeff loading. 2018-11-18 20:49:10 +08:00
sorgelig
3870c01ea3 Merge pull request #9 from brNX/master
T80: resume after halt even if IME is disabled, fixed 3 instructions
2018-11-18 17:17:17 +08:00
Bruno Gouveia
448e8d5d3f T80: fixed ld hl,sp+dd and add sp,dd flags 2018-11-17 02:11:30 +00:00
Bruno Gouveia
7939e38ed9 T80: fixed DAA instruction (different from Z80) 2018-11-16 22:06:33 +00:00
Bruno Gouveia
4d461d4be7 T80: GB cpu can use IRQ without IME set to resume from Halt 2018-11-16 19:26:02 +00:00
sorgelig
2042b23086 Merge pull request #7 from brNX/master
Only set irq_vector to specific address if both IE and IF are enabled
2018-11-14 12:03:50 +08:00
Bruno Duarte Gouveia
8c1dac4685 IRQ: only set irq_vector to specific address if both interrupt enable (IE) and interrupt flag (IF) are enabled 2018-11-14 00:50:00 +00:00
sorgelig
91f1f7afe9 Merge pull request #6 from brNX/master
Multiple I/O Regs fixes, OAM DMA from VRAM , RET cc opcode timing
2018-11-13 16:11:27 +08:00
Bruno Duarte Gouveia
6c94025f70 GB Regs: set a few hwio regs to default value 2018-11-12 21:55:35 +00:00
Bruno Duarte Gouveia
963c4d44cc GB Regs: fixed various registers to return the same unused bits values as the original hardware 2018-11-12 20:47:26 +00:00
Bruno Duarte Gouveia
6d86eae661 SOUND: moved read to combinational process block, fixes ld r,(HL) from sound registers 2018-11-12 20:47:18 +00:00
Bruno Duarte Gouveia
2fa7636ddf reset stat register 2018-11-12 20:46:49 +00:00
Bruno Duarte Gouveia
c742cb8fc8 OAM DMA: implemented missing dma transfer from VRAM 2018-11-12 20:46:36 +00:00
Bruno Duarte Gouveia
91cbfff6a3 T80: ret cc mcycles 20/8 for GB 2018-11-12 20:46:27 +00:00
sorgelig
8471a9ad01 Merge pull request #5 from brNX/opcodetimings
Video: STAT FF41$ mode should be 0 when lcd off
2018-11-09 05:53:20 +08:00
Bruno Duarte Gouveia
1476d96d51 Video: STAT FF41$ mode should be 0 when lcd off 2018-11-08 20:47:02 +00:00
sorgelig
6d57b1bb1d Merge pull request #4 from brNX/opcodetimings
Opcode timings, ADD SP,dd and LD HL,SP+dd, F Register
2018-11-06 23:14:39 +08:00
Bruno Duarte Gouveia
61b8f537d8 re-did ADD SP,+/-dd, still need to check if F flag is correct 2018-11-05 23:22:32 +00:00
Bruno Duarte Gouveia
03cfb9364a ld hl,sp+dd instruction redone(probably not the "right" way)
Moved things arround for LDHLSP added Flags, should be ok
2018-11-05 18:30:32 +00:00
Bruno Duarte Gouveia
d515cb8127 trigger interrupt earlier, on negedge 2018-11-05 13:52:03 +00:00
Bruno Duarte Gouveia
a108c3c11c fixed F flag so that 4 lowest bits always return 0 2018-11-03 16:13:43 +00:00
Bruno Duarte Gouveia
6717756852 fixed some opcode timings and reset div when reseting gameboy 2018-11-03 00:44:22 +00:00
sorgelig
d1e26152af Merge pull request #3 from brNX/mappers
memory bank controllers simplified to a single always block
2018-10-31 20:38:42 +08:00
Bruno Duarte Gouveia
095de6e493 refactored memory bank controllers to a single always block
re-enabled MBC2 and added ram upper 4bit masking
2018-10-30 18:46:46 +00:00
sorgelig
3bce0a2288 Merge pull request #2 from brNX/mappers
Memory bank controllers MBC3(not complete) and MBC5 implemented
2018-10-30 02:47:34 +08:00
Bruno Duarte Gouveia
76c652b7f1 moved mappers selection arround and reenabled ~status[6] weirdness on mbc1, disabled mbc2 for now 2018-10-29 16:31:44 +00:00
Bruno Duarte Gouveia
a703781adf initial versions of mbc3 and mbc5 mappers 2018-10-29 16:31:34 +00:00
sorgelig
64f0af8b6e Merge pull request #1 from brNX/lcdoff
changed DIV and lcd off register behaviour to reset internal counters, trigger ly==lyc irq earlier
2018-10-26 03:34:32 +08:00
unknown
b0ad754860 disable h_cnt and v_cnt when lcd_off, reset counters
trigger ly=lyc earlier, fixes duck tales background
2018-10-24 20:48:30 +01:00
unknown
b67ee7fdc9 reset internal counter when reseting div 2018-10-24 01:49:02 +01:00
sorgelig
2e9a60ccf1 Release 20180306. 2018-03-06 03:52:26 +08:00
sorgelig
1b390b4d09 Import updates from MiST. 2018-03-06 03:51:17 +08:00
sorgelig
f119c1aff2 Update API. 2018-03-06 02:45:59 +08:00
sorgelig
3730ea64bc Release 20171203. 2017-12-03 07:32:51 +08:00
sorgelig
d92202c897 Initial commit. 2017-12-03 07:32:02 +08:00