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ld hl,sp+dd instruction redone(probably not the "right" way)

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Moved things arround for LDHLSP added Flags, should be ok
This commit is contained in:
Bruno Duarte Gouveia
2018-11-05 13:46:38 +00:00
parent d515cb8127
commit 03cfb9364a
3 changed files with 40 additions and 20 deletions
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31
t80/T80.vhd
View File

@@ -150,6 +150,7 @@ architecture rtl of T80 is
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal TmpAddr2 : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
@@ -223,6 +224,7 @@ architecture rtl of T80 is
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal LDHLSP : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
@@ -292,6 +294,7 @@ begin
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
LDHLSP => LDHLSP,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
@@ -397,6 +400,14 @@ begin
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if LDHLSP = '1' and TState = 1 then
TmpAddr <= std_logic_vector(SP xor unsigned(Save_Mux) xor unsigned(TmpAddr2));
F(Flag_Z) <= '0';
F(Flag_N) <= '0';
F(Flag_H) <= TmpAddr(4);
F(Flag_C) <= TmpAddr(8);
end if;
if Mode = 3 then
IStatus <= "10";
@@ -592,6 +603,7 @@ begin
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
@@ -777,6 +789,8 @@ begin
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- LDHLSP
"010" when LDHLSP = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
@@ -790,7 +804,7 @@ begin
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
ExchangeDH, IncDec_16, MCycle, TState, Wait_n,LDHLSP)
begin
RegWEH <= '0';
RegWEL <= '0';
@@ -808,6 +822,11 @@ begin
RegWEH <= '1';
RegWEL <= '1';
end if;
if LDHLSP = '1' and MCycle = "010" and TState = 4 then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
@@ -820,11 +839,17 @@ begin
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if LDHLSP = '1' and MCycle = "010" and TState = 4 then
TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux)));
RegDIH <= TmpAddr2(15 downto 8);
RegDIL <= TmpAddr2(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);

28
t80/T80_MCode.vhd
View File

@@ -121,9 +121,10 @@ entity T80_MCode is
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
LDHLSP : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
@@ -223,6 +224,7 @@ begin
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
LDHLSP <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
@@ -1297,24 +1299,16 @@ begin
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! //shoud be mcycles=011, n is signed
MCycles <= "101";
-- LD HL,SP+n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Inc_PC <= '1';
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
LDHLSP <= '1';
Inc_PC <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
LDHLSP <= '1';
when others => null;
end case;
end case;

1
t80/T80_Pack.vhd
View File

@@ -173,6 +173,7 @@ package T80_Pack is
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
LDHLSP : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;