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T80: fixed ld hl,sp+dd and add sp,dd flags

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This commit is contained in:
Bruno Gouveia
2018-11-17 02:11:30 +00:00
parent 7939e38ed9
commit 448e8d5d3f
1 changed files with 16 additions and 13 deletions
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29
t80/T80.vhd
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@@ -151,7 +151,6 @@ architecture rtl of T80 is
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal TmpAddr2 : std_logic_vector(15 downto 0); -- Temporary address register
signal TmpAddr3 : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
@@ -359,6 +358,8 @@ begin
ALU_Q;
process (RESET_n, CLK_n)
variable temp_c : unsigned(8 downto 0);
variable temp_h : unsigned(4 downto 0);
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
@@ -404,20 +405,22 @@ begin
MCycles <= MCycles_d;
if LDHLSP = '1' and TState = 1 then
TmpAddr <= std_logic_vector(SP xor unsigned(Save_Mux) xor unsigned(TmpAddr2));
F(Flag_Z) <= '0';
F(Flag_N) <= '0';
F(Flag_H) <= TmpAddr(4);
F(Flag_C) <= TmpAddr(8);
end if;
if ADDSPdd = '1' and TState = 4 then
TmpAddr3 <= std_logic_vector(SP xor unsigned(Save_Mux) xor unsigned(TmpAddr));
if LDHLSP = '1' and MCycle = "011" and TState = 1 then
temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
F(Flag_Z) <= '0';
F(Flag_N) <= '0';
F(Flag_H) <= TmpAddr3(4);
F(Flag_C) <= TmpAddr3(8);
F(Flag_H) <= temp_h(4);
F(Flag_C) <= temp_c(8);
end if;
if ADDSPdd = '1' and TState = 1 then
temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
F(Flag_Z) <= '0';
F(Flag_N) <= '0';
F(Flag_H) <= temp_h(4);
F(Flag_C) <= temp_c(8);
end if;
if Mode = 3 then