mister-devel/Archie_MiSTer
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sorgelig c5c7069d55 Initial port.
2017-10-16 02:07:56 +08:00
amber
Initial port.
2017-10-16 02:07:56 +08:00
sys
Initial port.
2017-10-16 02:07:56 +08:00
.gitignore
Initial port.
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Archie-lite.qsf
Initial port.
2017-10-16 02:07:56 +08:00
Archie-lite.srf
Initial port.
2017-10-16 02:07:56 +08:00
Archie.qpf
Initial port.
2017-10-16 02:07:56 +08:00
Archie.qsf
Initial port.
2017-10-16 02:07:56 +08:00
Archie.srf
Initial port.
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Archie.sv
Initial port.
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archimedes_top.v
Initial port.
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audio.v
Initial port.
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clean.bat
Initial port.
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cmos.mif
Initial port.
2017-10-16 02:07:56 +08:00
fdc1772.v
Initial port.
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floppy.v
Initial port.
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i2cSlave_define.v
Initial port.
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i2cSlave.v
Initial port.
2017-10-16 02:07:56 +08:00
i2cSlaveTop.v
Initial port.
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ioc_irq.v
Initial port.
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ioc.v
Initial port.
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jtag_lite.cdf
Initial port.
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jtag.cdf
Initial port.
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latches.v
Initial port.
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memc_translator.v
Initial port.
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memc.v
Initial port.
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podules.v
Initial port.
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registerInterface.v
Initial port.
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sdram_defines.v
Initial port.
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sdram_init.v
Initial port.
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sdram_top.v
Initial port.
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serialInterface.v
Initial port.
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sram_byte_en.v
Initial port.
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sram_line_en.v
Initial port.
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timescale.v
Initial port.
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vidc_audio.v
Initial port.
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vidc_dmachannel.v
Initial port.
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vidc_fifo.v
Initial port.
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vidc_mulaw.mif
Initial port.
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vidc_timing.v
Initial port.
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vidc.v
Initial port.
2017-10-16 02:07:56 +08:00
Description
Acorn Archimedes for MiSTer
23 MiB
Languages
Verilog 67.8%
SystemVerilog 16.1%
VHDL 13%
Tcl 2%
Lua 0.9%
Other 0.2%