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75 lines
3.1 KiB
Verilog
75 lines
3.1 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// i2cSlaveTop.v ////
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//// ////
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//// This file is part of the i2cSlave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// You will need to modify this file to implement your
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//// interface.
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "i2cSlave_define.v"
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module i2cSlaveTop (
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clk,
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rst,
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sdaIn,
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sdaOut,
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scl
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);
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input clk;
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input rst;
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input sdaIn;
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output sdaOut;
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input scl;
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i2cSlave u_i2cSlave(
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.clk(clk),
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.rst(rst),
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.sdaIn(sdaIn),
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.sdaOut(sdaOut),
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.scl(scl)
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);
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endmodule
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