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101 lines
2.5 KiB
Verilog
101 lines
2.5 KiB
Verilog
/* sdram_init.v
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Copyright (c) 2013-2014, Stephen J. Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Stephen J. Leary nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL STEPHEN J. LEARY BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module sdram_init(
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input sd_clk,
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input sd_rst,
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output reg [3:0] sd_cmd,
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output reg [12:0] sd_a, // 13 bit multiplexed address bus
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output sd_rdy
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);
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`include "sdram_defines.v"
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parameter MODE = 0;
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reg [3:0] t;
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reg [4:0] reset;
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initial begin
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t = 4'd0;
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reset = 5'h1f;
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sd_a = 13'd0;
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sd_cmd = CMD_INHIBIT;
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end
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always @(posedge sd_clk) begin
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sd_cmd <= CMD_INHIBIT; // default: idle
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if (sd_rst) begin
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t <= 4'd0;
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reset <= 5'h1f;
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sd_a <= 13'd0;
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end else if (!sd_rdy) begin
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t <= t + 4'd1;
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if (t ==4'hF) begin
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reset <= reset - 5'd1;
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end
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if (t == 4'h0) begin
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if(reset == 13) begin
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$display("precharging all banks");
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sd_cmd <= CMD_PRECHARGE;
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sd_a[10] <= 1'b1; // precharge all banks
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end
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if(reset == 2) begin
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sd_cmd <= CMD_LOAD_MODE;
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sd_a <= MODE;
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end
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if(reset == 1) begin
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$display("loading mode");
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sd_cmd <= CMD_LOAD_MODE;
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sd_a <= MODE;
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end
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end
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end
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end
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assign sd_rdy = reset == 5'd0;
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endmodule |