16 Commits

Author	SHA1	Message	Date
Sorgelig	529f611074	vidc: delay pixel data.	2022-02-21 08:49:47 +08:00
Sorgelig	5bc3d70de4	fix: cmos change wasn't reported.	2022-02-21 08:32:02 +08:00
Adam Hay	cc7f68d5ee	Fix scrolling in James Pond ... Use the border enable as a video enable signal to position the screen correctly. This fixes cases where the video display start/end are shifted into the border to scroll the screen.	2021-08-25 23:36:32 +02:00
Adam Hay	a62ec86102	Apply STM write fixes to other memory areas too	2021-08-25 23:35:12 +02:00
Adam Hay	610eec8d1b	Fix colour and screen Glitches in Twinworld (#16) ... cpu_load is only true for the first write of a STM instruction, so subsequent writes to the VIDC registers were being lost	2021-08-23 13:14:13 +08:00
sorgelig	27caaacdfa	Adjust FDC timings, some IOC tweaks/refactoring.	2021-07-24 16:29:34 +08:00
sorgelig	8b1b4c9c5f	Update FDC.	2021-07-22 07:16:21 +08:00
sorgelig	e1000fb687	Use standard IDE interface and module.	2021-07-22 04:23:04 +08:00
sorgelig	79936abbad	ide: some cleanup and simplifications.	2020-08-21 03:30:37 +08:00
sorgelig	021e770fb8	sdram: refactor to improve routability.	2020-08-21 01:42:31 +08:00
sorgelig	9ef12f81b6	Rework cmos/rtc. Clear RAM upon BIOS load.	2020-08-20 14:32:04 +08:00
sorgelig	7a7af7cc5f	Enable FDD activity LED.	2020-08-19 06:33:25 +08:00
sorgelig	2b8126d7d0	Sources re-organization.	2020-08-19 06:11:56 +08:00
sorgelig	69f0f56407	Add IDE, update FDC.	2020-08-19 05:39:54 +08:00
RobertPeip	e272019a2e	add reset to cpu ... added more regs to reset for other modules added simulation some changes to be standard conform, mostly reordering of wire/reg defines	2020-08-08 22:53:38 +08:00
sorgelig	d1d852dabe	Update sys. Re-organize the sources.	2020-05-09 22:46:59 +08:00