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Fix the timings.

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sorgelig
2019-11-16 03:13:44 +08:00
parent 7ded251acd
commit e41b4f1a9c
5 changed files with 28 additions and 20 deletions
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2
Archie.qsf
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@@ -48,7 +48,7 @@ set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
set_global_assignment -name SEED 1
set_global_assignment -name SEED 2
source sys/sys.tcl
source sys/sys_analog.tcl

5
Archie.sdc Normal file
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@@ -0,0 +1,5 @@
derive_pll_clocks
derive_clock_uncertainty
set_multicycle_path -from [get_clocks {*|pll|pll_inst|altera_pll_i|*[2].*|divclk}] -to [get_clocks {*|pll|pll_inst|altera_pll_i|*[0].*|divclk}] -setup 2
set_multicycle_path -from [get_clocks {*|pll|pll_inst|altera_pll_i|*[2].*|divclk}] -to [get_clocks {*|pll|pll_inst|altera_pll_i|*[0].*|divclk}] -hold 1

1
files.qip
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@@ -20,4 +20,5 @@ set_global_assignment -name VERILOG_FILE sram_line_en.v
set_global_assignment -name VERILOG_FILE sram_byte_en.v
set_global_assignment -name VHDL_FILE bram.vhd
set_global_assignment -name VERILOG_FILE archimedes_top.v
set_global_assignment -name SDC_FILE Archie.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Archie.sv

12
sdram.sdc
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@@ -1,13 +1,15 @@
derive_pll_clocks
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
set clk_sdram_sys {*|pll|pll_inst|altera_pll_i|*[0].*|divclk}
set clk_sdram_chip {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}
create_generated_clock -name SDRAM_CLK -source [get_pins -compatibility_mode $clk_sdram_chip] [get_ports {SDRAM_CLK}]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
set_input_delay -max -clock $clk_sdram_sys 8.7ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock $clk_sdram_sys 6.0ns [get_ports SDRAM_DQ[*]]
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]

28
sdram.v
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@@ -61,7 +61,6 @@ localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd3; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam WRITE_BURST = 1'b0; // 0= write burst enabled, 1=only single access write
localparam RFC_DELAY = 4'd7; // tRFC=66ns -> 9 cycles@128MHz
// all possible commands
@@ -103,7 +102,7 @@ localparam CYCLE_CAS0 = CYCLE_RAS_START + RASCAS_DELAY;
localparam CYCLE_CAS1 = CYCLE_CAS0 + 4'd1;
localparam CYCLE_CAS2 = CYCLE_CAS1 + 4'd1;
localparam CYCLE_CAS3 = CYCLE_CAS2 + 4'd1;
localparam CYCLE_READ0 = CYCLE_CAS0 + CAS_LATENCY + 4'd1;
localparam CYCLE_READ0 = CYCLE_CAS0 + CAS_LATENCY + 4'd2;
localparam CYCLE_READ1 = CYCLE_READ0+ 1'd1;
localparam CYCLE_READ2 = CYCLE_READ1+ 1'd1;
localparam CYCLE_READ3 = CYCLE_READ2+ 1'd1;
@@ -117,14 +116,17 @@ localparam RAM_CLK = 128000000;
localparam REFRESH_PERIOD = (RAM_CLK / (16 * 8192));
always @(posedge sd_clk) begin
reg sd_reqD, sd_reqD2;
reg sd_newreq;
reg [3:0] sd_cycle = CYCLE_IDLE;
reg [2:0] word;
reg sd_reqD, sd_reqD2;
reg sd_newreq;
reg [3:0] sd_cycle = CYCLE_IDLE;
reg [2:0] word;
reg [15:0] sd_dq_reg;
sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
sd_cmd <= CMD_NOP;
sd_dq_reg <= sd_dq;
sd_reqD <= sd_req;
if(~sd_reqD & sd_req) sd_newreq <= 1;
@@ -135,14 +137,12 @@ always @(posedge sd_clk) begin
sd_ready <= 0;
sd_ba <= 0;
end else begin
if (!sd_ready) begin
if (reset) begin
t <= t + 4'd1;
if (t ==4'hF) begin
reset <= reset - 5'd1;
end
if (&t) reset <= reset - 5'd1;
if (t == 4'h0) begin
if (!t) begin
if(reset == 13) begin
$display("precharging all banks");
@@ -161,15 +161,15 @@ always @(posedge sd_clk) begin
sd_addr <= MODE;
end
if(!reset) sd_ready <= 1;
word <= 0;
end
end else begin
sd_ready <= 1;
sd_refresh <= sd_refresh + 9'd1;
if(word) begin
word <= word + 1'd1;
sd_dat[word[2:1]][{word[0],4'b0000} +:16] <= sd_dq;
sd_dat[word[2:1]][{word[0],4'b0000} +:16] <= sd_dq_reg;
end
// this is the auto refresh code.
@@ -233,7 +233,7 @@ always @(posedge sd_clk) begin
CYCLE_READ0: begin
if (sd_reading) begin
sd_dat[0][15:0]<= sd_dq;
sd_dat[0][15:0]<= sd_dq_reg;
word <= 1;
end else begin
if (sd_writing) sd_cycle <= CYCLE_IDLE;