mirror of
https://github.com/MiSTer-devel/Archie_MiSTer.git
synced 2026-04-19 03:04:04 +00:00
25 lines
1.3 KiB
Plaintext
25 lines
1.3 KiB
Plaintext
set_global_assignment -name QIP_FILE amber/amber.qip
|
|
set_global_assignment -name QIP_FILE sdram.qip
|
|
set_global_assignment -name VERILOG_FILE vidc_audio.v
|
|
set_global_assignment -name VERILOG_FILE vidc_dmachannel.v
|
|
set_global_assignment -name VERILOG_FILE vidc_fifo.v
|
|
set_global_assignment -name VERILOG_FILE vidc_timing.v
|
|
set_global_assignment -name VERILOG_FILE vidc.v
|
|
set_global_assignment -name VERILOG_FILE fdc1772.v
|
|
set_global_assignment -name VERILOG_FILE floppy.v
|
|
set_global_assignment -name VERILOG_FILE latches.v
|
|
set_global_assignment -name VERILOG_FILE podules.v
|
|
set_global_assignment -name VERILOG_FILE serialInterface.v
|
|
set_global_assignment -name VERILOG_FILE registerInterface.v
|
|
set_global_assignment -name VERILOG_FILE i2cSlave.v
|
|
set_global_assignment -name VERILOG_FILE ioc_irq.v
|
|
set_global_assignment -name VERILOG_FILE ioc.v
|
|
set_global_assignment -name VERILOG_FILE memc_translator.v
|
|
set_global_assignment -name VERILOG_FILE memc.v
|
|
set_global_assignment -name VERILOG_FILE sram_line_en.v
|
|
set_global_assignment -name VERILOG_FILE sram_byte_en.v
|
|
set_global_assignment -name VHDL_FILE bram.vhd
|
|
set_global_assignment -name VERILOG_FILE archimedes_top.v
|
|
set_global_assignment -name SDC_FILE Archie.sdc
|
|
set_global_assignment -name SYSTEMVERILOG_FILE Archie.sv
|