mirror of
https://github.com/MiSTer-devel/Archie_MiSTer.git
synced 2026-05-17 03:03:15 +00:00
Support for RTC. Support for CMOS loading.
This commit is contained in:
sorgelig
@@ -373,7 +373,6 @@ set_global_assignment -name VERILOG_FILE vidc_audio.v
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set_global_assignment -name VERILOG_FILE vidc_dmachannel.v
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set_global_assignment -name VERILOG_FILE serialInterface.v
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set_global_assignment -name VERILOG_FILE registerInterface.v
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set_global_assignment -name VERILOG_FILE i2cSlaveTop.v
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set_global_assignment -name VERILOG_FILE i2cSlave.v
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set_global_assignment -name VERILOG_FILE ioc_irq.v
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set_global_assignment -name VERILOG_FILE ioc.v
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35
Archie.sv
35
Archie.sv
@@ -249,6 +249,8 @@ wire kbd_out_strobe;
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wire [7:0] kbd_in_data;
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wire kbd_in_strobe;
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wire [64:0] RTC;
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wire ioctl_download;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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@@ -279,6 +281,8 @@ hps_io #(.STRLEN($size(CONF_STR)>>3), .WIDE(1), .VDNUM(2)) hps_io
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.buttons(buttons),
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.status(status),
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.RTC(RTC),
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.kbd_out_data(kbd_out_data),
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.kbd_out_strobe(kbd_out_strobe),
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@@ -430,19 +434,42 @@ sdram_top SDRAM
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.sd_ready (ram_ready )
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);
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i2cSlaveTop CMOS
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i2cSlave CMOS
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(
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.clk (clk_32m ),
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.rst (~pll_ready ),
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.sdaIn (i2c_din ),
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.sdaOut (i2c_dout ),
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.scl (i2c_clock )
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.scl (i2c_clock ),
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.RTC (RTC),
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.dl_addr(cmos_dl_addr),
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.dl_data(cmos_dl_addr[0] ? ioctl_dout[15:8] : ioctl_dout[7:0]),
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.dl_wr(|cmos_dl_wr),
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.dl_en(cmos_dl)
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);
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wire riscos_dl = (ioctl_index == 1) && ioctl_download;
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wire cmos_dl = (ioctl_index == 3) && ioctl_download;
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wire [7:0] cmos_dl_addr;
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wire [1:0] cmos_dl_wr;
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reg loader_stb = 0;
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always @(posedge clk_32m) begin
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if (ioctl_wr) loader_stb <= 1'b1;
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else if (ram_ack) loader_stb <= 1'b0;
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if (ram_ack) loader_stb <= 0;
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if(riscos_dl & ioctl_wr) loader_stb <= 1;
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cmos_dl_addr <= cmos_dl_addr + 1'd1;
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cmos_dl_wr <= {cmos_dl_wr[0],1'b0};
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if(cmos_dl) begin
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if(ioctl_wr) begin
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cmos_dl_addr <= ioctl_addr[7:0];
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cmos_dl_wr <= 1;
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end
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end
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end
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assign ram_we = riscos_dl ? 1'b1 : core_we_o;
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362
cmos.mif
362
cmos.mif
@@ -1,256 +1,106 @@
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-- Quartus Prime generated Memory Initialization File (.mif)
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WIDTH=8;
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DEPTH=256;
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ADDRESS_RADIX=HEX;
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DATA_RADIX=BIN;
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CONTENT BEGIN
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[000..002] : 00000000;
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003 : 00010110;
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004 : 00000000;
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005 : 11000100;
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006 : 00000011;
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[007..011] : 00000000;
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012 : 00000011;
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013 : 00000000;
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014 : 00011011;
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015 : 01101111;
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016 : 01000000;
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017 : 00100000;
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018 : 10000000;
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019 : 00010101;
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01A : 11110011;
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01B : 10001110;
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[01C..02B] : 00000000;
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02C : 00001101;
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[02D..02E] : 00000000;
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02F : 00001111;
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[030..03E] : 00000000;
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03F : 00100110;
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040 : 00000000;
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041 : 11111110;
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042 : 00000000;
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043 : 11101011;
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044 : 00000000;
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045 : 00001000;
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[046..049] : 00000000;
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04A : 00010000;
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04B : 01010000;
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04C : 00011101;
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04D : 00001100;
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04E : 00000000;
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04F : 00101110;
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050 : 10010000;
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051 : 00000010;
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[052..055] : 00000000;
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056 : 00000011;
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057 : 00001010;
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058 : 00000000;
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059 : 00000001;
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[05A..05B] : 00000000;
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05C : 00000010;
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[05D..0B3] : 00000000;
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0B4 : 00000001;
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[0B5..0B6] : 00000000;
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0B7 : 00000001;
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[0B8..0BF] : 00000000;
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0C0 : 00010011;
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0C1 : 00010100;
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[0C2..0C3] : 00000000;
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0C4 : 00000100;
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0C5 : 10010001;
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0C6 : 00100000;
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0C7 : 00000001;
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0C8 : 11110011;
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[0C9..0CB] : 00000000;
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0CC : 11111111;
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[0CD..0CE] : 00000000;
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0CF : 00001010;
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[0D0..0D3] : 00000000;
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0D4 : 11110000;
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0D5 : 10101000;
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0D6 : 11000011;
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0D7 : 00000000;
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0D8 : 11001111;
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[0D9..0F1] : 00000000;
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0F2 : 00111000;
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0F3 : 00000000;
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0F4 : 00000001;
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0F5 : 00101110;
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0F6 : 01111100;
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0F7 : 01111011;
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0F8 : 01111101;
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0F9 : 00001010;
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0FA : 01010000;
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0FB : 00000000;
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0FC : 10000000;
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0FD : 00000010;
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[0FE..0FF] : 00000000;
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END;
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||||
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34
i2cSlave.v
34
i2cSlave.v
@@ -45,19 +45,20 @@
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||||
`include "i2cSlave_define.v"
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||||
|
||||
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||||
module i2cSlave (
|
||||
clk,
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||||
rst,
|
||||
sdaIn,
|
||||
sdaOut,
|
||||
scl
|
||||
);
|
||||
module i2cSlave
|
||||
(
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||||
input clk,
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input rst,
|
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input sdaIn,
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||||
output sdaOut,
|
||||
input scl,
|
||||
|
||||
input clk;
|
||||
input rst;
|
||||
input sdaIn;
|
||||
output sdaOut;
|
||||
input scl;
|
||||
input [64:0] RTC,
|
||||
input [7:0] dl_addr,
|
||||
input [7:0] dl_data,
|
||||
input dl_wr,
|
||||
input dl_en
|
||||
);
|
||||
|
||||
// local wires and regs
|
||||
reg sdaDeb;
|
||||
@@ -154,10 +155,11 @@ end
|
||||
|
||||
registerInterface u_registerInterface(
|
||||
.clk(clk),
|
||||
.addr(regAddr),
|
||||
.dataIn(dataToRegIF),
|
||||
.writeEn(writeEn),
|
||||
.dataOut(dataFromRegIF)
|
||||
.addr(dl_en ? dl_addr : regAddr),
|
||||
.dataIn(dl_en ? dl_data : dataToRegIF),
|
||||
.writeEn(dl_en ? dl_wr : writeEn),
|
||||
.dataOut(dataFromRegIF),
|
||||
.RTC(RTC)
|
||||
);
|
||||
|
||||
serialInterface u_serialInterface (
|
||||
|
||||
@@ -1,74 +0,0 @@
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// i2cSlaveTop.v ////
|
||||
//// ////
|
||||
//// This file is part of the i2cSlave opencores effort.
|
||||
//// <http://www.opencores.org/cores//> ////
|
||||
//// ////
|
||||
//// Module Description: ////
|
||||
//// You will need to modify this file to implement your
|
||||
//// interface.
|
||||
//// ////
|
||||
//// To Do: ////
|
||||
////
|
||||
//// ////
|
||||
//// Author(s): ////
|
||||
//// - Steve Fielding, sfielding@base2designs.com ////
|
||||
//// ////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer. ////
|
||||
//// ////
|
||||
//// This source file is free software; you can redistribute it ////
|
||||
//// and/or modify it under the terms of the GNU Lesser General ////
|
||||
//// Public License as published by the Free Software Foundation; ////
|
||||
//// either version 2.1 of the License, or (at your option) any ////
|
||||
//// later version. ////
|
||||
//// ////
|
||||
//// This source is distributed in the hope that it will be ////
|
||||
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
||||
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
||||
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
||||
//// details. ////
|
||||
//// ////
|
||||
//// You should have received a copy of the GNU Lesser General ////
|
||||
//// Public License along with this source; if not, download it ////
|
||||
//// from <http://www.opencores.org/lgpl.shtml> ////
|
||||
//// ////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
`include "i2cSlave_define.v"
|
||||
|
||||
|
||||
module i2cSlaveTop (
|
||||
clk,
|
||||
rst,
|
||||
sdaIn,
|
||||
sdaOut,
|
||||
scl
|
||||
);
|
||||
input clk;
|
||||
input rst;
|
||||
input sdaIn;
|
||||
output sdaOut;
|
||||
input scl;
|
||||
|
||||
|
||||
i2cSlave u_i2cSlave(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.sdaIn(sdaIn),
|
||||
.sdaOut(sdaOut),
|
||||
.scl(scl)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -44,50 +44,46 @@
|
||||
//// ////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
`include "i2cSlave_define.v"
|
||||
|
||||
|
||||
module registerInterface (
|
||||
input clk,
|
||||
input [7:0] addr,
|
||||
input [7:0] dataIn,
|
||||
input writeEn,
|
||||
output reg [7:0] dataOut
|
||||
module registerInterface
|
||||
(
|
||||
input clk,
|
||||
input [7:0] addr,
|
||||
input [7:0] dataIn,
|
||||
input writeEn,
|
||||
output reg [7:0] dataOut,
|
||||
input [64:0] RTC
|
||||
);
|
||||
|
||||
localparam MEM_DEPTH = 256;
|
||||
|
||||
|
||||
reg [7:0] memory[0:MEM_DEPTH-1];
|
||||
wire [7:0] mem_out;
|
||||
spram #(8,8,"cmos.mif","CMOS") memory
|
||||
(
|
||||
.clock(clk),
|
||||
.address(addr),
|
||||
.data(dataIn),
|
||||
.wren(writeEn),
|
||||
.q(mem_out)
|
||||
);
|
||||
|
||||
integer i;
|
||||
|
||||
initial begin
|
||||
wire [7:0] year = {3'b000,RTC[47:44],1'b0} + {RTC[47:44],3'b000} + RTC[43:40];
|
||||
|
||||
$readmemh("cmos.mif", memory);
|
||||
|
||||
end
|
||||
|
||||
// --- I2C Read
|
||||
always @(posedge clk) begin
|
||||
always @(*) begin
|
||||
casex (addr)
|
||||
8'h02: dataOut <= 8'h33; // sec
|
||||
8'h03: dataOut <= 8'h33; // mins
|
||||
8'h04: dataOut <= 8'h11; // hour
|
||||
8'h05: dataOut <= 8'he9; // year
|
||||
8'h06: dataOut <= 8'h81; // month/week
|
||||
8'h0x: dataOut <= 8'h00; // everything else < 16
|
||||
default: dataOut <= memory[addr];
|
||||
8'h02: dataOut = RTC[7:0]; // secs
|
||||
8'h03: dataOut = RTC[15:8]; // mins
|
||||
8'h04: dataOut = RTC[23:16]; // hour
|
||||
8'h05: dataOut = {year[1:0],RTC[29:24]}; // date
|
||||
8'h06: dataOut = {RTC[50:48],RTC[36:32]}; // weekday/month
|
||||
8'hC0: dataOut = year;
|
||||
8'hC1: dataOut = 20;
|
||||
8'b0000000X,
|
||||
8'b00000111,
|
||||
8'b00001XXX: dataOut = 0;
|
||||
default: dataOut = mem_out;
|
||||
endcase
|
||||
end
|
||||
|
||||
// --- I2C Write
|
||||
always @(posedge clk) begin
|
||||
if (writeEn == 1'b1) begin
|
||||
memory[addr] <= dataIn;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user