diff --git a/Archie.qsf b/Archie.qsf
index 8cf4938..1e066a6 100644
--- a/Archie.qsf
+++ b/Archie.qsf
@@ -373,7 +373,6 @@ set_global_assignment -name VERILOG_FILE vidc_audio.v
set_global_assignment -name VERILOG_FILE vidc_dmachannel.v
set_global_assignment -name VERILOG_FILE serialInterface.v
set_global_assignment -name VERILOG_FILE registerInterface.v
-set_global_assignment -name VERILOG_FILE i2cSlaveTop.v
set_global_assignment -name VERILOG_FILE i2cSlave.v
set_global_assignment -name VERILOG_FILE ioc_irq.v
set_global_assignment -name VERILOG_FILE ioc.v
diff --git a/Archie.sv b/Archie.sv
index d8e9798..90f21b4 100644
--- a/Archie.sv
+++ b/Archie.sv
@@ -249,6 +249,8 @@ wire kbd_out_strobe;
wire [7:0] kbd_in_data;
wire kbd_in_strobe;
+wire [64:0] RTC;
+
wire ioctl_download;
wire [7:0] ioctl_index;
wire ioctl_wr;
@@ -279,6 +281,8 @@ hps_io #(.STRLEN($size(CONF_STR)>>3), .WIDE(1), .VDNUM(2)) hps_io
.buttons(buttons),
.status(status),
+
+ .RTC(RTC),
.kbd_out_data(kbd_out_data),
.kbd_out_strobe(kbd_out_strobe),
@@ -430,19 +434,42 @@ sdram_top SDRAM
.sd_ready (ram_ready )
);
-i2cSlaveTop CMOS
+i2cSlave CMOS
(
.clk (clk_32m ),
.rst (~pll_ready ),
.sdaIn (i2c_din ),
.sdaOut (i2c_dout ),
- .scl (i2c_clock )
+ .scl (i2c_clock ),
+
+ .RTC (RTC),
+
+ .dl_addr(cmos_dl_addr),
+ .dl_data(cmos_dl_addr[0] ? ioctl_dout[15:8] : ioctl_dout[7:0]),
+ .dl_wr(|cmos_dl_wr),
+ .dl_en(cmos_dl)
);
+
wire riscos_dl = (ioctl_index == 1) && ioctl_download;
+wire cmos_dl = (ioctl_index == 3) && ioctl_download;
+
+wire [7:0] cmos_dl_addr;
+wire [1:0] cmos_dl_wr;
+
reg loader_stb = 0;
always @(posedge clk_32m) begin
- if (ioctl_wr) loader_stb <= 1'b1;
- else if (ram_ack) loader_stb <= 1'b0;
+ if (ram_ack) loader_stb <= 0;
+ if(riscos_dl & ioctl_wr) loader_stb <= 1;
+
+ cmos_dl_addr <= cmos_dl_addr + 1'd1;
+ cmos_dl_wr <= {cmos_dl_wr[0],1'b0};
+
+ if(cmos_dl) begin
+ if(ioctl_wr) begin
+ cmos_dl_addr <= ioctl_addr[7:0];
+ cmos_dl_wr <= 1;
+ end
+ end
end
assign ram_we = riscos_dl ? 1'b1 : core_we_o;
diff --git a/cmos.mif b/cmos.mif
index 25e6d39..37d7d42 100644
--- a/cmos.mif
+++ b/cmos.mif
@@ -1,256 +1,106 @@
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-03
-00
-1b
-6f
-40
-20
-80
-15
-f3
-8e
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-0d
-00
-00
-0f
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-75
-00
-fe
-00
-eb
-00
-08
-00
-00
-00
-00
-10
-50
-1d
-0c
-00
-2e
-90
-02
-00
-00
-00
-00
-03
-0a
-00
-01
-00
-00
-02
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-01
-00
-00
-01
-00
-00
-00
-00
-00
-00
-00
-00
-63
-13
-00
-00
-04
-91
-20
-01
-f3
-00
-00
-00
-ff
-00
-00
-0a
-00
-00
-00
-00
-f0
-a8
-c3
-00
-cf
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-38
-00
-01
-2e
-7c
-7b
-7d
-0a
-50
-00
-80
-02
-00
-00
+-- Copyright (C) 2017 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Intel Program License
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel MegaCore Function License Agreement, or other
+-- applicable license agreement, including, without limitation,
+-- that your use is for the sole purpose of programming logic
+-- devices manufactured by Intel and sold by Intel or its
+-- authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=8;
+DEPTH=256;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=BIN;
+
+CONTENT BEGIN
+ [000..002] : 00000000;
+ 003 : 00010110;
+ 004 : 00000000;
+ 005 : 11000100;
+ 006 : 00000011;
+ [007..011] : 00000000;
+ 012 : 00000011;
+ 013 : 00000000;
+ 014 : 00011011;
+ 015 : 01101111;
+ 016 : 01000000;
+ 017 : 00100000;
+ 018 : 10000000;
+ 019 : 00010101;
+ 01A : 11110011;
+ 01B : 10001110;
+ [01C..02B] : 00000000;
+ 02C : 00001101;
+ [02D..02E] : 00000000;
+ 02F : 00001111;
+ [030..03E] : 00000000;
+ 03F : 00100110;
+ 040 : 00000000;
+ 041 : 11111110;
+ 042 : 00000000;
+ 043 : 11101011;
+ 044 : 00000000;
+ 045 : 00001000;
+ [046..049] : 00000000;
+ 04A : 00010000;
+ 04B : 01010000;
+ 04C : 00011101;
+ 04D : 00001100;
+ 04E : 00000000;
+ 04F : 00101110;
+ 050 : 10010000;
+ 051 : 00000010;
+ [052..055] : 00000000;
+ 056 : 00000011;
+ 057 : 00001010;
+ 058 : 00000000;
+ 059 : 00000001;
+ [05A..05B] : 00000000;
+ 05C : 00000010;
+ [05D..0B3] : 00000000;
+ 0B4 : 00000001;
+ [0B5..0B6] : 00000000;
+ 0B7 : 00000001;
+ [0B8..0BF] : 00000000;
+ 0C0 : 00010011;
+ 0C1 : 00010100;
+ [0C2..0C3] : 00000000;
+ 0C4 : 00000100;
+ 0C5 : 10010001;
+ 0C6 : 00100000;
+ 0C7 : 00000001;
+ 0C8 : 11110011;
+ [0C9..0CB] : 00000000;
+ 0CC : 11111111;
+ [0CD..0CE] : 00000000;
+ 0CF : 00001010;
+ [0D0..0D3] : 00000000;
+ 0D4 : 11110000;
+ 0D5 : 10101000;
+ 0D6 : 11000011;
+ 0D7 : 00000000;
+ 0D8 : 11001111;
+ [0D9..0F1] : 00000000;
+ 0F2 : 00111000;
+ 0F3 : 00000000;
+ 0F4 : 00000001;
+ 0F5 : 00101110;
+ 0F6 : 01111100;
+ 0F7 : 01111011;
+ 0F8 : 01111101;
+ 0F9 : 00001010;
+ 0FA : 01010000;
+ 0FB : 00000000;
+ 0FC : 10000000;
+ 0FD : 00000010;
+ [0FE..0FF] : 00000000;
+END;
diff --git a/i2cSlave.v b/i2cSlave.v
index 416b599..659b29b 100644
--- a/i2cSlave.v
+++ b/i2cSlave.v
@@ -45,19 +45,20 @@
`include "i2cSlave_define.v"
-module i2cSlave (
- clk,
- rst,
- sdaIn,
- sdaOut,
- scl
-);
+module i2cSlave
+(
+ input clk,
+ input rst,
+ input sdaIn,
+ output sdaOut,
+ input scl,
-input clk;
-input rst;
-input sdaIn;
-output sdaOut;
-input scl;
+ input [64:0] RTC,
+ input [7:0] dl_addr,
+ input [7:0] dl_data,
+ input dl_wr,
+ input dl_en
+);
// local wires and regs
reg sdaDeb;
@@ -154,10 +155,11 @@ end
registerInterface u_registerInterface(
.clk(clk),
- .addr(regAddr),
- .dataIn(dataToRegIF),
- .writeEn(writeEn),
- .dataOut(dataFromRegIF)
+ .addr(dl_en ? dl_addr : regAddr),
+ .dataIn(dl_en ? dl_data : dataToRegIF),
+ .writeEn(dl_en ? dl_wr : writeEn),
+ .dataOut(dataFromRegIF),
+ .RTC(RTC)
);
serialInterface u_serialInterface (
diff --git a/i2cSlaveTop.v b/i2cSlaveTop.v
deleted file mode 100644
index 124b26a..0000000
--- a/i2cSlaveTop.v
+++ /dev/null
@@ -1,74 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// i2cSlaveTop.v ////
-//// ////
-//// This file is part of the i2cSlave opencores effort.
-//// ////
-//// ////
-//// Module Description: ////
-//// You will need to modify this file to implement your
-//// interface.
-//// ////
-//// To Do: ////
-////
-//// ////
-//// Author(s): ////
-//// - Steve Fielding, sfielding@base2designs.com ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-`include "i2cSlave_define.v"
-
-
-module i2cSlaveTop (
- clk,
- rst,
- sdaIn,
- sdaOut,
- scl
-);
-input clk;
-input rst;
-input sdaIn;
-output sdaOut;
-input scl;
-
-
-i2cSlave u_i2cSlave(
- .clk(clk),
- .rst(rst),
- .sdaIn(sdaIn),
- .sdaOut(sdaOut),
- .scl(scl)
-);
-
-
-endmodule
-
-
-
diff --git a/registerInterface.v b/registerInterface.v
index 33370de..65bb3fd 100644
--- a/registerInterface.v
+++ b/registerInterface.v
@@ -44,50 +44,46 @@
//// ////
//////////////////////////////////////////////////////////////////////
//
-`include "i2cSlave_define.v"
-
-module registerInterface (
- input clk,
- input [7:0] addr,
- input [7:0] dataIn,
- input writeEn,
- output reg [7:0] dataOut
+module registerInterface
+(
+ input clk,
+ input [7:0] addr,
+ input [7:0] dataIn,
+ input writeEn,
+ output reg [7:0] dataOut,
+ input [64:0] RTC
);
- localparam MEM_DEPTH = 256;
-
-
-reg [7:0] memory[0:MEM_DEPTH-1];
+wire [7:0] mem_out;
+spram #(8,8,"cmos.mif","CMOS") memory
+(
+ .clock(clk),
+ .address(addr),
+ .data(dataIn),
+ .wren(writeEn),
+ .q(mem_out)
+);
-integer i;
-
-initial begin
+wire [7:0] year = {3'b000,RTC[47:44],1'b0} + {RTC[47:44],3'b000} + RTC[43:40];
- $readmemh("cmos.mif", memory);
-
-end
-
// --- I2C Read
-always @(posedge clk) begin
+always @(*) begin
casex (addr)
- 8'h02: dataOut <= 8'h33; // sec
- 8'h03: dataOut <= 8'h33; // mins
- 8'h04: dataOut <= 8'h11; // hour
- 8'h05: dataOut <= 8'he9; // year
- 8'h06: dataOut <= 8'h81; // month/week
- 8'h0x: dataOut <= 8'h00; // everything else < 16
- default: dataOut <= memory[addr];
+ 8'h02: dataOut = RTC[7:0]; // secs
+ 8'h03: dataOut = RTC[15:8]; // mins
+ 8'h04: dataOut = RTC[23:16]; // hour
+ 8'h05: dataOut = {year[1:0],RTC[29:24]}; // date
+ 8'h06: dataOut = {RTC[50:48],RTC[36:32]}; // weekday/month
+ 8'hC0: dataOut = year;
+ 8'hC1: dataOut = 20;
+ 8'b0000000X,
+ 8'b00000111,
+ 8'b00001XXX: dataOut = 0;
+ default: dataOut = mem_out;
endcase
end
-// --- I2C Write
-always @(posedge clk) begin
- if (writeEn == 1'b1) begin
- memory[addr] <= dataIn;
- end
-end
-
endmodule