mirror of
https://github.com/MiSTer-devel/Archie_MiSTer.git
synced 2026-04-19 03:04:04 +00:00
484 lines
11 KiB
Systemverilog
484 lines
11 KiB
Systemverilog
//============================================================================
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// Acorn Archimedes
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//
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// Port to MiSTer.
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// Copyright (C) 2017-2019 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [44:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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input TAPE_IN,
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// SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..5 - USR1..USR4
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// Set USER_OUT to 1 to read from USER_IN.
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input [5:0] USER_IN,
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output [5:0] USER_OUT,
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input OSD_STATUS
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);
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign LED_USER = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
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assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3;
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`include "build_id.v"
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localparam CONF_STR = {
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"ARCHIE;;",
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"J,Fire;",
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"V,v",`BUILD_DATE
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};
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//////////////////// CLOCKS ///////////////////
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/*
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24, 16, 12, 8
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25, 16.6, 12.6, 8.3
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36, 24, 18, 12
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24, 16, 12, 8
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*/
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vpll vpll
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(
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.refclk(CLK_50M),
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.rst(reset),
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.reconfig_to_pll(reconfig_to_pll),
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.reconfig_from_pll(reconfig_from_pll),
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.outclk_0(CLK_VIDEO)
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);
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wire [63:0] reconfig_to_pll;
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wire [63:0] reconfig_from_pll;
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wire cfg_waitrequest;
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reg cfg_write;
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reg [5:0] cfg_address;
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reg [31:0] cfg_writedata;
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altera_pll_reconfig_top #(
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.device_family ("Cyclone V"),
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.ENABLE_MIF (1),
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.MIF_FILE_NAME ("vpll_conf.mif"),
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.ENABLE_BYTEENABLE (0),
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.BYTEENABLE_WIDTH (4),
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.RECONFIG_ADDR_WIDTH (6),
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.RECONFIG_DATA_WIDTH (32),
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.reconf_width (64),
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.WAIT_FOR_LOCK (1)
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) vpll_cfg (
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.mgmt_reset (reset),
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.mgmt_clk (CLK_50M),
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.mgmt_write (cfg_write),
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.mgmt_address (cfg_address),
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.mgmt_writedata (cfg_writedata),
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.mgmt_waitrequest (cfg_waitrequest),
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.reconfig_to_pll (reconfig_to_pll),
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.reconfig_from_pll (reconfig_from_pll)
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);
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always @(posedge CLK_50M) begin
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reg [2:0] cfg_state = 0;
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reg cfg_start = 0;
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reg [1:0] cfg_cur;
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if(reset) cfg_start <= 1;
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else begin
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cfg_cur <= pixbaseclk_select;
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if(cfg_cur != pixbaseclk_select) cfg_start = 1;
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if(!cfg_waitrequest) begin
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cfg_write <= 0;
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case(cfg_state)
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0: if(cfg_start) begin
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cfg_cur <= pixbaseclk_select;
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cfg_start <= 0;
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cfg_state <= cfg_state + 1'd1;
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end
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1: begin
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cfg_address <= 31;
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cfg_writedata <= {cfg_cur,6'b000000};
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cfg_write <= 1;
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cfg_state <= cfg_state + 1'd1;
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end
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2: cfg_state <= cfg_state + 1'd1;
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3: begin
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cfg_address <= 2;
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cfg_writedata <= 0;
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cfg_write <= 1;
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cfg_state <= cfg_state + 1'd1;
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end
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4: cfg_state <= cfg_state + 1'd1;
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5: cfg_state <= 0;
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endcase
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end
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end
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end
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wire pll_ready;
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wire clk_128m;
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wire clk_32m;
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pll pll
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(
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.refclk(CLK_50M),
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.outclk_0(clk_128m),
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.outclk_1(SDRAM_CLK),
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.outclk_2(clk_32m),
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.locked(pll_ready)
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);
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wire reset = status[0] | buttons[1] | ~initReset_n;
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reg initReset_n = 0;
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always @(posedge clk_32m) if(ioctl_download) initReset_n <= 1;
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////////////////// HPS I/O ///////////////////
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wire [15:0] joyA;
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wire [15:0] joyB;
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wire [1:0] buttons;
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wire [31:0] status;
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wire [7:0] kbd_out_data;
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wire kbd_out_strobe;
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wire [7:0] kbd_in_data;
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wire kbd_in_strobe;
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wire [64:0] RTC;
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wire ioctl_download;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [15:0] ioctl_dout;
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wire [31:0] sd_lba;
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wire [1:0] sd_rd;
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wire [1:0] sd_wr;
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wire sd_ack;
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wire [7:0] sd_buff_addr;
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wire [15:0] sd_buff_dout;
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wire [15:0] sd_buff_din;
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wire sd_buff_wr;
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wire [1:0] img_mounted;
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wire [31:0] img_size;
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wire img_readonly;
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hps_io #(.STRLEN($size(CONF_STR)>>3), .WIDE(1), .VDNUM(2)) hps_io
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(
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.clk_sys(clk_32m),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.joystick_0(joyA),
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.joystick_1(joyB),
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.buttons(buttons),
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.status(status),
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.RTC(RTC),
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.kbd_out_data(kbd_out_data),
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.kbd_out_strobe(kbd_out_strobe),
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.kbd_in_data(kbd_in_data),
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.kbd_in_strobe(kbd_in_strobe),
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.ioctl_index(ioctl_index),
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.ioctl_download(ioctl_download),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_wr(ioctl_wr),
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.ioctl_wait(loader_stb),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
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.sd_buff_wr(sd_buff_wr),
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.img_mounted(img_mounted),
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.img_size(img_size),
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.img_readonly(img_readonly)
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);
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assign AUDIO_S = 0;
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assign AUDIO_MIX = status[3:2];
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wire [3:0] core_r, core_g, core_b;
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wire core_hs, core_vs;
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assign VGA_R = {core_r,core_r};
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assign VGA_G = {core_g,core_g};
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assign VGA_B = {core_b,core_b};
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assign VGA_HS = ~core_hs;
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assign VGA_VS = ~core_vs;
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assign VGA_F1 = 0;
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assign VGA_SL = 0;
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wire core_ack_in;
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wire core_stb_out;
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wire core_cyc_out;
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wire core_we_o;
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wire [3:0] core_sel_o;
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wire [2:0] core_cti_o;
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wire [31:0] core_data_in, core_data_out;
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wire [31:0] ram_data_in;
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wire [26:2] core_address_out;
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wire [1:0] pixbaseclk_select;
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wire i2c_din, i2c_dout, i2c_clock;
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archimedes_top ARCHIMEDES
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(
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.CLKCPU_I ( clk_32m ),
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.CLKPIX_I ( CLK_VIDEO ),
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.CEPIX_O ( CE_PIXEL ),
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.RESET_I (~ram_ready | ioctl_download | reset),
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.MEM_ACK_I ( core_ack_in ),
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.MEM_DAT_I ( core_data_in ),
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.MEM_DAT_O ( core_data_out ),
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.MEM_ADDR_O ( core_address_out),
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.MEM_STB_O ( core_stb_out ),
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.MEM_CYC_O ( core_cyc_out ),
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.MEM_SEL_O ( core_sel_o ),
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.MEM_WE_O ( core_we_o ),
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.MEM_CTI_O ( core_cti_o ),
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.HSYNC ( core_hs ),
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.VSYNC ( core_vs ),
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.VIDEO_R ( core_r ),
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.VIDEO_G ( core_g ),
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.VIDEO_B ( core_b ),
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.VIDEO_EN ( VGA_DE ),
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.AUDIO_L ( AUDIO_L ),
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.AUDIO_R ( AUDIO_R ),
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.I2C_DOUT ( i2c_din ),
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.I2C_DIN ( i2c_dout ),
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.I2C_CLOCK ( i2c_clock ),
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.DEBUG_LED ( ),
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.sd_lba ( sd_lba ),
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.sd_rd ( sd_rd ),
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.sd_wr ( sd_wr ),
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.sd_ack ( sd_ack ),
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.sd_buff_addr ( sd_buff_addr ),
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.sd_buff_dout ( sd_buff_dout ),
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.sd_buff_din ( sd_buff_din ),
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.sd_buff_wr ( sd_buff_wr ),
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.img_mounted ( img_mounted ),
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.img_size ( img_size ),
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.img_wp ( img_readonly ),
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.KBD_OUT_DATA ( kbd_out_data ),
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.KBD_OUT_STROBE ( kbd_out_strobe ),
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.KBD_IN_DATA ( kbd_in_data ),
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.KBD_IN_STROBE ( kbd_in_strobe ),
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.JOYSTICK0 (~{joyA[4],joyA[0],joyA[1],joyA[2],joyA[3]}),
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.JOYSTICK1 (~{joyB[4],joyB[0],joyB[1],joyB[2],joyB[3]}),
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.VIDBASECLK_O ( pixbaseclk_select ),
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.VIDSYNCPOL_O ( )
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);
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wire ram_ack;
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wire ram_stb;
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wire ram_cyc;
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wire ram_we;
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wire [3:0] ram_sel;
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wire [25:0] ram_address;
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wire ram_ready;
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sdram_top SDRAM
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(
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// wishbone interface
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.wb_clk (clk_32m ),
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.wb_stb (ram_stb ),
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.wb_cyc (ram_cyc ),
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.wb_we (ram_we ),
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.wb_ack (ram_ack ),
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.wb_sel (ram_sel ),
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.wb_adr (ram_address ),
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.wb_dat_i (ram_data_in ),
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.wb_dat_o (core_data_in),
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.wb_cti (core_cti_o ),
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// SDRAM Interface
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.sd_clk (clk_128m ),
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.sd_rst (~pll_ready ),
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.sd_cke (SDRAM_CKE ),
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.sd_dq (SDRAM_DQ ),
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.sd_addr (SDRAM_A ),
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.sd_dqm ({SDRAM_DQMH,SDRAM_DQML}),
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.sd_cs_n (SDRAM_nCS ),
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.sd_ba (SDRAM_BA ),
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.sd_we_n (SDRAM_nWE ),
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.sd_ras_n (SDRAM_nRAS ),
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.sd_cas_n (SDRAM_nCAS ),
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.sd_ready (ram_ready )
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);
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i2cSlave CMOS
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(
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.clk (clk_32m ),
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.rst (~pll_ready ),
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.sdaIn (i2c_din ),
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.sdaOut (i2c_dout ),
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.scl (i2c_clock ),
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.RTC (RTC),
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.dl_addr(cmos_dl_addr),
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.dl_data(cmos_dl_addr[0] ? ioctl_dout[15:8] : ioctl_dout[7:0]),
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.dl_wr(|cmos_dl_wr),
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.dl_en(cmos_dl)
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);
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wire riscos_dl = (ioctl_index == 1) && ioctl_download;
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wire cmos_dl = (ioctl_index == 3) && ioctl_download;
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wire [7:0] cmos_dl_addr;
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wire [1:0] cmos_dl_wr;
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reg loader_stb = 0;
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always @(posedge clk_32m) begin
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if (ram_ack) loader_stb <= 0;
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if(riscos_dl & ioctl_wr) loader_stb <= 1;
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cmos_dl_addr <= cmos_dl_addr + 1'd1;
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cmos_dl_wr <= {cmos_dl_wr[0],1'b0};
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if(cmos_dl) begin
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if(ioctl_wr) begin
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cmos_dl_addr <= ioctl_addr[7:0];
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cmos_dl_wr <= 1;
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end
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end
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end
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assign ram_we = riscos_dl ? 1'b1 : core_we_o;
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assign ram_sel = riscos_dl ? (ioctl_addr[1] ? 4'b1100 : 4'b0011) : core_sel_o;
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assign ram_address = riscos_dl ? 25'h400000 + {ioctl_addr[23:2],2'b00} : {core_address_out[23:2],2'b00};
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assign ram_stb = riscos_dl ? loader_stb : core_stb_out;
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assign ram_cyc = riscos_dl ? loader_stb : core_stb_out;
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assign ram_data_in = riscos_dl ? {ioctl_dout,ioctl_dout} : core_data_out;
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assign core_ack_in = riscos_dl ? 1'b0 : ram_ack;
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endmodule
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