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Merge pull request #4 from ika-musume/video-sprite

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Sprite engine complete
This commit is contained in:
Raki
2021-12-26 23:32:58 +09:00
committed by GitHub
parent 98ff09eecc 8c0ccb38aa
commit fecbb3a4fb
30 changed files with 2760 additions and 1236 deletions
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44
BubSysROM_core_ModelSim/BubSysROM_component/asic/K005290.v
View File

@@ -34,7 +34,7 @@ module K005290
///////////////////////////////////////////////////////////
////// PIXEL DATA LATCH
////// TILELINE LATCH
////
//
@@ -64,7 +64,7 @@ wire pixel7_n = ~(i_ABS_2H & ABS_2H_dl & ~i_ABS_n4H);
//
// pixel latches
// tileline latches
//
/*
@@ -73,8 +73,8 @@ wire pixel7_n = ~(i_ABS_2H & ABS_2H_dl & ~i_ABS_n4H);
DRAM A B C D E F G H
*/
reg [31:0] A_LINELATCH;
reg [31:0] B_LINELATCH;
reg [31:0] A_TILELINELATCH;
reg [31:0] B_TILELINELATCH;
always @(posedge i_EMU_MCLK)
begin
@@ -82,7 +82,7 @@ begin
begin
if(!pixel7_n) //posedge of px7
begin
A_LINELATCH <= i_GFXDATA;
A_TILELINELATCH <= i_GFXDATA;
end
end
end
@@ -93,7 +93,7 @@ begin
begin
if(!pixel3_n) //posedge of px3
begin
B_LINELATCH <= i_GFXDATA;
B_TILELINELATCH <= i_GFXDATA;
end
end
end
@@ -162,14 +162,14 @@ begin
A_PIXEL7 <= 4'h0;
end
2'b11: begin
A_PIXEL0 <= A_LINELATCH[31:28];
A_PIXEL1 <= A_LINELATCH[27:24];
A_PIXEL2 <= A_LINELATCH[23:20];
A_PIXEL3 <= A_LINELATCH[19:16];
A_PIXEL4 <= A_LINELATCH[15:12];
A_PIXEL5 <= A_LINELATCH[11:8];
A_PIXEL6 <= A_LINELATCH[7:4];
A_PIXEL7 <= A_LINELATCH[3:0];
A_PIXEL0 <= A_TILELINELATCH[31:28];
A_PIXEL1 <= A_TILELINELATCH[27:24];
A_PIXEL2 <= A_TILELINELATCH[23:20];
A_PIXEL3 <= A_TILELINELATCH[19:16];
A_PIXEL4 <= A_TILELINELATCH[15:12];
A_PIXEL5 <= A_TILELINELATCH[11:8];
A_PIXEL6 <= A_TILELINELATCH[7:4];
A_PIXEL7 <= A_TILELINELATCH[3:0];
end
endcase
end
@@ -238,14 +238,14 @@ begin
B_PIXEL7 <= 4'h0;
end
2'b11: begin
B_PIXEL0 <= B_LINELATCH[31:28];
B_PIXEL1 <= B_LINELATCH[27:24];
B_PIXEL2 <= B_LINELATCH[23:20];
B_PIXEL3 <= B_LINELATCH[19:16];
B_PIXEL4 <= B_LINELATCH[15:12];
B_PIXEL5 <= B_LINELATCH[11:8];
B_PIXEL6 <= B_LINELATCH[7:4];
B_PIXEL7 <= B_LINELATCH[3:0];
B_PIXEL0 <= B_TILELINELATCH[31:28];
B_PIXEL1 <= B_TILELINELATCH[27:24];
B_PIXEL2 <= B_TILELINELATCH[23:20];
B_PIXEL3 <= B_TILELINELATCH[19:16];
B_PIXEL4 <= B_TILELINELATCH[15:12];
B_PIXEL5 <= B_TILELINELATCH[11:8];
B_PIXEL6 <= B_TILELINELATCH[7:4];
B_PIXEL7 <= B_TILELINELATCH[3:0];
end
endcase
end

330
BubSysROM_core_ModelSim/BubSysROM_component/asic/K005292.v
View File

@@ -53,12 +53,12 @@ module K005292
output wire o_FLIP_2V,
output wire o_FLIP_1V,
output reg o_VCLK = 1'b0,
output reg o_VCLK,
output reg o_FRAMEPARITY = 1'b0,
output wire o_VSYNC_n,
output wire o_CSYNC_n,
output reg o_CSYNC,
output wire [8:0] __REF_HCOUNTER,
output wire [8:0] __REF_VCOUNTER
@@ -119,84 +119,26 @@ assign {
o_FLIP_1V
} = vertical_counter[7:0] ^ {8{i_VFLIP}};
always @(posedge i_EMU_MCLK or negedge i_MRST_n)
//
// HCOUNTER
//
always @(posedge i_EMU_MCLK)
begin
if(!i_MRST_n) //asynchronous reset
begin
horizontal_counter <= 9'd128;
vertical_counter <= 9'd248;
o_VBLANK_n <= 1'b0;
o_VBLANKH_n <= 1'b0;
o_FRAMEPARITY <= 1'b0;
__REF_DMA_n <= 1'b1;
end
else
begin //count up
begin
if(!i_EMU_CLK6MPCEN_n)
begin
if(horizontal_counter < 9'd511) //h count up
begin
if(horizontal_counter == 9'd175) //v count up
begin
if(vertical_counter < 9'd511)
begin
//VBLANK
if(vertical_counter > 9'd494 || vertical_counter < 9'd271)
begin
o_VBLANK_n <= 1'b0;
end
else
begin
o_VBLANK_n <= 1'b1;
end
//VBLANK**
if(vertical_counter > 9'd247 && vertical_counter < 9'd271)
begin
o_VBLANKH_n <= 1'b0;
end
else
begin
o_VBLANKH_n <= 1'b1;
end
//256V
if(vertical_counter == 9'd495) //flip parity value
begin
o_FRAMEPARITY <= ~o_FRAMEPARITY;
end
//DMA
if(vertical_counter > 9'd478 && vertical_counter < 9'd495)
begin
__REF_DMA_n <= 1'b0;
end
else
begin
__REF_DMA_n <= 1'b1;
end
vertical_counter <= vertical_counter + 9'd1;
end
else
begin
vertical_counter <= 9'd248;
end
end
if(horizontal_counter > 9'd174 && horizontal_counter < 9'd207)
begin
o_VCLK <= 1'b1;
end
else
begin
o_VCLK <= 1'b0;
end
horizontal_counter <= horizontal_counter + 9'd1;
end
else //h loop
else //h loop
begin
horizontal_counter <= 9'd128;
end
@@ -205,12 +147,262 @@ begin
end
//
// SYNC TIP GENERATOR
//
reg narrow_hsync_on_vsync = 1'b0; //appears on just before vsync period of even frame
reg wide_hsync_on_vsync = 1'b0; //appears on vsync period
reg hsync = 1'b0; //normal vclk
reg narrow_hsync_on_vsync_clken_n = 1'b1;
reg hsync_clken_n = 1'b1;
always @(posedge i_EMU_MCLK)
begin
if(!i_MRST_n) //asynchronous reset
begin
narrow_hsync_on_vsync <= 1'b0;
wide_hsync_on_vsync <= 1'b0;
hsync <= 1'b0;
end
else
begin
if(!i_EMU_CLK6MPCEN_n)
begin
//narrow hsync on vsync
if(horizontal_counter == 9'd175)
begin
narrow_hsync_on_vsync <= 1'b1;
end
else if(horizontal_counter == 9'd191)
begin
narrow_hsync_on_vsync <= 1'b0;
end
else if(horizontal_counter == 9'd367)
begin
narrow_hsync_on_vsync <= 1'b1;
end
else if(horizontal_counter == 9'd383)
begin
narrow_hsync_on_vsync <= 1'b0;
end
else
begin
narrow_hsync_on_vsync <= narrow_hsync_on_vsync;
end
//wide hysnc on vsync
if(horizontal_counter == 9'd143)
begin
wide_hsync_on_vsync <= 1'b1;
end
else if(horizontal_counter == 9'd175)
begin
wide_hsync_on_vsync <= 1'b0;
end
else if(horizontal_counter == 9'd335)
begin
wide_hsync_on_vsync <= 1'b1;
end
else if(horizontal_counter == 9'd367)
begin
wide_hsync_on_vsync <= 1'b0;
end
else
begin
wide_hsync_on_vsync <= wide_hsync_on_vsync;
end
//hysnc
if(horizontal_counter == 9'd175)
begin
hsync <= 1'b1;
end
else if(horizontal_counter == 9'd207)
begin
hsync <= 1'b0;
end
else
begin
hsync <= hsync;
end
//narrow hsync on vsync clken
if(horizontal_counter == 9'd366)
begin
narrow_hsync_on_vsync_clken_n <= 1'b0;
end
else
begin
narrow_hsync_on_vsync_clken_n <= 1'b1;
end
//hsync clken
if(horizontal_counter == 9'd174)
begin
hsync_clken_n <= 1'b0;
end
else
begin
hsync_clken_n <= 1'b1;
end
end
end
end
//
// VCLK GENERATOR
//
//VCLK output
always @(*)
begin
if(o_FRAMEPARITY == 1'b0) //EVEN FRAME
begin
if(vertical_counter > 9'd503 || vertical_counter < 9'd266)
begin
o_VCLK <= narrow_hsync_on_vsync & o_HBLANK_n;
end
else
begin
o_VCLK <= hsync;
end
end
else //ODD FRAME
begin
o_VCLK <= hsync;
end
end
//VCLK clken
reg vclk_clken_n;
always @(*)
begin
if(o_FRAMEPARITY == 1'b0) //EVEN FRAME
begin
if(vertical_counter > 9'd502 || vertical_counter < 9'd265) //not 503 and 266!! clken should be asserted before a posedge of VCLK, so it have to go 1V faster
begin
vclk_clken_n <= narrow_hsync_on_vsync_clken_n;
end
else
begin
vclk_clken_n <= hsync_clken_n;
end
end
else //ODD FRAME
begin
vclk_clken_n <= hsync_clken_n;
end
end
//
// VCOUNTER
//
always @(posedge i_EMU_MCLK) //do not use asynchronous VCLK
begin
if(!i_MRST_n) //asynchronous reset
begin
vertical_counter <= 9'd248;
end
else
begin
if(!i_EMU_CLK6MPCEN_n)
begin
if(!vclk_clken_n)
begin
if(vertical_counter < 9'd511)
begin
//VBLANK
if(vertical_counter > 9'd494 || vertical_counter < 9'd271)
begin
o_VBLANK_n <= 1'b0;
end
else
begin
o_VBLANK_n <= 1'b1;
end
//VBLANK**
if(vertical_counter > 9'd494 || vertical_counter < 9'd271)
begin
o_VBLANKH_n <= 1'b0;
end
else
begin
o_VBLANKH_n <= 1'b1; //VBLANK** goes high when vcounter = 248
end
//256V
if(vertical_counter == 9'd495) //flip parity value
begin
o_FRAMEPARITY <= ~o_FRAMEPARITY;
end
//DMA
if(vertical_counter > 9'd478 && vertical_counter < 9'd495)
begin
__REF_DMA_n <= 1'b0;
end
else
begin
__REF_DMA_n <= 1'b1;
end
vertical_counter <= vertical_counter + 9'd1;
end
else
begin
vertical_counter <= 9'd248;
o_VBLANKH_n <= 1'b1;
end
end
end
end
end
///////////////////////////////////////////////////////////
////// SYNC GENERATOR
////
assign o_VSYNC_n = vertical_counter[8];
assign o_CSYNC_n = o_VSYNC_n & ~o_VCLK;
always @(*)
begin
if(vertical_counter > 9'd503 || vertical_counter < 9'd266)
begin
if(vertical_counter > 9'd247 && vertical_counter < 9'd256)
begin
o_CSYNC <= o_VSYNC_n ^ wide_hsync_on_vsync;
end
else
begin
o_CSYNC <= o_VSYNC_n ^ narrow_hsync_on_vsync;
end
end
else
begin
o_CSYNC <= o_VSYNC_n ^ hsync;
end
end
endmodule

202
BubSysROM_core_ModelSim/BubSysROM_component/asic/K005294.v Normal file
View File

@@ -0,0 +1,202 @@
/*
K005294 "LINELATCH"
*/
module K005294
(
input wire i_EMU_MCLK,
input wire i_EMU_CLK6MPCEN_n,
input wire [31:0] i_GFXDATA,
input wire [3:0] i_OC,
input wire i_TILELINELATCH_n,
output reg [7:0] o_DA,
output reg [7:0] o_DB,
//005294 control signals
input wire i_WRTIME2,
input wire i_COLORLATCH_n,
input wire i_XPOS_D0,
input wire i_PIXELLATCH_WAIT_n,
input wire i_LATCH_A_D2,
input wire [2:0] i_PIXELSEL
);
///////////////////////////////////////////////////////////
////// COLORLATCH
////
//latches pixel palette data from VRAM
reg [3:0] OBJ_PALETTE;
always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK6MPCEN_n)
begin
if(!i_COLORLATCH_n)
begin
OBJ_PALETTE <= i_OC;
end
end
end
///////////////////////////////////////////////////////////
////// TILELINE LATCH
////
reg [31:0] OBJ_TILELINELATCH;
always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK6MPCEN_n)
begin
if(!i_TILELINELATCH_n) //posedge of px7
begin
OBJ_TILELINELATCH <= i_GFXDATA;
end
end
end
///////////////////////////////////////////////////////////
////// PIXEL SELECT / PIXELLATCH_WAIT / WRTIME2 DELAY
////
/*
It's probably intended to delay DRAM writing until a
new tile is copied from CHARRAM.
What a Konami style mess!!
005295(internally) -> 005294(internally) total delay
PIXELSEL 0clk dly 4clk dly = 4clk delay
WRTIME2 2clk dly 2clk dly = 4clk delay
PIXELLATCH_WAIT_n 1clk dly 3clk dly = 4clk delay
*/
reg [2:0] pixelsel_dly [3:0];
reg [1:0] wrtime2_dly;
reg [3:0] pixellatch_wait_dly;
always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK6MPCEN_n)
begin
pixelsel_dly[0] <= i_PIXELSEL;
pixelsel_dly[1] <= pixelsel_dly[0];
pixelsel_dly[2] <= pixelsel_dly[1];
pixelsel_dly[3] <= pixelsel_dly[2];
end
end
always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK6MPCEN_n)
begin
wrtime2_dly[0] <= i_WRTIME2;
wrtime2_dly[1] <= wrtime2_dly[0];
end
end
always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK6MPCEN_n)
begin
pixellatch_wait_dly[0] <= ~i_PIXELLATCH_WAIT_n;
pixellatch_wait_dly[1] <= pixellatch_wait_dly[0];
pixellatch_wait_dly[2] <= pixellatch_wait_dly[1];
pixellatch_wait_dly[3] <= pixellatch_wait_dly[2];
end
end
///////////////////////////////////////////////////////////
////// PIXEL SELECTOR AND PIXEL LATCH
////
wire pixellatch_n = wrtime2_dly[1] | pixellatch_wait_dly[2];
reg [3:0] OBJ_PIXEL_LATCHED;
reg [3:0] OBJ_PIXEL_UNLATCHED;
always @(*)
begin
case(pixelsel_dly[3])
3'b000: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[31:28]; //pixel 0(A)
3'b001: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[27:24]; //pixel 1(B)
3'b010: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[23:20];
3'b011: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[19:16];
3'b100: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[15:12];
3'b101: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[11:8];
3'b110: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[7:4];
3'b111: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[3:0];
endcase
end
always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK6MPCEN_n)
begin
if(!pixellatch_n)
begin
OBJ_PIXEL_LATCHED <= OBJ_PIXEL_UNLATCHED;
end
end
end
///////////////////////////////////////////////////////////
////// DOUT MUX
////
always @(*)
begin
case({pixellatch_wait_dly[2], i_XPOS_D0})
2'b00: begin
o_DA <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED};
o_DB <= {OBJ_PALETTE, OBJ_PIXEL_UNLATCHED};
end
2'b01: begin
o_DA <= {OBJ_PALETTE, OBJ_PIXEL_UNLATCHED};
o_DB <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED};
end
2'b10: begin
o_DA <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED};
o_DB <= {4'b0000, 4'b0000};
end
2'b11: begin
o_DA <= {4'b0000, 4'b0000};
o_DB <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED};
end
endcase
end
endmodule

1787
BubSysROM_core_ModelSim/BubSysROM_component/asic/K005295.v Normal file
View File

File diff suppressed because it is too large Load Diff

62
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px3.v → BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM.v
View File

@@ -1,23 +1,34 @@
/*
4416 DRAM
DRAM
*/
module DRAM16k4_charram_px3
module DRAM #( parameter
dw=8, // data width
aw=8, // address bus width (number of pins)
rw=aw, // row width (usually address but width)
cw=aw, // column width (address but width or shorter)
ctop=cw-1, // index in address where MSB of col is
cbot=0, // index in address where LSB of col is
simhexfile="",
init=0
)
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire [aw-1:0] i_ADDR,
input wire [dw-1:0] i_DIN,
output reg [dw-1:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
reg [dw-1:0] RAM [0:(2**(rw+cw))-1];
reg prev_ras;
reg prev_cas;
reg [rw-1:0] ROW_ADDR;
reg [cw-1:0] COL_ADDR;
wire [rw+cw-1:0] ADDR = {COL_ADDR, ROW_ADDR};
/*
MCLK 1 1
@@ -32,21 +43,24 @@ wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
prev_ras <= i_RAS_n;
prev_cas <= i_CAS_n;
if(i_RAS_n == 1'b0 && prev_ras == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
if(i_CAS_n == 1'b0 && prev_cas == 1'b1)
begin
__COL_ADDR <= i_ADDR[6:1];
COL_ADDR <= i_ADDR[ctop:cbot];
end
end
@@ -55,7 +69,7 @@ always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
RAM[ADDR] <= i_DIN;
end
end
@@ -63,13 +77,25 @@ always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
o_DOUT <= RAM[ADDR];
end
end
integer i;
initial
begin
$readmemh("init_charram_px3.txt", RAM16k4);
if( simhexfile != "" )
begin
$readmemh(simhexfile, RAM);
end
else if( init != 0 )
begin
for(i = 0; i < 2**(rw+cw); i = i + 1)
begin
RAM[i] <= {dw{1'b0}};
end
end
end
endmodule
endmodule

70
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4.v
View File

@@ -1,70 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
endmodule

75
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px0.v
View File

@@ -1,75 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4_charram_px0
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
initial
begin
$readmemh("init_charram_px0.txt", RAM16k4);
end
endmodule

75
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px1.v
View File

@@ -1,75 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4_charram_px1
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
initial
begin
$readmemh("init_charram_px1.txt", RAM16k4);
end
endmodule

75
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px2.v
View File

@@ -1,75 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4_charram_px2
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
initial
begin
$readmemh("init_charram_px2.txt", RAM16k4);
end
endmodule

75
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px4.v
View File

@@ -1,75 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4_charram_px4
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
initial
begin
$readmemh("init_charram_px4.txt", RAM16k4);
end
endmodule

75
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px5.v
View File

@@ -1,75 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4_charram_px5
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
initial
begin
$readmemh("init_charram_px5.txt", RAM16k4);
end
endmodule

75
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px6.v
View File

@@ -1,75 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4_charram_px6
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
initial
begin
$readmemh("init_charram_px6.txt", RAM16k4);
end
endmodule

75
BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px7.v
View File

@@ -1,75 +0,0 @@
/*
4416 DRAM
*/
module DRAM16k4_charram_px7
(
input wire i_MCLK,
input wire [7:0] i_ADDR,
input wire [3:0] i_DIN,
output reg [3:0] o_DOUT,
input wire i_RAS_n,
input wire i_CAS_n,
input wire i_WR_n,
input wire i_RD_n
);
reg [3:0] RAM16k4 [16383:0];
reg [7:0] __ROW_ADDR;
reg [5:0] __COL_ADDR;
wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR};
/*
MCLK 1 1
0 1 2 3 4 5 6 7 8 9 0 1
CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|
CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|
CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|
PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----|
/DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
|-----------| = access time = 162.75ns
>row
>column
>launch
>CPU acquisition
CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
/RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________
/CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________
*/
always @(posedge i_MCLK)
begin
if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1)
begin
__ROW_ADDR <= i_ADDR;
end
if(i_CAS_n == 1'b0)
begin
__COL_ADDR <= i_ADDR[6:1];
end
end
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM16k4[__ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM16k4[__ADDR];
end
end
initial
begin
$readmemh("init_charram_px7.txt", RAM16k4);
end
endmodule

44
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM.v Normal file
View File

@@ -0,0 +1,44 @@
/*
SRAM
*/
module SRAM #(parameter
dw=8,
aw=10,
simhexfile=""
)
(
input wire i_MCLK,
input wire [aw-1:0] i_ADDR,
input wire [dw-1:0] i_DIN,
output reg [dw-1:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [dw-1:0] RAM [0:(2**aw)-1];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM[i_ADDR];
end
end
initial
begin
if( simhexfile != "" ) begin
$readmemh(simhexfile, RAM);
end
end
endmodule

33
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8.v
View File

@@ -1,33 +0,0 @@
/*
6116 SRAM
*/
module SRAM2k8
(
input wire i_MCLK,
input wire [10:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM2k8 [2047:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM2k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM2k8[i_ADDR];
end
end
endmodule

38
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_high.v
View File

@@ -1,38 +0,0 @@
/*
6116 SRAM
*/
module SRAM2k8_color_high
(
input wire i_MCLK,
input wire [10:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM2k8 [2047:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM2k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM2k8[i_ADDR];
end
end
initial
begin
$readmemh("init_colorram_high.txt", RAM2k8);
end
endmodule

38
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_low.v
View File

@@ -1,38 +0,0 @@
/*
6116 SRAM
*/
module SRAM2k8_color_low
(
input wire i_MCLK,
input wire [10:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM2k8 [2047:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM2k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM2k8[i_ADDR];
end
end
initial
begin
$readmemh("init_colorram_low.txt", RAM2k8);
end
endmodule

38
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_obj.v
View File

@@ -1,38 +0,0 @@
/*
6116 SRAM
*/
module SRAM2k8_obj
(
input wire i_MCLK,
input wire [10:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM2k8 [2047:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM2k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM2k8[i_ADDR];
end
end
initial
begin
$readmemh("init_objram.txt", RAM2k8);
end
endmodule

38
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_scroll.v
View File

@@ -1,38 +0,0 @@
/*
6116 SRAM
*/
module SRAM2k8_scroll
(
input wire i_MCLK,
input wire [10:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM2k8 [2047:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM2k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM2k8[i_ADDR];
end
end
initial
begin
$readmemh("init_scrollram.txt", RAM2k8);
end
endmodule

33
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8.v
View File

@@ -1,33 +0,0 @@
/*
TC5533P SRAM
*/
module SRAM4k8
(
input wire i_MCLK,
input wire [11:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM4k8 [4095:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM4k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM4k8[i_ADDR];
end
end
endmodule

38
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_high.v
View File

@@ -1,38 +0,0 @@
/*
TC5533P SRAM
*/
module SRAM4k8_vram1_high
(
input wire i_MCLK,
input wire [11:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM4k8 [4095:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM4k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM4k8[i_ADDR];
end
end
initial
begin
$readmemh("init_vram1_high.txt", RAM4k8);
end
endmodule

38
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_low.v
View File

@@ -1,38 +0,0 @@
/*
TC5533P SRAM
*/
module SRAM4k8_vram1_low
(
input wire i_MCLK,
input wire [11:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM4k8 [4095:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM4k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM4k8[i_ADDR];
end
end
initial
begin
$readmemh("init_vram1_low.txt", RAM4k8);
end
endmodule

38
BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram2.v
View File

@@ -1,38 +0,0 @@
/*
TC5533P SRAM
*/
module SRAM4k8_vram2
(
input wire i_MCLK,
input wire [11:0] i_ADDR,
input wire [7:0] i_DIN,
output reg [7:0] o_DOUT,
input wire i_WR_n,
input wire i_RD_n
);
reg [7:0] RAM4k8 [4095:0];
always @(posedge i_MCLK)
begin
if(i_WR_n == 1'b0)
begin
RAM4k8[i_ADDR] <= i_DIN;
end
end
always @(posedge i_MCLK) //read
begin
if(i_RD_n == 1'b0)
begin
o_DOUT <= RAM4k8[i_ADDR];
end
end
initial
begin
$readmemh("init_vram2.txt", RAM4k8);
end
endmodule

5
BubSysROM_core_ModelSim/BubSysROM_screensim.v
View File

@@ -44,7 +44,7 @@ always @(posedge i_EMU_MCLK) begin
end
$display("Start of frame %d", frame); //debug message
frame = frame + 16'd1;
end
else if(i_HCOUNTER == 9'd277) begin
$fseek(fd, BITMAP_LINE_ADDRESS, 0); //set current line address
@@ -57,6 +57,9 @@ always @(posedge i_EMU_MCLK) begin
end
else if(i_VCOUNTER == 9'd495 && i_HCOUNTER == 9'd151) begin
$fclose(fd); //close this frame
$display("Frame %d saved", frame); //debug message
frame = frame + 16'd1;
end
else begin

418
BubSysROM_core_ModelSim/BubSysROM_video/BubSysROM_video.v
View File

@@ -124,51 +124,33 @@ wire HBLANK_n;
wire VBLANK_n;
assign o_VBLANK_n = VBLANK_n;
wire VBLANKH_n;
wire VCLK;
wire CSYNC_n;
wire ABS_256H;
//hcounter
wire ABS_256H,
ABS_128H, ABS_64H, ABS_32H, ABS_16H,
ABS_8H, ABS_4H, ABS_2H, ABS_1H;
wire FLIP_128H, FLIP_64H, FLIP_32H, FLIP_16H,
FLIP_8H, FLIP_4H, FLIP_2H, FLIP_1H;
//vcounter
wire ABS_128V, ABS_64V, ABS_32V, ABS_16V,
ABS_8V, ABS_4V, ABS_2V, ABS_1V;
wire FLIP_128V, FLIP_64V, FLIP_32V, FLIP_16V,
FLIP_8V, FLIP_4V, FLIP_2V, FLIP_1V;
//misc
wire ABS_n256H = ~ABS_256H;
wire ABS_128H;
wire ABS_64H;
wire ABS_32H;
wire ABS_16H;
wire ABS_8H;
wire ABS_4H;
wire ABS_2H;
wire ABS_1H;
wire ABS_n1H = ~ABS_1H;
wire ABS_128HA = (ABS_256H & ABS_128H) | (ABS_n256H & ABS_32H);
wire ABS_128V;
wire ABS_64V;
wire ABS_32V;
wire ABS_16V;
wire ABS_8V;
wire ABS_4V;
wire ABS_2V;
wire ABS_1V;
wire FLIP_n256H = ABS_n256H ^ i_HFLIP;
wire FLIP_128H;
wire FLIP_64H;
wire FLIP_32H;
wire FLIP_16H;
wire FLIP_8H;
wire FLIP_4H;
wire FLIP_2H;
wire FLIP_1H;
wire FLIP_128V;
wire FLIP_64V;
wire FLIP_32V;
wire FLIP_16V;
wire FLIP_8V;
wire FLIP_4V;
wire FLIP_2V;
wire FLIP_1V;
wire DMA_n = ~&{ABS_128V, ABS_64V, ABS_32V, ~ABS_16V}; //16C NAND; vcounter 480-495
wire VCLK;
wire CSYNC_n;
//declare K005292 core: this core does not have LS393 sprite code up counter
K005292 K005292_main
@@ -227,12 +209,39 @@ K005292 K005292_main
.o_FRAMEPARITY ( ), //256V
.o_VSYNC_n (o_VSYNC_n ),
.o_CSYNC_n (CSYNC_n ),
.o_CSYNC (CSYNC_n ),
.__REF_HCOUNTER (__REF_HCOUNTER ),
.__REF_VCOUNTER (__REF_VCOUNTER )
);
//fully asynchronous shit in K005292(modded)
wire ORINC;
reg [7:0] OBJ;
wire objcntr_tick = ORINC | (&{OBJ[7:4]});
always @(posedge i_EMU_MCLK)
begin
if(!o_EMU_CLK6MPCEN_n)
begin
if(ABS_1H == 1'b0) //posedge of 1H
begin
if(DMA_n == 1'b0)
begin
OBJ <= 8'd0;
end
else
begin
if(objcntr_tick == 1'b0)
begin
OBJ <= OBJ + 8'd1;
end
end
end
end
end
//
// CSYNC DFF
@@ -313,7 +322,7 @@ always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK18MNCEN_n)
begin
CHAMPX2 = CHAMPX;
CHAMPX2 <= CHAMPX;
end
end
@@ -323,7 +332,7 @@ end
//
//timing singals
wire OBJRW; //switches mux between active display+buffer clear/005295 write
wire OBJWR; //switches mux between active display+buffer clear/005295 write
wire OBJCLR; //fix mux output as 0 when clearing the buffer by writing 0s
//19H LS74A
@@ -343,9 +352,9 @@ end
reg DFF_19H_B;
always @(posedge i_EMU_MCLK)
begin
if(!o_EMU_CLK6MNCEN_n) //negedge cen
if(!o_EMU_CLK6MPCEN_n) //negedge cen
begin
if(ABS_1H == 1'b0) //every EVEN pixel
if(ABS_1H == 1'b1) //every ODD pixel
begin
DFF_19H_B <= DFF_19H_A;
end
@@ -385,7 +394,7 @@ begin
end
end
assign OBJRW = DFF_19H_B;
assign OBJWR = DFF_19H_B;
assign OBJCLR = ~DFF_19H_B;
assign o_BLK = DFF_17A_A;
@@ -477,7 +486,8 @@ wire scrollram_wr = (i_VZCS_n | i_CPU_RW | i_CPU_LDS_n | TIME2);
//declare SCROLLRAM
wire [7:0] scrollram_dout;
SRAM2k8_scroll SCROLLRAM_LOW
SRAM #(.aw( 11 ), .dw( 8 ), .simhexfile("init_scrollram.txt"))
SCROLLRAM_LOW
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (scrollram_addr ),
@@ -585,7 +595,8 @@ wire vram2l_wr = (i_VCS2_n | i_CPU_RW | i_CPU_LDS_n | ABS_1H | ABS_2H
//declare vram1
wire [15:0] vram1_dout;
SRAM4k8_vram1_high VRAM1_HIGH
SRAM #(.aw( 12 ), .dw( 8 ), .simhexfile("init_vram1_high.txt"))
VRAM1_HIGH
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (vram_addr ),
@@ -595,7 +606,8 @@ SRAM4k8_vram1_high VRAM1_HIGH
.i_RD_n (VRTIME )
);
SRAM4k8_vram1_low VRAM1_LOW
SRAM #(.aw( 12 ), .dw( 8 ), .simhexfile("init_vram1_low.txt"))
VRAM1_LOW
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (vram_addr ),
@@ -607,7 +619,8 @@ SRAM4k8_vram1_low VRAM1_LOW
//declare vram2
wire [7:0] vram2_dout;
SRAM4k8_vram2 VRAM2_LOW
SRAM #(.aw( 12 ), .dw( 8 ), .simhexfile("init_vram2.txt"))
VRAM2_LOW
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (vram_addr ),
@@ -653,28 +666,7 @@ wire [3:0] PR = vram1_dout[15:12];
wire [7:0] VCA;
wire [13:0] __REF_VCA_ORIGINAL = {tile_code, line_addr ^ {3{VVFF}}};
assign VCA = (CHAMPX2 == 1'b0) ?
{ //RAS
tile_code[4],
tile_code[3],
tile_code[2],
tile_code[1],
tile_code[0],
line_addr[2] ^ VVFF,
line_addr[1] ^ VVFF,
line_addr[0] ^ VVFF
} :
{ //CAS
1'b1,
tile_code[10],
tile_code[9],
tile_code[8],
tile_code[7],
tile_code[6],
tile_code[5],
1'b1
};
{tile_code[4:0], line_addr[2:0] ^ {3{VVFF}}} : {1'b1, tile_code[10:5], 1'b1}; //RAS : CAS
@@ -686,7 +678,7 @@ assign VCA = (CHAMPX2 == 1'b0) ?
////
//
// SPRITE NAMETABLE SECTION
// OBJRAM SECTION
//
//make objram address
@@ -700,7 +692,8 @@ wire objram_wr = |{i_OBJRAM_n, i_CPU_RW, i_CPU_LDS_n, TIME2}; //LS32*
//declare OBJRAM
wire [7:0] objram_dout;
SRAM2k8_obj OBJRAM_LOW
SRAM #(.aw( 11 ), .dw( 8 ), .simhexfile("init_objram.txt"))
OBJRAM_LOW
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (objram_addr ),
@@ -725,8 +718,7 @@ LOGIC373 OBJRAM_CPULATCH
// SPRITE DMA SECTION
//
wire dma = ~&{ABS_128V, ABS_64V, ABS_32V, ~ABS_16V}; //16C NAND; vcounter 480-495
//19G LS273
reg [7:0] obj_priority;
always @(posedge i_EMU_MCLK)
begin
@@ -739,22 +731,107 @@ begin
end
end
//17G LS374
reg [7:0] obj_attr;
always @(posedge i_EMU_MCLK)
begin
if(!o_EMU_CLK6MPCEN_n)
begin
if(ABS_1H == 1'b0) //posedge of 1H
if(ABS_1H == 1'b1) //posedge of /px1
begin
obj_attr <= objram_dout;
end
end
end
//make objtable address
wire [2:0] ORA;
wire [10:0] objtable_addr;
assign objtable_addr = (DMA_n == 1'b0) ?
{obj_priority, ABS_8H, ABS_4H, ABS_2H} :
{OBJ, ORA};
//make objtable_wr
wire objtable_wr = ~(ABS_1H & ~DMA_n);
//declare objtable ram
wire [7:0] objtable_dout;
SRAM #(.aw( 11 ), .dw( 8 ))
OBJTABLE
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (objtable_addr ),
.i_DIN (obj_attr ),
.o_DOUT (objtable_dout ),
.i_WR_n (objtable_wr ),
.i_RD_n (1'b0 )
);
//
// asic section
//
wire [7:0] OCA;
wire CHAOV;
reg OBJHL;
wire [7:0] FA, FB;
wire XA7, XB7;
wire OBJBUF_CAS;
wire WRTIME2;
wire COLORLATCH_n;
wire XPOS_D0;
wire PIXELLATCH_WAIT_n;
wire LATCH_A_D2;
wire [2:0] PIXELSEL;
//declare K005295 core
K005295 #(.__ENABLE_DOUBLE_HEIGHT_MODE(1'b0), .__SAVE_FRAMEBUFFER_CAPACITY(1'b1))
K005295_main
(
.i_EMU_MCLK (i_EMU_MCLK ),
.i_EMU_CLK6MPCEN_n (o_EMU_CLK6MPCEN_n ),
.i_DMA_n (DMA_n ),
.i_VBLANKH_n (VBLANKH_n ),
.i_VBLANK_n (VBLANK_n ),
.i_HBLANK_n (HBLANK_n ),
.i_ABS_4H (ABS_4H ),
.i_ABS_2H (ABS_2H ),
.i_ABS_1H (ABS_1H ),
.i_CHAMPX (CHAMPX2 ),
.i_OBJWR (OBJWR ),
.i_FLIP (i_HFLIP ),
.i_OBJDATA (objtable_dout ),
.o_ORA (ORA ),
.o_CAS (OBJBUF_CAS ),
.o_FA (FA ),
.o_FB (FB ),
.o_XA7 (XA7 ),
.o_XB7 (XB7 ),
.i_OBJHL (OBJHL ),
.o_CHAOV (CHAOV ),
.o_ORINC (ORINC ),
.o_WRTIME2 (WRTIME2 ),
.o_COLORLATCH_n (COLORLATCH_n ),
.o_XPOS_D0 (XPOS_D0 ),
.o_PIXELLATCH_WAIT_n (PIXELLATCH_WAIT_n ),
.o_LATCH_A_D2 (LATCH_A_D2 ),
.o_PIXELSEL (PIXELSEL ),
.o_OCA (OCA )
);
@@ -799,31 +876,11 @@ wire [7:0] cpu_addr;
assign cpu_addr = (i_CHACS_n == 1'b1) ?
refresh_addr :
(CHAMPX2 == 1'b0) ?
{ //RAS
i_CPU_ADDR[8], //A9
i_CPU_ADDR[7], //A8
i_CPU_ADDR[6], //A7
i_CPU_ADDR[5], //A6
i_CPU_ADDR[4], //A5
i_CPU_ADDR[3], //A4
i_CPU_ADDR[2], //A3
i_CPU_ADDR[1] //A2
} :
{ //CAS
1'b1, //HIGH
i_CPU_ADDR[14], //A15
i_CPU_ADDR[13], //A14
i_CPU_ADDR[12], //A13
i_CPU_ADDR[11], //A12
i_CPU_ADDR[10], //A11
i_CPU_ADDR[9], //A10
1'b1 //HIGH
};
i_CPU_ADDR[8:1] : {1'b1, i_CPU_ADDR[14:9], 1'b1}; //RAS(A9-A2) : CAS(1, A15-A10, 1)
//LS157*2 11A/B MUX
wire [7:0] gfx_addr;
assign gfx_addr = VCA;
//assign gfx_addr = (CHAOV_n == 1'b0) ? VCA : OCA;
assign gfx_addr = (CHAOV == 1'b0) ? OCA : VCA;
//LS157*2 10A/B MUX
wire [7:0] charram_addr;
@@ -836,7 +893,7 @@ assign charram_addr = (~ABS_2H == 1'b0) ? gfx_addr : cpu_addr;
//RAS/CAS
wire charram_ras_n = ~CHAMPX;
reg charram_cas_n = 1'b1; //54.25ns delayed RAS
reg charram_cas_n = 1'b1; //54.25ns delayed RAS, same as CHAMPX2
always @(posedge i_EMU_MCLK)
begin
if(!i_EMU_CLK18MNCEN_n)
@@ -870,13 +927,15 @@ wire charram2_rd = ~charram2_rw; //disables output when reading
wire charram1u_wr = charramu_en | charram1_rw;
wire charram1l_wr = charraml_en | charram1_rw;
wire charram2u_wr = charramu_en | charram2_rw;
wire charram2l_wr = charramu_en | charram2_rw;
wire charram2l_wr = charraml_en | charram2_rw;
//declare charram
wire [15:0] charram1_dout; //A1=0
wire [15:0] charram2_dout; //A1=1
DRAM16k4_charram_px0 CHARRAM_PX0 //6B
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px0.txt"))
CHARRAM_PX0 //6B
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -887,7 +946,10 @@ DRAM16k4_charram_px0 CHARRAM_PX0 //6B
.i_WR_n (charram1u_wr ),
.i_RD_n (charram1_rd )
);
DRAM16k4_charram_px1 CHARRAM_PX1 //6A
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px1.txt"))
CHARRAM_PX1 //6A
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -898,7 +960,10 @@ DRAM16k4_charram_px1 CHARRAM_PX1 //6A
.i_WR_n (charram1u_wr ),
.i_RD_n (charram1_rd )
);
DRAM16k4_charram_px2 CHARRAM_PX2 //2B
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px2.txt"))
CHARRAM_PX2 //2B
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -909,7 +974,10 @@ DRAM16k4_charram_px2 CHARRAM_PX2 //2B
.i_WR_n (charram1l_wr ),
.i_RD_n (charram1_rd )
);
DRAM16k4_charram_px3 CHARRAM_PX3 //2A
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px3.txt"))
CHARRAM_PX3 //2A
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -920,7 +988,10 @@ DRAM16k4_charram_px3 CHARRAM_PX3 //2A
.i_WR_n (charram1l_wr ),
.i_RD_n (charram1_rd )
);
DRAM16k4_charram_px4 CHARRAM_PX4 //7B
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px4.txt"))
CHARRAM_PX4 //7B
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -931,7 +1002,10 @@ DRAM16k4_charram_px4 CHARRAM_PX4 //7B
.i_WR_n (charram2u_wr ),
.i_RD_n (charram2_rd )
);
DRAM16k4_charram_px5 CHARRAM_PX5 //7A
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px5.txt"))
CHARRAM_PX5 //7A
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -942,7 +1016,10 @@ DRAM16k4_charram_px5 CHARRAM_PX5 //7A
.i_WR_n (charram2u_wr ),
.i_RD_n (charram2_rd )
);
DRAM16k4_charram_px6 CHARRAM_PX6 //4B
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px6.txt"))
CHARRAM_PX6 //4B
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -953,7 +1030,10 @@ DRAM16k4_charram_px6 CHARRAM_PX6 //4B
.i_WR_n (charram2l_wr ),
.i_RD_n (charram2_rd )
);
DRAM16k4_charram_px7 CHARRAM_PX7 //4A
DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ),
.simhexfile("init_charram_px7.txt"))
CHARRAM_PX7 //4A
(
.i_MCLK (i_EMU_MCLK ),
.i_ADDR (charram_addr ),
@@ -1028,6 +1108,128 @@ K005290 K005290_main
///////////////////////////////////////////////////////////
////// K005294
////
wire TILELINELATCH_n = ~(ABS_1H & ABS_2H);
wire [7:0] DA;
wire [7:0] DB;
K005294 K005294_main
(
.i_EMU_MCLK (i_EMU_MCLK ),
.i_EMU_CLK6MPCEN_n (o_EMU_CLK6MPCEN_n ),
.i_GFXDATA ({charram1_dout, charram2_dout}),
.i_OC (objtable_dout[4:1] ),
.i_TILELINELATCH_n (TILELINELATCH_n ),
.o_DA (DA ),
.o_DB (DB ),
.i_WRTIME2 (WRTIME2 ),
.i_COLORLATCH_n (COLORLATCH_n ),
.i_XPOS_D0 (XPOS_D0 ),
.i_PIXELLATCH_WAIT_n (PIXELLATCH_WAIT_n ),
.i_LATCH_A_D2 (LATCH_A_D2 ),
.i_PIXELSEL (PIXELSEL )
);
///////////////////////////////////////////////////////////
////// FRAME BUFFER
////
reg DFF_18H_A;
always @(posedge i_EMU_MCLK)
begin
if(!o_EMU_CLK6MPCEN_n)
begin
DFF_18H_A <= WRTIME2;
end
end
reg DFF_18H_B;
always @(posedge i_EMU_MCLK)
begin
if(!o_EMU_CLK6MNCEN_n) //negative edge of CLK6M
begin
DFF_18H_B <= DFF_18H_A;
end
end
wire wrtime2_buf_ras_n = DFF_18H_A & ~DFF_18H_B; //21H LS08 AND
wire objbuf_ras_n = (OBJWR == 1'b0) ? ~CHAMPX : wrtime2_buf_ras_n; //13H LS157
reg DFF_17H_B;
always @(posedge i_EMU_MCLK)
begin
if(!o_EMU_CLK6MPCEN_n) //positive edge of CLK6M
begin
DFF_17H_B <= DFF_18H_A;
end
end
wire wrtime2_buf_we_n = __REF_CLK6M | ~DFF_17H_B; //14H LS32 OR
wire objbuf_we_n = (OBJWR == 1'b0) ? OBJCLRWE : wrtime2_buf_we_n; //13H LS157
reg objbuf_ras_dly_n;
always @(posedge i_EMU_MCLK)
begin
OBJHL <= ~objbuf_ras_n;
objbuf_ras_dly_n <= objbuf_ras_n;
end
wire evenbuf_overwrite_disable = ~(~XA7 & |{DA[3:0]});
wire [7:0] evenbuf_dout;
wire [7:0] evenbuf_din = (OBJCLR == 1'b1) ? 8'h00 :
(evenbuf_overwrite_disable == 1'b0) ? DA : evenbuf_dout;
wire oddbuf_overwrite_disable = ~(~XB7 & |{DB[3:0]});
wire [7:0] oddbuf_dout;
wire [7:0] oddbuf_din = (OBJCLR == 1'b1) ? 8'h00 :
(oddbuf_overwrite_disable == 1'b0) ? DB : oddbuf_dout;
//EVEN
DRAM #(.dw( 8 ), .aw( 8 ), .init( 1 ))
EVENBUF
(
.i_MCLK (i_EMU_MCLK), .i_ADDR (FA),
.i_DIN (evenbuf_din), .o_DOUT (evenbuf_dout),
.i_RAS_n (objbuf_ras_n), .i_CAS_n (~OBJBUF_CAS), .i_WR_n (objbuf_we_n), .i_RD_n (1'b0)
);
//ODD
DRAM #(.dw( 8 ), .aw( 8 ), .init( 1 ))
ODDBUF
(
.i_MCLK (i_EMU_MCLK), .i_ADDR (FB),
.i_DIN (oddbuf_din), .o_DOUT (oddbuf_dout),
.i_RAS_n (objbuf_ras_n), .i_CAS_n (~OBJBUF_CAS), .i_WR_n (objbuf_we_n), .i_RD_n (1'b0)
);
///////////////////////////////////////////////////////////
////// K005293
@@ -1057,7 +1259,7 @@ K005293 K005293_main
.i_A_PIXEL (A_PIXEL ),
.i_B_PIXEL (B_PIXEL ),
.i_OBJBUF_DATA (16'h0000 ),
.i_OBJBUF_DATA ({oddbuf_dout, evenbuf_dout}),
.i_A_TRN_n (A_TRN_n ),
.i_B_TRN_n (B_TRN_n ),
@@ -1077,8 +1279,6 @@ K005293 K005293_main
///////////////////////////////////////////////////////////
////// DATA OUTPUT MUX
////

173
BubSysROM_core_ModelSim/wave.do
View File

@@ -1,94 +1,91 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /BubSysROM_video_tb/main/i_EMU_MCLK
add wave -noupdate /BubSysROM_video_tb/main/__REF_CLK9M
add wave -noupdate /BubSysROM_video_tb/main/__REF_CLK6M
add wave -noupdate -radix unsigned {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[2]}
add wave -noupdate -radix unsigned {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[1]}
add wave -noupdate /BubSysROM_video_tb/main/K005290_main/ABS_2H_dl
add wave -noupdate -radix unsigned {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[0]}
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VCLK
add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/K005292_main/vertical_counter
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_HBLANK_n
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VBLANK_n
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VBLANKH_n
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_FRAMEPARITY
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VSYNC_n
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_CSYNC_n
add wave -noupdate /BubSysROM_video_tb/main/TIME1
add wave -noupdate /BubSysROM_video_tb/main/TIME2
add wave -noupdate /BubSysROM_video_tb/main/CHAMPX
add wave -noupdate /BubSysROM_video_tb/main/VRTIME
add wave -noupdate /BubSysROM_video_tb/main/OBJCLRWE
add wave -noupdate /BubSysROM_video_tb/main/OBJRW
add wave -noupdate /BubSysROM_video_tb/main/OBJCLR
add wave -noupdate /BubSysROM_video_tb/main/BLK
add wave -noupdate -radix unsigned -childformat {{{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[8]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[7]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[6]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[5]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[4]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[3]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[2]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[1]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[0]} -radix unsigned}} -subitemconfig {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[8]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[7]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[6]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[5]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[4]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[3]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[2]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[1]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[0]} {-height 15 -radix unsigned}} /BubSysROM_video_tb/main/K005292_main/horizontal_counter
add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_video_tb/main/scrollram_addr[10]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[9]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[8]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[7]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[6]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[5]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[4]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[3]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[2]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[1]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_video_tb/main/scrollram_addr[10]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[9]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[8]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[7]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[6]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[5]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[4]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[3]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[2]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[1]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[0]} {-height 15 -radix hexadecimal}} /BubSysROM_video_tb/main/scrollram_addr
add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/scrollram_dout
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005291_main/TMA_HSCROLL_VALUE
add wave -noupdate /BubSysROM_video_tb/main/K005291_main/o_SHIFTA1
add wave -noupdate /BubSysROM_video_tb/main/K005291_main/o_SHIFTA2
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005291_main/TMB_HSCROLL_VALUE
add wave -noupdate /BubSysROM_video_tb/main/K005291_main/o_SHIFTB
add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/K005291_main/TMAB_VSCROLL_VALUE
add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[11]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[10]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[9]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[8]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[7]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[6]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[5]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[4]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[3]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[2]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[1]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[11]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[10]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[9]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[8]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[7]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[6]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[5]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[4]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[3]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[2]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[1]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[0]} {-height 15 -radix hexadecimal}} /BubSysROM_video_tb/main/K005291_main/o_VRAMADDR
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/tile_code
add wave -noupdate /BubSysROM_video_tb/main/VVFF
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005291_main/o_TILELINEADDR
add wave -noupdate -radix decimal /BubSysROM_video_tb/main/__REF_VCA_ORIGINAL
add wave -noupdate /BubSysROM_video_tb/main/CHAMPX2
add wave -noupdate /BubSysROM_video_tb/main/VCA
add wave -noupdate /BubSysROM_video_tb/main/charram_ras_n
add wave -noupdate /BubSysROM_video_tb/main/charram_cas_n
add wave -noupdate -radix decimal /BubSysROM_video_tb/main/CHARRAM_PX0/__ADDR
add wave -noupdate /BubSysROM_video_tb/main/charram1_rd
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/charram1_dout
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/charram2_dout
add wave -noupdate /BubSysROM_video_tb/main/__REF_CLK6M
add wave -noupdate /BubSysROM_video_tb/main/K005290_main/pixel7_n
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_LINELATCH
add wave -noupdate /BubSysROM_video_tb/main/K005290_main/i_A_MODE
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_PIXEL_DELAY1
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_PIXEL_DELAY2
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_PIXEL_DELAY3
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/o_A_PIXEL
add wave -noupdate /BubSysROM_video_tb/main/K005290_main/pixel3_n
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/B_LINELATCH
add wave -noupdate /BubSysROM_video_tb/main/K005290_main/i_B_MODE
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/o_B_PIXEL
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/PR
add wave -noupdate /BubSysROM_video_tb/main/VHFF
add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/VC
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY1
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY2
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY3
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY4
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/B_PROPERTY_DELAY1
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/B_PROPERTY_DELAY2
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/B_PROPERTY_DELAY3
add wave -noupdate /BubSysROM_video_tb/main/K005293_main/a_pr
add wave -noupdate /BubSysROM_video_tb/main/K005293_main/b_pr
add wave -noupdate /BubSysROM_video_tb/main/K005293_main/priority_mode
add wave -noupdate /BubSysROM_video_tb/main/K005293_main/transparency
add wave -noupdate /BubSysROM_video_tb/main/K005293_main/layer
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/i_A_PIXEL
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/i_B_PIXEL
add wave -noupdate /BubSysROM_video_tb/main/K005293_main/a_palette
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/b_palette
add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/o_CD
add wave -noupdate /BubSysROM_video_tb/main/ABS_8H
add wave -noupdate /BubSysROM_video_tb/main/ABS_4H
add wave -noupdate /BubSysROM_video_tb/main/ABS_2H
add wave -noupdate /BubSysROM_video_tb/main/ABS_1H
add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/K005292_main/horizontal_counter
add wave -noupdate -radix unsigned -childformat {{{/BubSysROM_video_tb/main/K005292_main/vertical_counter[8]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[7]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[6]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[5]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[4]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[3]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[2]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[1]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[0]} -radix unsigned}} -expand -subitemconfig {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[8]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[7]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[6]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[5]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[4]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[3]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[2]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[1]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[0]} {-height 15 -radix unsigned}} /BubSysROM_video_tb/main/K005292_main/vertical_counter
add wave -noupdate /BubSysROM_video_tb/main/dma
add wave -noupdate /BubSysROM_video_tb/main/K005292_main/__REF_DMA_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_HBLANK_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_VBLANK_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_VBLANKH_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_ABS_4H
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_ABS_2H
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_ABS_1H
add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJCLR
add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJWR
add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJCLRWE
add wave -noupdate /BubSysROM_top_tb/main/video_main/CHAMPX
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/buffer_frame_parity
add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/OBJ
add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/ORA
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/objtable_addr
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/objtable_dout
add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M
add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/sprite_engine_state
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/drawing_status
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hzoom_acc
add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005295_main/xpos_cnt_dly_n[1]}
add wave -noupdate -color {Blue Violet} -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/TILELINE_ADDR
add wave -noupdate -color {Blue Violet} -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/HLINE_ADDR
add wave -noupdate -color Cyan -radix unsigned -childformat {{{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[7]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[6]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[5]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[4]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[3]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[2]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[1]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[0]} -radix unsigned}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[7]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[6]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[5]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[4]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[3]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[2]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[1]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[0]} {-color Cyan -height 15 -radix unsigned}} /BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter
add wave -noupdate -color Cyan -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/oddbuffer_xpos_counter
add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005295_main/ypos_cnt_dly_n[3]}
add wave -noupdate -color {Blue Violet} -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/VTILE_ADDR
add wave -noupdate -color Cyan -radix unsigned -childformat {{{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[7]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[6]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[5]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[4]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[3]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[2]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[1]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[0]} -radix unsigned}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[7]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[6]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[5]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[4]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[3]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[2]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[1]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[0]} {-color Cyan -height 15 -radix unsigned}} /BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/x_out_of_screen
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/y_out_of_screen
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hsize_parity
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/oddsize_wrtime0
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/evensize_wrtime0
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/o_PIXELLATCH_WAIT_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/CHAOV
add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[13]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[12]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[11]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[10]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[9]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[8]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[7]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[6]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[5]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[4]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[3]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[2]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[1]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[13]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[12]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[11]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[10]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[9]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[8]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[7]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[6]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[5]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[4]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[3]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[2]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[1]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[0]} {-height 15 -radix hexadecimal}} /BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR
add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[13]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[12]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[11]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[10]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[9]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[8]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[7]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[6]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[5]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[4]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[3]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[2]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[1]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[13]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[12]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[11]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[10]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[9]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[8]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[7]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[6]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[5]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[4]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[3]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[2]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[1]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[0]} {-height 15 -radix hexadecimal}} /BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR
add wave -noupdate /BubSysROM_top_tb/main/video_main/CHARRAM_PX3/i_RAS_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/CHARRAM_PX3/i_CAS_n
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/i_GFXDATA
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/i_TILELINELATCH_n
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_TILELINELATCH
add wave -noupdate /BubSysROM_top_tb/main/video_main/COLORLATCH_n
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_PALETTE
add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hsize_parity
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/pixellatch_wait_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/PIXELLATCH_WAIT_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/WRTIME2
add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005294_main/wrtime2_dly[1]}
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hzoom_acc
add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/PIXELSEL
add wave -noupdate -radix unsigned {/BubSysROM_top_tb/main/video_main/K005294_main/pixelsel_dly[3]}
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005294_main/pixellatch_n
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_PIXEL_LATCHED
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_PIXEL_UNLATCHED
add wave -noupdate -color Coral -radix unsigned /BubSysROM_top_tb/main/video_main/XPOS_D0
add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/buffer_x_screencounter
add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/buffer_y_screencounter
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005295_main/EVENBUFFER_ADDR
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005295_main/ODDBUFFER_ADDR
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/EVENBUF/ADDR
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/ODDBUF/ADDR
add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005294_main/pixellatch_wait_dly[2]}
add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005294_main/pixellatch_wait_dly[3]}
add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_EMU_MCLK
add wave -noupdate -color Magenta -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/o_DA
add wave -noupdate -color Magenta -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/o_DB
add wave -noupdate /BubSysROM_top_tb/main/video_main/objbuf_ras_n
add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJBUF_CAS
add wave -noupdate /BubSysROM_top_tb/main/video_main/objbuf_we_n
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/evenbuffer_din
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/oddbuffer_din
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/evenbuffer_dout
add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/oddbuffer_dout
add wave -noupdate /BubSysROM_top_tb/main/video_main/evenbuffer_overwrite_disable
add wave -noupdate /BubSysROM_top_tb/main/video_main/oddbuffer_overwrite_disable
add wave -noupdate /BubSysROM_top_tb/main/video_main/i_EMU_MCLK
add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M
add wave -noupdate /BubSysROM_top_tb/main/video_main/ABS_1H
add wave -noupdate /BubSysROM_top_tb/main/video_main/o_BLK
add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJWR
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {5273950 ns} 0}
WaveRestoreCursors {{Cursor 1} {6539470 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 179
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
@@ -102,4 +99,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1025200 ns} {6261840 ns}
WaveRestoreZoom {29998270 ns} {30000100 ns}

4
README.md
View File

@@ -1,2 +1,2 @@
# MiSTer_BubSysROM_core
Bubble System ROM core for MiSTer FPGA
# ikacore_BubSysROM
Bubble System revised ROM version core for MiSTer FPGA

0
GX400_datasplitter/GX400_datasplitter.cpp → resources/GX400_datasplitter/GX400_datasplitter.cpp
View File

0
GX400_datasplitter/GX400_datasplitter.exe → resources/GX400_datasplitter/GX400_datasplitter.exe
View File

BIN
resources/waveform_captures.zip Normal file
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Binary file not shown.